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Build(deps): Bump yosys from 8b2a001 to 4fff228 #4482

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Build(deps): Bump yosys from 8b2a001 to 4fff228

Build(deps): Bump yosys from 8b2a001 to 4fff228 #4482

Triggered via pull request July 18, 2023 07:38
@dependabotdependabot[bot]
opened #1835
dependabot/submodules/yosys-4fff228
Status Failure
Total duration 3h 22m 10s
Artifacts 18

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 28s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 2s
Style check
Parsing Tests  /  SystemVerilog Plugin
30m 38s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
8m 46s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (Symbiflow synthesis)
10m 48s
Large Designs Tests / Ibex (Symbiflow synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
1h 57m
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  Swerv (synthesis)
6m 16s
Large Designs Tests / Swerv (synthesis)
Large Designs Tests  /  Black Parrot (synthesis)
29m 22s
Large Designs Tests / Black Parrot (synthesis)
Parsing Tests  /  Surelog
19m 44s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 23s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
4m 37s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 16s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 11s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

1 error and 2 warnings
Large Designs Tests / Ibex (Vivado synthesis)
Process completed with exit code 2.
Large Designs Tests / Swerv (synthesis)
No files were found with the provided path: UHDM-integration-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/synth-vivado/chipsalliance.org_cores_SweRV_EH1_1.8.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime
Name Size
binaries Expired
235 MB
binaries-asan Expired
1.14 GB
bp_e_bp_unicore_cfg.edif Expired
59 MB
bsg-logs Expired
95 MB
bsg-outputs Expired
11.5 MB
formal-verification-logs Expired
912 MB
formal-verification-tests-list Expired
59 KB
lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif Expired
326 MB
opentitan-logs-full Expired
195 MB
opentitan-logs-quick Expired
68 MB
parsing_read-systemverilog_logs Expired
25.8 MB
parsing_read-systemverilog_yosys-sv Expired
379 KB
parsing_read-uhdm_logs Expired
68 KB
parsing_read-uhdm_yosys-sv Expired
374 KB
parsing_test-results Expired
15.4 KB
plots Expired
32.5 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB