mglb/BumpSurelog; plugins: kr/adapt_surelog #4470

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Manually triggered July 5, 2023 18:20

mglb

mglb/BumpSurelog

Status Failure

Total duration 1h 33m 1s

Artifacts 18

main.yml

on: workflow_dispatch

Matrix: build-binaries

Emit Workflow Info

Parsing Tests / SystemVerilog Plugin

Matrix: Large Designs Tests / opentitan_parse_report

Large Designs Tests / Ibex (Vivado synthesis)

Large Designs Tests / Ibex (Symbiflow synthesis)

Large Designs Tests / Opentitan 9d82960888 (synthesis)

Large Designs Tests / Opentitan (synthesis)

Large Designs Tests / Swerv (synthesis)

Large Designs Tests / Black Parrot (synthesis)

Parsing Tests / Surelog

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Matrix: Formal Verification Tests / tests-formal-verification

Parsing Tests / Generate AST diff

Parsing Tests / Summary Generation

Formal Verification Tests / Passlist Check

Release Package

Release Package Installation Test

Annotations

8 errors and 3 warnings

Large Designs Tests / Opentitan (synthesis)

Process completed with exit code 2.

Formal Verification Tests / UHDM-integration-tests

Process completed with exit code 3.

Formal Verification Tests / yosys

Process completed with exit code 3.

Formal Verification Tests / sv2v

Process completed with exit code 3.

Parsing Tests / Surelog

Process completed with exit code 1.

Parsing Tests / SystemVerilog Plugin

Process completed with exit code 1.

Large Designs Tests / Opentitan parsing (quick)

Process completed with exit code 2.

Large Designs Tests / Opentitan parsing (full/top-down)

Process completed with exit code 2.

Large Designs Tests / Opentitan (synthesis)

No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.

Large Designs Tests / Swerv (synthesis)

No files were found with the provided path: UHDM-integration-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/synth-vivado/chipsalliance.org_cores_SweRV_EH1_1.8.edif. No artifacts will be uploaded.

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime

Name	Size
binaries Expired	245 MB
binaries-asan Expired	1.23 GB
bp_e_bp_unicore_cfg.edif Expired	47.3 MB
bsg-logs Expired	95 MB
bsg-outputs Expired	11.6 MB
formal-verification-logs Expired	676 MB
formal-verification-tests-list Expired	59 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired	2.09 MB
opentitan-logs-full Expired	251 MB
opentitan-logs-quick Expired	94.5 MB
parsing_read-systemverilog_logs Expired	28.9 MB
parsing_read-systemverilog_yosys-sv Expired	375 KB
parsing_read-uhdm_logs Expired	67.5 KB
parsing_read-uhdm_yosys-sv Expired	371 KB
parsing_test-results Expired	15.4 KB
plots Expired	17.7 MB
sv2v Expired	8.3 MB
top_artya7.bit Expired	2.09 MB