mglb/BumpSurelog; plugins: kr/adapt_surelog #4468
main.yml
on: workflow_dispatch
Matrix: build-binaries
Build sv2v
1m 51s
Emit Workflow Info
1m 10s
Style check
1m 4s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 11s
Large Designs Tests
/
Ibex (Symbiflow synthesis)
10m 50s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests
/
Opentitan (synthesis)
4m 29s
Large Designs Tests
/
Swerv (synthesis)
6m 28s
Large Designs Tests
/
Black Parrot (synthesis)
27m 14s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
9m 29s
Matrix: Formal Verification Tests / tests-formal-verification
Release Package Installation Test
0s
Annotations
8 errors and 3 warnings
Large Designs Tests / Opentitan (synthesis)
Process completed with exit code 2.
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Formal Verification Tests / UHDM-integration-tests
Process completed with exit code 3.
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Formal Verification Tests / sv2v
Process completed with exit code 3.
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Formal Verification Tests / yosys
Process completed with exit code 3.
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Parsing Tests / Surelog
Process completed with exit code 1.
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Parsing Tests / SystemVerilog Plugin
Process completed with exit code 1.
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Large Designs Tests / Opentitan parsing (quick)
Process completed with exit code 2.
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Large Designs Tests / Opentitan parsing (full/top-down)
Process completed with exit code 2.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.
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Large Designs Tests / Swerv (synthesis)
No files were found with the provided path: UHDM-integration-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/synth-vivado/chipsalliance.org_cores_SweRV_EH1_1.8.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Artifacts
Produced during runtime
Name | Size | |
---|---|---|
binaries
Expired
|
245 MB |
|
binaries-asan
Expired
|
1.23 GB |
|
bp_e_bp_unicore_cfg.edif
Expired
|
47.3 MB |
|
bsg-logs
Expired
|
95 MB |
|
bsg-outputs
Expired
|
11.6 MB |
|
formal-verification-logs
Expired
|
681 MB |
|
formal-verification-tests-list
Expired
|
59 KB |
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
Expired
|
2.09 MB |
|
opentitan-logs-full
Expired
|
264 MB |
|
opentitan-logs-quick
Expired
|
113 MB |
|
parsing_read-systemverilog_logs
Expired
|
28.9 MB |
|
parsing_read-systemverilog_yosys-sv
Expired
|
375 KB |
|
parsing_read-uhdm_logs
Expired
|
67.3 KB |
|
parsing_read-uhdm_yosys-sv
Expired
|
371 KB |
|
parsing_test-results
Expired
|
15.4 KB |
|
plots
Expired
|
16.2 MB |
|
sv2v
Expired
|
8.3 MB |
|
top_artya7.bit
Expired
|
2.09 MB |
|