Build(deps): Bump third_party/sby from `d9a5845` to `62d1708` #5947

Job	Run time
Build tools	10m 25s
Style check	1m 28s
Emit Workflow Info	0s
Build Synlig Release	7m 43s
Verify README Correctness (Installation From Sources)	41m 45s
Build Plugin	4m 13s
Build Synlig (ASAN)	9m 52s
Build Package	7m 42s
Build PySynlig	25m 0s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 18s
Parsing Tests / Test read_systemverilog release	4m 20s
Formal Verification Tests / simple	15m 54s
Parsing Tests / Test read_uhdm release	4m 6s
Parsing Tests / Test read_systemverilog plugin	4m 37s
Formal Verification Tests / sv2v	15m 40s
Parsing Tests / Test read_uhdm plugin	4m 2s
Formal Verification Tests / yosys	14m 37s
Parsing Tests / Test read_systemverilog asan	34m 42s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 55s
Parsing Tests / Test read_uhdm asan	25m 6s
Large Designs Tests / Ibex (Vivado synthesis)	6m 13s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	26m 3s
Large Designs Tests / Opentitan (synthesis)	1h 5m 17s
Large Designs Tests / Black Parrot (ASIC synthesis)	37m 13s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	15m 26s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 12s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 56s
Large Designs Tests / Opentitan parsing (quick)	5m 52s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	33m 7s
Parsing Tests / Summary Generation	1m 37s
Parsing Tests / Generate AST diff	1m 56s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 39m 17s

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