Allow to build Synlig as Python module #5935

Job	Run time
Build Synlig Release	4m 38s
Build Plugin	4m 12s
Build Synlig (ASAN)	8m 59s
Build Package	4m 47s
Build PySynlig	18m 12s
Build tools	11m 9s
Emit Workflow Info	0s
Style check	1m 29s
Verify README Correctness (Installation From Sources)	42m 39s
Large Designs Tests / Black Parrot (ASIC synthesis)	48m 2s
Formal Verification Tests / simple	15m 11s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	12m 52s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 32s
Formal Verification Tests / sv2v	14m 14s
Formal Verification Tests / yosys	14m 3s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	26m 51s
Large Designs Tests / Ibex (Vivado synthesis)	6m 14s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 55s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	35m 50s
Large Designs Tests / Opentitan parsing (full/top-down)	16m 42s
Large Designs Tests / Opentitan parsing (quick)	7m 1s
Large Designs Tests / Opentitan (synthesis)	1h 6m 1s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 10s
Parsing Tests / Test read_systemverilog release	4m 20s
Parsing Tests / Test read_uhdm release	4m 5s
Parsing Tests / Test read_systemverilog plugin	4m 26s
Parsing Tests / Test read_uhdm plugin	4m 17s
Parsing Tests / Test read_systemverilog asan	34m 55s
Parsing Tests / Test read_uhdm asan	25m 9s
Parsing Tests / Summary Generation	1m 41s
Parsing Tests / Generate AST diff	1m 56s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 42m 32s

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