Build(deps): Bump third_party/surelog from `4d8ef9e` to `6b6c364` #5933

Job	Run time
Style check	1m 27s
Build Synlig Release	5m 13s
Build Plugin	4m 45s
Build Synlig (ASAN)	9m 32s
Build Package	5m 32s
Build tools	10m 33s
Emit Workflow Info	0s
Verify README Correctness (Installation From Sources)	41m 11s
Large Designs Tests / Black Parrot (ASIC synthesis)	46m 23s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 18s
Large Designs Tests / Ibex (Vivado synthesis)	6m 15s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 50s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 52s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 13s
Large Designs Tests / Opentitan parsing (full/top-down)	15m 35s
Large Designs Tests / Opentitan (synthesis)	1h 0m 32s
Large Designs Tests / Opentitan parsing (quick)	5m 57s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 10s
Parsing Tests / Test read_systemverilog release	4m 28s
Parsing Tests / Test read_uhdm release	4m 11s
Parsing Tests / Test read_systemverilog plugin	4m 31s
Parsing Tests / Test read_uhdm plugin	4m 11s
Parsing Tests / Test read_systemverilog asan	34m 56s
Parsing Tests / Test read_uhdm asan	24m 50s
Formal Verification Tests / simple	17m 36s
Formal Verification Tests / sv2v	17m 5s
Formal Verification Tests / yosys	14m 16s
Parsing Tests / Summary Generation	1m 13s
Parsing Tests / Generate AST diff	1m 39s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	6h 54m 14s

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