Design Under test: RCC Unit used in DTMF Receiver

UVM testbench with DPI integration, Assertions and Functional Coverage

In this project a complete verification testbench architecture for a result character conversion chip is constructed.

The testcase used for verification are the randomly generated input transactions for the DUT.
Further the functional verification is performed by comparing the output of the DUT with that of reference model.
To implement the reference model direct programming interface (DPI) functionality of SystemVerilog is used.
The reference model is the software implementation of the DUT written using the C-programming language.

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
README.md		README.md
_config.yml		_config.yml
rcc_agent.sv		rcc_agent.sv
rcc_assertions.sv		rcc_assertions.sv
rcc_config.sv		rcc_config.sv
rcc_driver.sv		rcc_driver.sv
rcc_environment.sv		rcc_environment.sv
rcc_if.sv		rcc_if.sv
rcc_in_coverage.sv		rcc_in_coverage.sv
rcc_monitor.sv		rcc_monitor.sv
rcc_out_coverage.sv		rcc_out_coverage.sv
rcc_pkg.sv		rcc_pkg.sv
rcc_scoreboard.sv		rcc_scoreboard.sv
rcc_sequencer.sv		rcc_sequencer.sv
rcc_tb_top.sv		rcc_tb_top.sv
rcc_test.sv		rcc_test.sv
ref_pred.sv		ref_pred.sv
reference_model.c		reference_model.c
results_conv.v		results_conv.v
results_conv_test.sv		results_conv_test.sv
results_conv_test.v		results_conv_test.v
timescale.v		timescale.v
wall_time.c		wall_time.c