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2.0.B: minor updates
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@acaldero
acaldero committed Sep 20, 2019
1 parent 8096864 commit a72f86a
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Showing 4 changed files with 272 additions and 28 deletions.
10 changes: 5 additions & 5 deletions examples/assembly/asm-ep_s7_e1.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -5,14 +5,14 @@

.text
main:
#addi sp,sp,-32
addi sp,sp,-32
#sd s0,24(sp)
#addi s0,sp,32
addi s0,sp,32
#li a5,10
#sw a5,-20(s0)
sw a5,-20(s0)
#li a5,0
#mv a0,a5
mv a0,a5
#ld s0,24(sp)
#addi sp,sp,32
addi sp,sp,32
#jr ra

140 changes: 131 additions & 9 deletions examples/microcode/mc-ep_rv32.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -383,10 +383,44 @@ bgeu rs1 rs2 offset {
}

# LB rd,offset(rs1) Load Byte rd ← s8[rs1 + offset]
# TODO
lb rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LH rd,offset(rs1) Load Half rd ← s16[rs1 + offset]
# TODO
lh rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LW rd,offset(rs1) Load Word rd ← s32[rs1 + offset]
lw rd offset(rs1) {
Expand All @@ -411,16 +445,84 @@ lw rd offset(rs1) {
}

# LBU rd,offset(rs1) Load Byte Unsigned rd ← u8[rs1 + offset]
# TODO
lbu rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LHU rd,offset(rs1) Load Half Unsigned rd ← u16[rs1 + offset]
# TODO
lhu rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SB rs2,offset(rs1) Store Byte u8[rs1 + offset] ← rs2
# TODO
sb rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SH rs2,offset(rs1) Store Half u16[rs1 + offset] ← rs2
# TODO
sh rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SW rs2,offset(rs1) Store Word u32[rs1 + offset] ← rs2
sw reg1 val(reg2) {
Expand Down Expand Up @@ -538,7 +640,7 @@ ori rd rs1 inm {
}

# ANDI rd,rs1,imm And Immediate rd ← ux(rs1) ∧ ux(imm)
addi rd rs1 inm {
andi rd rs1 inm {
co=111111,
nwords=1,
rd=reg(25,21),
Expand Down Expand Up @@ -824,10 +926,30 @@ and reg1 reg2 reg3 {
}

# FENCE pred,succ Fence
# TODO
fence pred succ {
co=111111,
nwords=1,
pred=inm(25,21),
succ=inm(15,0),
native,
{
// TODO

simcore_native_go_maddr(0) ;
}
}

# FENCE.I Fence Instruction
# TODO
fence.i {
co=111111,
nwords=1,
native,
{
// TODO

simcore_native_go_maddr(0) ;
}
}


#
Expand Down
10 changes: 5 additions & 5 deletions ws_dist/examples/assembly/asm-ep_s7_e1.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,14 +5,14 @@

.text
main:
#addi sp,sp,-32
addi sp,sp,-32
#sd s0,24(sp)
#addi s0,sp,32
addi s0,sp,32
#li a5,10
#sw a5,-20(s0)
sw a5,-20(s0)
#li a5,0
#mv a0,a5
mv a0,a5
#ld s0,24(sp)
#addi sp,sp,32
addi sp,sp,32
#jr ra

140 changes: 131 additions & 9 deletions ws_dist/examples/microcode/mc-ep_rv32.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -383,10 +383,44 @@ bgeu rs1 rs2 offset {
}

# LB rd,offset(rs1) Load Byte rd ← s8[rs1 + offset]
# TODO
lb rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LH rd,offset(rs1) Load Half rd ← s16[rs1 + offset]
# TODO
lh rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LW rd,offset(rs1) Load Word rd ← s32[rs1 + offset]
lw rd offset(rs1) {
Expand All @@ -411,16 +445,84 @@ lw rd offset(rs1) {
}

# LBU rd,offset(rs1) Load Byte Unsigned rd ← u8[rs1 + offset]
# TODO
lbu rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# LHU rd,offset(rs1) Load Half Unsigned rd ← u16[rs1 + offset]
# TODO
lhu rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SB rs2,offset(rs1) Store Byte u8[rs1 + offset] ← rs2
# TODO
sb rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SH rs2,offset(rs1) Store Half u16[rs1 + offset] ← rs2
# TODO
sh rd offset(rs1) {
co=111111,
nwords=1,
rd=reg(25,21),
offset=inm(15,0),
rs1=reg(20,16),
native,
{
// fields is a default parameter with the instruction field information
var rd = simcore_native_get_field_from_ir(fields, 0) ;
var offset = simcore_native_get_field_from_ir(fields, 1) ;
var rs1 = simcore_native_get_field_from_ir(fields, 2) ;

// TODO

simcore_native_go_maddr(0) ;
}
}

# SW rs2,offset(rs1) Store Word u32[rs1 + offset] ← rs2
sw reg1 val(reg2) {
Expand Down Expand Up @@ -538,7 +640,7 @@ ori rd rs1 inm {
}

# ANDI rd,rs1,imm And Immediate rd ← ux(rs1) ∧ ux(imm)
addi rd rs1 inm {
andi rd rs1 inm {
co=111111,
nwords=1,
rd=reg(25,21),
Expand Down Expand Up @@ -824,10 +926,30 @@ and reg1 reg2 reg3 {
}

# FENCE pred,succ Fence
# TODO
fence pred succ {
co=111111,
nwords=1,
pred=inm(25,21),
succ=inm(15,0),
native,
{
// TODO

simcore_native_go_maddr(0) ;
}
}

# FENCE.I Fence Instruction
# TODO
fence.i {
co=111111,
nwords=1,
native,
{
// TODO

simcore_native_go_maddr(0) ;
}
}


#
Expand Down

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