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Add support for QuickLogic devices #89
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Commits on Oct 12, 2020
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Initial synth_quicklogic implementation
Fixed syntax error and set the WIDTH of signed_mult to 32 for default. (Maciej Kurc<[email protected]>) QL: cells_sim: fix port definitions for buffers (Karol Gugala<[email protected]>) QL: cells_map: map Valid_mult for mult16x16 (Karol Gugala<[email protected]>) QL: cells_sim: update simulation models (Karol Gugala<[email protected]>) QL: cells_sim: fix dff in logic_cell_macro (Karol Gugala<[email protected]>) QL: cells_sim: remove commented out code (Karol Gugala<[email protected]>) QL: use (* iopad_external_pin *) (Karol Gugala<[email protected]>) QL: synth: do not check for empty top_opt (Karol Gugala<[email protected]>) QL: replace YS_OVERRIDE -> override (Karol Gugala<[email protected]>) Fixed incorrect techmap for mux4x0 (Maciej Kurc<[email protected]>) QuickLogic: flatten designs by default (Karol Gugala<[email protected]>) QuickLogic: add autoname (Karol Gugala<[email protected]>) QuickLogic: add CODEOWNERS entry (Karol Gugala<[email protected]>) QuickLogic: refactor synth_quicklogic (Karol Gugala<[email protected]>) QuickLogic: Add MUX4 and MUX8 mappings (Karol Gugala<[email protected]>) QL: Updated the flow of synth_quicklogic (Maciej Kurc<[email protected]>) QL: Added more test cases (Maciej Kurc<[email protected]>) Fixed a typo (Maciej Kurc<[email protected]>) Added labels to the synth_quicklogic flow (Maciej Kurc<[email protected]>) Fixed an undeclared signal bug and FF models in quicklogic/cells_sim.v (Maciej Kurc<[email protected]>) quicklogic: add gpio_cell_macro sim model (Karol Gugala<[email protected]>) Updated flip-flop implementations (Grzegorz Latosinski<[email protected]>) Changed the Quicklogic synth flow to use clkbufmap. Updated cells_sim.v and tests. (Maciej Kurc<[email protected]>) Removed techmaps for gate-level builtin cells. (Maciej Kurc<[email protected]>) Added tests for synth_quicklogic. (Maciej Kurc<[email protected]>) QL: add gpio_macro_cell definition (Karol Gugala<[email protected]>) Fixed logic_cell_macro model in cells_sim.v (Maciej Kurc<[email protected]>) quicklogic: Added command for assigning undriven ports (Grzegorz Latosinski<[email protected]>) quicklogic: Removed synthesis comments (Grzegorz Latosinski<[email protected]>) quicklogic: Added implementation of the logic cell (Grzegorz Latosinski<[email protected]>) quicklogic: Used help_mode to alter the run calls (Grzegorz Latosinski<[email protected]>) quicklogic: Moved peepopt before techmap (Grzegorz Latosinski<[email protected]>) quicklogic: Removed excessive proc calls (Grzegorz Latosinski<[email protected]>) quicklogic: Removed -exe flag (Grzegorz Latosinski<[email protected]>) quicklogic: Added qlal4s3_mult_cell_macro (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed indents for qlal4s3b_cell_macro (Grzegorz Latosinski<[email protected]>) quicklogic: Added logic_cell_macro (Grzegorz Latosinski<[email protected]>) quicklogic: fix segfault in help synth_quicklogic (Karol Gugala<[email protected]>) quicklogic: remove redundant bipad module (Karol Gugala<[email protected]>) quicklogic: Added support for bipad (Grzegorz Latosinski<[email protected]>) quicklogic: Added support for latches (Grzegorz Latosinski<[email protected]>) quicklogic: Added dffsc module (Grzegorz Latosinski<[email protected]>) quicklogic: Add IO pads only to the top module IO ports (Grzegorz Latosinski<[email protected]>) quicklogic: Improved cleaning routines (Grzegorz Latosinski<[email protected]>) quicklogic: Added mapping from 32x32 multiplier to 16x16 multiplier (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed '-top' flag handling for synth_quicklogic (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed call to hierarchy check (Grzegorz Latosinski<[email protected]>) quicklogic: Added keep directive for Quicklogic CPU blackbox (Grzegorz Latosinski<[email protected]>) quicklogic: Renamed multiply blocks to convention accepted by SpDE (Grzegorz Latosinski<[email protected]>) quicklogic: Updated cells_sim.v and cells_map.v (Maciej Kurc<[email protected]>) quicklogic: Corrected simulation models of LUTs for Quicklogic. (Maciej Kurc<[email protected]>) quicklogic: Added mapping of VCC and GND in design to logic_1 and logic_0 (Grzegorz Latosinski<[email protected]>) quicklogic: Introduced VCC (logic_1) and GND (logic_0) blocks (Grzegorz Latosinski<[email protected]>) quicklogic: added minor blocks (Grzegorz Latosinski<[email protected]>) quicklogic: added multiplier blocks (Grzegorz Latosinski<[email protected]>) quicklogic: added RAM block (Grzegorz Latosinski<[email protected]>) quicklogic: Added black boxes for hard CPU and gclkbuff (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed mapping for QuickLogic LUTs (Grzegorz Latosinski<[email protected]>) quicklogic: Specialized all inpads assigned to asynchronous inputs to ckpads. (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed the output name for ckpad. (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed missing registered FF outputs. (Maciej Kurc<[email protected]>) quicklogic: Added splitting the ports (SpDE support) (Grzegorz Latosinski<[email protected]>) quicklogic: Added support for IO pads and CLK pads (Grzegorz Latosinski<[email protected]>) quicklogic: Added address inversion for QuickLogic LUTs (Grzegorz Latosinski<[email protected]>) quicklogic: Removed VCC/GND entries (Grzegorz Latosinski<[email protected]>) quicklogic: Added IO pads to the QuickLogic script (Grzegorz Latosinski<[email protected]>) quicklogic: Fixed cells mapping for inverted signals (Grzegorz Latosinski<[email protected]>) quicklogic: Updated the library of available cells for QuickLogic (Grzegorz Latosinski<[email protected]>) quicklogic: synth_quicklogic: Added loading cells library for QuickLogic (Grzegorz Latosinski<[email protected]>) quicklogic: Created an initial script for MUX-based FPGAs (Grzegorz Latosinski<[email protected]>) Signed-off-by: Grzegorz Latosinski <[email protected]> Signed-off-by: Maciej Kurc <[email protected]> Signed-off-by: Karol Gugala <[email protected]> Co-authored-by: Grzegorz Latosinski <[email protected]> Co-authored-by: Maciej Kurc <[email protected]> Co-authored-by: Karol Gugala <[email protected]>
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added ram, fifo and multiplier macros
Makefile.inc - added Mult, RAM and FIFO Macro details cells_sim.v - removed inpadff, outpadff, bipadiff, bipadoff and bipadioff definitions Signed-off-by: Rakesh Moolacheri <[email protected]>
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Adding -family option in synth_quicklogic option
Signed-off-by: Lalit Sharma <[email protected]>
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Updating cells map & sim files for pp3
Signed-off-by: Lalit Sharma <[email protected]>
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Updating ap3 device support in yosys
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QL: AP: tweak LUT costs to prefer bigger LUTs (Karol Gugala<[email protected]>) QL: techmaps: split LUT techmaps for PP3 and AP3 (Karol Gugala<[email protected]>) QL: AP3: set lut costs so LU4 is preferred one (Karol Gugala<[email protected]>) QL: AP3: fix sim and map Verilogs (Karol Gugala<[email protected]>) Signed-off-by: Karol Gugala <[email protected]>
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Updating LUT1,2,3 cell mapping to LUT4
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Adding io_reg related primitives
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Added techmaps for DFFE, split LUT and FF techmaps into separate files.
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Updated the synth_quicklogic pass.
Signed-off-by: Maciej Kurc <[email protected]>
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Signed-off-by: Lalit Sharma <[email protected]>
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Adder implementation where adder is inferred as carry+LUT4 instead of…
… one cell as add Signed-off-by: Lalit Sharma <[email protected]>
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Separating LUT4 definition for PP3 & AP3
Signed-off-by: Lalit Sharma <[email protected]>
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Merging changes from parent repo
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Fixed synth_quicklogic flow to allow AP3 adder inference
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Updating latch definition in cells_map file for AP3
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Inferring adder as a cell - full_adder
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Modify options to optimize lut utilization
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Adding lut optimization support for AP3
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Removing ap3_ff_map.v file and updating ap3_ffs_map.v file
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Optimizing adder inference for AP3
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added support for infering and initialization of bram
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abc lut option updated for ap2
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Changing lut option in abc for ap2
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update lut option in abc command
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Adding EQN property to LUT instance in edf
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Adding optimizations to PP3 synthesis
Signed-off-by: Lalit Sharma <[email protected]>
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Incorporating code review comments from Karol
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Removing latch definition which is now defined in a separate file
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Reverting lut option as suggested by Maciej
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Signed-off-by: Tarachand Pagarani <[email protected]>
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Modified the ram models to support initialization
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Signed-off-by: Maciej Kurc <[email protected]>
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correct the clock ports for RAM8k
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modified to correct the yosys compilation error
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Signed-off-by: Lalit Sharma <[email protected]>
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initialize bram primitives from hex file
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update make file to remove FIFO and RAM block depedencies
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map_bram is run only for PP3 as of now
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Modified pp3_cells_sim.v file to support RAM init
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Adding cell mapping for _DFFSR_NPP_ & _DFFSR_PPP_
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change init file format for 16k block
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Signed-off-by: Lalit Sharma <[email protected]>
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Signed-off-by: Lalit Sharma <[email protected]>
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Supporting d_buff inference for AP3
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Infer clk port in in_reg or out_reg as ck_buff for AP3 & AP2 devices.
Signed-off-by: Lalit Sharma <[email protected]>
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Adding external pad property to rst port
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Rectifying clkbuf property on in_reg in AP2
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Fixing an issue in RAM/DSP cell mapping
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Updating in_reg/out_reg def in AP3. Replacing in_reg, out_reg with io…
…_reg in AP2 Signed-off-by: Lalit Sharma <[email protected]>
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Rectifying d_buff declaration issue
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Fixing a compilation error in verilog
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Changing QL_CARRY to full_adder for AP2 & AP3 device
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Replacing adder instance to full_adder for AP2, like AP3
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Changing to uppercase for primitive cell names of AP3
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Fix wrong rebase strategy remains
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Substitute YS_OVERRIDE with override
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Updating IO names to lower case
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Added additional ABC optimizations to synth_quicklogic
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Allow less efficient use of BRAM resources
Before this change, yosys required 4096 bits (or at least 50%) of the bits in a RAM to be used, in order to implement it as a PB-RAM. Since there are less than 1000 FFs available in the FPGA it means that any memory using somewhere between 1k and 4k bits will not fit in the device. This lowers the requirements on RAM efficiency to be more in line with the iCE40 backend, which uses comparably sized FPGAs Signed-off-by: Olof Kindgren <[email protected]>
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Fix missing new lines and improve code formatting
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