ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IOC programming model) Suggested workaround is to do an additional Control Reg read, which ensures the 2nd read gets the right status. Cc: [email protected] #4.10 Signed-off-by: Alexey Brodkin <[email protected]> [vgupta: reworte changelog a bit] Signed-off-by: Vineet Gupta <[email protected]>
OpenDingux · Mar 31, 2017 · c70c473 · c70c473
1 parent ae9955a
commit c70c473
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
@@ -633,6 +633,9 @@ noinline static void slc_entire_op(const int op)
 
 	write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
 
+	/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+	read_aux_reg(r);
+
 	/* Important to wait for flush to complete */
 	while (read_aux_reg(r) & SLC_CTRL_BUSY);
 }