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Learning Switch Output Port Lookup
switch_output_port_lookup
v1.0.0
IP core (HW)
hw/lib/std/switch_output_port_lookup_v1_0_1/
AXI4-Stream
AXI-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.
C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.
C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.
SRC_PORT_POS: Source Port Position in the TUSER Field (note this is currently hardcoded in submodules)
DST_PORT_POS: DestinationPort Position in the TUSER Field (note this is currently hardcoded in submodules)
NUM_OUTPUT_QUEUES: Number of output queues.
C_BASEADDR: Base address value of the core.
C_HIGHADDR: High address value of the core.
This module uses register infrastructure Ver 1.00, please refer to here for more details.
0x0 : ID - Block ID
0x4 : VERSION - Block Version
0x8 : Reset - Clear counters [0], reset registers [4] and reset tables [8]
0xC : FLIP - Returns the negative value of a written register
0x10: DEBUG - Debug register, returns the written value plus a preconfigured value
0x14 : COUNTERIN - Total number of incoming packets
0x18: COUNTEROUT - Total number of outgoing packets
0x1C: LUTHIT - Total number of lookup table hits
0x20: LUTMISS - Total number of lookup table misses
The function of this block is to set the destination port metadata field for all packets. In the Learning Switch, each arriving packet first goes through an Ethernet parser where the source and destination MAC addresses and the source port are extracted from the packet. The fields are then looked up in the CAM. If the result is a hit, the packet will be sent to the destination ports indicated by the lookup (except for the source port). If the result is a miss, the destination ports are set to broadcast to all output ports (except for the source port). If the source MAC is not in the CAM, it will be learned for future lookups.