Restrict the first two variables in the Constraint system #324
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Still a bit confused. Isn't "insert_sub_gate" creating a - b = c where c = 0? |
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I am aware that this would lead to different indexing. But still the original one is not wrong? |
the circuit is unrelated to the value of 'wire' and is instead related to the selector? |
confuseSUN
changed the title
weikengchen
approved these changes
Oct 31, 2023
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The major changes of this PR
The equal_gate is implemented using a sub_gate, but the output selector in the sub_gate is set to 1, which makes the equal_gate act as a sub_gate. We need to restrict the output selector to be 0 in equal_gate.
The major impacts of this PR
Extra documentations