update verilog examples

FPGAwars · May 3, 2024 · 280095a · 280095a
1 parent 1fb58f7
commit 280095a
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Showing 10 changed files with 57,522 additions and 698 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1 +1,2 @@
 *.mo
+ice-build/
diff --git a/examples/6. Verilog/01. Four bits fixed binary value.ice b/examples/6. Verilog/01. Four bits fixed binary value.ice
@@ -8,7 +8,7 @@
     "image": ""
   },
   "design": {
-    "board": "icezum",
+    "board": "alhambra-ii",
     "graph": {
       "blocks": [
         {
@@ -20,7 +20,7 @@
               {
                 "index": "0",
                 "name": "LED3",
-                "value": "98"
+                "value": "42"
               }
             ],
             "virtual": false
@@ -39,7 +39,7 @@
               {
                 "index": "0",
                 "name": "LED2",
-                "value": "97"
+                "value": "43"
               }
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             "virtual": false
@@ -58,7 +58,7 @@
               {
                 "index": "0",
                 "name": "LED1",
-                "value": "96"
+                "value": "44"
               }
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             "virtual": false
@@ -77,7 +77,7 @@
               {
                 "index": "0",
                 "name": "LED0",
-                "value": "95"
+                "value": "45"
               }
             ],
             "virtual": false

diff --git a/examples/6. Verilog/02. Four bits fixed hexadecimal value.ice b/examples/6. Verilog/02. Four bits fixed hexadecimal value.ice
@@ -8,7 +8,7 @@
     "image": ""
   },
   "design": {
-    "board": "icezum",
+    "board": "alhambra-ii",
     "graph": {
       "blocks": [
         {
@@ -20,7 +20,7 @@
               {
                 "index": "0",
                 "name": "LED3",
-                "value": "98"
+                "value": "42"
               }
             ],
             "virtual": false
@@ -39,7 +39,7 @@
               {
                 "index": "0",
                 "name": "LED2",
-                "value": "97"
+                "value": "43"
               }
             ],
             "virtual": false
@@ -58,7 +58,7 @@
               {
                 "index": "0",
                 "name": "LED1",
-                "value": "96"
+                "value": "44"
               }
             ],
             "virtual": false
@@ -77,7 +77,7 @@
               {
                 "index": "0",
                 "name": "LED0",
-                "value": "95"
+                "value": "45"
               }
             ],
             "virtual": false

diff --git a/examples/6. Verilog/03. Eight bits fixed value buses.ice b/examples/6. Verilog/03. Eight bits fixed value buses.ice
@@ -8,7 +8,7 @@
     "image": ""
   },
   "design": {
-    "board": "icezum",
+    "board": "alhambra-ii",
     "graph": {
       "blocks": [
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@@ -21,42 +21,42 @@
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+                "value": "38"
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+                "value": "39"
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                 "name": "LED4",
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+                "value": "41"
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+                "value": "42"
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-                "value": "97"
+                "value": "43"
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-                "value": "96"
+                "value": "44"
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                 "index": "0",
                 "name": "LED0",
-                "value": "95"
+                "value": "45"
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             "virtual": false