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Merge pull request #3 from ProbabilityEngineer/collection-default-upd…
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…ated-flipflops

Updated flipflops
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@Obijuan
Obijuan authored Jan 31, 2024
2 parents b73ecac + 3f9cf50 commit 0369d25
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37 changes: 33 additions & 4 deletions blocks/Logic/Sequential/Flip-flop D.ice
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Expand Up @@ -70,12 +70,23 @@
"y": 304
}
},
{
"id": "7c0dcfe6-efa3-47d5-bc41-b52e1a3daf47",
"type": "basic.constant",
"data": {
"name": "INI",
"value": "0",
"local": false
},
"position": {
"x": 568,
"y": 16
}
},
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"code": "// D flip-flop\n\nreg q = 1'b0;\n\nalways @(posedge clk)\nbegin\n q <= d;\nend\n\n",
"params": [],
"ports": {
"in": [
{
Expand All @@ -89,8 +100,16 @@
{
"name": "q"
}
]
}
],
"inoutLeft": [],
"inoutRight": []
},
"params": [
{
"name": "INI"
}
],
"code": "// D flip-flop\n\n//-- Initial value\nreg qi = INI;\n\n//-- On the rising edge of the \n//-- system clock put input\n//-- data in register qi\nalways @(posedge clk)\n qi <= d;\n\n//-- The output pin q reflects\n//-- the state of register qi\nassign q = qi;\n\n"
},
"position": {
"x": 432,
Expand Down Expand Up @@ -132,6 +151,16 @@
"block": "ffdd9aa2-aea3-4aa9-8431-80e799226774",
"port": "in"
}
},
{
"source": {
"block": "7c0dcfe6-efa3-47d5-bc41-b52e1a3daf47",
"port": "constant-out"
},
"target": {
"block": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"port": "INI"
}
}
]
}
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91 changes: 60 additions & 31 deletions blocks/Logic/Sequential/Flip-flop T.ice
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Original file line number Diff line number Diff line change
Expand Up @@ -137,37 +137,6 @@
"design": {
"graph": {
"blocks": [
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"code": "// D flip-flop\n\nreg q = 1'b0;\n\nalways @(posedge clk)\nbegin\n q <= d;\nend\n\n",
"params": [],
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
]
}
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
},
{
"id": "6855f64f-fa1c-4371-b2e1-a98970674a96",
"type": "basic.input",
Expand Down Expand Up @@ -202,6 +171,56 @@
"x": 232,
"y": 304
}
},
{
"id": "d5c0c304-357a-4f03-9765-d50f9f7d53a9",
"type": "basic.constant",
"data": {
"name": "",
"value": "0",
"local": false
},
"position": {
"x": 568,
"y": 32
}
},
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
],
"inoutLeft": [],
"inoutRight": []
},
"params": [
{
"name": "INI"
}
],
"code": "// D flip-flop\n\n//-- Initial value\nreg qi = INI;\n\n//-- On the rising edge of the \n//-- system clock put input\n//-- data in register qi\nalways @(posedge clk)\n qi <= d;\n \n//-- The output pin q reflects\n//-- the state of register qi\nassign q = qi;\n\n"
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
}
],
"wires": [
Expand Down Expand Up @@ -234,6 +253,16 @@
"block": "ffdd9aa2-aea3-4aa9-8431-80e799226774",
"port": "in"
}
},
{
"source": {
"block": "d5c0c304-357a-4f03-9765-d50f9f7d53a9",
"port": "constant-out"
},
"target": {
"block": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"port": "INI"
}
}
]
}
Expand Down
91 changes: 60 additions & 31 deletions examples/2. Flip-flops/01. DFF manual load.ice
View file
Original file line number Diff line number Diff line change
Expand Up @@ -137,37 +137,6 @@
"design": {
"graph": {
"blocks": [
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"code": "// D flip-flop\n\nreg q = 1'b0;\n\nalways @(posedge clk)\nbegin\n q <= d;\nend\n\n",
"params": [],
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
]
}
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
},
{
"id": "6855f64f-fa1c-4371-b2e1-a98970674a96",
"type": "basic.input",
Expand Down Expand Up @@ -202,6 +171,56 @@
"x": 232,
"y": 304
}
},
{
"id": "5c23f968-b0f2-4f1a-bad0-397e50c34c0c",
"type": "basic.constant",
"data": {
"name": "",
"value": "0",
"local": false
},
"position": {
"x": 568,
"y": 32
}
},
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
],
"inoutLeft": [],
"inoutRight": []
},
"params": [
{
"name": "INI"
}
],
"code": "// D flip-flop\n\n//-- Initial value\nreg qi = INI;\n\n//-- On the rising edge of the \n//-- system clock put input\n//-- data in register qi\nalways @(posedge clk)\n qi <= d;\n\n//-- The output pin q reflects\n//-- the state of register qi\nassign q = qi;\n"
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
}
],
"wires": [
Expand Down Expand Up @@ -234,6 +253,16 @@
"block": "ffdd9aa2-aea3-4aa9-8431-80e799226774",
"port": "in"
}
},
{
"source": {
"block": "5c23f968-b0f2-4f1a-bad0-397e50c34c0c",
"port": "constant-out"
},
"target": {
"block": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"port": "INI"
}
}
]
}
Expand Down
91 changes: 60 additions & 31 deletions examples/2. Flip-flops/02. Chain of three DFFs.ice
View file
Original file line number Diff line number Diff line change
Expand Up @@ -406,37 +406,6 @@
"design": {
"graph": {
"blocks": [
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"code": "// D flip-flop\n\nreg q = 1'b0;\n\nalways @(posedge clk)\nbegin\n q <= d;\nend\n\n",
"params": [],
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
]
}
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
},
{
"id": "6855f64f-fa1c-4371-b2e1-a98970674a96",
"type": "basic.input",
Expand Down Expand Up @@ -471,6 +440,56 @@
"x": 232,
"y": 304
}
},
{
"id": "0914d43b-6de9-4105-a841-99bdaa35e718",
"type": "basic.constant",
"data": {
"name": "",
"value": "0",
"local": false
},
"position": {
"x": 568,
"y": 32
}
},
{
"id": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"type": "basic.code",
"data": {
"ports": {
"in": [
{
"name": "clk"
},
{
"name": "d"
}
],
"out": [
{
"name": "q"
}
],
"inoutLeft": [],
"inoutRight": []
},
"params": [
{
"name": "INI"
}
],
"code": "// D flip-flop\n\n//-- Initial value\nreg qi = INI;\n\n//-- On the rising edge of the \n//-- system clock put input\n//-- data in register qi\nalways @(posedge clk)\n qi <= d;\n \n//-- The output pin q reflects\n//-- the state of register qi\nassign q = qi;\n"
},
"position": {
"x": 432,
"y": 128
},
"size": {
"width": 368,
"height": 272
}
}
],
"wires": [
Expand Down Expand Up @@ -503,6 +522,16 @@
"block": "ffdd9aa2-aea3-4aa9-8431-80e799226774",
"port": "in"
}
},
{
"source": {
"block": "0914d43b-6de9-4105-a841-99bdaa35e718",
"port": "constant-out"
},
"target": {
"block": "e5222a6e-4717-4f08-99d7-7cde897060ca",
"port": "INI"
}
}
]
}
Expand Down
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