Merge pull request #43 from DylanVanAssche/feature/ISSUE-10

Feature/issue 10

README.md

@@ -7,17 +7,32 @@ This repository contains the VHDL files for the course "Digital Synthese: practi
 - Transmitter (top file)
 	- access layer: PNGenerator, MUX
 	- datalink layer: SequenceController, DataRegister
-	- application layer: EdgeDetector, UpDownCounter, Debouncer, SegDecoder 
+	- application layer: EdgeDetector, UpDownCounter, Debouncer, SegDecoder
 
 - Receiver (top file)
 	- access layer: SegDecoder, DataLatch
 	- datalink layer: DataShiftReg
 	- application layer: DPLL, MatchedFilter, Correlator, Despreader, MUX, PNGenerator, Edgedetector
 
-- Hardware UCF (Xilinx FPGA file)
-	- transmitter
-	- receiver
+- Hardware
+	- transmitter: Xilinx UCF file, Transmitter hardware top file
+	- receiver: Xilinx UCF file, Receiver hardware top file
+
+## Testbench (total_test.vhd)
+![Total testbench](docs/total_testbench.png "Total testbench")
+
+## Result
+A fully working DSSS Wireless Transmit-Receive System with 3 different PN codes.
+
+<h1 align="center">
+<img src="docs/deployment1.jpg" width="600px" alt="2 Virtex II Pro FPGA as a DSSS Wireless Transmit-Receive System">
+</h1>
+<h1 align="center">
+<img src="docs/deployment2.jpg" width="600px" alt="Wireless extension board for the Virtex II Pro FPGA">
+</h1>
+<h1 align="center">
+<img src="docs/demo.gif" width="600px" alt="Demo">
+</h1>
 
 ## License
 Everything in this repository is available under the GPLv3 License.
-

hardware/README.md

@@ -0,0 +1,11 @@
+# Deployment
+## What do you need?
+- FPGA platform (Virtex II Pro)
+- VHDL compiler
+- FPGA upload software, see the website of the FPGA manufacturer
+
+## Steps
+- Compile the VHDL code using a VHDL compiler. The top and UCF files for the Virtex II Pro platform are included in this repo.
+- Upload the bitfile to the FPGA using the upload software from your manufacturer.
+- Press the reset button to initialize the FPGA.
+- Enjoy!

hardware/receiver/nco.vhd

@@ -0,0 +1,66 @@
+--***************************************
+--* TITLE: NCO (receiver)		*
+--* TYPE: Component 			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 13/12/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- NCO to divide the 100 Mhz clock of the Virtex II Pro.
+--2)Principle:
+-- When counting down, send a clk_en signal out and restart.
+--3)Ingangen:
+-- rst, clk
+--4)Uitgangen:
+-- clk_en
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY nco_rx IS
+	PORT
+	(
+		clk     : IN std_logic;
+		rst     : IN std_logic;
+		clk_en  : OUT std_logic
+	);
+END;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF nco_rx IS
+	SIGNAL n_count		: std_logic_vector(10 DOWNTO 0);
+	SIGNAL p_count		: std_logic_vector(10 DOWNTO 0);
+	SIGNAL enable		: std_logic := '1'; -- allow for reset
+	SIGNAL enable_next	: std_logic := '0';
+	CONSTANT TRIGGER	: std_logic_vector(10 DOWNTO 0) := (OTHERS => '0');
+BEGIN
+clk_en <= enable;
+-- 2-Process: synchronous part
+count_sync : PROCESS (clk)
+BEGIN
+	IF (rising_edge(clk)) THEN
+		IF (rst = '1') THEN -- rst line high, go to initial state
+			p_count <= (OTHERS => '0');
+			enable <= '1';
+		ELSE -- normal operation
+			p_count <= n_count;
+			enable <= enable_next;
+		END IF;
+	END IF;
+END PROCESS count_sync;
+-- 2-Process: combinatoric part
+count_comb : PROCESS (p_count, enable)
+BEGIN
+	n_count <= p_count + 1;
+	IF (n_count = TRIGGER) THEN -- clk_en signal
+		enable_next <= '1';
+	ELSE
+		enable_next <= '0';
+	END IF;
+END PROCESS count_comb;
+END behavior;

hardware/receiver.ucf → hardware/receiver/receiver.ucf

@@ -8,9 +8,9 @@
 #****************
 #* CLOCK 100MHz *
 #****************
-Net clk_100mhz LOC="AJ15";
-Net clk_100mhz IOSTANDARD = LVCMOS25;
-Net clk_100mhz PERIOD = 10000 ps;
+NET clk LOC="AJ15";
+NET clk IOSTANDARD = LVCMOS25;
+NET clk PERIOD = 10000 ps;
 
 #*********************
 #* 7 SEGMENT DISPLAY *

hardware/receiver.vhd → hardware/receiver/receiver.vhd

@@ -1,105 +1,105 @@
---***************************************
---* TITLE: Receiver (receiver) 		*
---* TYPE: Top File			*
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 9/12/2017 			*
---***************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Connect all the layers into 1 VHDL file.
---2)Principle:
--- Connect every layer API.
---3)Inputs:
--- rx, pn_select, rst, clk, clk_en
---4)Outputs:
--- display_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-ENTITY receiver IS
-	PORT
-	(
-		clk		: IN std_logic;
-		rst_b		: IN std_logic;
-		rx		: IN std_logic;
-		pn_select_b_SW0	: IN std_logic;
-		pn_select_b_SW1	: IN std_logic;
-		display_b_SEG_A : OUT std_logic;
-		display_b_SEG_B : OUT std_logic;
-		display_b_SEG_C : OUT std_logic;
-		display_b_SEG_D : OUT std_logic;
-		display_b_SEG_E : OUT std_logic;
-		display_b_SEG_F : OUT std_logic;
-		display_b_SEG_G : OUT std_logic;
-		display_b_SEG_DP: OUT std_logic
-	);
-END receiver ;
-ARCHITECTURE behavior OF receiver IS
-	SIGNAL bitsample	: std_logic;
-	SIGNAL databit		: std_logic;
-	SIGNAL rst_b		: std_logic;
-	SIGNAL clk_en		: std_logic;
-	SIGNAL preamble		: std_logic_vector(6 DOWNTO 0);
-	SIGNAL data		: std_logic_vector(3 DOWNTO 0); -- received number from transmitter
-	SIGNAL display_b	: std_logic_vector(6 DOWNTO 0);
-	SIGNAL pn_select: std_logic_vector(1 DOWNTO 0);
-BEGIN
--- display outputs
-display_b_SEG_A <= display_b(6);
-display_b_SEG_B <= display_b(5);
-display_b_SEG_C <= display_b(4);
-display_b_SEG_D <= display_b(3);
-display_b_SEG_E <= display_b(2);
-display_b_SEG_F <= display_b(1);
-display_b_SEG_G <= display_b(0);
-display_b_SEG_DP <= '1'; -- turn DOT off
--- dipswitch inputs
-pn_select <= NOT(pn_select_b_SW1) & NOT(pn_select_b_SW0)
--- buttons inputs
-rst <= NOT(rst_b);
---layers
-nco_rx : ENTITY work.nco_rx(behavior)
-PORT MAP
-(
-	clk    => clk,
-	rst    => rst,
-	clk_en => clk_en
-);
-application_layer : ENTITY work.application_layer(behavior)
-PORT MAP
-(
-	clk       => clk,
-	clk_en    => clk_en,
-	rst       => rst,
-	bitsample => bitsample,
-	preamble  => preamble,
-	data_in   => data,
-	display_b => display_b
-);
-datalink_layer : ENTITY work.datashiftreg(behavior) -- datalink layer is only 1 component
-PORT MAP
-(
-	clk        => clk,
-	clk_en     => clk_en,
-	rst        => rst,
-	bitsample  => bitsample,
-	databit    => databit,
-	preamble   => preamble,
-	data       => data 
-);
-access_layer : ENTITY work.access_layer(behavior)
-PORT MAP
-(
-	clk		=> clk,
-	clk_en		=> clk_en,
-	rst		=> rst,
-	sdi_spread	=> rx,
-	pn_select	=> pn_select,
-	bitsample_out	=> bitsample,
-	databit		=> databit
-);
+--***************************************
+--* TITLE: Receiver (receiver) 		*
+--* TYPE: Top File			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 9/12/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Connect all the layers into 1 VHDL file.
+--2)Principle:
+-- Connect every layer API.
+--3)Inputs:
+-- rx, pn_select, rst, clk, clk_en
+--4)Outputs:
+-- display_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+ENTITY receiver_hw IS
+	PORT
+	(
+		clk		: IN std_logic;
+		rst_b		: IN std_logic;
+		rx		: IN std_logic;
+		pn_select_b_SW0	: IN std_logic;
+		pn_select_b_SW1	: IN std_logic;
+		display_b_SEG_A : OUT std_logic;
+		display_b_SEG_B : OUT std_logic;
+		display_b_SEG_C : OUT std_logic;
+		display_b_SEG_D : OUT std_logic;
+		display_b_SEG_E : OUT std_logic;
+		display_b_SEG_F : OUT std_logic;
+		display_b_SEG_G : OUT std_logic;
+		display_b_SEG_DP: OUT std_logic
+	);
+END receiver_hw;
+ARCHITECTURE behavior OF receiver_hw IS
+	SIGNAL bitsample	: std_logic;
+	SIGNAL databit		: std_logic;
+	SIGNAL rst		: std_logic;
+	SIGNAL clk_en		: std_logic;
+	SIGNAL preamble		: std_logic_vector(6 DOWNTO 0);
+	SIGNAL data		: std_logic_vector(3 DOWNTO 0); -- received number from transmitter
+	SIGNAL display_b	: std_logic_vector(6 DOWNTO 0);
+	SIGNAL pn_select: std_logic_vector(1 DOWNTO 0);
+BEGIN
+-- display outputs
+display_b_SEG_A <= display_b(6);
+display_b_SEG_B <= display_b(5);
+display_b_SEG_C <= display_b(4);
+display_b_SEG_D <= display_b(3);
+display_b_SEG_E <= display_b(2);
+display_b_SEG_F <= display_b(1);
+display_b_SEG_G <= display_b(0);
+display_b_SEG_DP <= '1'; -- turn DOT off
+-- dipswitch inputs
+pn_select <= NOT(pn_select_b_SW1) & NOT(pn_select_b_SW0);
+-- buttons inputs
+rst <= NOT(rst_b);
+--layers
+nco_rx : ENTITY work.nco_rx(behavior)
+PORT MAP
+(
+	clk    => clk,
+	rst    => rst,
+	clk_en => clk_en
+);
+application_layer : ENTITY work.application_layer(behavior)
+PORT MAP
+(
+	clk       => clk,
+	clk_en    => clk_en,
+	rst       => rst,
+	bitsample => bitsample,
+	preamble  => preamble,
+	data_in   => data,
+	display_b => display_b
+);
+datalink_layer : ENTITY work.datashiftreg(behavior) -- datalink layer is only 1 component
+PORT MAP
+(
+	clk        => clk,
+	clk_en     => clk_en,
+	rst        => rst,
+	bitsample  => bitsample,
+	databit    => databit,
+	preamble   => preamble,
+	data       => data 
+);
+access_layer : ENTITY work.access_layer(behavior)
+PORT MAP
+(
+	clk		=> clk,
+	clk_en		=> clk_en,
+	rst		=> rst,
+	sdi_spread	=> rx,
+	pn_select	=> pn_select,
+	bitsample_out	=> bitsample,
+	databit		=> databit
+);
 END behavior;