Update Chapter_6.rst

Baungarten-CINVESTAV · Nov 6, 2023 · c791732 · c791732
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diff --git a/HTML_Docs/source/Chapter_6.rst b/HTML_Docs/source/Chapter_6.rst
@@ -211,7 +211,7 @@ Following the execution of the testbench, you will discover the wave simulation,
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-   Fig. 7.2: As shown in the image, color-coded signals enhance visualization: Yellow represents AES I/O, Orange depicts DES I/O, Purple indicates Data/Key/Output registers, Green signifies Wishbone signals, and Red marks GPIO ports.
+   Fig. 7.2: As shown in the image, color-coded signals enhance visualization: Yellow represents AES I/O, Orange depicts DES I/O, Purple indicates Data/Key/Output registers, Green signifies Wishbone signals, and Blue marks GPIO ports.
 
 Notice the alignment of GPIO ports with values provided by the RISC-V processor when encryption matches the expected encrypted value. This synchronization demonstrates the correct functioning of the encryption process.