diff --git a/hw/application_fpga/core/ram/rtl/ram.v b/hw/application_fpga/core/ram/rtl/ram.v
index 4e8eda7b..fe36c132 100644
--- a/hw/application_fpga/core/ram/rtl/ram.v
+++ b/hw/application_fpga/core/ram/rtl/ram.v
@@ -27,7 +27,7 @@ module ram(
 
            input   wire          cs,
 	   input   wire [03 : 0] we,
-	   input   wire [14 : 0] address,
+	   input   wire [15 : 0] address,
 	   input   wire [31 : 0] write_data,
 	   output  wire [31 : 0] read_data,
 	   output  wire          ready
@@ -140,7 +140,7 @@ module ram(
   //----------------------------------------------------------------
   always @*
     begin: scramble_descramble
-      scrambled_ram_addr    = address ^ ram_addr_rand;
+      scrambled_ram_addr    = address[14 : 0]  ^ ram_addr_rand;
       scrambled_write_data  = write_data ^ ram_data_rand ^ {2{address}};
       descrambled_read_data = muxed_read_data ^ ram_data_rand ^ {2{address}};
     end
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index 7dcf14fe..4b274b20 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -94,7 +94,7 @@ module application_fpga(
 
   reg           ram_cs;
   reg  [3 : 0]  ram_we;
-  reg  [14 : 0] ram_address;
+  reg  [15 : 0] ram_address;
   reg  [31 : 0] ram_write_data;
   wire [31 : 0] ram_read_data;
   wire          ram_ready;
@@ -397,7 +397,7 @@ module application_fpga(
 
       ram_cs              = 1'h0;
       ram_we              = 4'h0;
-      ram_address         = cpu_addr[16 : 2];
+      ram_address         = cpu_addr[17 : 2];
       ram_write_data      = cpu_wdata;
 
       fw_ram_cs           = 1'h0;