-
Notifications
You must be signed in to change notification settings - Fork 2
/
hardware.go
113 lines (94 loc) · 1.75 KB
/
hardware.go
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
package gemu
type Hardware struct {
Up IHardware
Down []IHardware
Class *HardwareClass
}
func (H *Hardware) GetClass() *HardwareClass {
return H.Class
}
func (H *Hardware) GetUp() IHardware {
return H.Up
}
func (H *Hardware) GetMem() IMem {
if H.Up != nil {
if dcpu, ok := H.Up.(*DCPU); ok {
return dcpu.Mem
}
}
return nil
}
func (H *Hardware) SetUp(up IHardware) {
H.Up = up
}
func (H *Hardware) Attach(Add IHardware) {
H.Down = append(H.Down, Add)
}
func (H *Hardware) GetDown() []IHardware {
return H.Down
}
func (H *Hardware) Start() {
for _, obj := range H.Down {
obj.Start()
}
}
func (H *Hardware) Stop() {
for _, obj := range H.Down {
obj.Stop()
}
}
func (H *Hardware) Reset() {
for _, obj := range H.Down {
obj.Reset()
}
}
func (H *Hardware) HWI(D *DCPU) {
//log.Printf("Unhandled HWI\n")
}
func (H *Hardware) HWQ(D *DCPU) {
C := H.GetClass()
D.Reg[0] = uint16(C.DevID & 0xFFFF)
D.Reg[1] = uint16((C.DevID >> 16) & 0xFFFF)
D.Reg[2] = C.VerID
D.Reg[3] = uint16(C.MfgID & 0xFFFF)
D.Reg[4] = uint16((C.MfgID >> 16) & 0xFFFF)
}
type IHardware interface {
GetUp() IHardware
GetMem() IMem
Attach(Add IHardware)
GetDown() []IHardware
SetUp(up IHardware)
GetClass() *HardwareClass
Start()
Stop()
Reset()
HWI(D *DCPU)
HWQ(D *DCPU)
}
type Ticker interface {
Tick(int)
}
type HardwareClass struct {
Name string
Desc string
DevID uint32
VerID uint16
MfgID uint32
}
type IStateChanges interface {
IsDirty() bool
ClearDirty()
}
var Classes []*HardwareClass
func RegisterClass(hc *HardwareClass) {
Classes = append(Classes, hc)
}
type IMem interface {
ReadMem(addr uint16) uint16
WriteMem(addr uint16, val uint16)
LoadMem(data []uint16)
GetRaw() []uint16
RegisterSync(addr uint16, synclen uint16) *Sync
Reset()
}