From 0bc6b09dee2dda0b8373572bd0fa4e2fb8b4f594 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Thu, 16 May 2024 16:31:32 +0200 Subject: [PATCH 1/3] add is42s32400f to devices --- src/devices/is42s32400f.rs | 57 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 src/devices/is42s32400f.rs diff --git a/src/devices/is42s32400f.rs b/src/devices/is42s32400f.rs new file mode 100644 index 0000000..4a0b956 --- /dev/null +++ b/src/devices/is42s32400f.rs @@ -0,0 +1,57 @@ +/// ISI IS42S32400F SDRAM +#[allow(unused)] + +/// Speed Grade 6 +pub mod is42s32800g_6 { + use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming}; + + const BURST_LENGTH_1: u16 = 0x0000; + const BURST_LENGTH_2: u16 = 0x0001; + const BURST_LENGTH_4: u16 = 0x0002; + const BURST_LENGTH_8: u16 = 0x0004; + const BURST_TYPE_SEQUENTIAL: u16 = 0x0000; + const BURST_TYPE_INTERLEAVED: u16 = 0x0008; + const CAS_LATENCY_2: u16 = 0x0020; + const CAS_LATENCY_3: u16 = 0x0030; + const OPERATING_MODE_STANDARD: u16 = 0x0000; + const WRITEBURST_MODE_PROGRAMMED: u16 = 0x0000; + const WRITEBURST_MODE_SINGLE: u16 = 0x0200; + + /// Is42s32400f with Speed Grade 6 + #[derive(Clone, Copy, Debug, PartialEq)] + pub struct Is42s32400f6 {} + + impl SdramChip for Is42s32400f6 { + /// Value of the mode register + const MODE_REGISTER: u16 = BURST_LENGTH_1 + | BURST_TYPE_SEQUENTIAL + | CAS_LATENCY_3 + | OPERATING_MODE_STANDARD + | WRITEBURST_MODE_SINGLE; + + /// Timing Parameters + const TIMING: SdramTiming = SdramTiming { + startup_delay_ns: 100_000, // 100 µs + max_sd_clock_hz: 100_000_000, // 100 MHz + refresh_period_ns: 15_625, // 64ms / (4096 rows) = 15625ns + mode_register_to_active: 2, // tMRD = 2 cycles + exit_self_refresh: 7, // tXSR = 70ns + active_to_precharge: 4, // tRAS = 42ns + row_cycle: 6, // tRC = 60ns + row_precharge: 2, // tRP = 18ns + row_to_column: 2, // tRCD = 18ns + }; + + /// SDRAM controller configuration + const CONFIG: SdramConfiguration = SdramConfiguration { + column_bits: 8, + row_bits: 12, + memory_data_width: 32, // 32-bit + internal_banks: 4, // 4 internal banks + cas_latency: 3, // CAS latency = 3 + write_protection: false, + read_burst: true, + read_pipe_delay_cycles: 0, + }; + } +} From e23905012e461819d0f2762d9e3fc96b1d2727c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=ABl=20Schulz-Ansres?= Date: Thu, 16 May 2024 16:37:43 +0200 Subject: [PATCH 2/3] fix name --- src/devices/is42s32400f.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/devices/is42s32400f.rs b/src/devices/is42s32400f.rs index 4a0b956..cfe6e87 100644 --- a/src/devices/is42s32400f.rs +++ b/src/devices/is42s32400f.rs @@ -2,7 +2,7 @@ #[allow(unused)] /// Speed Grade 6 -pub mod is42s32800g_6 { +pub mod is42s32400g_6 { use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming}; const BURST_LENGTH_1: u16 = 0x0000; From 674aca303bafc9e760d9a93a0850c9fda9c96200 Mon Sep 17 00:00:00 2001 From: Joel Schulz-Andres Date: Wed, 31 Jul 2024 11:00:44 +0200 Subject: [PATCH 3/3] Update src/devices/is42s32400f.rs Co-authored-by: Michael Fairman --- src/devices/is42s32400f.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/devices/is42s32400f.rs b/src/devices/is42s32400f.rs index cfe6e87..e64348c 100644 --- a/src/devices/is42s32400f.rs +++ b/src/devices/is42s32400f.rs @@ -2,7 +2,7 @@ #[allow(unused)] /// Speed Grade 6 -pub mod is42s32400g_6 { +pub mod is42s32400f_6 { use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming}; const BURST_LENGTH_1: u16 = 0x0000;