diff --git a/src/adc.rs b/src/adc.rs index 727cc936c..d0c9d41ad 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -23,42 +23,90 @@ pub struct RegisterBlock { #[doc = "0x20 - Interrupt status after masking & forcing"] pub ints: INTS, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: ADC Control and Status + +You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "ADC Control and Status"] pub mod cs; -#[doc = "RESULT (r) register accessor: an alias for `Reg`"] +#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion + +You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@result`] +module"] pub type RESULT = crate::Reg; #[doc = "Result of most recent ADC conversion"] pub mod result; -#[doc = "FCS (rw) register accessor: an alias for `Reg`"] +#[doc = "FCS (rw) register accessor: FIFO control and status + +You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fcs`] +module"] pub type FCS = crate::Reg; #[doc = "FIFO control and status"] pub mod fcs; -#[doc = "FIFO (r) register accessor: an alias for `Reg`"] +#[doc = "FIFO (r) register accessor: Conversion result FIFO + +You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "Conversion result FIFO"] pub mod fifo; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] pub mod div; -#[doc = "INTR (r) register accessor: an alias for `Reg`"] +#[doc = "INTR (r) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/adc/cs.rs b/src/adc/cs.rs index 62984359c..f248cdf9d 100644 --- a/src/adc/cs.rs +++ b/src/adc/cs.rs @@ -1,57 +1,25 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."] pub type TS_EN_R = crate::BitReader; #[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."] -pub type TS_EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>; +pub type TS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] pub type START_ONCE_R = crate::BitReader; #[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] -pub type START_ONCE_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>; +pub type START_ONCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] pub type START_MANY_R = crate::BitReader; #[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] -pub type START_MANY_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>; +pub type START_MANY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] pub type READY_R = crate::BitReader; @@ -60,11 +28,11 @@ pub type ERR_R = crate::BitReader; #[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."] pub type ERR_STICKY_R = crate::BitReader; #[doc = "Field `ERR_STICKY` writer - Some past ADC conversion encountered an error. Write 1 to clear."] -pub type ERR_STICKY_W<'a, const O: u8> = crate::BitWriter1C<'a, CS_SPEC, O>; +pub type ERR_STICKY_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode."] pub type AINSEL_R = crate::FieldReader; #[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."] -pub type AINSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 3, O>; +pub type AINSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. @@ -74,7 +42,7 @@ pub type RROBIN_R = crate::FieldReader; Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] -pub type RROBIN_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 5, O>; +pub type RROBIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; impl R { #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] @@ -132,37 +100,37 @@ impl W { 1 - enabled. 0 - disabled."] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."] #[inline(always)] #[must_use] - pub fn ts_en(&mut self) -> TS_EN_W<1> { + pub fn ts_en(&mut self) -> TS_EN_W { TS_EN_W::new(self) } #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] #[inline(always)] #[must_use] - pub fn start_once(&mut self) -> START_ONCE_W<2> { + pub fn start_once(&mut self) -> START_ONCE_W { START_ONCE_W::new(self) } #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] #[inline(always)] #[must_use] - pub fn start_many(&mut self) -> START_MANY_W<3> { + pub fn start_many(&mut self) -> START_MANY_W { START_MANY_W::new(self) } #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."] #[inline(always)] #[must_use] - pub fn err_sticky(&mut self) -> ERR_STICKY_W<10> { + pub fn err_sticky(&mut self) -> ERR_STICKY_W { ERR_STICKY_W::new(self) } #[doc = "Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode."] #[inline(always)] #[must_use] - pub fn ainsel(&mut self) -> AINSEL_W<12> { + pub fn ainsel(&mut self) -> AINSEL_W { AINSEL_W::new(self) } #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. @@ -171,32 +139,31 @@ impl W { AINSEL will be updated after each conversion with the newly-selected channel."] #[inline(always)] #[must_use] - pub fn rrobin(&mut self) -> RROBIN_W<16> { + pub fn rrobin(&mut self) -> RROBIN_W { RROBIN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "ADC Control and Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [cs](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0400; } diff --git a/src/adc/div.rs b/src/adc/div.rs index 9b596bc5a..b6205a995 100644 --- a/src/adc/div.rs +++ b/src/adc/div.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional part of clock divisor. First-order delta-sigma."] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional part of clock divisor. First-order delta-sigma."] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer part of clock divisor."] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer part of clock divisor."] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 16, O, u16>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."] #[inline(always)] @@ -58,19 +26,23 @@ impl W { #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:23 - Integer part of clock divisor."] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -79,20 +51,15 @@ impl W { The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/adc/fcs.rs b/src/adc/fcs.rs index d1aaa87c2..42199f18e 100644 --- a/src/adc/fcs.rs +++ b/src/adc/fcs.rs @@ -1,55 +1,23 @@ #[doc = "Register `FCS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FCS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - If 1: write result to the FIFO after each conversion."] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - If 1: write result to the FIFO after each conversion."] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, FCS_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHIFT` reader - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] pub type SHIFT_R = crate::BitReader; #[doc = "Field `SHIFT` writer - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] -pub type SHIFT_W<'a, const O: u8> = crate::BitWriter<'a, FCS_SPEC, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERR` reader - If 1: conversion error bit appears in the FIFO alongside the result"] pub type ERR_R = crate::BitReader; #[doc = "Field `ERR` writer - If 1: conversion error bit appears in the FIFO alongside the result"] -pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, FCS_SPEC, O>; +pub type ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DREQ_EN` reader - If 1: assert DMA requests when FIFO contains data"] pub type DREQ_EN_R = crate::BitReader; #[doc = "Field `DREQ_EN` writer - If 1: assert DMA requests when FIFO contains data"] -pub type DREQ_EN_W<'a, const O: u8> = crate::BitWriter<'a, FCS_SPEC, O>; +pub type DREQ_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMPTY` reader - "] pub type EMPTY_R = crate::BitReader; #[doc = "Field `FULL` reader - "] @@ -57,17 +25,17 @@ pub type FULL_R = crate::BitReader; #[doc = "Field `UNDER` reader - 1 if the FIFO has been underflowed. Write 1 to clear."] pub type UNDER_R = crate::BitReader; #[doc = "Field `UNDER` writer - 1 if the FIFO has been underflowed. Write 1 to clear."] -pub type UNDER_W<'a, const O: u8> = crate::BitWriter1C<'a, FCS_SPEC, O>; +pub type UNDER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `OVER` reader - 1 if the FIFO has been overflowed. Write 1 to clear."] pub type OVER_R = crate::BitReader; #[doc = "Field `OVER` writer - 1 if the FIFO has been overflowed. Write 1 to clear."] -pub type OVER_W<'a, const O: u8> = crate::BitWriter1C<'a, FCS_SPEC, O>; +pub type OVER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `LEVEL` reader - The number of conversion results currently waiting in the FIFO"] pub type LEVEL_R = crate::FieldReader; #[doc = "Field `THRESH` reader - DREQ/IRQ asserted when level >= threshold"] pub type THRESH_R = crate::FieldReader; #[doc = "Field `THRESH` writer - DREQ/IRQ asserted when level >= threshold"] -pub type THRESH_W<'a, const O: u8> = crate::FieldWriter<'a, FCS_SPEC, 4, O>; +pub type THRESH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."] #[inline(always)] @@ -124,68 +92,67 @@ impl W { #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<1> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"] #[inline(always)] #[must_use] - pub fn err(&mut self) -> ERR_W<2> { + pub fn err(&mut self) -> ERR_W { ERR_W::new(self) } #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"] #[inline(always)] #[must_use] - pub fn dreq_en(&mut self) -> DREQ_EN_W<3> { + pub fn dreq_en(&mut self) -> DREQ_EN_W { DREQ_EN_W::new(self) } #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."] #[inline(always)] #[must_use] - pub fn under(&mut self) -> UNDER_W<10> { + pub fn under(&mut self) -> UNDER_W { UNDER_W::new(self) } #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."] #[inline(always)] #[must_use] - pub fn over(&mut self) -> OVER_W<11> { + pub fn over(&mut self) -> OVER_W { OVER_W::new(self) } #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"] #[inline(always)] #[must_use] - pub fn thresh(&mut self) -> THRESH_W<24> { + pub fn thresh(&mut self) -> THRESH_W { THRESH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "FIFO control and status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fcs](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FCS_SPEC; impl crate::RegisterSpec for FCS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fcs::R](R) reader structure"] -impl crate::Readable for FCS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fcs::W](W) writer structure"] +#[doc = "`read()` method returns [`fcs::R`](R) reader structure"] +impl crate::Readable for FCS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fcs::W`](W) writer structure"] impl crate::Writable for FCS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0c00; } diff --git a/src/adc/fifo.rs b/src/adc/fifo.rs index 67d689630..03d1ac60c 100644 --- a/src/adc/fifo.rs +++ b/src/adc/fifo.rs @@ -1,18 +1,5 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `VAL` reader - "] pub type VAL_R = crate::FieldReader; #[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."] @@ -31,17 +18,13 @@ impl R { } #[doc = "Conversion result FIFO -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fifo](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} #[doc = "`reset()` method sets FIFO to value 0"] impl crate::Resettable for FIFO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/adc/inte.rs b/src/adc/inte.rs index a629a456b..b78edbbee 100644 --- a/src/adc/inte.rs +++ b/src/adc/inte.rs @@ -1,45 +1,13 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; #[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] -pub type FIFO_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type FIFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] @@ -53,32 +21,31 @@ impl W { This level can be programmed via the FCS_THRESH field."] #[inline(always)] #[must_use] - pub fn fifo(&mut self) -> FIFO_W<0> { + pub fn fifo(&mut self) -> FIFO_W { FIFO_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/adc/intf.rs b/src/adc/intf.rs index cf828d7b6..c17033f61 100644 --- a/src/adc/intf.rs +++ b/src/adc/intf.rs @@ -1,45 +1,13 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; #[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] -pub type FIFO_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type FIFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] @@ -53,32 +21,31 @@ impl W { This level can be programmed via the FCS_THRESH field."] #[inline(always)] #[must_use] - pub fn fifo(&mut self) -> FIFO_W<0> { + pub fn fifo(&mut self) -> FIFO_W { FIFO_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/adc/intr.rs b/src/adc/intr.rs index 9e30be7d7..f01d7590f 100644 --- a/src/adc/intr.rs +++ b/src/adc/intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; @@ -26,17 +13,13 @@ impl R { } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/adc/ints.rs b/src/adc/ints.rs index abc9bc6a6..d8b51c1f2 100644 --- a/src/adc/ints.rs +++ b/src/adc/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; @@ -26,17 +13,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/adc/result.rs b/src/adc/result.rs index 9958e82d1..7148fdfdc 100644 --- a/src/adc/result.rs +++ b/src/adc/result.rs @@ -1,18 +1,5 @@ #[doc = "Register `RESULT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RESULT` reader - "] pub type RESULT_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Result of most recent ADC conversion -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [result](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESULT_SPEC; impl crate::RegisterSpec for RESULT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [result::R](R) reader structure"] -impl crate::Readable for RESULT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`result::R`](R) reader structure"] +impl crate::Readable for RESULT_SPEC {} #[doc = "`reset()` method sets RESULT to value 0"] impl crate::Resettable for RESULT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/busctrl.rs b/src/busctrl.rs index 32c93310b..536d043f7 100644 --- a/src/busctrl.rs +++ b/src/busctrl.rs @@ -22,43 +22,93 @@ pub struct RegisterBlock { #[doc = "0x24 - Bus fabric performance event select for PERFCTR3"] pub perfsel3: PERFSEL3, } -#[doc = "BUS_PRIORITY (rw) register accessor: an alias for `Reg`"] +#[doc = "BUS_PRIORITY (rw) register accessor: Set the priority of each master for bus arbitration. + +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bus_priority`] +module"] pub type BUS_PRIORITY = crate::Reg; #[doc = "Set the priority of each master for bus arbitration."] pub mod bus_priority; -#[doc = "BUS_PRIORITY_ACK (r) register accessor: an alias for `Reg`"] +#[doc = "BUS_PRIORITY_ACK (r) register accessor: Bus priority acknowledge + +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bus_priority_ack`] +module"] pub type BUS_PRIORITY_ACK = crate::Reg; #[doc = "Bus priority acknowledge"] pub mod bus_priority_ack; -#[doc = "PERFCTR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFCTR0 (rw) register accessor: Bus fabric performance counter 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr0`] +module"] pub type PERFCTR0 = crate::Reg; #[doc = "Bus fabric performance counter 0"] pub mod perfctr0; -#[doc = "PERFSEL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFSEL0 (rw) register accessor: Bus fabric performance event select for PERFCTR0 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel0`] +module"] pub type PERFSEL0 = crate::Reg; #[doc = "Bus fabric performance event select for PERFCTR0"] pub mod perfsel0; -#[doc = "PERFCTR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFCTR1 (rw) register accessor: Bus fabric performance counter 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr1`] +module"] pub type PERFCTR1 = crate::Reg; #[doc = "Bus fabric performance counter 1"] pub mod perfctr1; -#[doc = "PERFSEL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFSEL1 (rw) register accessor: Bus fabric performance event select for PERFCTR1 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel1`] +module"] pub type PERFSEL1 = crate::Reg; #[doc = "Bus fabric performance event select for PERFCTR1"] pub mod perfsel1; -#[doc = "PERFCTR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFCTR2 (rw) register accessor: Bus fabric performance counter 2 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr2`] +module"] pub type PERFCTR2 = crate::Reg; #[doc = "Bus fabric performance counter 2"] pub mod perfctr2; -#[doc = "PERFSEL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFSEL2 (rw) register accessor: Bus fabric performance event select for PERFCTR2 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel2`] +module"] pub type PERFSEL2 = crate::Reg; #[doc = "Bus fabric performance event select for PERFCTR2"] pub mod perfsel2; -#[doc = "PERFCTR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFCTR3 (rw) register accessor: Bus fabric performance counter 3 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr3`] +module"] pub type PERFCTR3 = crate::Reg; #[doc = "Bus fabric performance counter 3"] pub mod perfctr3; -#[doc = "PERFSEL3 (rw) register accessor: an alias for `Reg`"] +#[doc = "PERFSEL3 (rw) register accessor: Bus fabric performance event select for PERFCTR3 + +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel3`] +module"] pub type PERFSEL3 = crate::Reg; #[doc = "Bus fabric performance event select for PERFCTR3"] pub mod perfsel3; diff --git a/src/busctrl/bus_priority.rs b/src/busctrl/bus_priority.rs index 7e074e4c8..76b229f15 100644 --- a/src/busctrl/bus_priority.rs +++ b/src/busctrl/bus_priority.rs @@ -1,55 +1,23 @@ #[doc = "Register `BUS_PRIORITY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BUS_PRIORITY` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROC0` reader - 0 - low priority, 1 - high priority"] pub type PROC0_R = crate::BitReader; #[doc = "Field `PROC0` writer - 0 - low priority, 1 - high priority"] -pub type PROC0_W<'a, const O: u8> = crate::BitWriter<'a, BUS_PRIORITY_SPEC, O>; +pub type PROC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC1` reader - 0 - low priority, 1 - high priority"] pub type PROC1_R = crate::BitReader; #[doc = "Field `PROC1` writer - 0 - low priority, 1 - high priority"] -pub type PROC1_W<'a, const O: u8> = crate::BitWriter<'a, BUS_PRIORITY_SPEC, O>; +pub type PROC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_R` reader - 0 - low priority, 1 - high priority"] pub type DMA_R_R = crate::BitReader; #[doc = "Field `DMA_R` writer - 0 - low priority, 1 - high priority"] -pub type DMA_R_W<'a, const O: u8> = crate::BitWriter<'a, BUS_PRIORITY_SPEC, O>; +pub type DMA_R_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_W` reader - 0 - low priority, 1 - high priority"] pub type DMA_W_R = crate::BitReader; #[doc = "Field `DMA_W` writer - 0 - low priority, 1 - high priority"] -pub type DMA_W_W<'a, const O: u8> = crate::BitWriter<'a, BUS_PRIORITY_SPEC, O>; +pub type DMA_W_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - 0 - low priority, 1 - high priority"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0 - 0 - low priority, 1 - high priority"] #[inline(always)] #[must_use] - pub fn proc0(&mut self) -> PROC0_W<0> { + pub fn proc0(&mut self) -> PROC0_W { PROC0_W::new(self) } #[doc = "Bit 4 - 0 - low priority, 1 - high priority"] #[inline(always)] #[must_use] - pub fn proc1(&mut self) -> PROC1_W<4> { + pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self) } #[doc = "Bit 8 - 0 - low priority, 1 - high priority"] #[inline(always)] #[must_use] - pub fn dma_r(&mut self) -> DMA_R_W<8> { + pub fn dma_r(&mut self) -> DMA_R_W { DMA_R_W::new(self) } #[doc = "Bit 12 - 0 - low priority, 1 - high priority"] #[inline(always)] #[must_use] - pub fn dma_w(&mut self) -> DMA_W_W<12> { + pub fn dma_w(&mut self) -> DMA_W_W { DMA_W_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Set the priority of each master for bus arbitration. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [bus_priority](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUS_PRIORITY_SPEC; impl crate::RegisterSpec for BUS_PRIORITY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bus_priority::R](R) reader structure"] -impl crate::Readable for BUS_PRIORITY_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [bus_priority::W](W) writer structure"] +#[doc = "`read()` method returns [`bus_priority::R`](R) reader structure"] +impl crate::Readable for BUS_PRIORITY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_priority::W`](W) writer structure"] impl crate::Writable for BUS_PRIORITY_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/busctrl/bus_priority_ack.rs b/src/busctrl/bus_priority_ack.rs index 7f6adbbef..d796c6152 100644 --- a/src/busctrl/bus_priority_ack.rs +++ b/src/busctrl/bus_priority_ack.rs @@ -1,18 +1,5 @@ #[doc = "Register `BUS_PRIORITY_ACK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BUS_PRIORITY_ACK` reader - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] @@ -28,17 +15,13 @@ impl R { } #[doc = "Bus priority acknowledge -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [bus_priority_ack](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUS_PRIORITY_ACK_SPEC; impl crate::RegisterSpec for BUS_PRIORITY_ACK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bus_priority_ack::R](R) reader structure"] -impl crate::Readable for BUS_PRIORITY_ACK_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`bus_priority_ack::R`](R) reader structure"] +impl crate::Readable for BUS_PRIORITY_ACK_SPEC {} #[doc = "`reset()` method sets BUS_PRIORITY_ACK to value 0"] impl crate::Resettable for BUS_PRIORITY_ACK_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs index 07c8c6897..8a3498e81 100644 --- a/src/busctrl/perfctr0.rs +++ b/src/busctrl/perfctr0.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFCTR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFCTR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFCTR0` reader - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] @@ -41,7 +9,7 @@ pub type PERFCTR0_R = crate::FieldReader; #[doc = "Field `PERFCTR0` writer - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] -pub type PERFCTR0_W<'a, const O: u8> = crate::FieldWriter<'a, PERFCTR0_SPEC, 24, O, u32>; +pub type PERFCTR0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. @@ -57,32 +25,31 @@ impl W { Write any value to clear. Select an event to count using PERFSEL0"] #[inline(always)] #[must_use] - pub fn perfctr0(&mut self) -> PERFCTR0_W<0> { + pub fn perfctr0(&mut self) -> PERFCTR0_W { PERFCTR0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance counter 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfctr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFCTR0_SPEC; impl crate::RegisterSpec for PERFCTR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfctr0::R](R) reader structure"] -impl crate::Readable for PERFCTR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfctr0::W](W) writer structure"] +#[doc = "`read()` method returns [`perfctr0::R`](R) reader structure"] +impl crate::Readable for PERFCTR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr0::W`](W) writer structure"] impl crate::Writable for PERFCTR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs index 1acb3a2cb..5d2f05a52 100644 --- a/src/busctrl/perfctr1.rs +++ b/src/busctrl/perfctr1.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFCTR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFCTR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFCTR1` reader - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] @@ -41,7 +9,7 @@ pub type PERFCTR1_R = crate::FieldReader; #[doc = "Field `PERFCTR1` writer - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] -pub type PERFCTR1_W<'a, const O: u8> = crate::FieldWriter<'a, PERFCTR1_SPEC, 24, O, u32>; +pub type PERFCTR1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. @@ -57,32 +25,31 @@ impl W { Write any value to clear. Select an event to count using PERFSEL1"] #[inline(always)] #[must_use] - pub fn perfctr1(&mut self) -> PERFCTR1_W<0> { + pub fn perfctr1(&mut self) -> PERFCTR1_W { PERFCTR1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance counter 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfctr1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFCTR1_SPEC; impl crate::RegisterSpec for PERFCTR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfctr1::R](R) reader structure"] -impl crate::Readable for PERFCTR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfctr1::W](W) writer structure"] +#[doc = "`read()` method returns [`perfctr1::R`](R) reader structure"] +impl crate::Readable for PERFCTR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr1::W`](W) writer structure"] impl crate::Writable for PERFCTR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs index 00863dcdd..f3a4e6019 100644 --- a/src/busctrl/perfctr2.rs +++ b/src/busctrl/perfctr2.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFCTR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFCTR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFCTR2` reader - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] @@ -41,7 +9,7 @@ pub type PERFCTR2_R = crate::FieldReader; #[doc = "Field `PERFCTR2` writer - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] -pub type PERFCTR2_W<'a, const O: u8> = crate::FieldWriter<'a, PERFCTR2_SPEC, 24, O, u32>; +pub type PERFCTR2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. @@ -57,32 +25,31 @@ impl W { Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] #[must_use] - pub fn perfctr2(&mut self) -> PERFCTR2_W<0> { + pub fn perfctr2(&mut self) -> PERFCTR2_W { PERFCTR2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance counter 2 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfctr2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFCTR2_SPEC; impl crate::RegisterSpec for PERFCTR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfctr2::R](R) reader structure"] -impl crate::Readable for PERFCTR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfctr2::W](W) writer structure"] +#[doc = "`read()` method returns [`perfctr2::R`](R) reader structure"] +impl crate::Readable for PERFCTR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr2::W`](W) writer structure"] impl crate::Writable for PERFCTR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs index d211b56be..06449c12a 100644 --- a/src/busctrl/perfctr3.rs +++ b/src/busctrl/perfctr3.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFCTR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFCTR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFCTR3` reader - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] @@ -41,7 +9,7 @@ pub type PERFCTR3_R = crate::FieldReader; #[doc = "Field `PERFCTR3` writer - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] -pub type PERFCTR3_W<'a, const O: u8> = crate::FieldWriter<'a, PERFCTR3_SPEC, 24, O, u32>; +pub type PERFCTR3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. @@ -57,32 +25,31 @@ impl W { Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] #[must_use] - pub fn perfctr3(&mut self) -> PERFCTR3_W<0> { + pub fn perfctr3(&mut self) -> PERFCTR3_W { PERFCTR3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance counter 3 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfctr3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfctr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFCTR3_SPEC; impl crate::RegisterSpec for PERFCTR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfctr3::R](R) reader structure"] -impl crate::Readable for PERFCTR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfctr3::W](W) writer structure"] +#[doc = "`read()` method returns [`perfctr3::R`](R) reader structure"] +impl crate::Readable for PERFCTR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr3::W`](W) writer structure"] impl crate::Writable for PERFCTR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00ff_ffff; } diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs index d2c905261..d680985a7 100644 --- a/src/busctrl/perfsel0.rs +++ b/src/busctrl/perfsel0.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFSEL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFSEL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub type PERFSEL0_R = crate::FieldReader; #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. @@ -95,7 +63,7 @@ impl crate::FieldSpec for PERFSEL0_A { impl PERFSEL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(PERFSEL0_A::APB_CONTESTED), 1 => Some(PERFSEL0_A::APB), @@ -120,208 +88,212 @@ impl PERFSEL0_R { _ => None, } } - #[doc = "Checks if the value of the field is `APB_CONTESTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_apb_contested(&self) -> bool { *self == PERFSEL0_A::APB_CONTESTED } - #[doc = "Checks if the value of the field is `APB`"] + #[doc = "`1`"] #[inline(always)] pub fn is_apb(&self) -> bool { *self == PERFSEL0_A::APB } - #[doc = "Checks if the value of the field is `FASTPERI_CONTESTED`"] + #[doc = "`10`"] #[inline(always)] pub fn is_fastperi_contested(&self) -> bool { *self == PERFSEL0_A::FASTPERI_CONTESTED } - #[doc = "Checks if the value of the field is `FASTPERI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_fastperi(&self) -> bool { *self == PERFSEL0_A::FASTPERI } - #[doc = "Checks if the value of the field is `SRAM5_CONTESTED`"] + #[doc = "`100`"] #[inline(always)] pub fn is_sram5_contested(&self) -> bool { *self == PERFSEL0_A::SRAM5_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM5`"] + #[doc = "`101`"] #[inline(always)] pub fn is_sram5(&self) -> bool { *self == PERFSEL0_A::SRAM5 } - #[doc = "Checks if the value of the field is `SRAM4_CONTESTED`"] + #[doc = "`110`"] #[inline(always)] pub fn is_sram4_contested(&self) -> bool { *self == PERFSEL0_A::SRAM4_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM4`"] + #[doc = "`111`"] #[inline(always)] pub fn is_sram4(&self) -> bool { *self == PERFSEL0_A::SRAM4 } - #[doc = "Checks if the value of the field is `SRAM3_CONTESTED`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_sram3_contested(&self) -> bool { *self == PERFSEL0_A::SRAM3_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM3`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_sram3(&self) -> bool { *self == PERFSEL0_A::SRAM3 } - #[doc = "Checks if the value of the field is `SRAM2_CONTESTED`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_sram2_contested(&self) -> bool { *self == PERFSEL0_A::SRAM2_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM2`"] + #[doc = "`1011`"] #[inline(always)] pub fn is_sram2(&self) -> bool { *self == PERFSEL0_A::SRAM2 } - #[doc = "Checks if the value of the field is `SRAM1_CONTESTED`"] + #[doc = "`1100`"] #[inline(always)] pub fn is_sram1_contested(&self) -> bool { *self == PERFSEL0_A::SRAM1_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM1`"] + #[doc = "`1101`"] #[inline(always)] pub fn is_sram1(&self) -> bool { *self == PERFSEL0_A::SRAM1 } - #[doc = "Checks if the value of the field is `SRAM0_CONTESTED`"] + #[doc = "`1110`"] #[inline(always)] pub fn is_sram0_contested(&self) -> bool { *self == PERFSEL0_A::SRAM0_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM0`"] + #[doc = "`1111`"] #[inline(always)] pub fn is_sram0(&self) -> bool { *self == PERFSEL0_A::SRAM0 } - #[doc = "Checks if the value of the field is `XIP_MAIN_CONTESTED`"] + #[doc = "`10000`"] #[inline(always)] pub fn is_xip_main_contested(&self) -> bool { *self == PERFSEL0_A::XIP_MAIN_CONTESTED } - #[doc = "Checks if the value of the field is `XIP_MAIN`"] + #[doc = "`10001`"] #[inline(always)] pub fn is_xip_main(&self) -> bool { *self == PERFSEL0_A::XIP_MAIN } - #[doc = "Checks if the value of the field is `ROM_CONTESTED`"] + #[doc = "`10010`"] #[inline(always)] pub fn is_rom_contested(&self) -> bool { *self == PERFSEL0_A::ROM_CONTESTED } - #[doc = "Checks if the value of the field is `ROM`"] + #[doc = "`10011`"] #[inline(always)] pub fn is_rom(&self) -> bool { *self == PERFSEL0_A::ROM } } #[doc = "Field `PERFSEL0` writer - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL0_W<'a, const O: u8> = crate::FieldWriter<'a, PERFSEL0_SPEC, 5, O, PERFSEL0_A>; -impl<'a, const O: u8> PERFSEL0_W<'a, O> { +pub type PERFSEL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, PERFSEL0_A>; +impl<'a, REG, const O: u8> PERFSEL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn apb_contested(self) -> &'a mut W { + pub fn apb_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::APB_CONTESTED) } #[doc = "`1`"] #[inline(always)] - pub fn apb(self) -> &'a mut W { + pub fn apb(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::APB) } #[doc = "`10`"] #[inline(always)] - pub fn fastperi_contested(self) -> &'a mut W { + pub fn fastperi_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::FASTPERI_CONTESTED) } #[doc = "`11`"] #[inline(always)] - pub fn fastperi(self) -> &'a mut W { + pub fn fastperi(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::FASTPERI) } #[doc = "`100`"] #[inline(always)] - pub fn sram5_contested(self) -> &'a mut W { + pub fn sram5_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM5_CONTESTED) } #[doc = "`101`"] #[inline(always)] - pub fn sram5(self) -> &'a mut W { + pub fn sram5(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM5) } #[doc = "`110`"] #[inline(always)] - pub fn sram4_contested(self) -> &'a mut W { + pub fn sram4_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM4_CONTESTED) } #[doc = "`111`"] #[inline(always)] - pub fn sram4(self) -> &'a mut W { + pub fn sram4(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM4) } #[doc = "`1000`"] #[inline(always)] - pub fn sram3_contested(self) -> &'a mut W { + pub fn sram3_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM3_CONTESTED) } #[doc = "`1001`"] #[inline(always)] - pub fn sram3(self) -> &'a mut W { + pub fn sram3(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM3) } #[doc = "`1010`"] #[inline(always)] - pub fn sram2_contested(self) -> &'a mut W { + pub fn sram2_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM2_CONTESTED) } #[doc = "`1011`"] #[inline(always)] - pub fn sram2(self) -> &'a mut W { + pub fn sram2(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM2) } #[doc = "`1100`"] #[inline(always)] - pub fn sram1_contested(self) -> &'a mut W { + pub fn sram1_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM1_CONTESTED) } #[doc = "`1101`"] #[inline(always)] - pub fn sram1(self) -> &'a mut W { + pub fn sram1(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM1) } #[doc = "`1110`"] #[inline(always)] - pub fn sram0_contested(self) -> &'a mut W { + pub fn sram0_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM0_CONTESTED) } #[doc = "`1111`"] #[inline(always)] - pub fn sram0(self) -> &'a mut W { + pub fn sram0(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::SRAM0) } #[doc = "`10000`"] #[inline(always)] - pub fn xip_main_contested(self) -> &'a mut W { + pub fn xip_main_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::XIP_MAIN_CONTESTED) } #[doc = "`10001`"] #[inline(always)] - pub fn xip_main(self) -> &'a mut W { + pub fn xip_main(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::XIP_MAIN) } #[doc = "`10010`"] #[inline(always)] - pub fn rom_contested(self) -> &'a mut W { + pub fn rom_contested(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::ROM_CONTESTED) } #[doc = "`10011`"] #[inline(always)] - pub fn rom(self) -> &'a mut W { + pub fn rom(self) -> &'a mut crate::W { self.variant(PERFSEL0_A::ROM) } } @@ -336,32 +308,31 @@ impl W { #[doc = "Bits 0:4 - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] #[must_use] - pub fn perfsel0(&mut self) -> PERFSEL0_W<0> { + pub fn perfsel0(&mut self) -> PERFSEL0_W { PERFSEL0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance event select for PERFCTR0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfsel0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFSEL0_SPEC; impl crate::RegisterSpec for PERFSEL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfsel0::R](R) reader structure"] -impl crate::Readable for PERFSEL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfsel0::W](W) writer structure"] +#[doc = "`read()` method returns [`perfsel0::R`](R) reader structure"] +impl crate::Readable for PERFSEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel0::W`](W) writer structure"] impl crate::Writable for PERFSEL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs index 5ec9818cb..9599527fb 100644 --- a/src/busctrl/perfsel1.rs +++ b/src/busctrl/perfsel1.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFSEL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFSEL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub type PERFSEL1_R = crate::FieldReader; #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. @@ -95,7 +63,7 @@ impl crate::FieldSpec for PERFSEL1_A { impl PERFSEL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(PERFSEL1_A::APB_CONTESTED), 1 => Some(PERFSEL1_A::APB), @@ -120,208 +88,212 @@ impl PERFSEL1_R { _ => None, } } - #[doc = "Checks if the value of the field is `APB_CONTESTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_apb_contested(&self) -> bool { *self == PERFSEL1_A::APB_CONTESTED } - #[doc = "Checks if the value of the field is `APB`"] + #[doc = "`1`"] #[inline(always)] pub fn is_apb(&self) -> bool { *self == PERFSEL1_A::APB } - #[doc = "Checks if the value of the field is `FASTPERI_CONTESTED`"] + #[doc = "`10`"] #[inline(always)] pub fn is_fastperi_contested(&self) -> bool { *self == PERFSEL1_A::FASTPERI_CONTESTED } - #[doc = "Checks if the value of the field is `FASTPERI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_fastperi(&self) -> bool { *self == PERFSEL1_A::FASTPERI } - #[doc = "Checks if the value of the field is `SRAM5_CONTESTED`"] + #[doc = "`100`"] #[inline(always)] pub fn is_sram5_contested(&self) -> bool { *self == PERFSEL1_A::SRAM5_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM5`"] + #[doc = "`101`"] #[inline(always)] pub fn is_sram5(&self) -> bool { *self == PERFSEL1_A::SRAM5 } - #[doc = "Checks if the value of the field is `SRAM4_CONTESTED`"] + #[doc = "`110`"] #[inline(always)] pub fn is_sram4_contested(&self) -> bool { *self == PERFSEL1_A::SRAM4_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM4`"] + #[doc = "`111`"] #[inline(always)] pub fn is_sram4(&self) -> bool { *self == PERFSEL1_A::SRAM4 } - #[doc = "Checks if the value of the field is `SRAM3_CONTESTED`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_sram3_contested(&self) -> bool { *self == PERFSEL1_A::SRAM3_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM3`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_sram3(&self) -> bool { *self == PERFSEL1_A::SRAM3 } - #[doc = "Checks if the value of the field is `SRAM2_CONTESTED`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_sram2_contested(&self) -> bool { *self == PERFSEL1_A::SRAM2_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM2`"] + #[doc = "`1011`"] #[inline(always)] pub fn is_sram2(&self) -> bool { *self == PERFSEL1_A::SRAM2 } - #[doc = "Checks if the value of the field is `SRAM1_CONTESTED`"] + #[doc = "`1100`"] #[inline(always)] pub fn is_sram1_contested(&self) -> bool { *self == PERFSEL1_A::SRAM1_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM1`"] + #[doc = "`1101`"] #[inline(always)] pub fn is_sram1(&self) -> bool { *self == PERFSEL1_A::SRAM1 } - #[doc = "Checks if the value of the field is `SRAM0_CONTESTED`"] + #[doc = "`1110`"] #[inline(always)] pub fn is_sram0_contested(&self) -> bool { *self == PERFSEL1_A::SRAM0_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM0`"] + #[doc = "`1111`"] #[inline(always)] pub fn is_sram0(&self) -> bool { *self == PERFSEL1_A::SRAM0 } - #[doc = "Checks if the value of the field is `XIP_MAIN_CONTESTED`"] + #[doc = "`10000`"] #[inline(always)] pub fn is_xip_main_contested(&self) -> bool { *self == PERFSEL1_A::XIP_MAIN_CONTESTED } - #[doc = "Checks if the value of the field is `XIP_MAIN`"] + #[doc = "`10001`"] #[inline(always)] pub fn is_xip_main(&self) -> bool { *self == PERFSEL1_A::XIP_MAIN } - #[doc = "Checks if the value of the field is `ROM_CONTESTED`"] + #[doc = "`10010`"] #[inline(always)] pub fn is_rom_contested(&self) -> bool { *self == PERFSEL1_A::ROM_CONTESTED } - #[doc = "Checks if the value of the field is `ROM`"] + #[doc = "`10011`"] #[inline(always)] pub fn is_rom(&self) -> bool { *self == PERFSEL1_A::ROM } } #[doc = "Field `PERFSEL1` writer - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, PERFSEL1_SPEC, 5, O, PERFSEL1_A>; -impl<'a, const O: u8> PERFSEL1_W<'a, O> { +pub type PERFSEL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, PERFSEL1_A>; +impl<'a, REG, const O: u8> PERFSEL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn apb_contested(self) -> &'a mut W { + pub fn apb_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::APB_CONTESTED) } #[doc = "`1`"] #[inline(always)] - pub fn apb(self) -> &'a mut W { + pub fn apb(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::APB) } #[doc = "`10`"] #[inline(always)] - pub fn fastperi_contested(self) -> &'a mut W { + pub fn fastperi_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::FASTPERI_CONTESTED) } #[doc = "`11`"] #[inline(always)] - pub fn fastperi(self) -> &'a mut W { + pub fn fastperi(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::FASTPERI) } #[doc = "`100`"] #[inline(always)] - pub fn sram5_contested(self) -> &'a mut W { + pub fn sram5_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM5_CONTESTED) } #[doc = "`101`"] #[inline(always)] - pub fn sram5(self) -> &'a mut W { + pub fn sram5(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM5) } #[doc = "`110`"] #[inline(always)] - pub fn sram4_contested(self) -> &'a mut W { + pub fn sram4_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM4_CONTESTED) } #[doc = "`111`"] #[inline(always)] - pub fn sram4(self) -> &'a mut W { + pub fn sram4(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM4) } #[doc = "`1000`"] #[inline(always)] - pub fn sram3_contested(self) -> &'a mut W { + pub fn sram3_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM3_CONTESTED) } #[doc = "`1001`"] #[inline(always)] - pub fn sram3(self) -> &'a mut W { + pub fn sram3(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM3) } #[doc = "`1010`"] #[inline(always)] - pub fn sram2_contested(self) -> &'a mut W { + pub fn sram2_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM2_CONTESTED) } #[doc = "`1011`"] #[inline(always)] - pub fn sram2(self) -> &'a mut W { + pub fn sram2(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM2) } #[doc = "`1100`"] #[inline(always)] - pub fn sram1_contested(self) -> &'a mut W { + pub fn sram1_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM1_CONTESTED) } #[doc = "`1101`"] #[inline(always)] - pub fn sram1(self) -> &'a mut W { + pub fn sram1(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM1) } #[doc = "`1110`"] #[inline(always)] - pub fn sram0_contested(self) -> &'a mut W { + pub fn sram0_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM0_CONTESTED) } #[doc = "`1111`"] #[inline(always)] - pub fn sram0(self) -> &'a mut W { + pub fn sram0(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::SRAM0) } #[doc = "`10000`"] #[inline(always)] - pub fn xip_main_contested(self) -> &'a mut W { + pub fn xip_main_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::XIP_MAIN_CONTESTED) } #[doc = "`10001`"] #[inline(always)] - pub fn xip_main(self) -> &'a mut W { + pub fn xip_main(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::XIP_MAIN) } #[doc = "`10010`"] #[inline(always)] - pub fn rom_contested(self) -> &'a mut W { + pub fn rom_contested(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::ROM_CONTESTED) } #[doc = "`10011`"] #[inline(always)] - pub fn rom(self) -> &'a mut W { + pub fn rom(self) -> &'a mut crate::W { self.variant(PERFSEL1_A::ROM) } } @@ -336,32 +308,31 @@ impl W { #[doc = "Bits 0:4 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] #[must_use] - pub fn perfsel1(&mut self) -> PERFSEL1_W<0> { + pub fn perfsel1(&mut self) -> PERFSEL1_W { PERFSEL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance event select for PERFCTR1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfsel1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFSEL1_SPEC; impl crate::RegisterSpec for PERFSEL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfsel1::R](R) reader structure"] -impl crate::Readable for PERFSEL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfsel1::W](W) writer structure"] +#[doc = "`read()` method returns [`perfsel1::R`](R) reader structure"] +impl crate::Readable for PERFSEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel1::W`](W) writer structure"] impl crate::Writable for PERFSEL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs index 165468fe3..559c67bc9 100644 --- a/src/busctrl/perfsel2.rs +++ b/src/busctrl/perfsel2.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFSEL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFSEL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub type PERFSEL2_R = crate::FieldReader; #[doc = "Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. @@ -95,7 +63,7 @@ impl crate::FieldSpec for PERFSEL2_A { impl PERFSEL2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(PERFSEL2_A::APB_CONTESTED), 1 => Some(PERFSEL2_A::APB), @@ -120,208 +88,212 @@ impl PERFSEL2_R { _ => None, } } - #[doc = "Checks if the value of the field is `APB_CONTESTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_apb_contested(&self) -> bool { *self == PERFSEL2_A::APB_CONTESTED } - #[doc = "Checks if the value of the field is `APB`"] + #[doc = "`1`"] #[inline(always)] pub fn is_apb(&self) -> bool { *self == PERFSEL2_A::APB } - #[doc = "Checks if the value of the field is `FASTPERI_CONTESTED`"] + #[doc = "`10`"] #[inline(always)] pub fn is_fastperi_contested(&self) -> bool { *self == PERFSEL2_A::FASTPERI_CONTESTED } - #[doc = "Checks if the value of the field is `FASTPERI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_fastperi(&self) -> bool { *self == PERFSEL2_A::FASTPERI } - #[doc = "Checks if the value of the field is `SRAM5_CONTESTED`"] + #[doc = "`100`"] #[inline(always)] pub fn is_sram5_contested(&self) -> bool { *self == PERFSEL2_A::SRAM5_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM5`"] + #[doc = "`101`"] #[inline(always)] pub fn is_sram5(&self) -> bool { *self == PERFSEL2_A::SRAM5 } - #[doc = "Checks if the value of the field is `SRAM4_CONTESTED`"] + #[doc = "`110`"] #[inline(always)] pub fn is_sram4_contested(&self) -> bool { *self == PERFSEL2_A::SRAM4_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM4`"] + #[doc = "`111`"] #[inline(always)] pub fn is_sram4(&self) -> bool { *self == PERFSEL2_A::SRAM4 } - #[doc = "Checks if the value of the field is `SRAM3_CONTESTED`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_sram3_contested(&self) -> bool { *self == PERFSEL2_A::SRAM3_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM3`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_sram3(&self) -> bool { *self == PERFSEL2_A::SRAM3 } - #[doc = "Checks if the value of the field is `SRAM2_CONTESTED`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_sram2_contested(&self) -> bool { *self == PERFSEL2_A::SRAM2_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM2`"] + #[doc = "`1011`"] #[inline(always)] pub fn is_sram2(&self) -> bool { *self == PERFSEL2_A::SRAM2 } - #[doc = "Checks if the value of the field is `SRAM1_CONTESTED`"] + #[doc = "`1100`"] #[inline(always)] pub fn is_sram1_contested(&self) -> bool { *self == PERFSEL2_A::SRAM1_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM1`"] + #[doc = "`1101`"] #[inline(always)] pub fn is_sram1(&self) -> bool { *self == PERFSEL2_A::SRAM1 } - #[doc = "Checks if the value of the field is `SRAM0_CONTESTED`"] + #[doc = "`1110`"] #[inline(always)] pub fn is_sram0_contested(&self) -> bool { *self == PERFSEL2_A::SRAM0_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM0`"] + #[doc = "`1111`"] #[inline(always)] pub fn is_sram0(&self) -> bool { *self == PERFSEL2_A::SRAM0 } - #[doc = "Checks if the value of the field is `XIP_MAIN_CONTESTED`"] + #[doc = "`10000`"] #[inline(always)] pub fn is_xip_main_contested(&self) -> bool { *self == PERFSEL2_A::XIP_MAIN_CONTESTED } - #[doc = "Checks if the value of the field is `XIP_MAIN`"] + #[doc = "`10001`"] #[inline(always)] pub fn is_xip_main(&self) -> bool { *self == PERFSEL2_A::XIP_MAIN } - #[doc = "Checks if the value of the field is `ROM_CONTESTED`"] + #[doc = "`10010`"] #[inline(always)] pub fn is_rom_contested(&self) -> bool { *self == PERFSEL2_A::ROM_CONTESTED } - #[doc = "Checks if the value of the field is `ROM`"] + #[doc = "`10011`"] #[inline(always)] pub fn is_rom(&self) -> bool { *self == PERFSEL2_A::ROM } } #[doc = "Field `PERFSEL2` writer - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL2_W<'a, const O: u8> = crate::FieldWriter<'a, PERFSEL2_SPEC, 5, O, PERFSEL2_A>; -impl<'a, const O: u8> PERFSEL2_W<'a, O> { +pub type PERFSEL2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, PERFSEL2_A>; +impl<'a, REG, const O: u8> PERFSEL2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn apb_contested(self) -> &'a mut W { + pub fn apb_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::APB_CONTESTED) } #[doc = "`1`"] #[inline(always)] - pub fn apb(self) -> &'a mut W { + pub fn apb(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::APB) } #[doc = "`10`"] #[inline(always)] - pub fn fastperi_contested(self) -> &'a mut W { + pub fn fastperi_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::FASTPERI_CONTESTED) } #[doc = "`11`"] #[inline(always)] - pub fn fastperi(self) -> &'a mut W { + pub fn fastperi(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::FASTPERI) } #[doc = "`100`"] #[inline(always)] - pub fn sram5_contested(self) -> &'a mut W { + pub fn sram5_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM5_CONTESTED) } #[doc = "`101`"] #[inline(always)] - pub fn sram5(self) -> &'a mut W { + pub fn sram5(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM5) } #[doc = "`110`"] #[inline(always)] - pub fn sram4_contested(self) -> &'a mut W { + pub fn sram4_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM4_CONTESTED) } #[doc = "`111`"] #[inline(always)] - pub fn sram4(self) -> &'a mut W { + pub fn sram4(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM4) } #[doc = "`1000`"] #[inline(always)] - pub fn sram3_contested(self) -> &'a mut W { + pub fn sram3_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM3_CONTESTED) } #[doc = "`1001`"] #[inline(always)] - pub fn sram3(self) -> &'a mut W { + pub fn sram3(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM3) } #[doc = "`1010`"] #[inline(always)] - pub fn sram2_contested(self) -> &'a mut W { + pub fn sram2_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM2_CONTESTED) } #[doc = "`1011`"] #[inline(always)] - pub fn sram2(self) -> &'a mut W { + pub fn sram2(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM2) } #[doc = "`1100`"] #[inline(always)] - pub fn sram1_contested(self) -> &'a mut W { + pub fn sram1_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM1_CONTESTED) } #[doc = "`1101`"] #[inline(always)] - pub fn sram1(self) -> &'a mut W { + pub fn sram1(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM1) } #[doc = "`1110`"] #[inline(always)] - pub fn sram0_contested(self) -> &'a mut W { + pub fn sram0_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM0_CONTESTED) } #[doc = "`1111`"] #[inline(always)] - pub fn sram0(self) -> &'a mut W { + pub fn sram0(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::SRAM0) } #[doc = "`10000`"] #[inline(always)] - pub fn xip_main_contested(self) -> &'a mut W { + pub fn xip_main_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::XIP_MAIN_CONTESTED) } #[doc = "`10001`"] #[inline(always)] - pub fn xip_main(self) -> &'a mut W { + pub fn xip_main(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::XIP_MAIN) } #[doc = "`10010`"] #[inline(always)] - pub fn rom_contested(self) -> &'a mut W { + pub fn rom_contested(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::ROM_CONTESTED) } #[doc = "`10011`"] #[inline(always)] - pub fn rom(self) -> &'a mut W { + pub fn rom(self) -> &'a mut crate::W { self.variant(PERFSEL2_A::ROM) } } @@ -336,32 +308,31 @@ impl W { #[doc = "Bits 0:4 - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] #[must_use] - pub fn perfsel2(&mut self) -> PERFSEL2_W<0> { + pub fn perfsel2(&mut self) -> PERFSEL2_W { PERFSEL2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance event select for PERFCTR2 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfsel2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFSEL2_SPEC; impl crate::RegisterSpec for PERFSEL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfsel2::R](R) reader structure"] -impl crate::Readable for PERFSEL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfsel2::W](W) writer structure"] +#[doc = "`read()` method returns [`perfsel2::R`](R) reader structure"] +impl crate::Readable for PERFSEL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel2::W`](W) writer structure"] impl crate::Writable for PERFSEL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs index dac881de8..24c489147 100644 --- a/src/busctrl/perfsel3.rs +++ b/src/busctrl/perfsel3.rs @@ -1,39 +1,7 @@ #[doc = "Register `PERFSEL3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PERFSEL3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub type PERFSEL3_R = crate::FieldReader; #[doc = "Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. @@ -95,7 +63,7 @@ impl crate::FieldSpec for PERFSEL3_A { impl PERFSEL3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(PERFSEL3_A::APB_CONTESTED), 1 => Some(PERFSEL3_A::APB), @@ -120,208 +88,212 @@ impl PERFSEL3_R { _ => None, } } - #[doc = "Checks if the value of the field is `APB_CONTESTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_apb_contested(&self) -> bool { *self == PERFSEL3_A::APB_CONTESTED } - #[doc = "Checks if the value of the field is `APB`"] + #[doc = "`1`"] #[inline(always)] pub fn is_apb(&self) -> bool { *self == PERFSEL3_A::APB } - #[doc = "Checks if the value of the field is `FASTPERI_CONTESTED`"] + #[doc = "`10`"] #[inline(always)] pub fn is_fastperi_contested(&self) -> bool { *self == PERFSEL3_A::FASTPERI_CONTESTED } - #[doc = "Checks if the value of the field is `FASTPERI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_fastperi(&self) -> bool { *self == PERFSEL3_A::FASTPERI } - #[doc = "Checks if the value of the field is `SRAM5_CONTESTED`"] + #[doc = "`100`"] #[inline(always)] pub fn is_sram5_contested(&self) -> bool { *self == PERFSEL3_A::SRAM5_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM5`"] + #[doc = "`101`"] #[inline(always)] pub fn is_sram5(&self) -> bool { *self == PERFSEL3_A::SRAM5 } - #[doc = "Checks if the value of the field is `SRAM4_CONTESTED`"] + #[doc = "`110`"] #[inline(always)] pub fn is_sram4_contested(&self) -> bool { *self == PERFSEL3_A::SRAM4_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM4`"] + #[doc = "`111`"] #[inline(always)] pub fn is_sram4(&self) -> bool { *self == PERFSEL3_A::SRAM4 } - #[doc = "Checks if the value of the field is `SRAM3_CONTESTED`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_sram3_contested(&self) -> bool { *self == PERFSEL3_A::SRAM3_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM3`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_sram3(&self) -> bool { *self == PERFSEL3_A::SRAM3 } - #[doc = "Checks if the value of the field is `SRAM2_CONTESTED`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_sram2_contested(&self) -> bool { *self == PERFSEL3_A::SRAM2_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM2`"] + #[doc = "`1011`"] #[inline(always)] pub fn is_sram2(&self) -> bool { *self == PERFSEL3_A::SRAM2 } - #[doc = "Checks if the value of the field is `SRAM1_CONTESTED`"] + #[doc = "`1100`"] #[inline(always)] pub fn is_sram1_contested(&self) -> bool { *self == PERFSEL3_A::SRAM1_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM1`"] + #[doc = "`1101`"] #[inline(always)] pub fn is_sram1(&self) -> bool { *self == PERFSEL3_A::SRAM1 } - #[doc = "Checks if the value of the field is `SRAM0_CONTESTED`"] + #[doc = "`1110`"] #[inline(always)] pub fn is_sram0_contested(&self) -> bool { *self == PERFSEL3_A::SRAM0_CONTESTED } - #[doc = "Checks if the value of the field is `SRAM0`"] + #[doc = "`1111`"] #[inline(always)] pub fn is_sram0(&self) -> bool { *self == PERFSEL3_A::SRAM0 } - #[doc = "Checks if the value of the field is `XIP_MAIN_CONTESTED`"] + #[doc = "`10000`"] #[inline(always)] pub fn is_xip_main_contested(&self) -> bool { *self == PERFSEL3_A::XIP_MAIN_CONTESTED } - #[doc = "Checks if the value of the field is `XIP_MAIN`"] + #[doc = "`10001`"] #[inline(always)] pub fn is_xip_main(&self) -> bool { *self == PERFSEL3_A::XIP_MAIN } - #[doc = "Checks if the value of the field is `ROM_CONTESTED`"] + #[doc = "`10010`"] #[inline(always)] pub fn is_rom_contested(&self) -> bool { *self == PERFSEL3_A::ROM_CONTESTED } - #[doc = "Checks if the value of the field is `ROM`"] + #[doc = "`10011`"] #[inline(always)] pub fn is_rom(&self) -> bool { *self == PERFSEL3_A::ROM } } #[doc = "Field `PERFSEL3` writer - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL3_W<'a, const O: u8> = crate::FieldWriter<'a, PERFSEL3_SPEC, 5, O, PERFSEL3_A>; -impl<'a, const O: u8> PERFSEL3_W<'a, O> { +pub type PERFSEL3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, PERFSEL3_A>; +impl<'a, REG, const O: u8> PERFSEL3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn apb_contested(self) -> &'a mut W { + pub fn apb_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::APB_CONTESTED) } #[doc = "`1`"] #[inline(always)] - pub fn apb(self) -> &'a mut W { + pub fn apb(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::APB) } #[doc = "`10`"] #[inline(always)] - pub fn fastperi_contested(self) -> &'a mut W { + pub fn fastperi_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::FASTPERI_CONTESTED) } #[doc = "`11`"] #[inline(always)] - pub fn fastperi(self) -> &'a mut W { + pub fn fastperi(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::FASTPERI) } #[doc = "`100`"] #[inline(always)] - pub fn sram5_contested(self) -> &'a mut W { + pub fn sram5_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM5_CONTESTED) } #[doc = "`101`"] #[inline(always)] - pub fn sram5(self) -> &'a mut W { + pub fn sram5(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM5) } #[doc = "`110`"] #[inline(always)] - pub fn sram4_contested(self) -> &'a mut W { + pub fn sram4_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM4_CONTESTED) } #[doc = "`111`"] #[inline(always)] - pub fn sram4(self) -> &'a mut W { + pub fn sram4(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM4) } #[doc = "`1000`"] #[inline(always)] - pub fn sram3_contested(self) -> &'a mut W { + pub fn sram3_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM3_CONTESTED) } #[doc = "`1001`"] #[inline(always)] - pub fn sram3(self) -> &'a mut W { + pub fn sram3(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM3) } #[doc = "`1010`"] #[inline(always)] - pub fn sram2_contested(self) -> &'a mut W { + pub fn sram2_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM2_CONTESTED) } #[doc = "`1011`"] #[inline(always)] - pub fn sram2(self) -> &'a mut W { + pub fn sram2(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM2) } #[doc = "`1100`"] #[inline(always)] - pub fn sram1_contested(self) -> &'a mut W { + pub fn sram1_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM1_CONTESTED) } #[doc = "`1101`"] #[inline(always)] - pub fn sram1(self) -> &'a mut W { + pub fn sram1(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM1) } #[doc = "`1110`"] #[inline(always)] - pub fn sram0_contested(self) -> &'a mut W { + pub fn sram0_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM0_CONTESTED) } #[doc = "`1111`"] #[inline(always)] - pub fn sram0(self) -> &'a mut W { + pub fn sram0(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::SRAM0) } #[doc = "`10000`"] #[inline(always)] - pub fn xip_main_contested(self) -> &'a mut W { + pub fn xip_main_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::XIP_MAIN_CONTESTED) } #[doc = "`10001`"] #[inline(always)] - pub fn xip_main(self) -> &'a mut W { + pub fn xip_main(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::XIP_MAIN) } #[doc = "`10010`"] #[inline(always)] - pub fn rom_contested(self) -> &'a mut W { + pub fn rom_contested(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::ROM_CONTESTED) } #[doc = "`10011`"] #[inline(always)] - pub fn rom(self) -> &'a mut W { + pub fn rom(self) -> &'a mut crate::W { self.variant(PERFSEL3_A::ROM) } } @@ -336,32 +308,31 @@ impl W { #[doc = "Bits 0:4 - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] #[inline(always)] #[must_use] - pub fn perfsel3(&mut self) -> PERFSEL3_W<0> { + pub fn perfsel3(&mut self) -> PERFSEL3_W { PERFSEL3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bus fabric performance event select for PERFCTR3 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [perfsel3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`perfsel3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PERFSEL3_SPEC; impl crate::RegisterSpec for PERFSEL3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [perfsel3::R](R) reader structure"] -impl crate::Readable for PERFSEL3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [perfsel3::W](W) writer structure"] +#[doc = "`read()` method returns [`perfsel3::R`](R) reader structure"] +impl crate::Readable for PERFSEL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel3::W`](W) writer structure"] impl crate::Writable for PERFSEL3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks.rs b/src/clocks.rs index 197759c2d..73780e7ee 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -114,212 +114,470 @@ pub struct RegisterBlock { #[doc = "0xc4 - Interrupt status after masking & forcing"] pub ints: INTS, } -#[doc = "CLK_GPOUT0_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_ctrl`] +module"] pub type CLK_GPOUT0_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_gpout0_ctrl; -#[doc = "CLK_GPOUT0_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_div`] +module"] pub type CLK_GPOUT0_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout0_div; -#[doc = "CLK_GPOUT0_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_selected`] +module"] pub type CLK_GPOUT0_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_gpout0_selected; -#[doc = "CLK_GPOUT1_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_ctrl`] +module"] pub type CLK_GPOUT1_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_gpout1_ctrl; -#[doc = "CLK_GPOUT1_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_div`] +module"] pub type CLK_GPOUT1_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout1_div; -#[doc = "CLK_GPOUT1_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_selected`] +module"] pub type CLK_GPOUT1_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_gpout1_selected; -#[doc = "CLK_GPOUT2_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_ctrl`] +module"] pub type CLK_GPOUT2_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_gpout2_ctrl; -#[doc = "CLK_GPOUT2_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_div`] +module"] pub type CLK_GPOUT2_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout2_div; -#[doc = "CLK_GPOUT2_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_selected`] +module"] pub type CLK_GPOUT2_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_gpout2_selected; -#[doc = "CLK_GPOUT3_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_ctrl`] +module"] pub type CLK_GPOUT3_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_gpout3_ctrl; -#[doc = "CLK_GPOUT3_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_div`] +module"] pub type CLK_GPOUT3_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout3_div; -#[doc = "CLK_GPOUT3_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_selected`] +module"] pub type CLK_GPOUT3_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_gpout3_selected; -#[doc = "CLK_REF_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_ctrl`] +module"] pub type CLK_REF_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_ref_ctrl; -#[doc = "CLK_REF_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_div`] +module"] pub type CLK_REF_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_ref_div; -#[doc = "CLK_REF_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_selected`] +module"] pub type CLK_REF_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] pub mod clk_ref_selected; -#[doc = "CLK_SYS_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_ctrl`] +module"] pub type CLK_SYS_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_sys_ctrl; -#[doc = "CLK_SYS_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_div`] +module"] pub type CLK_SYS_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_sys_div; -#[doc = "CLK_SYS_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_selected`] +module"] pub type CLK_SYS_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] pub mod clk_sys_selected; -#[doc = "CLK_PERI_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_ctrl`] +module"] pub type CLK_PERI_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_peri_ctrl; -#[doc = "CLK_PERI_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_selected`] +module"] pub type CLK_PERI_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_peri_selected; -#[doc = "CLK_USB_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_ctrl`] +module"] pub type CLK_USB_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_usb_ctrl; -#[doc = "CLK_USB_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_div`] +module"] pub type CLK_USB_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_usb_div; -#[doc = "CLK_USB_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_selected`] +module"] pub type CLK_USB_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_usb_selected; -#[doc = "CLK_ADC_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_ctrl`] +module"] pub type CLK_ADC_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_adc_ctrl; -#[doc = "CLK_ADC_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_div`] +module"] pub type CLK_ADC_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_adc_div; -#[doc = "CLK_ADC_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_selected`] +module"] pub type CLK_ADC_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_adc_selected; -#[doc = "CLK_RTC_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_rtc_ctrl`] +module"] pub type CLK_RTC_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_rtc_ctrl; -#[doc = "CLK_RTC_DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_rtc_div`] +module"] pub type CLK_RTC_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_rtc_div; -#[doc = "CLK_RTC_SELECTED (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_rtc_selected`] +module"] pub type CLK_RTC_SELECTED = crate::Reg; #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] pub mod clk_rtc_selected; -#[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor: + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_resus_ctrl`] +module"] pub type CLK_SYS_RESUS_CTRL = crate::Reg; #[doc = ""] pub mod clk_sys_resus_ctrl; -#[doc = "CLK_SYS_RESUS_STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "CLK_SYS_RESUS_STATUS (r) register accessor: + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_resus_status`] +module"] pub type CLK_SYS_RESUS_STATUS = crate::Reg; #[doc = ""] pub mod clk_sys_resus_status; -#[doc = "FC0_REF_KHZ (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_ref_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_ref_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_ref_khz`] +module"] pub type FC0_REF_KHZ = crate::Reg; #[doc = "Reference clock frequency in kHz"] pub mod fc0_ref_khz; -#[doc = "FC0_MIN_KHZ (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_min_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_min_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_min_khz`] +module"] pub type FC0_MIN_KHZ = crate::Reg; #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"] pub mod fc0_min_khz; -#[doc = "FC0_MAX_KHZ (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_max_khz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_max_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_max_khz`] +module"] pub type FC0_MAX_KHZ = crate::Reg; #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] pub mod fc0_max_khz; -#[doc = "FC0_DELAY (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_delay`] +module"] pub type FC0_DELAY = crate::Reg; #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] pub mod fc0_delay; -#[doc = "FC0_INTERVAL (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_interval`] +module"] pub type FC0_INTERVAL = crate::Reg; #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] pub mod fc0_interval; -#[doc = "FC0_SRC (rw) register accessor: an alias for `Reg`"] +#[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_src`] +module"] pub type FC0_SRC = crate::Reg; #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] pub mod fc0_src; -#[doc = "FC0_STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "FC0_STATUS (r) register accessor: Frequency counter status + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_status`] +module"] pub type FC0_STATUS = crate::Reg; #[doc = "Frequency counter status"] pub mod fc0_status; -#[doc = "FC0_RESULT (r) register accessor: an alias for `Reg`"] +#[doc = "FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1 + +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_result`] +module"] pub type FC0_RESULT = crate::Reg; #[doc = "Result of frequency measurement, only valid when status_done=1"] pub mod fc0_result; -#[doc = "WAKE_EN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "WAKE_EN0 (rw) register accessor: enable clock in wake mode + +You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wake_en0`] +module"] pub type WAKE_EN0 = crate::Reg; #[doc = "enable clock in wake mode"] pub mod wake_en0; -#[doc = "WAKE_EN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "WAKE_EN1 (rw) register accessor: enable clock in wake mode + +You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wake_en1`] +module"] pub type WAKE_EN1 = crate::Reg; #[doc = "enable clock in wake mode"] pub mod wake_en1; -#[doc = "SLEEP_EN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SLEEP_EN0 (rw) register accessor: enable clock in sleep mode + +You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sleep_en0`] +module"] pub type SLEEP_EN0 = crate::Reg; #[doc = "enable clock in sleep mode"] pub mod sleep_en0; -#[doc = "SLEEP_EN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SLEEP_EN1 (rw) register accessor: enable clock in sleep mode + +You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sleep_en1`] +module"] pub type SLEEP_EN1 = crate::Reg; #[doc = "enable clock in sleep mode"] pub mod sleep_en1; -#[doc = "ENABLED0 (r) register accessor: an alias for `Reg`"] +#[doc = "ENABLED0 (r) register accessor: indicates the state of the clock enable + +You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@enabled0`] +module"] pub type ENABLED0 = crate::Reg; #[doc = "indicates the state of the clock enable"] pub mod enabled0; -#[doc = "ENABLED1 (r) register accessor: an alias for `Reg`"] +#[doc = "ENABLED1 (r) register accessor: indicates the state of the clock enable + +You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@enabled1`] +module"] pub type ENABLED1 = crate::Reg; #[doc = "indicates the state of the clock enable"] pub mod enabled1; -#[doc = "INTR (r) register accessor: an alias for `Reg`"] +#[doc = "INTR (r) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs index 15621c451..f84e66d3a 100644 --- a/src/clocks/clk_adc_ctrl.rs +++ b/src/clocks/clk_adc_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_ADC_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_ADC_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -67,7 +35,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), @@ -78,91 +46,95 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`11`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`100`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`101`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_ADC_CTRL_SPEC, 3, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`10`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`11`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`100`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`101`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_ADC_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_ADC_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_ADC_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_ADC_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -196,58 +168,57 @@ impl W { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_adc_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_ADC_CTRL_SPEC; impl crate::RegisterSpec for CLK_ADC_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_adc_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_ADC_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_adc_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_adc_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_ADC_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_adc_div.rs b/src/clocks/clk_adc_div.rs index 71a90cd09..3cd4e9fc9 100644 --- a/src/clocks/clk_adc_div.rs +++ b/src/clocks/clk_adc_div.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK_ADC_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_ADC_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_ADC_DIV_SPEC, 2, O>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_adc_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_ADC_DIV_SPEC; impl crate::RegisterSpec for CLK_ADC_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_adc_div::R](R) reader structure"] -impl crate::Readable for CLK_ADC_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_adc_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_adc_div::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_div::W`](W) writer structure"] impl crate::Writable for CLK_ADC_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_adc_selected.rs b/src/clocks/clk_adc_selected.rs index 271547e10..3b40b20f3 100644 --- a/src/clocks/clk_adc_selected.rs +++ b/src/clocks/clk_adc_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_ADC_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_adc_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_ADC_SELECTED_SPEC; impl crate::RegisterSpec for CLK_ADC_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_adc_selected::R](R) reader structure"] -impl crate::Readable for CLK_ADC_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_adc_selected::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_ADC_SELECTED to value 0x01"] impl crate::Resettable for CLK_ADC_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs index 4848c546c..c8459e1bf 100644 --- a/src/clocks/clk_gpout0_ctrl.rs +++ b/src/clocks/clk_gpout0_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_GPOUT0_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT0_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -77,7 +45,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), 1 => Some(AUXSRC_A::CLKSRC_GPIN0), @@ -93,145 +61,149 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`11`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC`"] + #[doc = "`100`"] #[inline(always)] pub fn is_rosc_clksrc(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`101`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == AUXSRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLK_USB`"] + #[doc = "`111`"] #[inline(always)] pub fn is_clk_usb(&self) -> bool { *self == AUXSRC_A::CLK_USB } - #[doc = "Checks if the value of the field is `CLK_ADC`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_clk_adc(&self) -> bool { *self == AUXSRC_A::CLK_ADC } - #[doc = "Checks if the value of the field is `CLK_RTC`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_clk_rtc(&self) -> bool { *self == AUXSRC_A::CLK_RTC } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == AUXSRC_A::CLK_REF } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT0_CTRL_SPEC, 4, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } #[doc = "`11`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`100`"] #[inline(always)] - pub fn rosc_clksrc(self) -> &'a mut W { + pub fn rosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC) } #[doc = "`101`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`110`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_SYS) } #[doc = "`111`"] #[inline(always)] - pub fn clk_usb(self) -> &'a mut W { + pub fn clk_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_USB) } #[doc = "`1000`"] #[inline(always)] - pub fn clk_adc(self) -> &'a mut W { + pub fn clk_adc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_ADC) } #[doc = "`1001`"] #[inline(always)] - pub fn clk_rtc(self) -> &'a mut W { + pub fn clk_rtc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_RTC) } #[doc = "`1010`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_REF) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT0_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT0_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] -pub type DC50_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT0_CTRL_SPEC, O>; +pub type DC50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT0_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT0_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -270,64 +242,63 @@ impl W { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"] #[inline(always)] #[must_use] - pub fn dc50(&mut self) -> DC50_W<12> { + pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout0_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT0_CTRL_SPEC; impl crate::RegisterSpec for CLK_GPOUT0_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout0_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT0_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout0_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout0_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT0_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout0_div.rs b/src/clocks/clk_gpout0_div.rs index de3d3ef2b..a273579cc 100644 --- a/src/clocks/clk_gpout0_div.rs +++ b/src/clocks/clk_gpout0_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_GPOUT0_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT0_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT0_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT0_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout0_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT0_DIV_SPEC; impl crate::RegisterSpec for CLK_GPOUT0_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout0_div::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT0_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout0_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout0_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT0_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout0_selected.rs b/src/clocks/clk_gpout0_selected.rs index 7c8935275..1c7ffb4f3 100644 --- a/src/clocks/clk_gpout0_selected.rs +++ b/src/clocks/clk_gpout0_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_GPOUT0_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout0_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT0_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT0_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout0_selected::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT0_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_gpout0_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_GPOUT0_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT0_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs index 9404464fa..f7de13f01 100644 --- a/src/clocks/clk_gpout1_ctrl.rs +++ b/src/clocks/clk_gpout1_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_GPOUT1_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT1_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -77,7 +45,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), 1 => Some(AUXSRC_A::CLKSRC_GPIN0), @@ -93,145 +61,149 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`11`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC`"] + #[doc = "`100`"] #[inline(always)] pub fn is_rosc_clksrc(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`101`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == AUXSRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLK_USB`"] + #[doc = "`111`"] #[inline(always)] pub fn is_clk_usb(&self) -> bool { *self == AUXSRC_A::CLK_USB } - #[doc = "Checks if the value of the field is `CLK_ADC`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_clk_adc(&self) -> bool { *self == AUXSRC_A::CLK_ADC } - #[doc = "Checks if the value of the field is `CLK_RTC`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_clk_rtc(&self) -> bool { *self == AUXSRC_A::CLK_RTC } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == AUXSRC_A::CLK_REF } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT1_CTRL_SPEC, 4, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } #[doc = "`11`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`100`"] #[inline(always)] - pub fn rosc_clksrc(self) -> &'a mut W { + pub fn rosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC) } #[doc = "`101`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`110`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_SYS) } #[doc = "`111`"] #[inline(always)] - pub fn clk_usb(self) -> &'a mut W { + pub fn clk_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_USB) } #[doc = "`1000`"] #[inline(always)] - pub fn clk_adc(self) -> &'a mut W { + pub fn clk_adc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_ADC) } #[doc = "`1001`"] #[inline(always)] - pub fn clk_rtc(self) -> &'a mut W { + pub fn clk_rtc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_RTC) } #[doc = "`1010`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_REF) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT1_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT1_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] -pub type DC50_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT1_CTRL_SPEC, O>; +pub type DC50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT1_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT1_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -270,64 +242,63 @@ impl W { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"] #[inline(always)] #[must_use] - pub fn dc50(&mut self) -> DC50_W<12> { + pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout1_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT1_CTRL_SPEC; impl crate::RegisterSpec for CLK_GPOUT1_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout1_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT1_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout1_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout1_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT1_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout1_div.rs b/src/clocks/clk_gpout1_div.rs index 4328537ab..c86a8f60c 100644 --- a/src/clocks/clk_gpout1_div.rs +++ b/src/clocks/clk_gpout1_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_GPOUT1_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT1_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT1_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT1_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout1_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT1_DIV_SPEC; impl crate::RegisterSpec for CLK_GPOUT1_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout1_div::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT1_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout1_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout1_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT1_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout1_selected.rs b/src/clocks/clk_gpout1_selected.rs index 323516910..5cc744c65 100644 --- a/src/clocks/clk_gpout1_selected.rs +++ b/src/clocks/clk_gpout1_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_GPOUT1_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout1_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT1_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT1_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout1_selected::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT1_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_gpout1_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_GPOUT1_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT1_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs index 317360b30..1cefdf1fb 100644 --- a/src/clocks/clk_gpout2_ctrl.rs +++ b/src/clocks/clk_gpout2_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_GPOUT2_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT2_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -77,7 +45,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), 1 => Some(AUXSRC_A::CLKSRC_GPIN0), @@ -93,145 +61,149 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`11`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`100`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`101`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == AUXSRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLK_USB`"] + #[doc = "`111`"] #[inline(always)] pub fn is_clk_usb(&self) -> bool { *self == AUXSRC_A::CLK_USB } - #[doc = "Checks if the value of the field is `CLK_ADC`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_clk_adc(&self) -> bool { *self == AUXSRC_A::CLK_ADC } - #[doc = "Checks if the value of the field is `CLK_RTC`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_clk_rtc(&self) -> bool { *self == AUXSRC_A::CLK_RTC } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == AUXSRC_A::CLK_REF } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT2_CTRL_SPEC, 4, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } #[doc = "`11`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`100`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`101`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`110`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_SYS) } #[doc = "`111`"] #[inline(always)] - pub fn clk_usb(self) -> &'a mut W { + pub fn clk_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_USB) } #[doc = "`1000`"] #[inline(always)] - pub fn clk_adc(self) -> &'a mut W { + pub fn clk_adc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_ADC) } #[doc = "`1001`"] #[inline(always)] - pub fn clk_rtc(self) -> &'a mut W { + pub fn clk_rtc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_RTC) } #[doc = "`1010`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_REF) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT2_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT2_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] -pub type DC50_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT2_CTRL_SPEC, O>; +pub type DC50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT2_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT2_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -270,64 +242,63 @@ impl W { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"] #[inline(always)] #[must_use] - pub fn dc50(&mut self) -> DC50_W<12> { + pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout2_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT2_CTRL_SPEC; impl crate::RegisterSpec for CLK_GPOUT2_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout2_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT2_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout2_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout2_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT2_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout2_div.rs b/src/clocks/clk_gpout2_div.rs index d32e54d00..14fbfc77e 100644 --- a/src/clocks/clk_gpout2_div.rs +++ b/src/clocks/clk_gpout2_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_GPOUT2_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT2_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT2_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT2_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout2_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT2_DIV_SPEC; impl crate::RegisterSpec for CLK_GPOUT2_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout2_div::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT2_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout2_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout2_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT2_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout2_selected.rs b/src/clocks/clk_gpout2_selected.rs index b1925018b..eb8c27707 100644 --- a/src/clocks/clk_gpout2_selected.rs +++ b/src/clocks/clk_gpout2_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_GPOUT2_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout2_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT2_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT2_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout2_selected::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT2_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_gpout2_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_GPOUT2_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT2_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs index 7790bacaf..5060d24ab 100644 --- a/src/clocks/clk_gpout3_ctrl.rs +++ b/src/clocks/clk_gpout3_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_GPOUT3_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT3_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -77,7 +45,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), 1 => Some(AUXSRC_A::CLKSRC_GPIN0), @@ -93,145 +61,149 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`11`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`100`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`101`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == AUXSRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLK_USB`"] + #[doc = "`111`"] #[inline(always)] pub fn is_clk_usb(&self) -> bool { *self == AUXSRC_A::CLK_USB } - #[doc = "Checks if the value of the field is `CLK_ADC`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_clk_adc(&self) -> bool { *self == AUXSRC_A::CLK_ADC } - #[doc = "Checks if the value of the field is `CLK_RTC`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_clk_rtc(&self) -> bool { *self == AUXSRC_A::CLK_RTC } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == AUXSRC_A::CLK_REF } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT3_CTRL_SPEC, 4, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } #[doc = "`11`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`100`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`101`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`110`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_SYS) } #[doc = "`111`"] #[inline(always)] - pub fn clk_usb(self) -> &'a mut W { + pub fn clk_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_USB) } #[doc = "`1000`"] #[inline(always)] - pub fn clk_adc(self) -> &'a mut W { + pub fn clk_adc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_ADC) } #[doc = "`1001`"] #[inline(always)] - pub fn clk_rtc(self) -> &'a mut W { + pub fn clk_rtc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_RTC) } #[doc = "`1010`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_REF) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT3_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT3_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] -pub type DC50_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT3_CTRL_SPEC, O>; +pub type DC50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT3_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_GPOUT3_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -270,64 +242,63 @@ impl W { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 12 - Enables duty cycle correction for odd divisors"] #[inline(always)] #[must_use] - pub fn dc50(&mut self) -> DC50_W<12> { + pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout3_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT3_CTRL_SPEC; impl crate::RegisterSpec for CLK_GPOUT3_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout3_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT3_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout3_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout3_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT3_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout3_div.rs b/src/clocks/clk_gpout3_div.rs index 30c5ddd65..9640bbe2b 100644 --- a/src/clocks/clk_gpout3_div.rs +++ b/src/clocks/clk_gpout3_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_GPOUT3_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_GPOUT3_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT3_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_GPOUT3_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout3_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT3_DIV_SPEC; impl crate::RegisterSpec for CLK_GPOUT3_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout3_div::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT3_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_gpout3_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_gpout3_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT3_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_gpout3_selected.rs b/src/clocks/clk_gpout3_selected.rs index 30b1b4bf7..4f4c87053 100644 --- a/src/clocks/clk_gpout3_selected.rs +++ b/src/clocks/clk_gpout3_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_GPOUT3_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_gpout3_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT3_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT3_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_gpout3_selected::R](R) reader structure"] -impl crate::Readable for CLK_GPOUT3_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_gpout3_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_GPOUT3_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT3_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs index cf53c534a..4f8c4a5f5 100644 --- a/src/clocks/clk_peri_ctrl.rs +++ b/src/clocks/clk_peri_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_PERI_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_PERI_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -69,7 +37,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLK_SYS), 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), @@ -81,89 +49,93 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == AUXSRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`11`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`100`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`101`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_PERI_CTRL_SPEC, 3, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLK_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`11`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`100`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`101`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`110`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_PERI_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_PERI_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -185,44 +157,43 @@ impl W { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_peri_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_PERI_CTRL_SPEC; impl crate::RegisterSpec for CLK_PERI_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_peri_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_PERI_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_peri_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_peri_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_PERI_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_peri_selected.rs b/src/clocks/clk_peri_selected.rs index c4fb27754..db3a51301 100644 --- a/src/clocks/clk_peri_selected.rs +++ b/src/clocks/clk_peri_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_PERI_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_peri_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_PERI_SELECTED_SPEC; impl crate::RegisterSpec for CLK_PERI_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_peri_selected::R](R) reader structure"] -impl crate::Readable for CLK_PERI_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_peri_selected::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_PERI_SELECTED to value 0x01"] impl crate::Resettable for CLK_PERI_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs index 1f918e52c..c929566f8 100644 --- a/src/clocks/clk_ref_ctrl.rs +++ b/src/clocks/clk_ref_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_REF_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_REF_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] pub type SRC_R = crate::FieldReader; #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly @@ -61,7 +29,7 @@ impl crate::FieldSpec for SRC_A { impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(SRC_A::ROSC_CLKSRC_PH), 1 => Some(SRC_A::CLKSRC_CLK_REF_AUX), @@ -69,38 +37,42 @@ impl SRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`0`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == SRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `CLKSRC_CLK_REF_AUX`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_clk_ref_aux(&self) -> bool { *self == SRC_A::CLKSRC_CLK_REF_AUX } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`10`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == SRC_A::XOSC_CLKSRC } } #[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"] -pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_REF_CTRL_SPEC, 2, O, SRC_A>; -impl<'a, const O: u8> SRC_W<'a, O> { +pub type SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SRC_A>; +impl<'a, REG, const O: u8> SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(SRC_A::ROSC_CLKSRC_PH) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_clk_ref_aux(self) -> &'a mut W { + pub fn clksrc_clk_ref_aux(self) -> &'a mut crate::W { self.variant(SRC_A::CLKSRC_CLK_REF_AUX) } #[doc = "`10`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(SRC_A::XOSC_CLKSRC) } } @@ -131,7 +103,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), 1 => Some(AUXSRC_A::CLKSRC_GPIN0), @@ -139,38 +111,42 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`10`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_REF_CTRL_SPEC, 2, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`10`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } @@ -190,38 +166,37 @@ impl W { #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"] #[inline(always)] #[must_use] - pub fn src(&mut self) -> SRC_W<0> { + pub fn src(&mut self) -> SRC_W { SRC_W::new(self) } #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_ref_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_REF_CTRL_SPEC; impl crate::RegisterSpec for CLK_REF_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_ref_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_REF_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_ref_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_ref_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_REF_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_REF_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_ref_div.rs b/src/clocks/clk_ref_div.rs index 004507b71..1540fe0e7 100644 --- a/src/clocks/clk_ref_div.rs +++ b/src/clocks/clk_ref_div.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK_REF_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_REF_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_REF_DIV_SPEC, 2, O>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_ref_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_REF_DIV_SPEC; impl crate::RegisterSpec for CLK_REF_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_ref_div::R](R) reader structure"] -impl crate::Readable for CLK_REF_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_ref_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_ref_div::R`](R) reader structure"] +impl crate::Readable for CLK_REF_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_div::W`](W) writer structure"] impl crate::Writable for CLK_REF_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_ref_selected.rs b/src/clocks/clk_ref_selected.rs index d2bf387d9..3cb0a41a7 100644 --- a/src/clocks/clk_ref_selected.rs +++ b/src/clocks/clk_ref_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_REF_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_ref_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_REF_SELECTED_SPEC; impl crate::RegisterSpec for CLK_REF_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_ref_selected::R](R) reader structure"] -impl crate::Readable for CLK_REF_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_ref_selected::R`](R) reader structure"] +impl crate::Readable for CLK_REF_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_REF_SELECTED to value 0x01"] impl crate::Resettable for CLK_REF_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs index ec51e7773..c4775b7bd 100644 --- a/src/clocks/clk_rtc_ctrl.rs +++ b/src/clocks/clk_rtc_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_RTC_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_RTC_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -67,7 +35,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), @@ -78,91 +46,95 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`11`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`100`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`101`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_RTC_CTRL_SPEC, 3, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`10`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`11`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`100`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`101`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_RTC_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_RTC_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_RTC_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_RTC_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -196,58 +168,57 @@ impl W { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_rtc_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_RTC_CTRL_SPEC; impl crate::RegisterSpec for CLK_RTC_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_rtc_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_RTC_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_rtc_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_rtc_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_RTC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_rtc_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_RTC_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_rtc_div.rs b/src/clocks/clk_rtc_div.rs index d6855e7fa..d825909c1 100644 --- a/src/clocks/clk_rtc_div.rs +++ b/src/clocks/clk_rtc_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_RTC_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_RTC_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_RTC_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_RTC_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_rtc_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_RTC_DIV_SPEC; impl crate::RegisterSpec for CLK_RTC_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_rtc_div::R](R) reader structure"] -impl crate::Readable for CLK_RTC_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_rtc_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_rtc_div::R`](R) reader structure"] +impl crate::Readable for CLK_RTC_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_rtc_div::W`](W) writer structure"] impl crate::Writable for CLK_RTC_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_rtc_selected.rs b/src/clocks/clk_rtc_selected.rs index 9ae36baf9..fbf61cccf 100644 --- a/src/clocks/clk_rtc_selected.rs +++ b/src/clocks/clk_rtc_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_RTC_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_rtc_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_RTC_SELECTED_SPEC; impl crate::RegisterSpec for CLK_RTC_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_rtc_selected::R](R) reader structure"] -impl crate::Readable for CLK_RTC_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_rtc_selected::R`](R) reader structure"] +impl crate::Readable for CLK_RTC_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_RTC_SELECTED to value 0x01"] impl crate::Resettable for CLK_RTC_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs index a342bc05f..1e346eb34 100644 --- a/src/clocks/clk_sys_ctrl.rs +++ b/src/clocks/clk_sys_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_SYS_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_SYS_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] pub type SRC_R = crate::BitReader; #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly @@ -55,34 +23,37 @@ impl From for bool { impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SRC_A { + pub const fn variant(&self) -> SRC_A { match self.bits { false => SRC_A::CLK_REF, true => SRC_A::CLKSRC_CLK_SYS_AUX, } } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == SRC_A::CLK_REF } - #[doc = "Checks if the value of the field is `CLKSRC_CLK_SYS_AUX`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_clk_sys_aux(&self) -> bool { *self == SRC_A::CLKSRC_CLK_SYS_AUX } } #[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"] -pub type SRC_W<'a, const O: u8> = crate::BitWriter<'a, CLK_SYS_CTRL_SPEC, O, SRC_A>; -impl<'a, const O: u8> SRC_W<'a, O> { +pub type SRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SRC_A>; +impl<'a, REG, const O: u8> SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(SRC_A::CLK_REF) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_clk_sys_aux(self) -> &'a mut W { + pub fn clksrc_clk_sys_aux(self) -> &'a mut crate::W { self.variant(SRC_A::CLKSRC_CLK_SYS_AUX) } } @@ -119,7 +90,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), 1 => Some(AUXSRC_A::CLKSRC_PLL_USB), @@ -130,68 +101,72 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rosc_clksrc(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`11`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`100`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`101`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SYS_CTRL_SPEC, 3, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`10`"] #[inline(always)] - pub fn rosc_clksrc(self) -> &'a mut W { + pub fn rosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC) } #[doc = "`11`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`100`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`101`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } @@ -211,38 +186,37 @@ impl W { #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"] #[inline(always)] #[must_use] - pub fn src(&mut self) -> SRC_W<0> { + pub fn src(&mut self) -> SRC_W { SRC_W::new(self) } #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_sys_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_CTRL_SPEC; impl crate::RegisterSpec for CLK_SYS_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_sys_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_SYS_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_sys_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_sys_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_SYS_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_sys_div.rs b/src/clocks/clk_sys_div.rs index 52e9b159e..e207652fa 100644 --- a/src/clocks/clk_sys_div.rs +++ b/src/clocks/clk_sys_div.rs @@ -1,47 +1,15 @@ #[doc = "Register `CLK_SYS_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_SYS_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional component of the divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SYS_DIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SYS_DIV_SPEC, 24, O, u32>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:7 - Fractional component of the divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_sys_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_DIV_SPEC; impl crate::RegisterSpec for CLK_SYS_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_sys_div::R](R) reader structure"] -impl crate::Readable for CLK_SYS_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_sys_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_sys_div::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_div::W`](W) writer structure"] impl crate::Writable for CLK_SYS_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs index ad6e87a95..d188424b1 100644 --- a/src/clocks/clk_sys_resus_ctrl.rs +++ b/src/clocks/clk_sys_resus_ctrl.rs @@ -1,57 +1,25 @@ #[doc = "Register `CLK_SYS_RESUS_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_SYS_RESUS_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMEOUT` reader - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] pub type TIMEOUT_R = crate::FieldReader; #[doc = "Field `TIMEOUT` writer - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] -pub type TIMEOUT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SYS_RESUS_CTRL_SPEC, 8, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ENABLE` reader - Enable resus"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable resus"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_SYS_RESUS_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRCE` reader - Force a resus, for test purposes only"] pub type FRCE_R = crate::BitReader; #[doc = "Field `FRCE` writer - Force a resus, for test purposes only"] -pub type FRCE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_SYS_RESUS_CTRL_SPEC, O>; +pub type FRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - For clearing the resus after the fault that triggered it has been corrected"] pub type CLEAR_R = crate::BitReader; #[doc = "Field `CLEAR` writer - For clearing the resus after the fault that triggered it has been corrected"] -pub type CLEAR_W<'a, const O: u8> = crate::BitWriter<'a, CLK_SYS_RESUS_CTRL_SPEC, O>; +pub type CLEAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] @@ -80,50 +48,49 @@ impl W { and must be >= 2x clk_ref_freq/min_clk_tst_freq"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<0> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 8 - Enable resus"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<8> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 12 - Force a resus, for test purposes only"] #[inline(always)] #[must_use] - pub fn frce(&mut self) -> FRCE_W<12> { + pub fn frce(&mut self) -> FRCE_W { FRCE_W::new(self) } #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<16> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = " -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_sys_resus_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_RESUS_CTRL_SPEC; impl crate::RegisterSpec for CLK_SYS_RESUS_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_sys_resus_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_SYS_RESUS_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_sys_resus_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_sys_resus_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_RESUS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_resus_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_SYS_RESUS_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_sys_resus_status.rs b/src/clocks/clk_sys_resus_status.rs index 86dc5f015..109ef2b28 100644 --- a/src/clocks/clk_sys_resus_status.rs +++ b/src/clocks/clk_sys_resus_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_SYS_RESUS_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RESUSSED` reader - Clock has been resuscitated, correct the error then send ctrl_clear=1"] pub type RESUSSED_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = " -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_sys_resus_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_RESUS_STATUS_SPEC; impl crate::RegisterSpec for CLK_SYS_RESUS_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_sys_resus_status::R](R) reader structure"] -impl crate::Readable for CLK_SYS_RESUS_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_sys_resus_status::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_RESUS_STATUS_SPEC {} #[doc = "`reset()` method sets CLK_SYS_RESUS_STATUS to value 0"] impl crate::Resettable for CLK_SYS_RESUS_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/clk_sys_selected.rs b/src/clocks/clk_sys_selected.rs index cc3bff581..c58965846 100644 --- a/src/clocks/clk_sys_selected.rs +++ b/src/clocks/clk_sys_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_SYS_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_sys_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_SELECTED_SPEC; impl crate::RegisterSpec for CLK_SYS_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_sys_selected::R](R) reader structure"] -impl crate::Readable for CLK_SYS_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_sys_selected::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_SYS_SELECTED to value 0x01"] impl crate::Resettable for CLK_SYS_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs index 03df7c847..4f23e9c94 100644 --- a/src/clocks/clk_usb_ctrl.rs +++ b/src/clocks/clk_usb_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK_USB_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_USB_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching @@ -67,7 +35,7 @@ impl crate::FieldSpec for AUXSRC_A { impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), @@ -78,91 +46,95 @@ impl AUXSRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_USB`"] + #[doc = "`0`"] #[inline(always)] pub fn is_clksrc_pll_usb(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_USB } - #[doc = "Checks if the value of the field is `CLKSRC_PLL_SYS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_clksrc_pll_sys(&self) -> bool { *self == AUXSRC_A::CLKSRC_PLL_SYS } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == AUXSRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`11`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == AUXSRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`100`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`101`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == AUXSRC_A::CLKSRC_GPIN1 } } #[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_USB_CTRL_SPEC, 3, O, AUXSRC_A>; -impl<'a, const O: u8> AUXSRC_W<'a, O> { +pub type AUXSRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, AUXSRC_A>; +impl<'a, REG, const O: u8> AUXSRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn clksrc_pll_usb(self) -> &'a mut W { + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_USB) } #[doc = "`1`"] #[inline(always)] - pub fn clksrc_pll_sys(self) -> &'a mut W { + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_PLL_SYS) } #[doc = "`10`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(AUXSRC_A::ROSC_CLKSRC_PH) } #[doc = "`11`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(AUXSRC_A::XOSC_CLKSRC) } #[doc = "`100`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN0) } #[doc = "`101`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(AUXSRC_A::CLKSRC_GPIN1) } } #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Asynchronously kills the clock generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, CLK_USB_CTRL_SPEC, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_USB_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; #[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] -pub type PHASE_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_USB_CTRL_SPEC, 2, O>; +pub type PHASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; #[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] -pub type NUDGE_W<'a, const O: u8> = crate::BitWriter<'a, CLK_USB_CTRL_SPEC, O>; +pub type NUDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] @@ -196,58 +168,57 @@ impl W { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] #[inline(always)] #[must_use] - pub fn auxsrc(&mut self) -> AUXSRC_W<5> { + pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self) } #[doc = "Bit 10 - Asynchronously kills the clock generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<10> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] - pub fn phase(&mut self) -> PHASE_W<16> { + pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self) } #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] - pub fn nudge(&mut self) -> NUDGE_W<20> { + pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_usb_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_USB_CTRL_SPEC; impl crate::RegisterSpec for CLK_USB_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_usb_ctrl::R](R) reader structure"] -impl crate::Readable for CLK_USB_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_usb_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_usb_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_USB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_USB_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_usb_div.rs b/src/clocks/clk_usb_div.rs index 50bb17ab6..ba5ad6eec 100644 --- a/src/clocks/clk_usb_div.rs +++ b/src/clocks/clk_usb_div.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK_USB_DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK_USB_DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_USB_DIV_SPEC, 2, O>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 8:9 - Integer component of the divisor, 0 -> divide by 2^16"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<8> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor, can be changed on-the-fly -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_usb_div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_USB_DIV_SPEC; impl crate::RegisterSpec for CLK_USB_DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_usb_div::R](R) reader structure"] -impl crate::Readable for CLK_USB_DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk_usb_div::W](W) writer structure"] +#[doc = "`read()` method returns [`clk_usb_div::R`](R) reader structure"] +impl crate::Readable for CLK_USB_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_div::W`](W) writer structure"] impl crate::Writable for CLK_USB_DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/clk_usb_selected.rs b/src/clocks/clk_usb_selected.rs index 7b1fb31fe..12dba7f76 100644 --- a/src/clocks/clk_usb_selected.rs +++ b/src/clocks/clk_usb_selected.rs @@ -1,18 +1,5 @@ #[doc = "Register `CLK_USB_SELECTED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clk_usb_selected](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_USB_SELECTED_SPEC; impl crate::RegisterSpec for CLK_USB_SELECTED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk_usb_selected::R](R) reader structure"] -impl crate::Readable for CLK_USB_SELECTED_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clk_usb_selected::R`](R) reader structure"] +impl crate::Readable for CLK_USB_SELECTED_SPEC {} #[doc = "`reset()` method sets CLK_USB_SELECTED to value 0x01"] impl crate::Resettable for CLK_USB_SELECTED_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/clocks/enabled0.rs b/src/clocks/enabled0.rs index 884897919..7f4c98da7 100644 --- a/src/clocks/enabled0.rs +++ b/src/clocks/enabled0.rs @@ -1,18 +1,5 @@ #[doc = "Register `ENABLED0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `clk_sys_clocks` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; #[doc = "Field `clk_adc_adc` reader - "] @@ -241,17 +228,13 @@ impl R { } #[doc = "indicates the state of the clock enable -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [enabled0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLED0_SPEC; impl crate::RegisterSpec for ENABLED0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enabled0::R](R) reader structure"] -impl crate::Readable for ENABLED0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`enabled0::R`](R) reader structure"] +impl crate::Readable for ENABLED0_SPEC {} #[doc = "`reset()` method sets ENABLED0 to value 0"] impl crate::Resettable for ENABLED0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/enabled1.rs b/src/clocks/enabled1.rs index 8b08ef2c3..c00505d59 100644 --- a/src/clocks/enabled1.rs +++ b/src/clocks/enabled1.rs @@ -1,18 +1,5 @@ #[doc = "Register `ENABLED1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `clk_sys_sram4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; #[doc = "Field `clk_sys_sram5` reader - "] @@ -122,17 +109,13 @@ impl R { } #[doc = "indicates the state of the clock enable -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [enabled1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLED1_SPEC; impl crate::RegisterSpec for ENABLED1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enabled1::R](R) reader structure"] -impl crate::Readable for ENABLED1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`enabled1::R`](R) reader structure"] +impl crate::Readable for ENABLED1_SPEC {} #[doc = "`reset()` method sets ENABLED1 to value 0"] impl crate::Resettable for ENABLED1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs index ed8cccc20..2a9c1ba9e 100644 --- a/src/clocks/fc0_delay.rs +++ b/src/clocks/fc0_delay.rs @@ -1,43 +1,11 @@ #[doc = "Register `FC0_DELAY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_DELAY` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_DELAY` reader - "] pub type FC0_DELAY_R = crate::FieldReader; #[doc = "Field `FC0_DELAY` writer - "] -pub type FC0_DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_DELAY_SPEC, 3, O>; +pub type FC0_DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2"] #[inline(always)] @@ -49,33 +17,32 @@ impl W { #[doc = "Bits 0:2"] #[inline(always)] #[must_use] - pub fn fc0_delay(&mut self) -> FC0_DELAY_W<0> { + pub fn fc0_delay(&mut self) -> FC0_DELAY_W { FC0_DELAY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_delay](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_DELAY_SPEC; impl crate::RegisterSpec for FC0_DELAY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_delay::R](R) reader structure"] -impl crate::Readable for FC0_DELAY_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_delay::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_delay::R`](R) reader structure"] +impl crate::Readable for FC0_DELAY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_delay::W`](W) writer structure"] impl crate::Writable for FC0_DELAY_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs index a1af310b3..117ebf904 100644 --- a/src/clocks/fc0_interval.rs +++ b/src/clocks/fc0_interval.rs @@ -1,43 +1,11 @@ #[doc = "Register `FC0_INTERVAL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_INTERVAL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_INTERVAL` reader - "] pub type FC0_INTERVAL_R = crate::FieldReader; #[doc = "Field `FC0_INTERVAL` writer - "] -pub type FC0_INTERVAL_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_INTERVAL_SPEC, 4, O>; +pub type FC0_INTERVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3"] #[inline(always)] @@ -49,33 +17,32 @@ impl W { #[doc = "Bits 0:3"] #[inline(always)] #[must_use] - pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W<0> { + pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W { FC0_INTERVAL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_interval](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_INTERVAL_SPEC; impl crate::RegisterSpec for FC0_INTERVAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_interval::R](R) reader structure"] -impl crate::Readable for FC0_INTERVAL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_interval::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_interval::R`](R) reader structure"] +impl crate::Readable for FC0_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_interval::W`](W) writer structure"] impl crate::Writable for FC0_INTERVAL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_max_khz.rs b/src/clocks/fc0_max_khz.rs index a1d6142b9..1333ad124 100644 --- a/src/clocks/fc0_max_khz.rs +++ b/src/clocks/fc0_max_khz.rs @@ -1,43 +1,11 @@ #[doc = "Register `FC0_MAX_KHZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_MAX_KHZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_MAX_KHZ` reader - "] pub type FC0_MAX_KHZ_R = crate::FieldReader; #[doc = "Field `FC0_MAX_KHZ` writer - "] -pub type FC0_MAX_KHZ_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_MAX_KHZ_SPEC, 25, O, u32>; +pub type FC0_MAX_KHZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 25, O, u32>; impl R { #[doc = "Bits 0:24"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:24"] #[inline(always)] #[must_use] - pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W<0> { + pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W { FC0_MAX_KHZ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_max_khz](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_max_khz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_max_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_MAX_KHZ_SPEC; impl crate::RegisterSpec for FC0_MAX_KHZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_max_khz::R](R) reader structure"] -impl crate::Readable for FC0_MAX_KHZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_max_khz::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_max_khz::R`](R) reader structure"] +impl crate::Readable for FC0_MAX_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_max_khz::W`](W) writer structure"] impl crate::Writable for FC0_MAX_KHZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_min_khz.rs b/src/clocks/fc0_min_khz.rs index 2f13746bf..298ffd16f 100644 --- a/src/clocks/fc0_min_khz.rs +++ b/src/clocks/fc0_min_khz.rs @@ -1,43 +1,11 @@ #[doc = "Register `FC0_MIN_KHZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_MIN_KHZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_MIN_KHZ` reader - "] pub type FC0_MIN_KHZ_R = crate::FieldReader; #[doc = "Field `FC0_MIN_KHZ` writer - "] -pub type FC0_MIN_KHZ_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_MIN_KHZ_SPEC, 25, O, u32>; +pub type FC0_MIN_KHZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 25, O, u32>; impl R { #[doc = "Bits 0:24"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:24"] #[inline(always)] #[must_use] - pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W<0> { + pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W { FC0_MIN_KHZ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_min_khz](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_min_khz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_min_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_MIN_KHZ_SPEC; impl crate::RegisterSpec for FC0_MIN_KHZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_min_khz::R](R) reader structure"] -impl crate::Readable for FC0_MIN_KHZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_min_khz::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_min_khz::R`](R) reader structure"] +impl crate::Readable for FC0_MIN_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_min_khz::W`](W) writer structure"] impl crate::Writable for FC0_MIN_KHZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_ref_khz.rs b/src/clocks/fc0_ref_khz.rs index 7b772ac73..be0377306 100644 --- a/src/clocks/fc0_ref_khz.rs +++ b/src/clocks/fc0_ref_khz.rs @@ -1,43 +1,11 @@ #[doc = "Register `FC0_REF_KHZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_REF_KHZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_REF_KHZ` reader - "] pub type FC0_REF_KHZ_R = crate::FieldReader; #[doc = "Field `FC0_REF_KHZ` writer - "] -pub type FC0_REF_KHZ_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_REF_KHZ_SPEC, 20, O, u32>; +pub type FC0_REF_KHZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; impl R { #[doc = "Bits 0:19"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:19"] #[inline(always)] #[must_use] - pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W<0> { + pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W { FC0_REF_KHZ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Reference clock frequency in kHz -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_ref_khz](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_ref_khz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_ref_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_REF_KHZ_SPEC; impl crate::RegisterSpec for FC0_REF_KHZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_ref_khz::R](R) reader structure"] -impl crate::Readable for FC0_REF_KHZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_ref_khz::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_ref_khz::R`](R) reader structure"] +impl crate::Readable for FC0_REF_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_ref_khz::W`](W) writer structure"] impl crate::Writable for FC0_REF_KHZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_result.rs b/src/clocks/fc0_result.rs index 18886dad7..f930d2684 100644 --- a/src/clocks/fc0_result.rs +++ b/src/clocks/fc0_result.rs @@ -1,18 +1,5 @@ #[doc = "Register `FC0_RESULT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRAC` reader - "] pub type FRAC_R = crate::FieldReader; #[doc = "Field `KHZ` reader - "] @@ -31,17 +18,13 @@ impl R { } #[doc = "Result of frequency measurement, only valid when status_done=1 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_result](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_RESULT_SPEC; impl crate::RegisterSpec for FC0_RESULT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_result::R](R) reader structure"] -impl crate::Readable for FC0_RESULT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fc0_result::R`](R) reader structure"] +impl crate::Readable for FC0_RESULT_SPEC {} #[doc = "`reset()` method sets FC0_RESULT to value 0"] impl crate::Resettable for FC0_RESULT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs index cb30bdc3f..9e0827191 100644 --- a/src/clocks/fc0_src.rs +++ b/src/clocks/fc0_src.rs @@ -1,39 +1,7 @@ #[doc = "Register `FC0_SRC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FC0_SRC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FC0_SRC` reader - "] pub type FC0_SRC_R = crate::FieldReader; #[doc = " @@ -83,7 +51,7 @@ impl crate::FieldSpec for FC0_SRC_A { impl FC0_SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(FC0_SRC_A::NULL), 1 => Some(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY), @@ -102,148 +70,152 @@ impl FC0_SRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `NULL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_null(&self) -> bool { *self == FC0_SRC_A::NULL } - #[doc = "Checks if the value of the field is `PLL_SYS_CLKSRC_PRIMARY`"] + #[doc = "`1`"] #[inline(always)] pub fn is_pll_sys_clksrc_primary(&self) -> bool { *self == FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY } - #[doc = "Checks if the value of the field is `PLL_USB_CLKSRC_PRIMARY`"] + #[doc = "`10`"] #[inline(always)] pub fn is_pll_usb_clksrc_primary(&self) -> bool { *self == FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC`"] + #[doc = "`11`"] #[inline(always)] pub fn is_rosc_clksrc(&self) -> bool { *self == FC0_SRC_A::ROSC_CLKSRC } - #[doc = "Checks if the value of the field is `ROSC_CLKSRC_PH`"] + #[doc = "`100`"] #[inline(always)] pub fn is_rosc_clksrc_ph(&self) -> bool { *self == FC0_SRC_A::ROSC_CLKSRC_PH } - #[doc = "Checks if the value of the field is `XOSC_CLKSRC`"] + #[doc = "`101`"] #[inline(always)] pub fn is_xosc_clksrc(&self) -> bool { *self == FC0_SRC_A::XOSC_CLKSRC } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN0`"] + #[doc = "`110`"] #[inline(always)] pub fn is_clksrc_gpin0(&self) -> bool { *self == FC0_SRC_A::CLKSRC_GPIN0 } - #[doc = "Checks if the value of the field is `CLKSRC_GPIN1`"] + #[doc = "`111`"] #[inline(always)] pub fn is_clksrc_gpin1(&self) -> bool { *self == FC0_SRC_A::CLKSRC_GPIN1 } - #[doc = "Checks if the value of the field is `CLK_REF`"] + #[doc = "`1000`"] #[inline(always)] pub fn is_clk_ref(&self) -> bool { *self == FC0_SRC_A::CLK_REF } - #[doc = "Checks if the value of the field is `CLK_SYS`"] + #[doc = "`1001`"] #[inline(always)] pub fn is_clk_sys(&self) -> bool { *self == FC0_SRC_A::CLK_SYS } - #[doc = "Checks if the value of the field is `CLK_PERI`"] + #[doc = "`1010`"] #[inline(always)] pub fn is_clk_peri(&self) -> bool { *self == FC0_SRC_A::CLK_PERI } - #[doc = "Checks if the value of the field is `CLK_USB`"] + #[doc = "`1011`"] #[inline(always)] pub fn is_clk_usb(&self) -> bool { *self == FC0_SRC_A::CLK_USB } - #[doc = "Checks if the value of the field is `CLK_ADC`"] + #[doc = "`1100`"] #[inline(always)] pub fn is_clk_adc(&self) -> bool { *self == FC0_SRC_A::CLK_ADC } - #[doc = "Checks if the value of the field is `CLK_RTC`"] + #[doc = "`1101`"] #[inline(always)] pub fn is_clk_rtc(&self) -> bool { *self == FC0_SRC_A::CLK_RTC } } #[doc = "Field `FC0_SRC` writer - "] -pub type FC0_SRC_W<'a, const O: u8> = crate::FieldWriter<'a, FC0_SRC_SPEC, 8, O, FC0_SRC_A>; -impl<'a, const O: u8> FC0_SRC_W<'a, O> { +pub type FC0_SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, FC0_SRC_A>; +impl<'a, REG, const O: u8> FC0_SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn null(self) -> &'a mut W { + pub fn null(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::NULL) } #[doc = "`1`"] #[inline(always)] - pub fn pll_sys_clksrc_primary(self) -> &'a mut W { + pub fn pll_sys_clksrc_primary(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY) } #[doc = "`10`"] #[inline(always)] - pub fn pll_usb_clksrc_primary(self) -> &'a mut W { + pub fn pll_usb_clksrc_primary(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY) } #[doc = "`11`"] #[inline(always)] - pub fn rosc_clksrc(self) -> &'a mut W { + pub fn rosc_clksrc(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::ROSC_CLKSRC) } #[doc = "`100`"] #[inline(always)] - pub fn rosc_clksrc_ph(self) -> &'a mut W { + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::ROSC_CLKSRC_PH) } #[doc = "`101`"] #[inline(always)] - pub fn xosc_clksrc(self) -> &'a mut W { + pub fn xosc_clksrc(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::XOSC_CLKSRC) } #[doc = "`110`"] #[inline(always)] - pub fn clksrc_gpin0(self) -> &'a mut W { + pub fn clksrc_gpin0(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLKSRC_GPIN0) } #[doc = "`111`"] #[inline(always)] - pub fn clksrc_gpin1(self) -> &'a mut W { + pub fn clksrc_gpin1(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLKSRC_GPIN1) } #[doc = "`1000`"] #[inline(always)] - pub fn clk_ref(self) -> &'a mut W { + pub fn clk_ref(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_REF) } #[doc = "`1001`"] #[inline(always)] - pub fn clk_sys(self) -> &'a mut W { + pub fn clk_sys(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_SYS) } #[doc = "`1010`"] #[inline(always)] - pub fn clk_peri(self) -> &'a mut W { + pub fn clk_peri(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_PERI) } #[doc = "`1011`"] #[inline(always)] - pub fn clk_usb(self) -> &'a mut W { + pub fn clk_usb(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_USB) } #[doc = "`1100`"] #[inline(always)] - pub fn clk_adc(self) -> &'a mut W { + pub fn clk_adc(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_ADC) } #[doc = "`1101`"] #[inline(always)] - pub fn clk_rtc(self) -> &'a mut W { + pub fn clk_rtc(self) -> &'a mut crate::W { self.variant(FC0_SRC_A::CLK_RTC) } } @@ -258,33 +230,32 @@ impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn fc0_src(&mut self) -> FC0_SRC_W<0> { + pub fn fc0_src(&mut self) -> FC0_SRC_W { FC0_SRC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_src](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_SRC_SPEC; impl crate::RegisterSpec for FC0_SRC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_src::R](R) reader structure"] -impl crate::Readable for FC0_SRC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fc0_src::W](W) writer structure"] +#[doc = "`read()` method returns [`fc0_src::R`](R) reader structure"] +impl crate::Readable for FC0_SRC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_src::W`](W) writer structure"] impl crate::Writable for FC0_SRC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/fc0_status.rs b/src/clocks/fc0_status.rs index c2878f314..dc3b2f8bd 100644 --- a/src/clocks/fc0_status.rs +++ b/src/clocks/fc0_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `FC0_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PASS` reader - Test passed"] pub type PASS_R = crate::BitReader; #[doc = "Field `DONE` reader - Test complete"] @@ -73,17 +60,13 @@ impl R { } #[doc = "Frequency counter status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fc0_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_STATUS_SPEC; impl crate::RegisterSpec for FC0_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fc0_status::R](R) reader structure"] -impl crate::Readable for FC0_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fc0_status::R`](R) reader structure"] +impl crate::Readable for FC0_STATUS_SPEC {} #[doc = "`reset()` method sets FC0_STATUS to value 0"] impl crate::Resettable for FC0_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/inte.rs b/src/clocks/inte.rs index 8e1fa1e44..757634258 100644 --- a/src/clocks/inte.rs +++ b/src/clocks/inte.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; #[doc = "Field `CLK_SYS_RESUS` writer - "] -pub type CLK_SYS_RESUS_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CLK_SYS_RESUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<0> { + pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { CLK_SYS_RESUS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/intf.rs b/src/clocks/intf.rs index 32152d00c..ea5db261c 100644 --- a/src/clocks/intf.rs +++ b/src/clocks/intf.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; #[doc = "Field `CLK_SYS_RESUS` writer - "] -pub type CLK_SYS_RESUS_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CLK_SYS_RESUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<0> { + pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { CLK_SYS_RESUS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/intr.rs b/src/clocks/intr.rs index 23f32fb12..22d2d097f 100644 --- a/src/clocks/intr.rs +++ b/src/clocks/intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/ints.rs b/src/clocks/ints.rs index b4400c008..9d41f3564 100644 --- a/src/clocks/ints.rs +++ b/src/clocks/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs index 02ed16c57..2133efda8 100644 --- a/src/clocks/sleep_en0.rs +++ b/src/clocks/sleep_en0.rs @@ -1,167 +1,135 @@ #[doc = "Register `SLEEP_EN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SLEEP_EN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `clk_sys_clocks` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; #[doc = "Field `clk_sys_clocks` writer - "] -pub type CLK_SYS_CLOCKS_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_CLOCKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_adc_adc` reader - "] pub type CLK_ADC_ADC_R = crate::BitReader; #[doc = "Field `clk_adc_adc` writer - "] -pub type CLK_ADC_ADC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_ADC_ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_adc` reader - "] pub type CLK_SYS_ADC_R = crate::BitReader; #[doc = "Field `clk_sys_adc` writer - "] -pub type CLK_SYS_ADC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_busctrl` reader - "] pub type CLK_SYS_BUSCTRL_R = crate::BitReader; #[doc = "Field `clk_sys_busctrl` writer - "] -pub type CLK_SYS_BUSCTRL_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_BUSCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_busfabric` reader - "] pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; #[doc = "Field `clk_sys_busfabric` writer - "] -pub type CLK_SYS_BUSFABRIC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_BUSFABRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_dma` reader - "] pub type CLK_SYS_DMA_R = crate::BitReader; #[doc = "Field `clk_sys_dma` writer - "] -pub type CLK_SYS_DMA_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_i2c0` reader - "] pub type CLK_SYS_I2C0_R = crate::BitReader; #[doc = "Field `clk_sys_i2c0` writer - "] -pub type CLK_SYS_I2C0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_I2C0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_i2c1` reader - "] pub type CLK_SYS_I2C1_R = crate::BitReader; #[doc = "Field `clk_sys_i2c1` writer - "] -pub type CLK_SYS_I2C1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_I2C1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_io` reader - "] pub type CLK_SYS_IO_R = crate::BitReader; #[doc = "Field `clk_sys_io` writer - "] -pub type CLK_SYS_IO_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_IO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_jtag` reader - "] pub type CLK_SYS_JTAG_R = crate::BitReader; #[doc = "Field `clk_sys_jtag` writer - "] -pub type CLK_SYS_JTAG_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_JTAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader; #[doc = "Field `clk_sys_vreg_and_chip_reset` writer - "] -pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pads` reader - "] pub type CLK_SYS_PADS_R = crate::BitReader; #[doc = "Field `clk_sys_pads` writer - "] -pub type CLK_SYS_PADS_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PADS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pio0` reader - "] pub type CLK_SYS_PIO0_R = crate::BitReader; #[doc = "Field `clk_sys_pio0` writer - "] -pub type CLK_SYS_PIO0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pio1` reader - "] pub type CLK_SYS_PIO1_R = crate::BitReader; #[doc = "Field `clk_sys_pio1` writer - "] -pub type CLK_SYS_PIO1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pll_sys` reader - "] pub type CLK_SYS_PLL_SYS_R = crate::BitReader; #[doc = "Field `clk_sys_pll_sys` writer - "] -pub type CLK_SYS_PLL_SYS_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PLL_SYS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pll_usb` reader - "] pub type CLK_SYS_PLL_USB_R = crate::BitReader; #[doc = "Field `clk_sys_pll_usb` writer - "] -pub type CLK_SYS_PLL_USB_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PLL_USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_psm` reader - "] pub type CLK_SYS_PSM_R = crate::BitReader; #[doc = "Field `clk_sys_psm` writer - "] -pub type CLK_SYS_PSM_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pwm` reader - "] pub type CLK_SYS_PWM_R = crate::BitReader; #[doc = "Field `clk_sys_pwm` writer - "] -pub type CLK_SYS_PWM_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_PWM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_resets` reader - "] pub type CLK_SYS_RESETS_R = crate::BitReader; #[doc = "Field `clk_sys_resets` writer - "] -pub type CLK_SYS_RESETS_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_RESETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rom` reader - "] pub type CLK_SYS_ROM_R = crate::BitReader; #[doc = "Field `clk_sys_rom` writer - "] -pub type CLK_SYS_ROM_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rosc` reader - "] pub type CLK_SYS_ROSC_R = crate::BitReader; #[doc = "Field `clk_sys_rosc` writer - "] -pub type CLK_SYS_ROSC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_ROSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_rtc_rtc` reader - "] pub type CLK_RTC_RTC_R = crate::BitReader; #[doc = "Field `clk_rtc_rtc` writer - "] -pub type CLK_RTC_RTC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_RTC_RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rtc` reader - "] pub type CLK_SYS_RTC_R = crate::BitReader; #[doc = "Field `clk_sys_rtc` writer - "] -pub type CLK_SYS_RTC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sio` reader - "] pub type CLK_SYS_SIO_R = crate::BitReader; #[doc = "Field `clk_sys_sio` writer - "] -pub type CLK_SYS_SIO_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_spi0` reader - "] pub type CLK_PERI_SPI0_R = crate::BitReader; #[doc = "Field `clk_peri_spi0` writer - "] -pub type CLK_PERI_SPI0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_PERI_SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_spi0` reader - "] pub type CLK_SYS_SPI0_R = crate::BitReader; #[doc = "Field `clk_sys_spi0` writer - "] -pub type CLK_SYS_SPI0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_spi1` reader - "] pub type CLK_PERI_SPI1_R = crate::BitReader; #[doc = "Field `clk_peri_spi1` writer - "] -pub type CLK_PERI_SPI1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_PERI_SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_spi1` reader - "] pub type CLK_SYS_SPI1_R = crate::BitReader; #[doc = "Field `clk_sys_spi1` writer - "] -pub type CLK_SYS_SPI1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram0` reader - "] pub type CLK_SYS_SRAM0_R = crate::BitReader; #[doc = "Field `clk_sys_sram0` writer - "] -pub type CLK_SYS_SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram1` reader - "] pub type CLK_SYS_SRAM1_R = crate::BitReader; #[doc = "Field `clk_sys_sram1` writer - "] -pub type CLK_SYS_SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram2` reader - "] pub type CLK_SYS_SRAM2_R = crate::BitReader; #[doc = "Field `clk_sys_sram2` writer - "] -pub type CLK_SYS_SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram3` reader - "] pub type CLK_SYS_SRAM3_R = crate::BitReader; #[doc = "Field `clk_sys_sram3` writer - "] -pub type CLK_SYS_SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN0_SPEC, O>; +pub type CLK_SYS_SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,219 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<0> { + pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W { CLK_SYS_CLOCKS_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W<1> { + pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W { CLK_ADC_ADC_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<2> { + pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W { CLK_SYS_ADC_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<3> { + pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W { CLK_SYS_BUSCTRL_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<4> { + pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W { CLK_SYS_BUSFABRIC_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<5> { + pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W { CLK_SYS_DMA_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<6> { + pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W { CLK_SYS_I2C0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<7> { + pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W { CLK_SYS_I2C1_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<8> { + pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W { CLK_SYS_IO_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<9> { + pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W { CLK_SYS_JTAG_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn clk_sys_vreg_and_chip_reset(&mut self) -> CLK_SYS_VREG_AND_CHIP_RESET_W<10> { + pub fn clk_sys_vreg_and_chip_reset( + &mut self, + ) -> CLK_SYS_VREG_AND_CHIP_RESET_W { CLK_SYS_VREG_AND_CHIP_RESET_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<11> { + pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W { CLK_SYS_PADS_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<12> { + pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W { CLK_SYS_PIO0_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<13> { + pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W { CLK_SYS_PIO1_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<14> { + pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W { CLK_SYS_PLL_SYS_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<15> { + pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W { CLK_SYS_PLL_USB_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<16> { + pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W { CLK_SYS_PSM_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<17> { + pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W { CLK_SYS_PWM_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<18> { + pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W { CLK_SYS_RESETS_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<19> { + pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W { CLK_SYS_ROM_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<20> { + pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W { CLK_SYS_ROSC_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W<21> { + pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W { CLK_RTC_RTC_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W<22> { + pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W { CLK_SYS_RTC_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<23> { + pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W { CLK_SYS_SIO_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<24> { + pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W { CLK_PERI_SPI0_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<25> { + pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W { CLK_SYS_SPI0_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<26> { + pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W { CLK_PERI_SPI1_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<27> { + pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W { CLK_SYS_SPI1_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<28> { + pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W { CLK_SYS_SRAM0_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<29> { + pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W { CLK_SYS_SRAM1_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<30> { + pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W { CLK_SYS_SRAM2_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<31> { + pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { CLK_SYS_SRAM3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "enable clock in sleep mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sleep_en0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLEEP_EN0_SPEC; impl crate::RegisterSpec for SLEEP_EN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sleep_en0::R](R) reader structure"] -impl crate::Readable for SLEEP_EN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sleep_en0::W](W) writer structure"] +#[doc = "`read()` method returns [`sleep_en0::R`](R) reader structure"] +impl crate::Readable for SLEEP_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_en0::W`](W) writer structure"] impl crate::Writable for SLEEP_EN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs index 8f0bda115..0c7c405ca 100644 --- a/src/clocks/sleep_en1.rs +++ b/src/clocks/sleep_en1.rs @@ -1,99 +1,67 @@ #[doc = "Register `SLEEP_EN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SLEEP_EN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `clk_sys_sram4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; #[doc = "Field `clk_sys_sram4` writer - "] -pub type CLK_SYS_SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram5` reader - "] pub type CLK_SYS_SRAM5_R = crate::BitReader; #[doc = "Field `clk_sys_sram5` writer - "] -pub type CLK_SYS_SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_syscfg` reader - "] pub type CLK_SYS_SYSCFG_R = crate::BitReader; #[doc = "Field `clk_sys_syscfg` writer - "] -pub type CLK_SYS_SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_SYSCFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sysinfo` reader - "] pub type CLK_SYS_SYSINFO_R = crate::BitReader; #[doc = "Field `clk_sys_sysinfo` writer - "] -pub type CLK_SYS_SYSINFO_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_SYSINFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_tbman` reader - "] pub type CLK_SYS_TBMAN_R = crate::BitReader; #[doc = "Field `clk_sys_tbman` writer - "] -pub type CLK_SYS_TBMAN_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_TBMAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_timer` reader - "] pub type CLK_SYS_TIMER_R = crate::BitReader; #[doc = "Field `clk_sys_timer` writer - "] -pub type CLK_SYS_TIMER_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_uart0` reader - "] pub type CLK_PERI_UART0_R = crate::BitReader; #[doc = "Field `clk_peri_uart0` writer - "] -pub type CLK_PERI_UART0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_PERI_UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_uart0` reader - "] pub type CLK_SYS_UART0_R = crate::BitReader; #[doc = "Field `clk_sys_uart0` writer - "] -pub type CLK_SYS_UART0_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_uart1` reader - "] pub type CLK_PERI_UART1_R = crate::BitReader; #[doc = "Field `clk_peri_uart1` writer - "] -pub type CLK_PERI_UART1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_PERI_UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_uart1` reader - "] pub type CLK_SYS_UART1_R = crate::BitReader; #[doc = "Field `clk_sys_uart1` writer - "] -pub type CLK_SYS_UART1_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_usbctrl` reader - "] pub type CLK_SYS_USBCTRL_R = crate::BitReader; #[doc = "Field `clk_sys_usbctrl` writer - "] -pub type CLK_SYS_USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_usb_usbctrl` reader - "] pub type CLK_USB_USBCTRL_R = crate::BitReader; #[doc = "Field `clk_usb_usbctrl` writer - "] -pub type CLK_USB_USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_USB_USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_watchdog` reader - "] pub type CLK_SYS_WATCHDOG_R = crate::BitReader; #[doc = "Field `clk_sys_watchdog` writer - "] -pub type CLK_SYS_WATCHDOG_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_WATCHDOG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_xip` reader - "] pub type CLK_SYS_XIP_R = crate::BitReader; #[doc = "Field `clk_sys_xip` writer - "] -pub type CLK_SYS_XIP_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_XIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_xosc` reader - "] pub type CLK_SYS_XOSC_R = crate::BitReader; #[doc = "Field `clk_sys_xosc` writer - "] -pub type CLK_SYS_XOSC_W<'a, const O: u8> = crate::BitWriter<'a, SLEEP_EN1_SPEC, O>; +pub type CLK_SYS_XOSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -175,116 +143,115 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<0> { + pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W { CLK_SYS_SRAM4_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<1> { + pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W { CLK_SYS_SRAM5_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<2> { + pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W { CLK_SYS_SYSCFG_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<3> { + pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W { CLK_SYS_SYSINFO_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<4> { + pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W { CLK_SYS_TBMAN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W<5> { + pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W { CLK_SYS_TIMER_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<6> { + pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W { CLK_PERI_UART0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<7> { + pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W { CLK_SYS_UART0_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<8> { + pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W { CLK_PERI_UART1_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<9> { + pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W { CLK_SYS_UART1_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<10> { + pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W { CLK_SYS_USBCTRL_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W<11> { + pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W { CLK_USB_USBCTRL_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<12> { + pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W { CLK_SYS_WATCHDOG_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<13> { + pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W { CLK_SYS_XIP_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<14> { + pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { CLK_SYS_XOSC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "enable clock in sleep mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sleep_en1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLEEP_EN1_SPEC; impl crate::RegisterSpec for SLEEP_EN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sleep_en1::R](R) reader structure"] -impl crate::Readable for SLEEP_EN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sleep_en1::W](W) writer structure"] +#[doc = "`read()` method returns [`sleep_en1::R`](R) reader structure"] +impl crate::Readable for SLEEP_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_en1::W`](W) writer structure"] impl crate::Writable for SLEEP_EN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs index b88b898cd..5c7119321 100644 --- a/src/clocks/wake_en0.rs +++ b/src/clocks/wake_en0.rs @@ -1,167 +1,135 @@ #[doc = "Register `WAKE_EN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WAKE_EN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `clk_sys_clocks` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; #[doc = "Field `clk_sys_clocks` writer - "] -pub type CLK_SYS_CLOCKS_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_CLOCKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_adc_adc` reader - "] pub type CLK_ADC_ADC_R = crate::BitReader; #[doc = "Field `clk_adc_adc` writer - "] -pub type CLK_ADC_ADC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_ADC_ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_adc` reader - "] pub type CLK_SYS_ADC_R = crate::BitReader; #[doc = "Field `clk_sys_adc` writer - "] -pub type CLK_SYS_ADC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_busctrl` reader - "] pub type CLK_SYS_BUSCTRL_R = crate::BitReader; #[doc = "Field `clk_sys_busctrl` writer - "] -pub type CLK_SYS_BUSCTRL_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_BUSCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_busfabric` reader - "] pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; #[doc = "Field `clk_sys_busfabric` writer - "] -pub type CLK_SYS_BUSFABRIC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_BUSFABRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_dma` reader - "] pub type CLK_SYS_DMA_R = crate::BitReader; #[doc = "Field `clk_sys_dma` writer - "] -pub type CLK_SYS_DMA_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_i2c0` reader - "] pub type CLK_SYS_I2C0_R = crate::BitReader; #[doc = "Field `clk_sys_i2c0` writer - "] -pub type CLK_SYS_I2C0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_I2C0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_i2c1` reader - "] pub type CLK_SYS_I2C1_R = crate::BitReader; #[doc = "Field `clk_sys_i2c1` writer - "] -pub type CLK_SYS_I2C1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_I2C1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_io` reader - "] pub type CLK_SYS_IO_R = crate::BitReader; #[doc = "Field `clk_sys_io` writer - "] -pub type CLK_SYS_IO_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_IO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_jtag` reader - "] pub type CLK_SYS_JTAG_R = crate::BitReader; #[doc = "Field `clk_sys_jtag` writer - "] -pub type CLK_SYS_JTAG_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_JTAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader; #[doc = "Field `clk_sys_vreg_and_chip_reset` writer - "] -pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pads` reader - "] pub type CLK_SYS_PADS_R = crate::BitReader; #[doc = "Field `clk_sys_pads` writer - "] -pub type CLK_SYS_PADS_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PADS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pio0` reader - "] pub type CLK_SYS_PIO0_R = crate::BitReader; #[doc = "Field `clk_sys_pio0` writer - "] -pub type CLK_SYS_PIO0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pio1` reader - "] pub type CLK_SYS_PIO1_R = crate::BitReader; #[doc = "Field `clk_sys_pio1` writer - "] -pub type CLK_SYS_PIO1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pll_sys` reader - "] pub type CLK_SYS_PLL_SYS_R = crate::BitReader; #[doc = "Field `clk_sys_pll_sys` writer - "] -pub type CLK_SYS_PLL_SYS_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PLL_SYS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pll_usb` reader - "] pub type CLK_SYS_PLL_USB_R = crate::BitReader; #[doc = "Field `clk_sys_pll_usb` writer - "] -pub type CLK_SYS_PLL_USB_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PLL_USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_psm` reader - "] pub type CLK_SYS_PSM_R = crate::BitReader; #[doc = "Field `clk_sys_psm` writer - "] -pub type CLK_SYS_PSM_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_pwm` reader - "] pub type CLK_SYS_PWM_R = crate::BitReader; #[doc = "Field `clk_sys_pwm` writer - "] -pub type CLK_SYS_PWM_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_PWM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_resets` reader - "] pub type CLK_SYS_RESETS_R = crate::BitReader; #[doc = "Field `clk_sys_resets` writer - "] -pub type CLK_SYS_RESETS_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_RESETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rom` reader - "] pub type CLK_SYS_ROM_R = crate::BitReader; #[doc = "Field `clk_sys_rom` writer - "] -pub type CLK_SYS_ROM_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rosc` reader - "] pub type CLK_SYS_ROSC_R = crate::BitReader; #[doc = "Field `clk_sys_rosc` writer - "] -pub type CLK_SYS_ROSC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_ROSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_rtc_rtc` reader - "] pub type CLK_RTC_RTC_R = crate::BitReader; #[doc = "Field `clk_rtc_rtc` writer - "] -pub type CLK_RTC_RTC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_RTC_RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_rtc` reader - "] pub type CLK_SYS_RTC_R = crate::BitReader; #[doc = "Field `clk_sys_rtc` writer - "] -pub type CLK_SYS_RTC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sio` reader - "] pub type CLK_SYS_SIO_R = crate::BitReader; #[doc = "Field `clk_sys_sio` writer - "] -pub type CLK_SYS_SIO_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_spi0` reader - "] pub type CLK_PERI_SPI0_R = crate::BitReader; #[doc = "Field `clk_peri_spi0` writer - "] -pub type CLK_PERI_SPI0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_PERI_SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_spi0` reader - "] pub type CLK_SYS_SPI0_R = crate::BitReader; #[doc = "Field `clk_sys_spi0` writer - "] -pub type CLK_SYS_SPI0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_spi1` reader - "] pub type CLK_PERI_SPI1_R = crate::BitReader; #[doc = "Field `clk_peri_spi1` writer - "] -pub type CLK_PERI_SPI1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_PERI_SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_spi1` reader - "] pub type CLK_SYS_SPI1_R = crate::BitReader; #[doc = "Field `clk_sys_spi1` writer - "] -pub type CLK_SYS_SPI1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram0` reader - "] pub type CLK_SYS_SRAM0_R = crate::BitReader; #[doc = "Field `clk_sys_sram0` writer - "] -pub type CLK_SYS_SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram1` reader - "] pub type CLK_SYS_SRAM1_R = crate::BitReader; #[doc = "Field `clk_sys_sram1` writer - "] -pub type CLK_SYS_SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram2` reader - "] pub type CLK_SYS_SRAM2_R = crate::BitReader; #[doc = "Field `clk_sys_sram2` writer - "] -pub type CLK_SYS_SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram3` reader - "] pub type CLK_SYS_SRAM3_R = crate::BitReader; #[doc = "Field `clk_sys_sram3` writer - "] -pub type CLK_SYS_SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN0_SPEC, O>; +pub type CLK_SYS_SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,219 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<0> { + pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W { CLK_SYS_CLOCKS_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W<1> { + pub fn clk_adc_adc(&mut self) -> CLK_ADC_ADC_W { CLK_ADC_ADC_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<2> { + pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W { CLK_SYS_ADC_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<3> { + pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W { CLK_SYS_BUSCTRL_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<4> { + pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W { CLK_SYS_BUSFABRIC_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<5> { + pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W { CLK_SYS_DMA_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<6> { + pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W { CLK_SYS_I2C0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<7> { + pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W { CLK_SYS_I2C1_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<8> { + pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W { CLK_SYS_IO_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<9> { + pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W { CLK_SYS_JTAG_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn clk_sys_vreg_and_chip_reset(&mut self) -> CLK_SYS_VREG_AND_CHIP_RESET_W<10> { + pub fn clk_sys_vreg_and_chip_reset( + &mut self, + ) -> CLK_SYS_VREG_AND_CHIP_RESET_W { CLK_SYS_VREG_AND_CHIP_RESET_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<11> { + pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W { CLK_SYS_PADS_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<12> { + pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W { CLK_SYS_PIO0_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<13> { + pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W { CLK_SYS_PIO1_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<14> { + pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W { CLK_SYS_PLL_SYS_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<15> { + pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W { CLK_SYS_PLL_USB_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<16> { + pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W { CLK_SYS_PSM_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<17> { + pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W { CLK_SYS_PWM_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<18> { + pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W { CLK_SYS_RESETS_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<19> { + pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W { CLK_SYS_ROM_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<20> { + pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W { CLK_SYS_ROSC_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W<21> { + pub fn clk_rtc_rtc(&mut self) -> CLK_RTC_RTC_W { CLK_RTC_RTC_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W<22> { + pub fn clk_sys_rtc(&mut self) -> CLK_SYS_RTC_W { CLK_SYS_RTC_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<23> { + pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W { CLK_SYS_SIO_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<24> { + pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W { CLK_PERI_SPI0_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<25> { + pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W { CLK_SYS_SPI0_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<26> { + pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W { CLK_PERI_SPI1_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<27> { + pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W { CLK_SYS_SPI1_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<28> { + pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W { CLK_SYS_SRAM0_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<29> { + pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W { CLK_SYS_SRAM1_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<30> { + pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W { CLK_SYS_SRAM2_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<31> { + pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { CLK_SYS_SRAM3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "enable clock in wake mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [wake_en0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WAKE_EN0_SPEC; impl crate::RegisterSpec for WAKE_EN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wake_en0::R](R) reader structure"] -impl crate::Readable for WAKE_EN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wake_en0::W](W) writer structure"] +#[doc = "`read()` method returns [`wake_en0::R`](R) reader structure"] +impl crate::Readable for WAKE_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wake_en0::W`](W) writer structure"] impl crate::Writable for WAKE_EN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs index da55b926b..8210e8ec0 100644 --- a/src/clocks/wake_en1.rs +++ b/src/clocks/wake_en1.rs @@ -1,99 +1,67 @@ #[doc = "Register `WAKE_EN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WAKE_EN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `clk_sys_sram4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; #[doc = "Field `clk_sys_sram4` writer - "] -pub type CLK_SYS_SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sram5` reader - "] pub type CLK_SYS_SRAM5_R = crate::BitReader; #[doc = "Field `clk_sys_sram5` writer - "] -pub type CLK_SYS_SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_syscfg` reader - "] pub type CLK_SYS_SYSCFG_R = crate::BitReader; #[doc = "Field `clk_sys_syscfg` writer - "] -pub type CLK_SYS_SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_SYSCFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_sysinfo` reader - "] pub type CLK_SYS_SYSINFO_R = crate::BitReader; #[doc = "Field `clk_sys_sysinfo` writer - "] -pub type CLK_SYS_SYSINFO_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_SYSINFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_tbman` reader - "] pub type CLK_SYS_TBMAN_R = crate::BitReader; #[doc = "Field `clk_sys_tbman` writer - "] -pub type CLK_SYS_TBMAN_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_TBMAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_timer` reader - "] pub type CLK_SYS_TIMER_R = crate::BitReader; #[doc = "Field `clk_sys_timer` writer - "] -pub type CLK_SYS_TIMER_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_uart0` reader - "] pub type CLK_PERI_UART0_R = crate::BitReader; #[doc = "Field `clk_peri_uart0` writer - "] -pub type CLK_PERI_UART0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_PERI_UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_uart0` reader - "] pub type CLK_SYS_UART0_R = crate::BitReader; #[doc = "Field `clk_sys_uart0` writer - "] -pub type CLK_SYS_UART0_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_peri_uart1` reader - "] pub type CLK_PERI_UART1_R = crate::BitReader; #[doc = "Field `clk_peri_uart1` writer - "] -pub type CLK_PERI_UART1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_PERI_UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_uart1` reader - "] pub type CLK_SYS_UART1_R = crate::BitReader; #[doc = "Field `clk_sys_uart1` writer - "] -pub type CLK_SYS_UART1_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_usbctrl` reader - "] pub type CLK_SYS_USBCTRL_R = crate::BitReader; #[doc = "Field `clk_sys_usbctrl` writer - "] -pub type CLK_SYS_USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_usb_usbctrl` reader - "] pub type CLK_USB_USBCTRL_R = crate::BitReader; #[doc = "Field `clk_usb_usbctrl` writer - "] -pub type CLK_USB_USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_USB_USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_watchdog` reader - "] pub type CLK_SYS_WATCHDOG_R = crate::BitReader; #[doc = "Field `clk_sys_watchdog` writer - "] -pub type CLK_SYS_WATCHDOG_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_WATCHDOG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_xip` reader - "] pub type CLK_SYS_XIP_R = crate::BitReader; #[doc = "Field `clk_sys_xip` writer - "] -pub type CLK_SYS_XIP_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_XIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clk_sys_xosc` reader - "] pub type CLK_SYS_XOSC_R = crate::BitReader; #[doc = "Field `clk_sys_xosc` writer - "] -pub type CLK_SYS_XOSC_W<'a, const O: u8> = crate::BitWriter<'a, WAKE_EN1_SPEC, O>; +pub type CLK_SYS_XOSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -175,116 +143,115 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<0> { + pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W { CLK_SYS_SRAM4_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<1> { + pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W { CLK_SYS_SRAM5_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<2> { + pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W { CLK_SYS_SYSCFG_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<3> { + pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W { CLK_SYS_SYSINFO_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<4> { + pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W { CLK_SYS_TBMAN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W<5> { + pub fn clk_sys_timer(&mut self) -> CLK_SYS_TIMER_W { CLK_SYS_TIMER_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<6> { + pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W { CLK_PERI_UART0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<7> { + pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W { CLK_SYS_UART0_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<8> { + pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W { CLK_PERI_UART1_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<9> { + pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W { CLK_SYS_UART1_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<10> { + pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W { CLK_SYS_USBCTRL_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W<11> { + pub fn clk_usb_usbctrl(&mut self) -> CLK_USB_USBCTRL_W { CLK_USB_USBCTRL_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<12> { + pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W { CLK_SYS_WATCHDOG_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<13> { + pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W { CLK_SYS_XIP_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<14> { + pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { CLK_SYS_XOSC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "enable clock in wake mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [wake_en1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WAKE_EN1_SPEC; impl crate::RegisterSpec for WAKE_EN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wake_en1::R](R) reader structure"] -impl crate::Readable for WAKE_EN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wake_en1::W](W) writer structure"] +#[doc = "`read()` method returns [`wake_en1::R`](R) reader structure"] +impl crate::Readable for WAKE_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wake_en1::W`](W) writer structure"] impl crate::Writable for WAKE_EN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma.rs b/src/dma.rs index 38bf5e96c..d3ed88865 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -111,172 +111,382 @@ pub use self::ch::CH; #[doc = r"Cluster"] #[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] pub mod ch; -#[doc = "INTR (rw) register accessor: an alias for `Reg`"] +#[doc = "INTR (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Interrupt Status (raw)"] pub mod intr; -#[doc = "INTE0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE0 (rw) register accessor: Interrupt Enables for IRQ 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`inte0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte0`] +module"] pub type INTE0 = crate::Reg; #[doc = "Interrupt Enables for IRQ 0"] pub mod inte0; -#[doc = "INTF0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF0 (rw) register accessor: Force Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf0`] +module"] pub type INTF0 = crate::Reg; #[doc = "Force Interrupts"] pub mod intf0; -#[doc = "INTS0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTS0 (rw) register accessor: Interrupt Status for IRQ 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`ints0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints0`] +module"] pub type INTS0 = crate::Reg; #[doc = "Interrupt Status for IRQ 0"] pub mod ints0; -#[doc = "INTE1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE1 (rw) register accessor: Interrupt Enables for IRQ 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte1`] +module"] pub type INTE1 = crate::Reg; #[doc = "Interrupt Enables for IRQ 1"] pub mod inte1; -#[doc = "INTF1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF1 (rw) register accessor: Force Interrupts for IRQ 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`intf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf1`] +module"] pub type INTF1 = crate::Reg; #[doc = "Force Interrupts for IRQ 1"] pub mod intf1; -#[doc = "INTS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTS1 (rw) register accessor: Interrupt Status (masked) for IRQ 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`ints1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints1`] +module"] pub type INTS1 = crate::Reg; #[doc = "Interrupt Status (masked) for IRQ 1"] pub mod ints1; -#[doc = "TIMER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer0`] +module"] pub type TIMER0 = crate::Reg; #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer0; -#[doc = "TIMER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer1`] +module"] pub type TIMER1 = crate::Reg; #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer1; -#[doc = "TIMER2 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer2`] +module"] pub type TIMER2 = crate::Reg; #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer2; -#[doc = "TIMER3 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer3`] +module"] pub type TIMER3 = crate::Reg; #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer3; -#[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: an alias for `Reg`"] +#[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously + +You can [`read`](crate::generic::Reg::read) this register and get [`multi_chan_trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`multi_chan_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@multi_chan_trigger`] +module"] pub type MULTI_CHAN_TRIGGER = crate::Reg; #[doc = "Trigger one or more channels simultaneously"] pub mod multi_chan_trigger; -#[doc = "SNIFF_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "SNIFF_CTRL (rw) register accessor: Sniffer Control + +You can [`read`](crate::generic::Reg::read) this register and get [`sniff_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sniff_ctrl`] +module"] pub type SNIFF_CTRL = crate::Reg; #[doc = "Sniffer Control"] pub mod sniff_ctrl; -#[doc = "SNIFF_DATA (rw) register accessor: an alias for `Reg`"] +#[doc = "SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + +You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sniff_data`] +module"] pub type SNIFF_DATA = crate::Reg; #[doc = "Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] pub mod sniff_data; -#[doc = "FIFO_LEVELS (r) register accessor: an alias for `Reg`"] +#[doc = "FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels + +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_levels`] +module"] pub type FIFO_LEVELS = crate::Reg; #[doc = "Debug RAF, WAF, TDF levels"] pub mod fifo_levels; -#[doc = "CHAN_ABORT (rw) register accessor: an alias for `Reg`"] +#[doc = "CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels + +You can [`read`](crate::generic::Reg::read) this register and get [`chan_abort::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chan_abort`] +module"] pub type CHAN_ABORT = crate::Reg; #[doc = "Abort an in-progress transfer sequence on one or more channels"] pub mod chan_abort; -#[doc = "N_CHANNELS (r) register accessor: an alias for `Reg`"] +#[doc = "N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + +You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@n_channels`] +module"] pub type N_CHANNELS = crate::Reg; #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] pub mod n_channels; -#[doc = "CH0_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch0_dbg_ctdreq`] +module"] pub type CH0_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch0_dbg_ctdreq; -#[doc = "CH0_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch0_dbg_tcr`] +module"] pub type CH0_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch0_dbg_tcr; -#[doc = "CH1_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch1_dbg_ctdreq`] +module"] pub type CH1_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch1_dbg_ctdreq; -#[doc = "CH1_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch1_dbg_tcr`] +module"] pub type CH1_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch1_dbg_tcr; -#[doc = "CH2_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch2_dbg_ctdreq`] +module"] pub type CH2_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch2_dbg_ctdreq; -#[doc = "CH2_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch2_dbg_tcr`] +module"] pub type CH2_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch2_dbg_tcr; -#[doc = "CH3_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch3_dbg_ctdreq`] +module"] pub type CH3_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch3_dbg_ctdreq; -#[doc = "CH3_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch3_dbg_tcr`] +module"] pub type CH3_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch3_dbg_tcr; -#[doc = "CH4_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch4_dbg_ctdreq`] +module"] pub type CH4_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch4_dbg_ctdreq; -#[doc = "CH4_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch4_dbg_tcr`] +module"] pub type CH4_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch4_dbg_tcr; -#[doc = "CH5_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch5_dbg_ctdreq`] +module"] pub type CH5_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch5_dbg_ctdreq; -#[doc = "CH5_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch5_dbg_tcr`] +module"] pub type CH5_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch5_dbg_tcr; -#[doc = "CH6_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch6_dbg_ctdreq`] +module"] pub type CH6_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch6_dbg_ctdreq; -#[doc = "CH6_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch6_dbg_tcr`] +module"] pub type CH6_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch6_dbg_tcr; -#[doc = "CH7_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch7_dbg_ctdreq`] +module"] pub type CH7_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch7_dbg_ctdreq; -#[doc = "CH7_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch7_dbg_tcr`] +module"] pub type CH7_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch7_dbg_tcr; -#[doc = "CH8_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch8_dbg_ctdreq`] +module"] pub type CH8_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch8_dbg_ctdreq; -#[doc = "CH8_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch8_dbg_tcr`] +module"] pub type CH8_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch8_dbg_tcr; -#[doc = "CH9_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch9_dbg_ctdreq`] +module"] pub type CH9_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch9_dbg_ctdreq; -#[doc = "CH9_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch9_dbg_tcr`] +module"] pub type CH9_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch9_dbg_tcr; -#[doc = "CH10_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch10_dbg_ctdreq`] +module"] pub type CH10_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch10_dbg_ctdreq; -#[doc = "CH10_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch10_dbg_tcr`] +module"] pub type CH10_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch10_dbg_tcr; -#[doc = "CH11_DBG_CTDREQ (rw) register accessor: an alias for `Reg`"] +#[doc = "CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_ctdreq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch11_dbg_ctdreq`] +module"] pub type CH11_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch11_dbg_ctdreq; -#[doc = "CH11_DBG_TCR (r) register accessor: an alias for `Reg`"] +#[doc = "CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch11_dbg_tcr`] +module"] pub type CH11_DBG_TCR = crate::Reg; #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] pub mod ch11_dbg_tcr; diff --git a/src/dma/ch.rs b/src/dma/ch.rs index afb9ea84f..afddf8b9e 100644 --- a/src/dma/ch.rs +++ b/src/dma/ch.rs @@ -49,17 +49,41 @@ pub struct CH { reload the channel counter and start the channel."] pub ch_al3_read_addr_trig: CH_AL3_READ_ADDR_TRIG, } -#[doc = "CH_READ_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_read_addr`] +module"] pub type CH_READ_ADDR = crate::Reg; #[doc = "DMA Channel 0 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] pub mod ch_read_addr; -#[doc = "CH_WRITE_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_write_addr`] +module"] pub type CH_WRITE_ADDR = crate::Reg; #[doc = "DMA Channel 0 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] pub mod ch_write_addr; -#[doc = "CH_TRANS_COUNT (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_trans_count`] +module"] pub type CH_TRANS_COUNT = crate::Reg; #[doc = "DMA Channel 0 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). @@ -70,60 +94,131 @@ pub type CH_TRANS_COUNT = crate::Reg; The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] pub mod ch_trans_count; -#[doc = "CH_CTRL_TRIG (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_ctrl_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_ctrl_trig`] +module"] pub type CH_CTRL_TRIG = crate::Reg; #[doc = "DMA Channel 0 Control and Status"] pub mod ch_ctrl_trig; -#[doc = "CH_AL1_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_ctrl`] +module"] pub type CH_AL1_CTRL = crate::Reg; #[doc = "DMA Channel 0 Control and Status"] pub mod ch_al1_ctrl; -#[doc = "CH_AL1_READ_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_read_addr`] +module"] pub type CH_AL1_READ_ADDR = crate::Reg; #[doc = "Alias for channel 0 READ_ADDR register"] pub mod ch_al1_read_addr; -#[doc = "CH_AL1_WRITE_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_write_addr`] +module"] pub type CH_AL1_WRITE_ADDR = crate::Reg; #[doc = "Alias for channel 0 WRITE_ADDR register"] pub mod ch_al1_write_addr; -#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_trans_count_trig`] +module"] pub type CH_AL1_TRANS_COUNT_TRIG = crate::Reg; #[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] pub mod ch_al1_trans_count_trig; -#[doc = "CH_AL2_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_ctrl`] +module"] pub type CH_AL2_CTRL = crate::Reg; #[doc = "DMA Channel 0 Control and Status"] pub mod ch_al2_ctrl; -#[doc = "CH_AL2_TRANS_COUNT (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_trans_count`] +module"] pub type CH_AL2_TRANS_COUNT = crate::Reg; #[doc = "Alias for channel 0 TRANS_COUNT register"] pub mod ch_al2_trans_count; -#[doc = "CH_AL2_READ_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_read_addr`] +module"] pub type CH_AL2_READ_ADDR = crate::Reg; #[doc = "Alias for channel 0 READ_ADDR register"] pub mod ch_al2_read_addr; -#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_write_addr_trig`] +module"] pub type CH_AL2_WRITE_ADDR_TRIG = crate::Reg; #[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] pub mod ch_al2_write_addr_trig; -#[doc = "CH_AL3_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_ctrl`] +module"] pub type CH_AL3_CTRL = crate::Reg; #[doc = "DMA Channel 0 Control and Status"] pub mod ch_al3_ctrl; -#[doc = "CH_AL3_WRITE_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_write_addr`] +module"] pub type CH_AL3_WRITE_ADDR = crate::Reg; #[doc = "Alias for channel 0 WRITE_ADDR register"] pub mod ch_al3_write_addr; -#[doc = "CH_AL3_TRANS_COUNT (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_trans_count`] +module"] pub type CH_AL3_TRANS_COUNT = crate::Reg; #[doc = "Alias for channel 0 TRANS_COUNT register"] pub mod ch_al3_trans_count; -#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: an alias for `Reg`"] +#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_read_addr_trig`] +module"] pub type CH_AL3_READ_ADDR_TRIG = crate::Reg; #[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs index a0ecf4e60..f226eff8e 100644 --- a/src/dma/ch/ch_al1_ctrl.rs +++ b/src/dma/ch/ch_al1_ctrl.rs @@ -1,45 +1,13 @@ #[doc = "Register `CH_AL1_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL1_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] @@ -47,7 +15,7 @@ pub type HIGH_PRIORITY_R = crate::BitReader; #[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] -pub type HIGH_PRIORITY_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type HIGH_PRIORITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -75,7 +43,7 @@ impl crate::FieldSpec for DATA_SIZE_A { impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DATA_SIZE_A::SIZE_BYTE), 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), @@ -83,38 +51,42 @@ impl DATA_SIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SIZE_BYTE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_size_byte(&self) -> bool { *self == DATA_SIZE_A::SIZE_BYTE } - #[doc = "Checks if the value of the field is `SIZE_HALFWORD`"] + #[doc = "`1`"] #[inline(always)] pub fn is_size_halfword(&self) -> bool { *self == DATA_SIZE_A::SIZE_HALFWORD } - #[doc = "Checks if the value of the field is `SIZE_WORD`"] + #[doc = "`10`"] #[inline(always)] pub fn is_size_word(&self) -> bool { *self == DATA_SIZE_A::SIZE_WORD } } #[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL1_CTRL_SPEC, 2, O, DATA_SIZE_A>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DATA_SIZE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn size_byte(self) -> &'a mut W { + pub fn size_byte(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_BYTE) } #[doc = "`1`"] #[inline(always)] - pub fn size_halfword(self) -> &'a mut W { + pub fn size_halfword(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_HALFWORD) } #[doc = "`10`"] #[inline(always)] - pub fn size_word(self) -> &'a mut W { + pub fn size_word(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_WORD) } } @@ -125,7 +97,7 @@ pub type INCR_READ_R = crate::BitReader; #[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] -pub type INCR_READ_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type INCR_READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] @@ -133,7 +105,7 @@ pub type INCR_WRITE_R = crate::BitReader; #[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] -pub type INCR_WRITE_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type INCR_WRITE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] @@ -161,13 +133,13 @@ impl crate::FieldSpec for RING_SIZE_A { impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(RING_SIZE_A::RING_NONE), _ => None, } } - #[doc = "Checks if the value of the field is `RING_NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_ring_none(&self) -> bool { *self == RING_SIZE_A::RING_NONE @@ -176,11 +148,15 @@ impl RING_SIZE_R { #[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL1_CTRL_SPEC, 4, O, RING_SIZE_A>; -impl<'a, const O: u8> RING_SIZE_W<'a, O> { +pub type RING_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, RING_SIZE_A>; +impl<'a, REG, const O: u8> RING_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn ring_none(self) -> &'a mut W { + pub fn ring_none(self) -> &'a mut crate::W { self.variant(RING_SIZE_A::RING_NONE) } } @@ -189,13 +165,13 @@ impl<'a, const O: u8> RING_SIZE_W<'a, O> { pub type RING_SEL_R = crate::BitReader; #[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] -pub type RING_SEL_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type RING_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] -pub type CHAIN_TO_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL1_CTRL_SPEC, 4, O>; +pub type CHAIN_TO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] @@ -311,7 +287,7 @@ impl crate::FieldSpec for TREQ_SEL_A { impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TREQ_SEL_A::PIO0_TX0), 1 => Some(TREQ_SEL_A::PIO0_TX1), @@ -361,227 +337,227 @@ impl TREQ_SEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `PIO0_TX0`"] + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX0 } - #[doc = "Checks if the value of the field is `PIO0_TX1`"] + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX1 } - #[doc = "Checks if the value of the field is `PIO0_TX2`"] + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX2 } - #[doc = "Checks if the value of the field is `PIO0_TX3`"] + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX3 } - #[doc = "Checks if the value of the field is `PIO0_RX0`"] + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX0 } - #[doc = "Checks if the value of the field is `PIO0_RX1`"] + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX1 } - #[doc = "Checks if the value of the field is `PIO0_RX2`"] + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX2 } - #[doc = "Checks if the value of the field is `PIO0_RX3`"] + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX3 } - #[doc = "Checks if the value of the field is `PIO1_TX0`"] + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX0 } - #[doc = "Checks if the value of the field is `PIO1_TX1`"] + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX1 } - #[doc = "Checks if the value of the field is `PIO1_TX2`"] + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX2 } - #[doc = "Checks if the value of the field is `PIO1_TX3`"] + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX3 } - #[doc = "Checks if the value of the field is `PIO1_RX0`"] + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX0 } - #[doc = "Checks if the value of the field is `PIO1_RX1`"] + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX1 } - #[doc = "Checks if the value of the field is `PIO1_RX2`"] + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX2 } - #[doc = "Checks if the value of the field is `PIO1_RX3`"] + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX3 } - #[doc = "Checks if the value of the field is `SPI0_TX`"] + #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_tx(&self) -> bool { *self == TREQ_SEL_A::SPI0_TX } - #[doc = "Checks if the value of the field is `SPI0_RX`"] + #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_rx(&self) -> bool { *self == TREQ_SEL_A::SPI0_RX } - #[doc = "Checks if the value of the field is `SPI1_TX`"] + #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_tx(&self) -> bool { *self == TREQ_SEL_A::SPI1_TX } - #[doc = "Checks if the value of the field is `SPI1_RX`"] + #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_rx(&self) -> bool { *self == TREQ_SEL_A::SPI1_RX } - #[doc = "Checks if the value of the field is `UART0_TX`"] + #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_tx(&self) -> bool { *self == TREQ_SEL_A::UART0_TX } - #[doc = "Checks if the value of the field is `UART0_RX`"] + #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_rx(&self) -> bool { *self == TREQ_SEL_A::UART0_RX } - #[doc = "Checks if the value of the field is `UART1_TX`"] + #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_tx(&self) -> bool { *self == TREQ_SEL_A::UART1_TX } - #[doc = "Checks if the value of the field is `UART1_RX`"] + #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_rx(&self) -> bool { *self == TREQ_SEL_A::UART1_RX } - #[doc = "Checks if the value of the field is `PWM_WRAP0`"] + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap0(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP0 } - #[doc = "Checks if the value of the field is `PWM_WRAP1`"] + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap1(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP1 } - #[doc = "Checks if the value of the field is `PWM_WRAP2`"] + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap2(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP2 } - #[doc = "Checks if the value of the field is `PWM_WRAP3`"] + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap3(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP3 } - #[doc = "Checks if the value of the field is `PWM_WRAP4`"] + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap4(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP4 } - #[doc = "Checks if the value of the field is `PWM_WRAP5`"] + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap5(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP5 } - #[doc = "Checks if the value of the field is `PWM_WRAP6`"] + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap6(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP6 } - #[doc = "Checks if the value of the field is `PWM_WRAP7`"] + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap7(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP7 } - #[doc = "Checks if the value of the field is `I2C0_TX`"] + #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_tx(&self) -> bool { *self == TREQ_SEL_A::I2C0_TX } - #[doc = "Checks if the value of the field is `I2C0_RX`"] + #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_rx(&self) -> bool { *self == TREQ_SEL_A::I2C0_RX } - #[doc = "Checks if the value of the field is `I2C1_TX`"] + #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_tx(&self) -> bool { *self == TREQ_SEL_A::I2C1_TX } - #[doc = "Checks if the value of the field is `I2C1_RX`"] + #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_rx(&self) -> bool { *self == TREQ_SEL_A::I2C1_RX } - #[doc = "Checks if the value of the field is `ADC`"] + #[doc = "Select the ADC as TREQ"] #[inline(always)] pub fn is_adc(&self) -> bool { *self == TREQ_SEL_A::ADC } - #[doc = "Checks if the value of the field is `XIP_STREAM`"] + #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] pub fn is_xip_stream(&self) -> bool { *self == TREQ_SEL_A::XIP_STREAM } - #[doc = "Checks if the value of the field is `XIP_SSITX`"] + #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssitx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSITX } - #[doc = "Checks if the value of the field is `XIP_SSIRX`"] + #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssirx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSIRX } - #[doc = "Checks if the value of the field is `TIMER0`"] + #[doc = "Select Timer 0 as TREQ"] #[inline(always)] pub fn is_timer0(&self) -> bool { *self == TREQ_SEL_A::TIMER0 } - #[doc = "Checks if the value of the field is `TIMER1`"] + #[doc = "Select Timer 1 as TREQ"] #[inline(always)] pub fn is_timer1(&self) -> bool { *self == TREQ_SEL_A::TIMER1 } - #[doc = "Checks if the value of the field is `TIMER2`"] + #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] pub fn is_timer2(&self) -> bool { *self == TREQ_SEL_A::TIMER2 } - #[doc = "Checks if the value of the field is `TIMER3`"] + #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] pub fn is_timer3(&self) -> bool { *self == TREQ_SEL_A::TIMER3 } - #[doc = "Checks if the value of the field is `PERMANENT`"] + #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] pub fn is_permanent(&self) -> bool { *self == TREQ_SEL_A::PERMANENT @@ -590,231 +566,235 @@ impl TREQ_SEL_R { #[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL1_CTRL_SPEC, 6, O, TREQ_SEL_A>; -impl<'a, const O: u8> TREQ_SEL_W<'a, O> { +pub type TREQ_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O, TREQ_SEL_A>; +impl<'a, REG, const O: u8> TREQ_SEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_tx0(self) -> &'a mut W { + pub fn pio0_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX0) } #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_tx1(self) -> &'a mut W { + pub fn pio0_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX1) } #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_tx2(self) -> &'a mut W { + pub fn pio0_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX2) } #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_tx3(self) -> &'a mut W { + pub fn pio0_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX3) } #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_rx0(self) -> &'a mut W { + pub fn pio0_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX0) } #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_rx1(self) -> &'a mut W { + pub fn pio0_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX1) } #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_rx2(self) -> &'a mut W { + pub fn pio0_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX2) } #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_rx3(self) -> &'a mut W { + pub fn pio0_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX3) } #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_tx0(self) -> &'a mut W { + pub fn pio1_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX0) } #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_tx1(self) -> &'a mut W { + pub fn pio1_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX1) } #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_tx2(self) -> &'a mut W { + pub fn pio1_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX2) } #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_tx3(self) -> &'a mut W { + pub fn pio1_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX3) } #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_rx0(self) -> &'a mut W { + pub fn pio1_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX0) } #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_rx1(self) -> &'a mut W { + pub fn pio1_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX1) } #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_rx2(self) -> &'a mut W { + pub fn pio1_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX2) } #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_rx3(self) -> &'a mut W { + pub fn pio1_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX3) } #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] - pub fn spi0_tx(self) -> &'a mut W { + pub fn spi0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_TX) } #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] - pub fn spi0_rx(self) -> &'a mut W { + pub fn spi0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_RX) } #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] - pub fn spi1_tx(self) -> &'a mut W { + pub fn spi1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_TX) } #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] - pub fn spi1_rx(self) -> &'a mut W { + pub fn spi1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_RX) } #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] - pub fn uart0_tx(self) -> &'a mut W { + pub fn uart0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_TX) } #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] - pub fn uart0_rx(self) -> &'a mut W { + pub fn uart0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_RX) } #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] - pub fn uart1_tx(self) -> &'a mut W { + pub fn uart1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_TX) } #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] - pub fn uart1_rx(self) -> &'a mut W { + pub fn uart1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_RX) } #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap0(self) -> &'a mut W { + pub fn pwm_wrap0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP0) } #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap1(self) -> &'a mut W { + pub fn pwm_wrap1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP1) } #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap2(self) -> &'a mut W { + pub fn pwm_wrap2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP2) } #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap3(self) -> &'a mut W { + pub fn pwm_wrap3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP3) } #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap4(self) -> &'a mut W { + pub fn pwm_wrap4(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP4) } #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap5(self) -> &'a mut W { + pub fn pwm_wrap5(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP5) } #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap6(self) -> &'a mut W { + pub fn pwm_wrap6(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP6) } #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap7(self) -> &'a mut W { + pub fn pwm_wrap7(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP7) } #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_tx(self) -> &'a mut W { + pub fn i2c0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_TX) } #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_rx(self) -> &'a mut W { + pub fn i2c0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_RX) } #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_tx(self) -> &'a mut W { + pub fn i2c1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_TX) } #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_rx(self) -> &'a mut W { + pub fn i2c1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_RX) } #[doc = "Select the ADC as TREQ"] #[inline(always)] - pub fn adc(self) -> &'a mut W { + pub fn adc(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::ADC) } #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] - pub fn xip_stream(self) -> &'a mut W { + pub fn xip_stream(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_STREAM) } #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssitx(self) -> &'a mut W { + pub fn xip_ssitx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSITX) } #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssirx(self) -> &'a mut W { + pub fn xip_ssirx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSIRX) } #[doc = "Select Timer 0 as TREQ"] #[inline(always)] - pub fn timer0(self) -> &'a mut W { + pub fn timer0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER0) } #[doc = "Select Timer 1 as TREQ"] #[inline(always)] - pub fn timer1(self) -> &'a mut W { + pub fn timer1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER1) } #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] - pub fn timer2(self) -> &'a mut W { + pub fn timer2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER2) } #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] - pub fn timer3(self) -> &'a mut W { + pub fn timer3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER3) } #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] - pub fn permanent(self) -> &'a mut W { + pub fn permanent(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PERMANENT) } } @@ -825,13 +805,13 @@ pub type IRQ_QUIET_R = crate::BitReader; #[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] -pub type IRQ_QUIET_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type IRQ_QUIET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; #[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] -pub type BSWAP_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type BSWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] @@ -839,7 +819,7 @@ pub type SNIFF_EN_R = crate::BitReader; #[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] -pub type SNIFF_EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL1_CTRL_SPEC, O>; +pub type SNIFF_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] @@ -849,13 +829,13 @@ pub type BUSY_R = crate::BitReader; pub type WRITE_ERROR_R = crate::BitReader; #[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] -pub type WRITE_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL1_CTRL_SPEC, O>; +pub type WRITE_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; #[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] -pub type READ_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL1_CTRL_SPEC, O>; +pub type READ_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { @@ -967,7 +947,7 @@ impl W { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. @@ -975,13 +955,13 @@ impl W { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] - pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<1> { + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W::new(self) } #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<2> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. @@ -989,7 +969,7 @@ impl W { Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] - pub fn incr_read(&mut self) -> INCR_READ_W<4> { + pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self) } #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. @@ -997,7 +977,7 @@ impl W { Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] - pub fn incr_write(&mut self) -> INCR_WRITE_W<5> { + pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self) } #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. @@ -1005,21 +985,21 @@ impl W { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] - pub fn ring_size(&mut self) -> RING_SIZE_W<6> { + pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self) } #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] - pub fn ring_sel(&mut self) -> RING_SEL_W<10> { + pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W::new(self) } #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] #[inline(always)] #[must_use] - pub fn chain_to(&mut self) -> CHAIN_TO_W<11> { + pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self) } #[doc = "Bits 15:20 - Select a Transfer Request signal. @@ -1027,7 +1007,7 @@ impl W { 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] - pub fn treq_sel(&mut self) -> TREQ_SEL_W<15> { + pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self) } #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. @@ -1035,14 +1015,14 @@ impl W { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] - pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<21> { + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self) } #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] - pub fn bswap(&mut self) -> BSWAP_W<22> { + pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self) } #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. @@ -1050,46 +1030,45 @@ impl W { This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] - pub fn sniff_en(&mut self) -> SNIFF_EN_W<23> { + pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self) } #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] - pub fn write_error(&mut self) -> WRITE_ERROR_W<29> { + pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self) } #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] - pub fn read_error(&mut self) -> READ_ERROR_W<30> { + pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Control and Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al1_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL1_CTRL_SPEC; impl crate::RegisterSpec for CH_AL1_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al1_ctrl::R](R) reader structure"] -impl crate::Readable for CH_AL1_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al1_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al1_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL1_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x6000_0000; } diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/dma/ch/ch_al1_read_addr.rs index ba95baba4..0c8e2d5ee 100644 --- a/src/dma/ch/ch_al1_read_addr.rs +++ b/src/dma/ch/ch_al1_read_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL1_READ_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL1_READ_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 READ_ADDR register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al1_read_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL1_READ_ADDR_SPEC; impl crate::RegisterSpec for CH_AL1_READ_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al1_read_addr::R](R) reader structure"] -impl crate::Readable for CH_AL1_READ_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al1_read_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al1_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL1_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_read_addr::W`](W) writer structure"] impl crate::Writable for CH_AL1_READ_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/dma/ch/ch_al1_trans_count_trig.rs index 7308a5be6..72c3b36bf 100644 --- a/src/dma/ch/ch_al1_trans_count_trig.rs +++ b/src/dma/ch/ch_al1_trans_count_trig.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL1_TRANS_COUNT_TRIG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL1_TRANS_COUNT_TRIG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -56,20 +28,15 @@ impl W { This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al1_trans_count_trig](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL1_TRANS_COUNT_TRIG_SPEC; impl crate::RegisterSpec for CH_AL1_TRANS_COUNT_TRIG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al1_trans_count_trig::R](R) reader structure"] -impl crate::Readable for CH_AL1_TRANS_COUNT_TRIG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al1_trans_count_trig::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al1_trans_count_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL1_TRANS_COUNT_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_trans_count_trig::W`](W) writer structure"] impl crate::Writable for CH_AL1_TRANS_COUNT_TRIG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/dma/ch/ch_al1_write_addr.rs index abeea2501..57b068c72 100644 --- a/src/dma/ch/ch_al1_write_addr.rs +++ b/src/dma/ch/ch_al1_write_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL1_WRITE_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL1_WRITE_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 WRITE_ADDR register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al1_write_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL1_WRITE_ADDR_SPEC; impl crate::RegisterSpec for CH_AL1_WRITE_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al1_write_addr::R](R) reader structure"] -impl crate::Readable for CH_AL1_WRITE_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al1_write_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al1_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL1_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_write_addr::W`](W) writer structure"] impl crate::Writable for CH_AL1_WRITE_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs index 6e5f40739..3624ed3b0 100644 --- a/src/dma/ch/ch_al2_ctrl.rs +++ b/src/dma/ch/ch_al2_ctrl.rs @@ -1,45 +1,13 @@ #[doc = "Register `CH_AL2_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL2_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] @@ -47,7 +15,7 @@ pub type HIGH_PRIORITY_R = crate::BitReader; #[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] -pub type HIGH_PRIORITY_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type HIGH_PRIORITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -75,7 +43,7 @@ impl crate::FieldSpec for DATA_SIZE_A { impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DATA_SIZE_A::SIZE_BYTE), 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), @@ -83,38 +51,42 @@ impl DATA_SIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SIZE_BYTE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_size_byte(&self) -> bool { *self == DATA_SIZE_A::SIZE_BYTE } - #[doc = "Checks if the value of the field is `SIZE_HALFWORD`"] + #[doc = "`1`"] #[inline(always)] pub fn is_size_halfword(&self) -> bool { *self == DATA_SIZE_A::SIZE_HALFWORD } - #[doc = "Checks if the value of the field is `SIZE_WORD`"] + #[doc = "`10`"] #[inline(always)] pub fn is_size_word(&self) -> bool { *self == DATA_SIZE_A::SIZE_WORD } } #[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL2_CTRL_SPEC, 2, O, DATA_SIZE_A>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DATA_SIZE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn size_byte(self) -> &'a mut W { + pub fn size_byte(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_BYTE) } #[doc = "`1`"] #[inline(always)] - pub fn size_halfword(self) -> &'a mut W { + pub fn size_halfword(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_HALFWORD) } #[doc = "`10`"] #[inline(always)] - pub fn size_word(self) -> &'a mut W { + pub fn size_word(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_WORD) } } @@ -125,7 +97,7 @@ pub type INCR_READ_R = crate::BitReader; #[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] -pub type INCR_READ_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type INCR_READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] @@ -133,7 +105,7 @@ pub type INCR_WRITE_R = crate::BitReader; #[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] -pub type INCR_WRITE_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type INCR_WRITE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] @@ -161,13 +133,13 @@ impl crate::FieldSpec for RING_SIZE_A { impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(RING_SIZE_A::RING_NONE), _ => None, } } - #[doc = "Checks if the value of the field is `RING_NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_ring_none(&self) -> bool { *self == RING_SIZE_A::RING_NONE @@ -176,11 +148,15 @@ impl RING_SIZE_R { #[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL2_CTRL_SPEC, 4, O, RING_SIZE_A>; -impl<'a, const O: u8> RING_SIZE_W<'a, O> { +pub type RING_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, RING_SIZE_A>; +impl<'a, REG, const O: u8> RING_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn ring_none(self) -> &'a mut W { + pub fn ring_none(self) -> &'a mut crate::W { self.variant(RING_SIZE_A::RING_NONE) } } @@ -189,13 +165,13 @@ impl<'a, const O: u8> RING_SIZE_W<'a, O> { pub type RING_SEL_R = crate::BitReader; #[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] -pub type RING_SEL_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type RING_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] -pub type CHAIN_TO_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL2_CTRL_SPEC, 4, O>; +pub type CHAIN_TO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] @@ -311,7 +287,7 @@ impl crate::FieldSpec for TREQ_SEL_A { impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TREQ_SEL_A::PIO0_TX0), 1 => Some(TREQ_SEL_A::PIO0_TX1), @@ -361,227 +337,227 @@ impl TREQ_SEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `PIO0_TX0`"] + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX0 } - #[doc = "Checks if the value of the field is `PIO0_TX1`"] + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX1 } - #[doc = "Checks if the value of the field is `PIO0_TX2`"] + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX2 } - #[doc = "Checks if the value of the field is `PIO0_TX3`"] + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX3 } - #[doc = "Checks if the value of the field is `PIO0_RX0`"] + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX0 } - #[doc = "Checks if the value of the field is `PIO0_RX1`"] + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX1 } - #[doc = "Checks if the value of the field is `PIO0_RX2`"] + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX2 } - #[doc = "Checks if the value of the field is `PIO0_RX3`"] + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX3 } - #[doc = "Checks if the value of the field is `PIO1_TX0`"] + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX0 } - #[doc = "Checks if the value of the field is `PIO1_TX1`"] + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX1 } - #[doc = "Checks if the value of the field is `PIO1_TX2`"] + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX2 } - #[doc = "Checks if the value of the field is `PIO1_TX3`"] + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX3 } - #[doc = "Checks if the value of the field is `PIO1_RX0`"] + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX0 } - #[doc = "Checks if the value of the field is `PIO1_RX1`"] + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX1 } - #[doc = "Checks if the value of the field is `PIO1_RX2`"] + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX2 } - #[doc = "Checks if the value of the field is `PIO1_RX3`"] + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX3 } - #[doc = "Checks if the value of the field is `SPI0_TX`"] + #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_tx(&self) -> bool { *self == TREQ_SEL_A::SPI0_TX } - #[doc = "Checks if the value of the field is `SPI0_RX`"] + #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_rx(&self) -> bool { *self == TREQ_SEL_A::SPI0_RX } - #[doc = "Checks if the value of the field is `SPI1_TX`"] + #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_tx(&self) -> bool { *self == TREQ_SEL_A::SPI1_TX } - #[doc = "Checks if the value of the field is `SPI1_RX`"] + #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_rx(&self) -> bool { *self == TREQ_SEL_A::SPI1_RX } - #[doc = "Checks if the value of the field is `UART0_TX`"] + #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_tx(&self) -> bool { *self == TREQ_SEL_A::UART0_TX } - #[doc = "Checks if the value of the field is `UART0_RX`"] + #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_rx(&self) -> bool { *self == TREQ_SEL_A::UART0_RX } - #[doc = "Checks if the value of the field is `UART1_TX`"] + #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_tx(&self) -> bool { *self == TREQ_SEL_A::UART1_TX } - #[doc = "Checks if the value of the field is `UART1_RX`"] + #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_rx(&self) -> bool { *self == TREQ_SEL_A::UART1_RX } - #[doc = "Checks if the value of the field is `PWM_WRAP0`"] + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap0(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP0 } - #[doc = "Checks if the value of the field is `PWM_WRAP1`"] + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap1(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP1 } - #[doc = "Checks if the value of the field is `PWM_WRAP2`"] + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap2(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP2 } - #[doc = "Checks if the value of the field is `PWM_WRAP3`"] + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap3(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP3 } - #[doc = "Checks if the value of the field is `PWM_WRAP4`"] + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap4(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP4 } - #[doc = "Checks if the value of the field is `PWM_WRAP5`"] + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap5(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP5 } - #[doc = "Checks if the value of the field is `PWM_WRAP6`"] + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap6(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP6 } - #[doc = "Checks if the value of the field is `PWM_WRAP7`"] + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap7(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP7 } - #[doc = "Checks if the value of the field is `I2C0_TX`"] + #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_tx(&self) -> bool { *self == TREQ_SEL_A::I2C0_TX } - #[doc = "Checks if the value of the field is `I2C0_RX`"] + #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_rx(&self) -> bool { *self == TREQ_SEL_A::I2C0_RX } - #[doc = "Checks if the value of the field is `I2C1_TX`"] + #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_tx(&self) -> bool { *self == TREQ_SEL_A::I2C1_TX } - #[doc = "Checks if the value of the field is `I2C1_RX`"] + #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_rx(&self) -> bool { *self == TREQ_SEL_A::I2C1_RX } - #[doc = "Checks if the value of the field is `ADC`"] + #[doc = "Select the ADC as TREQ"] #[inline(always)] pub fn is_adc(&self) -> bool { *self == TREQ_SEL_A::ADC } - #[doc = "Checks if the value of the field is `XIP_STREAM`"] + #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] pub fn is_xip_stream(&self) -> bool { *self == TREQ_SEL_A::XIP_STREAM } - #[doc = "Checks if the value of the field is `XIP_SSITX`"] + #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssitx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSITX } - #[doc = "Checks if the value of the field is `XIP_SSIRX`"] + #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssirx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSIRX } - #[doc = "Checks if the value of the field is `TIMER0`"] + #[doc = "Select Timer 0 as TREQ"] #[inline(always)] pub fn is_timer0(&self) -> bool { *self == TREQ_SEL_A::TIMER0 } - #[doc = "Checks if the value of the field is `TIMER1`"] + #[doc = "Select Timer 1 as TREQ"] #[inline(always)] pub fn is_timer1(&self) -> bool { *self == TREQ_SEL_A::TIMER1 } - #[doc = "Checks if the value of the field is `TIMER2`"] + #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] pub fn is_timer2(&self) -> bool { *self == TREQ_SEL_A::TIMER2 } - #[doc = "Checks if the value of the field is `TIMER3`"] + #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] pub fn is_timer3(&self) -> bool { *self == TREQ_SEL_A::TIMER3 } - #[doc = "Checks if the value of the field is `PERMANENT`"] + #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] pub fn is_permanent(&self) -> bool { *self == TREQ_SEL_A::PERMANENT @@ -590,231 +566,235 @@ impl TREQ_SEL_R { #[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL2_CTRL_SPEC, 6, O, TREQ_SEL_A>; -impl<'a, const O: u8> TREQ_SEL_W<'a, O> { +pub type TREQ_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O, TREQ_SEL_A>; +impl<'a, REG, const O: u8> TREQ_SEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_tx0(self) -> &'a mut W { + pub fn pio0_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX0) } #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_tx1(self) -> &'a mut W { + pub fn pio0_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX1) } #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_tx2(self) -> &'a mut W { + pub fn pio0_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX2) } #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_tx3(self) -> &'a mut W { + pub fn pio0_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX3) } #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_rx0(self) -> &'a mut W { + pub fn pio0_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX0) } #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_rx1(self) -> &'a mut W { + pub fn pio0_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX1) } #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_rx2(self) -> &'a mut W { + pub fn pio0_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX2) } #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_rx3(self) -> &'a mut W { + pub fn pio0_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX3) } #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_tx0(self) -> &'a mut W { + pub fn pio1_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX0) } #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_tx1(self) -> &'a mut W { + pub fn pio1_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX1) } #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_tx2(self) -> &'a mut W { + pub fn pio1_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX2) } #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_tx3(self) -> &'a mut W { + pub fn pio1_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX3) } #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_rx0(self) -> &'a mut W { + pub fn pio1_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX0) } #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_rx1(self) -> &'a mut W { + pub fn pio1_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX1) } #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_rx2(self) -> &'a mut W { + pub fn pio1_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX2) } #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_rx3(self) -> &'a mut W { + pub fn pio1_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX3) } #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] - pub fn spi0_tx(self) -> &'a mut W { + pub fn spi0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_TX) } #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] - pub fn spi0_rx(self) -> &'a mut W { + pub fn spi0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_RX) } #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] - pub fn spi1_tx(self) -> &'a mut W { + pub fn spi1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_TX) } #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] - pub fn spi1_rx(self) -> &'a mut W { + pub fn spi1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_RX) } #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] - pub fn uart0_tx(self) -> &'a mut W { + pub fn uart0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_TX) } #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] - pub fn uart0_rx(self) -> &'a mut W { + pub fn uart0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_RX) } #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] - pub fn uart1_tx(self) -> &'a mut W { + pub fn uart1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_TX) } #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] - pub fn uart1_rx(self) -> &'a mut W { + pub fn uart1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_RX) } #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap0(self) -> &'a mut W { + pub fn pwm_wrap0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP0) } #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap1(self) -> &'a mut W { + pub fn pwm_wrap1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP1) } #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap2(self) -> &'a mut W { + pub fn pwm_wrap2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP2) } #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap3(self) -> &'a mut W { + pub fn pwm_wrap3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP3) } #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap4(self) -> &'a mut W { + pub fn pwm_wrap4(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP4) } #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap5(self) -> &'a mut W { + pub fn pwm_wrap5(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP5) } #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap6(self) -> &'a mut W { + pub fn pwm_wrap6(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP6) } #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap7(self) -> &'a mut W { + pub fn pwm_wrap7(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP7) } #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_tx(self) -> &'a mut W { + pub fn i2c0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_TX) } #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_rx(self) -> &'a mut W { + pub fn i2c0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_RX) } #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_tx(self) -> &'a mut W { + pub fn i2c1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_TX) } #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_rx(self) -> &'a mut W { + pub fn i2c1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_RX) } #[doc = "Select the ADC as TREQ"] #[inline(always)] - pub fn adc(self) -> &'a mut W { + pub fn adc(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::ADC) } #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] - pub fn xip_stream(self) -> &'a mut W { + pub fn xip_stream(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_STREAM) } #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssitx(self) -> &'a mut W { + pub fn xip_ssitx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSITX) } #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssirx(self) -> &'a mut W { + pub fn xip_ssirx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSIRX) } #[doc = "Select Timer 0 as TREQ"] #[inline(always)] - pub fn timer0(self) -> &'a mut W { + pub fn timer0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER0) } #[doc = "Select Timer 1 as TREQ"] #[inline(always)] - pub fn timer1(self) -> &'a mut W { + pub fn timer1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER1) } #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] - pub fn timer2(self) -> &'a mut W { + pub fn timer2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER2) } #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] - pub fn timer3(self) -> &'a mut W { + pub fn timer3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER3) } #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] - pub fn permanent(self) -> &'a mut W { + pub fn permanent(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PERMANENT) } } @@ -825,13 +805,13 @@ pub type IRQ_QUIET_R = crate::BitReader; #[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] -pub type IRQ_QUIET_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type IRQ_QUIET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; #[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] -pub type BSWAP_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type BSWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] @@ -839,7 +819,7 @@ pub type SNIFF_EN_R = crate::BitReader; #[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] -pub type SNIFF_EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL2_CTRL_SPEC, O>; +pub type SNIFF_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] @@ -849,13 +829,13 @@ pub type BUSY_R = crate::BitReader; pub type WRITE_ERROR_R = crate::BitReader; #[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] -pub type WRITE_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL2_CTRL_SPEC, O>; +pub type WRITE_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; #[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] -pub type READ_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL2_CTRL_SPEC, O>; +pub type READ_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { @@ -967,7 +947,7 @@ impl W { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. @@ -975,13 +955,13 @@ impl W { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] - pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<1> { + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W::new(self) } #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<2> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. @@ -989,7 +969,7 @@ impl W { Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] - pub fn incr_read(&mut self) -> INCR_READ_W<4> { + pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self) } #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. @@ -997,7 +977,7 @@ impl W { Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] - pub fn incr_write(&mut self) -> INCR_WRITE_W<5> { + pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self) } #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. @@ -1005,21 +985,21 @@ impl W { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] - pub fn ring_size(&mut self) -> RING_SIZE_W<6> { + pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self) } #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] - pub fn ring_sel(&mut self) -> RING_SEL_W<10> { + pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W::new(self) } #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] #[inline(always)] #[must_use] - pub fn chain_to(&mut self) -> CHAIN_TO_W<11> { + pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self) } #[doc = "Bits 15:20 - Select a Transfer Request signal. @@ -1027,7 +1007,7 @@ impl W { 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] - pub fn treq_sel(&mut self) -> TREQ_SEL_W<15> { + pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self) } #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. @@ -1035,14 +1015,14 @@ impl W { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] - pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<21> { + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self) } #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] - pub fn bswap(&mut self) -> BSWAP_W<22> { + pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self) } #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. @@ -1050,46 +1030,45 @@ impl W { This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] - pub fn sniff_en(&mut self) -> SNIFF_EN_W<23> { + pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self) } #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] - pub fn write_error(&mut self) -> WRITE_ERROR_W<29> { + pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self) } #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] - pub fn read_error(&mut self) -> READ_ERROR_W<30> { + pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Control and Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al2_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL2_CTRL_SPEC; impl crate::RegisterSpec for CH_AL2_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al2_ctrl::R](R) reader structure"] -impl crate::Readable for CH_AL2_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al2_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al2_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL2_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL2_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x6000_0000; } diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/dma/ch/ch_al2_read_addr.rs index d15163c81..c68205bca 100644 --- a/src/dma/ch/ch_al2_read_addr.rs +++ b/src/dma/ch/ch_al2_read_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL2_READ_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL2_READ_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 READ_ADDR register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al2_read_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL2_READ_ADDR_SPEC; impl crate::RegisterSpec for CH_AL2_READ_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al2_read_addr::R](R) reader structure"] -impl crate::Readable for CH_AL2_READ_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al2_read_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al2_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL2_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_read_addr::W`](W) writer structure"] impl crate::Writable for CH_AL2_READ_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/dma/ch/ch_al2_trans_count.rs index ae662e184..94669cd12 100644 --- a/src/dma/ch/ch_al2_trans_count.rs +++ b/src/dma/ch/ch_al2_trans_count.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL2_TRANS_COUNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL2_TRANS_COUNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 TRANS_COUNT register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al2_trans_count](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL2_TRANS_COUNT_SPEC; impl crate::RegisterSpec for CH_AL2_TRANS_COUNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al2_trans_count::R](R) reader structure"] -impl crate::Readable for CH_AL2_TRANS_COUNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al2_trans_count::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al2_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_AL2_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_trans_count::W`](W) writer structure"] impl crate::Writable for CH_AL2_TRANS_COUNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/dma/ch/ch_al2_write_addr_trig.rs index def8ae28f..28eb49e53 100644 --- a/src/dma/ch/ch_al2_write_addr_trig.rs +++ b/src/dma/ch/ch_al2_write_addr_trig.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL2_WRITE_ADDR_TRIG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL2_WRITE_ADDR_TRIG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -56,20 +28,15 @@ impl W { This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al2_write_addr_trig](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL2_WRITE_ADDR_TRIG_SPEC; impl crate::RegisterSpec for CH_AL2_WRITE_ADDR_TRIG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al2_write_addr_trig::R](R) reader structure"] -impl crate::Readable for CH_AL2_WRITE_ADDR_TRIG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al2_write_addr_trig::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al2_write_addr_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL2_WRITE_ADDR_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_write_addr_trig::W`](W) writer structure"] impl crate::Writable for CH_AL2_WRITE_ADDR_TRIG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs index b7afe1b9b..a4f289e9d 100644 --- a/src/dma/ch/ch_al3_ctrl.rs +++ b/src/dma/ch/ch_al3_ctrl.rs @@ -1,45 +1,13 @@ #[doc = "Register `CH_AL3_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL3_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] @@ -47,7 +15,7 @@ pub type HIGH_PRIORITY_R = crate::BitReader; #[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] -pub type HIGH_PRIORITY_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type HIGH_PRIORITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -75,7 +43,7 @@ impl crate::FieldSpec for DATA_SIZE_A { impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DATA_SIZE_A::SIZE_BYTE), 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), @@ -83,38 +51,42 @@ impl DATA_SIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SIZE_BYTE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_size_byte(&self) -> bool { *self == DATA_SIZE_A::SIZE_BYTE } - #[doc = "Checks if the value of the field is `SIZE_HALFWORD`"] + #[doc = "`1`"] #[inline(always)] pub fn is_size_halfword(&self) -> bool { *self == DATA_SIZE_A::SIZE_HALFWORD } - #[doc = "Checks if the value of the field is `SIZE_WORD`"] + #[doc = "`10`"] #[inline(always)] pub fn is_size_word(&self) -> bool { *self == DATA_SIZE_A::SIZE_WORD } } #[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL3_CTRL_SPEC, 2, O, DATA_SIZE_A>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DATA_SIZE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn size_byte(self) -> &'a mut W { + pub fn size_byte(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_BYTE) } #[doc = "`1`"] #[inline(always)] - pub fn size_halfword(self) -> &'a mut W { + pub fn size_halfword(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_HALFWORD) } #[doc = "`10`"] #[inline(always)] - pub fn size_word(self) -> &'a mut W { + pub fn size_word(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_WORD) } } @@ -125,7 +97,7 @@ pub type INCR_READ_R = crate::BitReader; #[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] -pub type INCR_READ_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type INCR_READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] @@ -133,7 +105,7 @@ pub type INCR_WRITE_R = crate::BitReader; #[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] -pub type INCR_WRITE_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type INCR_WRITE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] @@ -161,13 +133,13 @@ impl crate::FieldSpec for RING_SIZE_A { impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(RING_SIZE_A::RING_NONE), _ => None, } } - #[doc = "Checks if the value of the field is `RING_NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_ring_none(&self) -> bool { *self == RING_SIZE_A::RING_NONE @@ -176,11 +148,15 @@ impl RING_SIZE_R { #[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL3_CTRL_SPEC, 4, O, RING_SIZE_A>; -impl<'a, const O: u8> RING_SIZE_W<'a, O> { +pub type RING_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, RING_SIZE_A>; +impl<'a, REG, const O: u8> RING_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn ring_none(self) -> &'a mut W { + pub fn ring_none(self) -> &'a mut crate::W { self.variant(RING_SIZE_A::RING_NONE) } } @@ -189,13 +165,13 @@ impl<'a, const O: u8> RING_SIZE_W<'a, O> { pub type RING_SEL_R = crate::BitReader; #[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] -pub type RING_SEL_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type RING_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] -pub type CHAIN_TO_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL3_CTRL_SPEC, 4, O>; +pub type CHAIN_TO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] @@ -311,7 +287,7 @@ impl crate::FieldSpec for TREQ_SEL_A { impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TREQ_SEL_A::PIO0_TX0), 1 => Some(TREQ_SEL_A::PIO0_TX1), @@ -361,227 +337,227 @@ impl TREQ_SEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `PIO0_TX0`"] + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX0 } - #[doc = "Checks if the value of the field is `PIO0_TX1`"] + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX1 } - #[doc = "Checks if the value of the field is `PIO0_TX2`"] + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX2 } - #[doc = "Checks if the value of the field is `PIO0_TX3`"] + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX3 } - #[doc = "Checks if the value of the field is `PIO0_RX0`"] + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX0 } - #[doc = "Checks if the value of the field is `PIO0_RX1`"] + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX1 } - #[doc = "Checks if the value of the field is `PIO0_RX2`"] + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX2 } - #[doc = "Checks if the value of the field is `PIO0_RX3`"] + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX3 } - #[doc = "Checks if the value of the field is `PIO1_TX0`"] + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX0 } - #[doc = "Checks if the value of the field is `PIO1_TX1`"] + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX1 } - #[doc = "Checks if the value of the field is `PIO1_TX2`"] + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX2 } - #[doc = "Checks if the value of the field is `PIO1_TX3`"] + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX3 } - #[doc = "Checks if the value of the field is `PIO1_RX0`"] + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX0 } - #[doc = "Checks if the value of the field is `PIO1_RX1`"] + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX1 } - #[doc = "Checks if the value of the field is `PIO1_RX2`"] + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX2 } - #[doc = "Checks if the value of the field is `PIO1_RX3`"] + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX3 } - #[doc = "Checks if the value of the field is `SPI0_TX`"] + #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_tx(&self) -> bool { *self == TREQ_SEL_A::SPI0_TX } - #[doc = "Checks if the value of the field is `SPI0_RX`"] + #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_rx(&self) -> bool { *self == TREQ_SEL_A::SPI0_RX } - #[doc = "Checks if the value of the field is `SPI1_TX`"] + #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_tx(&self) -> bool { *self == TREQ_SEL_A::SPI1_TX } - #[doc = "Checks if the value of the field is `SPI1_RX`"] + #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_rx(&self) -> bool { *self == TREQ_SEL_A::SPI1_RX } - #[doc = "Checks if the value of the field is `UART0_TX`"] + #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_tx(&self) -> bool { *self == TREQ_SEL_A::UART0_TX } - #[doc = "Checks if the value of the field is `UART0_RX`"] + #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_rx(&self) -> bool { *self == TREQ_SEL_A::UART0_RX } - #[doc = "Checks if the value of the field is `UART1_TX`"] + #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_tx(&self) -> bool { *self == TREQ_SEL_A::UART1_TX } - #[doc = "Checks if the value of the field is `UART1_RX`"] + #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_rx(&self) -> bool { *self == TREQ_SEL_A::UART1_RX } - #[doc = "Checks if the value of the field is `PWM_WRAP0`"] + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap0(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP0 } - #[doc = "Checks if the value of the field is `PWM_WRAP1`"] + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap1(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP1 } - #[doc = "Checks if the value of the field is `PWM_WRAP2`"] + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap2(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP2 } - #[doc = "Checks if the value of the field is `PWM_WRAP3`"] + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap3(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP3 } - #[doc = "Checks if the value of the field is `PWM_WRAP4`"] + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap4(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP4 } - #[doc = "Checks if the value of the field is `PWM_WRAP5`"] + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap5(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP5 } - #[doc = "Checks if the value of the field is `PWM_WRAP6`"] + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap6(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP6 } - #[doc = "Checks if the value of the field is `PWM_WRAP7`"] + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap7(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP7 } - #[doc = "Checks if the value of the field is `I2C0_TX`"] + #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_tx(&self) -> bool { *self == TREQ_SEL_A::I2C0_TX } - #[doc = "Checks if the value of the field is `I2C0_RX`"] + #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_rx(&self) -> bool { *self == TREQ_SEL_A::I2C0_RX } - #[doc = "Checks if the value of the field is `I2C1_TX`"] + #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_tx(&self) -> bool { *self == TREQ_SEL_A::I2C1_TX } - #[doc = "Checks if the value of the field is `I2C1_RX`"] + #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_rx(&self) -> bool { *self == TREQ_SEL_A::I2C1_RX } - #[doc = "Checks if the value of the field is `ADC`"] + #[doc = "Select the ADC as TREQ"] #[inline(always)] pub fn is_adc(&self) -> bool { *self == TREQ_SEL_A::ADC } - #[doc = "Checks if the value of the field is `XIP_STREAM`"] + #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] pub fn is_xip_stream(&self) -> bool { *self == TREQ_SEL_A::XIP_STREAM } - #[doc = "Checks if the value of the field is `XIP_SSITX`"] + #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssitx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSITX } - #[doc = "Checks if the value of the field is `XIP_SSIRX`"] + #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssirx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSIRX } - #[doc = "Checks if the value of the field is `TIMER0`"] + #[doc = "Select Timer 0 as TREQ"] #[inline(always)] pub fn is_timer0(&self) -> bool { *self == TREQ_SEL_A::TIMER0 } - #[doc = "Checks if the value of the field is `TIMER1`"] + #[doc = "Select Timer 1 as TREQ"] #[inline(always)] pub fn is_timer1(&self) -> bool { *self == TREQ_SEL_A::TIMER1 } - #[doc = "Checks if the value of the field is `TIMER2`"] + #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] pub fn is_timer2(&self) -> bool { *self == TREQ_SEL_A::TIMER2 } - #[doc = "Checks if the value of the field is `TIMER3`"] + #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] pub fn is_timer3(&self) -> bool { *self == TREQ_SEL_A::TIMER3 } - #[doc = "Checks if the value of the field is `PERMANENT`"] + #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] pub fn is_permanent(&self) -> bool { *self == TREQ_SEL_A::PERMANENT @@ -590,231 +566,235 @@ impl TREQ_SEL_R { #[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CH_AL3_CTRL_SPEC, 6, O, TREQ_SEL_A>; -impl<'a, const O: u8> TREQ_SEL_W<'a, O> { +pub type TREQ_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O, TREQ_SEL_A>; +impl<'a, REG, const O: u8> TREQ_SEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_tx0(self) -> &'a mut W { + pub fn pio0_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX0) } #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_tx1(self) -> &'a mut W { + pub fn pio0_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX1) } #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_tx2(self) -> &'a mut W { + pub fn pio0_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX2) } #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_tx3(self) -> &'a mut W { + pub fn pio0_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX3) } #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_rx0(self) -> &'a mut W { + pub fn pio0_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX0) } #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_rx1(self) -> &'a mut W { + pub fn pio0_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX1) } #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_rx2(self) -> &'a mut W { + pub fn pio0_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX2) } #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_rx3(self) -> &'a mut W { + pub fn pio0_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX3) } #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_tx0(self) -> &'a mut W { + pub fn pio1_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX0) } #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_tx1(self) -> &'a mut W { + pub fn pio1_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX1) } #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_tx2(self) -> &'a mut W { + pub fn pio1_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX2) } #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_tx3(self) -> &'a mut W { + pub fn pio1_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX3) } #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_rx0(self) -> &'a mut W { + pub fn pio1_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX0) } #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_rx1(self) -> &'a mut W { + pub fn pio1_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX1) } #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_rx2(self) -> &'a mut W { + pub fn pio1_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX2) } #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_rx3(self) -> &'a mut W { + pub fn pio1_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX3) } #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] - pub fn spi0_tx(self) -> &'a mut W { + pub fn spi0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_TX) } #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] - pub fn spi0_rx(self) -> &'a mut W { + pub fn spi0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_RX) } #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] - pub fn spi1_tx(self) -> &'a mut W { + pub fn spi1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_TX) } #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] - pub fn spi1_rx(self) -> &'a mut W { + pub fn spi1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_RX) } #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] - pub fn uart0_tx(self) -> &'a mut W { + pub fn uart0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_TX) } #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] - pub fn uart0_rx(self) -> &'a mut W { + pub fn uart0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_RX) } #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] - pub fn uart1_tx(self) -> &'a mut W { + pub fn uart1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_TX) } #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] - pub fn uart1_rx(self) -> &'a mut W { + pub fn uart1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_RX) } #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap0(self) -> &'a mut W { + pub fn pwm_wrap0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP0) } #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap1(self) -> &'a mut W { + pub fn pwm_wrap1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP1) } #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap2(self) -> &'a mut W { + pub fn pwm_wrap2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP2) } #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap3(self) -> &'a mut W { + pub fn pwm_wrap3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP3) } #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap4(self) -> &'a mut W { + pub fn pwm_wrap4(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP4) } #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap5(self) -> &'a mut W { + pub fn pwm_wrap5(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP5) } #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap6(self) -> &'a mut W { + pub fn pwm_wrap6(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP6) } #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap7(self) -> &'a mut W { + pub fn pwm_wrap7(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP7) } #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_tx(self) -> &'a mut W { + pub fn i2c0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_TX) } #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_rx(self) -> &'a mut W { + pub fn i2c0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_RX) } #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_tx(self) -> &'a mut W { + pub fn i2c1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_TX) } #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_rx(self) -> &'a mut W { + pub fn i2c1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_RX) } #[doc = "Select the ADC as TREQ"] #[inline(always)] - pub fn adc(self) -> &'a mut W { + pub fn adc(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::ADC) } #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] - pub fn xip_stream(self) -> &'a mut W { + pub fn xip_stream(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_STREAM) } #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssitx(self) -> &'a mut W { + pub fn xip_ssitx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSITX) } #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssirx(self) -> &'a mut W { + pub fn xip_ssirx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSIRX) } #[doc = "Select Timer 0 as TREQ"] #[inline(always)] - pub fn timer0(self) -> &'a mut W { + pub fn timer0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER0) } #[doc = "Select Timer 1 as TREQ"] #[inline(always)] - pub fn timer1(self) -> &'a mut W { + pub fn timer1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER1) } #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] - pub fn timer2(self) -> &'a mut W { + pub fn timer2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER2) } #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] - pub fn timer3(self) -> &'a mut W { + pub fn timer3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER3) } #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] - pub fn permanent(self) -> &'a mut W { + pub fn permanent(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PERMANENT) } } @@ -825,13 +805,13 @@ pub type IRQ_QUIET_R = crate::BitReader; #[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] -pub type IRQ_QUIET_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type IRQ_QUIET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; #[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] -pub type BSWAP_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type BSWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] @@ -839,7 +819,7 @@ pub type SNIFF_EN_R = crate::BitReader; #[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] -pub type SNIFF_EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_AL3_CTRL_SPEC, O>; +pub type SNIFF_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] @@ -849,13 +829,13 @@ pub type BUSY_R = crate::BitReader; pub type WRITE_ERROR_R = crate::BitReader; #[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] -pub type WRITE_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL3_CTRL_SPEC, O>; +pub type WRITE_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; #[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] -pub type READ_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_AL3_CTRL_SPEC, O>; +pub type READ_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { @@ -967,7 +947,7 @@ impl W { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. @@ -975,13 +955,13 @@ impl W { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] - pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<1> { + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W::new(self) } #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<2> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. @@ -989,7 +969,7 @@ impl W { Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] - pub fn incr_read(&mut self) -> INCR_READ_W<4> { + pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self) } #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. @@ -997,7 +977,7 @@ impl W { Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] - pub fn incr_write(&mut self) -> INCR_WRITE_W<5> { + pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self) } #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. @@ -1005,21 +985,21 @@ impl W { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] - pub fn ring_size(&mut self) -> RING_SIZE_W<6> { + pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self) } #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] - pub fn ring_sel(&mut self) -> RING_SEL_W<10> { + pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W::new(self) } #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] #[inline(always)] #[must_use] - pub fn chain_to(&mut self) -> CHAIN_TO_W<11> { + pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self) } #[doc = "Bits 15:20 - Select a Transfer Request signal. @@ -1027,7 +1007,7 @@ impl W { 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] - pub fn treq_sel(&mut self) -> TREQ_SEL_W<15> { + pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self) } #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. @@ -1035,14 +1015,14 @@ impl W { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] - pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<21> { + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self) } #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] - pub fn bswap(&mut self) -> BSWAP_W<22> { + pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self) } #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. @@ -1050,46 +1030,45 @@ impl W { This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] - pub fn sniff_en(&mut self) -> SNIFF_EN_W<23> { + pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self) } #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] - pub fn write_error(&mut self) -> WRITE_ERROR_W<29> { + pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self) } #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] - pub fn read_error(&mut self) -> READ_ERROR_W<30> { + pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Control and Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al3_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL3_CTRL_SPEC; impl crate::RegisterSpec for CH_AL3_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al3_ctrl::R](R) reader structure"] -impl crate::Readable for CH_AL3_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al3_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al3_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL3_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL3_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x6000_0000; } diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/dma/ch/ch_al3_read_addr_trig.rs index 3cce8489c..340615c2a 100644 --- a/src/dma/ch/ch_al3_read_addr_trig.rs +++ b/src/dma/ch/ch_al3_read_addr_trig.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL3_READ_ADDR_TRIG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL3_READ_ADDR_TRIG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -56,20 +28,15 @@ impl W { This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al3_read_addr_trig](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL3_READ_ADDR_TRIG_SPEC; impl crate::RegisterSpec for CH_AL3_READ_ADDR_TRIG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al3_read_addr_trig::R](R) reader structure"] -impl crate::Readable for CH_AL3_READ_ADDR_TRIG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al3_read_addr_trig::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al3_read_addr_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL3_READ_ADDR_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_read_addr_trig::W`](W) writer structure"] impl crate::Writable for CH_AL3_READ_ADDR_TRIG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/dma/ch/ch_al3_trans_count.rs index a033fce0b..d54c0c85d 100644 --- a/src/dma/ch/ch_al3_trans_count.rs +++ b/src/dma/ch/ch_al3_trans_count.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL3_TRANS_COUNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL3_TRANS_COUNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 TRANS_COUNT register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al3_trans_count](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL3_TRANS_COUNT_SPEC; impl crate::RegisterSpec for CH_AL3_TRANS_COUNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al3_trans_count::R](R) reader structure"] -impl crate::Readable for CH_AL3_TRANS_COUNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al3_trans_count::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al3_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_AL3_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_trans_count::W`](W) writer structure"] impl crate::Writable for CH_AL3_TRANS_COUNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/dma/ch/ch_al3_write_addr.rs index 236858365..0dd5228e5 100644 --- a/src/dma/ch/ch_al3_write_addr.rs +++ b/src/dma/ch/ch_al3_write_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_AL3_WRITE_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_AL3_WRITE_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Alias for channel 0 WRITE_ADDR register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_al3_write_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL3_WRITE_ADDR_SPEC; impl crate::RegisterSpec for CH_AL3_WRITE_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_al3_write_addr::R](R) reader structure"] -impl crate::Readable for CH_AL3_WRITE_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_al3_write_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_al3_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL3_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_write_addr::W`](W) writer structure"] impl crate::Writable for CH_AL3_WRITE_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs index bea17333d..5257754b2 100644 --- a/src/dma/ch/ch_ctrl_trig.rs +++ b/src/dma/ch/ch_ctrl_trig.rs @@ -1,45 +1,13 @@ #[doc = "Register `CH_CTRL_TRIG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_CTRL_TRIG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] @@ -47,7 +15,7 @@ pub type HIGH_PRIORITY_R = crate::BitReader; #[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] -pub type HIGH_PRIORITY_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type HIGH_PRIORITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -75,7 +43,7 @@ impl crate::FieldSpec for DATA_SIZE_A { impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DATA_SIZE_A::SIZE_BYTE), 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), @@ -83,39 +51,42 @@ impl DATA_SIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SIZE_BYTE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_size_byte(&self) -> bool { *self == DATA_SIZE_A::SIZE_BYTE } - #[doc = "Checks if the value of the field is `SIZE_HALFWORD`"] + #[doc = "`1`"] #[inline(always)] pub fn is_size_halfword(&self) -> bool { *self == DATA_SIZE_A::SIZE_HALFWORD } - #[doc = "Checks if the value of the field is `SIZE_WORD`"] + #[doc = "`10`"] #[inline(always)] pub fn is_size_word(&self) -> bool { *self == DATA_SIZE_A::SIZE_WORD } } #[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_W<'a, const O: u8> = - crate::FieldWriter<'a, CH_CTRL_TRIG_SPEC, 2, O, DATA_SIZE_A>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DATA_SIZE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn size_byte(self) -> &'a mut W { + pub fn size_byte(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_BYTE) } #[doc = "`1`"] #[inline(always)] - pub fn size_halfword(self) -> &'a mut W { + pub fn size_halfword(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_HALFWORD) } #[doc = "`10`"] #[inline(always)] - pub fn size_word(self) -> &'a mut W { + pub fn size_word(self) -> &'a mut crate::W { self.variant(DATA_SIZE_A::SIZE_WORD) } } @@ -126,7 +97,7 @@ pub type INCR_READ_R = crate::BitReader; #[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] -pub type INCR_READ_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type INCR_READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] @@ -134,7 +105,7 @@ pub type INCR_WRITE_R = crate::BitReader; #[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] -pub type INCR_WRITE_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type INCR_WRITE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] @@ -162,13 +133,13 @@ impl crate::FieldSpec for RING_SIZE_A { impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(RING_SIZE_A::RING_NONE), _ => None, } } - #[doc = "Checks if the value of the field is `RING_NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_ring_none(&self) -> bool { *self == RING_SIZE_A::RING_NONE @@ -177,12 +148,15 @@ impl RING_SIZE_R { #[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_W<'a, const O: u8> = - crate::FieldWriter<'a, CH_CTRL_TRIG_SPEC, 4, O, RING_SIZE_A>; -impl<'a, const O: u8> RING_SIZE_W<'a, O> { +pub type RING_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, RING_SIZE_A>; +impl<'a, REG, const O: u8> RING_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn ring_none(self) -> &'a mut W { + pub fn ring_none(self) -> &'a mut crate::W { self.variant(RING_SIZE_A::RING_NONE) } } @@ -191,13 +165,13 @@ impl<'a, const O: u8> RING_SIZE_W<'a, O> { pub type RING_SEL_R = crate::BitReader; #[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] -pub type RING_SEL_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type RING_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] -pub type CHAIN_TO_W<'a, const O: u8> = crate::FieldWriter<'a, CH_CTRL_TRIG_SPEC, 4, O>; +pub type CHAIN_TO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] @@ -313,7 +287,7 @@ impl crate::FieldSpec for TREQ_SEL_A { impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TREQ_SEL_A::PIO0_TX0), 1 => Some(TREQ_SEL_A::PIO0_TX1), @@ -363,227 +337,227 @@ impl TREQ_SEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `PIO0_TX0`"] + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX0 } - #[doc = "Checks if the value of the field is `PIO0_TX1`"] + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX1 } - #[doc = "Checks if the value of the field is `PIO0_TX2`"] + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX2 } - #[doc = "Checks if the value of the field is `PIO0_TX3`"] + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_TX3 } - #[doc = "Checks if the value of the field is `PIO0_RX0`"] + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio0_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX0 } - #[doc = "Checks if the value of the field is `PIO0_RX1`"] + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio0_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX1 } - #[doc = "Checks if the value of the field is `PIO0_RX2`"] + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio0_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX2 } - #[doc = "Checks if the value of the field is `PIO0_RX3`"] + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio0_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO0_RX3 } - #[doc = "Checks if the value of the field is `PIO1_TX0`"] + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_tx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX0 } - #[doc = "Checks if the value of the field is `PIO1_TX1`"] + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_tx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX1 } - #[doc = "Checks if the value of the field is `PIO1_TX2`"] + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_tx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX2 } - #[doc = "Checks if the value of the field is `PIO1_TX3`"] + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_tx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_TX3 } - #[doc = "Checks if the value of the field is `PIO1_RX0`"] + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] pub fn is_pio1_rx0(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX0 } - #[doc = "Checks if the value of the field is `PIO1_RX1`"] + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] pub fn is_pio1_rx1(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX1 } - #[doc = "Checks if the value of the field is `PIO1_RX2`"] + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] pub fn is_pio1_rx2(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX2 } - #[doc = "Checks if the value of the field is `PIO1_RX3`"] + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] pub fn is_pio1_rx3(&self) -> bool { *self == TREQ_SEL_A::PIO1_RX3 } - #[doc = "Checks if the value of the field is `SPI0_TX`"] + #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_tx(&self) -> bool { *self == TREQ_SEL_A::SPI0_TX } - #[doc = "Checks if the value of the field is `SPI0_RX`"] + #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi0_rx(&self) -> bool { *self == TREQ_SEL_A::SPI0_RX } - #[doc = "Checks if the value of the field is `SPI1_TX`"] + #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_tx(&self) -> bool { *self == TREQ_SEL_A::SPI1_TX } - #[doc = "Checks if the value of the field is `SPI1_RX`"] + #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] pub fn is_spi1_rx(&self) -> bool { *self == TREQ_SEL_A::SPI1_RX } - #[doc = "Checks if the value of the field is `UART0_TX`"] + #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_tx(&self) -> bool { *self == TREQ_SEL_A::UART0_TX } - #[doc = "Checks if the value of the field is `UART0_RX`"] + #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart0_rx(&self) -> bool { *self == TREQ_SEL_A::UART0_RX } - #[doc = "Checks if the value of the field is `UART1_TX`"] + #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_tx(&self) -> bool { *self == TREQ_SEL_A::UART1_TX } - #[doc = "Checks if the value of the field is `UART1_RX`"] + #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] pub fn is_uart1_rx(&self) -> bool { *self == TREQ_SEL_A::UART1_RX } - #[doc = "Checks if the value of the field is `PWM_WRAP0`"] + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap0(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP0 } - #[doc = "Checks if the value of the field is `PWM_WRAP1`"] + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap1(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP1 } - #[doc = "Checks if the value of the field is `PWM_WRAP2`"] + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap2(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP2 } - #[doc = "Checks if the value of the field is `PWM_WRAP3`"] + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap3(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP3 } - #[doc = "Checks if the value of the field is `PWM_WRAP4`"] + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap4(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP4 } - #[doc = "Checks if the value of the field is `PWM_WRAP5`"] + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap5(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP5 } - #[doc = "Checks if the value of the field is `PWM_WRAP6`"] + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap6(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP6 } - #[doc = "Checks if the value of the field is `PWM_WRAP7`"] + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] pub fn is_pwm_wrap7(&self) -> bool { *self == TREQ_SEL_A::PWM_WRAP7 } - #[doc = "Checks if the value of the field is `I2C0_TX`"] + #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_tx(&self) -> bool { *self == TREQ_SEL_A::I2C0_TX } - #[doc = "Checks if the value of the field is `I2C0_RX`"] + #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c0_rx(&self) -> bool { *self == TREQ_SEL_A::I2C0_RX } - #[doc = "Checks if the value of the field is `I2C1_TX`"] + #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_tx(&self) -> bool { *self == TREQ_SEL_A::I2C1_TX } - #[doc = "Checks if the value of the field is `I2C1_RX`"] + #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] pub fn is_i2c1_rx(&self) -> bool { *self == TREQ_SEL_A::I2C1_RX } - #[doc = "Checks if the value of the field is `ADC`"] + #[doc = "Select the ADC as TREQ"] #[inline(always)] pub fn is_adc(&self) -> bool { *self == TREQ_SEL_A::ADC } - #[doc = "Checks if the value of the field is `XIP_STREAM`"] + #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] pub fn is_xip_stream(&self) -> bool { *self == TREQ_SEL_A::XIP_STREAM } - #[doc = "Checks if the value of the field is `XIP_SSITX`"] + #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssitx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSITX } - #[doc = "Checks if the value of the field is `XIP_SSIRX`"] + #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] pub fn is_xip_ssirx(&self) -> bool { *self == TREQ_SEL_A::XIP_SSIRX } - #[doc = "Checks if the value of the field is `TIMER0`"] + #[doc = "Select Timer 0 as TREQ"] #[inline(always)] pub fn is_timer0(&self) -> bool { *self == TREQ_SEL_A::TIMER0 } - #[doc = "Checks if the value of the field is `TIMER1`"] + #[doc = "Select Timer 1 as TREQ"] #[inline(always)] pub fn is_timer1(&self) -> bool { *self == TREQ_SEL_A::TIMER1 } - #[doc = "Checks if the value of the field is `TIMER2`"] + #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] pub fn is_timer2(&self) -> bool { *self == TREQ_SEL_A::TIMER2 } - #[doc = "Checks if the value of the field is `TIMER3`"] + #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] pub fn is_timer3(&self) -> bool { *self == TREQ_SEL_A::TIMER3 } - #[doc = "Checks if the value of the field is `PERMANENT`"] + #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] pub fn is_permanent(&self) -> bool { *self == TREQ_SEL_A::PERMANENT @@ -592,231 +566,235 @@ impl TREQ_SEL_R { #[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CH_CTRL_TRIG_SPEC, 6, O, TREQ_SEL_A>; -impl<'a, const O: u8> TREQ_SEL_W<'a, O> { +pub type TREQ_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O, TREQ_SEL_A>; +impl<'a, REG, const O: u8> TREQ_SEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select PIO0's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_tx0(self) -> &'a mut W { + pub fn pio0_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX0) } #[doc = "Select PIO0's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_tx1(self) -> &'a mut W { + pub fn pio0_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX1) } #[doc = "Select PIO0's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_tx2(self) -> &'a mut W { + pub fn pio0_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX2) } #[doc = "Select PIO0's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_tx3(self) -> &'a mut W { + pub fn pio0_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_TX3) } #[doc = "Select PIO0's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio0_rx0(self) -> &'a mut W { + pub fn pio0_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX0) } #[doc = "Select PIO0's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio0_rx1(self) -> &'a mut W { + pub fn pio0_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX1) } #[doc = "Select PIO0's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio0_rx2(self) -> &'a mut W { + pub fn pio0_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX2) } #[doc = "Select PIO0's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio0_rx3(self) -> &'a mut W { + pub fn pio0_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO0_RX3) } #[doc = "Select PIO1's TX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_tx0(self) -> &'a mut W { + pub fn pio1_tx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX0) } #[doc = "Select PIO1's TX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_tx1(self) -> &'a mut W { + pub fn pio1_tx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX1) } #[doc = "Select PIO1's TX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_tx2(self) -> &'a mut W { + pub fn pio1_tx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX2) } #[doc = "Select PIO1's TX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_tx3(self) -> &'a mut W { + pub fn pio1_tx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_TX3) } #[doc = "Select PIO1's RX FIFO 0 as TREQ"] #[inline(always)] - pub fn pio1_rx0(self) -> &'a mut W { + pub fn pio1_rx0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX0) } #[doc = "Select PIO1's RX FIFO 1 as TREQ"] #[inline(always)] - pub fn pio1_rx1(self) -> &'a mut W { + pub fn pio1_rx1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX1) } #[doc = "Select PIO1's RX FIFO 2 as TREQ"] #[inline(always)] - pub fn pio1_rx2(self) -> &'a mut W { + pub fn pio1_rx2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX2) } #[doc = "Select PIO1's RX FIFO 3 as TREQ"] #[inline(always)] - pub fn pio1_rx3(self) -> &'a mut W { + pub fn pio1_rx3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PIO1_RX3) } #[doc = "Select SPI0's TX FIFO as TREQ"] #[inline(always)] - pub fn spi0_tx(self) -> &'a mut W { + pub fn spi0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_TX) } #[doc = "Select SPI0's RX FIFO as TREQ"] #[inline(always)] - pub fn spi0_rx(self) -> &'a mut W { + pub fn spi0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI0_RX) } #[doc = "Select SPI1's TX FIFO as TREQ"] #[inline(always)] - pub fn spi1_tx(self) -> &'a mut W { + pub fn spi1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_TX) } #[doc = "Select SPI1's RX FIFO as TREQ"] #[inline(always)] - pub fn spi1_rx(self) -> &'a mut W { + pub fn spi1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::SPI1_RX) } #[doc = "Select UART0's TX FIFO as TREQ"] #[inline(always)] - pub fn uart0_tx(self) -> &'a mut W { + pub fn uart0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_TX) } #[doc = "Select UART0's RX FIFO as TREQ"] #[inline(always)] - pub fn uart0_rx(self) -> &'a mut W { + pub fn uart0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART0_RX) } #[doc = "Select UART1's TX FIFO as TREQ"] #[inline(always)] - pub fn uart1_tx(self) -> &'a mut W { + pub fn uart1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_TX) } #[doc = "Select UART1's RX FIFO as TREQ"] #[inline(always)] - pub fn uart1_rx(self) -> &'a mut W { + pub fn uart1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::UART1_RX) } #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap0(self) -> &'a mut W { + pub fn pwm_wrap0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP0) } #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap1(self) -> &'a mut W { + pub fn pwm_wrap1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP1) } #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap2(self) -> &'a mut W { + pub fn pwm_wrap2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP2) } #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap3(self) -> &'a mut W { + pub fn pwm_wrap3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP3) } #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap4(self) -> &'a mut W { + pub fn pwm_wrap4(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP4) } #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap5(self) -> &'a mut W { + pub fn pwm_wrap5(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP5) } #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap6(self) -> &'a mut W { + pub fn pwm_wrap6(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP6) } #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] #[inline(always)] - pub fn pwm_wrap7(self) -> &'a mut W { + pub fn pwm_wrap7(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PWM_WRAP7) } #[doc = "Select I2C0's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_tx(self) -> &'a mut W { + pub fn i2c0_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_TX) } #[doc = "Select I2C0's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c0_rx(self) -> &'a mut W { + pub fn i2c0_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C0_RX) } #[doc = "Select I2C1's TX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_tx(self) -> &'a mut W { + pub fn i2c1_tx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_TX) } #[doc = "Select I2C1's RX FIFO as TREQ"] #[inline(always)] - pub fn i2c1_rx(self) -> &'a mut W { + pub fn i2c1_rx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::I2C1_RX) } #[doc = "Select the ADC as TREQ"] #[inline(always)] - pub fn adc(self) -> &'a mut W { + pub fn adc(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::ADC) } #[doc = "Select the XIP Streaming FIFO as TREQ"] #[inline(always)] - pub fn xip_stream(self) -> &'a mut W { + pub fn xip_stream(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_STREAM) } #[doc = "Select the XIP SSI TX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssitx(self) -> &'a mut W { + pub fn xip_ssitx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSITX) } #[doc = "Select the XIP SSI RX FIFO as TREQ"] #[inline(always)] - pub fn xip_ssirx(self) -> &'a mut W { + pub fn xip_ssirx(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::XIP_SSIRX) } #[doc = "Select Timer 0 as TREQ"] #[inline(always)] - pub fn timer0(self) -> &'a mut W { + pub fn timer0(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER0) } #[doc = "Select Timer 1 as TREQ"] #[inline(always)] - pub fn timer1(self) -> &'a mut W { + pub fn timer1(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER1) } #[doc = "Select Timer 2 as TREQ (Optional)"] #[inline(always)] - pub fn timer2(self) -> &'a mut W { + pub fn timer2(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER2) } #[doc = "Select Timer 3 as TREQ (Optional)"] #[inline(always)] - pub fn timer3(self) -> &'a mut W { + pub fn timer3(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::TIMER3) } #[doc = "Permanent request, for unpaced transfers."] #[inline(always)] - pub fn permanent(self) -> &'a mut W { + pub fn permanent(self) -> &'a mut crate::W { self.variant(TREQ_SEL_A::PERMANENT) } } @@ -827,13 +805,13 @@ pub type IRQ_QUIET_R = crate::BitReader; #[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] -pub type IRQ_QUIET_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type IRQ_QUIET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; #[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] -pub type BSWAP_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type BSWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] @@ -841,7 +819,7 @@ pub type SNIFF_EN_R = crate::BitReader; #[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] -pub type SNIFF_EN_W<'a, const O: u8> = crate::BitWriter<'a, CH_CTRL_TRIG_SPEC, O>; +pub type SNIFF_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] @@ -851,13 +829,13 @@ pub type BUSY_R = crate::BitReader; pub type WRITE_ERROR_R = crate::BitReader; #[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] -pub type WRITE_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_CTRL_TRIG_SPEC, O>; +pub type WRITE_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; #[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] -pub type READ_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, CH_CTRL_TRIG_SPEC, O>; +pub type READ_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { @@ -969,7 +947,7 @@ impl W { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. @@ -977,13 +955,13 @@ impl W { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] - pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<1> { + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W::new(self) } #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<2> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. @@ -991,7 +969,7 @@ impl W { Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] - pub fn incr_read(&mut self) -> INCR_READ_W<4> { + pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self) } #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. @@ -999,7 +977,7 @@ impl W { Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] - pub fn incr_write(&mut self) -> INCR_WRITE_W<5> { + pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self) } #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. @@ -1007,21 +985,21 @@ impl W { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] - pub fn ring_size(&mut self) -> RING_SIZE_W<6> { + pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self) } #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] - pub fn ring_sel(&mut self) -> RING_SEL_W<10> { + pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W::new(self) } #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] #[inline(always)] #[must_use] - pub fn chain_to(&mut self) -> CHAIN_TO_W<11> { + pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self) } #[doc = "Bits 15:20 - Select a Transfer Request signal. @@ -1029,7 +1007,7 @@ impl W { 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] - pub fn treq_sel(&mut self) -> TREQ_SEL_W<15> { + pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self) } #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. @@ -1037,14 +1015,14 @@ impl W { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] - pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<21> { + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self) } #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] - pub fn bswap(&mut self) -> BSWAP_W<22> { + pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self) } #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. @@ -1052,46 +1030,45 @@ impl W { This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] - pub fn sniff_en(&mut self) -> SNIFF_EN_W<23> { + pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self) } #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] - pub fn write_error(&mut self) -> WRITE_ERROR_W<29> { + pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self) } #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] - pub fn read_error(&mut self) -> READ_ERROR_W<30> { + pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Control and Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_ctrl_trig](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_ctrl_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_CTRL_TRIG_SPEC; impl crate::RegisterSpec for CH_CTRL_TRIG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_ctrl_trig::R](R) reader structure"] -impl crate::Readable for CH_CTRL_TRIG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_ctrl_trig::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_ctrl_trig::R`](R) reader structure"] +impl crate::Readable for CH_CTRL_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_ctrl_trig::W`](W) writer structure"] impl crate::Writable for CH_CTRL_TRIG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x6000_0000; } diff --git a/src/dma/ch/ch_read_addr.rs b/src/dma/ch/ch_read_addr.rs index ca2a3fc6d..bf7b6ad31 100644 --- a/src/dma/ch/ch_read_addr.rs +++ b/src/dma/ch/ch_read_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_READ_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_READ_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_read_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_READ_ADDR_SPEC; impl crate::RegisterSpec for CH_READ_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_read_addr::R](R) reader structure"] -impl crate::Readable for CH_READ_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_read_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_read_addr::W`](W) writer structure"] impl crate::Writable for CH_READ_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_trans_count.rs b/src/dma/ch/ch_trans_count.rs index a81b084aa..47b40d363 100644 --- a/src/dma/ch/ch_trans_count.rs +++ b/src/dma/ch/ch_trans_count.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_TRANS_COUNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_TRANS_COUNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -61,20 +33,15 @@ impl W { The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_trans_count](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_TRANS_COUNT_SPEC; impl crate::RegisterSpec for CH_TRANS_COUNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_trans_count::R](R) reader structure"] -impl crate::Readable for CH_TRANS_COUNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_trans_count::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_trans_count::W`](W) writer structure"] impl crate::Writable for CH_TRANS_COUNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch/ch_write_addr.rs b/src/dma/ch/ch_write_addr.rs index a4a171720..106213df2 100644 --- a/src/dma/ch/ch_write_addr.rs +++ b/src/dma/ch/ch_write_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CH_WRITE_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH_WRITE_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Channel 0 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch_write_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_WRITE_ADDR_SPEC; impl crate::RegisterSpec for CH_WRITE_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch_write_addr::R](R) reader structure"] -impl crate::Readable for CH_WRITE_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch_write_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`ch_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_write_addr::W`](W) writer structure"] impl crate::Writable for CH_WRITE_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/dma/ch0_dbg_ctdreq.rs index 00dda2129..0531b2bdc 100644 --- a/src/dma/ch0_dbg_ctdreq.rs +++ b/src/dma/ch0_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH0_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH0_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0_DBG_CTDREQ` reader - "] pub type CH0_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH0_DBG_CTDREQ` writer - "] -pub type CH0_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH0_DBG_CTDREQ_SPEC, 6, O>; +pub type CH0_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch0_dbg_ctdreq(&mut self) -> CH0_DBG_CTDREQ_W<0> { + pub fn ch0_dbg_ctdreq(&mut self) -> CH0_DBG_CTDREQ_W { CH0_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch0_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH0_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH0_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch0_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH0_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch0_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch0_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH0_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH0_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch0_dbg_tcr.rs b/src/dma/ch0_dbg_tcr.rs index ca8560172..d8541f097 100644 --- a/src/dma/ch0_dbg_tcr.rs +++ b/src/dma/ch0_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH0_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch0_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH0_DBG_TCR_SPEC; impl crate::RegisterSpec for CH0_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch0_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH0_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch0_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH0_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH0_DBG_TCR to value 0"] impl crate::Resettable for CH0_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/dma/ch10_dbg_ctdreq.rs index 52a23d319..4b90824af 100644 --- a/src/dma/ch10_dbg_ctdreq.rs +++ b/src/dma/ch10_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH10_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH10_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH10_DBG_CTDREQ` reader - "] pub type CH10_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH10_DBG_CTDREQ` writer - "] -pub type CH10_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH10_DBG_CTDREQ_SPEC, 6, O>; +pub type CH10_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch10_dbg_ctdreq(&mut self) -> CH10_DBG_CTDREQ_W<0> { + pub fn ch10_dbg_ctdreq(&mut self) -> CH10_DBG_CTDREQ_W { CH10_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch10_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH10_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH10_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch10_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH10_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch10_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch10_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH10_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH10_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch10_dbg_tcr.rs b/src/dma/ch10_dbg_tcr.rs index a4575c14a..9044f305a 100644 --- a/src/dma/ch10_dbg_tcr.rs +++ b/src/dma/ch10_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH10_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch10_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH10_DBG_TCR_SPEC; impl crate::RegisterSpec for CH10_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch10_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH10_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch10_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH10_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH10_DBG_TCR to value 0"] impl crate::Resettable for CH10_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/dma/ch11_dbg_ctdreq.rs index 6bdba5181..23a65daf2 100644 --- a/src/dma/ch11_dbg_ctdreq.rs +++ b/src/dma/ch11_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH11_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH11_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH11_DBG_CTDREQ` reader - "] pub type CH11_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH11_DBG_CTDREQ` writer - "] -pub type CH11_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH11_DBG_CTDREQ_SPEC, 6, O>; +pub type CH11_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch11_dbg_ctdreq(&mut self) -> CH11_DBG_CTDREQ_W<0> { + pub fn ch11_dbg_ctdreq(&mut self) -> CH11_DBG_CTDREQ_W { CH11_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch11_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH11_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH11_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch11_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH11_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch11_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch11_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH11_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH11_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch11_dbg_tcr.rs b/src/dma/ch11_dbg_tcr.rs index 6d4949cf6..18c5f495d 100644 --- a/src/dma/ch11_dbg_tcr.rs +++ b/src/dma/ch11_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH11_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch11_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH11_DBG_TCR_SPEC; impl crate::RegisterSpec for CH11_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch11_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH11_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch11_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH11_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH11_DBG_TCR to value 0"] impl crate::Resettable for CH11_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/dma/ch1_dbg_ctdreq.rs index 9829eeeb8..a18b83b29 100644 --- a/src/dma/ch1_dbg_ctdreq.rs +++ b/src/dma/ch1_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH1_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH1_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH1_DBG_CTDREQ` reader - "] pub type CH1_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH1_DBG_CTDREQ` writer - "] -pub type CH1_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH1_DBG_CTDREQ_SPEC, 6, O>; +pub type CH1_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch1_dbg_ctdreq(&mut self) -> CH1_DBG_CTDREQ_W<0> { + pub fn ch1_dbg_ctdreq(&mut self) -> CH1_DBG_CTDREQ_W { CH1_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch1_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH1_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH1_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch1_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH1_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch1_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch1_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH1_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH1_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch1_dbg_tcr.rs b/src/dma/ch1_dbg_tcr.rs index f347cbd88..3ef5a19ad 100644 --- a/src/dma/ch1_dbg_tcr.rs +++ b/src/dma/ch1_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH1_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch1_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH1_DBG_TCR_SPEC; impl crate::RegisterSpec for CH1_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch1_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH1_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch1_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH1_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH1_DBG_TCR to value 0"] impl crate::Resettable for CH1_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/dma/ch2_dbg_ctdreq.rs index 1bd7450c8..e742ded7a 100644 --- a/src/dma/ch2_dbg_ctdreq.rs +++ b/src/dma/ch2_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH2_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH2_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH2_DBG_CTDREQ` reader - "] pub type CH2_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH2_DBG_CTDREQ` writer - "] -pub type CH2_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH2_DBG_CTDREQ_SPEC, 6, O>; +pub type CH2_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch2_dbg_ctdreq(&mut self) -> CH2_DBG_CTDREQ_W<0> { + pub fn ch2_dbg_ctdreq(&mut self) -> CH2_DBG_CTDREQ_W { CH2_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch2_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH2_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH2_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch2_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH2_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch2_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch2_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH2_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH2_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch2_dbg_tcr.rs b/src/dma/ch2_dbg_tcr.rs index 35735d15c..1967e9439 100644 --- a/src/dma/ch2_dbg_tcr.rs +++ b/src/dma/ch2_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH2_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch2_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH2_DBG_TCR_SPEC; impl crate::RegisterSpec for CH2_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch2_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH2_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch2_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH2_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH2_DBG_TCR to value 0"] impl crate::Resettable for CH2_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/dma/ch3_dbg_ctdreq.rs index 74335f4d4..74df261d5 100644 --- a/src/dma/ch3_dbg_ctdreq.rs +++ b/src/dma/ch3_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH3_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH3_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH3_DBG_CTDREQ` reader - "] pub type CH3_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH3_DBG_CTDREQ` writer - "] -pub type CH3_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH3_DBG_CTDREQ_SPEC, 6, O>; +pub type CH3_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch3_dbg_ctdreq(&mut self) -> CH3_DBG_CTDREQ_W<0> { + pub fn ch3_dbg_ctdreq(&mut self) -> CH3_DBG_CTDREQ_W { CH3_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch3_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH3_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH3_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch3_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH3_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch3_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch3_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH3_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH3_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch3_dbg_tcr.rs b/src/dma/ch3_dbg_tcr.rs index 2b3aa5c63..533105fda 100644 --- a/src/dma/ch3_dbg_tcr.rs +++ b/src/dma/ch3_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH3_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch3_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH3_DBG_TCR_SPEC; impl crate::RegisterSpec for CH3_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch3_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH3_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch3_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH3_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH3_DBG_TCR to value 0"] impl crate::Resettable for CH3_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/dma/ch4_dbg_ctdreq.rs index 16a833dc9..12ce1d456 100644 --- a/src/dma/ch4_dbg_ctdreq.rs +++ b/src/dma/ch4_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH4_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH4_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH4_DBG_CTDREQ` reader - "] pub type CH4_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH4_DBG_CTDREQ` writer - "] -pub type CH4_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH4_DBG_CTDREQ_SPEC, 6, O>; +pub type CH4_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch4_dbg_ctdreq(&mut self) -> CH4_DBG_CTDREQ_W<0> { + pub fn ch4_dbg_ctdreq(&mut self) -> CH4_DBG_CTDREQ_W { CH4_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch4_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH4_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH4_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch4_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH4_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch4_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch4_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH4_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH4_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch4_dbg_tcr.rs b/src/dma/ch4_dbg_tcr.rs index 70d4178d4..cb046e8b6 100644 --- a/src/dma/ch4_dbg_tcr.rs +++ b/src/dma/ch4_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH4_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch4_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH4_DBG_TCR_SPEC; impl crate::RegisterSpec for CH4_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch4_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH4_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch4_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH4_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH4_DBG_TCR to value 0"] impl crate::Resettable for CH4_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/dma/ch5_dbg_ctdreq.rs index 73426d1b1..98f36c5fa 100644 --- a/src/dma/ch5_dbg_ctdreq.rs +++ b/src/dma/ch5_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH5_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH5_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH5_DBG_CTDREQ` reader - "] pub type CH5_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH5_DBG_CTDREQ` writer - "] -pub type CH5_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH5_DBG_CTDREQ_SPEC, 6, O>; +pub type CH5_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch5_dbg_ctdreq(&mut self) -> CH5_DBG_CTDREQ_W<0> { + pub fn ch5_dbg_ctdreq(&mut self) -> CH5_DBG_CTDREQ_W { CH5_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch5_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH5_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH5_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch5_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH5_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch5_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch5_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH5_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH5_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch5_dbg_tcr.rs b/src/dma/ch5_dbg_tcr.rs index fd066b5c1..6f387c42f 100644 --- a/src/dma/ch5_dbg_tcr.rs +++ b/src/dma/ch5_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH5_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch5_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH5_DBG_TCR_SPEC; impl crate::RegisterSpec for CH5_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch5_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH5_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch5_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH5_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH5_DBG_TCR to value 0"] impl crate::Resettable for CH5_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/dma/ch6_dbg_ctdreq.rs index 07e2e0a14..2e54b870e 100644 --- a/src/dma/ch6_dbg_ctdreq.rs +++ b/src/dma/ch6_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH6_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH6_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH6_DBG_CTDREQ` reader - "] pub type CH6_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH6_DBG_CTDREQ` writer - "] -pub type CH6_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH6_DBG_CTDREQ_SPEC, 6, O>; +pub type CH6_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch6_dbg_ctdreq(&mut self) -> CH6_DBG_CTDREQ_W<0> { + pub fn ch6_dbg_ctdreq(&mut self) -> CH6_DBG_CTDREQ_W { CH6_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch6_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH6_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH6_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch6_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH6_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch6_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch6_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH6_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH6_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch6_dbg_tcr.rs b/src/dma/ch6_dbg_tcr.rs index fa6a84181..cbb7b14a5 100644 --- a/src/dma/ch6_dbg_tcr.rs +++ b/src/dma/ch6_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH6_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch6_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH6_DBG_TCR_SPEC; impl crate::RegisterSpec for CH6_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch6_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH6_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch6_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH6_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH6_DBG_TCR to value 0"] impl crate::Resettable for CH6_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/dma/ch7_dbg_ctdreq.rs index f67cd23b6..8b7dba356 100644 --- a/src/dma/ch7_dbg_ctdreq.rs +++ b/src/dma/ch7_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH7_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH7_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH7_DBG_CTDREQ` reader - "] pub type CH7_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH7_DBG_CTDREQ` writer - "] -pub type CH7_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH7_DBG_CTDREQ_SPEC, 6, O>; +pub type CH7_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch7_dbg_ctdreq(&mut self) -> CH7_DBG_CTDREQ_W<0> { + pub fn ch7_dbg_ctdreq(&mut self) -> CH7_DBG_CTDREQ_W { CH7_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch7_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH7_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH7_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch7_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH7_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch7_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch7_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH7_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH7_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch7_dbg_tcr.rs b/src/dma/ch7_dbg_tcr.rs index cbe13e027..1d748a66a 100644 --- a/src/dma/ch7_dbg_tcr.rs +++ b/src/dma/ch7_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH7_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch7_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH7_DBG_TCR_SPEC; impl crate::RegisterSpec for CH7_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch7_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH7_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch7_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH7_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH7_DBG_TCR to value 0"] impl crate::Resettable for CH7_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/dma/ch8_dbg_ctdreq.rs index 61d1261a6..8141a304d 100644 --- a/src/dma/ch8_dbg_ctdreq.rs +++ b/src/dma/ch8_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH8_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH8_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH8_DBG_CTDREQ` reader - "] pub type CH8_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH8_DBG_CTDREQ` writer - "] -pub type CH8_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH8_DBG_CTDREQ_SPEC, 6, O>; +pub type CH8_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch8_dbg_ctdreq(&mut self) -> CH8_DBG_CTDREQ_W<0> { + pub fn ch8_dbg_ctdreq(&mut self) -> CH8_DBG_CTDREQ_W { CH8_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch8_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH8_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH8_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch8_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH8_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch8_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch8_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH8_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH8_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch8_dbg_tcr.rs b/src/dma/ch8_dbg_tcr.rs index 869f3c290..931568641 100644 --- a/src/dma/ch8_dbg_tcr.rs +++ b/src/dma/ch8_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH8_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch8_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH8_DBG_TCR_SPEC; impl crate::RegisterSpec for CH8_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch8_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH8_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch8_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH8_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH8_DBG_TCR to value 0"] impl crate::Resettable for CH8_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/dma/ch9_dbg_ctdreq.rs index 5b4017834..a6829a402 100644 --- a/src/dma/ch9_dbg_ctdreq.rs +++ b/src/dma/ch9_dbg_ctdreq.rs @@ -1,43 +1,11 @@ #[doc = "Register `CH9_DBG_CTDREQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CH9_DBG_CTDREQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH9_DBG_CTDREQ` reader - "] pub type CH9_DBG_CTDREQ_R = crate::FieldReader; #[doc = "Field `CH9_DBG_CTDREQ` writer - "] -pub type CH9_DBG_CTDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CH9_DBG_CTDREQ_SPEC, 6, O>; +pub type CH9_DBG_CTDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn ch9_dbg_ctdreq(&mut self) -> CH9_DBG_CTDREQ_W<0> { + pub fn ch9_dbg_ctdreq(&mut self) -> CH9_DBG_CTDREQ_W { CH9_DBG_CTDREQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch9_dbg_ctdreq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_ctdreq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH9_DBG_CTDREQ_SPEC; impl crate::RegisterSpec for CH9_DBG_CTDREQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch9_dbg_ctdreq::R](R) reader structure"] -impl crate::Readable for CH9_DBG_CTDREQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ch9_dbg_ctdreq::W](W) writer structure"] +#[doc = "`read()` method returns [`ch9_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH9_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH9_DBG_CTDREQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x3f; } diff --git a/src/dma/ch9_dbg_tcr.rs b/src/dma/ch9_dbg_tcr.rs index 865ffd0d1..3dd89798e 100644 --- a/src/dma/ch9_dbg_tcr.rs +++ b/src/dma/ch9_dbg_tcr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CH9_DBG_TCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ch9_dbg_tcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH9_DBG_TCR_SPEC; impl crate::RegisterSpec for CH9_DBG_TCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ch9_dbg_tcr::R](R) reader structure"] -impl crate::Readable for CH9_DBG_TCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ch9_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH9_DBG_TCR_SPEC {} #[doc = "`reset()` method sets CH9_DBG_TCR to value 0"] impl crate::Resettable for CH9_DBG_TCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs index 382f47c65..7d49cfb77 100644 --- a/src/dma/chan_abort.rs +++ b/src/dma/chan_abort.rs @@ -1,39 +1,7 @@ #[doc = "Register `CHAN_ABORT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CHAN_ABORT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHAN_ABORT` reader - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] @@ -41,7 +9,7 @@ pub type CHAN_ABORT_R = crate::FieldReader; #[doc = "Field `CHAN_ABORT` writer - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] -pub type CHAN_ABORT_W<'a, const O: u8> = crate::FieldWriter<'a, CHAN_ABORT_SPEC, 16, O, u16>; +pub type CHAN_ABORT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. @@ -57,32 +25,31 @@ impl W { After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] #[must_use] - pub fn chan_abort(&mut self) -> CHAN_ABORT_W<0> { + pub fn chan_abort(&mut self) -> CHAN_ABORT_W { CHAN_ABORT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Abort an in-progress transfer sequence on one or more channels -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [chan_abort](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`chan_abort::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_abort::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHAN_ABORT_SPEC; impl crate::RegisterSpec for CHAN_ABORT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chan_abort::R](R) reader structure"] -impl crate::Readable for CHAN_ABORT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [chan_abort::W](W) writer structure"] +#[doc = "`read()` method returns [`chan_abort::R`](R) reader structure"] +impl crate::Readable for CHAN_ABORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chan_abort::W`](W) writer structure"] impl crate::Writable for CHAN_ABORT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/fifo_levels.rs b/src/dma/fifo_levels.rs index da486b904..56ea001ba 100644 --- a/src/dma/fifo_levels.rs +++ b/src/dma/fifo_levels.rs @@ -1,18 +1,5 @@ #[doc = "Register `FIFO_LEVELS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TDF_LVL` reader - Current Transfer-Data-FIFO fill level"] pub type TDF_LVL_R = crate::FieldReader; #[doc = "Field `WAF_LVL` reader - Current Write-Address-FIFO fill level"] @@ -38,17 +25,13 @@ impl R { } #[doc = "Debug RAF, WAF, TDF levels -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fifo_levels](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_LEVELS_SPEC; impl crate::RegisterSpec for FIFO_LEVELS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo_levels::R](R) reader structure"] -impl crate::Readable for FIFO_LEVELS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fifo_levels::R`](R) reader structure"] +impl crate::Readable for FIFO_LEVELS_SPEC {} #[doc = "`reset()` method sets FIFO_LEVELS to value 0"] impl crate::Resettable for FIFO_LEVELS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/inte0.rs b/src/dma/inte0.rs index 1987e955b..e14ea01b2 100644 --- a/src/dma/inte0.rs +++ b/src/dma/inte0.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTE0` reader - Set bit n to pass interrupts from channel n to DMA IRQ 0."] pub type INTE0_R = crate::FieldReader; #[doc = "Field `INTE0` writer - Set bit n to pass interrupts from channel n to DMA IRQ 0."] -pub type INTE0_W<'a, const O: u8> = crate::FieldWriter<'a, INTE0_SPEC, 16, O, u16>; +pub type INTE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0."] #[inline(always)] #[must_use] - pub fn inte0(&mut self) -> INTE0_W<0> { + pub fn inte0(&mut self) -> INTE0_W { INTE0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enables for IRQ 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE0_SPEC; impl crate::RegisterSpec for INTE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte0::R](R) reader structure"] -impl crate::Readable for INTE0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte0::W](W) writer structure"] +#[doc = "`read()` method returns [`inte0::R`](R) reader structure"] +impl crate::Readable for INTE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte0::W`](W) writer structure"] impl crate::Writable for INTE0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/inte1.rs b/src/dma/inte1.rs index daf0143f3..004a02530 100644 --- a/src/dma/inte1.rs +++ b/src/dma/inte1.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTE1` reader - Set bit n to pass interrupts from channel n to DMA IRQ 1."] pub type INTE1_R = crate::FieldReader; #[doc = "Field `INTE1` writer - Set bit n to pass interrupts from channel n to DMA IRQ 1."] -pub type INTE1_W<'a, const O: u8> = crate::FieldWriter<'a, INTE1_SPEC, 16, O, u16>; +pub type INTE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1."] #[inline(always)] #[must_use] - pub fn inte1(&mut self) -> INTE1_W<0> { + pub fn inte1(&mut self) -> INTE1_W { INTE1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enables for IRQ 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE1_SPEC; impl crate::RegisterSpec for INTE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte1::R](R) reader structure"] -impl crate::Readable for INTE1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte1::W](W) writer structure"] +#[doc = "`read()` method returns [`inte1::R`](R) reader structure"] +impl crate::Readable for INTE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte1::W`](W) writer structure"] impl crate::Writable for INTE1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/intf0.rs b/src/dma/intf0.rs index 21906d245..d2011ef09 100644 --- a/src/dma/intf0.rs +++ b/src/dma/intf0.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTF0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTF0` reader - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] pub type INTF0_R = crate::FieldReader; #[doc = "Field `INTF0` writer - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] -pub type INTF0_W<'a, const O: u8> = crate::FieldWriter<'a, INTF0_SPEC, 16, O, u16>; +pub type INTF0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] #[inline(always)] #[must_use] - pub fn intf0(&mut self) -> INTF0_W<0> { + pub fn intf0(&mut self) -> INTF0_W { INTF0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Force Interrupts -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF0_SPEC; impl crate::RegisterSpec for INTF0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf0::R](R) reader structure"] -impl crate::Readable for INTF0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf0::W](W) writer structure"] +#[doc = "`read()` method returns [`intf0::R`](R) reader structure"] +impl crate::Readable for INTF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf0::W`](W) writer structure"] impl crate::Writable for INTF0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/intf1.rs b/src/dma/intf1.rs index 57c4948ed..6a6f5f673 100644 --- a/src/dma/intf1.rs +++ b/src/dma/intf1.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTF1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTF1` reader - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] pub type INTF1_R = crate::FieldReader; #[doc = "Field `INTF1` writer - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] -pub type INTF1_W<'a, const O: u8> = crate::FieldWriter<'a, INTF1_SPEC, 16, O, u16>; +pub type INTF1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] #[inline(always)] #[must_use] - pub fn intf1(&mut self) -> INTF1_W<0> { + pub fn intf1(&mut self) -> INTF1_W { INTF1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Force Interrupts for IRQ 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF1_SPEC; impl crate::RegisterSpec for INTF1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf1::R](R) reader structure"] -impl crate::Readable for INTF1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf1::W](W) writer structure"] +#[doc = "`read()` method returns [`intf1::R`](R) reader structure"] +impl crate::Readable for INTF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf1::W`](W) writer structure"] impl crate::Writable for INTF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/intr.rs b/src/dma/intr.rs index a3f3a7f92..b64e1a840 100644 --- a/src/dma/intr.rs +++ b/src/dma/intr.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTR` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. @@ -49,7 +17,7 @@ pub type INTR_R = crate::FieldReader; This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] -pub type INTR_W<'a, const O: u8> = crate::FieldWriter<'a, INTR_SPEC, 16, O, u16>; +pub type INTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. @@ -73,32 +41,31 @@ impl W { It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<0> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Status (raw) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intr::W](W) writer structure"] +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff; } diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs index b837c8c60..781fb0087 100644 --- a/src/dma/ints0.rs +++ b/src/dma/ints0.rs @@ -1,45 +1,13 @@ #[doc = "Register `INTS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTS0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTS0` reader - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS0_R = crate::FieldReader; #[doc = "Field `INTS0` writer - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] -pub type INTS0_W<'a, const O: u8> = crate::FieldWriter<'a, INTS0_SPEC, 16, O, u16>; +pub type INTS0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] @@ -53,32 +21,31 @@ impl W { Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] #[must_use] - pub fn ints0(&mut self) -> INTS0_W<0> { + pub fn ints0(&mut self) -> INTS0_W { INTS0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Status for IRQ 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS0_SPEC; impl crate::RegisterSpec for INTS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints0::R](R) reader structure"] -impl crate::Readable for INTS0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ints0::W](W) writer structure"] +#[doc = "`read()` method returns [`ints0::R`](R) reader structure"] +impl crate::Readable for INTS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints0::W`](W) writer structure"] impl crate::Writable for INTS0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff; } diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs index 55eb042b8..bd22db920 100644 --- a/src/dma/ints1.rs +++ b/src/dma/ints1.rs @@ -1,45 +1,13 @@ #[doc = "Register `INTS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTS1` reader - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS1_R = crate::FieldReader; #[doc = "Field `INTS1` writer - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] -pub type INTS1_W<'a, const O: u8> = crate::FieldWriter<'a, INTS1_SPEC, 16, O, u16>; +pub type INTS1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] @@ -53,32 +21,31 @@ impl W { Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] #[must_use] - pub fn ints1(&mut self) -> INTS1_W<0> { + pub fn ints1(&mut self) -> INTS1_W { INTS1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Status (masked) for IRQ 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS1_SPEC; impl crate::RegisterSpec for INTS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints1::R](R) reader structure"] -impl crate::Readable for INTS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ints1::W](W) writer structure"] +#[doc = "`read()` method returns [`ints1::R`](R) reader structure"] +impl crate::Readable for INTS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints1::W`](W) writer structure"] impl crate::Writable for INTS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff; } diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs index efda8cfaa..7c38d2245 100644 --- a/src/dma/multi_chan_trigger.rs +++ b/src/dma/multi_chan_trigger.rs @@ -1,44 +1,11 @@ #[doc = "Register `MULTI_CHAN_TRIGGER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MULTI_CHAN_TRIGGER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MULTI_CHAN_TRIGGER` reader - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] pub type MULTI_CHAN_TRIGGER_R = crate::FieldReader; #[doc = "Field `MULTI_CHAN_TRIGGER` writer - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] -pub type MULTI_CHAN_TRIGGER_W<'a, const O: u8> = - crate::FieldWriter<'a, MULTI_CHAN_TRIGGER_SPEC, 16, O, u16>; +pub type MULTI_CHAN_TRIGGER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] #[inline(always)] @@ -50,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] #[inline(always)] #[must_use] - pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W<0> { + pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W { MULTI_CHAN_TRIGGER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Trigger one or more channels simultaneously -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [multi_chan_trigger](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`multi_chan_trigger::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`multi_chan_trigger::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MULTI_CHAN_TRIGGER_SPEC; impl crate::RegisterSpec for MULTI_CHAN_TRIGGER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [multi_chan_trigger::R](R) reader structure"] -impl crate::Readable for MULTI_CHAN_TRIGGER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [multi_chan_trigger::W](W) writer structure"] +#[doc = "`read()` method returns [`multi_chan_trigger::R`](R) reader structure"] +impl crate::Readable for MULTI_CHAN_TRIGGER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`multi_chan_trigger::W`](W) writer structure"] impl crate::Writable for MULTI_CHAN_TRIGGER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/n_channels.rs b/src/dma/n_channels.rs index fbf2f7808..16337bda9 100644 --- a/src/dma/n_channels.rs +++ b/src/dma/n_channels.rs @@ -1,18 +1,5 @@ #[doc = "Register `N_CHANNELS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `N_CHANNELS` reader - "] pub type N_CHANNELS_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [n_channels](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct N_CHANNELS_SPEC; impl crate::RegisterSpec for N_CHANNELS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [n_channels::R](R) reader structure"] -impl crate::Readable for N_CHANNELS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`n_channels::R`](R) reader structure"] +impl crate::Readable for N_CHANNELS_SPEC {} #[doc = "`reset()` method sets N_CHANNELS to value 0"] impl crate::Resettable for N_CHANNELS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs index 25f4dcb6b..903116af0 100644 --- a/src/dma/sniff_ctrl.rs +++ b/src/dma/sniff_ctrl.rs @@ -1,47 +1,15 @@ #[doc = "Register `SNIFF_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SNIFF_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - Enable sniffer"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Enable sniffer"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, SNIFF_CTRL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMACH` reader - DMA channel for Sniffer to observe"] pub type DMACH_R = crate::FieldReader; #[doc = "Field `DMACH` writer - DMA channel for Sniffer to observe"] -pub type DMACH_W<'a, const O: u8> = crate::FieldWriter<'a, SNIFF_CTRL_SPEC, 4, O>; +pub type DMACH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CALC` reader - "] pub type CALC_R = crate::FieldReader; #[doc = " @@ -75,7 +43,7 @@ impl crate::FieldSpec for CALC_A { impl CALC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(CALC_A::CRC32), 1 => Some(CALC_A::CRC32R), @@ -86,68 +54,72 @@ impl CALC_R { _ => None, } } - #[doc = "Checks if the value of the field is `CRC32`"] + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] #[inline(always)] pub fn is_crc32(&self) -> bool { *self == CALC_A::CRC32 } - #[doc = "Checks if the value of the field is `CRC32R`"] + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] #[inline(always)] pub fn is_crc32r(&self) -> bool { *self == CALC_A::CRC32R } - #[doc = "Checks if the value of the field is `CRC16`"] + #[doc = "Calculate a CRC-16-CCITT"] #[inline(always)] pub fn is_crc16(&self) -> bool { *self == CALC_A::CRC16 } - #[doc = "Checks if the value of the field is `CRC16R`"] + #[doc = "Calculate a CRC-16-CCITT with bit reversed data"] #[inline(always)] pub fn is_crc16r(&self) -> bool { *self == CALC_A::CRC16R } - #[doc = "Checks if the value of the field is `EVEN`"] + #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."] #[inline(always)] pub fn is_even(&self) -> bool { *self == CALC_A::EVEN } - #[doc = "Checks if the value of the field is `SUM`"] + #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"] #[inline(always)] pub fn is_sum(&self) -> bool { *self == CALC_A::SUM } } #[doc = "Field `CALC` writer - "] -pub type CALC_W<'a, const O: u8> = crate::FieldWriter<'a, SNIFF_CTRL_SPEC, 4, O, CALC_A>; -impl<'a, const O: u8> CALC_W<'a, O> { +pub type CALC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, CALC_A>; +impl<'a, REG, const O: u8> CALC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] #[inline(always)] - pub fn crc32(self) -> &'a mut W { + pub fn crc32(self) -> &'a mut crate::W { self.variant(CALC_A::CRC32) } #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] #[inline(always)] - pub fn crc32r(self) -> &'a mut W { + pub fn crc32r(self) -> &'a mut crate::W { self.variant(CALC_A::CRC32R) } #[doc = "Calculate a CRC-16-CCITT"] #[inline(always)] - pub fn crc16(self) -> &'a mut W { + pub fn crc16(self) -> &'a mut crate::W { self.variant(CALC_A::CRC16) } #[doc = "Calculate a CRC-16-CCITT with bit reversed data"] #[inline(always)] - pub fn crc16r(self) -> &'a mut W { + pub fn crc16r(self) -> &'a mut crate::W { self.variant(CALC_A::CRC16R) } #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."] #[inline(always)] - pub fn even(self) -> &'a mut W { + pub fn even(self) -> &'a mut crate::W { self.variant(CALC_A::EVEN) } #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"] #[inline(always)] - pub fn sum(self) -> &'a mut W { + pub fn sum(self) -> &'a mut crate::W { self.variant(CALC_A::SUM) } } @@ -158,15 +130,15 @@ pub type BSWAP_R = crate::BitReader; #[doc = "Field `BSWAP` writer - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] -pub type BSWAP_W<'a, const O: u8> = crate::BitWriter<'a, SNIFF_CTRL_SPEC, O>; +pub type BSWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_REV` reader - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] pub type OUT_REV_R = crate::BitReader; #[doc = "Field `OUT_REV` writer - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] -pub type OUT_REV_W<'a, const O: u8> = crate::BitWriter<'a, SNIFF_CTRL_SPEC, O>; +pub type OUT_REV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_INV` reader - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] pub type OUT_INV_R = crate::BitReader; #[doc = "Field `OUT_INV` writer - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] -pub type OUT_INV_W<'a, const O: u8> = crate::BitWriter<'a, SNIFF_CTRL_SPEC, O>; +pub type OUT_INV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable sniffer"] #[inline(always)] @@ -205,19 +177,19 @@ impl W { #[doc = "Bit 0 - Enable sniffer"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bits 1:4 - DMA channel for Sniffer to observe"] #[inline(always)] #[must_use] - pub fn dmach(&mut self) -> DMACH_W<1> { + pub fn dmach(&mut self) -> DMACH_W { DMACH_W::new(self) } #[doc = "Bits 5:8"] #[inline(always)] #[must_use] - pub fn calc(&mut self) -> CALC_W<5> { + pub fn calc(&mut self) -> CALC_W { CALC_W::new(self) } #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. @@ -225,44 +197,43 @@ impl W { Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] #[inline(always)] #[must_use] - pub fn bswap(&mut self) -> BSWAP_W<9> { + pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self) } #[doc = "Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] #[inline(always)] #[must_use] - pub fn out_rev(&mut self) -> OUT_REV_W<10> { + pub fn out_rev(&mut self) -> OUT_REV_W { OUT_REV_W::new(self) } #[doc = "Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] #[inline(always)] #[must_use] - pub fn out_inv(&mut self) -> OUT_INV_W<11> { + pub fn out_inv(&mut self) -> OUT_INV_W { OUT_INV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Sniffer Control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sniff_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sniff_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SNIFF_CTRL_SPEC; impl crate::RegisterSpec for SNIFF_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sniff_ctrl::R](R) reader structure"] -impl crate::Readable for SNIFF_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sniff_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`sniff_ctrl::R`](R) reader structure"] +impl crate::Readable for SNIFF_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sniff_ctrl::W`](W) writer structure"] impl crate::Writable for SNIFF_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/sniff_data.rs b/src/dma/sniff_data.rs index ddc31c6d4..e93716594 100644 --- a/src/dma/sniff_data.rs +++ b/src/dma/sniff_data.rs @@ -1,39 +1,7 @@ #[doc = "Register `SNIFF_DATA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SNIFF_DATA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sniff_data](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SNIFF_DATA_SPEC; impl crate::RegisterSpec for SNIFF_DATA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sniff_data::R](R) reader structure"] -impl crate::Readable for SNIFF_DATA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sniff_data::W](W) writer structure"] +#[doc = "`read()` method returns [`sniff_data::R`](R) reader structure"] +impl crate::Readable for SNIFF_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sniff_data::W`](W) writer structure"] impl crate::Writable for SNIFF_DATA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs index 078ed8b5f..cb7be0207 100644 --- a/src/dma/timer0.rs +++ b/src/dma/timer0.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIMER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub type Y_R = crate::FieldReader; #[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] -pub type Y_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER0_SPEC, 16, O, u16>; +pub type Y_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub type X_R = crate::FieldReader; #[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] -pub type X_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER0_SPEC, 16, O, u16>; +pub type X_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] @@ -58,39 +26,38 @@ impl W { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn y(&mut self) -> Y_W<0> { + pub fn y(&mut self) -> Y_W { Y_W::new(self) } #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn x(&mut self) -> X_W<16> { + pub fn x(&mut self) -> X_W { X_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timer0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER0_SPEC; impl crate::RegisterSpec for TIMER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timer0::R](R) reader structure"] -impl crate::Readable for TIMER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timer0::W](W) writer structure"] +#[doc = "`read()` method returns [`timer0::R`](R) reader structure"] +impl crate::Readable for TIMER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer0::W`](W) writer structure"] impl crate::Writable for TIMER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs index eca674c15..1a76a78f9 100644 --- a/src/dma/timer1.rs +++ b/src/dma/timer1.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIMER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub type Y_R = crate::FieldReader; #[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] -pub type Y_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER1_SPEC, 16, O, u16>; +pub type Y_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub type X_R = crate::FieldReader; #[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] -pub type X_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER1_SPEC, 16, O, u16>; +pub type X_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] @@ -58,39 +26,38 @@ impl W { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn y(&mut self) -> Y_W<0> { + pub fn y(&mut self) -> Y_W { Y_W::new(self) } #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn x(&mut self) -> X_W<16> { + pub fn x(&mut self) -> X_W { X_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timer1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER1_SPEC; impl crate::RegisterSpec for TIMER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timer1::R](R) reader structure"] -impl crate::Readable for TIMER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timer1::W](W) writer structure"] +#[doc = "`read()` method returns [`timer1::R`](R) reader structure"] +impl crate::Readable for TIMER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"] impl crate::Writable for TIMER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs index 64c7f8bcd..da61bb1d1 100644 --- a/src/dma/timer2.rs +++ b/src/dma/timer2.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIMER2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub type Y_R = crate::FieldReader; #[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] -pub type Y_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER2_SPEC, 16, O, u16>; +pub type Y_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub type X_R = crate::FieldReader; #[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] -pub type X_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER2_SPEC, 16, O, u16>; +pub type X_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] @@ -58,39 +26,38 @@ impl W { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn y(&mut self) -> Y_W<0> { + pub fn y(&mut self) -> Y_W { Y_W::new(self) } #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn x(&mut self) -> X_W<16> { + pub fn x(&mut self) -> X_W { X_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timer2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER2_SPEC; impl crate::RegisterSpec for TIMER2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timer2::R](R) reader structure"] -impl crate::Readable for TIMER2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timer2::W](W) writer structure"] +#[doc = "`read()` method returns [`timer2::R`](R) reader structure"] +impl crate::Readable for TIMER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer2::W`](W) writer structure"] impl crate::Writable for TIMER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs index dfa39d217..ea2c29090 100644 --- a/src/dma/timer3.rs +++ b/src/dma/timer3.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIMER3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMER3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub type Y_R = crate::FieldReader; #[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] -pub type Y_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER3_SPEC, 16, O, u16>; +pub type Y_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub type X_R = crate::FieldReader; #[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] -pub type X_W<'a, const O: u8> = crate::FieldWriter<'a, TIMER3_SPEC, 16, O, u16>; +pub type X_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] @@ -58,39 +26,38 @@ impl W { #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn y(&mut self) -> Y_W<0> { + pub fn y(&mut self) -> Y_W { Y_W::new(self) } #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] #[inline(always)] #[must_use] - pub fn x(&mut self) -> X_W<16> { + pub fn x(&mut self) -> X_W { X_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timer3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER3_SPEC; impl crate::RegisterSpec for TIMER3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timer3::R](R) reader structure"] -impl crate::Readable for TIMER3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timer3::W](W) writer structure"] +#[doc = "`read()` method returns [`timer3::R`](R) reader structure"] +impl crate::Readable for TIMER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer3::W`](W) writer structure"] impl crate::Writable for TIMER3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/generic.rs b/src/generic.rs index a592894ec..247a6b37d 100644 --- a/src/generic.rs +++ b/src/generic.rs @@ -53,18 +53,13 @@ pub trait FieldSpec: Sized { #[doc = " Trait implemented by readable registers to enable the `read` method."] #[doc = ""] #[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec { - #[doc = " Result from a call to `read` and argument to `modify`."] - type Reader: From> + core::ops::Deref>; -} +pub trait Readable: RegisterSpec {} #[doc = " Trait implemented by writeable registers."] #[doc = ""] #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { - #[doc = " Writer type argument to `write`, et al."] - type Writer: From> + core::ops::DerefMut>; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -115,11 +110,11 @@ impl Reg { #[doc = " let flag = reader.field2().bit_is_set();"] #[doc = " ```"] #[inline(always)] - pub fn read(&self) -> REG::Reader { - REG::Reader::from(R { + pub fn read(&self) -> R { + R { bits: self.register.get(), _reg: marker::PhantomData, - }) + } } } impl Reg { @@ -156,14 +151,14 @@ impl Reg { #[inline(always)] pub fn write(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -179,13 +174,13 @@ impl Reg { #[inline(always)] pub unsafe fn write_with_zero(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::Ux::default(), _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -219,37 +214,36 @@ impl Reg { #[inline(always)] pub fn modify(&self, f: F) where - for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set( f( - ®::Reader::from(R { + &R { bits, _reg: marker::PhantomData, - }), - &mut REG::Writer::from(W { + }, + &mut W { bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - }), + }, ) .bits, ); } } +#[doc(hidden)] +pub mod raw; #[doc = " Register reader."] #[doc = ""] #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] #[doc = " method."] -pub struct R { - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} +pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -267,68 +261,17 @@ where #[doc = " Register writer."] #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc(hidden)] -pub struct FieldReaderRaw -where - FI: FieldSpec, -{ - pub(crate) bits: FI::Ux, - _reg: marker::PhantomData, -} -impl FieldReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: FI::Ux) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitReaderRaw { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} +pub type W = raw::W; #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] -pub type FieldReader = FieldReaderRaw; +pub type FieldReader = raw::FieldReader; #[doc = " Bit-wise field reader"] -pub type BitReader = BitReaderRaw; +pub type BitReader = raw::BitReader; impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> FI::Ux { + pub const fn bits(&self) -> FI::Ux { self.bits } } @@ -354,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -372,82 +315,64 @@ impl BitReader { pub struct Safe; #[doc(hidden)] pub struct Unsafe; -#[doc(hidden)] -pub struct FieldWriterRaw<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, Safety)>, -} -impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriterRaw<'a, REG, WI, O, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitWriterRaw<'a, REG, const O: u8, FI = bool, M = BitM> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, REG, const O: u8, FI, M> BitWriterRaw<'a, REG, O, FI, M> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} #[doc = " Write field Proxy with unsafe `bits`"] pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = - FieldWriterRaw<'a, REG, WI, O, FI, Unsafe>; + raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = - FieldWriterRaw<'a, REG, WI, O, FI, Safe>; + raw::FieldWriter<'a, REG, WI, O, FI, Safe>; impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, const O: u8, FI = bool> = BitWriterRaw<'a, REG, O, FI, $mwv>; + pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> where REG: Writable + RegisterSpec, @@ -455,26 +380,16 @@ macro_rules! bit_proxy { { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { #[doc = " Writes bit to the field"] #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut REG::Writer { + pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bit(bool::from(variant)) } } @@ -487,55 +402,6 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut REG::Writer { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut REG::Writer { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - self.bits(FI::Ux::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> where REG: Writable + RegisterSpec, @@ -543,13 +409,13 @@ where { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { + pub fn set_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { + pub fn clear_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -561,7 +427,7 @@ where { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { + pub fn set_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -573,7 +439,7 @@ where { #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { + pub fn clear_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -585,7 +451,7 @@ where { #[doc = "Clears the field bit by passing one"] #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + pub fn clear_bit_by_one(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -597,7 +463,7 @@ where { #[doc = "Sets the field bit by passing zero"] #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + pub fn set_bit_by_zero(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -609,7 +475,7 @@ where { #[doc = "Toggle the field bit by passing one"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { + pub fn toggle_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -621,7 +487,7 @@ where { #[doc = "Toggle the field bit by passing zero"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { + pub fn toggle_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } diff --git a/src/i2c0.rs b/src/i2c0.rs index 44080713d..9f745e3b3 100644 --- a/src/i2c0.rs +++ b/src/i2c0.rs @@ -164,14 +164,32 @@ has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling th #[doc = "0xfc - I2C Component Type Register"] pub ic_comp_type: IC_COMP_TYPE, } -#[doc = "IC_CON (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_con`] +module"] pub type IC_CON = crate::Reg; #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] pub mod ic_con; -#[doc = "IC_TAR (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_TAR (rw) register accessor: I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tar`] +module"] pub type IC_TAR = crate::Reg; #[doc = "I2C Target Address Register @@ -180,11 +198,25 @@ is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] pub mod ic_tar; -#[doc = "IC_SAR (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_SAR (rw) register accessor: I2C Slave Address Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sar`] +module"] pub type IC_SAR = crate::Reg; #[doc = "I2C Slave Address Register"] pub mod ic_sar; -#[doc = "IC_DATA_CMD (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_data_cmd`] +module"] pub type IC_DATA_CMD = crate::Reg; #[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. @@ -192,97 +224,217 @@ pub type IC_DATA_CMD = crate::Reg; Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] pub mod ic_data_cmd; -#[doc = "IC_SS_SCL_HCNT (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ss_scl_hcnt`] +module"] pub type IC_SS_SCL_HCNT = crate::Reg; #[doc = "Standard Speed I2C Clock SCL High Count Register"] pub mod ic_ss_scl_hcnt; -#[doc = "IC_SS_SCL_LCNT (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ss_scl_lcnt`] +module"] pub type IC_SS_SCL_LCNT = crate::Reg; #[doc = "Standard Speed I2C Clock SCL Low Count Register"] pub mod ic_ss_scl_lcnt; -#[doc = "IC_FS_SCL_HCNT (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_scl_hcnt`] +module"] pub type IC_FS_SCL_HCNT = crate::Reg; #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"] pub mod ic_fs_scl_hcnt; -#[doc = "IC_FS_SCL_LCNT (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_scl_lcnt`] +module"] pub type IC_FS_SCL_LCNT = crate::Reg; #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] pub mod ic_fs_scl_lcnt; -#[doc = "IC_INTR_STAT (r) register accessor: an alias for `Reg`"] +#[doc = "IC_INTR_STAT (r) register accessor: I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_intr_stat`] +module"] pub type IC_INTR_STAT = crate::Reg; #[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] pub mod ic_intr_stat; -#[doc = "IC_INTR_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_intr_mask`] +module"] pub type IC_INTR_MASK = crate::Reg; #[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] pub mod ic_intr_mask; -#[doc = "IC_RAW_INTR_STAT (r) register accessor: an alias for `Reg`"] +#[doc = "IC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_raw_intr_stat`] +module"] pub type IC_RAW_INTR_STAT = crate::Reg; #[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] pub mod ic_raw_intr_stat; -#[doc = "IC_RX_TL (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_rx_tl`] +module"] pub type IC_RX_TL = crate::Reg; #[doc = "I2C Receive FIFO Threshold Register"] pub mod ic_rx_tl; -#[doc = "IC_TX_TL (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tx_tl`] +module"] pub type IC_TX_TL = crate::Reg; #[doc = "I2C Transmit FIFO Threshold Register"] pub mod ic_tx_tl; -#[doc = "IC_CLR_INTR (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_intr`] +module"] pub type IC_CLR_INTR = crate::Reg; #[doc = "Clear Combined and Individual Interrupt Register"] pub mod ic_clr_intr; -#[doc = "IC_CLR_RX_UNDER (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_under`] +module"] pub type IC_CLR_RX_UNDER = crate::Reg; #[doc = "Clear RX_UNDER Interrupt Register"] pub mod ic_clr_rx_under; -#[doc = "IC_CLR_RX_OVER (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_over`] +module"] pub type IC_CLR_RX_OVER = crate::Reg; #[doc = "Clear RX_OVER Interrupt Register"] pub mod ic_clr_rx_over; -#[doc = "IC_CLR_TX_OVER (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_tx_over`] +module"] pub type IC_CLR_TX_OVER = crate::Reg; #[doc = "Clear TX_OVER Interrupt Register"] pub mod ic_clr_tx_over; -#[doc = "IC_CLR_RD_REQ (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rd_req`] +module"] pub type IC_CLR_RD_REQ = crate::Reg; #[doc = "Clear RD_REQ Interrupt Register"] pub mod ic_clr_rd_req; -#[doc = "IC_CLR_TX_ABRT (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_tx_abrt`] +module"] pub type IC_CLR_TX_ABRT = crate::Reg; #[doc = "Clear TX_ABRT Interrupt Register"] pub mod ic_clr_tx_abrt; -#[doc = "IC_CLR_RX_DONE (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_done`] +module"] pub type IC_CLR_RX_DONE = crate::Reg; #[doc = "Clear RX_DONE Interrupt Register"] pub mod ic_clr_rx_done; -#[doc = "IC_CLR_ACTIVITY (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_activity`] +module"] pub type IC_CLR_ACTIVITY = crate::Reg; #[doc = "Clear ACTIVITY Interrupt Register"] pub mod ic_clr_activity; -#[doc = "IC_CLR_STOP_DET (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_stop_det`] +module"] pub type IC_CLR_STOP_DET = crate::Reg; #[doc = "Clear STOP_DET Interrupt Register"] pub mod ic_clr_stop_det; -#[doc = "IC_CLR_START_DET (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_start_det`] +module"] pub type IC_CLR_START_DET = crate::Reg; #[doc = "Clear START_DET Interrupt Register"] pub mod ic_clr_start_det; -#[doc = "IC_CLR_GEN_CALL (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_gen_call`] +module"] pub type IC_CLR_GEN_CALL = crate::Reg; #[doc = "Clear GEN_CALL Interrupt Register"] pub mod ic_clr_gen_call; -#[doc = "IC_ENABLE (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_ENABLE (rw) register accessor: I2C Enable Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_enable`] +module"] pub type IC_ENABLE = crate::Reg; #[doc = "I2C Enable Register"] pub mod ic_enable; -#[doc = "IC_STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "IC_STATUS (r) register accessor: I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_status`] +module"] pub type IC_STATUS = crate::Reg; #[doc = "I2C Status Register @@ -290,15 +442,42 @@ pub type IC_STATUS = crate::Reg; When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] pub mod ic_status; -#[doc = "IC_TXFLR (r) register accessor: an alias for `Reg`"] +#[doc = "IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_txflr`] +module"] pub type IC_TXFLR = crate::Reg; #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] pub mod ic_txflr; -#[doc = "IC_RXFLR (r) register accessor: an alias for `Reg`"] +#[doc = "IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_rxflr`] +module"] pub type IC_RXFLR = crate::Reg; #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] pub mod ic_rxflr; -#[doc = "IC_SDA_HOLD (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register + + The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE\\[0\\]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sda_hold`] +module"] pub type IC_SDA_HOLD = crate::Reg; #[doc = "I2C SDA Hold Time Length Register @@ -314,7 +493,16 @@ of this register are used to extend the SDA transition (if any) whenever SCL is The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] pub mod ic_sda_hold; -#[doc = "IC_TX_ABRT_SOURCE (r) register accessor: an alias for `Reg`"] +#[doc = "IC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tx_abrt_source`] +module"] pub type IC_TX_ABRT_SOURCE = crate::Reg; #[doc = "I2C Transmit Abort Source Register @@ -322,7 +510,19 @@ pub type IC_TX_ABRT_SOURCE = crate::Reg; #[doc = "Generate Slave Data NACK Register @@ -333,21 +533,50 @@ pub type IC_SLV_DATA_NACK_ONLY = crate::Reg; #[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] pub mod ic_dma_cr; -#[doc = "IC_DMA_TDLR (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_dma_tdlr`] +module"] pub type IC_DMA_TDLR = crate::Reg; #[doc = "DMA Transmit Data Level Register"] pub mod ic_dma_tdlr; -#[doc = "IC_DMA_RDLR (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_dma_rdlr`] +module"] pub type IC_DMA_RDLR = crate::Reg; #[doc = "I2C Receive Data Level Register"] pub mod ic_dma_rdlr; -#[doc = "IC_SDA_SETUP (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. + + Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sda_setup`] +module"] pub type IC_SDA_SETUP = crate::Reg; #[doc = "I2C SDA Setup Register @@ -358,7 +587,16 @@ pub type IC_SDA_SETUP = crate::Reg; Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] pub mod ic_sda_setup; -#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ack_general_call`] +module"] pub type IC_ACK_GENERAL_CALL = crate::Reg; #[doc = "I2C ACK General Call Register @@ -366,7 +604,24 @@ pub type IC_ACK_GENERAL_CALL = crate::Reg; #[doc = "I2C Enable Status Register @@ -382,27 +637,56 @@ has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] pub mod ic_enable_status; -#[doc = "IC_FS_SPKLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_spklen`] +module"] pub type IC_FS_SPKLEN = crate::Reg; #[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] pub mod ic_fs_spklen; -#[doc = "IC_CLR_RESTART_DET (r) register accessor: an alias for `Reg`"] +#[doc = "IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_restart_det`] +module"] pub type IC_CLR_RESTART_DET = crate::Reg; #[doc = "Clear RESTART_DET Interrupt Register"] pub mod ic_clr_restart_det; -#[doc = "IC_COMP_PARAM_1 (r) register accessor: an alias for `Reg`"] +#[doc = "IC_COMP_PARAM_1 (r) register accessor: Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_param_1`] +module"] pub type IC_COMP_PARAM_1 = crate::Reg; #[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] pub mod ic_comp_param_1; -#[doc = "IC_COMP_VERSION (r) register accessor: an alias for `Reg`"] +#[doc = "IC_COMP_VERSION (r) register accessor: I2C Component Version Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_version`] +module"] pub type IC_COMP_VERSION = crate::Reg; #[doc = "I2C Component Version Register"] pub mod ic_comp_version; -#[doc = "IC_COMP_TYPE (r) register accessor: an alias for `Reg`"] +#[doc = "IC_COMP_TYPE (r) register accessor: I2C Component Type Register + +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_type`] +module"] pub type IC_COMP_TYPE = crate::Reg; #[doc = "I2C Component Type Register"] pub mod ic_comp_type; diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs index 61ec2c086..4ec24dfad 100644 --- a/src/i2c0/ic_ack_general_call.rs +++ b/src/i2c0/ic_ack_general_call.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_ACK_GENERAL_CALL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_ACK_GENERAL_CALL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACK_GEN_CALL` reader - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] pub type ACK_GEN_CALL_R = crate::BitReader; #[doc = "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). @@ -55,35 +23,37 @@ impl From for bool { impl ACK_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ACK_GEN_CALL_A { + pub const fn variant(&self) -> ACK_GEN_CALL_A { match self.bits { false => ACK_GEN_CALL_A::DISABLED, true => ACK_GEN_CALL_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Generate NACK for a General Call"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == ACK_GEN_CALL_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Generate ACK for a General Call"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == ACK_GEN_CALL_A::ENABLED } } #[doc = "Field `ACK_GEN_CALL` writer - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] -pub type ACK_GEN_CALL_W<'a, const O: u8> = - crate::BitWriter<'a, IC_ACK_GENERAL_CALL_SPEC, O, ACK_GEN_CALL_A>; -impl<'a, const O: u8> ACK_GEN_CALL_W<'a, O> { +pub type ACK_GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ACK_GEN_CALL_A>; +impl<'a, REG, const O: u8> ACK_GEN_CALL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Generate NACK for a General Call"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(ACK_GEN_CALL_A::DISABLED) } #[doc = "Generate ACK for a General Call"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(ACK_GEN_CALL_A::ENABLED) } } @@ -98,13 +68,17 @@ impl W { #[doc = "Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] #[inline(always)] #[must_use] - pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W<0> { + pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W { ACK_GEN_CALL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -114,20 +88,15 @@ impl W { This register is applicable only when the DW_apb_i2c is in slave mode. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_ack_general_call](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_ACK_GENERAL_CALL_SPEC; impl crate::RegisterSpec for IC_ACK_GENERAL_CALL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_ack_general_call::R](R) reader structure"] -impl crate::Readable for IC_ACK_GENERAL_CALL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_ack_general_call::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_ack_general_call::R`](R) reader structure"] +impl crate::Readable for IC_ACK_GENERAL_CALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ack_general_call::W`](W) writer structure"] impl crate::Writable for IC_ACK_GENERAL_CALL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_clr_activity.rs b/src/i2c0/ic_clr_activity.rs index 448ee5233..129fcbbb1 100644 --- a/src/i2c0/ic_clr_activity.rs +++ b/src/i2c0/ic_clr_activity.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_ACTIVITY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_ACTIVITY` reader - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear ACTIVITY Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_activity](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_ACTIVITY_SPEC; impl crate::RegisterSpec for IC_CLR_ACTIVITY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_activity::R](R) reader structure"] -impl crate::Readable for IC_CLR_ACTIVITY_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_activity::R`](R) reader structure"] +impl crate::Readable for IC_CLR_ACTIVITY_SPEC {} #[doc = "`reset()` method sets IC_CLR_ACTIVITY to value 0"] impl crate::Resettable for IC_CLR_ACTIVITY_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/i2c0/ic_clr_gen_call.rs index 90f5b0512..ed067ae56 100644 --- a/src/i2c0/ic_clr_gen_call.rs +++ b/src/i2c0/ic_clr_gen_call.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_GEN_CALL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_GEN_CALL` reader - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear GEN_CALL Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_gen_call](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_GEN_CALL_SPEC; impl crate::RegisterSpec for IC_CLR_GEN_CALL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_gen_call::R](R) reader structure"] -impl crate::Readable for IC_CLR_GEN_CALL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_gen_call::R`](R) reader structure"] +impl crate::Readable for IC_CLR_GEN_CALL_SPEC {} #[doc = "`reset()` method sets IC_CLR_GEN_CALL to value 0"] impl crate::Resettable for IC_CLR_GEN_CALL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_intr.rs b/src/i2c0/ic_clr_intr.rs index 83926262b..76a5f0dce 100644 --- a/src/i2c0/ic_clr_intr.rs +++ b/src/i2c0/ic_clr_intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_INTR` reader - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear Combined and Individual Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_INTR_SPEC; impl crate::RegisterSpec for IC_CLR_INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_intr::R](R) reader structure"] -impl crate::Readable for IC_CLR_INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_intr::R`](R) reader structure"] +impl crate::Readable for IC_CLR_INTR_SPEC {} #[doc = "`reset()` method sets IC_CLR_INTR to value 0"] impl crate::Resettable for IC_CLR_INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/i2c0/ic_clr_rd_req.rs index 013c4d7be..0beeccb94 100644 --- a/src/i2c0/ic_clr_rd_req.rs +++ b/src/i2c0/ic_clr_rd_req.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_RD_REQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_RD_REQ` reader - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear RD_REQ Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_rd_req](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RD_REQ_SPEC; impl crate::RegisterSpec for IC_CLR_RD_REQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_rd_req::R](R) reader structure"] -impl crate::Readable for IC_CLR_RD_REQ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_rd_req::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RD_REQ_SPEC {} #[doc = "`reset()` method sets IC_CLR_RD_REQ to value 0"] impl crate::Resettable for IC_CLR_RD_REQ_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/i2c0/ic_clr_restart_det.rs index e1433c5c1..59a0018d1 100644 --- a/src/i2c0/ic_clr_restart_det.rs +++ b/src/i2c0/ic_clr_restart_det.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_RESTART_DET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_RESTART_DET` reader - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear RESTART_DET Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_restart_det](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RESTART_DET_SPEC; impl crate::RegisterSpec for IC_CLR_RESTART_DET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_restart_det::R](R) reader structure"] -impl crate::Readable for IC_CLR_RESTART_DET_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_restart_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RESTART_DET_SPEC {} #[doc = "`reset()` method sets IC_CLR_RESTART_DET to value 0"] impl crate::Resettable for IC_CLR_RESTART_DET_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/i2c0/ic_clr_rx_done.rs index fd9af7a2c..fe07985c5 100644 --- a/src/i2c0/ic_clr_rx_done.rs +++ b/src/i2c0/ic_clr_rx_done.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_RX_DONE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_RX_DONE` reader - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear RX_DONE Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_rx_done](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_DONE_SPEC; impl crate::RegisterSpec for IC_CLR_RX_DONE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_rx_done::R](R) reader structure"] -impl crate::Readable for IC_CLR_RX_DONE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_rx_done::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_DONE_SPEC {} #[doc = "`reset()` method sets IC_CLR_RX_DONE to value 0"] impl crate::Resettable for IC_CLR_RX_DONE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/i2c0/ic_clr_rx_over.rs index efce5e536..db577fc38 100644 --- a/src/i2c0/ic_clr_rx_over.rs +++ b/src/i2c0/ic_clr_rx_over.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_RX_OVER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_RX_OVER` reader - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear RX_OVER Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_rx_over](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_OVER_SPEC; impl crate::RegisterSpec for IC_CLR_RX_OVER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_rx_over::R](R) reader structure"] -impl crate::Readable for IC_CLR_RX_OVER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_rx_over::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_OVER_SPEC {} #[doc = "`reset()` method sets IC_CLR_RX_OVER to value 0"] impl crate::Resettable for IC_CLR_RX_OVER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/i2c0/ic_clr_rx_under.rs index 8287ddaa9..dfe6e00e8 100644 --- a/src/i2c0/ic_clr_rx_under.rs +++ b/src/i2c0/ic_clr_rx_under.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_RX_UNDER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_RX_UNDER` reader - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear RX_UNDER Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_rx_under](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_UNDER_SPEC; impl crate::RegisterSpec for IC_CLR_RX_UNDER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_rx_under::R](R) reader structure"] -impl crate::Readable for IC_CLR_RX_UNDER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_rx_under::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_UNDER_SPEC {} #[doc = "`reset()` method sets IC_CLR_RX_UNDER to value 0"] impl crate::Resettable for IC_CLR_RX_UNDER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_start_det.rs b/src/i2c0/ic_clr_start_det.rs index c63f2e63a..1005f9f22 100644 --- a/src/i2c0/ic_clr_start_det.rs +++ b/src/i2c0/ic_clr_start_det.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_START_DET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_START_DET` reader - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear START_DET Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_start_det](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_START_DET_SPEC; impl crate::RegisterSpec for IC_CLR_START_DET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_start_det::R](R) reader structure"] -impl crate::Readable for IC_CLR_START_DET_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_start_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_START_DET_SPEC {} #[doc = "`reset()` method sets IC_CLR_START_DET to value 0"] impl crate::Resettable for IC_CLR_START_DET_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/i2c0/ic_clr_stop_det.rs index 904ed594d..02f606b37 100644 --- a/src/i2c0/ic_clr_stop_det.rs +++ b/src/i2c0/ic_clr_stop_det.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_STOP_DET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_STOP_DET` reader - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear STOP_DET Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_stop_det](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_STOP_DET_SPEC; impl crate::RegisterSpec for IC_CLR_STOP_DET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_stop_det::R](R) reader structure"] -impl crate::Readable for IC_CLR_STOP_DET_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_stop_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_STOP_DET_SPEC {} #[doc = "`reset()` method sets IC_CLR_STOP_DET to value 0"] impl crate::Resettable for IC_CLR_STOP_DET_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/i2c0/ic_clr_tx_abrt.rs index cff538f19..83818dedc 100644 --- a/src/i2c0/ic_clr_tx_abrt.rs +++ b/src/i2c0/ic_clr_tx_abrt.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_TX_ABRT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_TX_ABRT` reader - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear TX_ABRT Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_tx_abrt](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_TX_ABRT_SPEC; impl crate::RegisterSpec for IC_CLR_TX_ABRT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_tx_abrt::R](R) reader structure"] -impl crate::Readable for IC_CLR_TX_ABRT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_tx_abrt::R`](R) reader structure"] +impl crate::Readable for IC_CLR_TX_ABRT_SPEC {} #[doc = "`reset()` method sets IC_CLR_TX_ABRT to value 0"] impl crate::Resettable for IC_CLR_TX_ABRT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/i2c0/ic_clr_tx_over.rs index e99b9dd52..b214ea38d 100644 --- a/src/i2c0/ic_clr_tx_over.rs +++ b/src/i2c0/ic_clr_tx_over.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_CLR_TX_OVER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CLR_TX_OVER` reader - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "Clear TX_OVER Interrupt Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_clr_tx_over](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_TX_OVER_SPEC; impl crate::RegisterSpec for IC_CLR_TX_OVER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_clr_tx_over::R](R) reader structure"] -impl crate::Readable for IC_CLR_TX_OVER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_clr_tx_over::R`](R) reader structure"] +impl crate::Readable for IC_CLR_TX_OVER_SPEC {} #[doc = "`reset()` method sets IC_CLR_TX_OVER to value 0"] impl crate::Resettable for IC_CLR_TX_OVER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_comp_param_1.rs b/src/i2c0/ic_comp_param_1.rs index d6001b7f1..90873b5ad 100644 --- a/src/i2c0/ic_comp_param_1.rs +++ b/src/i2c0/ic_comp_param_1.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_COMP_PARAM_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `APB_DATA_WIDTH` reader - APB data bus width is 32 bits"] pub type APB_DATA_WIDTH_R = crate::FieldReader; #[doc = "Field `MAX_SPEED_MODE` reader - MAX SPEED MODE = FAST MODE"] @@ -75,17 +62,13 @@ impl R { Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_comp_param_1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_PARAM_1_SPEC; impl crate::RegisterSpec for IC_COMP_PARAM_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_comp_param_1::R](R) reader structure"] -impl crate::Readable for IC_COMP_PARAM_1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_comp_param_1::R`](R) reader structure"] +impl crate::Readable for IC_COMP_PARAM_1_SPEC {} #[doc = "`reset()` method sets IC_COMP_PARAM_1 to value 0"] impl crate::Resettable for IC_COMP_PARAM_1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_comp_type.rs b/src/i2c0/ic_comp_type.rs index c9295e454..9bf6aa032 100644 --- a/src/i2c0/ic_comp_type.rs +++ b/src/i2c0/ic_comp_type.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_COMP_TYPE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IC_COMP_TYPE` reader - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."] pub type IC_COMP_TYPE_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "I2C Component Type Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_comp_type](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_TYPE_SPEC; impl crate::RegisterSpec for IC_COMP_TYPE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_comp_type::R](R) reader structure"] -impl crate::Readable for IC_COMP_TYPE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_comp_type::R`](R) reader structure"] +impl crate::Readable for IC_COMP_TYPE_SPEC {} #[doc = "`reset()` method sets IC_COMP_TYPE to value 0x4457_0140"] impl crate::Resettable for IC_COMP_TYPE_SPEC { const RESET_VALUE: Self::Ux = 0x4457_0140; diff --git a/src/i2c0/ic_comp_version.rs b/src/i2c0/ic_comp_version.rs index 14702900b..d36e2121b 100644 --- a/src/i2c0/ic_comp_version.rs +++ b/src/i2c0/ic_comp_version.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_COMP_VERSION` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IC_COMP_VERSION` reader - "] pub type IC_COMP_VERSION_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "I2C Component Version Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_comp_version](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_VERSION_SPEC; impl crate::RegisterSpec for IC_COMP_VERSION_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_comp_version::R](R) reader structure"] -impl crate::Readable for IC_COMP_VERSION_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_comp_version::R`](R) reader structure"] +impl crate::Readable for IC_COMP_VERSION_SPEC {} #[doc = "`reset()` method sets IC_COMP_VERSION to value 0x3230_312a"] impl crate::Resettable for IC_COMP_VERSION_SPEC { const RESET_VALUE: Self::Ux = 0x3230_312a; diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs index dac20fb23..ab1759e2c 100644 --- a/src/i2c0/ic_con.rs +++ b/src/i2c0/ic_con.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_CON` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_CON` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] @@ -59,18 +27,18 @@ impl From for bool { impl MASTER_MODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MASTER_MODE_A { + pub const fn variant(&self) -> MASTER_MODE_A { match self.bits { false => MASTER_MODE_A::DISABLED, true => MASTER_MODE_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Master mode is disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == MASTER_MODE_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Master mode is enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == MASTER_MODE_A::ENABLED @@ -79,16 +47,19 @@ impl MASTER_MODE_R { #[doc = "Field `MASTER_MODE` writer - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] -pub type MASTER_MODE_W<'a, const O: u8> = crate::BitWriter<'a, IC_CON_SPEC, O, MASTER_MODE_A>; -impl<'a, const O: u8> MASTER_MODE_W<'a, O> { +pub type MASTER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MASTER_MODE_A>; +impl<'a, REG, const O: u8> MASTER_MODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Master mode is disabled"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(MASTER_MODE_A::DISABLED) } #[doc = "Master mode is enabled"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(MASTER_MODE_A::ENABLED) } } @@ -139,7 +110,7 @@ impl crate::FieldSpec for SPEED_A { impl SPEED_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(SPEED_A::STANDARD), 2 => Some(SPEED_A::FAST), @@ -147,17 +118,17 @@ impl SPEED_R { _ => None, } } - #[doc = "Checks if the value of the field is `STANDARD`"] + #[doc = "Standard Speed mode of operation"] #[inline(always)] pub fn is_standard(&self) -> bool { *self == SPEED_A::STANDARD } - #[doc = "Checks if the value of the field is `FAST`"] + #[doc = "Fast or Fast Plus mode of operation"] #[inline(always)] pub fn is_fast(&self) -> bool { *self == SPEED_A::FAST } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "High Speed mode of operation"] #[inline(always)] pub fn is_high(&self) -> bool { *self == SPEED_A::HIGH @@ -174,21 +145,25 @@ impl SPEED_R { 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] -pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, IC_CON_SPEC, 2, O, SPEED_A>; -impl<'a, const O: u8> SPEED_W<'a, O> { +pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SPEED_A>; +impl<'a, REG, const O: u8> SPEED_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Standard Speed mode of operation"] #[inline(always)] - pub fn standard(self) -> &'a mut W { + pub fn standard(self) -> &'a mut crate::W { self.variant(SPEED_A::STANDARD) } #[doc = "Fast or Fast Plus mode of operation"] #[inline(always)] - pub fn fast(self) -> &'a mut W { + pub fn fast(self) -> &'a mut crate::W { self.variant(SPEED_A::FAST) } #[doc = "High Speed mode of operation"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(SPEED_A::HIGH) } } @@ -213,35 +188,38 @@ impl From for bool { impl IC_10BITADDR_SLAVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IC_10BITADDR_SLAVE_A { + pub const fn variant(&self) -> IC_10BITADDR_SLAVE_A { match self.bits { false => IC_10BITADDR_SLAVE_A::ADDR_7BITS, true => IC_10BITADDR_SLAVE_A::ADDR_10BITS, } } - #[doc = "Checks if the value of the field is `ADDR_7BITS`"] + #[doc = "Slave 7Bit addressing"] #[inline(always)] pub fn is_addr_7bits(&self) -> bool { *self == IC_10BITADDR_SLAVE_A::ADDR_7BITS } - #[doc = "Checks if the value of the field is `ADDR_10BITS`"] + #[doc = "Slave 10Bit addressing"] #[inline(always)] pub fn is_addr_10bits(&self) -> bool { *self == IC_10BITADDR_SLAVE_A::ADDR_10BITS } } #[doc = "Field `IC_10BITADDR_SLAVE` writer - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] -pub type IC_10BITADDR_SLAVE_W<'a, const O: u8> = - crate::BitWriter<'a, IC_CON_SPEC, O, IC_10BITADDR_SLAVE_A>; -impl<'a, const O: u8> IC_10BITADDR_SLAVE_W<'a, O> { +pub type IC_10BITADDR_SLAVE_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, IC_10BITADDR_SLAVE_A>; +impl<'a, REG, const O: u8> IC_10BITADDR_SLAVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Slave 7Bit addressing"] #[inline(always)] - pub fn addr_7bits(self) -> &'a mut W { + pub fn addr_7bits(self) -> &'a mut crate::W { self.variant(IC_10BITADDR_SLAVE_A::ADDR_7BITS) } #[doc = "Slave 10Bit addressing"] #[inline(always)] - pub fn addr_10bits(self) -> &'a mut W { + pub fn addr_10bits(self) -> &'a mut crate::W { self.variant(IC_10BITADDR_SLAVE_A::ADDR_10BITS) } } @@ -266,35 +244,38 @@ impl From for bool { impl IC_10BITADDR_MASTER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IC_10BITADDR_MASTER_A { + pub const fn variant(&self) -> IC_10BITADDR_MASTER_A { match self.bits { false => IC_10BITADDR_MASTER_A::ADDR_7BITS, true => IC_10BITADDR_MASTER_A::ADDR_10BITS, } } - #[doc = "Checks if the value of the field is `ADDR_7BITS`"] + #[doc = "Master 7Bit addressing mode"] #[inline(always)] pub fn is_addr_7bits(&self) -> bool { *self == IC_10BITADDR_MASTER_A::ADDR_7BITS } - #[doc = "Checks if the value of the field is `ADDR_10BITS`"] + #[doc = "Master 10Bit addressing mode"] #[inline(always)] pub fn is_addr_10bits(&self) -> bool { *self == IC_10BITADDR_MASTER_A::ADDR_10BITS } } #[doc = "Field `IC_10BITADDR_MASTER` writer - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] -pub type IC_10BITADDR_MASTER_W<'a, const O: u8> = - crate::BitWriter<'a, IC_CON_SPEC, O, IC_10BITADDR_MASTER_A>; -impl<'a, const O: u8> IC_10BITADDR_MASTER_W<'a, O> { +pub type IC_10BITADDR_MASTER_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, IC_10BITADDR_MASTER_A>; +impl<'a, REG, const O: u8> IC_10BITADDR_MASTER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Master 7Bit addressing mode"] #[inline(always)] - pub fn addr_7bits(self) -> &'a mut W { + pub fn addr_7bits(self) -> &'a mut crate::W { self.variant(IC_10BITADDR_MASTER_A::ADDR_7BITS) } #[doc = "Master 10Bit addressing mode"] #[inline(always)] - pub fn addr_10bits(self) -> &'a mut W { + pub fn addr_10bits(self) -> &'a mut crate::W { self.variant(IC_10BITADDR_MASTER_A::ADDR_10BITS) } } @@ -323,18 +304,18 @@ impl From for bool { impl IC_RESTART_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IC_RESTART_EN_A { + pub const fn variant(&self) -> IC_RESTART_EN_A { match self.bits { false => IC_RESTART_EN_A::DISABLED, true => IC_RESTART_EN_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Master restart disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == IC_RESTART_EN_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Master restart enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == IC_RESTART_EN_A::ENABLED @@ -343,16 +324,19 @@ impl IC_RESTART_EN_R { #[doc = "Field `IC_RESTART_EN` writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] -pub type IC_RESTART_EN_W<'a, const O: u8> = crate::BitWriter<'a, IC_CON_SPEC, O, IC_RESTART_EN_A>; -impl<'a, const O: u8> IC_RESTART_EN_W<'a, O> { +pub type IC_RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, IC_RESTART_EN_A>; +impl<'a, REG, const O: u8> IC_RESTART_EN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Master restart disabled"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(IC_RESTART_EN_A::DISABLED) } #[doc = "Master restart enabled"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(IC_RESTART_EN_A::ENABLED) } } @@ -385,18 +369,18 @@ impl From for bool { impl IC_SLAVE_DISABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IC_SLAVE_DISABLE_A { + pub const fn variant(&self) -> IC_SLAVE_DISABLE_A { match self.bits { false => IC_SLAVE_DISABLE_A::SLAVE_ENABLED, true => IC_SLAVE_DISABLE_A::SLAVE_DISABLED, } } - #[doc = "Checks if the value of the field is `SLAVE_ENABLED`"] + #[doc = "Slave mode is enabled"] #[inline(always)] pub fn is_slave_enabled(&self) -> bool { *self == IC_SLAVE_DISABLE_A::SLAVE_ENABLED } - #[doc = "Checks if the value of the field is `SLAVE_DISABLED`"] + #[doc = "Slave mode is disabled"] #[inline(always)] pub fn is_slave_disabled(&self) -> bool { *self == IC_SLAVE_DISABLE_A::SLAVE_DISABLED @@ -407,17 +391,20 @@ impl IC_SLAVE_DISABLE_R { If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] -pub type IC_SLAVE_DISABLE_W<'a, const O: u8> = - crate::BitWriter<'a, IC_CON_SPEC, O, IC_SLAVE_DISABLE_A>; -impl<'a, const O: u8> IC_SLAVE_DISABLE_W<'a, O> { +pub type IC_SLAVE_DISABLE_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, IC_SLAVE_DISABLE_A>; +impl<'a, REG, const O: u8> IC_SLAVE_DISABLE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Slave mode is enabled"] #[inline(always)] - pub fn slave_enabled(self) -> &'a mut W { + pub fn slave_enabled(self) -> &'a mut crate::W { self.variant(IC_SLAVE_DISABLE_A::SLAVE_ENABLED) } #[doc = "Slave mode is disabled"] #[inline(always)] - pub fn slave_disabled(self) -> &'a mut W { + pub fn slave_disabled(self) -> &'a mut crate::W { self.variant(IC_SLAVE_DISABLE_A::SLAVE_DISABLED) } } @@ -446,18 +433,18 @@ impl From for bool { impl STOP_DET_IFADDRESSED_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> STOP_DET_IFADDRESSED_A { + pub const fn variant(&self) -> STOP_DET_IFADDRESSED_A { match self.bits { false => STOP_DET_IFADDRESSED_A::DISABLED, true => STOP_DET_IFADDRESSED_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "slave issues STOP_DET intr always"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == STOP_DET_IFADDRESSED_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "slave issues STOP_DET intr only if addressed"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == STOP_DET_IFADDRESSED_A::ENABLED @@ -466,17 +453,20 @@ impl STOP_DET_IFADDRESSED_R { #[doc = "Field `STOP_DET_IFADDRESSED` writer - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] -pub type STOP_DET_IFADDRESSED_W<'a, const O: u8> = - crate::BitWriter<'a, IC_CON_SPEC, O, STOP_DET_IFADDRESSED_A>; -impl<'a, const O: u8> STOP_DET_IFADDRESSED_W<'a, O> { +pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, STOP_DET_IFADDRESSED_A>; +impl<'a, REG, const O: u8> STOP_DET_IFADDRESSED_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "slave issues STOP_DET intr always"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(STOP_DET_IFADDRESSED_A::DISABLED) } #[doc = "slave issues STOP_DET intr only if addressed"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(STOP_DET_IFADDRESSED_A::ENABLED) } } @@ -505,18 +495,18 @@ impl From for bool { impl TX_EMPTY_CTRL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TX_EMPTY_CTRL_A { + pub const fn variant(&self) -> TX_EMPTY_CTRL_A { match self.bits { false => TX_EMPTY_CTRL_A::DISABLED, true => TX_EMPTY_CTRL_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Default behaviour of TX_EMPTY interrupt"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == TX_EMPTY_CTRL_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Controlled generation of TX_EMPTY interrupt"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == TX_EMPTY_CTRL_A::ENABLED @@ -525,16 +515,19 @@ impl TX_EMPTY_CTRL_R { #[doc = "Field `TX_EMPTY_CTRL` writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] -pub type TX_EMPTY_CTRL_W<'a, const O: u8> = crate::BitWriter<'a, IC_CON_SPEC, O, TX_EMPTY_CTRL_A>; -impl<'a, const O: u8> TX_EMPTY_CTRL_W<'a, O> { +pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TX_EMPTY_CTRL_A>; +impl<'a, REG, const O: u8> TX_EMPTY_CTRL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Default behaviour of TX_EMPTY interrupt"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(TX_EMPTY_CTRL_A::DISABLED) } #[doc = "Controlled generation of TX_EMPTY interrupt"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(TX_EMPTY_CTRL_A::ENABLED) } } @@ -563,18 +556,18 @@ impl From for bool { impl RX_FIFO_FULL_HLD_CTRL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RX_FIFO_FULL_HLD_CTRL_A { + pub const fn variant(&self) -> RX_FIFO_FULL_HLD_CTRL_A { match self.bits { false => RX_FIFO_FULL_HLD_CTRL_A::DISABLED, true => RX_FIFO_FULL_HLD_CTRL_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Overflow when RX_FIFO is full"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == RX_FIFO_FULL_HLD_CTRL_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Hold bus when RX_FIFO is full"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == RX_FIFO_FULL_HLD_CTRL_A::ENABLED @@ -583,17 +576,20 @@ impl RX_FIFO_FULL_HLD_CTRL_R { #[doc = "Field `RX_FIFO_FULL_HLD_CTRL` writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, const O: u8> = - crate::BitWriter<'a, IC_CON_SPEC, O, RX_FIFO_FULL_HLD_CTRL_A>; -impl<'a, const O: u8> RX_FIFO_FULL_HLD_CTRL_W<'a, O> { +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, RX_FIFO_FULL_HLD_CTRL_A>; +impl<'a, REG, const O: u8> RX_FIFO_FULL_HLD_CTRL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Overflow when RX_FIFO is full"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(RX_FIFO_FULL_HLD_CTRL_A::DISABLED) } #[doc = "Hold bus when RX_FIFO is full"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(RX_FIFO_FULL_HLD_CTRL_A::ENABLED) } } @@ -681,7 +677,7 @@ impl W { NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] #[inline(always)] #[must_use] - pub fn master_mode(&mut self) -> MASTER_MODE_W<0> { + pub fn master_mode(&mut self) -> MASTER_MODE_W { MASTER_MODE_W::new(self) } #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. @@ -697,19 +693,19 @@ impl W { Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W<1> { + pub fn speed(&mut self) -> SPEED_W { SPEED_W::new(self) } #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] #[inline(always)] #[must_use] - pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W<3> { + pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W { IC_10BITADDR_SLAVE_W::new(self) } #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] #[inline(always)] #[must_use] - pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W<4> { + pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W { IC_10BITADDR_MASTER_W::new(self) } #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. @@ -717,7 +713,7 @@ impl W { Reset value: ENABLED"] #[inline(always)] #[must_use] - pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W<5> { + pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W { IC_RESTART_EN_W::new(self) } #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. @@ -727,7 +723,7 @@ impl W { NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] #[inline(always)] #[must_use] - pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W<6> { + pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W { IC_SLAVE_DISABLE_W::new(self) } #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 @@ -735,7 +731,7 @@ impl W { NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W<7> { + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { STOP_DET_IFADDRESSED_W::new(self) } #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. @@ -743,7 +739,7 @@ impl W { Reset value: 0x0."] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W<8> { + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { TX_EMPTY_CTRL_W::new(self) } #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. @@ -751,13 +747,17 @@ impl W { Reset value: 0x0."] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W<9> { + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { RX_FIFO_FULL_HLD_CTRL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -766,20 +766,15 @@ register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_con](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CON_SPEC; impl crate::RegisterSpec for IC_CON_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_con::R](R) reader structure"] -impl crate::Readable for IC_CON_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_con::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_con::R`](R) reader structure"] +impl crate::Readable for IC_CON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"] impl crate::Writable for IC_CON_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs index 847ef88cf..5faac3c9d 100644 --- a/src/i2c0/ic_data_cmd.rs +++ b/src/i2c0/ic_data_cmd.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_DATA_CMD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_DATA_CMD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DAT` reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] @@ -41,7 +9,7 @@ pub type DAT_R = crate::FieldReader; #[doc = "Field `DAT` writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] -pub type DAT_W<'a, const O: u8> = crate::FieldWriter<'a, IC_DATA_CMD_SPEC, 8, O>; +pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CMD` reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. @@ -75,18 +43,18 @@ impl From for bool { impl CMD_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CMD_A { + pub const fn variant(&self) -> CMD_A { match self.bits { false => CMD_A::WRITE, true => CMD_A::READ, } } - #[doc = "Checks if the value of the field is `WRITE`"] + #[doc = "Master Write Command"] #[inline(always)] pub fn is_write(&self) -> bool { *self == CMD_A::WRITE } - #[doc = "Checks if the value of the field is `READ`"] + #[doc = "Master Read Command"] #[inline(always)] pub fn is_read(&self) -> bool { *self == CMD_A::READ @@ -99,16 +67,19 @@ impl CMD_R { When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] -pub type CMD_W<'a, const O: u8> = crate::BitWriter<'a, IC_DATA_CMD_SPEC, O, CMD_A>; -impl<'a, const O: u8> CMD_W<'a, O> { +pub type CMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CMD_A>; +impl<'a, REG, const O: u8> CMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Master Write Command"] #[inline(always)] - pub fn write(self) -> &'a mut W { + pub fn write(self) -> &'a mut crate::W { self.variant(CMD_A::WRITE) } #[doc = "Master Read Command"] #[inline(always)] - pub fn read(self) -> &'a mut W { + pub fn read(self) -> &'a mut crate::W { self.variant(CMD_A::READ) } } @@ -137,18 +108,18 @@ impl From for bool { impl STOP_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> STOP_A { + pub const fn variant(&self) -> STOP_A { match self.bits { false => STOP_A::DISABLE, true => STOP_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "Don't Issue STOP after this command"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == STOP_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "Issue STOP after this command"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == STOP_A::ENABLE @@ -157,16 +128,19 @@ impl STOP_R { #[doc = "Field `STOP` writer - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] -pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, IC_DATA_CMD_SPEC, O, STOP_A>; -impl<'a, const O: u8> STOP_W<'a, O> { +pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, STOP_A>; +impl<'a, REG, const O: u8> STOP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Don't Issue STOP after this command"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(STOP_A::DISABLE) } #[doc = "Issue STOP after this command"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(STOP_A::ENABLE) } } @@ -203,18 +177,18 @@ impl From for bool { impl RESTART_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RESTART_A { + pub const fn variant(&self) -> RESTART_A { match self.bits { false => RESTART_A::DISABLE, true => RESTART_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "Don't Issue RESTART before this command"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == RESTART_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "Issue RESTART before this command"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == RESTART_A::ENABLE @@ -227,16 +201,19 @@ impl RESTART_R { 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] -pub type RESTART_W<'a, const O: u8> = crate::BitWriter<'a, IC_DATA_CMD_SPEC, O, RESTART_A>; -impl<'a, const O: u8> RESTART_W<'a, O> { +pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RESTART_A>; +impl<'a, REG, const O: u8> RESTART_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Don't Issue RESTART before this command"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(RESTART_A::DISABLE) } #[doc = "Issue RESTART before this command"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(RESTART_A::ENABLE) } } @@ -287,18 +264,18 @@ impl From for bool { impl FIRST_DATA_BYTE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FIRST_DATA_BYTE_A { + pub const fn variant(&self) -> FIRST_DATA_BYTE_A { match self.bits { false => FIRST_DATA_BYTE_A::INACTIVE, true => FIRST_DATA_BYTE_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "Sequential data byte received"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == FIRST_DATA_BYTE_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Non sequential data byte received"] #[inline(always)] pub fn is_active(&self) -> bool { *self == FIRST_DATA_BYTE_A::ACTIVE @@ -366,7 +343,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W<0> { + pub fn dat(&mut self) -> DAT_W { DAT_W::new(self) } #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. @@ -378,7 +355,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn cmd(&mut self) -> CMD_W<8> { + pub fn cmd(&mut self) -> CMD_W { CMD_W::new(self) } #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. @@ -386,7 +363,7 @@ impl W { - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W<9> { + pub fn stop(&mut self) -> STOP_W { STOP_W::new(self) } #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. @@ -398,13 +375,17 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W<10> { + pub fn restart(&mut self) -> RESTART_W { RESTART_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -414,20 +395,15 @@ impl W { Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_data_cmd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DATA_CMD_SPEC; impl crate::RegisterSpec for IC_DATA_CMD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_data_cmd::R](R) reader structure"] -impl crate::Readable for IC_DATA_CMD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_data_cmd::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_data_cmd::R`](R) reader structure"] +impl crate::Readable for IC_DATA_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"] impl crate::Writable for IC_DATA_CMD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs index 21e97db76..fdbdece8c 100644 --- a/src/i2c0/ic_dma_cr.rs +++ b/src/i2c0/ic_dma_cr.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_DMA_CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_DMA_CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] pub type RDMAE_R = crate::BitReader; #[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 @@ -55,34 +23,37 @@ impl From for bool { impl RDMAE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RDMAE_A { + pub const fn variant(&self) -> RDMAE_A { match self.bits { false => RDMAE_A::DISABLED, true => RDMAE_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Receive FIFO DMA channel disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == RDMAE_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Receive FIFO DMA channel enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == RDMAE_A::ENABLED } } #[doc = "Field `RDMAE` writer - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] -pub type RDMAE_W<'a, const O: u8> = crate::BitWriter<'a, IC_DMA_CR_SPEC, O, RDMAE_A>; -impl<'a, const O: u8> RDMAE_W<'a, O> { +pub type RDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RDMAE_A>; +impl<'a, REG, const O: u8> RDMAE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Receive FIFO DMA channel disabled"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(RDMAE_A::DISABLED) } #[doc = "Receive FIFO DMA channel enabled"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(RDMAE_A::ENABLED) } } @@ -107,34 +78,37 @@ impl From for bool { impl TDMAE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TDMAE_A { + pub const fn variant(&self) -> TDMAE_A { match self.bits { false => TDMAE_A::DISABLED, true => TDMAE_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "transmit FIFO DMA channel disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == TDMAE_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Transmit FIFO DMA channel enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == TDMAE_A::ENABLED } } #[doc = "Field `TDMAE` writer - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] -pub type TDMAE_W<'a, const O: u8> = crate::BitWriter<'a, IC_DMA_CR_SPEC, O, TDMAE_A>; -impl<'a, const O: u8> TDMAE_W<'a, O> { +pub type TDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TDMAE_A>; +impl<'a, REG, const O: u8> TDMAE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "transmit FIFO DMA channel disabled"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(TDMAE_A::DISABLED) } #[doc = "Transmit FIFO DMA channel enabled"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(TDMAE_A::ENABLED) } } @@ -154,19 +128,23 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn rdmae(&mut self) -> RDMAE_W<0> { + pub fn rdmae(&mut self) -> RDMAE_W { RDMAE_W::new(self) } #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn tdmae(&mut self) -> TDMAE_W<1> { + pub fn tdmae(&mut self) -> TDMAE_W { TDMAE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -174,20 +152,15 @@ impl W { The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_dma_cr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DMA_CR_SPEC; impl crate::RegisterSpec for IC_DMA_CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_dma_cr::R](R) reader structure"] -impl crate::Readable for IC_DMA_CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_dma_cr::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_dma_cr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"] impl crate::Writable for IC_DMA_CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs index 01044aea6..64bd457e2 100644 --- a/src/i2c0/ic_dma_rdlr.rs +++ b/src/i2c0/ic_dma_rdlr.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_DMA_RDLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_DMA_RDLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMARDL` reader - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] @@ -41,7 +9,7 @@ pub type DMARDL_R = crate::FieldReader; #[doc = "Field `DMARDL` writer - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] -pub type DMARDL_W<'a, const O: u8> = crate::FieldWriter<'a, IC_DMA_RDLR_SPEC, 4, O>; +pub type DMARDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. @@ -57,32 +25,31 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn dmardl(&mut self) -> DMARDL_W<0> { + pub fn dmardl(&mut self) -> DMARDL_W { DMARDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "I2C Receive Data Level Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_dma_rdlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DMA_RDLR_SPEC; impl crate::RegisterSpec for IC_DMA_RDLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_dma_rdlr::R](R) reader structure"] -impl crate::Readable for IC_DMA_RDLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_dma_rdlr::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_dma_rdlr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_RDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"] impl crate::Writable for IC_DMA_RDLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs index ec8f9b414..114845ccc 100644 --- a/src/i2c0/ic_dma_tdlr.rs +++ b/src/i2c0/ic_dma_tdlr.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_DMA_TDLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_DMA_TDLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMATDL` reader - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] @@ -41,7 +9,7 @@ pub type DMATDL_R = crate::FieldReader; #[doc = "Field `DMATDL` writer - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] -pub type DMATDL_W<'a, const O: u8> = crate::FieldWriter<'a, IC_DMA_TDLR_SPEC, 4, O>; +pub type DMATDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. @@ -57,32 +25,31 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn dmatdl(&mut self) -> DMATDL_W<0> { + pub fn dmatdl(&mut self) -> DMATDL_W { DMATDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Transmit Data Level Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_dma_tdlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_tdlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DMA_TDLR_SPEC; impl crate::RegisterSpec for IC_DMA_TDLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_dma_tdlr::R](R) reader structure"] -impl crate::Readable for IC_DMA_TDLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_dma_tdlr::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_dma_tdlr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_TDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_tdlr::W`](W) writer structure"] impl crate::Writable for IC_DMA_TDLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs index 2c9054d77..c7c5866cf 100644 --- a/src/i2c0/ic_enable.rs +++ b/src/i2c0/ic_enable.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_ENABLE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_ENABLE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. @@ -67,18 +35,18 @@ impl From for bool { impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ENABLE_A { + pub const fn variant(&self) -> ENABLE_A { match self.bits { false => ENABLE_A::DISABLED, true => ENABLE_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "I2C is disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == ENABLE_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "I2C is enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == ENABLE_A::ENABLED @@ -91,16 +59,19 @@ impl ENABLE_R { In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, IC_ENABLE_SPEC, O, ENABLE_A>; -impl<'a, const O: u8> ENABLE_W<'a, O> { +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ENABLE_A>; +impl<'a, REG, const O: u8> ENABLE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "I2C is disabled"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(ENABLE_A::DISABLED) } #[doc = "I2C is enabled"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(ENABLE_A::ENABLED) } } @@ -133,18 +104,18 @@ impl From for bool { impl ABORT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABORT_A { + pub const fn variant(&self) -> ABORT_A { match self.bits { false => ABORT_A::DISABLE, true => ABORT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "ABORT operation not in progress"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == ABORT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "ABORT operation in progress"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == ABORT_A::ENABLED @@ -155,16 +126,19 @@ impl ABORT_R { For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] -pub type ABORT_W<'a, const O: u8> = crate::BitWriter<'a, IC_ENABLE_SPEC, O, ABORT_A>; -impl<'a, const O: u8> ABORT_W<'a, O> { +pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ABORT_A>; +impl<'a, REG, const O: u8> ABORT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "ABORT operation not in progress"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(ABORT_A::DISABLE) } #[doc = "ABORT operation in progress"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(ABORT_A::ENABLED) } } @@ -191,18 +165,18 @@ impl From for bool { impl TX_CMD_BLOCK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TX_CMD_BLOCK_A { + pub const fn variant(&self) -> TX_CMD_BLOCK_A { match self.bits { false => TX_CMD_BLOCK_A::NOT_BLOCKED, true => TX_CMD_BLOCK_A::BLOCKED, } } - #[doc = "Checks if the value of the field is `NOT_BLOCKED`"] + #[doc = "Tx Command execution not blocked"] #[inline(always)] pub fn is_not_blocked(&self) -> bool { *self == TX_CMD_BLOCK_A::NOT_BLOCKED } - #[doc = "Checks if the value of the field is `BLOCKED`"] + #[doc = "Tx Command execution blocked"] #[inline(always)] pub fn is_blocked(&self) -> bool { *self == TX_CMD_BLOCK_A::BLOCKED @@ -210,16 +184,19 @@ impl TX_CMD_BLOCK_R { } #[doc = "Field `TX_CMD_BLOCK` writer - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] -pub type TX_CMD_BLOCK_W<'a, const O: u8> = crate::BitWriter<'a, IC_ENABLE_SPEC, O, TX_CMD_BLOCK_A>; -impl<'a, const O: u8> TX_CMD_BLOCK_W<'a, O> { +pub type TX_CMD_BLOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TX_CMD_BLOCK_A>; +impl<'a, REG, const O: u8> TX_CMD_BLOCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Tx Command execution not blocked"] #[inline(always)] - pub fn not_blocked(self) -> &'a mut W { + pub fn not_blocked(self) -> &'a mut crate::W { self.variant(TX_CMD_BLOCK_A::NOT_BLOCKED) } #[doc = "Tx Command execution blocked"] #[inline(always)] - pub fn blocked(self) -> &'a mut W { + pub fn blocked(self) -> &'a mut crate::W { self.variant(TX_CMD_BLOCK_A::BLOCKED) } } @@ -261,7 +238,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. @@ -271,39 +248,38 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W<1> { + pub fn abort(&mut self) -> ABORT_W { ABORT_W::new(self) } #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] #[inline(always)] #[must_use] - pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W<2> { + pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { TX_CMD_BLOCK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "I2C Enable Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_enable](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_ENABLE_SPEC; impl crate::RegisterSpec for IC_ENABLE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_enable::R](R) reader structure"] -impl crate::Readable for IC_ENABLE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_enable::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_enable::R`](R) reader structure"] +impl crate::Readable for IC_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"] impl crate::Writable for IC_ENABLE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs index 7ea2b0dfa..2fc6c5691 100644 --- a/src/i2c0/ic_enable_status.rs +++ b/src/i2c0/ic_enable_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_ENABLE_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] @@ -38,18 +25,18 @@ impl From for bool { impl IC_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IC_EN_A { + pub const fn variant(&self) -> IC_EN_A { match self.bits { false => IC_EN_A::DISABLED, true => IC_EN_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "I2C disabled"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == IC_EN_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "I2C enabled"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == IC_EN_A::ENABLED @@ -110,18 +97,18 @@ impl From for bool { impl SLV_DISABLED_WHILE_BUSY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SLV_DISABLED_WHILE_BUSY_A { + pub const fn variant(&self) -> SLV_DISABLED_WHILE_BUSY_A { match self.bits { false => SLV_DISABLED_WHILE_BUSY_A::INACTIVE, true => SLV_DISABLED_WHILE_BUSY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "Slave is disabled when it is idle"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == SLV_DISABLED_WHILE_BUSY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Slave is disabled when it is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == SLV_DISABLED_WHILE_BUSY_A::ACTIVE @@ -166,18 +153,18 @@ impl From for bool { impl SLV_RX_DATA_LOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SLV_RX_DATA_LOST_A { + pub const fn variant(&self) -> SLV_RX_DATA_LOST_A { match self.bits { false => SLV_RX_DATA_LOST_A::INACTIVE, true => SLV_RX_DATA_LOST_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "Slave RX Data is not lost"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == SLV_RX_DATA_LOST_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Slave RX Data is lost"] #[inline(always)] pub fn is_active(&self) -> bool { *self == SLV_RX_DATA_LOST_A::ACTIVE @@ -242,17 +229,13 @@ has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_enable_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_ENABLE_STATUS_SPEC; impl crate::RegisterSpec for IC_ENABLE_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_enable_status::R](R) reader structure"] -impl crate::Readable for IC_ENABLE_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"] +impl crate::Readable for IC_ENABLE_STATUS_SPEC {} #[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"] impl crate::Resettable for IC_ENABLE_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs index 7d6c70d62..0607beaee 100644 --- a/src/i2c0/ic_fs_scl_hcnt.rs +++ b/src/i2c0/ic_fs_scl_hcnt.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_FS_SCL_HCNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_FS_SCL_HCNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_FS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] @@ -47,8 +15,7 @@ pub type IC_FS_SCL_HCNT_R = crate::FieldReader; register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] -pub type IC_FS_SCL_HCNT_W<'a, const O: u8> = - crate::FieldWriter<'a, IC_FS_SCL_HCNT_SPEC, 16, O, u16>; +pub type IC_FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. @@ -70,32 +37,31 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] #[inline(always)] #[must_use] - pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W<0> { + pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W { IC_FS_SCL_HCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_fs_scl_hcnt](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_FS_SCL_HCNT_SPEC; impl crate::RegisterSpec for IC_FS_SCL_HCNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_fs_scl_hcnt::R](R) reader structure"] -impl crate::Readable for IC_FS_SCL_HCNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_fs_scl_hcnt::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_fs_scl_hcnt::R`](R) reader structure"] +impl crate::Readable for IC_FS_SCL_HCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_scl_hcnt::W`](W) writer structure"] impl crate::Writable for IC_FS_SCL_HCNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs index db3e990a7..0f6f2f69d 100644 --- a/src/i2c0/ic_fs_scl_lcnt.rs +++ b/src/i2c0/ic_fs_scl_lcnt.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_FS_SCL_LCNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_FS_SCL_LCNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_FS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. @@ -51,8 +19,7 @@ pub type IC_FS_SCL_LCNT_R = crate::FieldReader; register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] -pub type IC_FS_SCL_LCNT_W<'a, const O: u8> = - crate::FieldWriter<'a, IC_FS_SCL_LCNT_SPEC, 16, O, u16>; +pub type IC_FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. @@ -78,32 +45,31 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] #[inline(always)] #[must_use] - pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W<0> { + pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W { IC_FS_SCL_LCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_fs_scl_lcnt](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_FS_SCL_LCNT_SPEC; impl crate::RegisterSpec for IC_FS_SCL_LCNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_fs_scl_lcnt::R](R) reader structure"] -impl crate::Readable for IC_FS_SCL_LCNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_fs_scl_lcnt::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_fs_scl_lcnt::R`](R) reader structure"] +impl crate::Readable for IC_FS_SCL_LCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"] impl crate::Writable for IC_FS_SCL_LCNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs index 704149a64..0a7c127c4 100644 --- a/src/i2c0/ic_fs_spklen.rs +++ b/src/i2c0/ic_fs_spklen.rs @@ -1,45 +1,13 @@ #[doc = "Register `IC_FS_SPKLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_FS_SPKLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_FS_SPKLEN` reader - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] pub type IC_FS_SPKLEN_R = crate::FieldReader; #[doc = "Field `IC_FS_SPKLEN` writer - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] -pub type IC_FS_SPKLEN_W<'a, const O: u8> = crate::FieldWriter<'a, IC_FS_SPKLEN_SPEC, 8, O>; +pub type IC_FS_SPKLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] @@ -53,13 +21,17 @@ impl W { register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] #[inline(always)] #[must_use] - pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W<0> { + pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W { IC_FS_SPKLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -67,20 +39,15 @@ register being set to 0. Writes at other times have no effect. The minimum valid This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_fs_spklen](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_FS_SPKLEN_SPEC; impl crate::RegisterSpec for IC_FS_SPKLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_fs_spklen::R](R) reader structure"] -impl crate::Readable for IC_FS_SPKLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_fs_spklen::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_fs_spklen::R`](R) reader structure"] +impl crate::Readable for IC_FS_SPKLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_spklen::W`](W) writer structure"] impl crate::Writable for IC_FS_SPKLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs index 2e3b31c02..db46b26ab 100644 --- a/src/i2c0/ic_intr_mask.rs +++ b/src/i2c0/ic_intr_mask.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_INTR_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_INTR_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] @@ -59,18 +27,18 @@ impl From for bool { impl M_RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RX_UNDER_A { + pub const fn variant(&self) -> M_RX_UNDER_A { match self.bits { false => M_RX_UNDER_A::ENABLED, true => M_RX_UNDER_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RX_UNDER interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RX_UNDER_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RX_UNDER interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RX_UNDER_A::DISABLED @@ -79,16 +47,19 @@ impl M_RX_UNDER_R { #[doc = "Field `M_RX_UNDER` writer - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_RX_UNDER_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RX_UNDER_A>; -impl<'a, const O: u8> M_RX_UNDER_W<'a, O> { +pub type M_RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RX_UNDER_A>; +impl<'a, REG, const O: u8> M_RX_UNDER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RX_UNDER interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RX_UNDER_A::ENABLED) } #[doc = "RX_UNDER interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RX_UNDER_A::DISABLED) } } @@ -117,18 +88,18 @@ impl From for bool { impl M_RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RX_OVER_A { + pub const fn variant(&self) -> M_RX_OVER_A { match self.bits { false => M_RX_OVER_A::ENABLED, true => M_RX_OVER_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RX_OVER interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RX_OVER_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RX_OVER interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RX_OVER_A::DISABLED @@ -137,16 +108,19 @@ impl M_RX_OVER_R { #[doc = "Field `M_RX_OVER` writer - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_RX_OVER_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RX_OVER_A>; -impl<'a, const O: u8> M_RX_OVER_W<'a, O> { +pub type M_RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RX_OVER_A>; +impl<'a, REG, const O: u8> M_RX_OVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RX_OVER interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RX_OVER_A::ENABLED) } #[doc = "RX_OVER interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RX_OVER_A::DISABLED) } } @@ -175,18 +149,18 @@ impl From for bool { impl M_RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RX_FULL_A { + pub const fn variant(&self) -> M_RX_FULL_A { match self.bits { false => M_RX_FULL_A::ENABLED, true => M_RX_FULL_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RX_FULL interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RX_FULL_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RX_FULL interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RX_FULL_A::DISABLED @@ -195,16 +169,19 @@ impl M_RX_FULL_R { #[doc = "Field `M_RX_FULL` writer - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RX_FULL_A>; -impl<'a, const O: u8> M_RX_FULL_W<'a, O> { +pub type M_RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RX_FULL_A>; +impl<'a, REG, const O: u8> M_RX_FULL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RX_FULL interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RX_FULL_A::ENABLED) } #[doc = "RX_FULL interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RX_FULL_A::DISABLED) } } @@ -233,18 +210,18 @@ impl From for bool { impl M_TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_TX_OVER_A { + pub const fn variant(&self) -> M_TX_OVER_A { match self.bits { false => M_TX_OVER_A::ENABLED, true => M_TX_OVER_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "TX_OVER interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_TX_OVER_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "TX_OVER interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_TX_OVER_A::DISABLED @@ -253,16 +230,19 @@ impl M_TX_OVER_R { #[doc = "Field `M_TX_OVER` writer - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_TX_OVER_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_TX_OVER_A>; -impl<'a, const O: u8> M_TX_OVER_W<'a, O> { +pub type M_TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_TX_OVER_A>; +impl<'a, REG, const O: u8> M_TX_OVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "TX_OVER interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_TX_OVER_A::ENABLED) } #[doc = "TX_OVER interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_TX_OVER_A::DISABLED) } } @@ -291,18 +271,18 @@ impl From for bool { impl M_TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_TX_EMPTY_A { + pub const fn variant(&self) -> M_TX_EMPTY_A { match self.bits { false => M_TX_EMPTY_A::ENABLED, true => M_TX_EMPTY_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "TX_EMPTY interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_TX_EMPTY_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "TX_EMPTY interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_TX_EMPTY_A::DISABLED @@ -311,16 +291,19 @@ impl M_TX_EMPTY_R { #[doc = "Field `M_TX_EMPTY` writer - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_TX_EMPTY_A>; -impl<'a, const O: u8> M_TX_EMPTY_W<'a, O> { +pub type M_TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_TX_EMPTY_A>; +impl<'a, REG, const O: u8> M_TX_EMPTY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "TX_EMPTY interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_TX_EMPTY_A::ENABLED) } #[doc = "TX_EMPTY interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_TX_EMPTY_A::DISABLED) } } @@ -349,18 +332,18 @@ impl From for bool { impl M_RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RD_REQ_A { + pub const fn variant(&self) -> M_RD_REQ_A { match self.bits { false => M_RD_REQ_A::ENABLED, true => M_RD_REQ_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RD_REQ interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RD_REQ_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RD_REQ interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RD_REQ_A::DISABLED @@ -369,16 +352,19 @@ impl M_RD_REQ_R { #[doc = "Field `M_RD_REQ` writer - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_RD_REQ_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RD_REQ_A>; -impl<'a, const O: u8> M_RD_REQ_W<'a, O> { +pub type M_RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RD_REQ_A>; +impl<'a, REG, const O: u8> M_RD_REQ_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RD_REQ interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RD_REQ_A::ENABLED) } #[doc = "RD_REQ interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RD_REQ_A::DISABLED) } } @@ -407,18 +393,18 @@ impl From for bool { impl M_TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_TX_ABRT_A { + pub const fn variant(&self) -> M_TX_ABRT_A { match self.bits { false => M_TX_ABRT_A::ENABLED, true => M_TX_ABRT_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "TX_ABORT interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_TX_ABRT_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "TX_ABORT interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_TX_ABRT_A::DISABLED @@ -427,16 +413,19 @@ impl M_TX_ABRT_R { #[doc = "Field `M_TX_ABRT` writer - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_TX_ABRT_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_TX_ABRT_A>; -impl<'a, const O: u8> M_TX_ABRT_W<'a, O> { +pub type M_TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_TX_ABRT_A>; +impl<'a, REG, const O: u8> M_TX_ABRT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "TX_ABORT interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_TX_ABRT_A::ENABLED) } #[doc = "TX_ABORT interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_TX_ABRT_A::DISABLED) } } @@ -465,18 +454,18 @@ impl From for bool { impl M_RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RX_DONE_A { + pub const fn variant(&self) -> M_RX_DONE_A { match self.bits { false => M_RX_DONE_A::ENABLED, true => M_RX_DONE_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RX_DONE interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RX_DONE_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RX_DONE interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RX_DONE_A::DISABLED @@ -485,16 +474,19 @@ impl M_RX_DONE_R { #[doc = "Field `M_RX_DONE` writer - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_RX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RX_DONE_A>; -impl<'a, const O: u8> M_RX_DONE_W<'a, O> { +pub type M_RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RX_DONE_A>; +impl<'a, REG, const O: u8> M_RX_DONE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RX_DONE interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RX_DONE_A::ENABLED) } #[doc = "RX_DONE interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RX_DONE_A::DISABLED) } } @@ -523,18 +515,18 @@ impl From for bool { impl M_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_ACTIVITY_A { + pub const fn variant(&self) -> M_ACTIVITY_A { match self.bits { false => M_ACTIVITY_A::ENABLED, true => M_ACTIVITY_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "ACTIVITY interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_ACTIVITY_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "ACTIVITY interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_ACTIVITY_A::DISABLED @@ -543,16 +535,19 @@ impl M_ACTIVITY_R { #[doc = "Field `M_ACTIVITY` writer - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] -pub type M_ACTIVITY_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_ACTIVITY_A>; -impl<'a, const O: u8> M_ACTIVITY_W<'a, O> { +pub type M_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_ACTIVITY_A>; +impl<'a, REG, const O: u8> M_ACTIVITY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "ACTIVITY interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_ACTIVITY_A::ENABLED) } #[doc = "ACTIVITY interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_ACTIVITY_A::DISABLED) } } @@ -581,18 +576,18 @@ impl From for bool { impl M_STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_STOP_DET_A { + pub const fn variant(&self) -> M_STOP_DET_A { match self.bits { false => M_STOP_DET_A::ENABLED, true => M_STOP_DET_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "STOP_DET interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_STOP_DET_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "STOP_DET interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_STOP_DET_A::DISABLED @@ -601,16 +596,19 @@ impl M_STOP_DET_R { #[doc = "Field `M_STOP_DET` writer - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] -pub type M_STOP_DET_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_STOP_DET_A>; -impl<'a, const O: u8> M_STOP_DET_W<'a, O> { +pub type M_STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_STOP_DET_A>; +impl<'a, REG, const O: u8> M_STOP_DET_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "STOP_DET interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_STOP_DET_A::ENABLED) } #[doc = "STOP_DET interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_STOP_DET_A::DISABLED) } } @@ -639,18 +637,18 @@ impl From for bool { impl M_START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_START_DET_A { + pub const fn variant(&self) -> M_START_DET_A { match self.bits { false => M_START_DET_A::ENABLED, true => M_START_DET_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "START_DET interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_START_DET_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "START_DET interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_START_DET_A::DISABLED @@ -659,16 +657,19 @@ impl M_START_DET_R { #[doc = "Field `M_START_DET` writer - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] -pub type M_START_DET_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_START_DET_A>; -impl<'a, const O: u8> M_START_DET_W<'a, O> { +pub type M_START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_START_DET_A>; +impl<'a, REG, const O: u8> M_START_DET_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "START_DET interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_START_DET_A::ENABLED) } #[doc = "START_DET interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_START_DET_A::DISABLED) } } @@ -697,18 +698,18 @@ impl From for bool { impl M_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_GEN_CALL_A { + pub const fn variant(&self) -> M_GEN_CALL_A { match self.bits { false => M_GEN_CALL_A::ENABLED, true => M_GEN_CALL_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "GEN_CALL interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_GEN_CALL_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "GEN_CALL interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_GEN_CALL_A::DISABLED @@ -717,16 +718,19 @@ impl M_GEN_CALL_R { #[doc = "Field `M_GEN_CALL` writer - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] -pub type M_GEN_CALL_W<'a, const O: u8> = crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_GEN_CALL_A>; -impl<'a, const O: u8> M_GEN_CALL_W<'a, O> { +pub type M_GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_GEN_CALL_A>; +impl<'a, REG, const O: u8> M_GEN_CALL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "GEN_CALL interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_GEN_CALL_A::ENABLED) } #[doc = "GEN_CALL interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_GEN_CALL_A::DISABLED) } } @@ -755,18 +759,18 @@ impl From for bool { impl M_RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> M_RESTART_DET_A { + pub const fn variant(&self) -> M_RESTART_DET_A { match self.bits { false => M_RESTART_DET_A::ENABLED, true => M_RESTART_DET_A::DISABLED, } } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "RESTART_DET interrupt is masked"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == M_RESTART_DET_A::ENABLED } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "RESTART_DET interrupt is unmasked"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == M_RESTART_DET_A::DISABLED @@ -775,17 +779,19 @@ impl M_RESTART_DET_R { #[doc = "Field `M_RESTART_DET` writer - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] -pub type M_RESTART_DET_W<'a, const O: u8> = - crate::BitWriter<'a, IC_INTR_MASK_SPEC, O, M_RESTART_DET_A>; -impl<'a, const O: u8> M_RESTART_DET_W<'a, O> { +pub type M_RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, M_RESTART_DET_A>; +impl<'a, REG, const O: u8> M_RESTART_DET_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "RESTART_DET interrupt is masked"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(M_RESTART_DET_A::ENABLED) } #[doc = "RESTART_DET interrupt is unmasked"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(M_RESTART_DET_A::DISABLED) } } @@ -888,7 +894,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_rx_under(&mut self) -> M_RX_UNDER_W<0> { + pub fn m_rx_under(&mut self) -> M_RX_UNDER_W { M_RX_UNDER_W::new(self) } #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. @@ -896,7 +902,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_rx_over(&mut self) -> M_RX_OVER_W<1> { + pub fn m_rx_over(&mut self) -> M_RX_OVER_W { M_RX_OVER_W::new(self) } #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. @@ -904,7 +910,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_rx_full(&mut self) -> M_RX_FULL_W<2> { + pub fn m_rx_full(&mut self) -> M_RX_FULL_W { M_RX_FULL_W::new(self) } #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. @@ -912,7 +918,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_tx_over(&mut self) -> M_TX_OVER_W<3> { + pub fn m_tx_over(&mut self) -> M_TX_OVER_W { M_TX_OVER_W::new(self) } #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. @@ -920,7 +926,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W<4> { + pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W { M_TX_EMPTY_W::new(self) } #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. @@ -928,7 +934,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_rd_req(&mut self) -> M_RD_REQ_W<5> { + pub fn m_rd_req(&mut self) -> M_RD_REQ_W { M_RD_REQ_W::new(self) } #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. @@ -936,7 +942,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W<6> { + pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W { M_TX_ABRT_W::new(self) } #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. @@ -944,7 +950,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_rx_done(&mut self) -> M_RX_DONE_W<7> { + pub fn m_rx_done(&mut self) -> M_RX_DONE_W { M_RX_DONE_W::new(self) } #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. @@ -952,7 +958,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn m_activity(&mut self) -> M_ACTIVITY_W<8> { + pub fn m_activity(&mut self) -> M_ACTIVITY_W { M_ACTIVITY_W::new(self) } #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. @@ -960,7 +966,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn m_stop_det(&mut self) -> M_STOP_DET_W<9> { + pub fn m_stop_det(&mut self) -> M_STOP_DET_W { M_STOP_DET_W::new(self) } #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. @@ -968,7 +974,7 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn m_start_det(&mut self) -> M_START_DET_W<10> { + pub fn m_start_det(&mut self) -> M_START_DET_W { M_START_DET_W::new(self) } #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. @@ -976,7 +982,7 @@ impl W { Reset value: 0x1"] #[inline(always)] #[must_use] - pub fn m_gen_call(&mut self) -> M_GEN_CALL_W<11> { + pub fn m_gen_call(&mut self) -> M_GEN_CALL_W { M_GEN_CALL_W::new(self) } #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. @@ -984,13 +990,17 @@ impl W { Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn m_restart_det(&mut self) -> M_RESTART_DET_W<12> { + pub fn m_restart_det(&mut self) -> M_RESTART_DET_W { M_RESTART_DET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -998,20 +1008,15 @@ impl W { These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_intr_mask](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_INTR_MASK_SPEC; impl crate::RegisterSpec for IC_INTR_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_intr_mask::R](R) reader structure"] -impl crate::Readable for IC_INTR_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_intr_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_intr_mask::R`](R) reader structure"] +impl crate::Readable for IC_INTR_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"] impl crate::Writable for IC_INTR_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs index 93e514123..716483a80 100644 --- a/src/i2c0/ic_intr_stat.rs +++ b/src/i2c0/ic_intr_stat.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_INTR_STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] @@ -38,18 +25,18 @@ impl From for bool { impl R_RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RX_UNDER_A { + pub const fn variant(&self) -> R_RX_UNDER_A { match self.bits { false => R_RX_UNDER_A::INACTIVE, true => R_RX_UNDER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RX_UNDER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RX_UNDER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RX_UNDER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RX_UNDER_A::ACTIVE @@ -80,18 +67,18 @@ impl From for bool { impl R_RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RX_OVER_A { + pub const fn variant(&self) -> R_RX_OVER_A { match self.bits { false => R_RX_OVER_A::INACTIVE, true => R_RX_OVER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_RX_OVER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RX_OVER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_RX_OVER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RX_OVER_A::ACTIVE @@ -122,18 +109,18 @@ impl From for bool { impl R_RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RX_FULL_A { + pub const fn variant(&self) -> R_RX_FULL_A { match self.bits { false => R_RX_FULL_A::INACTIVE, true => R_RX_FULL_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_RX_FULL interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RX_FULL_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_RX_FULL interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RX_FULL_A::ACTIVE @@ -164,18 +151,18 @@ impl From for bool { impl R_TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_TX_OVER_A { + pub const fn variant(&self) -> R_TX_OVER_A { match self.bits { false => R_TX_OVER_A::INACTIVE, true => R_TX_OVER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_TX_OVER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_TX_OVER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_TX_OVER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_TX_OVER_A::ACTIVE @@ -206,18 +193,18 @@ impl From for bool { impl R_TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_TX_EMPTY_A { + pub const fn variant(&self) -> R_TX_EMPTY_A { match self.bits { false => R_TX_EMPTY_A::INACTIVE, true => R_TX_EMPTY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_TX_EMPTY interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_TX_EMPTY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_TX_EMPTY interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_TX_EMPTY_A::ACTIVE @@ -248,18 +235,18 @@ impl From for bool { impl R_RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RD_REQ_A { + pub const fn variant(&self) -> R_RD_REQ_A { match self.bits { false => R_RD_REQ_A::INACTIVE, true => R_RD_REQ_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_RD_REQ interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RD_REQ_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_RD_REQ interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RD_REQ_A::ACTIVE @@ -290,18 +277,18 @@ impl From for bool { impl R_TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_TX_ABRT_A { + pub const fn variant(&self) -> R_TX_ABRT_A { match self.bits { false => R_TX_ABRT_A::INACTIVE, true => R_TX_ABRT_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_TX_ABRT interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_TX_ABRT_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_TX_ABRT interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_TX_ABRT_A::ACTIVE @@ -332,18 +319,18 @@ impl From for bool { impl R_RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RX_DONE_A { + pub const fn variant(&self) -> R_RX_DONE_A { match self.bits { false => R_RX_DONE_A::INACTIVE, true => R_RX_DONE_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_RX_DONE interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RX_DONE_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_RX_DONE interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RX_DONE_A::ACTIVE @@ -374,18 +361,18 @@ impl From for bool { impl R_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_ACTIVITY_A { + pub const fn variant(&self) -> R_ACTIVITY_A { match self.bits { false => R_ACTIVITY_A::INACTIVE, true => R_ACTIVITY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_ACTIVITY interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_ACTIVITY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_ACTIVITY interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_ACTIVITY_A::ACTIVE @@ -416,18 +403,18 @@ impl From for bool { impl R_STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_STOP_DET_A { + pub const fn variant(&self) -> R_STOP_DET_A { match self.bits { false => R_STOP_DET_A::INACTIVE, true => R_STOP_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_STOP_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_STOP_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_STOP_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_STOP_DET_A::ACTIVE @@ -458,18 +445,18 @@ impl From for bool { impl R_START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_START_DET_A { + pub const fn variant(&self) -> R_START_DET_A { match self.bits { false => R_START_DET_A::INACTIVE, true => R_START_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_START_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_START_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_START_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_START_DET_A::ACTIVE @@ -500,18 +487,18 @@ impl From for bool { impl R_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_GEN_CALL_A { + pub const fn variant(&self) -> R_GEN_CALL_A { match self.bits { false => R_GEN_CALL_A::INACTIVE, true => R_GEN_CALL_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_GEN_CALL interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_GEN_CALL_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_GEN_CALL interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_GEN_CALL_A::ACTIVE @@ -542,18 +529,18 @@ impl From for bool { impl R_RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> R_RESTART_DET_A { + pub const fn variant(&self) -> R_RESTART_DET_A { match self.bits { false => R_RESTART_DET_A::INACTIVE, true => R_RESTART_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "R_RESTART_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == R_RESTART_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "R_RESTART_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == R_RESTART_DET_A::ACTIVE @@ -656,17 +643,13 @@ impl R { Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_intr_stat](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_INTR_STAT_SPEC; impl crate::RegisterSpec for IC_INTR_STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_intr_stat::R](R) reader structure"] -impl crate::Readable for IC_INTR_STAT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_intr_stat::R`](R) reader structure"] +impl crate::Readable for IC_INTR_STAT_SPEC {} #[doc = "`reset()` method sets IC_INTR_STAT to value 0"] impl crate::Resettable for IC_INTR_STAT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs index 22f9041de..b350cba83 100644 --- a/src/i2c0/ic_raw_intr_stat.rs +++ b/src/i2c0/ic_raw_intr_stat.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_RAW_INTR_STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] @@ -38,18 +25,18 @@ impl From for bool { impl RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RX_UNDER_A { + pub const fn variant(&self) -> RX_UNDER_A { match self.bits { false => RX_UNDER_A::INACTIVE, true => RX_UNDER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RX_UNDER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RX_UNDER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RX_UNDER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RX_UNDER_A::ACTIVE @@ -84,18 +71,18 @@ impl From for bool { impl RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RX_OVER_A { + pub const fn variant(&self) -> RX_OVER_A { match self.bits { false => RX_OVER_A::INACTIVE, true => RX_OVER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RX_OVER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RX_OVER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RX_OVER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RX_OVER_A::ACTIVE @@ -126,18 +113,18 @@ impl From for bool { impl RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RX_FULL_A { + pub const fn variant(&self) -> RX_FULL_A { match self.bits { false => RX_FULL_A::INACTIVE, true => RX_FULL_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RX_FULL interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RX_FULL_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RX_FULL interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RX_FULL_A::ACTIVE @@ -168,18 +155,18 @@ impl From for bool { impl TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TX_OVER_A { + pub const fn variant(&self) -> TX_OVER_A { match self.bits { false => TX_OVER_A::INACTIVE, true => TX_OVER_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "TX_OVER interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == TX_OVER_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "TX_OVER interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == TX_OVER_A::ACTIVE @@ -212,18 +199,18 @@ impl From for bool { impl TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TX_EMPTY_A { + pub const fn variant(&self) -> TX_EMPTY_A { match self.bits { false => TX_EMPTY_A::INACTIVE, true => TX_EMPTY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "TX_EMPTY interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == TX_EMPTY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "TX_EMPTY interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == TX_EMPTY_A::ACTIVE @@ -254,18 +241,18 @@ impl From for bool { impl RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RD_REQ_A { + pub const fn variant(&self) -> RD_REQ_A { match self.bits { false => RD_REQ_A::INACTIVE, true => RD_REQ_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RD_REQ interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RD_REQ_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RD_REQ interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RD_REQ_A::ACTIVE @@ -300,18 +287,18 @@ impl From for bool { impl TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TX_ABRT_A { + pub const fn variant(&self) -> TX_ABRT_A { match self.bits { false => TX_ABRT_A::INACTIVE, true => TX_ABRT_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "TX_ABRT interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == TX_ABRT_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "TX_ABRT interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == TX_ABRT_A::ACTIVE @@ -342,18 +329,18 @@ impl From for bool { impl RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RX_DONE_A { + pub const fn variant(&self) -> RX_DONE_A { match self.bits { false => RX_DONE_A::INACTIVE, true => RX_DONE_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RX_DONE interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RX_DONE_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RX_DONE interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RX_DONE_A::ACTIVE @@ -384,18 +371,18 @@ impl From for bool { impl ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ACTIVITY_A { + pub const fn variant(&self) -> ACTIVITY_A { match self.bits { false => ACTIVITY_A::INACTIVE, true => ACTIVITY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RAW_INTR_ACTIVITY interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == ACTIVITY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RAW_INTR_ACTIVITY interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == ACTIVITY_A::ACTIVE @@ -426,18 +413,18 @@ impl From for bool { impl STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> STOP_DET_A { + pub const fn variant(&self) -> STOP_DET_A { match self.bits { false => STOP_DET_A::INACTIVE, true => STOP_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "STOP_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == STOP_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "STOP_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == STOP_DET_A::ACTIVE @@ -468,18 +455,18 @@ impl From for bool { impl START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> START_DET_A { + pub const fn variant(&self) -> START_DET_A { match self.bits { false => START_DET_A::INACTIVE, true => START_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "START_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == START_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "START_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == START_DET_A::ACTIVE @@ -510,18 +497,18 @@ impl From for bool { impl GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GEN_CALL_A { + pub const fn variant(&self) -> GEN_CALL_A { match self.bits { false => GEN_CALL_A::INACTIVE, true => GEN_CALL_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "GEN_CALL interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == GEN_CALL_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "GEN_CALL interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == GEN_CALL_A::ACTIVE @@ -556,18 +543,18 @@ impl From for bool { impl RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RESTART_DET_A { + pub const fn variant(&self) -> RESTART_DET_A { match self.bits { false => RESTART_DET_A::INACTIVE, true => RESTART_DET_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "RESTART_DET interrupt is inactive"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == RESTART_DET_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "RESTART_DET interrupt is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == RESTART_DET_A::ACTIVE @@ -677,17 +664,13 @@ is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks l Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_raw_intr_stat](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_RAW_INTR_STAT_SPEC; impl crate::RegisterSpec for IC_RAW_INTR_STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_raw_intr_stat::R](R) reader structure"] -impl crate::Readable for IC_RAW_INTR_STAT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"] +impl crate::Readable for IC_RAW_INTR_STAT_SPEC {} #[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"] impl crate::Resettable for IC_RAW_INTR_STAT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs index 64fb8c279..bfb68caf0 100644 --- a/src/i2c0/ic_rx_tl.rs +++ b/src/i2c0/ic_rx_tl.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_RX_TL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_RX_TL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RX_TL` reader - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] @@ -41,7 +9,7 @@ pub type RX_TL_R = crate::FieldReader; #[doc = "Field `RX_TL` writer - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] -pub type RX_TL_W<'a, const O: u8> = crate::FieldWriter<'a, IC_RX_TL_SPEC, 8, O>; +pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Receive FIFO Threshold Level. @@ -57,32 +25,31 @@ impl W { Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W<0> { + pub fn rx_tl(&mut self) -> RX_TL_W { RX_TL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "I2C Receive FIFO Threshold Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_rx_tl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rx_tl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_RX_TL_SPEC; impl crate::RegisterSpec for IC_RX_TL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_rx_tl::R](R) reader structure"] -impl crate::Readable for IC_RX_TL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_rx_tl::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_rx_tl::R`](R) reader structure"] +impl crate::Readable for IC_RX_TL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_rx_tl::W`](W) writer structure"] impl crate::Writable for IC_RX_TL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_rxflr.rs b/src/i2c0/ic_rxflr.rs index 47a21056d..0e4f2b493 100644 --- a/src/i2c0/ic_rxflr.rs +++ b/src/i2c0/ic_rxflr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_RXFLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXFLR` reader - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_rxflr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_RXFLR_SPEC; impl crate::RegisterSpec for IC_RXFLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_rxflr::R](R) reader structure"] -impl crate::Readable for IC_RXFLR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_rxflr::R`](R) reader structure"] +impl crate::Readable for IC_RXFLR_SPEC {} #[doc = "`reset()` method sets IC_RXFLR to value 0"] impl crate::Resettable for IC_RXFLR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs index ae6510aec..e2a82fd8e 100644 --- a/src/i2c0/ic_sar.rs +++ b/src/i2c0/ic_sar.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_SAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_SAR` reader - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] is used. @@ -49,7 +17,7 @@ is used. register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] -pub type IC_SAR_W<'a, const O: u8> = crate::FieldWriter<'a, IC_SAR_SPEC, 10, O, u16>; +pub type IC_SAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; impl R { #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] is used. @@ -73,32 +41,31 @@ register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] #[inline(always)] #[must_use] - pub fn ic_sar(&mut self) -> IC_SAR_W<0> { + pub fn ic_sar(&mut self) -> IC_SAR_W { IC_SAR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "I2C Slave Address Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_sar](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SAR_SPEC; impl crate::RegisterSpec for IC_SAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_sar::R](R) reader structure"] -impl crate::Readable for IC_SAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_sar::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_sar::R`](R) reader structure"] +impl crate::Readable for IC_SAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sar::W`](W) writer structure"] impl crate::Writable for IC_SAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs index cb4c3aee9..7f3161708 100644 --- a/src/i2c0/ic_sda_hold.rs +++ b/src/i2c0/ic_sda_hold.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_SDA_HOLD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SDA_HOLD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_SDA_TX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] @@ -41,7 +9,7 @@ pub type IC_SDA_TX_HOLD_R = crate::FieldReader; #[doc = "Field `IC_SDA_TX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] -pub type IC_SDA_TX_HOLD_W<'a, const O: u8> = crate::FieldWriter<'a, IC_SDA_HOLD_SPEC, 16, O, u16>; +pub type IC_SDA_TX_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `IC_SDA_RX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] @@ -49,7 +17,7 @@ pub type IC_SDA_RX_HOLD_R = crate::FieldReader; #[doc = "Field `IC_SDA_RX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] -pub type IC_SDA_RX_HOLD_W<'a, const O: u8> = crate::FieldWriter<'a, IC_SDA_HOLD_SPEC, 8, O>; +pub type IC_SDA_RX_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. @@ -72,7 +40,7 @@ impl W { Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] #[inline(always)] #[must_use] - pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W<0> { + pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W { IC_SDA_TX_HOLD_W::new(self) } #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. @@ -80,13 +48,17 @@ impl W { Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] #[inline(always)] #[must_use] - pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W<16> { + pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W { IC_SDA_RX_HOLD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -104,20 +76,15 @@ of this register are used to extend the SDA transition (if any) whenever SCL is The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_sda_hold](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SDA_HOLD_SPEC; impl crate::RegisterSpec for IC_SDA_HOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_sda_hold::R](R) reader structure"] -impl crate::Readable for IC_SDA_HOLD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_sda_hold::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_sda_hold::R`](R) reader structure"] +impl crate::Readable for IC_SDA_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sda_hold::W`](W) writer structure"] impl crate::Writable for IC_SDA_HOLD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs index 24b5d503e..ce2e42232 100644 --- a/src/i2c0/ic_sda_setup.rs +++ b/src/i2c0/ic_sda_setup.rs @@ -1,43 +1,11 @@ #[doc = "Register `IC_SDA_SETUP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SDA_SETUP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDA_SETUP` reader - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] pub type SDA_SETUP_R = crate::FieldReader; #[doc = "Field `SDA_SETUP` writer - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] -pub type SDA_SETUP_W<'a, const O: u8> = crate::FieldWriter<'a, IC_SDA_SETUP_SPEC, 8, O>; +pub type SDA_SETUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] #[inline(always)] @@ -49,13 +17,17 @@ impl W { #[doc = "Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] #[inline(always)] #[must_use] - pub fn sda_setup(&mut self) -> SDA_SETUP_W<0> { + pub fn sda_setup(&mut self) -> SDA_SETUP_W { SDA_SETUP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -68,20 +40,15 @@ impl W { Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_sda_setup](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SDA_SETUP_SPEC; impl crate::RegisterSpec for IC_SDA_SETUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_sda_setup::R](R) reader structure"] -impl crate::Readable for IC_SDA_SETUP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_sda_setup::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_sda_setup::R`](R) reader structure"] +impl crate::Readable for IC_SDA_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sda_setup::W`](W) writer structure"] impl crate::Writable for IC_SDA_SETUP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs index 59cba30fb..c1e5bf09e 100644 --- a/src/i2c0/ic_slv_data_nack_only.rs +++ b/src/i2c0/ic_slv_data_nack_only.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_SLV_DATA_NACK_ONLY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] @@ -59,18 +27,18 @@ impl From for bool { impl NACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> NACK_A { + pub const fn variant(&self) -> NACK_A { match self.bits { false => NACK_A::DISABLED, true => NACK_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Slave receiver generates NACK normally"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == NACK_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Slave receiver generates NACK upon data reception only"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == NACK_A::ENABLED @@ -79,16 +47,19 @@ impl NACK_R { #[doc = "Field `NACK` writer - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] -pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, IC_SLV_DATA_NACK_ONLY_SPEC, O, NACK_A>; -impl<'a, const O: u8> NACK_W<'a, O> { +pub type NACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NACK_A>; +impl<'a, REG, const O: u8> NACK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Slave receiver generates NACK normally"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(NACK_A::DISABLED) } #[doc = "Slave receiver generates NACK upon data reception only"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(NACK_A::ENABLED) } } @@ -107,13 +78,17 @@ impl W { When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn nack(&mut self) -> NACK_W<0> { + pub fn nack(&mut self) -> NACK_W { NACK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -126,20 +101,15 @@ impl W { = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_slv_data_nack_only](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SLV_DATA_NACK_ONLY_SPEC; impl crate::RegisterSpec for IC_SLV_DATA_NACK_ONLY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_slv_data_nack_only::R](R) reader structure"] -impl crate::Readable for IC_SLV_DATA_NACK_ONLY_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_slv_data_nack_only::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_slv_data_nack_only::R`](R) reader structure"] +impl crate::Readable for IC_SLV_DATA_NACK_ONLY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_slv_data_nack_only::W`](W) writer structure"] impl crate::Writable for IC_SLV_DATA_NACK_ONLY_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs index d8762e1d7..f36e7c241 100644 --- a/src/i2c0/ic_ss_scl_hcnt.rs +++ b/src/i2c0/ic_ss_scl_hcnt.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_SS_SCL_HCNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SS_SCL_HCNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_SS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] @@ -51,8 +19,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] -pub type IC_SS_SCL_HCNT_W<'a, const O: u8> = - crate::FieldWriter<'a, IC_SS_SCL_HCNT_SPEC, 16, O, u16>; +pub type IC_SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. @@ -78,32 +45,31 @@ register being set to 0. Writes at other times have no effect. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] #[inline(always)] #[must_use] - pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W<0> { + pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W { IC_SS_SCL_HCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Standard Speed I2C Clock SCL High Count Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_ss_scl_hcnt](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SS_SCL_HCNT_SPEC; impl crate::RegisterSpec for IC_SS_SCL_HCNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_ss_scl_hcnt::R](R) reader structure"] -impl crate::Readable for IC_SS_SCL_HCNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_ss_scl_hcnt::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_ss_scl_hcnt::R`](R) reader structure"] +impl crate::Readable for IC_SS_SCL_HCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"] impl crate::Writable for IC_SS_SCL_HCNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs index 4ff49cfb9..74d255f4e 100644 --- a/src/i2c0/ic_ss_scl_lcnt.rs +++ b/src/i2c0/ic_ss_scl_lcnt.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_SS_SCL_LCNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_SS_SCL_LCNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_SS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] @@ -47,8 +15,7 @@ pub type IC_SS_SCL_LCNT_R = crate::FieldReader; register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] -pub type IC_SS_SCL_LCNT_W<'a, const O: u8> = - crate::FieldWriter<'a, IC_SS_SCL_LCNT_SPEC, 16, O, u16>; +pub type IC_SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' @@ -70,32 +37,31 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] #[inline(always)] #[must_use] - pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W<0> { + pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W { IC_SS_SCL_LCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Standard Speed I2C Clock SCL Low Count Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_ss_scl_lcnt](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SS_SCL_LCNT_SPEC; impl crate::RegisterSpec for IC_SS_SCL_LCNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_ss_scl_lcnt::R](R) reader structure"] -impl crate::Readable for IC_SS_SCL_LCNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_ss_scl_lcnt::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_ss_scl_lcnt::R`](R) reader structure"] +impl crate::Readable for IC_SS_SCL_LCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"] impl crate::Writable for IC_SS_SCL_LCNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs index d89dc8859..9d4df918c 100644 --- a/src/i2c0/ic_status.rs +++ b/src/i2c0/ic_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ACTIVITY` reader - I2C Activity Status. Reset value: 0x0"] pub type ACTIVITY_R = crate::BitReader; #[doc = "I2C Activity Status. Reset value: 0x0 @@ -34,18 +21,18 @@ impl From for bool { impl ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ACTIVITY_A { + pub const fn variant(&self) -> ACTIVITY_A { match self.bits { false => ACTIVITY_A::INACTIVE, true => ACTIVITY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "I2C is idle"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == ACTIVITY_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "I2C is active"] #[inline(always)] pub fn is_active(&self) -> bool { *self == ACTIVITY_A::ACTIVE @@ -72,18 +59,18 @@ impl From for bool { impl TFNF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TFNF_A { + pub const fn variant(&self) -> TFNF_A { match self.bits { false => TFNF_A::FULL, true => TFNF_A::NOT_FULL, } } - #[doc = "Checks if the value of the field is `FULL`"] + #[doc = "Tx FIFO is full"] #[inline(always)] pub fn is_full(&self) -> bool { *self == TFNF_A::FULL } - #[doc = "Checks if the value of the field is `NOT_FULL`"] + #[doc = "Tx FIFO not full"] #[inline(always)] pub fn is_not_full(&self) -> bool { *self == TFNF_A::NOT_FULL @@ -110,18 +97,18 @@ impl From for bool { impl TFE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TFE_A { + pub const fn variant(&self) -> TFE_A { match self.bits { false => TFE_A::NON_EMPTY, true => TFE_A::EMPTY, } } - #[doc = "Checks if the value of the field is `NON_EMPTY`"] + #[doc = "Tx FIFO not empty"] #[inline(always)] pub fn is_non_empty(&self) -> bool { *self == TFE_A::NON_EMPTY } - #[doc = "Checks if the value of the field is `EMPTY`"] + #[doc = "Tx FIFO is empty"] #[inline(always)] pub fn is_empty(&self) -> bool { *self == TFE_A::EMPTY @@ -148,18 +135,18 @@ impl From for bool { impl RFNE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RFNE_A { + pub const fn variant(&self) -> RFNE_A { match self.bits { false => RFNE_A::EMPTY, true => RFNE_A::NOT_EMPTY, } } - #[doc = "Checks if the value of the field is `EMPTY`"] + #[doc = "Rx FIFO is empty"] #[inline(always)] pub fn is_empty(&self) -> bool { *self == RFNE_A::EMPTY } - #[doc = "Checks if the value of the field is `NOT_EMPTY`"] + #[doc = "Rx FIFO not empty"] #[inline(always)] pub fn is_not_empty(&self) -> bool { *self == RFNE_A::NOT_EMPTY @@ -186,18 +173,18 @@ impl From for bool { impl RFF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RFF_A { + pub const fn variant(&self) -> RFF_A { match self.bits { false => RFF_A::NOT_FULL, true => RFF_A::FULL, } } - #[doc = "Checks if the value of the field is `NOT_FULL`"] + #[doc = "Rx FIFO not full"] #[inline(always)] pub fn is_not_full(&self) -> bool { *self == RFF_A::NOT_FULL } - #[doc = "Checks if the value of the field is `FULL`"] + #[doc = "Rx FIFO is full"] #[inline(always)] pub fn is_full(&self) -> bool { *self == RFF_A::FULL @@ -228,18 +215,18 @@ impl From for bool { impl MST_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MST_ACTIVITY_A { + pub const fn variant(&self) -> MST_ACTIVITY_A { match self.bits { false => MST_ACTIVITY_A::IDLE, true => MST_ACTIVITY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `IDLE`"] + #[doc = "Master is idle"] #[inline(always)] pub fn is_idle(&self) -> bool { *self == MST_ACTIVITY_A::IDLE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Master not idle"] #[inline(always)] pub fn is_active(&self) -> bool { *self == MST_ACTIVITY_A::ACTIVE @@ -266,18 +253,18 @@ impl From for bool { impl SLV_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SLV_ACTIVITY_A { + pub const fn variant(&self) -> SLV_ACTIVITY_A { match self.bits { false => SLV_ACTIVITY_A::IDLE, true => SLV_ACTIVITY_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `IDLE`"] + #[doc = "Slave is idle"] #[inline(always)] pub fn is_idle(&self) -> bool { *self == SLV_ACTIVITY_A::IDLE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Slave not idle"] #[inline(always)] pub fn is_active(&self) -> bool { *self == SLV_ACTIVITY_A::ACTIVE @@ -328,17 +315,13 @@ impl R { When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_STATUS_SPEC; impl crate::RegisterSpec for IC_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_status::R](R) reader structure"] -impl crate::Readable for IC_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_status::R`](R) reader structure"] +impl crate::Readable for IC_STATUS_SPEC {} #[doc = "`reset()` method sets IC_STATUS to value 0x06"] impl crate::Resettable for IC_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0x06; diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs index a468c32c3..0afe3e055 100644 --- a/src/i2c0/ic_tar.rs +++ b/src/i2c0/ic_tar.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_TAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_TAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IC_TAR` reader - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] @@ -41,7 +9,7 @@ pub type IC_TAR_R = crate::FieldReader; #[doc = "Field `IC_TAR` writer - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] -pub type IC_TAR_W<'a, const O: u8> = crate::FieldWriter<'a, IC_TAR_SPEC, 10, O, u16>; +pub type IC_TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] pub type GC_OR_START_R = crate::BitReader; #[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 @@ -63,34 +31,37 @@ impl From for bool { impl GC_OR_START_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GC_OR_START_A { + pub const fn variant(&self) -> GC_OR_START_A { match self.bits { false => GC_OR_START_A::GENERAL_CALL, true => GC_OR_START_A::START_BYTE, } } - #[doc = "Checks if the value of the field is `GENERAL_CALL`"] + #[doc = "GENERAL_CALL byte transmission"] #[inline(always)] pub fn is_general_call(&self) -> bool { *self == GC_OR_START_A::GENERAL_CALL } - #[doc = "Checks if the value of the field is `START_BYTE`"] + #[doc = "START byte transmission"] #[inline(always)] pub fn is_start_byte(&self) -> bool { *self == GC_OR_START_A::START_BYTE } } #[doc = "Field `GC_OR_START` writer - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] -pub type GC_OR_START_W<'a, const O: u8> = crate::BitWriter<'a, IC_TAR_SPEC, O, GC_OR_START_A>; -impl<'a, const O: u8> GC_OR_START_W<'a, O> { +pub type GC_OR_START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, GC_OR_START_A>; +impl<'a, REG, const O: u8> GC_OR_START_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "GENERAL_CALL byte transmission"] #[inline(always)] - pub fn general_call(self) -> &'a mut W { + pub fn general_call(self) -> &'a mut crate::W { self.variant(GC_OR_START_A::GENERAL_CALL) } #[doc = "START byte transmission"] #[inline(always)] - pub fn start_byte(self) -> &'a mut W { + pub fn start_byte(self) -> &'a mut crate::W { self.variant(GC_OR_START_A::START_BYTE) } } @@ -115,34 +86,37 @@ impl From for bool { impl SPECIAL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SPECIAL_A { + pub const fn variant(&self) -> SPECIAL_A { match self.bits { false => SPECIAL_A::DISABLED, true => SPECIAL_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == SPECIAL_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == SPECIAL_A::ENABLED } } #[doc = "Field `SPECIAL` writer - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] -pub type SPECIAL_W<'a, const O: u8> = crate::BitWriter<'a, IC_TAR_SPEC, O, SPECIAL_A>; -impl<'a, const O: u8> SPECIAL_W<'a, O> { +pub type SPECIAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SPECIAL_A>; +impl<'a, REG, const O: u8> SPECIAL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(SPECIAL_A::DISABLED) } #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(SPECIAL_A::ENABLED) } } @@ -171,25 +145,29 @@ impl W { If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] #[inline(always)] #[must_use] - pub fn ic_tar(&mut self) -> IC_TAR_W<0> { + pub fn ic_tar(&mut self) -> IC_TAR_W { IC_TAR_W::new(self) } #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn gc_or_start(&mut self) -> GC_OR_START_W<10> { + pub fn gc_or_start(&mut self) -> GC_OR_START_W { GC_OR_START_W::new(self) } #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] #[inline(always)] #[must_use] - pub fn special(&mut self) -> SPECIAL_W<11> { + pub fn special(&mut self) -> SPECIAL_W { SPECIAL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -200,20 +178,15 @@ is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_tar](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TAR_SPEC; impl crate::RegisterSpec for IC_TAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_tar::R](R) reader structure"] -impl crate::Readable for IC_TAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_tar::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_tar::R`](R) reader structure"] +impl crate::Readable for IC_TAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"] impl crate::Writable for IC_TAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs index 699b3effd..43f1ca617 100644 --- a/src/i2c0/ic_tx_abrt_source.rs +++ b/src/i2c0/ic_tx_abrt_source.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_TX_ABRT_SOURCE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 @@ -42,18 +29,18 @@ impl From for bool { impl ABRT_7B_ADDR_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_7B_ADDR_NOACK_A { + pub const fn variant(&self) -> ABRT_7B_ADDR_NOACK_A { match self.bits { false => ABRT_7B_ADDR_NOACK_A::INACTIVE, true => ABRT_7B_ADDR_NOACK_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "This abort is not generated"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == ABRT_7B_ADDR_NOACK_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "This abort is generated because of NOACK for 7-bit address"] #[inline(always)] pub fn is_active(&self) -> bool { *self == ABRT_7B_ADDR_NOACK_A::ACTIVE @@ -88,18 +75,18 @@ impl From for bool { impl ABRT_10ADDR1_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_10ADDR1_NOACK_A { + pub const fn variant(&self) -> ABRT_10ADDR1_NOACK_A { match self.bits { false => ABRT_10ADDR1_NOACK_A::INACTIVE, true => ABRT_10ADDR1_NOACK_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "This abort is not generated"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == ABRT_10ADDR1_NOACK_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Byte 1 of 10Bit Address not ACKed by any slave"] #[inline(always)] pub fn is_active(&self) -> bool { *self == ABRT_10ADDR1_NOACK_A::ACTIVE @@ -134,18 +121,18 @@ impl From for bool { impl ABRT_10ADDR2_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_10ADDR2_NOACK_A { + pub const fn variant(&self) -> ABRT_10ADDR2_NOACK_A { match self.bits { false => ABRT_10ADDR2_NOACK_A::INACTIVE, true => ABRT_10ADDR2_NOACK_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "This abort is not generated"] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == ABRT_10ADDR2_NOACK_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "Byte 2 of 10Bit Address not ACKed by any slave"] #[inline(always)] pub fn is_active(&self) -> bool { *self == ABRT_10ADDR2_NOACK_A::ACTIVE @@ -180,18 +167,18 @@ impl From for bool { impl ABRT_TXDATA_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_TXDATA_NOACK_A { + pub const fn variant(&self) -> ABRT_TXDATA_NOACK_A { match self.bits { false => ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_VOID, true => ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_TXDATA_NOACK_VOID`"] + #[doc = "Transmitted data non-ACKed by addressed slave-scenario not present"] #[inline(always)] pub fn is_abrt_txdata_noack_void(&self) -> bool { *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_VOID } - #[doc = "Checks if the value of the field is `ABRT_TXDATA_NOACK_GENERATED`"] + #[doc = "Transmitted data not ACKed by addressed slave"] #[inline(always)] pub fn is_abrt_txdata_noack_generated(&self) -> bool { *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED @@ -226,18 +213,18 @@ impl From for bool { impl ABRT_GCALL_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_GCALL_NOACK_A { + pub const fn variant(&self) -> ABRT_GCALL_NOACK_A { match self.bits { false => ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_VOID, true => ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_GCALL_NOACK_VOID`"] + #[doc = "GCALL not ACKed by any slave-scenario not present"] #[inline(always)] pub fn is_abrt_gcall_noack_void(&self) -> bool { *self == ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_VOID } - #[doc = "Checks if the value of the field is `ABRT_GCALL_NOACK_GENERATED`"] + #[doc = "GCALL not ACKed by any slave"] #[inline(always)] pub fn is_abrt_gcall_noack_generated(&self) -> bool { *self == ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_GENERATED @@ -274,18 +261,18 @@ impl From for bool { impl ABRT_GCALL_READ_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_GCALL_READ_A { + pub const fn variant(&self) -> ABRT_GCALL_READ_A { match self.bits { false => ABRT_GCALL_READ_A::ABRT_GCALL_READ_VOID, true => ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_GCALL_READ_VOID`"] + #[doc = "GCALL is followed by read from bus-scenario not present"] #[inline(always)] pub fn is_abrt_gcall_read_void(&self) -> bool { *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_VOID } - #[doc = "Checks if the value of the field is `ABRT_GCALL_READ_GENERATED`"] + #[doc = "GCALL is followed by read from bus"] #[inline(always)] pub fn is_abrt_gcall_read_generated(&self) -> bool { *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED @@ -320,18 +307,18 @@ impl From for bool { impl ABRT_HS_ACKDET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_HS_ACKDET_A { + pub const fn variant(&self) -> ABRT_HS_ACKDET_A { match self.bits { false => ABRT_HS_ACKDET_A::ABRT_HS_ACK_VOID, true => ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_HS_ACK_VOID`"] + #[doc = "HS Master code ACKed in HS Mode- scenario not present"] #[inline(always)] pub fn is_abrt_hs_ack_void(&self) -> bool { *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_VOID } - #[doc = "Checks if the value of the field is `ABRT_HS_ACK_GENERATED`"] + #[doc = "HS Master code ACKed in HS Mode"] #[inline(always)] pub fn is_abrt_hs_ack_generated(&self) -> bool { *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED @@ -366,18 +353,18 @@ impl From for bool { impl ABRT_SBYTE_ACKDET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_SBYTE_ACKDET_A { + pub const fn variant(&self) -> ABRT_SBYTE_ACKDET_A { match self.bits { false => ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_VOID, true => ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_SBYTE_ACKDET_VOID`"] + #[doc = "ACK detected for START byte- scenario not present"] #[inline(always)] pub fn is_abrt_sbyte_ackdet_void(&self) -> bool { *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_VOID } - #[doc = "Checks if the value of the field is `ABRT_SBYTE_ACKDET_GENERATED`"] + #[doc = "ACK detected for START byte"] #[inline(always)] pub fn is_abrt_sbyte_ackdet_generated(&self) -> bool { *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED @@ -412,18 +399,18 @@ impl From for bool { impl ABRT_HS_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_HS_NORSTRT_A { + pub const fn variant(&self) -> ABRT_HS_NORSTRT_A { match self.bits { false => ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_VOID, true => ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_HS_NORSTRT_VOID`"] + #[doc = "User trying to switch Master to HS mode when RESTART disabled- scenario not present"] #[inline(always)] pub fn is_abrt_hs_norstrt_void(&self) -> bool { *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_VOID } - #[doc = "Checks if the value of the field is `ABRT_HS_NORSTRT_GENERATED`"] + #[doc = "User trying to switch Master to HS mode when RESTART disabled"] #[inline(always)] pub fn is_abrt_hs_norstrt_generated(&self) -> bool { *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED @@ -458,18 +445,18 @@ impl From for bool { impl ABRT_SBYTE_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_SBYTE_NORSTRT_A { + pub const fn variant(&self) -> ABRT_SBYTE_NORSTRT_A { match self.bits { false => ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_VOID, true => ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_SBYTE_NORSTRT_VOID`"] + #[doc = "User trying to send START byte when RESTART disabled- scenario not present"] #[inline(always)] pub fn is_abrt_sbyte_norstrt_void(&self) -> bool { *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_VOID } - #[doc = "Checks if the value of the field is `ABRT_SBYTE_NORSTRT_GENERATED`"] + #[doc = "User trying to send START byte when RESTART disabled"] #[inline(always)] pub fn is_abrt_sbyte_norstrt_generated(&self) -> bool { *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED @@ -504,18 +491,18 @@ impl From for bool { impl ABRT_10B_RD_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_10B_RD_NORSTRT_A { + pub const fn variant(&self) -> ABRT_10B_RD_NORSTRT_A { match self.bits { false => ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_VOID, true => ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_10B_RD_VOID`"] + #[doc = "Master not trying to read in 10Bit addressing mode when RESTART disabled"] #[inline(always)] pub fn is_abrt_10b_rd_void(&self) -> bool { *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_VOID } - #[doc = "Checks if the value of the field is `ABRT_10B_RD_GENERATED`"] + #[doc = "Master trying to read in 10Bit addressing mode when RESTART disabled"] #[inline(always)] pub fn is_abrt_10b_rd_generated(&self) -> bool { *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED @@ -550,18 +537,18 @@ impl From for bool { impl ABRT_MASTER_DIS_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_MASTER_DIS_A { + pub const fn variant(&self) -> ABRT_MASTER_DIS_A { match self.bits { false => ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_VOID, true => ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_MASTER_DIS_VOID`"] + #[doc = "User initiating master operation when MASTER disabled- scenario not present"] #[inline(always)] pub fn is_abrt_master_dis_void(&self) -> bool { *self == ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_VOID } - #[doc = "Checks if the value of the field is `ABRT_MASTER_DIS_GENERATED`"] + #[doc = "User initiating master operation when MASTER disabled"] #[inline(always)] pub fn is_abrt_master_dis_generated(&self) -> bool { *self == ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_GENERATED @@ -598,18 +585,18 @@ impl From for bool { impl ARB_LOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ARB_LOST_A { + pub const fn variant(&self) -> ARB_LOST_A { match self.bits { false => ARB_LOST_A::ABRT_LOST_VOID, true => ARB_LOST_A::ABRT_LOST_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_LOST_VOID`"] + #[doc = "Master or Slave-Transmitter lost arbitration- scenario not present"] #[inline(always)] pub fn is_abrt_lost_void(&self) -> bool { *self == ARB_LOST_A::ABRT_LOST_VOID } - #[doc = "Checks if the value of the field is `ABRT_LOST_GENERATED`"] + #[doc = "Master or Slave-Transmitter lost arbitration"] #[inline(always)] pub fn is_abrt_lost_generated(&self) -> bool { *self == ARB_LOST_A::ABRT_LOST_GENERATED @@ -644,18 +631,18 @@ impl From for bool { impl ABRT_SLVFLUSH_TXFIFO_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_SLVFLUSH_TXFIFO_A { + pub const fn variant(&self) -> ABRT_SLVFLUSH_TXFIFO_A { match self.bits { false => ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_VOID, true => ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_SLVFLUSH_TXFIFO_VOID`"] + #[doc = "Slave flushes existing data in TX-FIFO upon getting read command- scenario not present"] #[inline(always)] pub fn is_abrt_slvflush_txfifo_void(&self) -> bool { *self == ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_VOID } - #[doc = "Checks if the value of the field is `ABRT_SLVFLUSH_TXFIFO_GENERATED`"] + #[doc = "Slave flushes existing data in TX-FIFO upon getting read command"] #[inline(always)] pub fn is_abrt_slvflush_txfifo_generated(&self) -> bool { *self == ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_GENERATED @@ -692,18 +679,18 @@ impl From for bool { impl ABRT_SLV_ARBLOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_SLV_ARBLOST_A { + pub const fn variant(&self) -> ABRT_SLV_ARBLOST_A { match self.bits { false => ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_VOID, true => ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_SLV_ARBLOST_VOID`"] + #[doc = "Slave lost arbitration to remote master- scenario not present"] #[inline(always)] pub fn is_abrt_slv_arblost_void(&self) -> bool { *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_VOID } - #[doc = "Checks if the value of the field is `ABRT_SLV_ARBLOST_GENERATED`"] + #[doc = "Slave lost arbitration to remote master"] #[inline(always)] pub fn is_abrt_slv_arblost_generated(&self) -> bool { *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED @@ -738,18 +725,18 @@ impl From for bool { impl ABRT_SLVRD_INTX_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_SLVRD_INTX_A { + pub const fn variant(&self) -> ABRT_SLVRD_INTX_A { match self.bits { false => ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_VOID, true => ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_SLVRD_INTX_VOID`"] + #[doc = "Slave trying to transmit to remote master in read mode- scenario not present"] #[inline(always)] pub fn is_abrt_slvrd_intx_void(&self) -> bool { *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_VOID } - #[doc = "Checks if the value of the field is `ABRT_SLVRD_INTX_GENERATED`"] + #[doc = "Slave trying to transmit to remote master in read mode"] #[inline(always)] pub fn is_abrt_slvrd_intx_generated(&self) -> bool { *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED @@ -784,18 +771,18 @@ impl From for bool { impl ABRT_USER_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ABRT_USER_ABRT_A { + pub const fn variant(&self) -> ABRT_USER_ABRT_A { match self.bits { false => ABRT_USER_ABRT_A::ABRT_USER_ABRT_VOID, true => ABRT_USER_ABRT_A::ABRT_USER_ABRT_GENERATED, } } - #[doc = "Checks if the value of the field is `ABRT_USER_ABRT_VOID`"] + #[doc = "Transfer abort detected by master- scenario not present"] #[inline(always)] pub fn is_abrt_user_abrt_void(&self) -> bool { *self == ABRT_USER_ABRT_A::ABRT_USER_ABRT_VOID } - #[doc = "Checks if the value of the field is `ABRT_USER_ABRT_GENERATED`"] + #[doc = "Transfer abort detected by master"] #[inline(always)] pub fn is_abrt_user_abrt_generated(&self) -> bool { *self == ABRT_USER_ABRT_A::ABRT_USER_ABRT_GENERATED @@ -980,17 +967,13 @@ is set at the same time. Note: Even though the slave never 'owns' the bus, somet Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_tx_abrt_source](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TX_ABRT_SOURCE_SPEC; impl crate::RegisterSpec for IC_TX_ABRT_SOURCE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_tx_abrt_source::R](R) reader structure"] -impl crate::Readable for IC_TX_ABRT_SOURCE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_tx_abrt_source::R`](R) reader structure"] +impl crate::Readable for IC_TX_ABRT_SOURCE_SPEC {} #[doc = "`reset()` method sets IC_TX_ABRT_SOURCE to value 0"] impl crate::Resettable for IC_TX_ABRT_SOURCE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs index fe81f195c..3509fea06 100644 --- a/src/i2c0/ic_tx_tl.rs +++ b/src/i2c0/ic_tx_tl.rs @@ -1,39 +1,7 @@ #[doc = "Register `IC_TX_TL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IC_TX_TL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TX_TL` reader - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] @@ -41,7 +9,7 @@ pub type TX_TL_R = crate::FieldReader; #[doc = "Field `TX_TL` writer - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] -pub type TX_TL_W<'a, const O: u8> = crate::FieldWriter<'a, IC_TX_TL_SPEC, 8, O>; +pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. @@ -57,32 +25,31 @@ impl W { Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W<0> { + pub fn tx_tl(&mut self) -> TX_TL_W { TX_TL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "I2C Transmit FIFO Threshold Register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_tx_tl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_tl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TX_TL_SPEC; impl crate::RegisterSpec for IC_TX_TL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_tx_tl::R](R) reader structure"] -impl crate::Readable for IC_TX_TL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ic_tx_tl::W](W) writer structure"] +#[doc = "`read()` method returns [`ic_tx_tl::R`](R) reader structure"] +impl crate::Readable for IC_TX_TL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tx_tl::W`](W) writer structure"] impl crate::Writable for IC_TX_TL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/i2c0/ic_txflr.rs b/src/i2c0/ic_txflr.rs index b8cadd3b3..d22e69301 100644 --- a/src/i2c0/ic_txflr.rs +++ b/src/i2c0/ic_txflr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IC_TXFLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXFLR` reader - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] @@ -28,17 +15,13 @@ impl R { } #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ic_txflr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TXFLR_SPEC; impl crate::RegisterSpec for IC_TXFLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ic_txflr::R](R) reader structure"] -impl crate::Readable for IC_TXFLR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ic_txflr::R`](R) reader structure"] +impl crate::Readable for IC_TXFLR_SPEC {} #[doc = "`reset()` method sets IC_TXFLR to value 0"] impl crate::Resettable for IC_TXFLR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_bank0.rs b/src/io_bank0.rs index 162acb7d9..508608dce 100644 --- a/src/io_bank0.rs +++ b/src/io_bank0.rs @@ -29,43 +29,93 @@ pub use self::gpio::GPIO; #[doc = r"Cluster"] #[doc = "Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] pub mod gpio; -#[doc = "INTR (rw) register accessor: an alias for `Reg`"] +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "PROC0_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc%s + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_inte`] +module"] pub type PROC0_INTE = crate::Reg; #[doc = "Interrupt Enable for proc%s"] pub mod proc0_inte; -#[doc = "PROC0_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc%s + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_intf`] +module"] pub type PROC0_INTF = crate::Reg; #[doc = "Interrupt Force for proc%s"] pub mod proc0_intf; -#[doc = "PROC0_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking & forcing for proc%s + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_ints`] +module"] pub type PROC0_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for proc%s"] pub mod proc0_ints; -#[doc = "PROC1_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_inte`] +module"] pub type PROC1_INTE = crate::Reg; #[doc = "Interrupt Enable for proc1"] pub mod proc1_inte; -#[doc = "PROC1_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_intf`] +module"] pub type PROC1_INTF = crate::Reg; #[doc = "Interrupt Force for proc1"] pub mod proc1_intf; -#[doc = "PROC1_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_ints`] +module"] pub type PROC1_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for proc1"] pub mod proc1_ints; -#[doc = "DORMANT_WAKE_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_inte`] +module"] pub type DORMANT_WAKE_INTE = crate::Reg; #[doc = "Interrupt Enable for dormant_wake"] pub mod dormant_wake_inte; -#[doc = "DORMANT_WAKE_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_intf`] +module"] pub type DORMANT_WAKE_INTF = crate::Reg; #[doc = "Interrupt Force for dormant_wake"] pub mod dormant_wake_intf; -#[doc = "DORMANT_WAKE_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_ints`] +module"] pub type DORMANT_WAKE_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for dormant_wake"] pub mod dormant_wake_ints; diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/io_bank0/dormant_wake_inte.rs index bd4c5c612..dc88b5d4b 100644 --- a/src/io_bank0/dormant_wake_inte.rs +++ b/src/io_bank0/dormant_wake_inte.rs @@ -1,167 +1,135 @@ #[doc = "Register `DORMANT_WAKE_INTE%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT_WAKE_INTE%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for dormant_wake -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTE_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_inte::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant_wake_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant_wake_inte::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/io_bank0/dormant_wake_intf.rs index 2108d9da7..1974b4837 100644 --- a/src/io_bank0/dormant_wake_intf.rs +++ b/src/io_bank0/dormant_wake_intf.rs @@ -1,167 +1,135 @@ #[doc = "Register `DORMANT_WAKE_INTF%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT_WAKE_INTF%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for dormant_wake -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTF_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_intf::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant_wake_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant_wake_intf::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/io_bank0/dormant_wake_ints.rs index aa066662b..011b8297e 100644 --- a/src/io_bank0/dormant_wake_ints.rs +++ b/src/io_bank0/dormant_wake_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `DORMANT_WAKE_INTS%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -241,17 +228,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for dormant_wake -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTS_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_ints::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} #[doc = "`reset()` method sets DORMANT_WAKE_INTS%s to value 0"] impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_bank0/gpio.rs b/src/io_bank0/gpio.rs index cbbbe7784..ecba35a98 100644 --- a/src/io_bank0/gpio.rs +++ b/src/io_bank0/gpio.rs @@ -6,11 +6,21 @@ pub struct GPIO { #[doc = "0x04 - GPIO control including function select and overrides."] pub gpio_ctrl: GPIO_CTRL, } -#[doc = "GPIO_STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "GPIO_STATUS (r) register accessor: GPIO status + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_status`] +module"] pub type GPIO_STATUS = crate::Reg; #[doc = "GPIO status"] pub mod gpio_status; -#[doc = "GPIO_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_CTRL (rw) register accessor: GPIO control including function select and overrides. + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_ctrl`] +module"] pub type GPIO_CTRL = crate::Reg; #[doc = "GPIO control including function select and overrides."] pub mod gpio_ctrl; diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs index 1e75f1c26..e586ad4b1 100644 --- a/src/io_bank0/gpio/gpio_ctrl.rs +++ b/src/io_bank0/gpio/gpio_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] pub type FUNCSEL_R = crate::FieldReader; #[doc = "0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. @@ -77,7 +45,7 @@ impl crate::FieldSpec for FUNCSEL_A { impl FUNCSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(FUNCSEL_A::JTAG), 1 => Some(FUNCSEL_A::SPI), @@ -93,118 +61,122 @@ impl FUNCSEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `JTAG`"] + #[doc = "Connect to JTAG peripheral"] #[inline(always)] pub fn is_jtag(&self) -> bool { *self == FUNCSEL_A::JTAG } - #[doc = "Checks if the value of the field is `SPI`"] + #[doc = "Connect to matching SPI peripheral"] #[inline(always)] pub fn is_spi(&self) -> bool { *self == FUNCSEL_A::SPI } - #[doc = "Checks if the value of the field is `UART`"] + #[doc = "Connect to matching UART peripheral"] #[inline(always)] pub fn is_uart(&self) -> bool { *self == FUNCSEL_A::UART } - #[doc = "Checks if the value of the field is `I2C`"] + #[doc = "Connect to matching I2C peripheral"] #[inline(always)] pub fn is_i2c(&self) -> bool { *self == FUNCSEL_A::I2C } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "Connect to matching PWM peripheral"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == FUNCSEL_A::PWM } - #[doc = "Checks if the value of the field is `SIO`"] + #[doc = "Use as a GPIO pin (connect to SIO peripheral)"] #[inline(always)] pub fn is_sio(&self) -> bool { *self == FUNCSEL_A::SIO } - #[doc = "Checks if the value of the field is `PIO0`"] + #[doc = "Connect to PIO0 peripheral"] #[inline(always)] pub fn is_pio0(&self) -> bool { *self == FUNCSEL_A::PIO0 } - #[doc = "Checks if the value of the field is `PIO1`"] + #[doc = "Connect to PIO1 peripheral"] #[inline(always)] pub fn is_pio1(&self) -> bool { *self == FUNCSEL_A::PIO1 } - #[doc = "Checks if the value of the field is `CLOCK`"] + #[doc = "Connect to Clock peripheral"] #[inline(always)] pub fn is_clock(&self) -> bool { *self == FUNCSEL_A::CLOCK } - #[doc = "Checks if the value of the field is `USB`"] + #[doc = "Connect to USB peripheral"] #[inline(always)] pub fn is_usb(&self) -> bool { *self == FUNCSEL_A::USB } - #[doc = "Checks if the value of the field is `NULL`"] + #[doc = "Connect to nothing"] #[inline(always)] pub fn is_null(&self) -> bool { *self == FUNCSEL_A::NULL } } #[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] -pub type FUNCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_CTRL_SPEC, 5, O, FUNCSEL_A>; -impl<'a, const O: u8> FUNCSEL_W<'a, O> { +pub type FUNCSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, FUNCSEL_A>; +impl<'a, REG, const O: u8> FUNCSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Connect to JTAG peripheral"] #[inline(always)] - pub fn jtag(self) -> &'a mut W { + pub fn jtag(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::JTAG) } #[doc = "Connect to matching SPI peripheral"] #[inline(always)] - pub fn spi(self) -> &'a mut W { + pub fn spi(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::SPI) } #[doc = "Connect to matching UART peripheral"] #[inline(always)] - pub fn uart(self) -> &'a mut W { + pub fn uart(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::UART) } #[doc = "Connect to matching I2C peripheral"] #[inline(always)] - pub fn i2c(self) -> &'a mut W { + pub fn i2c(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::I2C) } #[doc = "Connect to matching PWM peripheral"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::PWM) } #[doc = "Use as a GPIO pin (connect to SIO peripheral)"] #[inline(always)] - pub fn sio(self) -> &'a mut W { + pub fn sio(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::SIO) } #[doc = "Connect to PIO0 peripheral"] #[inline(always)] - pub fn pio0(self) -> &'a mut W { + pub fn pio0(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::PIO0) } #[doc = "Connect to PIO1 peripheral"] #[inline(always)] - pub fn pio1(self) -> &'a mut W { + pub fn pio1(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::PIO1) } #[doc = "Connect to Clock peripheral"] #[inline(always)] - pub fn clock(self) -> &'a mut W { + pub fn clock(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::CLOCK) } #[doc = "Connect to USB peripheral"] #[inline(always)] - pub fn usb(self) -> &'a mut W { + pub fn usb(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::USB) } #[doc = "Connect to nothing"] #[inline(always)] - pub fn null(self) -> &'a mut W { + pub fn null(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::NULL) } } @@ -237,7 +209,7 @@ impl crate::FieldSpec for OUTOVER_A { impl OUTOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> OUTOVER_A { + pub const fn variant(&self) -> OUTOVER_A { match self.bits { 0 => OUTOVER_A::NORMAL, 1 => OUTOVER_A::INVERT, @@ -246,48 +218,52 @@ impl OUTOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "drive output from peripheral signal selected by funcsel"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == OUTOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == OUTOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive output low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == OUTOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive output high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == OUTOVER_A::HIGH } } #[doc = "Field `OUTOVER` writer - "] -pub type OUTOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, OUTOVER_A>; -impl<'a, const O: u8> OUTOVER_W<'a, O> { +pub type OUTOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OUTOVER_A>; +impl<'a, REG, const O: u8> OUTOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "drive output from peripheral signal selected by funcsel"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(OUTOVER_A::NORMAL) } #[doc = "drive output from inverse of peripheral signal selected by funcsel"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(OUTOVER_A::INVERT) } #[doc = "drive output low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(OUTOVER_A::LOW) } #[doc = "drive output high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(OUTOVER_A::HIGH) } } @@ -320,7 +296,7 @@ impl crate::FieldSpec for OEOVER_A { impl OEOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> OEOVER_A { + pub const fn variant(&self) -> OEOVER_A { match self.bits { 0 => OEOVER_A::NORMAL, 1 => OEOVER_A::INVERT, @@ -329,48 +305,52 @@ impl OEOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "drive output enable from peripheral signal selected by funcsel"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == OEOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == OEOVER_A::INVERT } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "disable output"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == OEOVER_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "enable output"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == OEOVER_A::ENABLE } } #[doc = "Field `OEOVER` writer - "] -pub type OEOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, OEOVER_A>; -impl<'a, const O: u8> OEOVER_W<'a, O> { +pub type OEOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OEOVER_A>; +impl<'a, REG, const O: u8> OEOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "drive output enable from peripheral signal selected by funcsel"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(OEOVER_A::NORMAL) } #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(OEOVER_A::INVERT) } #[doc = "disable output"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(OEOVER_A::DISABLE) } #[doc = "enable output"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(OEOVER_A::ENABLE) } } @@ -403,7 +383,7 @@ impl crate::FieldSpec for INOVER_A { impl INOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INOVER_A { + pub const fn variant(&self) -> INOVER_A { match self.bits { 0 => INOVER_A::NORMAL, 1 => INOVER_A::INVERT, @@ -412,48 +392,52 @@ impl INOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "don't invert the peri input"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == INOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "invert the peri input"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == INOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive peri input low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == INOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive peri input high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == INOVER_A::HIGH } } #[doc = "Field `INOVER` writer - "] -pub type INOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, INOVER_A>; -impl<'a, const O: u8> INOVER_W<'a, O> { +pub type INOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, INOVER_A>; +impl<'a, REG, const O: u8> INOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "don't invert the peri input"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(INOVER_A::NORMAL) } #[doc = "invert the peri input"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(INOVER_A::INVERT) } #[doc = "drive peri input low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(INOVER_A::LOW) } #[doc = "drive peri input high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(INOVER_A::HIGH) } } @@ -486,7 +470,7 @@ impl crate::FieldSpec for IRQOVER_A { impl IRQOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IRQOVER_A { + pub const fn variant(&self) -> IRQOVER_A { match self.bits { 0 => IRQOVER_A::NORMAL, 1 => IRQOVER_A::INVERT, @@ -495,48 +479,52 @@ impl IRQOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "don't invert the interrupt"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == IRQOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "invert the interrupt"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == IRQOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive interrupt low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == IRQOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive interrupt high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == IRQOVER_A::HIGH } } #[doc = "Field `IRQOVER` writer - "] -pub type IRQOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, IRQOVER_A>; -impl<'a, const O: u8> IRQOVER_W<'a, O> { +pub type IRQOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, IRQOVER_A>; +impl<'a, REG, const O: u8> IRQOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "don't invert the interrupt"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(IRQOVER_A::NORMAL) } #[doc = "invert the interrupt"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(IRQOVER_A::INVERT) } #[doc = "drive interrupt low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(IRQOVER_A::LOW) } #[doc = "drive interrupt high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(IRQOVER_A::HIGH) } } @@ -571,56 +559,55 @@ impl W { #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] #[inline(always)] #[must_use] - pub fn funcsel(&mut self) -> FUNCSEL_W<0> { + pub fn funcsel(&mut self) -> FUNCSEL_W { FUNCSEL_W::new(self) } #[doc = "Bits 8:9"] #[inline(always)] #[must_use] - pub fn outover(&mut self) -> OUTOVER_W<8> { + pub fn outover(&mut self) -> OUTOVER_W { OUTOVER_W::new(self) } #[doc = "Bits 12:13"] #[inline(always)] #[must_use] - pub fn oeover(&mut self) -> OEOVER_W<12> { + pub fn oeover(&mut self) -> OEOVER_W { OEOVER_W::new(self) } #[doc = "Bits 16:17"] #[inline(always)] #[must_use] - pub fn inover(&mut self) -> INOVER_W<16> { + pub fn inover(&mut self) -> INOVER_W { INOVER_W::new(self) } #[doc = "Bits 28:29"] #[inline(always)] #[must_use] - pub fn irqover(&mut self) -> IRQOVER_W<28> { + pub fn irqover(&mut self) -> IRQOVER_W { IRQOVER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO control including function select and overrides. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_CTRL_SPEC; impl crate::RegisterSpec for GPIO_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_ctrl::R](R) reader structure"] -impl crate::Readable for GPIO_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_ctrl::R`](R) reader structure"] +impl crate::Readable for GPIO_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] impl crate::Writable for GPIO_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/io_bank0/gpio/gpio_status.rs index 62044d6cf..2efb9aaee 100644 --- a/src/io_bank0/gpio/gpio_status.rs +++ b/src/io_bank0/gpio/gpio_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `GPIO_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub type OUTFROMPERI_R = crate::BitReader; #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] @@ -73,17 +60,13 @@ impl R { } #[doc = "GPIO status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_STATUS_SPEC; impl crate::RegisterSpec for GPIO_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_status::R](R) reader structure"] -impl crate::Readable for GPIO_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] +impl crate::Readable for GPIO_STATUS_SPEC {} #[doc = "`reset()` method sets GPIO_STATUS to value 0"] impl crate::Resettable for GPIO_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_bank0/intr.rs b/src/io_bank0/intr.rs index 05830fd4c..1388182c8 100644 --- a/src/io_bank0/intr.rs +++ b/src/io_bank0/intr.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTR%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTR%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -41,11 +9,11 @@ pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] @@ -53,11 +21,11 @@ pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] @@ -65,11 +33,11 @@ pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] @@ -77,11 +45,11 @@ pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] @@ -89,11 +57,11 @@ pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] @@ -101,11 +69,11 @@ pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] @@ -113,11 +81,11 @@ pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] @@ -125,11 +93,11 @@ pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -296,122 +264,121 @@ impl W { #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intr::W](W) writer structure"] +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xcccc_cccc; } diff --git a/src/io_bank0/proc0_inte.rs b/src/io_bank0/proc0_inte.rs index 57d5914b0..5fa2c0732 100644 --- a/src/io_bank0/proc0_inte.rs +++ b/src/io_bank0/proc0_inte.rs @@ -1,167 +1,135 @@ #[doc = "Register `PROC0_INTE%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC0_INTE%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for proc%s -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTE_SPEC; impl crate::RegisterSpec for PROC0_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_inte::R](R) reader structure"] -impl crate::Readable for PROC0_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc0_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`proc0_inte::R`](R) reader structure"] +impl crate::Readable for PROC0_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] impl crate::Writable for PROC0_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/proc0_intf.rs b/src/io_bank0/proc0_intf.rs index bb9c9141f..f9bfd3171 100644 --- a/src/io_bank0/proc0_intf.rs +++ b/src/io_bank0/proc0_intf.rs @@ -1,167 +1,135 @@ #[doc = "Register `PROC0_INTF%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC0_INTF%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for proc%s -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTF_SPEC; impl crate::RegisterSpec for PROC0_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_intf::R](R) reader structure"] -impl crate::Readable for PROC0_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc0_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`proc0_intf::R`](R) reader structure"] +impl crate::Readable for PROC0_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] impl crate::Writable for PROC0_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/proc0_ints.rs b/src/io_bank0/proc0_ints.rs index deeb72726..18b3ba903 100644 --- a/src/io_bank0/proc0_ints.rs +++ b/src/io_bank0/proc0_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `PROC0_INTS%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -241,17 +228,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for proc%s -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTS_SPEC; impl crate::RegisterSpec for PROC0_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_ints::R](R) reader structure"] -impl crate::Readable for PROC0_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] +impl crate::Readable for PROC0_INTS_SPEC {} #[doc = "`reset()` method sets PROC0_INTS%s to value 0"] impl crate::Resettable for PROC0_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_bank0/proc1_inte.rs b/src/io_bank0/proc1_inte.rs index 7789b1243..29e8c35c5 100644 --- a/src/io_bank0/proc1_inte.rs +++ b/src/io_bank0/proc1_inte.rs @@ -1,167 +1,135 @@ #[doc = "Register `PROC1_INTE%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC1_INTE%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for proc1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTE_SPEC; impl crate::RegisterSpec for PROC1_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_inte::R](R) reader structure"] -impl crate::Readable for PROC1_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc1_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`proc1_inte::R`](R) reader structure"] +impl crate::Readable for PROC1_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] impl crate::Writable for PROC1_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/proc1_intf.rs b/src/io_bank0/proc1_intf.rs index 6c7fc9f19..59e45b3f9 100644 --- a/src/io_bank0/proc1_intf.rs +++ b/src/io_bank0/proc1_intf.rs @@ -1,167 +1,135 @@ #[doc = "Register `PROC1_INTF%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC1_INTF%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_LOW` writer - "] -pub type GPIO0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] -pub type GPIO0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub type GPIO0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_LOW` writer - "] -pub type GPIO0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub type GPIO0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO0_EDGE_HIGH` writer - "] -pub type GPIO0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub type GPIO1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_LOW` writer - "] -pub type GPIO1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] -pub type GPIO1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub type GPIO1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_LOW` writer - "] -pub type GPIO1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub type GPIO1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO1_EDGE_HIGH` writer - "] -pub type GPIO1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub type GPIO2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_LOW` writer - "] -pub type GPIO2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] -pub type GPIO2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub type GPIO2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_LOW` writer - "] -pub type GPIO2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub type GPIO2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO2_EDGE_HIGH` writer - "] -pub type GPIO2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub type GPIO3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_LOW` writer - "] -pub type GPIO3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] -pub type GPIO3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub type GPIO3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_LOW` writer - "] -pub type GPIO3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub type GPIO3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO3_EDGE_HIGH` writer - "] -pub type GPIO3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub type GPIO4_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_LOW` writer - "] -pub type GPIO4_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO4_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] -pub type GPIO4_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO4_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub type GPIO4_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_LOW` writer - "] -pub type GPIO4_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO4_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub type GPIO4_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO4_EDGE_HIGH` writer - "] -pub type GPIO4_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO4_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub type GPIO5_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_LOW` writer - "] -pub type GPIO5_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO5_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] -pub type GPIO5_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO5_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub type GPIO5_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_LOW` writer - "] -pub type GPIO5_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO5_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub type GPIO5_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO5_EDGE_HIGH` writer - "] -pub type GPIO5_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO5_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub type GPIO6_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_LOW` writer - "] -pub type GPIO6_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO6_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] -pub type GPIO6_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO6_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub type GPIO6_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_LOW` writer - "] -pub type GPIO6_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO6_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub type GPIO6_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO6_EDGE_HIGH` writer - "] -pub type GPIO6_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO6_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub type GPIO7_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_LOW` writer - "] -pub type GPIO7_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO7_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] -pub type GPIO7_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO7_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub type GPIO7_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_LOW` writer - "] -pub type GPIO7_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO7_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub type GPIO7_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO7_EDGE_HIGH` writer - "] -pub type GPIO7_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO7_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<0> { + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { GPIO0_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<1> { + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { GPIO0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<2> { + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { GPIO0_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<3> { + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { GPIO0_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<4> { + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { GPIO1_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<5> { + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { GPIO1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<6> { + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { GPIO1_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<7> { + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { GPIO1_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<8> { + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { GPIO2_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<9> { + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { GPIO2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<10> { + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { GPIO2_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<11> { + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { GPIO2_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<12> { + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { GPIO3_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<13> { + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { GPIO3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<14> { + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { GPIO3_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<15> { + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { GPIO3_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<16> { + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { GPIO4_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<17> { + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { GPIO4_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<18> { + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { GPIO4_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<19> { + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { GPIO4_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<20> { + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { GPIO5_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<21> { + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { GPIO5_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<22> { + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { GPIO5_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<23> { + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { GPIO5_EDGE_HIGH_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<24> { + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { GPIO6_LEVEL_LOW_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<25> { + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { GPIO6_LEVEL_HIGH_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<26> { + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { GPIO6_EDGE_LOW_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<27> { + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { GPIO6_EDGE_HIGH_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<28> { + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { GPIO7_LEVEL_LOW_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<29> { + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { GPIO7_LEVEL_HIGH_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<30> { + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { GPIO7_EDGE_LOW_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<31> { + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for proc1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTF_SPEC; impl crate::RegisterSpec for PROC1_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_intf::R](R) reader structure"] -impl crate::Readable for PROC1_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc1_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`proc1_intf::R`](R) reader structure"] +impl crate::Readable for PROC1_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] impl crate::Writable for PROC1_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_bank0/proc1_ints.rs b/src/io_bank0/proc1_ints.rs index c3fd60025..4320be3fa 100644 --- a/src/io_bank0/proc1_ints.rs +++ b/src/io_bank0/proc1_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `PROC1_INTS%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -241,17 +228,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for proc1 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTS_SPEC; impl crate::RegisterSpec for PROC1_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_ints::R](R) reader structure"] -impl crate::Readable for PROC1_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] +impl crate::Readable for PROC1_INTS_SPEC {} #[doc = "`reset()` method sets PROC1_INTS%s to value 0"] impl crate::Resettable for PROC1_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_qspi.rs b/src/io_qspi.rs index 55dafa046..0077b24f6 100644 --- a/src/io_qspi.rs +++ b/src/io_qspi.rs @@ -61,43 +61,93 @@ pub use self::gpio_qspi::GPIO_QSPI; #[doc = r"Cluster"] #[doc = "Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] pub mod gpio_qspi; -#[doc = "INTR (rw) register accessor: an alias for `Reg`"] +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "PROC0_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc0 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_inte`] +module"] pub type PROC0_INTE = crate::Reg; #[doc = "Interrupt Enable for proc0"] pub mod proc0_inte; -#[doc = "PROC0_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc0 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_intf`] +module"] pub type PROC0_INTF = crate::Reg; #[doc = "Interrupt Force for proc0"] pub mod proc0_intf; -#[doc = "PROC0_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking & forcing for proc0 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_ints`] +module"] pub type PROC0_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for proc0"] pub mod proc0_ints; -#[doc = "PROC1_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_inte`] +module"] pub type PROC1_INTE = crate::Reg; #[doc = "Interrupt Enable for proc1"] pub mod proc1_inte; -#[doc = "PROC1_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_intf`] +module"] pub type PROC1_INTF = crate::Reg; #[doc = "Interrupt Force for proc1"] pub mod proc1_intf; -#[doc = "PROC1_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_ints`] +module"] pub type PROC1_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for proc1"] pub mod proc1_ints; -#[doc = "DORMANT_WAKE_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_inte`] +module"] pub type DORMANT_WAKE_INTE = crate::Reg; #[doc = "Interrupt Enable for dormant_wake"] pub mod dormant_wake_inte; -#[doc = "DORMANT_WAKE_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_intf`] +module"] pub type DORMANT_WAKE_INTF = crate::Reg; #[doc = "Interrupt Force for dormant_wake"] pub mod dormant_wake_intf; -#[doc = "DORMANT_WAKE_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_ints`] +module"] pub type DORMANT_WAKE_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for dormant_wake"] pub mod dormant_wake_ints; diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/io_qspi/dormant_wake_inte.rs index 69806828e..68be462fd 100644 --- a/src/io_qspi/dormant_wake_inte.rs +++ b/src/io_qspi/dormant_wake_inte.rs @@ -1,158 +1,103 @@ #[doc = "Register `DORMANT_WAKE_INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT_WAKE_INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -279,170 +224,215 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low( + &mut self, + ) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high( + &mut self, + ) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high( + &mut self, + ) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low( + &mut self, + ) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high( + &mut self, + ) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low( + &mut self, + ) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high( + &mut self, + ) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low( + &mut self, + ) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high( + &mut self, + ) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low( + &mut self, + ) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high( + &mut self, + ) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for dormant_wake -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTE_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_inte::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant_wake_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant_wake_inte::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/io_qspi/dormant_wake_intf.rs index 0ebdb6889..69e041ac7 100644 --- a/src/io_qspi/dormant_wake_intf.rs +++ b/src/io_qspi/dormant_wake_intf.rs @@ -1,158 +1,103 @@ #[doc = "Register `DORMANT_WAKE_INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT_WAKE_INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = - crate::BitWriter<'a, DORMANT_WAKE_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -279,170 +224,215 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low( + &mut self, + ) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high( + &mut self, + ) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high( + &mut self, + ) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low( + &mut self, + ) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high( + &mut self, + ) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low( + &mut self, + ) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high( + &mut self, + ) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low( + &mut self, + ) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high( + &mut self, + ) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low( + &mut self, + ) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high( + &mut self, + ) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for dormant_wake -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTF_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_intf::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant_wake_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant_wake_intf::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/io_qspi/dormant_wake_ints.rs index e6284b61f..ffb2cd09e 100644 --- a/src/io_qspi/dormant_wake_ints.rs +++ b/src/io_qspi/dormant_wake_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `DORMANT_WAKE_INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -185,17 +172,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for dormant_wake -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant_wake_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTS_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant_wake_ints::R](R) reader structure"] -impl crate::Readable for DORMANT_WAKE_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} #[doc = "`reset()` method sets DORMANT_WAKE_INTS to value 0"] impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_qspi/gpio_qspi.rs b/src/io_qspi/gpio_qspi.rs index ba90447d6..ac890089d 100644 --- a/src/io_qspi/gpio_qspi.rs +++ b/src/io_qspi/gpio_qspi.rs @@ -6,11 +6,21 @@ pub struct GPIO_QSPI { #[doc = "0x04 - GPIO control including function select and overrides."] pub gpio_ctrl: GPIO_CTRL, } -#[doc = "GPIO_STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "GPIO_STATUS (r) register accessor: GPIO status + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_status`] +module"] pub type GPIO_STATUS = crate::Reg; #[doc = "GPIO status"] pub mod gpio_status; -#[doc = "GPIO_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_CTRL (rw) register accessor: GPIO control including function select and overrides. + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_ctrl`] +module"] pub type GPIO_CTRL = crate::Reg; #[doc = "GPIO control including function select and overrides."] pub mod gpio_ctrl; diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs index a2049ebbb..378c39f74 100644 --- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs +++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table 31 == NULL"] pub type FUNCSEL_R = crate::FieldReader; @@ -63,7 +31,7 @@ impl crate::FieldSpec for FUNCSEL_A { impl FUNCSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(FUNCSEL_A::XIP_SCLK), 5 => Some(FUNCSEL_A::SIO_30), @@ -71,17 +39,17 @@ impl FUNCSEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `XIP_SCLK`"] + #[doc = "`0`"] #[inline(always)] pub fn is_xip_sclk(&self) -> bool { *self == FUNCSEL_A::XIP_SCLK } - #[doc = "Checks if the value of the field is `SIO_30`"] + #[doc = "`101`"] #[inline(always)] pub fn is_sio_30(&self) -> bool { *self == FUNCSEL_A::SIO_30 } - #[doc = "Checks if the value of the field is `NULL`"] + #[doc = "`11111`"] #[inline(always)] pub fn is_null(&self) -> bool { *self == FUNCSEL_A::NULL @@ -89,21 +57,25 @@ impl FUNCSEL_R { } #[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table 31 == NULL"] -pub type FUNCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_CTRL_SPEC, 5, O, FUNCSEL_A>; -impl<'a, const O: u8> FUNCSEL_W<'a, O> { +pub type FUNCSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, FUNCSEL_A>; +impl<'a, REG, const O: u8> FUNCSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn xip_sclk(self) -> &'a mut W { + pub fn xip_sclk(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::XIP_SCLK) } #[doc = "`101`"] #[inline(always)] - pub fn sio_30(self) -> &'a mut W { + pub fn sio_30(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::SIO_30) } #[doc = "`11111`"] #[inline(always)] - pub fn null(self) -> &'a mut W { + pub fn null(self) -> &'a mut crate::W { self.variant(FUNCSEL_A::NULL) } } @@ -136,7 +108,7 @@ impl crate::FieldSpec for OUTOVER_A { impl OUTOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> OUTOVER_A { + pub const fn variant(&self) -> OUTOVER_A { match self.bits { 0 => OUTOVER_A::NORMAL, 1 => OUTOVER_A::INVERT, @@ -145,48 +117,52 @@ impl OUTOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "drive output from peripheral signal selected by funcsel"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == OUTOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == OUTOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive output low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == OUTOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive output high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == OUTOVER_A::HIGH } } #[doc = "Field `OUTOVER` writer - "] -pub type OUTOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, OUTOVER_A>; -impl<'a, const O: u8> OUTOVER_W<'a, O> { +pub type OUTOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OUTOVER_A>; +impl<'a, REG, const O: u8> OUTOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "drive output from peripheral signal selected by funcsel"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(OUTOVER_A::NORMAL) } #[doc = "drive output from inverse of peripheral signal selected by funcsel"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(OUTOVER_A::INVERT) } #[doc = "drive output low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(OUTOVER_A::LOW) } #[doc = "drive output high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(OUTOVER_A::HIGH) } } @@ -219,7 +195,7 @@ impl crate::FieldSpec for OEOVER_A { impl OEOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> OEOVER_A { + pub const fn variant(&self) -> OEOVER_A { match self.bits { 0 => OEOVER_A::NORMAL, 1 => OEOVER_A::INVERT, @@ -228,48 +204,52 @@ impl OEOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "drive output enable from peripheral signal selected by funcsel"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == OEOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == OEOVER_A::INVERT } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "disable output"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == OEOVER_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "enable output"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == OEOVER_A::ENABLE } } #[doc = "Field `OEOVER` writer - "] -pub type OEOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, OEOVER_A>; -impl<'a, const O: u8> OEOVER_W<'a, O> { +pub type OEOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OEOVER_A>; +impl<'a, REG, const O: u8> OEOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "drive output enable from peripheral signal selected by funcsel"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(OEOVER_A::NORMAL) } #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(OEOVER_A::INVERT) } #[doc = "disable output"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(OEOVER_A::DISABLE) } #[doc = "enable output"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(OEOVER_A::ENABLE) } } @@ -302,7 +282,7 @@ impl crate::FieldSpec for INOVER_A { impl INOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INOVER_A { + pub const fn variant(&self) -> INOVER_A { match self.bits { 0 => INOVER_A::NORMAL, 1 => INOVER_A::INVERT, @@ -311,48 +291,52 @@ impl INOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "don't invert the peri input"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == INOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "invert the peri input"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == INOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive peri input low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == INOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive peri input high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == INOVER_A::HIGH } } #[doc = "Field `INOVER` writer - "] -pub type INOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, INOVER_A>; -impl<'a, const O: u8> INOVER_W<'a, O> { +pub type INOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, INOVER_A>; +impl<'a, REG, const O: u8> INOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "don't invert the peri input"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(INOVER_A::NORMAL) } #[doc = "invert the peri input"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(INOVER_A::INVERT) } #[doc = "drive peri input low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(INOVER_A::LOW) } #[doc = "drive peri input high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(INOVER_A::HIGH) } } @@ -385,7 +369,7 @@ impl crate::FieldSpec for IRQOVER_A { impl IRQOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> IRQOVER_A { + pub const fn variant(&self) -> IRQOVER_A { match self.bits { 0 => IRQOVER_A::NORMAL, 1 => IRQOVER_A::INVERT, @@ -394,48 +378,52 @@ impl IRQOVER_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "don't invert the interrupt"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == IRQOVER_A::NORMAL } - #[doc = "Checks if the value of the field is `INVERT`"] + #[doc = "invert the interrupt"] #[inline(always)] pub fn is_invert(&self) -> bool { *self == IRQOVER_A::INVERT } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "drive interrupt low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == IRQOVER_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "drive interrupt high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == IRQOVER_A::HIGH } } #[doc = "Field `IRQOVER` writer - "] -pub type IRQOVER_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_CTRL_SPEC, 2, O, IRQOVER_A>; -impl<'a, const O: u8> IRQOVER_W<'a, O> { +pub type IRQOVER_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, IRQOVER_A>; +impl<'a, REG, const O: u8> IRQOVER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "don't invert the interrupt"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(IRQOVER_A::NORMAL) } #[doc = "invert the interrupt"] #[inline(always)] - pub fn invert(self) -> &'a mut W { + pub fn invert(self) -> &'a mut crate::W { self.variant(IRQOVER_A::INVERT) } #[doc = "drive interrupt low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(IRQOVER_A::LOW) } #[doc = "drive interrupt high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(IRQOVER_A::HIGH) } } @@ -472,56 +460,55 @@ impl W { 31 == NULL"] #[inline(always)] #[must_use] - pub fn funcsel(&mut self) -> FUNCSEL_W<0> { + pub fn funcsel(&mut self) -> FUNCSEL_W { FUNCSEL_W::new(self) } #[doc = "Bits 8:9"] #[inline(always)] #[must_use] - pub fn outover(&mut self) -> OUTOVER_W<8> { + pub fn outover(&mut self) -> OUTOVER_W { OUTOVER_W::new(self) } #[doc = "Bits 12:13"] #[inline(always)] #[must_use] - pub fn oeover(&mut self) -> OEOVER_W<12> { + pub fn oeover(&mut self) -> OEOVER_W { OEOVER_W::new(self) } #[doc = "Bits 16:17"] #[inline(always)] #[must_use] - pub fn inover(&mut self) -> INOVER_W<16> { + pub fn inover(&mut self) -> INOVER_W { INOVER_W::new(self) } #[doc = "Bits 28:29"] #[inline(always)] #[must_use] - pub fn irqover(&mut self) -> IRQOVER_W<28> { + pub fn irqover(&mut self) -> IRQOVER_W { IRQOVER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO control including function select and overrides. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_CTRL_SPEC; impl crate::RegisterSpec for GPIO_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_ctrl::R](R) reader structure"] -impl crate::Readable for GPIO_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_ctrl::R`](R) reader structure"] +impl crate::Readable for GPIO_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] impl crate::Writable for GPIO_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/io_qspi/gpio_qspi/gpio_status.rs index 62044d6cf..2efb9aaee 100644 --- a/src/io_qspi/gpio_qspi/gpio_status.rs +++ b/src/io_qspi/gpio_qspi/gpio_status.rs @@ -1,18 +1,5 @@ #[doc = "Register `GPIO_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub type OUTFROMPERI_R = crate::BitReader; #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] @@ -73,17 +60,13 @@ impl R { } #[doc = "GPIO status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_STATUS_SPEC; impl crate::RegisterSpec for GPIO_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_status::R](R) reader structure"] -impl crate::Readable for GPIO_STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] +impl crate::Readable for GPIO_STATUS_SPEC {} #[doc = "`reset()` method sets GPIO_STATUS to value 0"] impl crate::Resettable for GPIO_STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_qspi/intr.rs b/src/io_qspi/intr.rs index a2e7a8e29..62c103371 100644 --- a/src/io_qspi/intr.rs +++ b/src/io_qspi/intr.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -41,11 +9,11 @@ pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] @@ -53,11 +21,11 @@ pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] @@ -65,11 +33,11 @@ pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] @@ -77,11 +45,11 @@ pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] @@ -89,11 +57,11 @@ pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] @@ -101,11 +69,11 @@ pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -232,98 +200,97 @@ impl W { #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intr::W](W) writer structure"] +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00cc_cccc; } diff --git a/src/io_qspi/proc0_inte.rs b/src/io_qspi/proc0_inte.rs index c487d3e16..94e903f9f 100644 --- a/src/io_qspi/proc0_inte.rs +++ b/src/io_qspi/proc0_inte.rs @@ -1,135 +1,103 @@ #[doc = "Register `PROC0_INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC0_INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -256,170 +224,169 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for proc0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTE_SPEC; impl crate::RegisterSpec for PROC0_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_inte::R](R) reader structure"] -impl crate::Readable for PROC0_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc0_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`proc0_inte::R`](R) reader structure"] +impl crate::Readable for PROC0_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] impl crate::Writable for PROC0_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/proc0_intf.rs b/src/io_qspi/proc0_intf.rs index 521d7dde4..051f213f5 100644 --- a/src/io_qspi/proc0_intf.rs +++ b/src/io_qspi/proc0_intf.rs @@ -1,135 +1,103 @@ #[doc = "Register `PROC0_INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC0_INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC0_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -256,170 +224,169 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for proc0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTF_SPEC; impl crate::RegisterSpec for PROC0_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_intf::R](R) reader structure"] -impl crate::Readable for PROC0_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc0_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`proc0_intf::R`](R) reader structure"] +impl crate::Readable for PROC0_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] impl crate::Writable for PROC0_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/proc0_ints.rs b/src/io_qspi/proc0_ints.rs index 45b33bb38..c2b0dac7a 100644 --- a/src/io_qspi/proc0_ints.rs +++ b/src/io_qspi/proc0_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `PROC0_INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -185,17 +172,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for proc0 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTS_SPEC; impl crate::RegisterSpec for PROC0_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_ints::R](R) reader structure"] -impl crate::Readable for PROC0_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] +impl crate::Readable for PROC0_INTS_SPEC {} #[doc = "`reset()` method sets PROC0_INTS to value 0"] impl crate::Resettable for PROC0_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/io_qspi/proc1_inte.rs b/src/io_qspi/proc1_inte.rs index 97a0af0da..69d56915b 100644 --- a/src/io_qspi/proc1_inte.rs +++ b/src/io_qspi/proc1_inte.rs @@ -1,135 +1,103 @@ #[doc = "Register `PROC1_INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC1_INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTE_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -256,170 +224,169 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for proc1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTE_SPEC; impl crate::RegisterSpec for PROC1_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_inte::R](R) reader structure"] -impl crate::Readable for PROC1_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc1_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`proc1_inte::R`](R) reader structure"] +impl crate::Readable for PROC1_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] impl crate::Writable for PROC1_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/proc1_intf.rs b/src/io_qspi/proc1_intf.rs index 0c3c3e621..a2a6a44c1 100644 --- a/src/io_qspi/proc1_intf.rs +++ b/src/io_qspi/proc1_intf.rs @@ -1,135 +1,103 @@ #[doc = "Register `PROC1_INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC1_INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] -pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] -pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] -pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, PROC1_INTF_SPEC, O>; +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -256,170 +224,169 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<0> { + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<1> { + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<2> { + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { GPIO_QSPI_SCLK_EDGE_LOW_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<3> { + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<4> { + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { GPIO_QSPI_SS_LEVEL_LOW_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<5> { + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { GPIO_QSPI_SS_LEVEL_HIGH_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<6> { + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { GPIO_QSPI_SS_EDGE_LOW_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<7> { + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { GPIO_QSPI_SS_EDGE_HIGH_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<8> { + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { GPIO_QSPI_SD0_LEVEL_LOW_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<9> { + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<10> { + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { GPIO_QSPI_SD0_EDGE_LOW_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<11> { + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { GPIO_QSPI_SD0_EDGE_HIGH_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<12> { + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { GPIO_QSPI_SD1_LEVEL_LOW_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<13> { + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<14> { + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { GPIO_QSPI_SD1_EDGE_LOW_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<15> { + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { GPIO_QSPI_SD1_EDGE_HIGH_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<16> { + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { GPIO_QSPI_SD2_LEVEL_LOW_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<17> { + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<18> { + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { GPIO_QSPI_SD2_EDGE_LOW_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<19> { + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { GPIO_QSPI_SD2_EDGE_HIGH_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<20> { + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { GPIO_QSPI_SD3_LEVEL_LOW_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<21> { + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<22> { + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { GPIO_QSPI_SD3_EDGE_LOW_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<23> { + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for proc1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTF_SPEC; impl crate::RegisterSpec for PROC1_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_intf::R](R) reader structure"] -impl crate::Readable for PROC1_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc1_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`proc1_intf::R`](R) reader structure"] +impl crate::Readable for PROC1_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] impl crate::Writable for PROC1_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/io_qspi/proc1_ints.rs b/src/io_qspi/proc1_ints.rs index 8f5bcf2de..0d6cc6079 100644 --- a/src/io_qspi/proc1_ints.rs +++ b/src/io_qspi/proc1_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `PROC1_INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -185,17 +172,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for proc1 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTS_SPEC; impl crate::RegisterSpec for PROC1_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_ints::R](R) reader structure"] -impl crate::Readable for PROC1_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] +impl crate::Readable for PROC1_INTS_SPEC {} #[doc = "`reset()` method sets PROC1_INTS to value 0"] impl crate::Resettable for PROC1_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/lib.rs b/src/lib.rs index 999c2f03f..a23722cc8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,11 +1,11 @@ -#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.29.0 ( )) +#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.30.2 ( )) You can find an overview of the generated API [here]. API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. -[here]: https://docs.rs/svd2rust/0.29.0/svd2rust/#peripheral-api +[here]: https://docs.rs/svd2rust/0.30.2/svd2rust/#peripheral-api [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased [repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] @@ -16,7 +16,8 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] +#![deny(private_bounds)] +#![deny(private_interfaces)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] @@ -245,6 +246,24 @@ impl XIP_CTRL { pub const fn ptr() -> *const xip_ctrl::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for XIP_CTRL { type Target = xip_ctrl::RegisterBlock; @@ -298,6 +317,24 @@ impl XIP_SSI { pub const fn ptr() -> *const xip_ssi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for XIP_SSI { type Target = xip_ssi::RegisterBlock; @@ -351,6 +388,24 @@ impl SYSINFO { pub const fn ptr() -> *const sysinfo::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYSINFO { type Target = sysinfo::RegisterBlock; @@ -379,6 +434,24 @@ impl SYSCFG { pub const fn ptr() -> *const syscfg::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYSCFG { type Target = syscfg::RegisterBlock; @@ -407,6 +480,24 @@ impl CLOCKS { pub const fn ptr() -> *const clocks::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CLOCKS { type Target = clocks::RegisterBlock; @@ -435,6 +526,24 @@ impl RESETS { pub const fn ptr() -> *const resets::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RESETS { type Target = resets::RegisterBlock; @@ -463,6 +572,24 @@ impl PSM { pub const fn ptr() -> *const psm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PSM { type Target = psm::RegisterBlock; @@ -491,6 +618,24 @@ impl IO_BANK0 { pub const fn ptr() -> *const io_bank0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for IO_BANK0 { type Target = io_bank0::RegisterBlock; @@ -519,6 +664,24 @@ impl IO_QSPI { pub const fn ptr() -> *const io_qspi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for IO_QSPI { type Target = io_qspi::RegisterBlock; @@ -547,6 +710,24 @@ impl PADS_BANK0 { pub const fn ptr() -> *const pads_bank0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PADS_BANK0 { type Target = pads_bank0::RegisterBlock; @@ -575,6 +756,24 @@ impl PADS_QSPI { pub const fn ptr() -> *const pads_qspi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PADS_QSPI { type Target = pads_qspi::RegisterBlock; @@ -603,6 +802,24 @@ impl XOSC { pub const fn ptr() -> *const xosc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for XOSC { type Target = xosc::RegisterBlock; @@ -631,6 +848,24 @@ impl PLL_SYS { pub const fn ptr() -> *const pll_sys::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PLL_SYS { type Target = pll_sys::RegisterBlock; @@ -659,6 +894,24 @@ impl PLL_USB { pub const fn ptr() -> *const pll_sys::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PLL_USB { type Target = pll_sys::RegisterBlock; @@ -687,6 +940,24 @@ impl BUSCTRL { pub const fn ptr() -> *const busctrl::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BUSCTRL { type Target = busctrl::RegisterBlock; @@ -715,6 +986,24 @@ impl UART0 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART0 { type Target = uart0::RegisterBlock; @@ -743,6 +1032,24 @@ impl UART1 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART1 { type Target = uart0::RegisterBlock; @@ -771,6 +1078,24 @@ impl SPI0 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI0 { type Target = spi0::RegisterBlock; @@ -799,6 +1124,24 @@ impl SPI1 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI1 { type Target = spi0::RegisterBlock; @@ -898,6 +1241,24 @@ impl I2C0 { pub const fn ptr() -> *const i2c0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for I2C0 { type Target = i2c0::RegisterBlock; @@ -1068,6 +1429,24 @@ impl I2C1 { pub const fn ptr() -> *const i2c0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for I2C1 { type Target = i2c0::RegisterBlock; @@ -1167,6 +1546,24 @@ impl ADC { pub const fn ptr() -> *const adc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ADC { type Target = adc::RegisterBlock; @@ -1195,6 +1592,24 @@ impl PWM { pub const fn ptr() -> *const pwm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM { type Target = pwm::RegisterBlock; @@ -1232,6 +1647,24 @@ impl TIMER { pub const fn ptr() -> *const timer::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TIMER { type Target = timer::RegisterBlock; @@ -1269,6 +1702,24 @@ impl WATCHDOG { pub const fn ptr() -> *const watchdog::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for WATCHDOG { type Target = watchdog::RegisterBlock; @@ -1297,6 +1748,24 @@ impl RTC { pub const fn ptr() -> *const rtc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RTC { type Target = rtc::RegisterBlock; @@ -1325,6 +1794,24 @@ impl ROSC { pub const fn ptr() -> *const rosc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ROSC { type Target = rosc::RegisterBlock; @@ -1353,6 +1840,24 @@ impl VREG_AND_CHIP_RESET { pub const fn ptr() -> *const vreg_and_chip_reset::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for VREG_AND_CHIP_RESET { type Target = vreg_and_chip_reset::RegisterBlock; @@ -1381,6 +1886,24 @@ impl TBMAN { pub const fn ptr() -> *const tbman::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TBMAN { type Target = tbman::RegisterBlock; @@ -1409,6 +1932,24 @@ impl DMA { pub const fn ptr() -> *const dma::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for DMA { type Target = dma::RegisterBlock; @@ -1437,6 +1978,24 @@ impl USBCTRL_DPRAM { pub const fn ptr() -> *const usbctrl_dpram::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USBCTRL_DPRAM { type Target = usbctrl_dpram::RegisterBlock; @@ -1465,6 +2024,24 @@ impl USBCTRL_REGS { pub const fn ptr() -> *const usbctrl_regs::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USBCTRL_REGS { type Target = usbctrl_regs::RegisterBlock; @@ -1493,6 +2070,24 @@ impl PIO0 { pub const fn ptr() -> *const pio0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIO0 { type Target = pio0::RegisterBlock; @@ -1521,6 +2116,24 @@ impl PIO1 { pub const fn ptr() -> *const pio0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIO1 { type Target = pio0::RegisterBlock; @@ -1550,6 +2163,24 @@ impl SIO { pub const fn ptr() -> *const sio::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SIO { type Target = sio::RegisterBlock; @@ -1579,6 +2210,24 @@ impl PPB { pub const fn ptr() -> *const ppb::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PPB { type Target = ppb::RegisterBlock; diff --git a/src/pads_bank0.rs b/src/pads_bank0.rs index 3de652e2e..8e3cce7c2 100644 --- a/src/pads_bank0.rs +++ b/src/pads_bank0.rs @@ -10,19 +10,39 @@ pub struct RegisterBlock { #[doc = "0x80 - Pad control register"] pub swd: SWD, } -#[doc = "VOLTAGE_SELECT (rw) register accessor: an alias for `Reg`"] +#[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control + +You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@voltage_select`] +module"] pub type VOLTAGE_SELECT = crate::Reg; #[doc = "Voltage select. Per bank control"] pub mod voltage_select; -#[doc = "GPIO (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio`] +module"] pub type GPIO = crate::Reg; #[doc = "Pad control register"] pub mod gpio; -#[doc = "SWCLK (rw) register accessor: an alias for `Reg`"] +#[doc = "SWCLK (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`swclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@swclk`] +module"] pub type SWCLK = crate::Reg; #[doc = "Pad control register"] pub mod swclk; -#[doc = "SWD (rw) register accessor: an alias for `Reg`"] +#[doc = "SWD (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`swd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@swd`] +module"] pub type SWD = crate::Reg; #[doc = "Pad control register"] pub mod swd; diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs index 5f5b44a1c..c6a0b18e2 100644 --- a/src/pads_bank0/gpio.rs +++ b/src/pads_bank0/gpio.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_SPEC; impl crate::RegisterSpec for GPIO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio::R](R) reader structure"] -impl crate::Readable for GPIO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio::R`](R) reader structure"] +impl crate::Readable for GPIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio::W`](W) writer structure"] impl crate::Writable for GPIO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs index adb7c3d5b..d9a1c5783 100644 --- a/src/pads_bank0/swclk.rs +++ b/src/pads_bank0/swclk.rs @@ -1,55 +1,23 @@ #[doc = "Register `SWCLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SWCLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, SWCLK_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, SWCLK_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [swclk](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`swclk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SWCLK_SPEC; impl crate::RegisterSpec for SWCLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [swclk::R](R) reader structure"] -impl crate::Readable for SWCLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [swclk::W](W) writer structure"] +#[doc = "`read()` method returns [`swclk::R`](R) reader structure"] +impl crate::Readable for SWCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swclk::W`](W) writer structure"] impl crate::Writable for SWCLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs index 77a31e72e..6c9afa5ee 100644 --- a/src/pads_bank0/swd.rs +++ b/src/pads_bank0/swd.rs @@ -1,55 +1,23 @@ #[doc = "Register `SWD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SWD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, SWD_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, SWD_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [swd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`swd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SWD_SPEC; impl crate::RegisterSpec for SWD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [swd::R](R) reader structure"] -impl crate::Readable for SWD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [swd::W](W) writer structure"] +#[doc = "`read()` method returns [`swd::R`](R) reader structure"] +impl crate::Readable for SWD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swd::W`](W) writer structure"] impl crate::Writable for SWD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_bank0/voltage_select.rs b/src/pads_bank0/voltage_select.rs index 9da4a9a8e..a9aae42cc 100644 --- a/src/pads_bank0/voltage_select.rs +++ b/src/pads_bank0/voltage_select.rs @@ -1,39 +1,7 @@ #[doc = "Register `VOLTAGE_SELECT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `VOLTAGE_SELECT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VOLTAGE_SELECT` reader - "] pub type VOLTAGE_SELECT_R = crate::BitReader; #[doc = " @@ -55,35 +23,37 @@ impl From for bool { impl VOLTAGE_SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> VOLTAGE_SELECT_A { + pub const fn variant(&self) -> VOLTAGE_SELECT_A { match self.bits { false => VOLTAGE_SELECT_A::_3V3, true => VOLTAGE_SELECT_A::_1V8, } } - #[doc = "Checks if the value of the field is `_3V3`"] + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] #[inline(always)] pub fn is_3v3(&self) -> bool { *self == VOLTAGE_SELECT_A::_3V3 } - #[doc = "Checks if the value of the field is `_1V8`"] + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] #[inline(always)] pub fn is_1v8(&self) -> bool { *self == VOLTAGE_SELECT_A::_1V8 } } #[doc = "Field `VOLTAGE_SELECT` writer - "] -pub type VOLTAGE_SELECT_W<'a, const O: u8> = - crate::BitWriter<'a, VOLTAGE_SELECT_SPEC, O, VOLTAGE_SELECT_A>; -impl<'a, const O: u8> VOLTAGE_SELECT_W<'a, O> { +pub type VOLTAGE_SELECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VOLTAGE_SELECT_A>; +impl<'a, REG, const O: u8> VOLTAGE_SELECT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] #[inline(always)] - pub fn _3v3(self) -> &'a mut W { + pub fn _3v3(self) -> &'a mut crate::W { self.variant(VOLTAGE_SELECT_A::_3V3) } #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] #[inline(always)] - pub fn _1v8(self) -> &'a mut W { + pub fn _1v8(self) -> &'a mut crate::W { self.variant(VOLTAGE_SELECT_A::_1V8) } } @@ -98,32 +68,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<0> { + pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { VOLTAGE_SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Voltage select. Per bank control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [voltage_select](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VOLTAGE_SELECT_SPEC; impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [voltage_select::R](R) reader structure"] -impl crate::Readable for VOLTAGE_SELECT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [voltage_select::W](W) writer structure"] +#[doc = "`read()` method returns [`voltage_select::R`](R) reader structure"] +impl crate::Readable for VOLTAGE_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] impl crate::Writable for VOLTAGE_SELECT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi.rs b/src/pads_qspi.rs index d5205028b..c64b47d9c 100644 --- a/src/pads_qspi.rs +++ b/src/pads_qspi.rs @@ -16,31 +16,66 @@ pub struct RegisterBlock { #[doc = "0x18 - Pad control register"] pub gpio_qspi_ss: GPIO_QSPI_SS, } -#[doc = "VOLTAGE_SELECT (rw) register accessor: an alias for `Reg`"] +#[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control + +You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@voltage_select`] +module"] pub type VOLTAGE_SELECT = crate::Reg; #[doc = "Voltage select. Per bank control"] pub mod voltage_select; -#[doc = "GPIO_QSPI_SCLK (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SCLK (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sclk`] +module"] pub type GPIO_QSPI_SCLK = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_sclk; -#[doc = "GPIO_QSPI_SD0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SD0 (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd0`] +module"] pub type GPIO_QSPI_SD0 = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_sd0; -#[doc = "GPIO_QSPI_SD1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SD1 (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd1`] +module"] pub type GPIO_QSPI_SD1 = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_sd1; -#[doc = "GPIO_QSPI_SD2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SD2 (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd2`] +module"] pub type GPIO_QSPI_SD2 = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_sd2; -#[doc = "GPIO_QSPI_SD3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SD3 (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd3`] +module"] pub type GPIO_QSPI_SD3 = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_sd3; -#[doc = "GPIO_QSPI_SS (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_QSPI_SS (rw) register accessor: Pad control register + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_ss::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_ss`] +module"] pub type GPIO_QSPI_SS = crate::Reg; #[doc = "Pad control register"] pub mod gpio_qspi_ss; diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs index 540f716aa..f45c53e43 100644 --- a/src/pads_qspi/gpio_qspi_sclk.rs +++ b/src/pads_qspi/gpio_qspi_sclk.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SCLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SCLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SCLK_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SCLK_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_sclk](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sclk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SCLK_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SCLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_sclk::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SCLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_sclk::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_sclk::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sclk::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SCLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs index 97c3ebd92..722a991d7 100644 --- a/src/pads_qspi/gpio_qspi_sd0.rs +++ b/src/pads_qspi/gpio_qspi_sd0.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SD0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SD0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SD0_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD0_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_sd0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SD0_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SD0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_sd0::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SD0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_sd0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_sd0::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd0::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs index aab06e7a6..2b2a9d3c4 100644 --- a/src/pads_qspi/gpio_qspi_sd1.rs +++ b/src/pads_qspi/gpio_qspi_sd1.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SD1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SD1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SD1_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD1_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_sd1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SD1_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SD1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_sd1::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SD1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_sd1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_sd1::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd1::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs index dc1f317b1..f0312c650 100644 --- a/src/pads_qspi/gpio_qspi_sd2.rs +++ b/src/pads_qspi/gpio_qspi_sd2.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SD2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SD2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SD2_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD2_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_sd2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SD2_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SD2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_sd2::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SD2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_sd2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_sd2::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd2::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs index 685be5162..32ae701f5 100644 --- a/src/pads_qspi/gpio_qspi_sd3.rs +++ b/src/pads_qspi/gpio_qspi_sd3.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SD3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SD3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SD3_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SD3_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_sd3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SD3_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SD3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_sd3::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SD3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_sd3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_sd3::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd3::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs index f6dfd19ba..8a80d36b1 100644 --- a/src/pads_qspi/gpio_qspi_ss.rs +++ b/src/pads_qspi/gpio_qspi_ss.rs @@ -1,55 +1,23 @@ #[doc = "Register `GPIO_QSPI_SS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_QSPI_SS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub type SLEWFAST_R = crate::BitReader; #[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] -pub type SLEWFAST_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type SLEWFAST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub type SCHMITT_R = crate::BitReader; #[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] -pub type SCHMITT_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type SCHMITT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDE` reader - Pull down enable"] pub type PDE_R = crate::BitReader; #[doc = "Field `PDE` writer - Pull down enable"] -pub type PDE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type PDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUE` reader - Pull up enable"] pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] -pub type PUE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type PUE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIVE` reader - Drive strength."] pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. @@ -79,7 +47,7 @@ impl crate::FieldSpec for DRIVE_A { impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DRIVE_A { + pub const fn variant(&self) -> DRIVE_A { match self.bits { 0 => DRIVE_A::_2M_A, 1 => DRIVE_A::_4M_A, @@ -88,59 +56,63 @@ impl DRIVE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_2M_A`"] + #[doc = "`0`"] #[inline(always)] pub fn is_2m_a(&self) -> bool { *self == DRIVE_A::_2M_A } - #[doc = "Checks if the value of the field is `_4M_A`"] + #[doc = "`1`"] #[inline(always)] pub fn is_4m_a(&self) -> bool { *self == DRIVE_A::_4M_A } - #[doc = "Checks if the value of the field is `_8M_A`"] + #[doc = "`10`"] #[inline(always)] pub fn is_8m_a(&self) -> bool { *self == DRIVE_A::_8M_A } - #[doc = "Checks if the value of the field is `_12M_A`"] + #[doc = "`11`"] #[inline(always)] pub fn is_12m_a(&self) -> bool { *self == DRIVE_A::_12M_A } } #[doc = "Field `DRIVE` writer - Drive strength."] -pub type DRIVE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, GPIO_QSPI_SS_SPEC, 2, O, DRIVE_A>; -impl<'a, const O: u8> DRIVE_W<'a, O> { +pub type DRIVE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DRIVE_A>; +impl<'a, REG, const O: u8> DRIVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _2m_a(self) -> &'a mut W { + pub fn _2m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_2M_A) } #[doc = "`1`"] #[inline(always)] - pub fn _4m_a(self) -> &'a mut W { + pub fn _4m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_4M_A) } #[doc = "`10`"] #[inline(always)] - pub fn _8m_a(self) -> &'a mut W { + pub fn _8m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_8M_A) } #[doc = "`11`"] #[inline(always)] - pub fn _12m_a(self) -> &'a mut W { + pub fn _12m_a(self) -> &'a mut crate::W { self.variant(DRIVE_A::_12M_A) } } #[doc = "Field `IE` reader - Input enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - Input enable"] -pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub type OD_R = crate::BitReader; #[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] -pub type OD_W<'a, const O: u8> = crate::BitWriter<'a, GPIO_QSPI_SS_SPEC, O>; +pub type OD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] @@ -182,68 +154,67 @@ impl W { #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] #[inline(always)] #[must_use] - pub fn slewfast(&mut self) -> SLEWFAST_W<0> { + pub fn slewfast(&mut self) -> SLEWFAST_W { SLEWFAST_W::new(self) } #[doc = "Bit 1 - Enable schmitt trigger"] #[inline(always)] #[must_use] - pub fn schmitt(&mut self) -> SCHMITT_W<1> { + pub fn schmitt(&mut self) -> SCHMITT_W { SCHMITT_W::new(self) } #[doc = "Bit 2 - Pull down enable"] #[inline(always)] #[must_use] - pub fn pde(&mut self) -> PDE_W<2> { + pub fn pde(&mut self) -> PDE_W { PDE_W::new(self) } #[doc = "Bit 3 - Pull up enable"] #[inline(always)] #[must_use] - pub fn pue(&mut self) -> PUE_W<3> { + pub fn pue(&mut self) -> PUE_W { PUE_W::new(self) } #[doc = "Bits 4:5 - Drive strength."] #[inline(always)] #[must_use] - pub fn drive(&mut self) -> DRIVE_W<4> { + pub fn drive(&mut self) -> DRIVE_W { DRIVE_W::new(self) } #[doc = "Bit 6 - Input enable"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W<6> { + pub fn ie(&mut self) -> IE_W { IE_W::new(self) } #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] #[inline(always)] #[must_use] - pub fn od(&mut self) -> OD_W<7> { + pub fn od(&mut self) -> OD_W { OD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Pad control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_qspi_ss](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_ss::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_QSPI_SS_SPEC; impl crate::RegisterSpec for GPIO_QSPI_SS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_qspi_ss::R](R) reader structure"] -impl crate::Readable for GPIO_QSPI_SS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_qspi_ss::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_qspi_ss::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_ss::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pads_qspi/voltage_select.rs b/src/pads_qspi/voltage_select.rs index 9da4a9a8e..a9aae42cc 100644 --- a/src/pads_qspi/voltage_select.rs +++ b/src/pads_qspi/voltage_select.rs @@ -1,39 +1,7 @@ #[doc = "Register `VOLTAGE_SELECT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `VOLTAGE_SELECT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VOLTAGE_SELECT` reader - "] pub type VOLTAGE_SELECT_R = crate::BitReader; #[doc = " @@ -55,35 +23,37 @@ impl From for bool { impl VOLTAGE_SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> VOLTAGE_SELECT_A { + pub const fn variant(&self) -> VOLTAGE_SELECT_A { match self.bits { false => VOLTAGE_SELECT_A::_3V3, true => VOLTAGE_SELECT_A::_1V8, } } - #[doc = "Checks if the value of the field is `_3V3`"] + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] #[inline(always)] pub fn is_3v3(&self) -> bool { *self == VOLTAGE_SELECT_A::_3V3 } - #[doc = "Checks if the value of the field is `_1V8`"] + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] #[inline(always)] pub fn is_1v8(&self) -> bool { *self == VOLTAGE_SELECT_A::_1V8 } } #[doc = "Field `VOLTAGE_SELECT` writer - "] -pub type VOLTAGE_SELECT_W<'a, const O: u8> = - crate::BitWriter<'a, VOLTAGE_SELECT_SPEC, O, VOLTAGE_SELECT_A>; -impl<'a, const O: u8> VOLTAGE_SELECT_W<'a, O> { +pub type VOLTAGE_SELECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VOLTAGE_SELECT_A>; +impl<'a, REG, const O: u8> VOLTAGE_SELECT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] #[inline(always)] - pub fn _3v3(self) -> &'a mut W { + pub fn _3v3(self) -> &'a mut crate::W { self.variant(VOLTAGE_SELECT_A::_3V3) } #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] #[inline(always)] - pub fn _1v8(self) -> &'a mut W { + pub fn _1v8(self) -> &'a mut crate::W { self.variant(VOLTAGE_SELECT_A::_1V8) } } @@ -98,32 +68,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<0> { + pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { VOLTAGE_SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Voltage select. Per bank control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [voltage_select](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VOLTAGE_SELECT_SPEC; impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [voltage_select::R](R) reader structure"] -impl crate::Readable for VOLTAGE_SELECT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [voltage_select::W](W) writer structure"] +#[doc = "`read()` method returns [`voltage_select::R`](R) reader structure"] +impl crate::Readable for VOLTAGE_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] impl crate::Writable for VOLTAGE_SELECT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0.rs b/src/pio0.rs index 832122046..bdf6cadc1 100644 --- a/src/pio0.rs +++ b/src/pio0.rs @@ -40,61 +40,132 @@ pub struct RegisterBlock { #[doc = "0x12c..0x144 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] pub sm_irq: [SM_IRQ; 2], } -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: PIO control register + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "PIO control register"] pub mod ctrl; -#[doc = "FSTAT (r) register accessor: an alias for `Reg`"] +#[doc = "FSTAT (r) register accessor: FIFO status register + +You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fstat`] +module"] pub type FSTAT = crate::Reg; #[doc = "FIFO status register"] pub mod fstat; -#[doc = "FDEBUG (rw) register accessor: an alias for `Reg`"] +#[doc = "FDEBUG (rw) register accessor: FIFO debug register + +You can [`read`](crate::generic::Reg::read) this register and get [`fdebug::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdebug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fdebug`] +module"] pub type FDEBUG = crate::Reg; #[doc = "FIFO debug register"] pub mod fdebug; -#[doc = "FLEVEL (r) register accessor: an alias for `Reg`"] +#[doc = "FLEVEL (r) register accessor: FIFO levels + +You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flevel`] +module"] pub type FLEVEL = crate::Reg; #[doc = "FIFO levels"] pub mod flevel; -#[doc = "TXF (w) register accessor: an alias for `Reg`"] +#[doc = "TXF (w) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txf`] +module"] pub type TXF = crate::Reg; #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] pub mod txf; -#[doc = "RXF (r) register accessor: an alias for `Reg`"] +#[doc = "RXF (r) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + +You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf`] +module"] pub type RXF = crate::Reg; #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] pub mod rxf; -#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ (rw) register accessor: State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + +You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq`] +module"] pub type IRQ = crate::Reg; #[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] pub mod irq; -#[doc = "IRQ_FORCE (w) register accessor: an alias for `Reg`"] +#[doc = "IRQ_FORCE (w) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_force`] +module"] pub type IRQ_FORCE = crate::Reg; #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] pub mod irq_force; -#[doc = "INPUT_SYNC_BYPASS (rw) register accessor: an alias for `Reg`"] +#[doc = "INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + +You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@input_sync_bypass`] +module"] pub type INPUT_SYNC_BYPASS = crate::Reg; #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] pub mod input_sync_bypass; -#[doc = "DBG_PADOUT (r) register accessor: an alias for `Reg`"] +#[doc = "DBG_PADOUT (r) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_padout`] +module"] pub type DBG_PADOUT = crate::Reg; #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] pub mod dbg_padout; -#[doc = "DBG_PADOE (r) register accessor: an alias for `Reg`"] +#[doc = "DBG_PADOE (r) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_padoe`] +module"] pub type DBG_PADOE = crate::Reg; #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] pub mod dbg_padoe; -#[doc = "DBG_CFGINFO (r) register accessor: an alias for `Reg`"] +#[doc = "DBG_CFGINFO (r) register accessor: The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_cfginfo`] +module"] pub type DBG_CFGINFO = crate::Reg; #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] pub mod dbg_cfginfo; -#[doc = "INSTR_MEM (w) register accessor: an alias for `Reg`"] +#[doc = "INSTR_MEM (w) register accessor: Write-only access to instruction memory location %s + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@instr_mem`] +module"] pub type INSTR_MEM = crate::Reg; #[doc = "Write-only access to instruction memory location %s"] pub mod instr_mem; @@ -103,7 +174,12 @@ pub use self::sm::SM; #[doc = r"Cluster"] #[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] pub mod sm; -#[doc = "INTR (r) register accessor: an alias for `Reg`"] +#[doc = "INTR (r) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs index 9b332c4b0..474e232ac 100644 --- a/src/pio0/ctrl.rs +++ b/src/pio0/ctrl.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SM_ENABLE` reader - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] pub type SM_ENABLE_R = crate::FieldReader; #[doc = "Field `SM_ENABLE` writer - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] -pub type SM_ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type SM_ENABLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SM_RESTART` reader - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. @@ -49,7 +17,7 @@ pub type SM_RESTART_R = crate::FieldReader; Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] -pub type SM_RESTART_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type SM_RESTART_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CLKDIV_RESTART` reader - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. @@ -61,7 +29,7 @@ pub type CLKDIV_RESTART_R = crate::FieldReader; Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] -pub type CLKDIV_RESTART_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type CLKDIV_RESTART_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] #[inline(always)] @@ -91,7 +59,7 @@ impl W { #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] #[inline(always)] #[must_use] - pub fn sm_enable(&mut self) -> SM_ENABLE_W<0> { + pub fn sm_enable(&mut self) -> SM_ENABLE_W { SM_ENABLE_W::new(self) } #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. @@ -101,7 +69,7 @@ impl W { The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] #[inline(always)] #[must_use] - pub fn sm_restart(&mut self) -> SM_RESTART_W<4> { + pub fn sm_restart(&mut self) -> SM_RESTART_W { SM_RESTART_W::new(self) } #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. @@ -111,32 +79,31 @@ impl W { Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] #[inline(always)] #[must_use] - pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W<8> { + pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W { CLKDIV_RESTART_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "PIO control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/dbg_cfginfo.rs b/src/pio0/dbg_cfginfo.rs index fcc3c1a77..4d9e91e03 100644 --- a/src/pio0/dbg_cfginfo.rs +++ b/src/pio0/dbg_cfginfo.rs @@ -1,18 +1,5 @@ #[doc = "Register `DBG_CFGINFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FIFO_DEPTH` reader - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] @@ -43,17 +30,13 @@ impl R { #[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dbg_cfginfo](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_CFGINFO_SPEC; impl crate::RegisterSpec for DBG_CFGINFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_cfginfo::R](R) reader structure"] -impl crate::Readable for DBG_CFGINFO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dbg_cfginfo::R`](R) reader structure"] +impl crate::Readable for DBG_CFGINFO_SPEC {} #[doc = "`reset()` method sets DBG_CFGINFO to value 0"] impl crate::Resettable for DBG_CFGINFO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/dbg_padoe.rs b/src/pio0/dbg_padoe.rs index f617853b9..ab6c7c165 100644 --- a/src/pio0/dbg_padoe.rs +++ b/src/pio0/dbg_padoe.rs @@ -1,18 +1,5 @@ #[doc = "Register `DBG_PADOE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dbg_padoe](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_PADOE_SPEC; impl crate::RegisterSpec for DBG_PADOE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_padoe::R](R) reader structure"] -impl crate::Readable for DBG_PADOE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dbg_padoe::R`](R) reader structure"] +impl crate::Readable for DBG_PADOE_SPEC {} #[doc = "`reset()` method sets DBG_PADOE to value 0"] impl crate::Resettable for DBG_PADOE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/dbg_padout.rs b/src/pio0/dbg_padout.rs index eeea45e17..b6f706a44 100644 --- a/src/pio0/dbg_padout.rs +++ b/src/pio0/dbg_padout.rs @@ -1,18 +1,5 @@ #[doc = "Register `DBG_PADOUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dbg_padout](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_PADOUT_SPEC; impl crate::RegisterSpec for DBG_PADOUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_padout::R](R) reader structure"] -impl crate::Readable for DBG_PADOUT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dbg_padout::R`](R) reader structure"] +impl crate::Readable for DBG_PADOUT_SPEC {} #[doc = "`reset()` method sets DBG_PADOUT to value 0"] impl crate::Resettable for DBG_PADOUT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/fdebug.rs b/src/pio0/fdebug.rs index 61813f508..7848ffebc 100644 --- a/src/pio0/fdebug.rs +++ b/src/pio0/fdebug.rs @@ -1,55 +1,23 @@ #[doc = "Register `FDEBUG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FDEBUG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXSTALL` reader - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] pub type RXSTALL_R = crate::FieldReader; #[doc = "Field `RXSTALL` writer - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] -pub type RXSTALL_W<'a, const O: u8> = crate::FieldWriter<'a, FDEBUG_SPEC, 4, O>; +pub type RXSTALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RXUNDER` reader - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] pub type RXUNDER_R = crate::FieldReader; #[doc = "Field `RXUNDER` writer - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] -pub type RXUNDER_W<'a, const O: u8> = crate::FieldWriter<'a, FDEBUG_SPEC, 4, O>; +pub type RXUNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TXOVER` reader - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] pub type TXOVER_R = crate::FieldReader; #[doc = "Field `TXOVER` writer - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] -pub type TXOVER_W<'a, const O: u8> = crate::FieldWriter<'a, FDEBUG_SPEC, 4, O>; +pub type TXOVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TXSTALL` reader - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] pub type TXSTALL_R = crate::FieldReader; #[doc = "Field `TXSTALL` writer - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] -pub type TXSTALL_W<'a, const O: u8> = crate::FieldWriter<'a, FDEBUG_SPEC, 4, O>; +pub type TXSTALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 0:3 - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] #[inline(always)] #[must_use] - pub fn rxstall(&mut self) -> RXSTALL_W<0> { + pub fn rxstall(&mut self) -> RXSTALL_W { RXSTALL_W::new(self) } #[doc = "Bits 8:11 - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] #[inline(always)] #[must_use] - pub fn rxunder(&mut self) -> RXUNDER_W<8> { + pub fn rxunder(&mut self) -> RXUNDER_W { RXUNDER_W::new(self) } #[doc = "Bits 16:19 - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] #[inline(always)] #[must_use] - pub fn txover(&mut self) -> TXOVER_W<16> { + pub fn txover(&mut self) -> TXOVER_W { TXOVER_W::new(self) } #[doc = "Bits 24:27 - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] #[inline(always)] #[must_use] - pub fn txstall(&mut self) -> TXSTALL_W<24> { + pub fn txstall(&mut self) -> TXSTALL_W { TXSTALL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "FIFO debug register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fdebug](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fdebug::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdebug::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FDEBUG_SPEC; impl crate::RegisterSpec for FDEBUG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fdebug::R](R) reader structure"] -impl crate::Readable for FDEBUG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fdebug::W](W) writer structure"] +#[doc = "`read()` method returns [`fdebug::R`](R) reader structure"] +impl crate::Readable for FDEBUG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fdebug::W`](W) writer structure"] impl crate::Writable for FDEBUG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f0f_0f0f; } diff --git a/src/pio0/flevel.rs b/src/pio0/flevel.rs index 6db1c8ed4..ab8ede0d6 100644 --- a/src/pio0/flevel.rs +++ b/src/pio0/flevel.rs @@ -1,18 +1,5 @@ #[doc = "Register `FLEVEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TX0` reader - "] pub type TX0_R = crate::FieldReader; #[doc = "Field `RX0` reader - "] @@ -73,17 +60,13 @@ impl R { } #[doc = "FIFO levels -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [flevel](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FLEVEL_SPEC; impl crate::RegisterSpec for FLEVEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [flevel::R](R) reader structure"] -impl crate::Readable for FLEVEL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`flevel::R`](R) reader structure"] +impl crate::Readable for FLEVEL_SPEC {} #[doc = "`reset()` method sets FLEVEL to value 0"] impl crate::Resettable for FLEVEL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/fstat.rs b/src/pio0/fstat.rs index 1cca26dae..4c89ca4b7 100644 --- a/src/pio0/fstat.rs +++ b/src/pio0/fstat.rs @@ -1,18 +1,5 @@ #[doc = "Register `FSTAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXFULL` reader - State machine RX FIFO is full"] pub type RXFULL_R = crate::FieldReader; #[doc = "Field `RXEMPTY` reader - State machine RX FIFO is empty"] @@ -45,17 +32,13 @@ impl R { } #[doc = "FIFO status register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fstat](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSTAT_SPEC; impl crate::RegisterSpec for FSTAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fstat::R](R) reader structure"] -impl crate::Readable for FSTAT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fstat::R`](R) reader structure"] +impl crate::Readable for FSTAT_SPEC {} #[doc = "`reset()` method sets FSTAT to value 0x0f00_0f00"] impl crate::Resettable for FSTAT_SPEC { const RESET_VALUE: Self::Ux = 0x0f00_0f00; diff --git a/src/pio0/input_sync_bypass.rs b/src/pio0/input_sync_bypass.rs index 022c50b74..36ee00029 100644 --- a/src/pio0/input_sync_bypass.rs +++ b/src/pio0/input_sync_bypass.rs @@ -1,39 +1,7 @@ #[doc = "Register `INPUT_SYNC_BYPASS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INPUT_SYNC_BYPASS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [input_sync_bypass](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INPUT_SYNC_BYPASS_SPEC; impl crate::RegisterSpec for INPUT_SYNC_BYPASS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [input_sync_bypass::R](R) reader structure"] -impl crate::Readable for INPUT_SYNC_BYPASS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [input_sync_bypass::W](W) writer structure"] +#[doc = "`read()` method returns [`input_sync_bypass::R`](R) reader structure"] +impl crate::Readable for INPUT_SYNC_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`input_sync_bypass::W`](W) writer structure"] impl crate::Writable for INPUT_SYNC_BYPASS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/instr_mem.rs b/src/pio0/instr_mem.rs index 8a9de5aed..688a0bf1d 100644 --- a/src/pio0/instr_mem.rs +++ b/src/pio0/instr_mem.rs @@ -1,52 +1,34 @@ #[doc = "Register `INSTR_MEM%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INSTR_MEM0` writer - "] -pub type INSTR_MEM0_W<'a, const O: u8> = crate::FieldWriter<'a, INSTR_MEM_SPEC, 16, O, u16>; +pub type INSTR_MEM0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn instr_mem0(&mut self) -> INSTR_MEM0_W<0> { + pub fn instr_mem0(&mut self) -> INSTR_MEM0_W { INSTR_MEM0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Write-only access to instruction memory location %s -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [instr_mem](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INSTR_MEM_SPEC; impl crate::RegisterSpec for INSTR_MEM_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [instr_mem::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`instr_mem::W`](W) writer structure"] impl crate::Writable for INSTR_MEM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/intr.rs b/src/pio0/intr.rs index 092796852..ee881195a 100644 --- a/src/pio0/intr.rs +++ b/src/pio0/intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` reader - "] @@ -101,17 +88,13 @@ impl R { } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs index 6879e0b24..1a0324b67 100644 --- a/src/pio0/irq.rs +++ b/src/pio0/irq.rs @@ -1,43 +1,11 @@ #[doc = "Register `IRQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRQ` reader - "] pub type IRQ_R = crate::FieldReader; #[doc = "Field `IRQ` writer - "] -pub type IRQ_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SPEC, 8, O>; +pub type IRQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7"] #[inline(always)] @@ -49,13 +17,17 @@ impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn irq(&mut self) -> IRQ_W<0> { + pub fn irq(&mut self) -> IRQ_W { IRQ_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -63,20 +35,15 @@ impl W { Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SPEC; impl crate::RegisterSpec for IRQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq::R](R) reader structure"] -impl crate::Readable for IRQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +#[doc = "`read()` method returns [`irq::R`](R) reader structure"] +impl crate::Readable for IRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] impl crate::Writable for IRQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/src/pio0/irq_force.rs b/src/pio0/irq_force.rs index f72bca7ac..c4026fdf5 100644 --- a/src/pio0/irq_force.rs +++ b/src/pio0/irq_force.rs @@ -1,52 +1,34 @@ #[doc = "Register `IRQ_FORCE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRQ_FORCE` writer - "] -pub type IRQ_FORCE_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_FORCE_SPEC, 8, O>; +pub type IRQ_FORCE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn irq_force(&mut self) -> IRQ_FORCE_W<0> { + pub fn irq_force(&mut self) -> IRQ_FORCE_W { IRQ_FORCE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_force](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_FORCE_SPEC; impl crate::RegisterSpec for IRQ_FORCE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [irq_force::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`irq_force::W`](W) writer structure"] impl crate::Writable for IRQ_FORCE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/rxf.rs b/src/pio0/rxf.rs index 9198568b1..ca7d2bda4 100644 --- a/src/pio0/rxf.rs +++ b/src/pio0/rxf.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXF%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rxf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF_SPEC; impl crate::RegisterSpec for RXF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf::R](R) reader structure"] -impl crate::Readable for RXF_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxf::R`](R) reader structure"] +impl crate::Readable for RXF_SPEC {} #[doc = "`reset()` method sets RXF%s to value 0"] impl crate::Resettable for RXF_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/sm.rs b/src/pio0/sm.rs index ad1962f22..890adce7c 100644 --- a/src/pio0/sm.rs +++ b/src/pio0/sm.rs @@ -16,29 +16,61 @@ pub struct SM { #[doc = "0x14 - State machine pin control"] pub sm_pinctrl: SM_PINCTRL, } -#[doc = "SM_CLKDIV (rw) register accessor: an alias for `Reg`"] +#[doc = "SM_CLKDIV (rw) register accessor: Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_clkdiv`] +module"] pub type SM_CLKDIV = crate::Reg; #[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] pub mod sm_clkdiv; -#[doc = "SM_EXECCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "SM_EXECCTRL (rw) register accessor: Execution/behavioural settings for state machine 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_execctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_execctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_execctrl`] +module"] pub type SM_EXECCTRL = crate::Reg; #[doc = "Execution/behavioural settings for state machine 0"] pub mod sm_execctrl; -#[doc = "SM_SHIFTCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "SM_SHIFTCTRL (rw) register accessor: Control behaviour of the input/output shift registers for state machine 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_shiftctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_shiftctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_shiftctrl`] +module"] pub type SM_SHIFTCTRL = crate::Reg; #[doc = "Control behaviour of the input/output shift registers for state machine 0"] pub mod sm_shiftctrl; -#[doc = "SM_ADDR (r) register accessor: an alias for `Reg`"] +#[doc = "SM_ADDR (r) register accessor: Current instruction address of state machine 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_addr`] +module"] pub type SM_ADDR = crate::Reg; #[doc = "Current instruction address of state machine 0"] pub mod sm_addr; -#[doc = "SM_INSTR (rw) register accessor: an alias for `Reg`"] +#[doc = "SM_INSTR (rw) register accessor: Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_instr`] +module"] pub type SM_INSTR = crate::Reg; #[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] pub mod sm_instr; -#[doc = "SM_PINCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "SM_PINCTRL (rw) register accessor: State machine pin control + +You can [`read`](crate::generic::Reg::read) this register and get [`sm_pinctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_pinctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_pinctrl`] +module"] pub type SM_PINCTRL = crate::Reg; #[doc = "State machine pin control"] pub mod sm_pinctrl; diff --git a/src/pio0/sm/sm_addr.rs b/src/pio0/sm/sm_addr.rs index e8aed8595..e0340acab 100644 --- a/src/pio0/sm/sm_addr.rs +++ b/src/pio0/sm/sm_addr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SM_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SM0_ADDR` reader - "] pub type SM0_ADDR_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Current instruction address of state machine 0 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_ADDR_SPEC; impl crate::RegisterSpec for SM_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_addr::R](R) reader structure"] -impl crate::Readable for SM_ADDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sm_addr::R`](R) reader structure"] +impl crate::Readable for SM_ADDR_SPEC {} #[doc = "`reset()` method sets SM_ADDR to value 0"] impl crate::Resettable for SM_ADDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs index 366a44cca..e08331ba4 100644 --- a/src/pio0/sm/sm_clkdiv.rs +++ b/src/pio0/sm/sm_clkdiv.rs @@ -1,49 +1,17 @@ #[doc = "Register `SM_CLKDIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SM_CLKDIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - Fractional part of clock divisor"] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional part of clock divisor"] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, SM_CLKDIV_SPEC, 8, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT` reader - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, SM_CLKDIV_SPEC, 16, O, u16>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 8:15 - Fractional part of clock divisor"] #[inline(always)] @@ -61,40 +29,39 @@ impl W { #[doc = "Bits 8:15 - Fractional part of clock divisor"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<8> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<16> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_clkdiv](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_CLKDIV_SPEC; impl crate::RegisterSpec for SM_CLKDIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_clkdiv::R](R) reader structure"] -impl crate::Readable for SM_CLKDIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sm_clkdiv::W](W) writer structure"] +#[doc = "`read()` method returns [`sm_clkdiv::R`](R) reader structure"] +impl crate::Readable for SM_CLKDIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_clkdiv::W`](W) writer structure"] impl crate::Writable for SM_CLKDIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs index 78fc53e47..bd534259c 100644 --- a/src/pio0/sm/sm_execctrl.rs +++ b/src/pio0/sm/sm_execctrl.rs @@ -1,43 +1,11 @@ #[doc = "Register `SM_EXECCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SM_EXECCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STATUS_N` reader - Comparison level for the MOV x, STATUS instruction"] pub type STATUS_N_R = crate::FieldReader; #[doc = "Field `STATUS_N` writer - Comparison level for the MOV x, STATUS instruction"] -pub type STATUS_N_W<'a, const O: u8> = crate::FieldWriter<'a, SM_EXECCTRL_SPEC, 4, O>; +pub type STATUS_N_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."] pub type STATUS_SEL_R = crate::BitReader; #[doc = "Comparison used for the MOV x, STATUS instruction. @@ -59,51 +27,54 @@ impl From for bool { impl STATUS_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> STATUS_SEL_A { + pub const fn variant(&self) -> STATUS_SEL_A { match self.bits { false => STATUS_SEL_A::TXLEVEL, true => STATUS_SEL_A::RXLEVEL, } } - #[doc = "Checks if the value of the field is `TXLEVEL`"] + #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] #[inline(always)] pub fn is_txlevel(&self) -> bool { *self == STATUS_SEL_A::TXLEVEL } - #[doc = "Checks if the value of the field is `RXLEVEL`"] + #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] #[inline(always)] pub fn is_rxlevel(&self) -> bool { *self == STATUS_SEL_A::RXLEVEL } } #[doc = "Field `STATUS_SEL` writer - Comparison used for the MOV x, STATUS instruction."] -pub type STATUS_SEL_W<'a, const O: u8> = crate::BitWriter<'a, SM_EXECCTRL_SPEC, O, STATUS_SEL_A>; -impl<'a, const O: u8> STATUS_SEL_W<'a, O> { +pub type STATUS_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, STATUS_SEL_A>; +impl<'a, REG, const O: u8> STATUS_SEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] #[inline(always)] - pub fn txlevel(self) -> &'a mut W { + pub fn txlevel(self) -> &'a mut crate::W { self.variant(STATUS_SEL_A::TXLEVEL) } #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] #[inline(always)] - pub fn rxlevel(self) -> &'a mut W { + pub fn rxlevel(self) -> &'a mut crate::W { self.variant(STATUS_SEL_A::RXLEVEL) } } #[doc = "Field `WRAP_BOTTOM` reader - After reaching wrap_top, execution is wrapped to this address."] pub type WRAP_BOTTOM_R = crate::FieldReader; #[doc = "Field `WRAP_BOTTOM` writer - After reaching wrap_top, execution is wrapped to this address."] -pub type WRAP_BOTTOM_W<'a, const O: u8> = crate::FieldWriter<'a, SM_EXECCTRL_SPEC, 5, O>; +pub type WRAP_BOTTOM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `WRAP_TOP` reader - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] pub type WRAP_TOP_R = crate::FieldReader; #[doc = "Field `WRAP_TOP` writer - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] -pub type WRAP_TOP_W<'a, const O: u8> = crate::FieldWriter<'a, SM_EXECCTRL_SPEC, 5, O>; +pub type WRAP_TOP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `OUT_STICKY` reader - Continuously assert the most recent OUT/SET to the pins"] pub type OUT_STICKY_R = crate::BitReader; #[doc = "Field `OUT_STICKY` writer - Continuously assert the most recent OUT/SET to the pins"] -pub type OUT_STICKY_W<'a, const O: u8> = crate::BitWriter<'a, SM_EXECCTRL_SPEC, O>; +pub type OUT_STICKY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour @@ -113,23 +84,23 @@ pub type INLINE_OUT_EN_R = crate::BitReader; When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] -pub type INLINE_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, SM_EXECCTRL_SPEC, O>; +pub type INLINE_OUT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"] pub type OUT_EN_SEL_R = crate::FieldReader; #[doc = "Field `OUT_EN_SEL` writer - Which data bit to use for inline OUT enable"] -pub type OUT_EN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, SM_EXECCTRL_SPEC, 5, O>; +pub type OUT_EN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `JMP_PIN` reader - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] pub type JMP_PIN_R = crate::FieldReader; #[doc = "Field `JMP_PIN` writer - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] -pub type JMP_PIN_W<'a, const O: u8> = crate::FieldWriter<'a, SM_EXECCTRL_SPEC, 5, O>; +pub type JMP_PIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIDE_PINDIR` reader - If 1, side-set data is asserted to pin directions, instead of pin values"] pub type SIDE_PINDIR_R = crate::BitReader; #[doc = "Field `SIDE_PINDIR` writer - If 1, side-set data is asserted to pin directions, instead of pin values"] -pub type SIDE_PINDIR_W<'a, const O: u8> = crate::BitWriter<'a, SM_EXECCTRL_SPEC, O>; +pub type SIDE_PINDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIDE_EN` reader - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] pub type SIDE_EN_R = crate::BitReader; #[doc = "Field `SIDE_EN` writer - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] -pub type SIDE_EN_W<'a, const O: u8> = crate::BitWriter<'a, SM_EXECCTRL_SPEC, O>; +pub type SIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXEC_STALLED` reader - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."] pub type EXEC_STALLED_R = crate::BitReader; impl R { @@ -197,32 +168,32 @@ impl W { #[doc = "Bits 0:3 - Comparison level for the MOV x, STATUS instruction"] #[inline(always)] #[must_use] - pub fn status_n(&mut self) -> STATUS_N_W<0> { + pub fn status_n(&mut self) -> STATUS_N_W { STATUS_N_W::new(self) } #[doc = "Bit 4 - Comparison used for the MOV x, STATUS instruction."] #[inline(always)] #[must_use] - pub fn status_sel(&mut self) -> STATUS_SEL_W<4> { + pub fn status_sel(&mut self) -> STATUS_SEL_W { STATUS_SEL_W::new(self) } #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."] #[inline(always)] #[must_use] - pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<7> { + pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W { WRAP_BOTTOM_W::new(self) } #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] #[inline(always)] #[must_use] - pub fn wrap_top(&mut self) -> WRAP_TOP_W<12> { + pub fn wrap_top(&mut self) -> WRAP_TOP_W { WRAP_TOP_W::new(self) } #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"] #[inline(always)] #[must_use] - pub fn out_sticky(&mut self) -> OUT_STICKY_W<17> { + pub fn out_sticky(&mut self) -> OUT_STICKY_W { OUT_STICKY_W::new(self) } #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable @@ -231,56 +202,55 @@ impl W { due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] #[inline(always)] #[must_use] - pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<18> { + pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W { INLINE_OUT_EN_W::new(self) } #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"] #[inline(always)] #[must_use] - pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<19> { + pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W { OUT_EN_SEL_W::new(self) } #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] #[inline(always)] #[must_use] - pub fn jmp_pin(&mut self) -> JMP_PIN_W<24> { + pub fn jmp_pin(&mut self) -> JMP_PIN_W { JMP_PIN_W::new(self) } #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"] #[inline(always)] #[must_use] - pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<29> { + pub fn side_pindir(&mut self) -> SIDE_PINDIR_W { SIDE_PINDIR_W::new(self) } #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] #[inline(always)] #[must_use] - pub fn side_en(&mut self) -> SIDE_EN_W<30> { + pub fn side_en(&mut self) -> SIDE_EN_W { SIDE_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Execution/behavioural settings for state machine 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_execctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_execctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_execctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_EXECCTRL_SPEC; impl crate::RegisterSpec for SM_EXECCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_execctrl::R](R) reader structure"] -impl crate::Readable for SM_EXECCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sm_execctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`sm_execctrl::R`](R) reader structure"] +impl crate::Readable for SM_EXECCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_execctrl::W`](W) writer structure"] impl crate::Writable for SM_EXECCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs index 8366ffa56..dbc229523 100644 --- a/src/pio0/sm/sm_instr.rs +++ b/src/pio0/sm/sm_instr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SM_INSTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SM_INSTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SM0_INSTR` reader - "] pub type SM0_INSTR_R = crate::FieldReader; #[doc = "Field `SM0_INSTR` writer - "] -pub type SM0_INSTR_W<'a, const O: u8> = crate::FieldWriter<'a, SM_INSTR_SPEC, 16, O, u16>; +pub type SM0_INSTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -49,33 +17,32 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn sm0_instr(&mut self) -> SM0_INSTR_W<0> { + pub fn sm0_instr(&mut self) -> SM0_INSTR_W { SM0_INSTR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_instr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_INSTR_SPEC; impl crate::RegisterSpec for SM_INSTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_instr::R](R) reader structure"] -impl crate::Readable for SM_INSTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sm_instr::W](W) writer structure"] +#[doc = "`read()` method returns [`sm_instr::R`](R) reader structure"] +impl crate::Readable for SM_INSTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_instr::W`](W) writer structure"] impl crate::Writable for SM_INSTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/pio0/sm/sm_pinctrl.rs index aeecf169a..e411a199c 100644 --- a/src/pio0/sm/sm_pinctrl.rs +++ b/src/pio0/sm/sm_pinctrl.rs @@ -1,67 +1,35 @@ #[doc = "Register `SM_PINCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SM_PINCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OUT_BASE` reader - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] pub type OUT_BASE_R = crate::FieldReader; #[doc = "Field `OUT_BASE` writer - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] -pub type OUT_BASE_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 5, O>; +pub type OUT_BASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SET_BASE` reader - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] pub type SET_BASE_R = crate::FieldReader; #[doc = "Field `SET_BASE` writer - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] -pub type SET_BASE_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 5, O>; +pub type SET_BASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIDESET_BASE` reader - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] pub type SIDESET_BASE_R = crate::FieldReader; #[doc = "Field `SIDESET_BASE` writer - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] -pub type SIDESET_BASE_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 5, O>; +pub type SIDESET_BASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `IN_BASE` reader - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] pub type IN_BASE_R = crate::FieldReader; #[doc = "Field `IN_BASE` writer - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] -pub type IN_BASE_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 5, O>; +pub type IN_BASE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `OUT_COUNT` reader - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] pub type OUT_COUNT_R = crate::FieldReader; #[doc = "Field `OUT_COUNT` writer - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] -pub type OUT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 6, O>; +pub type OUT_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `SET_COUNT` reader - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] pub type SET_COUNT_R = crate::FieldReader; #[doc = "Field `SET_COUNT` writer - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] -pub type SET_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 3, O>; +pub type SET_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SIDESET_COUNT` reader - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] pub type SIDESET_COUNT_R = crate::FieldReader; #[doc = "Field `SIDESET_COUNT` writer - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] -pub type SIDESET_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, SM_PINCTRL_SPEC, 3, O>; +pub type SIDESET_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] #[inline(always)] @@ -103,68 +71,67 @@ impl W { #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] #[inline(always)] #[must_use] - pub fn out_base(&mut self) -> OUT_BASE_W<0> { + pub fn out_base(&mut self) -> OUT_BASE_W { OUT_BASE_W::new(self) } #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] #[inline(always)] #[must_use] - pub fn set_base(&mut self) -> SET_BASE_W<5> { + pub fn set_base(&mut self) -> SET_BASE_W { SET_BASE_W::new(self) } #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] #[inline(always)] #[must_use] - pub fn sideset_base(&mut self) -> SIDESET_BASE_W<10> { + pub fn sideset_base(&mut self) -> SIDESET_BASE_W { SIDESET_BASE_W::new(self) } #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] #[inline(always)] #[must_use] - pub fn in_base(&mut self) -> IN_BASE_W<15> { + pub fn in_base(&mut self) -> IN_BASE_W { IN_BASE_W::new(self) } #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] #[inline(always)] #[must_use] - pub fn out_count(&mut self) -> OUT_COUNT_W<20> { + pub fn out_count(&mut self) -> OUT_COUNT_W { OUT_COUNT_W::new(self) } #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] #[inline(always)] #[must_use] - pub fn set_count(&mut self) -> SET_COUNT_W<26> { + pub fn set_count(&mut self) -> SET_COUNT_W { SET_COUNT_W::new(self) } #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] #[inline(always)] #[must_use] - pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<29> { + pub fn sideset_count(&mut self) -> SIDESET_COUNT_W { SIDESET_COUNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "State machine pin control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_pinctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_pinctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_pinctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_PINCTRL_SPEC; impl crate::RegisterSpec for SM_PINCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_pinctrl::R](R) reader structure"] -impl crate::Readable for SM_PINCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sm_pinctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`sm_pinctrl::R`](R) reader structure"] +impl crate::Readable for SM_PINCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_pinctrl::W`](W) writer structure"] impl crate::Writable for SM_PINCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs index 7a53f695c..bd8944dd4 100644 --- a/src/pio0/sm/sm_shiftctrl.rs +++ b/src/pio0/sm/sm_shiftctrl.rs @@ -1,67 +1,35 @@ #[doc = "Register `SM_SHIFTCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SM_SHIFTCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AUTOPUSH` reader - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] pub type AUTOPUSH_R = crate::BitReader; #[doc = "Field `AUTOPUSH` writer - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] -pub type AUTOPUSH_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type AUTOPUSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AUTOPULL` reader - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] pub type AUTOPULL_R = crate::BitReader; #[doc = "Field `AUTOPULL` writer - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] -pub type AUTOPULL_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type AUTOPULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IN_SHIFTDIR` reader - 1 = shift input shift register to right (data enters from left). 0 = to left."] pub type IN_SHIFTDIR_R = crate::BitReader; #[doc = "Field `IN_SHIFTDIR` writer - 1 = shift input shift register to right (data enters from left). 0 = to left."] -pub type IN_SHIFTDIR_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type IN_SHIFTDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_SHIFTDIR` reader - 1 = shift out of output shift register to right. 0 = to left."] pub type OUT_SHIFTDIR_R = crate::BitReader; #[doc = "Field `OUT_SHIFTDIR` writer - 1 = shift out of output shift register to right. 0 = to left."] -pub type OUT_SHIFTDIR_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type OUT_SHIFTDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PUSH_THRESH` reader - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] pub type PUSH_THRESH_R = crate::FieldReader; #[doc = "Field `PUSH_THRESH` writer - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] -pub type PUSH_THRESH_W<'a, const O: u8> = crate::FieldWriter<'a, SM_SHIFTCTRL_SPEC, 5, O>; +pub type PUSH_THRESH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `PULL_THRESH` reader - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] pub type PULL_THRESH_R = crate::FieldReader; #[doc = "Field `PULL_THRESH` writer - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] -pub type PULL_THRESH_W<'a, const O: u8> = crate::FieldWriter<'a, SM_SHIFTCTRL_SPEC, 5, O>; +pub type PULL_THRESH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `FJOIN_TX` reader - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] @@ -69,7 +37,7 @@ pub type FJOIN_TX_R = crate::BitReader; #[doc = "Field `FJOIN_TX` writer - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] -pub type FJOIN_TX_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type FJOIN_TX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FJOIN_RX` reader - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] @@ -77,7 +45,7 @@ pub type FJOIN_RX_R = crate::BitReader; #[doc = "Field `FJOIN_RX` writer - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] -pub type FJOIN_RX_W<'a, const O: u8> = crate::BitWriter<'a, SM_SHIFTCTRL_SPEC, O>; +pub type FJOIN_RX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] #[inline(always)] @@ -130,39 +98,39 @@ impl W { #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] #[inline(always)] #[must_use] - pub fn autopush(&mut self) -> AUTOPUSH_W<16> { + pub fn autopush(&mut self) -> AUTOPUSH_W { AUTOPUSH_W::new(self) } #[doc = "Bit 17 - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] #[inline(always)] #[must_use] - pub fn autopull(&mut self) -> AUTOPULL_W<17> { + pub fn autopull(&mut self) -> AUTOPULL_W { AUTOPULL_W::new(self) } #[doc = "Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left."] #[inline(always)] #[must_use] - pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<18> { + pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W { IN_SHIFTDIR_W::new(self) } #[doc = "Bit 19 - 1 = shift out of output shift register to right. 0 = to left."] #[inline(always)] #[must_use] - pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<19> { + pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W { OUT_SHIFTDIR_W::new(self) } #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] #[inline(always)] #[must_use] - pub fn push_thresh(&mut self) -> PUSH_THRESH_W<20> { + pub fn push_thresh(&mut self) -> PUSH_THRESH_W { PUSH_THRESH_W::new(self) } #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] #[inline(always)] #[must_use] - pub fn pull_thresh(&mut self) -> PULL_THRESH_W<25> { + pub fn pull_thresh(&mut self) -> PULL_THRESH_W { PULL_THRESH_W::new(self) } #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. @@ -170,7 +138,7 @@ impl W { FIFOs are flushed when this bit is changed."] #[inline(always)] #[must_use] - pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<30> { + pub fn fjoin_tx(&mut self) -> FJOIN_TX_W { FJOIN_TX_W::new(self) } #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. @@ -178,32 +146,31 @@ impl W { FIFOs are flushed when this bit is changed."] #[inline(always)] #[must_use] - pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<31> { + pub fn fjoin_rx(&mut self) -> FJOIN_RX_W { FJOIN_RX_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control behaviour of the input/output shift registers for state machine 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sm_shiftctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_shiftctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_shiftctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_SHIFTCTRL_SPEC; impl crate::RegisterSpec for SM_SHIFTCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sm_shiftctrl::R](R) reader structure"] -impl crate::Readable for SM_SHIFTCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sm_shiftctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`sm_shiftctrl::R`](R) reader structure"] +impl crate::Readable for SM_SHIFTCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_shiftctrl::W`](W) writer structure"] impl crate::Writable for SM_SHIFTCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm_irq.rs b/src/pio0/sm_irq.rs index 70d512548..c1001bd8a 100644 --- a/src/pio0/sm_irq.rs +++ b/src/pio0/sm_irq.rs @@ -8,15 +8,30 @@ pub struct SM_IRQ { #[doc = "0x08 - Interrupt status after masking & forcing for irq0"] pub irq_ints: IRQ_INTS, } -#[doc = "IRQ_INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ_INTE (rw) register accessor: Interrupt Enable for irq0 + +You can [`read`](crate::generic::Reg::read) this register and get [`irq_inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_inte`] +module"] pub type IRQ_INTE = crate::Reg; #[doc = "Interrupt Enable for irq0"] pub mod irq_inte; -#[doc = "IRQ_INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ_INTF (rw) register accessor: Interrupt Force for irq0 + +You can [`read`](crate::generic::Reg::read) this register and get [`irq_intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_intf`] +module"] pub type IRQ_INTF = crate::Reg; #[doc = "Interrupt Force for irq0"] pub mod irq_intf; -#[doc = "IRQ_INTS (r) register accessor: an alias for `Reg`"] +#[doc = "IRQ_INTS (r) register accessor: Interrupt status after masking & forcing for irq0 + +You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_ints`] +module"] pub type IRQ_INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing for irq0"] pub mod irq_ints; diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/pio0/sm_irq/irq_inte.rs index dfbbefa2a..9f06fbdae 100644 --- a/src/pio0/sm_irq/irq_inte.rs +++ b/src/pio0/sm_irq/irq_inte.rs @@ -1,87 +1,55 @@ #[doc = "Register `IRQ_INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ_INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM0_RXNEMPTY` writer - "] -pub type SM0_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM0_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1_RXNEMPTY` reader - "] pub type SM1_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` writer - "] -pub type SM1_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM1_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2_RXNEMPTY` reader - "] pub type SM2_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM2_RXNEMPTY` writer - "] -pub type SM2_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM2_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3_RXNEMPTY` reader - "] pub type SM3_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM3_RXNEMPTY` writer - "] -pub type SM3_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM3_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM0_TXNFULL` reader - "] pub type SM0_TXNFULL_R = crate::BitReader; #[doc = "Field `SM0_TXNFULL` writer - "] -pub type SM0_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM0_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1_TXNFULL` reader - "] pub type SM1_TXNFULL_R = crate::BitReader; #[doc = "Field `SM1_TXNFULL` writer - "] -pub type SM1_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM1_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2_TXNFULL` reader - "] pub type SM2_TXNFULL_R = crate::BitReader; #[doc = "Field `SM2_TXNFULL` writer - "] -pub type SM2_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM2_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3_TXNFULL` reader - "] pub type SM3_TXNFULL_R = crate::BitReader; #[doc = "Field `SM3_TXNFULL` writer - "] -pub type SM3_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM3_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM0` reader - "] pub type SM0_R = crate::BitReader; #[doc = "Field `SM0` writer - "] -pub type SM0_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1` reader - "] pub type SM1_R = crate::BitReader; #[doc = "Field `SM1` writer - "] -pub type SM1_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2` reader - "] pub type SM2_R = crate::BitReader; #[doc = "Field `SM2` writer - "] -pub type SM2_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3` reader - "] pub type SM3_R = crate::BitReader; #[doc = "Field `SM3` writer - "] -pub type SM3_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTE_SPEC, O>; +pub type SM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -148,98 +116,97 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<0> { + pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W { SM0_RXNEMPTY_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<1> { + pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W { SM1_RXNEMPTY_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<2> { + pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W { SM2_RXNEMPTY_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<3> { + pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W { SM3_RXNEMPTY_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<4> { + pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W { SM0_TXNFULL_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<5> { + pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W { SM1_TXNFULL_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<6> { + pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W { SM2_TXNFULL_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<7> { + pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W { SM3_TXNFULL_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn sm0(&mut self) -> SM0_W<8> { + pub fn sm0(&mut self) -> SM0_W { SM0_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn sm1(&mut self) -> SM1_W<9> { + pub fn sm1(&mut self) -> SM1_W { SM1_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn sm2(&mut self) -> SM2_W<10> { + pub fn sm2(&mut self) -> SM2_W { SM2_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn sm3(&mut self) -> SM3_W<11> { + pub fn sm3(&mut self) -> SM3_W { SM3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable for irq0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_INTE_SPEC; impl crate::RegisterSpec for IRQ_INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq_inte::R](R) reader structure"] -impl crate::Readable for IRQ_INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq_inte::W](W) writer structure"] +#[doc = "`read()` method returns [`irq_inte::R`](R) reader structure"] +impl crate::Readable for IRQ_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_inte::W`](W) writer structure"] impl crate::Writable for IRQ_INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/pio0/sm_irq/irq_intf.rs index eea0df0e0..c98ff267c 100644 --- a/src/pio0/sm_irq/irq_intf.rs +++ b/src/pio0/sm_irq/irq_intf.rs @@ -1,87 +1,55 @@ #[doc = "Register `IRQ_INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ_INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM0_RXNEMPTY` writer - "] -pub type SM0_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM0_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1_RXNEMPTY` reader - "] pub type SM1_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` writer - "] -pub type SM1_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM1_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2_RXNEMPTY` reader - "] pub type SM2_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM2_RXNEMPTY` writer - "] -pub type SM2_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM2_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3_RXNEMPTY` reader - "] pub type SM3_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM3_RXNEMPTY` writer - "] -pub type SM3_RXNEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM3_RXNEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM0_TXNFULL` reader - "] pub type SM0_TXNFULL_R = crate::BitReader; #[doc = "Field `SM0_TXNFULL` writer - "] -pub type SM0_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM0_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1_TXNFULL` reader - "] pub type SM1_TXNFULL_R = crate::BitReader; #[doc = "Field `SM1_TXNFULL` writer - "] -pub type SM1_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM1_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2_TXNFULL` reader - "] pub type SM2_TXNFULL_R = crate::BitReader; #[doc = "Field `SM2_TXNFULL` writer - "] -pub type SM2_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM2_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3_TXNFULL` reader - "] pub type SM3_TXNFULL_R = crate::BitReader; #[doc = "Field `SM3_TXNFULL` writer - "] -pub type SM3_TXNFULL_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM3_TXNFULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM0` reader - "] pub type SM0_R = crate::BitReader; #[doc = "Field `SM0` writer - "] -pub type SM0_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM1` reader - "] pub type SM1_R = crate::BitReader; #[doc = "Field `SM1` writer - "] -pub type SM1_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM2` reader - "] pub type SM2_R = crate::BitReader; #[doc = "Field `SM2` writer - "] -pub type SM2_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SM3` reader - "] pub type SM3_R = crate::BitReader; #[doc = "Field `SM3` writer - "] -pub type SM3_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_INTF_SPEC, O>; +pub type SM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -148,98 +116,97 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<0> { + pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W { SM0_RXNEMPTY_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<1> { + pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W { SM1_RXNEMPTY_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<2> { + pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W { SM2_RXNEMPTY_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<3> { + pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W { SM3_RXNEMPTY_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<4> { + pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W { SM0_TXNFULL_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<5> { + pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W { SM1_TXNFULL_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<6> { + pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W { SM2_TXNFULL_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<7> { + pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W { SM3_TXNFULL_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn sm0(&mut self) -> SM0_W<8> { + pub fn sm0(&mut self) -> SM0_W { SM0_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn sm1(&mut self) -> SM1_W<9> { + pub fn sm1(&mut self) -> SM1_W { SM1_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn sm2(&mut self) -> SM2_W<10> { + pub fn sm2(&mut self) -> SM2_W { SM2_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn sm3(&mut self) -> SM3_W<11> { + pub fn sm3(&mut self) -> SM3_W { SM3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force for irq0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_INTF_SPEC; impl crate::RegisterSpec for IRQ_INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq_intf::R](R) reader structure"] -impl crate::Readable for IRQ_INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq_intf::W](W) writer structure"] +#[doc = "`read()` method returns [`irq_intf::R`](R) reader structure"] +impl crate::Readable for IRQ_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_intf::W`](W) writer structure"] impl crate::Writable for IRQ_INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/pio0/sm_irq/irq_ints.rs index 15fb9a11b..cb89033a4 100644 --- a/src/pio0/sm_irq/irq_ints.rs +++ b/src/pio0/sm_irq/irq_ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `IRQ_INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` reader - "] @@ -101,17 +88,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing for irq0 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_INTS_SPEC; impl crate::RegisterSpec for IRQ_INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq_ints::R](R) reader structure"] -impl crate::Readable for IRQ_INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`irq_ints::R`](R) reader structure"] +impl crate::Readable for IRQ_INTS_SPEC {} #[doc = "`reset()` method sets IRQ_INTS to value 0"] impl crate::Resettable for IRQ_INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/pio0/txf.rs b/src/pio0/txf.rs index 57f89f343..e7e868d63 100644 --- a/src/pio0/txf.rs +++ b/src/pio0/txf.rs @@ -1,49 +1,31 @@ #[doc = "Register `TXF%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [txf](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXF_SPEC; impl crate::RegisterSpec for TXF_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [txf::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`txf::W`](W) writer structure"] impl crate::Writable for TXF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pll_sys.rs b/src/pll_sys.rs index 275062c5d..00537982a 100644 --- a/src/pll_sys.rs +++ b/src/pll_sys.rs @@ -17,7 +17,16 @@ pub struct RegisterBlock { the primary output is driven from VCO divided by postdiv1*postdiv2"] pub prim: PRIM, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + +You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control and Status GENERAL CONSTRAINTS: @@ -25,16 +34,34 @@ pub type CS = crate::Reg; Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] pub mod cs; -#[doc = "PWR (rw) register accessor: an alias for `Reg`"] +#[doc = "PWR (rw) register accessor: Controls the PLL power modes. + +You can [`read`](crate::generic::Reg::read) this register and get [`pwr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwr`] +module"] pub type PWR = crate::Reg; #[doc = "Controls the PLL power modes."] pub mod pwr; -#[doc = "FBDIV_INT (rw) register accessor: an alias for `Reg`"] +#[doc = "FBDIV_INT (rw) register accessor: Feedback divisor + (note: this PLL does not support fractional division) + +You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fbdiv_int`] +module"] pub type FBDIV_INT = crate::Reg; #[doc = "Feedback divisor (note: this PLL does not support fractional division)"] pub mod fbdiv_int; -#[doc = "PRIM (rw) register accessor: an alias for `Reg`"] +#[doc = "PRIM (rw) register accessor: Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + +You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@prim`] +module"] pub type PRIM = crate::Reg; #[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs index 4f387bb70..6b2fbf8ec 100644 --- a/src/pll_sys/cs.rs +++ b/src/pll_sys/cs.rs @@ -1,39 +1,7 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REFDIV` reader - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] @@ -41,11 +9,11 @@ pub type REFDIV_R = crate::FieldReader; #[doc = "Field `REFDIV` writer - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] -pub type REFDIV_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 6, O>; +pub type REFDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `BYPASS` reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] pub type BYPASS_R = crate::BitReader; #[doc = "Field `BYPASS` writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] -pub type BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>; +pub type BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK` reader - PLL is locked"] pub type LOCK_R = crate::BitReader; impl R { @@ -73,19 +41,23 @@ impl W { PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] #[inline(always)] #[must_use] - pub fn refdiv(&mut self) -> REFDIV_W<0> { + pub fn refdiv(&mut self) -> REFDIV_W { REFDIV_W::new(self) } #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] #[inline(always)] #[must_use] - pub fn bypass(&mut self) -> BYPASS_W<8> { + pub fn bypass(&mut self) -> BYPASS_W { BYPASS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -95,20 +67,15 @@ impl W { Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [cs](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs index e7d59deea..6f5f69ad0 100644 --- a/src/pll_sys/fbdiv_int.rs +++ b/src/pll_sys/fbdiv_int.rs @@ -1,43 +1,11 @@ #[doc = "Register `FBDIV_INT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FBDIV_INT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FBDIV_INT` reader - see ctrl reg description for constraints"] pub type FBDIV_INT_R = crate::FieldReader; #[doc = "Field `FBDIV_INT` writer - see ctrl reg description for constraints"] -pub type FBDIV_INT_W<'a, const O: u8> = crate::FieldWriter<'a, FBDIV_INT_SPEC, 12, O, u16>; +pub type FBDIV_INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - see ctrl reg description for constraints"] #[inline(always)] @@ -49,33 +17,32 @@ impl W { #[doc = "Bits 0:11 - see ctrl reg description for constraints"] #[inline(always)] #[must_use] - pub fn fbdiv_int(&mut self) -> FBDIV_INT_W<0> { + pub fn fbdiv_int(&mut self) -> FBDIV_INT_W { FBDIV_INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Feedback divisor (note: this PLL does not support fractional division) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fbdiv_int](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FBDIV_INT_SPEC; impl crate::RegisterSpec for FBDIV_INT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fbdiv_int::R](R) reader structure"] -impl crate::Readable for FBDIV_INT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fbdiv_int::W](W) writer structure"] +#[doc = "`read()` method returns [`fbdiv_int::R`](R) reader structure"] +impl crate::Readable for FBDIV_INT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fbdiv_int::W`](W) writer structure"] impl crate::Writable for FBDIV_INT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs index 3c0134596..a56216a93 100644 --- a/src/pll_sys/prim.rs +++ b/src/pll_sys/prim.rs @@ -1,47 +1,15 @@ #[doc = "Register `PRIM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PRIM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `POSTDIV2` reader - divide by 1-7"] pub type POSTDIV2_R = crate::FieldReader; #[doc = "Field `POSTDIV2` writer - divide by 1-7"] -pub type POSTDIV2_W<'a, const O: u8> = crate::FieldWriter<'a, PRIM_SPEC, 3, O>; +pub type POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `POSTDIV1` reader - divide by 1-7"] pub type POSTDIV1_R = crate::FieldReader; #[doc = "Field `POSTDIV1` writer - divide by 1-7"] -pub type POSTDIV1_W<'a, const O: u8> = crate::FieldWriter<'a, PRIM_SPEC, 3, O>; +pub type POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 12:14 - divide by 1-7"] #[inline(always)] @@ -58,19 +26,23 @@ impl W { #[doc = "Bits 12:14 - divide by 1-7"] #[inline(always)] #[must_use] - pub fn postdiv2(&mut self) -> POSTDIV2_W<12> { + pub fn postdiv2(&mut self) -> POSTDIV2_W { POSTDIV2_W::new(self) } #[doc = "Bits 16:18 - divide by 1-7"] #[inline(always)] #[must_use] - pub fn postdiv1(&mut self) -> POSTDIV1_W<16> { + pub fn postdiv1(&mut self) -> POSTDIV1_W { POSTDIV1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -78,20 +50,15 @@ impl W { (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [prim](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PRIM_SPEC; impl crate::RegisterSpec for PRIM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [prim::R](R) reader structure"] -impl crate::Readable for PRIM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [prim::W](W) writer structure"] +#[doc = "`read()` method returns [`prim::R`](R) reader structure"] +impl crate::Readable for PRIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`prim::W`](W) writer structure"] impl crate::Writable for PRIM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs index af24a09f7..16edfadf8 100644 --- a/src/pll_sys/pwr.rs +++ b/src/pll_sys/pwr.rs @@ -1,63 +1,31 @@ #[doc = "Register `PWR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PD` reader - PLL powerdown To save power set high when PLL output not required."] pub type PD_R = crate::BitReader; #[doc = "Field `PD` writer - PLL powerdown To save power set high when PLL output not required."] -pub type PD_W<'a, const O: u8> = crate::BitWriter<'a, PWR_SPEC, O>; +pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSMPD` reader - PLL DSM powerdown Nothing is achieved by setting this low."] pub type DSMPD_R = crate::BitReader; #[doc = "Field `DSMPD` writer - PLL DSM powerdown Nothing is achieved by setting this low."] -pub type DSMPD_W<'a, const O: u8> = crate::BitWriter<'a, PWR_SPEC, O>; +pub type DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POSTDIVPD` reader - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] pub type POSTDIVPD_R = crate::BitReader; #[doc = "Field `POSTDIVPD` writer - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] -pub type POSTDIVPD_W<'a, const O: u8> = crate::BitWriter<'a, PWR_SPEC, O>; +pub type POSTDIVPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VCOPD` reader - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] pub type VCOPD_R = crate::BitReader; #[doc = "Field `VCOPD` writer - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] -pub type VCOPD_W<'a, const O: u8> = crate::BitWriter<'a, PWR_SPEC, O>; +pub type VCOPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] @@ -89,53 +57,52 @@ impl W { To save power set high when PLL output not required."] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W<0> { + pub fn pd(&mut self) -> PD_W { PD_W::new(self) } #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] #[inline(always)] #[must_use] - pub fn dsmpd(&mut self) -> DSMPD_W<2> { + pub fn dsmpd(&mut self) -> DSMPD_W { DSMPD_W::new(self) } #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] #[must_use] - pub fn postdivpd(&mut self) -> POSTDIVPD_W<3> { + pub fn postdivpd(&mut self) -> POSTDIVPD_W { POSTDIVPD_W::new(self) } #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] #[must_use] - pub fn vcopd(&mut self) -> VCOPD_W<5> { + pub fn vcopd(&mut self) -> VCOPD_W { VCOPD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Controls the PLL power modes. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [pwr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`pwr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PWR_SPEC; impl crate::RegisterSpec for PWR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pwr::R](R) reader structure"] -impl crate::Readable for PWR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pwr::W](W) writer structure"] +#[doc = "`read()` method returns [`pwr::R`](R) reader structure"] +impl crate::Readable for PWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwr::W`](W) writer structure"] impl crate::Writable for PWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb.rs b/src/ppb.rs index bdf980087..2a8fe21dd 100644 --- a/src/ppb.rs +++ b/src/ppb.rs @@ -75,127 +75,281 @@ pub struct RegisterBlock { #[doc = "0xeda0 - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region."] pub mpu_rasr: MPU_RASR, } -#[doc = "SYST_CSR (rw) register accessor: an alias for `Reg`"] +#[doc = "SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features. + +You can [`read`](crate::generic::Reg::read) this register and get [`syst_csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_csr`] +module"] pub type SYST_CSR = crate::Reg; #[doc = "Use the SysTick Control and Status Register to enable the SysTick features."] pub mod syst_csr; -#[doc = "SYST_RVR (rw) register accessor: an alias for `Reg`"] +#[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + +You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_rvr`] +module"] pub type SYST_RVR = crate::Reg; #[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] pub mod syst_rvr; -#[doc = "SYST_CVR (rw) register accessor: an alias for `Reg`"] +#[doc = "SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + +You can [`read`](crate::generic::Reg::read) this register and get [`syst_cvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_cvr`] +module"] pub type SYST_CVR = crate::Reg; #[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."] pub mod syst_cvr; -#[doc = "SYST_CALIB (r) register accessor: an alias for `Reg`"] +#[doc = "SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + +You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_calib`] +module"] pub type SYST_CALIB = crate::Reg; #[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."] pub mod syst_calib; -#[doc = "NVIC_ISER (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. + If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_iser`] +module"] pub type NVIC_ISER = crate::Reg; #[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."] pub mod nvic_iser; -#[doc = "NVIC_ICER (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_ICER (rw) register accessor: Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icer`] +module"] pub type NVIC_ICER = crate::Reg; #[doc = "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled."] pub mod nvic_icer; -#[doc = "NVIC_ISPR (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_ISPR (rw) register accessor: The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ispr`] +module"] pub type NVIC_ISPR = crate::Reg; #[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending."] pub mod nvic_ispr; -#[doc = "NVIC_ICPR (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_ICPR (rw) register accessor: Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icpr`] +module"] pub type NVIC_ICPR = crate::Reg; #[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending."] pub mod nvic_icpr; -#[doc = "NVIC_IPR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR0 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. + These registers are only word-accessible + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr0`] +module"] pub type NVIC_IPR0 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible"] pub mod nvic_ipr0; -#[doc = "NVIC_IPR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr1`] +module"] pub type NVIC_IPR1 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr1; -#[doc = "NVIC_IPR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR2 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr2`] +module"] pub type NVIC_IPR2 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr2; -#[doc = "NVIC_IPR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR3 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr3`] +module"] pub type NVIC_IPR3 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr3; -#[doc = "NVIC_IPR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR4 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr4`] +module"] pub type NVIC_IPR4 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr4; -#[doc = "NVIC_IPR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR5 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr5`] +module"] pub type NVIC_IPR5 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr5; -#[doc = "NVIC_IPR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR6 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr6`] +module"] pub type NVIC_IPR6 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr6; -#[doc = "NVIC_IPR7 (rw) register accessor: an alias for `Reg`"] +#[doc = "NVIC_IPR7 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr7`] +module"] pub type NVIC_IPR7 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr7; -#[doc = "CPUID (r) register accessor: an alias for `Reg`"] +#[doc = "CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. + +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cpuid`] +module"] pub type CPUID = crate::Reg; #[doc = "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core."] pub mod cpuid; -#[doc = "ICSR (rw) register accessor: an alias for `Reg`"] +#[doc = "ICSR (rw) register accessor: Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. + +You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@icsr`] +module"] pub type ICSR = crate::Reg; #[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception."] pub mod icsr; -#[doc = "VTOR (rw) register accessor: an alias for `Reg`"] +#[doc = "VTOR (rw) register accessor: The VTOR holds the vector table offset address. + +You can [`read`](crate::generic::Reg::read) this register and get [`vtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vtor`] +module"] pub type VTOR = crate::Reg; #[doc = "The VTOR holds the vector table offset address."] pub mod vtor; -#[doc = "AIRCR (rw) register accessor: an alias for `Reg`"] +#[doc = "AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + +You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@aircr`] +module"] pub type AIRCR = crate::Reg; #[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."] pub mod aircr; -#[doc = "SCR (rw) register accessor: an alias for `Reg`"] +#[doc = "SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + +You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scr`] +module"] pub type SCR = crate::Reg; #[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."] pub mod scr; -#[doc = "CCR (r) register accessor: an alias for `Reg`"] +#[doc = "CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. + +You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ccr`] +module"] pub type CCR = crate::Reg; #[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault."] pub mod ccr; -#[doc = "SHPR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "SHPR2 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. + +You can [`read`](crate::generic::Reg::read) this register and get [`shpr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shpr2`] +module"] pub type SHPR2 = crate::Reg; #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall."] pub mod shpr2; -#[doc = "SHPR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "SHPR3 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. + +You can [`read`](crate::generic::Reg::read) this register and get [`shpr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shpr3`] +module"] pub type SHPR3 = crate::Reg; #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick."] pub mod shpr3; -#[doc = "SHCSR (rw) register accessor: an alias for `Reg`"] +#[doc = "SHCSR (rw) register accessor: Use the System Handler Control and State Register to determine or clear the pending status of SVCall. + +You can [`read`](crate::generic::Reg::read) this register and get [`shcsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shcsr`] +module"] pub type SHCSR = crate::Reg; #[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall."] pub mod shcsr; -#[doc = "MPU_TYPE (r) register accessor: an alias for `Reg`"] +#[doc = "MPU_TYPE (r) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. + +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_type`] +module"] pub type MPU_TYPE = crate::Reg; #[doc = "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports."] pub mod mpu_type; -#[doc = "MPU_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "MPU_CTRL (rw) register accessor: Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. + +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_ctrl`] +module"] pub type MPU_CTRL = crate::Reg; #[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs."] pub mod mpu_ctrl; -#[doc = "MPU_RNR (rw) register accessor: an alias for `Reg`"] +#[doc = "MPU_RNR (rw) register accessor: Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. + +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rnr`] +module"] pub type MPU_RNR = crate::Reg; #[doc = "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR."] pub mod mpu_rnr; -#[doc = "MPU_RBAR (rw) register accessor: an alias for `Reg`"] +#[doc = "MPU_RBAR (rw) register accessor: Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. + +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rbar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rbar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rbar`] +module"] pub type MPU_RBAR = crate::Reg; #[doc = "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated."] pub mod mpu_rbar; -#[doc = "MPU_RASR (rw) register accessor: an alias for `Reg`"] +#[doc = "MPU_RASR (rw) register accessor: Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. + +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rasr`] +module"] pub type MPU_RASR = crate::Reg; #[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region."] pub mod mpu_rasr; diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs index 5e91f1879..ba4baad8c 100644 --- a/src/ppb/aircr.rs +++ b/src/ppb/aircr.rs @@ -1,47 +1,15 @@ #[doc = "Register `AIRCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `AIRCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VECTCLRACTIVE` reader - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] pub type VECTCLRACTIVE_R = crate::BitReader; #[doc = "Field `VECTCLRACTIVE` writer - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] -pub type VECTCLRACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, AIRCR_SPEC, O>; +pub type VECTCLRACTIVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYSRESETREQ` reader - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] pub type SYSRESETREQ_R = crate::BitReader; #[doc = "Field `SYSRESETREQ` writer - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] -pub type SYSRESETREQ_W<'a, const O: u8> = crate::BitWriter<'a, AIRCR_SPEC, O>; +pub type SYSRESETREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDIANESS` reader - Data endianness implemented: 0 = Little-endian."] pub type ENDIANESS_R = crate::BitReader; @@ -52,7 +20,7 @@ pub type VECTKEY_R = crate::FieldReader; #[doc = "Field `VECTKEY` writer - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] -pub type VECTKEY_W<'a, const O: u8> = crate::FieldWriter<'a, AIRCR_SPEC, 16, O, u16>; +pub type VECTKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] #[inline(always)] @@ -82,13 +50,13 @@ impl W { #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] #[inline(always)] #[must_use] - pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<1> { + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { VECTCLRACTIVE_W::new(self) } #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] #[inline(always)] #[must_use] - pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<2> { + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { SYSRESETREQ_W::new(self) } #[doc = "Bits 16:31 - Register key: @@ -96,32 +64,31 @@ impl W { On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] #[inline(always)] #[must_use] - pub fn vectkey(&mut self) -> VECTKEY_W<16> { + pub fn vectkey(&mut self) -> VECTKEY_W { VECTKEY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [aircr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AIRCR_SPEC; impl crate::RegisterSpec for AIRCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [aircr::R](R) reader structure"] -impl crate::Readable for AIRCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +#[doc = "`read()` method returns [`aircr::R`](R) reader structure"] +impl crate::Readable for AIRCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aircr::W`](W) writer structure"] impl crate::Writable for AIRCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/ccr.rs b/src/ppb/ccr.rs index f9a8d33b2..d77b687ad 100644 --- a/src/ppb/ccr.rs +++ b/src/ppb/ccr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UNALIGN_TRP` reader - Always reads as one, indicates that all unaligned accesses generate a HardFault."] pub type UNALIGN_TRP_R = crate::BitReader; #[doc = "Field `STKALIGN` reader - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit\\[9\\] @@ -33,17 +20,13 @@ of the stacked PSR to indicate the stack alignment. On return from the exception } #[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ccr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccr::R](R) reader structure"] -impl crate::Readable for CCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CCR_SPEC {} #[doc = "`reset()` method sets CCR to value 0"] impl crate::Resettable for CCR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/ppb/cpuid.rs b/src/ppb/cpuid.rs index 3413cd1cc..409c1fde3 100644 --- a/src/ppb/cpuid.rs +++ b/src/ppb/cpuid.rs @@ -1,18 +1,5 @@ #[doc = "Register `CPUID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `REVISION` reader - Minor revision number m in the rnpm revision status: 0x1 = Patch 1."] pub type REVISION_R = crate::FieldReader; @@ -58,17 +45,13 @@ impl R { } #[doc = "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [cpuid](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPUID_SPEC; impl crate::RegisterSpec for CPUID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cpuid::R](R) reader structure"] -impl crate::Readable for CPUID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] +impl crate::Readable for CPUID_SPEC {} #[doc = "`reset()` method sets CPUID to value 0x410c_c601"] impl crate::Resettable for CPUID_SPEC { const RESET_VALUE: Self::Ux = 0x410c_c601; diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs index 40929550a..7a0529449 100644 --- a/src/ppb/icsr.rs +++ b/src/ppb/icsr.rs @@ -1,39 +1,7 @@ #[doc = "Register `ICSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ICSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VECTACTIVE` reader - Active exception number field. Reset clears the VECTACTIVE field."] pub type VECTACTIVE_R = crate::FieldReader; #[doc = "Field `VECTPENDING` reader - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier."] @@ -53,7 +21,7 @@ pub type PENDSTCLR_R = crate::BitReader; 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] -pub type PENDSTCLR_W<'a, const O: u8> = crate::BitWriter<'a, ICSR_SPEC, O>; +pub type PENDSTCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit. Write: 0 = No effect. @@ -69,7 +37,7 @@ pub type PENDSTSET_R = crate::BitReader; Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] -pub type PENDSTSET_W<'a, const O: u8> = crate::BitWriter<'a, ICSR_SPEC, O>; +pub type PENDSTSET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit. Write: 0 = No effect. @@ -79,7 +47,7 @@ pub type PENDSVCLR_R = crate::BitReader; Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] -pub type PENDSVCLR_W<'a, const O: u8> = crate::BitWriter<'a, ICSR_SPEC, O>; +pub type PENDSVCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENDSVSET` reader - PendSV set-pending bit. Write: 0 = No effect. @@ -97,7 +65,7 @@ pub type PENDSVSET_R = crate::BitReader; 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] -pub type PENDSVSET_W<'a, const O: u8> = crate::BitWriter<'a, ICSR_SPEC, O>; +pub type PENDSVSET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NMIPENDSET` reader - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: @@ -123,7 +91,7 @@ pub type NMIPENDSET_R = crate::BitReader; exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] -pub type NMIPENDSET_W<'a, const O: u8> = crate::BitWriter<'a, ICSR_SPEC, O>; +pub type NMIPENDSET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:8 - Active exception number field. Reset clears the VECTACTIVE field."] #[inline(always)] @@ -210,7 +178,7 @@ impl W { This bit is WO. On a register read its value is Unknown."] #[inline(always)] #[must_use] - pub fn pendstclr(&mut self) -> PENDSTCLR_W<25> { + pub fn pendstclr(&mut self) -> PENDSTCLR_W { PENDSTCLR_W::new(self) } #[doc = "Bit 26 - SysTick exception set-pending bit. @@ -222,7 +190,7 @@ impl W { 1 = SysTick exception is pending."] #[inline(always)] #[must_use] - pub fn pendstset(&mut self) -> PENDSTSET_W<26> { + pub fn pendstset(&mut self) -> PENDSTSET_W { PENDSTSET_W::new(self) } #[doc = "Bit 27 - PendSV clear-pending bit. @@ -231,7 +199,7 @@ impl W { 1 = Removes the pending state from the PendSV exception."] #[inline(always)] #[must_use] - pub fn pendsvclr(&mut self) -> PENDSVCLR_W<27> { + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { PENDSVCLR_W::new(self) } #[doc = "Bit 28 - PendSV set-pending bit. @@ -244,7 +212,7 @@ impl W { Writing 1 to this bit is the only way to set the PendSV exception state to pending."] #[inline(always)] #[must_use] - pub fn pendsvset(&mut self) -> PENDSVSET_W<28> { + pub fn pendsvset(&mut self) -> PENDSVSET_W { PENDSVSET_W::new(self) } #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. @@ -261,32 +229,31 @@ impl W { NMI signal is reasserted while the processor is executing that handler."] #[inline(always)] #[must_use] - pub fn nmipendset(&mut self) -> NMIPENDSET_W<31> { + pub fn nmipendset(&mut self) -> NMIPENDSET_W { NMIPENDSET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [icsr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICSR_SPEC; impl crate::RegisterSpec for ICSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [icsr::R](R) reader structure"] -impl crate::Readable for ICSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +#[doc = "`read()` method returns [`icsr::R`](R) reader structure"] +impl crate::Readable for ICSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"] impl crate::Writable for ICSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs index 188537145..04d57b21d 100644 --- a/src/ppb/mpu_ctrl.rs +++ b/src/ppb/mpu_ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `MPU_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MPU_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] @@ -41,7 +9,7 @@ pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, MPU_CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HFNMIENA` reader - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. @@ -51,7 +19,7 @@ pub type HFNMIENA_R = crate::BitReader; When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] -pub type HFNMIENA_W<'a, const O: u8> = crate::BitWriter<'a, MPU_CTRL_SPEC, O>; +pub type HFNMIENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRIVDEFENA` reader - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. @@ -63,7 +31,7 @@ pub type PRIVDEFENA_R = crate::BitReader; covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] -pub type PRIVDEFENA_W<'a, const O: u8> = crate::BitWriter<'a, MPU_CTRL_SPEC, O>; +pub type PRIVDEFENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. @@ -96,7 +64,7 @@ impl W { 1 = MPU enabled."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. @@ -105,7 +73,7 @@ impl W { 1 = the MPU is enabled during HardFault and NMI handlers."] #[inline(always)] #[must_use] - pub fn hfnmiena(&mut self) -> HFNMIENA_W<1> { + pub fn hfnmiena(&mut self) -> HFNMIENA_W { HFNMIENA_W::new(self) } #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. @@ -115,32 +83,31 @@ impl W { When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] #[inline(always)] #[must_use] - pub fn privdefena(&mut self) -> PRIVDEFENA_W<2> { + pub fn privdefena(&mut self) -> PRIVDEFENA_W { PRIVDEFENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mpu_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_CTRL_SPEC; impl crate::RegisterSpec for MPU_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mpu_ctrl::R](R) reader structure"] -impl crate::Readable for MPU_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mpu_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`mpu_ctrl::R`](R) reader structure"] +impl crate::Readable for MPU_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"] impl crate::Writable for MPU_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/mpu_rasr.rs b/src/ppb/mpu_rasr.rs index 60bbc8e6c..7ff9cf845 100644 --- a/src/ppb/mpu_rasr.rs +++ b/src/ppb/mpu_rasr.rs @@ -1,51 +1,19 @@ #[doc = "Register `MPU_RASR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MPU_RASR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enables the region."] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enables the region."] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, MPU_RASR_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIZE` reader - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"] pub type SIZE_R = crate::FieldReader; #[doc = "Field `SIZE` writer - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"] -pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RASR_SPEC, 5, O>; +pub type SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SRD` reader - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."] pub type SRD_R = crate::FieldReader; #[doc = "Field `SRD` writer - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."] -pub type SRD_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RASR_SPEC, 8, O>; +pub type SRD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ATTRS` reader - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. @@ -63,7 +31,7 @@ pub type ATTRS_R = crate::FieldReader; 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] -pub type ATTRS_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RASR_SPEC, 16, O, u16>; +pub type ATTRS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Enables the region."] #[inline(always)] @@ -97,19 +65,19 @@ impl W { #[doc = "Bit 0 - Enables the region."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 1:5 - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"] #[inline(always)] #[must_use] - pub fn size(&mut self) -> SIZE_W<1> { + pub fn size(&mut self) -> SIZE_W { SIZE_W::new(self) } #[doc = "Bits 8:15 - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."] #[inline(always)] #[must_use] - pub fn srd(&mut self) -> SRD_W<8> { + pub fn srd(&mut self) -> SRD_W { SRD_W::new(self) } #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. @@ -122,32 +90,31 @@ impl W { 16 = B: Bufferable bit"] #[inline(always)] #[must_use] - pub fn attrs(&mut self) -> ATTRS_W<16> { + pub fn attrs(&mut self) -> ATTRS_W { ATTRS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mpu_rasr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_RASR_SPEC; impl crate::RegisterSpec for MPU_RASR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mpu_rasr::R](R) reader structure"] -impl crate::Readable for MPU_RASR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mpu_rasr::W](W) writer structure"] +#[doc = "`read()` method returns [`mpu_rasr::R`](R) reader structure"] +impl crate::Readable for MPU_RASR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rasr::W`](W) writer structure"] impl crate::Writable for MPU_RASR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs index def245fd6..6a1a16936 100644 --- a/src/ppb/mpu_rbar.rs +++ b/src/ppb/mpu_rbar.rs @@ -1,45 +1,13 @@ #[doc = "Register `MPU_RBAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MPU_RBAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REGION` reader - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits \\[3:0\\] of MPU_RNR."] pub type REGION_R = crate::FieldReader; #[doc = "Field `REGION` writer - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits \\[3:0\\] of MPU_RNR."] -pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RBAR_SPEC, 4, O>; +pub type REGION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `VALID` reader - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: @@ -59,11 +27,11 @@ pub type VALID_R = crate::BitReader; Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] -pub type VALID_W<'a, const O: u8> = crate::BitWriter<'a, MPU_RBAR_SPEC, O>; +pub type VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADDR` reader - Base address of the region."] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Base address of the region."] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RBAR_SPEC, 24, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:3 - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits \\[3:0\\] of MPU_RNR."] @@ -95,7 +63,7 @@ impl W { of MPU_RNR."] #[inline(always)] #[must_use] - pub fn region(&mut self) -> REGION_W<0> { + pub fn region(&mut self) -> REGION_W { REGION_W::new(self) } #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. @@ -109,38 +77,37 @@ of MPU_RNR."] Always reads as zero."] #[inline(always)] #[must_use] - pub fn valid(&mut self) -> VALID_W<4> { + pub fn valid(&mut self) -> VALID_W { VALID_W::new(self) } #[doc = "Bits 8:31 - Base address of the region."] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<8> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mpu_rbar](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rbar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rbar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_RBAR_SPEC; impl crate::RegisterSpec for MPU_RBAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mpu_rbar::R](R) reader structure"] -impl crate::Readable for MPU_RBAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mpu_rbar::W](W) writer structure"] +#[doc = "`read()` method returns [`mpu_rbar::R`](R) reader structure"] +impl crate::Readable for MPU_RBAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rbar::W`](W) writer structure"] impl crate::Writable for MPU_RBAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs index 0ca95179b..ba89b4e35 100644 --- a/src/ppb/mpu_rnr.rs +++ b/src/ppb/mpu_rnr.rs @@ -1,45 +1,13 @@ #[doc = "Register `MPU_RNR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MPU_RNR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REGION` reader - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] pub type REGION_R = crate::FieldReader; #[doc = "Field `REGION` writer - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] -pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, MPU_RNR_SPEC, 4, O>; +pub type REGION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] @@ -53,32 +21,31 @@ impl W { The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] #[inline(always)] #[must_use] - pub fn region(&mut self) -> REGION_W<0> { + pub fn region(&mut self) -> REGION_W { REGION_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mpu_rnr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rnr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_RNR_SPEC; impl crate::RegisterSpec for MPU_RNR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mpu_rnr::R](R) reader structure"] -impl crate::Readable for MPU_RNR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mpu_rnr::W](W) writer structure"] +#[doc = "`read()` method returns [`mpu_rnr::R`](R) reader structure"] +impl crate::Readable for MPU_RNR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rnr::W`](W) writer structure"] impl crate::Writable for MPU_RNR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/mpu_type.rs b/src/ppb/mpu_type.rs index ef12266c2..938076553 100644 --- a/src/ppb/mpu_type.rs +++ b/src/ppb/mpu_type.rs @@ -1,18 +1,5 @@ #[doc = "Register `MPU_TYPE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SEPARATE` reader - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU."] pub type SEPARATE_R = crate::BitReader; #[doc = "Field `DREGION` reader - Number of regions supported by the MPU."] @@ -38,17 +25,13 @@ impl R { } #[doc = "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mpu_type](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_TYPE_SPEC; impl crate::RegisterSpec for MPU_TYPE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mpu_type::R](R) reader structure"] -impl crate::Readable for MPU_TYPE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mpu_type::R`](R) reader structure"] +impl crate::Readable for MPU_TYPE_SPEC {} #[doc = "`reset()` method sets MPU_TYPE to value 0x0800"] impl crate::Resettable for MPU_TYPE_SPEC { const RESET_VALUE: Self::Ux = 0x0800; diff --git a/src/ppb/nvic_icer.rs b/src/ppb/nvic_icer.rs index 7585ffa7e..d08359aa5 100644 --- a/src/ppb/nvic_icer.rs +++ b/src/ppb/nvic_icer.rs @@ -1,39 +1,7 @@ #[doc = "Register `NVIC_ICER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_ICER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLRENA` reader - Interrupt clear-enable bits. Write: 0 = No effect. @@ -49,7 +17,7 @@ pub type CLRENA_R = crate::FieldReader; Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] -pub type CLRENA_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_ICER_SPEC, 32, O, u32>; +pub type CLRENA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Interrupt clear-enable bits. Write: @@ -73,32 +41,31 @@ impl W { 1 = Interrupt enabled."] #[inline(always)] #[must_use] - pub fn clrena(&mut self) -> CLRENA_W<0> { + pub fn clrena(&mut self) -> CLRENA_W { CLRENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_icer](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_ICER_SPEC; impl crate::RegisterSpec for NVIC_ICER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_icer::R](R) reader structure"] -impl crate::Readable for NVIC_ICER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_icer::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_icer::R`](R) reader structure"] +impl crate::Readable for NVIC_ICER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icer::W`](W) writer structure"] impl crate::Writable for NVIC_ICER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_icpr.rs b/src/ppb/nvic_icpr.rs index 04a1fe834..91f084543 100644 --- a/src/ppb/nvic_icpr.rs +++ b/src/ppb/nvic_icpr.rs @@ -1,39 +1,7 @@ #[doc = "Register `NVIC_ICPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_ICPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLRPEND` reader - Interrupt clear-pending bits. Write: 0 = No effect. @@ -49,7 +17,7 @@ pub type CLRPEND_R = crate::FieldReader; Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] -pub type CLRPEND_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_ICPR_SPEC, 32, O, u32>; +pub type CLRPEND_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Interrupt clear-pending bits. Write: @@ -73,32 +41,31 @@ impl W { 1 = Interrupt is pending."] #[inline(always)] #[must_use] - pub fn clrpend(&mut self) -> CLRPEND_W<0> { + pub fn clrpend(&mut self) -> CLRPEND_W { CLRPEND_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_icpr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_ICPR_SPEC; impl crate::RegisterSpec for NVIC_ICPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_icpr::R](R) reader structure"] -impl crate::Readable for NVIC_ICPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_icpr::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_icpr::R`](R) reader structure"] +impl crate::Readable for NVIC_ICPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icpr::W`](W) writer structure"] impl crate::Writable for NVIC_ICPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs index b47675f8b..d61a2e991 100644 --- a/src/ppb/nvic_ipr0.rs +++ b/src/ppb/nvic_ipr0.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_0` reader - Priority of interrupt 0"] pub type IP_0_R = crate::FieldReader; #[doc = "Field `IP_0` writer - Priority of interrupt 0"] -pub type IP_0_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR0_SPEC, 2, O>; +pub type IP_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_1` reader - Priority of interrupt 1"] pub type IP_1_R = crate::FieldReader; #[doc = "Field `IP_1` writer - Priority of interrupt 1"] -pub type IP_1_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR0_SPEC, 2, O>; +pub type IP_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_2` reader - Priority of interrupt 2"] pub type IP_2_R = crate::FieldReader; #[doc = "Field `IP_2` writer - Priority of interrupt 2"] -pub type IP_2_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR0_SPEC, 2, O>; +pub type IP_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_3` reader - Priority of interrupt 3"] pub type IP_3_R = crate::FieldReader; #[doc = "Field `IP_3` writer - Priority of interrupt 3"] -pub type IP_3_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR0_SPEC, 2, O>; +pub type IP_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 0"] #[inline(always)] @@ -76,31 +44,35 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 0"] #[inline(always)] #[must_use] - pub fn ip_0(&mut self) -> IP_0_W<6> { + pub fn ip_0(&mut self) -> IP_0_W { IP_0_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 1"] #[inline(always)] #[must_use] - pub fn ip_1(&mut self) -> IP_1_W<14> { + pub fn ip_1(&mut self) -> IP_1_W { IP_1_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 2"] #[inline(always)] #[must_use] - pub fn ip_2(&mut self) -> IP_2_W<22> { + pub fn ip_2(&mut self) -> IP_2_W { IP_2_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 3"] #[inline(always)] #[must_use] - pub fn ip_3(&mut self) -> IP_3_W<30> { + pub fn ip_3(&mut self) -> IP_3_W { IP_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -108,20 +80,15 @@ impl W { Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR0_SPEC; impl crate::RegisterSpec for NVIC_IPR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr0::R](R) reader structure"] -impl crate::Readable for NVIC_IPR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr0::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr0::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr0::W`](W) writer structure"] impl crate::Writable for NVIC_IPR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr1.rs b/src/ppb/nvic_ipr1.rs index 792ee49ac..4c6d83be9 100644 --- a/src/ppb/nvic_ipr1.rs +++ b/src/ppb/nvic_ipr1.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_4` reader - Priority of interrupt 4"] pub type IP_4_R = crate::FieldReader; #[doc = "Field `IP_4` writer - Priority of interrupt 4"] -pub type IP_4_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR1_SPEC, 2, O>; +pub type IP_4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_5` reader - Priority of interrupt 5"] pub type IP_5_R = crate::FieldReader; #[doc = "Field `IP_5` writer - Priority of interrupt 5"] -pub type IP_5_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR1_SPEC, 2, O>; +pub type IP_5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_6` reader - Priority of interrupt 6"] pub type IP_6_R = crate::FieldReader; #[doc = "Field `IP_6` writer - Priority of interrupt 6"] -pub type IP_6_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR1_SPEC, 2, O>; +pub type IP_6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_7` reader - Priority of interrupt 7"] pub type IP_7_R = crate::FieldReader; #[doc = "Field `IP_7` writer - Priority of interrupt 7"] -pub type IP_7_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR1_SPEC, 2, O>; +pub type IP_7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 4"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 4"] #[inline(always)] #[must_use] - pub fn ip_4(&mut self) -> IP_4_W<6> { + pub fn ip_4(&mut self) -> IP_4_W { IP_4_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 5"] #[inline(always)] #[must_use] - pub fn ip_5(&mut self) -> IP_5_W<14> { + pub fn ip_5(&mut self) -> IP_5_W { IP_5_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 6"] #[inline(always)] #[must_use] - pub fn ip_6(&mut self) -> IP_6_W<22> { + pub fn ip_6(&mut self) -> IP_6_W { IP_6_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 7"] #[inline(always)] #[must_use] - pub fn ip_7(&mut self) -> IP_7_W<30> { + pub fn ip_7(&mut self) -> IP_7_W { IP_7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR1_SPEC; impl crate::RegisterSpec for NVIC_IPR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr1::R](R) reader structure"] -impl crate::Readable for NVIC_IPR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr1::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr1::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr1::W`](W) writer structure"] impl crate::Writable for NVIC_IPR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr2.rs b/src/ppb/nvic_ipr2.rs index b4966b212..3723ca54b 100644 --- a/src/ppb/nvic_ipr2.rs +++ b/src/ppb/nvic_ipr2.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_8` reader - Priority of interrupt 8"] pub type IP_8_R = crate::FieldReader; #[doc = "Field `IP_8` writer - Priority of interrupt 8"] -pub type IP_8_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR2_SPEC, 2, O>; +pub type IP_8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_9` reader - Priority of interrupt 9"] pub type IP_9_R = crate::FieldReader; #[doc = "Field `IP_9` writer - Priority of interrupt 9"] -pub type IP_9_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR2_SPEC, 2, O>; +pub type IP_9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_10` reader - Priority of interrupt 10"] pub type IP_10_R = crate::FieldReader; #[doc = "Field `IP_10` writer - Priority of interrupt 10"] -pub type IP_10_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR2_SPEC, 2, O>; +pub type IP_10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_11` reader - Priority of interrupt 11"] pub type IP_11_R = crate::FieldReader; #[doc = "Field `IP_11` writer - Priority of interrupt 11"] -pub type IP_11_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR2_SPEC, 2, O>; +pub type IP_11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 8"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 8"] #[inline(always)] #[must_use] - pub fn ip_8(&mut self) -> IP_8_W<6> { + pub fn ip_8(&mut self) -> IP_8_W { IP_8_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 9"] #[inline(always)] #[must_use] - pub fn ip_9(&mut self) -> IP_9_W<14> { + pub fn ip_9(&mut self) -> IP_9_W { IP_9_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 10"] #[inline(always)] #[must_use] - pub fn ip_10(&mut self) -> IP_10_W<22> { + pub fn ip_10(&mut self) -> IP_10_W { IP_10_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 11"] #[inline(always)] #[must_use] - pub fn ip_11(&mut self) -> IP_11_W<30> { + pub fn ip_11(&mut self) -> IP_11_W { IP_11_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR2_SPEC; impl crate::RegisterSpec for NVIC_IPR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr2::R](R) reader structure"] -impl crate::Readable for NVIC_IPR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr2::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr2::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr2::W`](W) writer structure"] impl crate::Writable for NVIC_IPR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr3.rs b/src/ppb/nvic_ipr3.rs index 4a7c767f7..cd71e4545 100644 --- a/src/ppb/nvic_ipr3.rs +++ b/src/ppb/nvic_ipr3.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_12` reader - Priority of interrupt 12"] pub type IP_12_R = crate::FieldReader; #[doc = "Field `IP_12` writer - Priority of interrupt 12"] -pub type IP_12_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR3_SPEC, 2, O>; +pub type IP_12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_13` reader - Priority of interrupt 13"] pub type IP_13_R = crate::FieldReader; #[doc = "Field `IP_13` writer - Priority of interrupt 13"] -pub type IP_13_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR3_SPEC, 2, O>; +pub type IP_13_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_14` reader - Priority of interrupt 14"] pub type IP_14_R = crate::FieldReader; #[doc = "Field `IP_14` writer - Priority of interrupt 14"] -pub type IP_14_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR3_SPEC, 2, O>; +pub type IP_14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_15` reader - Priority of interrupt 15"] pub type IP_15_R = crate::FieldReader; #[doc = "Field `IP_15` writer - Priority of interrupt 15"] -pub type IP_15_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR3_SPEC, 2, O>; +pub type IP_15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 12"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 12"] #[inline(always)] #[must_use] - pub fn ip_12(&mut self) -> IP_12_W<6> { + pub fn ip_12(&mut self) -> IP_12_W { IP_12_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 13"] #[inline(always)] #[must_use] - pub fn ip_13(&mut self) -> IP_13_W<14> { + pub fn ip_13(&mut self) -> IP_13_W { IP_13_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 14"] #[inline(always)] #[must_use] - pub fn ip_14(&mut self) -> IP_14_W<22> { + pub fn ip_14(&mut self) -> IP_14_W { IP_14_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 15"] #[inline(always)] #[must_use] - pub fn ip_15(&mut self) -> IP_15_W<30> { + pub fn ip_15(&mut self) -> IP_15_W { IP_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR3_SPEC; impl crate::RegisterSpec for NVIC_IPR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr3::R](R) reader structure"] -impl crate::Readable for NVIC_IPR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr3::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr3::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr3::W`](W) writer structure"] impl crate::Writable for NVIC_IPR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr4.rs b/src/ppb/nvic_ipr4.rs index 72801bb26..7ee7acd6f 100644 --- a/src/ppb/nvic_ipr4.rs +++ b/src/ppb/nvic_ipr4.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_16` reader - Priority of interrupt 16"] pub type IP_16_R = crate::FieldReader; #[doc = "Field `IP_16` writer - Priority of interrupt 16"] -pub type IP_16_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR4_SPEC, 2, O>; +pub type IP_16_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_17` reader - Priority of interrupt 17"] pub type IP_17_R = crate::FieldReader; #[doc = "Field `IP_17` writer - Priority of interrupt 17"] -pub type IP_17_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR4_SPEC, 2, O>; +pub type IP_17_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_18` reader - Priority of interrupt 18"] pub type IP_18_R = crate::FieldReader; #[doc = "Field `IP_18` writer - Priority of interrupt 18"] -pub type IP_18_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR4_SPEC, 2, O>; +pub type IP_18_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_19` reader - Priority of interrupt 19"] pub type IP_19_R = crate::FieldReader; #[doc = "Field `IP_19` writer - Priority of interrupt 19"] -pub type IP_19_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR4_SPEC, 2, O>; +pub type IP_19_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 16"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 16"] #[inline(always)] #[must_use] - pub fn ip_16(&mut self) -> IP_16_W<6> { + pub fn ip_16(&mut self) -> IP_16_W { IP_16_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 17"] #[inline(always)] #[must_use] - pub fn ip_17(&mut self) -> IP_17_W<14> { + pub fn ip_17(&mut self) -> IP_17_W { IP_17_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 18"] #[inline(always)] #[must_use] - pub fn ip_18(&mut self) -> IP_18_W<22> { + pub fn ip_18(&mut self) -> IP_18_W { IP_18_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 19"] #[inline(always)] #[must_use] - pub fn ip_19(&mut self) -> IP_19_W<30> { + pub fn ip_19(&mut self) -> IP_19_W { IP_19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr4](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR4_SPEC; impl crate::RegisterSpec for NVIC_IPR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr4::R](R) reader structure"] -impl crate::Readable for NVIC_IPR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr4::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr4::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr4::W`](W) writer structure"] impl crate::Writable for NVIC_IPR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr5.rs b/src/ppb/nvic_ipr5.rs index 579aa0c4a..0af8b30ab 100644 --- a/src/ppb/nvic_ipr5.rs +++ b/src/ppb/nvic_ipr5.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_20` reader - Priority of interrupt 20"] pub type IP_20_R = crate::FieldReader; #[doc = "Field `IP_20` writer - Priority of interrupt 20"] -pub type IP_20_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR5_SPEC, 2, O>; +pub type IP_20_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_21` reader - Priority of interrupt 21"] pub type IP_21_R = crate::FieldReader; #[doc = "Field `IP_21` writer - Priority of interrupt 21"] -pub type IP_21_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR5_SPEC, 2, O>; +pub type IP_21_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_22` reader - Priority of interrupt 22"] pub type IP_22_R = crate::FieldReader; #[doc = "Field `IP_22` writer - Priority of interrupt 22"] -pub type IP_22_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR5_SPEC, 2, O>; +pub type IP_22_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_23` reader - Priority of interrupt 23"] pub type IP_23_R = crate::FieldReader; #[doc = "Field `IP_23` writer - Priority of interrupt 23"] -pub type IP_23_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR5_SPEC, 2, O>; +pub type IP_23_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 20"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 20"] #[inline(always)] #[must_use] - pub fn ip_20(&mut self) -> IP_20_W<6> { + pub fn ip_20(&mut self) -> IP_20_W { IP_20_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 21"] #[inline(always)] #[must_use] - pub fn ip_21(&mut self) -> IP_21_W<14> { + pub fn ip_21(&mut self) -> IP_21_W { IP_21_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 22"] #[inline(always)] #[must_use] - pub fn ip_22(&mut self) -> IP_22_W<22> { + pub fn ip_22(&mut self) -> IP_22_W { IP_22_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 23"] #[inline(always)] #[must_use] - pub fn ip_23(&mut self) -> IP_23_W<30> { + pub fn ip_23(&mut self) -> IP_23_W { IP_23_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr5](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR5_SPEC; impl crate::RegisterSpec for NVIC_IPR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr5::R](R) reader structure"] -impl crate::Readable for NVIC_IPR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr5::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr5::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr5::W`](W) writer structure"] impl crate::Writable for NVIC_IPR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr6.rs b/src/ppb/nvic_ipr6.rs index 7952266cd..f5cce3837 100644 --- a/src/ppb/nvic_ipr6.rs +++ b/src/ppb/nvic_ipr6.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_24` reader - Priority of interrupt 24"] pub type IP_24_R = crate::FieldReader; #[doc = "Field `IP_24` writer - Priority of interrupt 24"] -pub type IP_24_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR6_SPEC, 2, O>; +pub type IP_24_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_25` reader - Priority of interrupt 25"] pub type IP_25_R = crate::FieldReader; #[doc = "Field `IP_25` writer - Priority of interrupt 25"] -pub type IP_25_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR6_SPEC, 2, O>; +pub type IP_25_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_26` reader - Priority of interrupt 26"] pub type IP_26_R = crate::FieldReader; #[doc = "Field `IP_26` writer - Priority of interrupt 26"] -pub type IP_26_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR6_SPEC, 2, O>; +pub type IP_26_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_27` reader - Priority of interrupt 27"] pub type IP_27_R = crate::FieldReader; #[doc = "Field `IP_27` writer - Priority of interrupt 27"] -pub type IP_27_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR6_SPEC, 2, O>; +pub type IP_27_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 24"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 24"] #[inline(always)] #[must_use] - pub fn ip_24(&mut self) -> IP_24_W<6> { + pub fn ip_24(&mut self) -> IP_24_W { IP_24_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 25"] #[inline(always)] #[must_use] - pub fn ip_25(&mut self) -> IP_25_W<14> { + pub fn ip_25(&mut self) -> IP_25_W { IP_25_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 26"] #[inline(always)] #[must_use] - pub fn ip_26(&mut self) -> IP_26_W<22> { + pub fn ip_26(&mut self) -> IP_26_W { IP_26_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 27"] #[inline(always)] #[must_use] - pub fn ip_27(&mut self) -> IP_27_W<30> { + pub fn ip_27(&mut self) -> IP_27_W { IP_27_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr6](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR6_SPEC; impl crate::RegisterSpec for NVIC_IPR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr6::R](R) reader structure"] -impl crate::Readable for NVIC_IPR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr6::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr6::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr6::W`](W) writer structure"] impl crate::Writable for NVIC_IPR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ipr7.rs b/src/ppb/nvic_ipr7.rs index 51ff317bc..25fe7c1f0 100644 --- a/src/ppb/nvic_ipr7.rs +++ b/src/ppb/nvic_ipr7.rs @@ -1,55 +1,23 @@ #[doc = "Register `NVIC_IPR7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_IPR7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP_28` reader - Priority of interrupt 28"] pub type IP_28_R = crate::FieldReader; #[doc = "Field `IP_28` writer - Priority of interrupt 28"] -pub type IP_28_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR7_SPEC, 2, O>; +pub type IP_28_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_29` reader - Priority of interrupt 29"] pub type IP_29_R = crate::FieldReader; #[doc = "Field `IP_29` writer - Priority of interrupt 29"] -pub type IP_29_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR7_SPEC, 2, O>; +pub type IP_29_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_30` reader - Priority of interrupt 30"] pub type IP_30_R = crate::FieldReader; #[doc = "Field `IP_30` writer - Priority of interrupt 30"] -pub type IP_30_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR7_SPEC, 2, O>; +pub type IP_30_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IP_31` reader - Priority of interrupt 31"] pub type IP_31_R = crate::FieldReader; #[doc = "Field `IP_31` writer - Priority of interrupt 31"] -pub type IP_31_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_IPR7_SPEC, 2, O>; +pub type IP_31_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 6:7 - Priority of interrupt 28"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 6:7 - Priority of interrupt 28"] #[inline(always)] #[must_use] - pub fn ip_28(&mut self) -> IP_28_W<6> { + pub fn ip_28(&mut self) -> IP_28_W { IP_28_W::new(self) } #[doc = "Bits 14:15 - Priority of interrupt 29"] #[inline(always)] #[must_use] - pub fn ip_29(&mut self) -> IP_29_W<14> { + pub fn ip_29(&mut self) -> IP_29_W { IP_29_W::new(self) } #[doc = "Bits 22:23 - Priority of interrupt 30"] #[inline(always)] #[must_use] - pub fn ip_30(&mut self) -> IP_30_W<22> { + pub fn ip_30(&mut self) -> IP_30_W { IP_30_W::new(self) } #[doc = "Bits 30:31 - Priority of interrupt 31"] #[inline(always)] #[must_use] - pub fn ip_31(&mut self) -> IP_31_W<30> { + pub fn ip_31(&mut self) -> IP_31_W { IP_31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ipr7](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR7_SPEC; impl crate::RegisterSpec for NVIC_IPR7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ipr7::R](R) reader structure"] -impl crate::Readable for NVIC_IPR7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ipr7::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ipr7::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr7::W`](W) writer structure"] impl crate::Writable for NVIC_IPR7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_iser.rs b/src/ppb/nvic_iser.rs index 254dff120..e693b5233 100644 --- a/src/ppb/nvic_iser.rs +++ b/src/ppb/nvic_iser.rs @@ -1,39 +1,7 @@ #[doc = "Register `NVIC_ISER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_ISER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SETENA` reader - Interrupt set-enable bits. Write: 0 = No effect. @@ -49,7 +17,7 @@ pub type SETENA_R = crate::FieldReader; Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] -pub type SETENA_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_ISER_SPEC, 32, O, u32>; +pub type SETENA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Interrupt set-enable bits. Write: @@ -73,33 +41,32 @@ impl W { 1 = Interrupt enabled."] #[inline(always)] #[must_use] - pub fn setena(&mut self) -> SETENA_W<0> { + pub fn setena(&mut self) -> SETENA_W { SETENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_iser](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_ISER_SPEC; impl crate::RegisterSpec for NVIC_ISER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_iser::R](R) reader structure"] -impl crate::Readable for NVIC_ISER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_iser::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_iser::R`](R) reader structure"] +impl crate::Readable for NVIC_ISER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_iser::W`](W) writer structure"] impl crate::Writable for NVIC_ISER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/nvic_ispr.rs b/src/ppb/nvic_ispr.rs index 16656e090..3c04a20ed 100644 --- a/src/ppb/nvic_ispr.rs +++ b/src/ppb/nvic_ispr.rs @@ -1,39 +1,7 @@ #[doc = "Register `NVIC_ISPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NVIC_ISPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SETPEND` reader - Interrupt set-pending bits. Write: 0 = No effect. @@ -55,7 +23,7 @@ pub type SETPEND_R = crate::FieldReader; Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] -pub type SETPEND_W<'a, const O: u8> = crate::FieldWriter<'a, NVIC_ISPR_SPEC, 32, O, u32>; +pub type SETPEND_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Interrupt set-pending bits. Write: @@ -85,32 +53,31 @@ impl W { A disabled interrupt sets the state of that interrupt to pending."] #[inline(always)] #[must_use] - pub fn setpend(&mut self) -> SETPEND_W<0> { + pub fn setpend(&mut self) -> SETPEND_W { SETPEND_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nvic_ispr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_ISPR_SPEC; impl crate::RegisterSpec for NVIC_ISPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nvic_ispr::R](R) reader structure"] -impl crate::Readable for NVIC_ISPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nvic_ispr::W](W) writer structure"] +#[doc = "`read()` method returns [`nvic_ispr::R`](R) reader structure"] +impl crate::Readable for NVIC_ISPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ispr::W`](W) writer structure"] impl crate::Writable for NVIC_ISPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs index 944c41336..14568ea60 100644 --- a/src/ppb/scr.rs +++ b/src/ppb/scr.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLEEPONEXIT` reader - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. @@ -43,7 +11,7 @@ pub type SLEEPONEXIT_R = crate::BitReader; 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] -pub type SLEEPONEXIT_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type SLEEPONEXIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SLEEPDEEP` reader - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] @@ -51,7 +19,7 @@ pub type SLEEPDEEP_R = crate::BitReader; #[doc = "Field `SLEEPDEEP` writer - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] -pub type SLEEPDEEP_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type SLEEPDEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SEVONPEND` reader - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. @@ -65,7 +33,7 @@ pub type SEVONPEND_R = crate::BitReader; When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] -pub type SEVONPEND_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type SEVONPEND_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. @@ -100,7 +68,7 @@ impl W { Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] #[inline(always)] #[must_use] - pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<1> { + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { SLEEPONEXIT_W::new(self) } #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: @@ -108,7 +76,7 @@ impl W { 1 = Deep sleep."] #[inline(always)] #[must_use] - pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<2> { + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { SLEEPDEEP_W::new(self) } #[doc = "Bit 4 - Send Event on Pending bit: @@ -119,32 +87,31 @@ impl W { The processor also wakes up on execution of an SEV instruction or an external event."] #[inline(always)] #[must_use] - pub fn sevonpend(&mut self) -> SEVONPEND_W<4> { + pub fn sevonpend(&mut self) -> SEVONPEND_W { SEVONPEND_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCR_SPEC; impl crate::RegisterSpec for SCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scr::R](R) reader structure"] -impl crate::Readable for SCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for SCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] impl crate::Writable for SCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/shcsr.rs b/src/ppb/shcsr.rs index 235417c26..9ee3a6fad 100644 --- a/src/ppb/shcsr.rs +++ b/src/ppb/shcsr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SHCSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SHCSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SVCALLPENDED` reader - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall."] pub type SVCALLPENDED_R = crate::BitReader; #[doc = "Field `SVCALLPENDED` writer - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall."] -pub type SVCALLPENDED_W<'a, const O: u8> = crate::BitWriter<'a, SHCSR_SPEC, O>; +pub type SVCALLPENDED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 15 - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 15 - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall."] #[inline(always)] #[must_use] - pub fn svcallpended(&mut self) -> SVCALLPENDED_W<15> { + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { SVCALLPENDED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [shcsr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`shcsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SHCSR_SPEC; impl crate::RegisterSpec for SHCSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [shcsr::R](R) reader structure"] -impl crate::Readable for SHCSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +#[doc = "`read()` method returns [`shcsr::R`](R) reader structure"] +impl crate::Readable for SHCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shcsr::W`](W) writer structure"] impl crate::Writable for SHCSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/shpr2.rs b/src/ppb/shpr2.rs index 445096f99..9db178380 100644 --- a/src/ppb/shpr2.rs +++ b/src/ppb/shpr2.rs @@ -1,43 +1,11 @@ #[doc = "Register `SHPR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SHPR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] pub type PRI_11_R = crate::FieldReader; #[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] -pub type PRI_11_W<'a, const O: u8> = crate::FieldWriter<'a, SHPR2_SPEC, 2, O>; +pub type PRI_11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 30:31 - Priority of system handler 11, SVCall"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 30:31 - Priority of system handler 11, SVCall"] #[inline(always)] #[must_use] - pub fn pri_11(&mut self) -> PRI_11_W<30> { + pub fn pri_11(&mut self) -> PRI_11_W { PRI_11_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [shpr2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`shpr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SHPR2_SPEC; impl crate::RegisterSpec for SHPR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [shpr2::R](R) reader structure"] -impl crate::Readable for SHPR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +#[doc = "`read()` method returns [`shpr2::R`](R) reader structure"] +impl crate::Readable for SHPR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shpr2::W`](W) writer structure"] impl crate::Writable for SHPR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/shpr3.rs b/src/ppb/shpr3.rs index f3fb461cb..95231aa0a 100644 --- a/src/ppb/shpr3.rs +++ b/src/ppb/shpr3.rs @@ -1,47 +1,15 @@ #[doc = "Register `SHPR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SHPR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] pub type PRI_14_R = crate::FieldReader; #[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] -pub type PRI_14_W<'a, const O: u8> = crate::FieldWriter<'a, SHPR3_SPEC, 2, O>; +pub type PRI_14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick"] pub type PRI_15_R = crate::FieldReader; #[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick"] -pub type PRI_15_W<'a, const O: u8> = crate::FieldWriter<'a, SHPR3_SPEC, 2, O>; +pub type PRI_15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 22:23 - Priority of system handler 14, PendSV"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 22:23 - Priority of system handler 14, PendSV"] #[inline(always)] #[must_use] - pub fn pri_14(&mut self) -> PRI_14_W<22> { + pub fn pri_14(&mut self) -> PRI_14_W { PRI_14_W::new(self) } #[doc = "Bits 30:31 - Priority of system handler 15, SysTick"] #[inline(always)] #[must_use] - pub fn pri_15(&mut self) -> PRI_15_W<30> { + pub fn pri_15(&mut self) -> PRI_15_W { PRI_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [shpr3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`shpr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SHPR3_SPEC; impl crate::RegisterSpec for SHPR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [shpr3::R](R) reader structure"] -impl crate::Readable for SHPR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +#[doc = "`read()` method returns [`shpr3::R`](R) reader structure"] +impl crate::Readable for SHPR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shpr3::W`](W) writer structure"] impl crate::Writable for SHPR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/syst_calib.rs b/src/ppb/syst_calib.rs index 4ce2f1fb2..55ae9a88d 100644 --- a/src/ppb/syst_calib.rs +++ b/src/ppb/syst_calib.rs @@ -1,18 +1,5 @@ #[doc = "Register `SYST_CALIB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TENMS` reader - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known."] pub type TENMS_R = crate::FieldReader; #[doc = "Field `SKEW` reader - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)."] @@ -38,17 +25,13 @@ impl R { } #[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [syst_calib](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_CALIB_SPEC; impl crate::RegisterSpec for SYST_CALIB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [syst_calib::R](R) reader structure"] -impl crate::Readable for SYST_CALIB_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`syst_calib::R`](R) reader structure"] +impl crate::Readable for SYST_CALIB_SPEC {} #[doc = "`reset()` method sets SYST_CALIB to value 0"] impl crate::Resettable for SYST_CALIB_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs index 15424754d..b738d992c 100644 --- a/src/ppb/syst_csr.rs +++ b/src/ppb/syst_csr.rs @@ -1,39 +1,7 @@ #[doc = "Register `SYST_CSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SYST_CSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] @@ -41,7 +9,7 @@ pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, SYST_CSR_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TICKINT` reader - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] @@ -49,7 +17,7 @@ pub type TICKINT_R = crate::BitReader; #[doc = "Field `TICKINT` writer - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] -pub type TICKINT_W<'a, const O: u8> = crate::BitWriter<'a, SYST_CSR_SPEC, O>; +pub type TICKINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKSOURCE` reader - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. @@ -59,7 +27,7 @@ pub type CLKSOURCE_R = crate::BitReader; Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] -pub type CLKSOURCE_W<'a, const O: u8> = crate::BitWriter<'a, SYST_CSR_SPEC, O>; +pub type CLKSOURCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COUNTFLAG` reader - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger."] pub type COUNTFLAG_R = crate::BitReader; impl R { @@ -97,7 +65,7 @@ impl W { 1 = Counter enabled."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 1 - Enables SysTick exception request: @@ -105,7 +73,7 @@ impl W { 1 = Counting down to zero to asserts the SysTick exception request."] #[inline(always)] #[must_use] - pub fn tickint(&mut self) -> TICKINT_W<1> { + pub fn tickint(&mut self) -> TICKINT_W { TICKINT_W::new(self) } #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. @@ -114,32 +82,31 @@ impl W { 1 = Processor clock."] #[inline(always)] #[must_use] - pub fn clksource(&mut self) -> CLKSOURCE_W<2> { + pub fn clksource(&mut self) -> CLKSOURCE_W { CLKSOURCE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the SysTick Control and Status Register to enable the SysTick features. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [syst_csr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`syst_csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_CSR_SPEC; impl crate::RegisterSpec for SYST_CSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [syst_csr::R](R) reader structure"] -impl crate::Readable for SYST_CSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [syst_csr::W](W) writer structure"] +#[doc = "`read()` method returns [`syst_csr::R`](R) reader structure"] +impl crate::Readable for SYST_CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_csr::W`](W) writer structure"] impl crate::Writable for SYST_CSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/syst_cvr.rs b/src/ppb/syst_cvr.rs index 381d09eba..1c4c92b3c 100644 --- a/src/ppb/syst_cvr.rs +++ b/src/ppb/syst_cvr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SYST_CVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SYST_CVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CURRENT` reader - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] pub type CURRENT_R = crate::FieldReader; #[doc = "Field `CURRENT` writer - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] -pub type CURRENT_W<'a, const O: u8> = crate::FieldWriter<'a, SYST_CVR_SPEC, 24, O, u32>; +pub type CURRENT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] #[inline(always)] #[must_use] - pub fn current(&mut self) -> CURRENT_W<0> { + pub fn current(&mut self) -> CURRENT_W { CURRENT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [syst_cvr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`syst_cvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_CVR_SPEC; impl crate::RegisterSpec for SYST_CVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [syst_cvr::R](R) reader structure"] -impl crate::Readable for SYST_CVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [syst_cvr::W](W) writer structure"] +#[doc = "`read()` method returns [`syst_cvr::R`](R) reader structure"] +impl crate::Readable for SYST_CVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_cvr::W`](W) writer structure"] impl crate::Writable for SYST_CVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs index e5a99b0d7..b30698454 100644 --- a/src/ppb/syst_rvr.rs +++ b/src/ppb/syst_rvr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SYST_RVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SYST_RVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0."] pub type RELOAD_R = crate::FieldReader; #[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0."] -pub type RELOAD_W<'a, const O: u8> = crate::FieldWriter<'a, SYST_RVR_SPEC, 24, O, u32>; +pub type RELOAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0."] #[inline(always)] @@ -49,33 +17,32 @@ impl W { #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0."] #[inline(always)] #[must_use] - pub fn reload(&mut self) -> RELOAD_W<0> { + pub fn reload(&mut self) -> RELOAD_W { RELOAD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [syst_rvr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_RVR_SPEC; impl crate::RegisterSpec for SYST_RVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [syst_rvr::R](R) reader structure"] -impl crate::Readable for SYST_RVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [syst_rvr::W](W) writer structure"] +#[doc = "`read()` method returns [`syst_rvr::R`](R) reader structure"] +impl crate::Readable for SYST_RVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_rvr::W`](W) writer structure"] impl crate::Writable for SYST_RVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/ppb/vtor.rs b/src/ppb/vtor.rs index 7d0d950c7..e94a79614 100644 --- a/src/ppb/vtor.rs +++ b/src/ppb/vtor.rs @@ -1,45 +1,13 @@ #[doc = "Register `VTOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `VTOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TBLOFF` reader - Bits \\[31:8\\] of the indicate the vector table offset address."] pub type TBLOFF_R = crate::FieldReader; #[doc = "Field `TBLOFF` writer - Bits \\[31:8\\] of the indicate the vector table offset address."] -pub type TBLOFF_W<'a, const O: u8> = crate::FieldWriter<'a, VTOR_SPEC, 24, O, u32>; +pub type TBLOFF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 8:31 - Bits \\[31:8\\] of the indicate the vector table offset address."] @@ -53,32 +21,31 @@ impl W { of the indicate the vector table offset address."] #[inline(always)] #[must_use] - pub fn tbloff(&mut self) -> TBLOFF_W<8> { + pub fn tbloff(&mut self) -> TBLOFF_W { TBLOFF_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "The VTOR holds the vector table offset address. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [vtor](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`vtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VTOR_SPEC; impl crate::RegisterSpec for VTOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vtor::R](R) reader structure"] -impl crate::Readable for VTOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +#[doc = "`read()` method returns [`vtor::R`](R) reader structure"] +impl crate::Readable for VTOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vtor::W`](W) writer structure"] impl crate::Writable for VTOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/psm.rs b/src/psm.rs index a63b4b620..ace8e4a65 100644 --- a/src/psm.rs +++ b/src/psm.rs @@ -10,19 +10,39 @@ pub struct RegisterBlock { #[doc = "0x0c - Indicates the peripheral's registers are ready to access."] pub done: DONE, } -#[doc = "FRCE_ON (rw) register accessor: an alias for `Reg`"] +#[doc = "FRCE_ON (rw) register accessor: Force block out of reset (i.e. power it on) + +You can [`read`](crate::generic::Reg::read) this register and get [`frce_on::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_on::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@frce_on`] +module"] pub type FRCE_ON = crate::Reg; #[doc = "Force block out of reset (i.e. power it on)"] pub mod frce_on; -#[doc = "FRCE_OFF (rw) register accessor: an alias for `Reg`"] +#[doc = "FRCE_OFF (rw) register accessor: Force into reset (i.e. power it off) + +You can [`read`](crate::generic::Reg::read) this register and get [`frce_off::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_off::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@frce_off`] +module"] pub type FRCE_OFF = crate::Reg; #[doc = "Force into reset (i.e. power it off)"] pub mod frce_off; -#[doc = "WDSEL (rw) register accessor: an alias for `Reg`"] +#[doc = "WDSEL (rw) register accessor: Set to 1 if this peripheral should be reset when the watchdog fires. + +You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdsel`] +module"] pub type WDSEL = crate::Reg; #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires."] pub mod wdsel; -#[doc = "DONE (r) register accessor: an alias for `Reg`"] +#[doc = "DONE (r) register accessor: Indicates the peripheral's registers are ready to access. + +You can [`read`](crate::generic::Reg::read) this register and get [`done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@done`] +module"] pub type DONE = crate::Reg; #[doc = "Indicates the peripheral's registers are ready to access."] pub mod done; diff --git a/src/psm/done.rs b/src/psm/done.rs index c49eb2f92..33bc2154f 100644 --- a/src/psm/done.rs +++ b/src/psm/done.rs @@ -1,18 +1,5 @@ #[doc = "Register `DONE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `rosc` reader - "] pub type ROSC_R = crate::BitReader; #[doc = "Field `xosc` reader - "] @@ -136,17 +123,13 @@ impl R { } #[doc = "Indicates the peripheral's registers are ready to access. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [done](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DONE_SPEC; impl crate::RegisterSpec for DONE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [done::R](R) reader structure"] -impl crate::Readable for DONE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`done::R`](R) reader structure"] +impl crate::Readable for DONE_SPEC {} #[doc = "`reset()` method sets DONE to value 0"] impl crate::Resettable for DONE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs index 3aac021d0..a702f0722 100644 --- a/src/psm/frce_off.rs +++ b/src/psm/frce_off.rs @@ -1,107 +1,75 @@ #[doc = "Register `FRCE_OFF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FRCE_OFF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `rosc` reader - "] pub type ROSC_R = crate::BitReader; #[doc = "Field `rosc` writer - "] -pub type ROSC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type ROSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xosc` reader - "] pub type XOSC_R = crate::BitReader; #[doc = "Field `xosc` writer - "] -pub type XOSC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type XOSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clocks` reader - "] pub type CLOCKS_R = crate::BitReader; #[doc = "Field `clocks` writer - "] -pub type CLOCKS_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type CLOCKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `resets` reader - "] pub type RESETS_R = crate::BitReader; #[doc = "Field `resets` writer - "] -pub type RESETS_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type RESETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `busfabric` reader - "] pub type BUSFABRIC_R = crate::BitReader; #[doc = "Field `busfabric` writer - "] -pub type BUSFABRIC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type BUSFABRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `rom` reader - "] pub type ROM_R = crate::BitReader; #[doc = "Field `rom` writer - "] -pub type ROM_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram0` reader - "] pub type SRAM0_R = crate::BitReader; #[doc = "Field `sram0` writer - "] -pub type SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram1` reader - "] pub type SRAM1_R = crate::BitReader; #[doc = "Field `sram1` writer - "] -pub type SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram2` reader - "] pub type SRAM2_R = crate::BitReader; #[doc = "Field `sram2` writer - "] -pub type SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram3` reader - "] pub type SRAM3_R = crate::BitReader; #[doc = "Field `sram3` writer - "] -pub type SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram4` reader - "] pub type SRAM4_R = crate::BitReader; #[doc = "Field `sram4` writer - "] -pub type SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram5` reader - "] pub type SRAM5_R = crate::BitReader; #[doc = "Field `sram5` writer - "] -pub type SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xip` reader - "] pub type XIP_R = crate::BitReader; #[doc = "Field `xip` writer - "] -pub type XIP_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type XIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `vreg_and_chip_reset` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; #[doc = "Field `vreg_and_chip_reset` writer - "] -pub type VREG_AND_CHIP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type VREG_AND_CHIP_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sio` reader - "] pub type SIO_R = crate::BitReader; #[doc = "Field `sio` writer - "] -pub type SIO_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type SIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc0` reader - "] pub type PROC0_R = crate::BitReader; #[doc = "Field `proc0` writer - "] -pub type PROC0_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type PROC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc1` reader - "] pub type PROC1_R = crate::BitReader; #[doc = "Field `proc1` writer - "] -pub type PROC1_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_OFF_SPEC, O>; +pub type PROC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -193,128 +161,127 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn rosc(&mut self) -> ROSC_W<0> { + pub fn rosc(&mut self) -> ROSC_W { ROSC_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn xosc(&mut self) -> XOSC_W<1> { + pub fn xosc(&mut self) -> XOSC_W { XOSC_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clocks(&mut self) -> CLOCKS_W<2> { + pub fn clocks(&mut self) -> CLOCKS_W { CLOCKS_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn resets(&mut self) -> RESETS_W<3> { + pub fn resets(&mut self) -> RESETS_W { RESETS_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn busfabric(&mut self) -> BUSFABRIC_W<4> { + pub fn busfabric(&mut self) -> BUSFABRIC_W { BUSFABRIC_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn rom(&mut self) -> ROM_W<5> { + pub fn rom(&mut self) -> ROM_W { ROM_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn sram0(&mut self) -> SRAM0_W<6> { + pub fn sram0(&mut self) -> SRAM0_W { SRAM0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn sram1(&mut self) -> SRAM1_W<7> { + pub fn sram1(&mut self) -> SRAM1_W { SRAM1_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn sram2(&mut self) -> SRAM2_W<8> { + pub fn sram2(&mut self) -> SRAM2_W { SRAM2_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn sram3(&mut self) -> SRAM3_W<9> { + pub fn sram3(&mut self) -> SRAM3_W { SRAM3_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn sram4(&mut self) -> SRAM4_W<10> { + pub fn sram4(&mut self) -> SRAM4_W { SRAM4_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn sram5(&mut self) -> SRAM5_W<11> { + pub fn sram5(&mut self) -> SRAM5_W { SRAM5_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn xip(&mut self) -> XIP_W<12> { + pub fn xip(&mut self) -> XIP_W { XIP_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<13> { + pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W { VREG_AND_CHIP_RESET_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn sio(&mut self) -> SIO_W<14> { + pub fn sio(&mut self) -> SIO_W { SIO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn proc0(&mut self) -> PROC0_W<15> { + pub fn proc0(&mut self) -> PROC0_W { PROC0_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn proc1(&mut self) -> PROC1_W<16> { + pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Force into reset (i.e. power it off) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [frce_off](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`frce_off::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_off::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FRCE_OFF_SPEC; impl crate::RegisterSpec for FRCE_OFF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [frce_off::R](R) reader structure"] -impl crate::Readable for FRCE_OFF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [frce_off::W](W) writer structure"] +#[doc = "`read()` method returns [`frce_off::R`](R) reader structure"] +impl crate::Readable for FRCE_OFF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frce_off::W`](W) writer structure"] impl crate::Writable for FRCE_OFF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs index c07fba0e4..a25d2df67 100644 --- a/src/psm/frce_on.rs +++ b/src/psm/frce_on.rs @@ -1,107 +1,75 @@ #[doc = "Register `FRCE_ON` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FRCE_ON` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `rosc` reader - "] pub type ROSC_R = crate::BitReader; #[doc = "Field `rosc` writer - "] -pub type ROSC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type ROSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xosc` reader - "] pub type XOSC_R = crate::BitReader; #[doc = "Field `xosc` writer - "] -pub type XOSC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type XOSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clocks` reader - "] pub type CLOCKS_R = crate::BitReader; #[doc = "Field `clocks` writer - "] -pub type CLOCKS_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type CLOCKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `resets` reader - "] pub type RESETS_R = crate::BitReader; #[doc = "Field `resets` writer - "] -pub type RESETS_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type RESETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `busfabric` reader - "] pub type BUSFABRIC_R = crate::BitReader; #[doc = "Field `busfabric` writer - "] -pub type BUSFABRIC_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type BUSFABRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `rom` reader - "] pub type ROM_R = crate::BitReader; #[doc = "Field `rom` writer - "] -pub type ROM_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram0` reader - "] pub type SRAM0_R = crate::BitReader; #[doc = "Field `sram0` writer - "] -pub type SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram1` reader - "] pub type SRAM1_R = crate::BitReader; #[doc = "Field `sram1` writer - "] -pub type SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram2` reader - "] pub type SRAM2_R = crate::BitReader; #[doc = "Field `sram2` writer - "] -pub type SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram3` reader - "] pub type SRAM3_R = crate::BitReader; #[doc = "Field `sram3` writer - "] -pub type SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram4` reader - "] pub type SRAM4_R = crate::BitReader; #[doc = "Field `sram4` writer - "] -pub type SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram5` reader - "] pub type SRAM5_R = crate::BitReader; #[doc = "Field `sram5` writer - "] -pub type SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xip` reader - "] pub type XIP_R = crate::BitReader; #[doc = "Field `xip` writer - "] -pub type XIP_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type XIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `vreg_and_chip_reset` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; #[doc = "Field `vreg_and_chip_reset` writer - "] -pub type VREG_AND_CHIP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type VREG_AND_CHIP_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sio` reader - "] pub type SIO_R = crate::BitReader; #[doc = "Field `sio` writer - "] -pub type SIO_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type SIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc0` reader - "] pub type PROC0_R = crate::BitReader; #[doc = "Field `proc0` writer - "] -pub type PROC0_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type PROC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc1` reader - "] pub type PROC1_R = crate::BitReader; #[doc = "Field `proc1` writer - "] -pub type PROC1_W<'a, const O: u8> = crate::BitWriter<'a, FRCE_ON_SPEC, O>; +pub type PROC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -193,128 +161,127 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn rosc(&mut self) -> ROSC_W<0> { + pub fn rosc(&mut self) -> ROSC_W { ROSC_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn xosc(&mut self) -> XOSC_W<1> { + pub fn xosc(&mut self) -> XOSC_W { XOSC_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clocks(&mut self) -> CLOCKS_W<2> { + pub fn clocks(&mut self) -> CLOCKS_W { CLOCKS_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn resets(&mut self) -> RESETS_W<3> { + pub fn resets(&mut self) -> RESETS_W { RESETS_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn busfabric(&mut self) -> BUSFABRIC_W<4> { + pub fn busfabric(&mut self) -> BUSFABRIC_W { BUSFABRIC_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn rom(&mut self) -> ROM_W<5> { + pub fn rom(&mut self) -> ROM_W { ROM_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn sram0(&mut self) -> SRAM0_W<6> { + pub fn sram0(&mut self) -> SRAM0_W { SRAM0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn sram1(&mut self) -> SRAM1_W<7> { + pub fn sram1(&mut self) -> SRAM1_W { SRAM1_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn sram2(&mut self) -> SRAM2_W<8> { + pub fn sram2(&mut self) -> SRAM2_W { SRAM2_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn sram3(&mut self) -> SRAM3_W<9> { + pub fn sram3(&mut self) -> SRAM3_W { SRAM3_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn sram4(&mut self) -> SRAM4_W<10> { + pub fn sram4(&mut self) -> SRAM4_W { SRAM4_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn sram5(&mut self) -> SRAM5_W<11> { + pub fn sram5(&mut self) -> SRAM5_W { SRAM5_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn xip(&mut self) -> XIP_W<12> { + pub fn xip(&mut self) -> XIP_W { XIP_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<13> { + pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W { VREG_AND_CHIP_RESET_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn sio(&mut self) -> SIO_W<14> { + pub fn sio(&mut self) -> SIO_W { SIO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn proc0(&mut self) -> PROC0_W<15> { + pub fn proc0(&mut self) -> PROC0_W { PROC0_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn proc1(&mut self) -> PROC1_W<16> { + pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Force block out of reset (i.e. power it on) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [frce_on](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`frce_on::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_on::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FRCE_ON_SPEC; impl crate::RegisterSpec for FRCE_ON_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [frce_on::R](R) reader structure"] -impl crate::Readable for FRCE_ON_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [frce_on::W](W) writer structure"] +#[doc = "`read()` method returns [`frce_on::R`](R) reader structure"] +impl crate::Readable for FRCE_ON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frce_on::W`](W) writer structure"] impl crate::Writable for FRCE_ON_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs index 64f3702bd..be9033769 100644 --- a/src/psm/wdsel.rs +++ b/src/psm/wdsel.rs @@ -1,107 +1,75 @@ #[doc = "Register `WDSEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WDSEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `rosc` reader - "] pub type ROSC_R = crate::BitReader; #[doc = "Field `rosc` writer - "] -pub type ROSC_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type ROSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xosc` reader - "] pub type XOSC_R = crate::BitReader; #[doc = "Field `xosc` writer - "] -pub type XOSC_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type XOSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `clocks` reader - "] pub type CLOCKS_R = crate::BitReader; #[doc = "Field `clocks` writer - "] -pub type CLOCKS_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type CLOCKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `resets` reader - "] pub type RESETS_R = crate::BitReader; #[doc = "Field `resets` writer - "] -pub type RESETS_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type RESETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `busfabric` reader - "] pub type BUSFABRIC_R = crate::BitReader; #[doc = "Field `busfabric` writer - "] -pub type BUSFABRIC_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type BUSFABRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `rom` reader - "] pub type ROM_R = crate::BitReader; #[doc = "Field `rom` writer - "] -pub type ROM_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram0` reader - "] pub type SRAM0_R = crate::BitReader; #[doc = "Field `sram0` writer - "] -pub type SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram1` reader - "] pub type SRAM1_R = crate::BitReader; #[doc = "Field `sram1` writer - "] -pub type SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram2` reader - "] pub type SRAM2_R = crate::BitReader; #[doc = "Field `sram2` writer - "] -pub type SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram3` reader - "] pub type SRAM3_R = crate::BitReader; #[doc = "Field `sram3` writer - "] -pub type SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram4` reader - "] pub type SRAM4_R = crate::BitReader; #[doc = "Field `sram4` writer - "] -pub type SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sram5` reader - "] pub type SRAM5_R = crate::BitReader; #[doc = "Field `sram5` writer - "] -pub type SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `xip` reader - "] pub type XIP_R = crate::BitReader; #[doc = "Field `xip` writer - "] -pub type XIP_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type XIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `vreg_and_chip_reset` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; #[doc = "Field `vreg_and_chip_reset` writer - "] -pub type VREG_AND_CHIP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type VREG_AND_CHIP_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sio` reader - "] pub type SIO_R = crate::BitReader; #[doc = "Field `sio` writer - "] -pub type SIO_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc0` reader - "] pub type PROC0_R = crate::BitReader; #[doc = "Field `proc0` writer - "] -pub type PROC0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PROC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `proc1` reader - "] pub type PROC1_R = crate::BitReader; #[doc = "Field `proc1` writer - "] -pub type PROC1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PROC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -193,128 +161,127 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn rosc(&mut self) -> ROSC_W<0> { + pub fn rosc(&mut self) -> ROSC_W { ROSC_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn xosc(&mut self) -> XOSC_W<1> { + pub fn xosc(&mut self) -> XOSC_W { XOSC_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn clocks(&mut self) -> CLOCKS_W<2> { + pub fn clocks(&mut self) -> CLOCKS_W { CLOCKS_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn resets(&mut self) -> RESETS_W<3> { + pub fn resets(&mut self) -> RESETS_W { RESETS_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn busfabric(&mut self) -> BUSFABRIC_W<4> { + pub fn busfabric(&mut self) -> BUSFABRIC_W { BUSFABRIC_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn rom(&mut self) -> ROM_W<5> { + pub fn rom(&mut self) -> ROM_W { ROM_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn sram0(&mut self) -> SRAM0_W<6> { + pub fn sram0(&mut self) -> SRAM0_W { SRAM0_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn sram1(&mut self) -> SRAM1_W<7> { + pub fn sram1(&mut self) -> SRAM1_W { SRAM1_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn sram2(&mut self) -> SRAM2_W<8> { + pub fn sram2(&mut self) -> SRAM2_W { SRAM2_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn sram3(&mut self) -> SRAM3_W<9> { + pub fn sram3(&mut self) -> SRAM3_W { SRAM3_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn sram4(&mut self) -> SRAM4_W<10> { + pub fn sram4(&mut self) -> SRAM4_W { SRAM4_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn sram5(&mut self) -> SRAM5_W<11> { + pub fn sram5(&mut self) -> SRAM5_W { SRAM5_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn xip(&mut self) -> XIP_W<12> { + pub fn xip(&mut self) -> XIP_W { XIP_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W<13> { + pub fn vreg_and_chip_reset(&mut self) -> VREG_AND_CHIP_RESET_W { VREG_AND_CHIP_RESET_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn sio(&mut self) -> SIO_W<14> { + pub fn sio(&mut self) -> SIO_W { SIO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn proc0(&mut self) -> PROC0_W<15> { + pub fn proc0(&mut self) -> PROC0_W { PROC0_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn proc1(&mut self) -> PROC1_W<16> { + pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [wdsel](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WDSEL_SPEC; impl crate::RegisterSpec for WDSEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wdsel::R](R) reader structure"] -impl crate::Readable for WDSEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wdsel::W](W) writer structure"] +#[doc = "`read()` method returns [`wdsel::R`](R) reader structure"] +impl crate::Readable for WDSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] impl crate::Writable for WDSEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm.rs b/src/pwm.rs index 7e9e8a447..f5a143b76 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -23,7 +23,16 @@ pub use self::ch::CH; #[doc = r"Cluster"] #[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] pub mod ch; -#[doc = "EN (rw) register accessor: an alias for `Reg`"] +#[doc = "EN (rw) register accessor: This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + +You can [`read`](crate::generic::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@en`] +module"] pub type EN = crate::Reg; #[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled @@ -31,19 +40,39 @@ pub type EN = crate::Reg; For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] pub mod en; -#[doc = "INTR (rw) register accessor: an alias for `Reg`"] +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/pwm/ch.rs b/src/pwm/ch.rs index a4edd9fdc..b295fba5b 100644 --- a/src/pwm/ch.rs +++ b/src/pwm/ch.rs @@ -14,25 +14,52 @@ pub struct CH { #[doc = "0x10 - Counter wrap value"] pub top: TOP, } -#[doc = "CC (rw) register accessor: an alias for `Reg`"] +#[doc = "CC (rw) register accessor: Counter compare values + +You can [`read`](crate::generic::Reg::read) this register and get [`cc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cc`] +module"] pub type CC = crate::Reg; #[doc = "Counter compare values"] pub mod cc; -#[doc = "CSR (rw) register accessor: an alias for `Reg`"] +#[doc = "CSR (rw) register accessor: Control and status register + +You can [`read`](crate::generic::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@csr`] +module"] pub type CSR = crate::Reg; #[doc = "Control and status register"] pub mod csr; -#[doc = "CTR (rw) register accessor: an alias for `Reg`"] +#[doc = "CTR (rw) register accessor: Direct access to the PWM counter + +You can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr`] +module"] pub type CTR = crate::Reg; #[doc = "Direct access to the PWM counter"] pub mod ctr; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] pub mod div; -#[doc = "TOP (rw) register accessor: an alias for `Reg`"] +#[doc = "TOP (rw) register accessor: Counter wrap value + +You can [`read`](crate::generic::Reg::read) this register and get [`top::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@top`] +module"] pub type TOP = crate::Reg; #[doc = "Counter wrap value"] pub mod top; diff --git a/src/pwm/ch/cc.rs b/src/pwm/ch/cc.rs index 93dd5a514..24ed81477 100644 --- a/src/pwm/ch/cc.rs +++ b/src/pwm/ch/cc.rs @@ -1,47 +1,15 @@ #[doc = "Register `CC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `A` reader - "] pub type A_R = crate::FieldReader; #[doc = "Field `A` writer - "] -pub type A_W<'a, const O: u8> = crate::FieldWriter<'a, CC_SPEC, 16, O, u16>; +pub type A_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `B` reader - "] pub type B_R = crate::FieldReader; #[doc = "Field `B` writer - "] -pub type B_W<'a, const O: u8> = crate::FieldWriter<'a, CC_SPEC, 16, O, u16>; +pub type B_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn a(&mut self) -> A_W<0> { + pub fn a(&mut self) -> A_W { A_W::new(self) } #[doc = "Bits 16:31"] #[inline(always)] #[must_use] - pub fn b(&mut self) -> B_W<16> { + pub fn b(&mut self) -> B_W { B_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Counter compare values -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [cc](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`cc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CC_SPEC; impl crate::RegisterSpec for CC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cc::R](R) reader structure"] -impl crate::Readable for CC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +#[doc = "`read()` method returns [`cc::R`](R) reader structure"] +impl crate::Readable for CC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cc::W`](W) writer structure"] impl crate::Writable for CC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs index 446f90921..1deef1455 100644 --- a/src/pwm/ch/csr.rs +++ b/src/pwm/ch/csr.rs @@ -1,55 +1,23 @@ #[doc = "Register `CSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - Enable the PWM channel."] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Enable the PWM channel."] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PH_CORRECT` reader - 1: Enable phase-correct modulation. 0: Trailing-edge"] pub type PH_CORRECT_R = crate::BitReader; #[doc = "Field `PH_CORRECT` writer - 1: Enable phase-correct modulation. 0: Trailing-edge"] -pub type PH_CORRECT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type PH_CORRECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `A_INV` reader - Invert output A"] pub type A_INV_R = crate::BitReader; #[doc = "Field `A_INV` writer - Invert output A"] -pub type A_INV_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type A_INV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B_INV` reader - Invert output B"] pub type B_INV_R = crate::BitReader; #[doc = "Field `B_INV` writer - Invert output B"] -pub type B_INV_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type B_INV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIVMODE` reader - "] pub type DIVMODE_R = crate::FieldReader; #[doc = " @@ -79,7 +47,7 @@ impl crate::FieldSpec for DIVMODE_A { impl DIVMODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DIVMODE_A { + pub const fn variant(&self) -> DIVMODE_A { match self.bits { 0 => DIVMODE_A::DIV, 1 => DIVMODE_A::LEVEL, @@ -88,48 +56,52 @@ impl DIVMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DIV`"] + #[doc = "Free-running counting at rate dictated by fractional divider"] #[inline(always)] pub fn is_div(&self) -> bool { *self == DIVMODE_A::DIV } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Fractional divider operation is gated by the PWM B pin."] #[inline(always)] pub fn is_level(&self) -> bool { *self == DIVMODE_A::LEVEL } - #[doc = "Checks if the value of the field is `RISE`"] + #[doc = "Counter advances with each rising edge of the PWM B pin."] #[inline(always)] pub fn is_rise(&self) -> bool { *self == DIVMODE_A::RISE } - #[doc = "Checks if the value of the field is `FALL`"] + #[doc = "Counter advances with each falling edge of the PWM B pin."] #[inline(always)] pub fn is_fall(&self) -> bool { *self == DIVMODE_A::FALL } } #[doc = "Field `DIVMODE` writer - "] -pub type DIVMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CSR_SPEC, 2, O, DIVMODE_A>; -impl<'a, const O: u8> DIVMODE_W<'a, O> { +pub type DIVMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DIVMODE_A>; +impl<'a, REG, const O: u8> DIVMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Free-running counting at rate dictated by fractional divider"] #[inline(always)] - pub fn div(self) -> &'a mut W { + pub fn div(self) -> &'a mut crate::W { self.variant(DIVMODE_A::DIV) } #[doc = "Fractional divider operation is gated by the PWM B pin."] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DIVMODE_A::LEVEL) } #[doc = "Counter advances with each rising edge of the PWM B pin."] #[inline(always)] - pub fn rise(self) -> &'a mut W { + pub fn rise(self) -> &'a mut crate::W { self.variant(DIVMODE_A::RISE) } #[doc = "Counter advances with each falling edge of the PWM B pin."] #[inline(always)] - pub fn fall(self) -> &'a mut W { + pub fn fall(self) -> &'a mut crate::W { self.variant(DIVMODE_A::FALL) } } @@ -138,7 +110,7 @@ impl<'a, const O: u8> DIVMODE_W<'a, O> { pub type PH_RET_R = crate::BitReader; #[doc = "Field `PH_RET` writer - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] -pub type PH_RET_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type PH_RET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PH_ADV` reader - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] @@ -146,7 +118,7 @@ pub type PH_ADV_R = crate::BitReader; #[doc = "Field `PH_ADV` writer - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] -pub type PH_ADV_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type PH_ADV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the PWM channel."] #[inline(always)] @@ -191,38 +163,38 @@ impl W { #[doc = "Bit 0 - Enable the PWM channel."] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"] #[inline(always)] #[must_use] - pub fn ph_correct(&mut self) -> PH_CORRECT_W<1> { + pub fn ph_correct(&mut self) -> PH_CORRECT_W { PH_CORRECT_W::new(self) } #[doc = "Bit 2 - Invert output A"] #[inline(always)] #[must_use] - pub fn a_inv(&mut self) -> A_INV_W<2> { + pub fn a_inv(&mut self) -> A_INV_W { A_INV_W::new(self) } #[doc = "Bit 3 - Invert output B"] #[inline(always)] #[must_use] - pub fn b_inv(&mut self) -> B_INV_W<3> { + pub fn b_inv(&mut self) -> B_INV_W { B_INV_W::new(self) } #[doc = "Bits 4:5"] #[inline(always)] #[must_use] - pub fn divmode(&mut self) -> DIVMODE_W<4> { + pub fn divmode(&mut self) -> DIVMODE_W { DIVMODE_W::new(self) } #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] #[inline(always)] #[must_use] - pub fn ph_ret(&mut self) -> PH_RET_W<6> { + pub fn ph_ret(&mut self) -> PH_RET_W { PH_RET_W::new(self) } #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. @@ -230,32 +202,31 @@ impl W { at less than full speed (div_int + div_frac / 16 > 1)"] #[inline(always)] #[must_use] - pub fn ph_adv(&mut self) -> PH_ADV_W<7> { + pub fn ph_adv(&mut self) -> PH_ADV_W { PH_ADV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control and status register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [csr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [csr::R](R) reader structure"] -impl crate::Readable for CSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] impl crate::Writable for CSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/ch/ctr.rs b/src/pwm/ch/ctr.rs index ca13f0633..a903ffa9e 100644 --- a/src/pwm/ch/ctr.rs +++ b/src/pwm/ch/ctr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTR` reader - "] pub type CTR_R = crate::FieldReader; #[doc = "Field `CTR` writer - "] -pub type CTR_W<'a, const O: u8> = crate::FieldWriter<'a, CTR_SPEC, 16, O, u16>; +pub type CTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn ctr(&mut self) -> CTR_W<0> { + pub fn ctr(&mut self) -> CTR_W { CTR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Direct access to the PWM counter -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTR_SPEC; impl crate::RegisterSpec for CTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctr::R](R) reader structure"] -impl crate::Readable for CTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctr::W](W) writer structure"] +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] impl crate::Writable for CTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs index 9c43a96b7..b35210714 100644 --- a/src/pwm/ch/div.rs +++ b/src/pwm/ch/div.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRAC` reader - "] pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - "] -pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 4, O>; +pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `INT` reader - "] pub type INT_R = crate::FieldReader; #[doc = "Field `INT` writer - "] -pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 8, O>; +pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:3"] #[inline(always)] @@ -58,19 +26,23 @@ impl W { #[doc = "Bits 0:3"] #[inline(always)] #[must_use] - pub fn frac(&mut self) -> FRAC_W<0> { + pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self) } #[doc = "Bits 4:11"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W<4> { + pub fn int(&mut self) -> INT_W { INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -78,20 +50,15 @@ impl W { Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/ch/top.rs b/src/pwm/ch/top.rs index 6bbad2f31..09d86775d 100644 --- a/src/pwm/ch/top.rs +++ b/src/pwm/ch/top.rs @@ -1,43 +1,11 @@ #[doc = "Register `TOP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TOP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOP` reader - "] pub type TOP_R = crate::FieldReader; #[doc = "Field `TOP` writer - "] -pub type TOP_W<'a, const O: u8> = crate::FieldWriter<'a, TOP_SPEC, 16, O, u16>; +pub type TOP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn top(&mut self) -> TOP_W<0> { + pub fn top(&mut self) -> TOP_W { TOP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Counter wrap value -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [top](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`top::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TOP_SPEC; impl crate::RegisterSpec for TOP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [top::R](R) reader structure"] -impl crate::Readable for TOP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [top::W](W) writer structure"] +#[doc = "`read()` method returns [`top::R`](R) reader structure"] +impl crate::Readable for TOP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`top::W`](W) writer structure"] impl crate::Writable for TOP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/en.rs b/src/pwm/en.rs index 8063bd347..2ce88f862 100644 --- a/src/pwm/en.rs +++ b/src/pwm/en.rs @@ -1,71 +1,39 @@ #[doc = "Register `EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH0` writer - "] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` reader - "] pub type CH1_R = crate::BitReader; #[doc = "Field `CH1` writer - "] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH2` reader - "] pub type CH2_R = crate::BitReader; #[doc = "Field `CH2` writer - "] -pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH3` reader - "] pub type CH3_R = crate::BitReader; #[doc = "Field `CH3` writer - "] -pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH4` reader - "] pub type CH4_R = crate::BitReader; #[doc = "Field `CH4` writer - "] -pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH5` reader - "] pub type CH5_R = crate::BitReader; #[doc = "Field `CH5` writer - "] -pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH6` reader - "] pub type CH6_R = crate::BitReader; #[doc = "Field `CH6` writer - "] -pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH7` reader - "] pub type CH7_R = crate::BitReader; #[doc = "Field `CH7` writer - "] -pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, EN_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -112,55 +80,59 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -170,20 +142,15 @@ impl W { For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [en](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EN_SPEC; impl crate::RegisterSpec for EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [en::R](R) reader structure"] -impl crate::Readable for EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [en::W](W) writer structure"] +#[doc = "`read()` method returns [`en::R`](R) reader structure"] +impl crate::Readable for EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`en::W`](W) writer structure"] impl crate::Writable for EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/inte.rs b/src/pwm/inte.rs index d14fe2425..5aab76b6f 100644 --- a/src/pwm/inte.rs +++ b/src/pwm/inte.rs @@ -1,71 +1,39 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH0` writer - "] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` reader - "] pub type CH1_R = crate::BitReader; #[doc = "Field `CH1` writer - "] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH2` reader - "] pub type CH2_R = crate::BitReader; #[doc = "Field `CH2` writer - "] -pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH3` reader - "] pub type CH3_R = crate::BitReader; #[doc = "Field `CH3` writer - "] -pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH4` reader - "] pub type CH4_R = crate::BitReader; #[doc = "Field `CH4` writer - "] -pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH5` reader - "] pub type CH5_R = crate::BitReader; #[doc = "Field `CH5` writer - "] -pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH6` reader - "] pub type CH6_R = crate::BitReader; #[doc = "Field `CH6` writer - "] -pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH7` reader - "] pub type CH7_R = crate::BitReader; #[doc = "Field `CH7` writer - "] -pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -112,74 +80,73 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/intf.rs b/src/pwm/intf.rs index 260e08ee5..93970d150 100644 --- a/src/pwm/intf.rs +++ b/src/pwm/intf.rs @@ -1,71 +1,39 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH0` writer - "] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` reader - "] pub type CH1_R = crate::BitReader; #[doc = "Field `CH1` writer - "] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH2` reader - "] pub type CH2_R = crate::BitReader; #[doc = "Field `CH2` writer - "] -pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH3` reader - "] pub type CH3_R = crate::BitReader; #[doc = "Field `CH3` writer - "] -pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH4` reader - "] pub type CH4_R = crate::BitReader; #[doc = "Field `CH4` writer - "] -pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH5` reader - "] pub type CH5_R = crate::BitReader; #[doc = "Field `CH5` writer - "] -pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH6` reader - "] pub type CH6_R = crate::BitReader; #[doc = "Field `CH6` writer - "] -pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH7` reader - "] pub type CH7_R = crate::BitReader; #[doc = "Field `CH7` writer - "] -pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -112,74 +80,73 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/pwm/intr.rs b/src/pwm/intr.rs index 5f2bda09f..0f5ccf8ab 100644 --- a/src/pwm/intr.rs +++ b/src/pwm/intr.rs @@ -1,71 +1,39 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH0` writer - "] -pub type CH0_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH1` reader - "] pub type CH1_R = crate::BitReader; #[doc = "Field `CH1` writer - "] -pub type CH1_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH2` reader - "] pub type CH2_R = crate::BitReader; #[doc = "Field `CH2` writer - "] -pub type CH2_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH3` reader - "] pub type CH3_R = crate::BitReader; #[doc = "Field `CH3` writer - "] -pub type CH3_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH4` reader - "] pub type CH4_R = crate::BitReader; #[doc = "Field `CH4` writer - "] -pub type CH4_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH5` reader - "] pub type CH5_R = crate::BitReader; #[doc = "Field `CH5` writer - "] -pub type CH5_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH6` reader - "] pub type CH6_R = crate::BitReader; #[doc = "Field `CH6` writer - "] -pub type CH6_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CH7` reader - "] pub type CH7_R = crate::BitReader; #[doc = "Field `CH7` writer - "] -pub type CH7_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -112,74 +80,73 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intr::W](W) writer structure"] +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/src/pwm/ints.rs b/src/pwm/ints.rs index 5732ebdc3..f7d6696e3 100644 --- a/src/pwm/ints.rs +++ b/src/pwm/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH1` reader - "] @@ -73,17 +60,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/resets.rs b/src/resets.rs index 1936513b8..9bc756d20 100644 --- a/src/resets.rs +++ b/src/resets.rs @@ -8,15 +8,30 @@ pub struct RegisterBlock { #[doc = "0x08 - Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed."] pub reset_done: RESET_DONE, } -#[doc = "RESET (rw) register accessor: an alias for `Reg`"] +#[doc = "RESET (rw) register accessor: Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. + +You can [`read`](crate::generic::Reg::read) this register and get [`reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reset`] +module"] pub type RESET = crate::Reg; #[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted."] pub mod reset; -#[doc = "WDSEL (rw) register accessor: an alias for `Reg`"] +#[doc = "WDSEL (rw) register accessor: Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. + +You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdsel`] +module"] pub type WDSEL = crate::Reg; #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires."] pub mod wdsel; -#[doc = "RESET_DONE (r) register accessor: an alias for `Reg`"] +#[doc = "RESET_DONE (r) register accessor: Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. + +You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reset_done`] +module"] pub type RESET_DONE = crate::Reg; #[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed."] pub mod reset_done; diff --git a/src/resets/reset.rs b/src/resets/reset.rs index 461ddac44..96c99f314 100644 --- a/src/resets/reset.rs +++ b/src/resets/reset.rs @@ -1,139 +1,107 @@ #[doc = "Register `RESET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `adc` reader - "] pub type ADC_R = crate::BitReader; #[doc = "Field `adc` writer - "] -pub type ADC_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `busctrl` reader - "] pub type BUSCTRL_R = crate::BitReader; #[doc = "Field `busctrl` writer - "] -pub type BUSCTRL_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type BUSCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `dma` reader - "] pub type DMA_R = crate::BitReader; #[doc = "Field `dma` writer - "] -pub type DMA_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `i2c0` reader - "] pub type I2C0_R = crate::BitReader; #[doc = "Field `i2c0` writer - "] -pub type I2C0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type I2C0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `i2c1` reader - "] pub type I2C1_R = crate::BitReader; #[doc = "Field `i2c1` writer - "] -pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type I2C1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `io_bank0` reader - "] pub type IO_BANK0_R = crate::BitReader; #[doc = "Field `io_bank0` writer - "] -pub type IO_BANK0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type IO_BANK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `io_qspi` reader - "] pub type IO_QSPI_R = crate::BitReader; #[doc = "Field `io_qspi` writer - "] -pub type IO_QSPI_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type IO_QSPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `jtag` reader - "] pub type JTAG_R = crate::BitReader; #[doc = "Field `jtag` writer - "] -pub type JTAG_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type JTAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pads_bank0` reader - "] pub type PADS_BANK0_R = crate::BitReader; #[doc = "Field `pads_bank0` writer - "] -pub type PADS_BANK0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PADS_BANK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pads_qspi` reader - "] pub type PADS_QSPI_R = crate::BitReader; #[doc = "Field `pads_qspi` writer - "] -pub type PADS_QSPI_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PADS_QSPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pio0` reader - "] pub type PIO0_R = crate::BitReader; #[doc = "Field `pio0` writer - "] -pub type PIO0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pio1` reader - "] pub type PIO1_R = crate::BitReader; #[doc = "Field `pio1` writer - "] -pub type PIO1_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pll_sys` reader - "] pub type PLL_SYS_R = crate::BitReader; #[doc = "Field `pll_sys` writer - "] -pub type PLL_SYS_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PLL_SYS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pll_usb` reader - "] pub type PLL_USB_R = crate::BitReader; #[doc = "Field `pll_usb` writer - "] -pub type PLL_USB_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PLL_USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pwm` reader - "] pub type PWM_R = crate::BitReader; #[doc = "Field `pwm` writer - "] -pub type PWM_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type PWM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `rtc` reader - "] pub type RTC_R = crate::BitReader; #[doc = "Field `rtc` writer - "] -pub type RTC_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `spi0` reader - "] pub type SPI0_R = crate::BitReader; #[doc = "Field `spi0` writer - "] -pub type SPI0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `spi1` reader - "] pub type SPI1_R = crate::BitReader; #[doc = "Field `spi1` writer - "] -pub type SPI1_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `syscfg` reader - "] pub type SYSCFG_R = crate::BitReader; #[doc = "Field `syscfg` writer - "] -pub type SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type SYSCFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sysinfo` reader - "] pub type SYSINFO_R = crate::BitReader; #[doc = "Field `sysinfo` writer - "] -pub type SYSINFO_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type SYSINFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `tbman` reader - "] pub type TBMAN_R = crate::BitReader; #[doc = "Field `tbman` writer - "] -pub type TBMAN_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type TBMAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `timer` reader - "] pub type TIMER_R = crate::BitReader; #[doc = "Field `timer` writer - "] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `uart0` reader - "] pub type UART0_R = crate::BitReader; #[doc = "Field `uart0` writer - "] -pub type UART0_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `uart1` reader - "] pub type UART1_R = crate::BitReader; #[doc = "Field `uart1` writer - "] -pub type UART1_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `usbctrl` reader - "] pub type USBCTRL_R = crate::BitReader; #[doc = "Field `usbctrl` writer - "] -pub type USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, RESET_SPEC, O>; +pub type USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -265,176 +233,175 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn adc(&mut self) -> ADC_W<0> { + pub fn adc(&mut self) -> ADC_W { ADC_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn busctrl(&mut self) -> BUSCTRL_W<1> { + pub fn busctrl(&mut self) -> BUSCTRL_W { BUSCTRL_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn dma(&mut self) -> DMA_W<2> { + pub fn dma(&mut self) -> DMA_W { DMA_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn i2c0(&mut self) -> I2C0_W<3> { + pub fn i2c0(&mut self) -> I2C0_W { I2C0_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn i2c1(&mut self) -> I2C1_W<4> { + pub fn i2c1(&mut self) -> I2C1_W { I2C1_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn io_bank0(&mut self) -> IO_BANK0_W<5> { + pub fn io_bank0(&mut self) -> IO_BANK0_W { IO_BANK0_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn io_qspi(&mut self) -> IO_QSPI_W<6> { + pub fn io_qspi(&mut self) -> IO_QSPI_W { IO_QSPI_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn jtag(&mut self) -> JTAG_W<7> { + pub fn jtag(&mut self) -> JTAG_W { JTAG_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn pads_bank0(&mut self) -> PADS_BANK0_W<8> { + pub fn pads_bank0(&mut self) -> PADS_BANK0_W { PADS_BANK0_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn pads_qspi(&mut self) -> PADS_QSPI_W<9> { + pub fn pads_qspi(&mut self) -> PADS_QSPI_W { PADS_QSPI_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn pio0(&mut self) -> PIO0_W<10> { + pub fn pio0(&mut self) -> PIO0_W { PIO0_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn pio1(&mut self) -> PIO1_W<11> { + pub fn pio1(&mut self) -> PIO1_W { PIO1_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn pll_sys(&mut self) -> PLL_SYS_W<12> { + pub fn pll_sys(&mut self) -> PLL_SYS_W { PLL_SYS_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn pll_usb(&mut self) -> PLL_USB_W<13> { + pub fn pll_usb(&mut self) -> PLL_USB_W { PLL_USB_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn pwm(&mut self) -> PWM_W<14> { + pub fn pwm(&mut self) -> PWM_W { PWM_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn rtc(&mut self) -> RTC_W<15> { + pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn spi0(&mut self) -> SPI0_W<16> { + pub fn spi0(&mut self) -> SPI0_W { SPI0_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn spi1(&mut self) -> SPI1_W<17> { + pub fn spi1(&mut self) -> SPI1_W { SPI1_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn syscfg(&mut self) -> SYSCFG_W<18> { + pub fn syscfg(&mut self) -> SYSCFG_W { SYSCFG_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn sysinfo(&mut self) -> SYSINFO_W<19> { + pub fn sysinfo(&mut self) -> SYSINFO_W { SYSINFO_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn tbman(&mut self) -> TBMAN_W<20> { + pub fn tbman(&mut self) -> TBMAN_W { TBMAN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<21> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn uart0(&mut self) -> UART0_W<22> { + pub fn uart0(&mut self) -> UART0_W { UART0_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn uart1(&mut self) -> UART1_W<23> { + pub fn uart1(&mut self) -> UART1_W { UART1_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn usbctrl(&mut self) -> USBCTRL_W<24> { + pub fn usbctrl(&mut self) -> USBCTRL_W { USBCTRL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [reset](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESET_SPEC; impl crate::RegisterSpec for RESET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [reset::R](R) reader structure"] -impl crate::Readable for RESET_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [reset::W](W) writer structure"] +#[doc = "`read()` method returns [`reset::R`](R) reader structure"] +impl crate::Readable for RESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset::W`](W) writer structure"] impl crate::Writable for RESET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/resets/reset_done.rs b/src/resets/reset_done.rs index 684708582..75bcc36f3 100644 --- a/src/resets/reset_done.rs +++ b/src/resets/reset_done.rs @@ -1,18 +1,5 @@ #[doc = "Register `RESET_DONE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `adc` reader - "] pub type ADC_R = crate::BitReader; #[doc = "Field `busctrl` reader - "] @@ -192,17 +179,13 @@ impl R { } #[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [reset_done](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESET_DONE_SPEC; impl crate::RegisterSpec for RESET_DONE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [reset_done::R](R) reader structure"] -impl crate::Readable for RESET_DONE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`reset_done::R`](R) reader structure"] +impl crate::Readable for RESET_DONE_SPEC {} #[doc = "`reset()` method sets RESET_DONE to value 0"] impl crate::Resettable for RESET_DONE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs index e3f6c9a8c..e1f649d4a 100644 --- a/src/resets/wdsel.rs +++ b/src/resets/wdsel.rs @@ -1,139 +1,107 @@ #[doc = "Register `WDSEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WDSEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `adc` reader - "] pub type ADC_R = crate::BitReader; #[doc = "Field `adc` writer - "] -pub type ADC_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type ADC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `busctrl` reader - "] pub type BUSCTRL_R = crate::BitReader; #[doc = "Field `busctrl` writer - "] -pub type BUSCTRL_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type BUSCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `dma` reader - "] pub type DMA_R = crate::BitReader; #[doc = "Field `dma` writer - "] -pub type DMA_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `i2c0` reader - "] pub type I2C0_R = crate::BitReader; #[doc = "Field `i2c0` writer - "] -pub type I2C0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type I2C0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `i2c1` reader - "] pub type I2C1_R = crate::BitReader; #[doc = "Field `i2c1` writer - "] -pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type I2C1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `io_bank0` reader - "] pub type IO_BANK0_R = crate::BitReader; #[doc = "Field `io_bank0` writer - "] -pub type IO_BANK0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type IO_BANK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `io_qspi` reader - "] pub type IO_QSPI_R = crate::BitReader; #[doc = "Field `io_qspi` writer - "] -pub type IO_QSPI_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type IO_QSPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `jtag` reader - "] pub type JTAG_R = crate::BitReader; #[doc = "Field `jtag` writer - "] -pub type JTAG_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type JTAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pads_bank0` reader - "] pub type PADS_BANK0_R = crate::BitReader; #[doc = "Field `pads_bank0` writer - "] -pub type PADS_BANK0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PADS_BANK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pads_qspi` reader - "] pub type PADS_QSPI_R = crate::BitReader; #[doc = "Field `pads_qspi` writer - "] -pub type PADS_QSPI_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PADS_QSPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pio0` reader - "] pub type PIO0_R = crate::BitReader; #[doc = "Field `pio0` writer - "] -pub type PIO0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pio1` reader - "] pub type PIO1_R = crate::BitReader; #[doc = "Field `pio1` writer - "] -pub type PIO1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pll_sys` reader - "] pub type PLL_SYS_R = crate::BitReader; #[doc = "Field `pll_sys` writer - "] -pub type PLL_SYS_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PLL_SYS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pll_usb` reader - "] pub type PLL_USB_R = crate::BitReader; #[doc = "Field `pll_usb` writer - "] -pub type PLL_USB_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PLL_USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `pwm` reader - "] pub type PWM_R = crate::BitReader; #[doc = "Field `pwm` writer - "] -pub type PWM_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type PWM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `rtc` reader - "] pub type RTC_R = crate::BitReader; #[doc = "Field `rtc` writer - "] -pub type RTC_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `spi0` reader - "] pub type SPI0_R = crate::BitReader; #[doc = "Field `spi0` writer - "] -pub type SPI0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SPI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `spi1` reader - "] pub type SPI1_R = crate::BitReader; #[doc = "Field `spi1` writer - "] -pub type SPI1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SPI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `syscfg` reader - "] pub type SYSCFG_R = crate::BitReader; #[doc = "Field `syscfg` writer - "] -pub type SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SYSCFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `sysinfo` reader - "] pub type SYSINFO_R = crate::BitReader; #[doc = "Field `sysinfo` writer - "] -pub type SYSINFO_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type SYSINFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `tbman` reader - "] pub type TBMAN_R = crate::BitReader; #[doc = "Field `tbman` writer - "] -pub type TBMAN_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type TBMAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `timer` reader - "] pub type TIMER_R = crate::BitReader; #[doc = "Field `timer` writer - "] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `uart0` reader - "] pub type UART0_R = crate::BitReader; #[doc = "Field `uart0` writer - "] -pub type UART0_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type UART0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `uart1` reader - "] pub type UART1_R = crate::BitReader; #[doc = "Field `uart1` writer - "] -pub type UART1_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type UART1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `usbctrl` reader - "] pub type USBCTRL_R = crate::BitReader; #[doc = "Field `usbctrl` writer - "] -pub type USBCTRL_W<'a, const O: u8> = crate::BitWriter<'a, WDSEL_SPEC, O>; +pub type USBCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -265,176 +233,175 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn adc(&mut self) -> ADC_W<0> { + pub fn adc(&mut self) -> ADC_W { ADC_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn busctrl(&mut self) -> BUSCTRL_W<1> { + pub fn busctrl(&mut self) -> BUSCTRL_W { BUSCTRL_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn dma(&mut self) -> DMA_W<2> { + pub fn dma(&mut self) -> DMA_W { DMA_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn i2c0(&mut self) -> I2C0_W<3> { + pub fn i2c0(&mut self) -> I2C0_W { I2C0_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn i2c1(&mut self) -> I2C1_W<4> { + pub fn i2c1(&mut self) -> I2C1_W { I2C1_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn io_bank0(&mut self) -> IO_BANK0_W<5> { + pub fn io_bank0(&mut self) -> IO_BANK0_W { IO_BANK0_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn io_qspi(&mut self) -> IO_QSPI_W<6> { + pub fn io_qspi(&mut self) -> IO_QSPI_W { IO_QSPI_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn jtag(&mut self) -> JTAG_W<7> { + pub fn jtag(&mut self) -> JTAG_W { JTAG_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn pads_bank0(&mut self) -> PADS_BANK0_W<8> { + pub fn pads_bank0(&mut self) -> PADS_BANK0_W { PADS_BANK0_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn pads_qspi(&mut self) -> PADS_QSPI_W<9> { + pub fn pads_qspi(&mut self) -> PADS_QSPI_W { PADS_QSPI_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn pio0(&mut self) -> PIO0_W<10> { + pub fn pio0(&mut self) -> PIO0_W { PIO0_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn pio1(&mut self) -> PIO1_W<11> { + pub fn pio1(&mut self) -> PIO1_W { PIO1_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn pll_sys(&mut self) -> PLL_SYS_W<12> { + pub fn pll_sys(&mut self) -> PLL_SYS_W { PLL_SYS_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn pll_usb(&mut self) -> PLL_USB_W<13> { + pub fn pll_usb(&mut self) -> PLL_USB_W { PLL_USB_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn pwm(&mut self) -> PWM_W<14> { + pub fn pwm(&mut self) -> PWM_W { PWM_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn rtc(&mut self) -> RTC_W<15> { + pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn spi0(&mut self) -> SPI0_W<16> { + pub fn spi0(&mut self) -> SPI0_W { SPI0_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn spi1(&mut self) -> SPI1_W<17> { + pub fn spi1(&mut self) -> SPI1_W { SPI1_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn syscfg(&mut self) -> SYSCFG_W<18> { + pub fn syscfg(&mut self) -> SYSCFG_W { SYSCFG_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn sysinfo(&mut self) -> SYSINFO_W<19> { + pub fn sysinfo(&mut self) -> SYSINFO_W { SYSINFO_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn tbman(&mut self) -> TBMAN_W<20> { + pub fn tbman(&mut self) -> TBMAN_W { TBMAN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<21> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn uart0(&mut self) -> UART0_W<22> { + pub fn uart0(&mut self) -> UART0_W { UART0_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn uart1(&mut self) -> UART1_W<23> { + pub fn uart1(&mut self) -> UART1_W { UART1_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn usbctrl(&mut self) -> USBCTRL_W<24> { + pub fn usbctrl(&mut self) -> USBCTRL_W { USBCTRL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [wdsel](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WDSEL_SPEC; impl crate::RegisterSpec for WDSEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wdsel::R](R) reader structure"] -impl crate::Readable for WDSEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wdsel::W](W) writer structure"] +#[doc = "`read()` method returns [`wdsel::R`](R) reader structure"] +impl crate::Readable for WDSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] impl crate::Writable for WDSEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc.rs b/src/rosc.rs index 539af587a..fb5f74a76 100644 --- a/src/rosc.rs +++ b/src/rosc.rs @@ -28,11 +28,27 @@ pub struct RegisterBlock { #[doc = "0x1c - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] pub randombit: RANDOMBIT, } -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: Ring Oscillator control + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "Ring Oscillator control"] pub mod ctrl; -#[doc = "FREQA (rw) register accessor: an alias for `Reg`"] +#[doc = "FREQA (rw) register accessor: The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + +You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@freqa`] +module"] pub type FREQA = crate::Reg; #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set @@ -42,11 +58,25 @@ pub type FREQA = crate::Reg; 2 bits set triples drive strength 3 bits set quadruples drive strength"] pub mod freqa; -#[doc = "FREQB (rw) register accessor: an alias for `Reg`"] +#[doc = "FREQB (rw) register accessor: For a detailed description see freqa register + +You can [`read`](crate::generic::Reg::read) this register and get [`freqb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@freqb`] +module"] pub type FREQB = crate::Reg; #[doc = "For a detailed description see freqa register"] pub mod freqb; -#[doc = "DORMANT (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT (rw) register accessor: Ring Oscillator pause control + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant`] +module"] pub type DORMANT = crate::Reg; #[doc = "Ring Oscillator pause control This is used to save power by pausing the ROSC @@ -54,19 +84,39 @@ pub type DORMANT = crate::Reg; An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] pub mod dormant; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Controls the output divider + +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Controls the output divider"] pub mod div; -#[doc = "PHASE (rw) register accessor: an alias for `Reg`"] +#[doc = "PHASE (rw) register accessor: Controls the phase shifted output + +You can [`read`](crate::generic::Reg::read) this register and get [`phase::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@phase`] +module"] pub type PHASE = crate::Reg; #[doc = "Controls the phase shifted output"] pub mod phase; -#[doc = "RANDOMBIT (r) register accessor: an alias for `Reg`"] +#[doc = "RANDOMBIT (r) register accessor: This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + +You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randombit`] +module"] pub type RANDOMBIT = crate::Reg; #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] pub mod randombit; -#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +#[doc = "STATUS (r) register accessor: Ring Oscillator Status + +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@status`] +module"] pub type STATUS = crate::Reg; #[doc = "Ring Oscillator Status"] pub mod status; diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs index f213ffcd1..6f4934d07 100644 --- a/src/rosc/ctrl.rs +++ b/src/rosc/ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 @@ -77,7 +45,7 @@ impl crate::FieldSpec for FREQ_RANGE_A { impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 4004 => Some(FREQ_RANGE_A::LOW), 4005 => Some(FREQ_RANGE_A::MEDIUM), @@ -86,22 +54,22 @@ impl FREQ_RANGE_R { _ => None, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "`111110100100`"] #[inline(always)] pub fn is_low(&self) -> bool { *self == FREQ_RANGE_A::LOW } - #[doc = "Checks if the value of the field is `MEDIUM`"] + #[doc = "`111110100101`"] #[inline(always)] pub fn is_medium(&self) -> bool { *self == FREQ_RANGE_A::MEDIUM } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "`111110100111`"] #[inline(always)] pub fn is_high(&self) -> bool { *self == FREQ_RANGE_A::HIGH } - #[doc = "Checks if the value of the field is `TOOHIGH`"] + #[doc = "`111110100110`"] #[inline(always)] pub fn is_toohigh(&self) -> bool { *self == FREQ_RANGE_A::TOOHIGH @@ -115,26 +83,30 @@ impl FREQ_RANGE_R { The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] -pub type FREQ_RANGE_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 12, O, FREQ_RANGE_A>; -impl<'a, const O: u8> FREQ_RANGE_W<'a, O> { +pub type FREQ_RANGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, FREQ_RANGE_A>; +impl<'a, REG, const O: u8> FREQ_RANGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`111110100100`"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::LOW) } #[doc = "`111110100101`"] #[inline(always)] - pub fn medium(self) -> &'a mut W { + pub fn medium(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::MEDIUM) } #[doc = "`111110100111`"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::HIGH) } #[doc = "`111110100110`"] #[inline(always)] - pub fn toohigh(self) -> &'a mut W { + pub fn toohigh(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::TOOHIGH) } } @@ -167,19 +139,19 @@ impl crate::FieldSpec for ENABLE_A { impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 3358 => Some(ENABLE_A::DISABLE), 4011 => Some(ENABLE_A::ENABLE), _ => None, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "`110100011110`"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == ENABLE_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "`111110101011`"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == ENABLE_A::ENABLE @@ -188,16 +160,20 @@ impl ENABLE_R { #[doc = "Field `ENABLE` writer - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] -pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 12, O, ENABLE_A>; -impl<'a, const O: u8> ENABLE_W<'a, O> { +pub type ENABLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, ENABLE_A>; +impl<'a, REG, const O: u8> ENABLE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`110100011110`"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(ENABLE_A::DISABLE) } #[doc = "`111110101011`"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(ENABLE_A::ENABLE) } } @@ -233,7 +209,7 @@ impl W { Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] #[inline(always)] #[must_use] - pub fn freq_range(&mut self) -> FREQ_RANGE_W<0> { + pub fn freq_range(&mut self) -> FREQ_RANGE_W { FREQ_RANGE_W::new(self) } #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE @@ -241,32 +217,31 @@ impl W { The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<12> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Ring Oscillator control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/div.rs b/src/rosc/div.rs index efca482d4..16c027594 100644 --- a/src/rosc/div.rs +++ b/src/rosc/div.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIV` reader - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div @@ -65,13 +33,13 @@ impl crate::FieldSpec for DIV_A { impl DIV_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 2720 => Some(DIV_A::PASS), _ => None, } } - #[doc = "Checks if the value of the field is `PASS`"] + #[doc = "`101010100000`"] #[inline(always)] pub fn is_pass(&self) -> bool { *self == DIV_A::PASS @@ -82,11 +50,15 @@ impl DIV_R { div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] -pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 12, O, DIV_A>; -impl<'a, const O: u8> DIV_W<'a, O> { +pub type DIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, DIV_A>; +impl<'a, REG, const O: u8> DIV_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`101010100000`"] #[inline(always)] - pub fn pass(self) -> &'a mut W { + pub fn pass(self) -> &'a mut crate::W { self.variant(DIV_A::PASS) } } @@ -109,32 +81,31 @@ impl W { this register resets to div=16"] #[inline(always)] #[must_use] - pub fn div(&mut self) -> DIV_W<0> { + pub fn div(&mut self) -> DIV_W { DIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Controls the output divider -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/dormant.rs b/src/rosc/dormant.rs index c7611fa09..47df8a16d 100644 --- a/src/rosc/dormant.rs +++ b/src/rosc/dormant.rs @@ -1,39 +1,7 @@ #[doc = "Register `DORMANT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -58,20 +30,15 @@ impl W { An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_SPEC; impl crate::RegisterSpec for DORMANT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant::R](R) reader structure"] -impl crate::Readable for DORMANT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant::R`](R) reader structure"] +impl crate::Readable for DORMANT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] impl crate::Writable for DORMANT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs index e89e58c4a..82e2cbe6c 100644 --- a/src/rosc/freqa.rs +++ b/src/rosc/freqa.rs @@ -1,55 +1,23 @@ #[doc = "Register `FREQA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FREQA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DS0` reader - Stage 0 drive strength"] pub type DS0_R = crate::FieldReader; #[doc = "Field `DS0` writer - Stage 0 drive strength"] -pub type DS0_W<'a, const O: u8> = crate::FieldWriter<'a, FREQA_SPEC, 3, O>; +pub type DS0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS1` reader - Stage 1 drive strength"] pub type DS1_R = crate::FieldReader; #[doc = "Field `DS1` writer - Stage 1 drive strength"] -pub type DS1_W<'a, const O: u8> = crate::FieldWriter<'a, FREQA_SPEC, 3, O>; +pub type DS1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS2` reader - Stage 2 drive strength"] pub type DS2_R = crate::FieldReader; #[doc = "Field `DS2` writer - Stage 2 drive strength"] -pub type DS2_W<'a, const O: u8> = crate::FieldWriter<'a, FREQA_SPEC, 3, O>; +pub type DS2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS3` reader - Stage 3 drive strength"] pub type DS3_R = crate::FieldReader; #[doc = "Field `DS3` writer - Stage 3 drive strength"] -pub type DS3_W<'a, const O: u8> = crate::FieldWriter<'a, FREQA_SPEC, 3, O>; +pub type DS3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_R = crate::FieldReader; @@ -75,13 +43,13 @@ impl crate::FieldSpec for PASSWD_A { impl PASSWD_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 38550 => Some(PASSWD_A::PASS), _ => None, } } - #[doc = "Checks if the value of the field is `PASS`"] + #[doc = "`1001011010010110`"] #[inline(always)] pub fn is_pass(&self) -> bool { *self == PASSWD_A::PASS @@ -89,11 +57,15 @@ impl PASSWD_R { } #[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, FREQA_SPEC, 16, O, PASSWD_A>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, PASSWD_A>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1001011010010110`"] #[inline(always)] - pub fn pass(self) -> &'a mut W { + pub fn pass(self) -> &'a mut crate::W { self.variant(PASSWD_A::PASS) } } @@ -129,38 +101,42 @@ impl W { #[doc = "Bits 0:2 - Stage 0 drive strength"] #[inline(always)] #[must_use] - pub fn ds0(&mut self) -> DS0_W<0> { + pub fn ds0(&mut self) -> DS0_W { DS0_W::new(self) } #[doc = "Bits 4:6 - Stage 1 drive strength"] #[inline(always)] #[must_use] - pub fn ds1(&mut self) -> DS1_W<4> { + pub fn ds1(&mut self) -> DS1_W { DS1_W::new(self) } #[doc = "Bits 8:10 - Stage 2 drive strength"] #[inline(always)] #[must_use] - pub fn ds2(&mut self) -> DS2_W<8> { + pub fn ds2(&mut self) -> DS2_W { DS2_W::new(self) } #[doc = "Bits 12:14 - Stage 3 drive strength"] #[inline(always)] #[must_use] - pub fn ds3(&mut self) -> DS3_W<12> { + pub fn ds3(&mut self) -> DS3_W { DS3_W::new(self) } #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<16> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -172,20 +148,15 @@ impl W { 2 bits set triples drive strength 3 bits set quadruples drive strength -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [freqa](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FREQA_SPEC; impl crate::RegisterSpec for FREQA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [freqa::R](R) reader structure"] -impl crate::Readable for FREQA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [freqa::W](W) writer structure"] +#[doc = "`read()` method returns [`freqa::R`](R) reader structure"] +impl crate::Readable for FREQA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`freqa::W`](W) writer structure"] impl crate::Writable for FREQA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs index 098ecee07..4ad5de84c 100644 --- a/src/rosc/freqb.rs +++ b/src/rosc/freqb.rs @@ -1,55 +1,23 @@ #[doc = "Register `FREQB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FREQB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DS4` reader - Stage 4 drive strength"] pub type DS4_R = crate::FieldReader; #[doc = "Field `DS4` writer - Stage 4 drive strength"] -pub type DS4_W<'a, const O: u8> = crate::FieldWriter<'a, FREQB_SPEC, 3, O>; +pub type DS4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS5` reader - Stage 5 drive strength"] pub type DS5_R = crate::FieldReader; #[doc = "Field `DS5` writer - Stage 5 drive strength"] -pub type DS5_W<'a, const O: u8> = crate::FieldWriter<'a, FREQB_SPEC, 3, O>; +pub type DS5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS6` reader - Stage 6 drive strength"] pub type DS6_R = crate::FieldReader; #[doc = "Field `DS6` writer - Stage 6 drive strength"] -pub type DS6_W<'a, const O: u8> = crate::FieldWriter<'a, FREQB_SPEC, 3, O>; +pub type DS6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DS7` reader - Stage 7 drive strength"] pub type DS7_R = crate::FieldReader; #[doc = "Field `DS7` writer - Stage 7 drive strength"] -pub type DS7_W<'a, const O: u8> = crate::FieldWriter<'a, FREQB_SPEC, 3, O>; +pub type DS7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_R = crate::FieldReader; @@ -75,13 +43,13 @@ impl crate::FieldSpec for PASSWD_A { impl PASSWD_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 38550 => Some(PASSWD_A::PASS), _ => None, } } - #[doc = "Checks if the value of the field is `PASS`"] + #[doc = "`1001011010010110`"] #[inline(always)] pub fn is_pass(&self) -> bool { *self == PASSWD_A::PASS @@ -89,11 +57,15 @@ impl PASSWD_R { } #[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, FREQB_SPEC, 16, O, PASSWD_A>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, PASSWD_A>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1001011010010110`"] #[inline(always)] - pub fn pass(self) -> &'a mut W { + pub fn pass(self) -> &'a mut crate::W { self.variant(PASSWD_A::PASS) } } @@ -129,57 +101,56 @@ impl W { #[doc = "Bits 0:2 - Stage 4 drive strength"] #[inline(always)] #[must_use] - pub fn ds4(&mut self) -> DS4_W<0> { + pub fn ds4(&mut self) -> DS4_W { DS4_W::new(self) } #[doc = "Bits 4:6 - Stage 5 drive strength"] #[inline(always)] #[must_use] - pub fn ds5(&mut self) -> DS5_W<4> { + pub fn ds5(&mut self) -> DS5_W { DS5_W::new(self) } #[doc = "Bits 8:10 - Stage 6 drive strength"] #[inline(always)] #[must_use] - pub fn ds6(&mut self) -> DS6_W<8> { + pub fn ds6(&mut self) -> DS6_W { DS6_W::new(self) } #[doc = "Bits 12:14 - Stage 7 drive strength"] #[inline(always)] #[must_use] - pub fn ds7(&mut self) -> DS7_W<12> { + pub fn ds7(&mut self) -> DS7_W { DS7_W::new(self) } #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<16> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "For a detailed description see freqa register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [freqb](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`freqb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FREQB_SPEC; impl crate::RegisterSpec for FREQB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [freqb::R](R) reader structure"] -impl crate::Readable for FREQB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [freqb::W](W) writer structure"] +#[doc = "`read()` method returns [`freqb::R`](R) reader structure"] +impl crate::Readable for FREQB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`freqb::W`](W) writer structure"] impl crate::Writable for FREQB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs index 33c2c738f..3021d9c0e 100644 --- a/src/rosc/phase.rs +++ b/src/rosc/phase.rs @@ -1,39 +1,7 @@ #[doc = "Register `PHASE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PHASE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT` reader - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] @@ -41,25 +9,25 @@ pub type SHIFT_R = crate::FieldReader; #[doc = "Field `SHIFT` writer - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] -pub type SHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, PHASE_SPEC, 2, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `FLIP` reader - invert the phase-shifted output this is ignored when div=1"] pub type FLIP_R = crate::BitReader; #[doc = "Field `FLIP` writer - invert the phase-shifted output this is ignored when div=1"] -pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, PHASE_SPEC, O>; +pub type FLIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - enable the phase-shifted output this can be changed on-the-fly"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - enable the phase-shifted output this can be changed on-the-fly"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, PHASE_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PASSWD` reader - set to 0xaa any other value enables the output with shift=0"] pub type PASSWD_R = crate::FieldReader; #[doc = "Field `PASSWD` writer - set to 0xaa any other value enables the output with shift=0"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, PHASE_SPEC, 8, O>; +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly @@ -93,53 +61,52 @@ impl W { must be set to 0 before setting div=1"] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<0> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] #[inline(always)] #[must_use] - pub fn flip(&mut self) -> FLIP_W<2> { + pub fn flip(&mut self) -> FLIP_W { FLIP_W::new(self) } #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<3> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<4> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Controls the phase shifted output -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [phase](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`phase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PHASE_SPEC; impl crate::RegisterSpec for PHASE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [phase::R](R) reader structure"] -impl crate::Readable for PHASE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [phase::W](W) writer structure"] +#[doc = "`read()` method returns [`phase::R`](R) reader structure"] +impl crate::Readable for PHASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phase::W`](W) writer structure"] impl crate::Writable for PHASE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rosc/randombit.rs b/src/rosc/randombit.rs index 0b96ffef3..2f308a710 100644 --- a/src/rosc/randombit.rs +++ b/src/rosc/randombit.rs @@ -1,18 +1,5 @@ #[doc = "Register `RANDOMBIT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RANDOMBIT` reader - "] pub type RANDOMBIT_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [randombit](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RANDOMBIT_SPEC; impl crate::RegisterSpec for RANDOMBIT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [randombit::R](R) reader structure"] -impl crate::Readable for RANDOMBIT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`randombit::R`](R) reader structure"] +impl crate::Readable for RANDOMBIT_SPEC {} #[doc = "`reset()` method sets RANDOMBIT to value 0x01"] impl crate::Resettable for RANDOMBIT_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/rosc/status.rs b/src/rosc/status.rs index 48210813d..d1f745830 100644 --- a/src/rosc/status.rs +++ b/src/rosc/status.rs @@ -1,18 +1,5 @@ #[doc = "Register `STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"] pub type ENABLED_R = crate::BitReader; #[doc = "Field `DIV_RUNNING` reader - post-divider is running this resets to 0 but transitions to 1 during chip startup"] @@ -38,17 +25,13 @@ impl R { } #[doc = "Ring Oscillator Status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status::R](R) reader structure"] -impl crate::Readable for STATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} #[doc = "`reset()` method sets STATUS to value 0"] impl crate::Resettable for STATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/rtc.rs b/src/rtc.rs index 53cf537ac..f6f6b73e2 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -27,52 +27,113 @@ pub struct RegisterBlock { #[doc = "0x2c - Interrupt status after masking & forcing"] pub ints: INTS, } -#[doc = "CLKDIV_M1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CLKDIV_M1 (rw) register accessor: Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. + +You can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_m1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_m1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clkdiv_m1`] +module"] pub type CLKDIV_M1 = crate::Reg; #[doc = "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled."] pub mod clkdiv_m1; -#[doc = "SETUP_0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SETUP_0 (rw) register accessor: RTC setup register 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`setup_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_0`] +module"] pub type SETUP_0 = crate::Reg; #[doc = "RTC setup register 0"] pub mod setup_0; -#[doc = "SETUP_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SETUP_1 (rw) register accessor: RTC setup register 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`setup_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_1`] +module"] pub type SETUP_1 = crate::Reg; #[doc = "RTC setup register 1"] pub mod setup_1; -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: RTC Control and status + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "RTC Control and status"] pub mod ctrl; -#[doc = "IRQ_SETUP_0 (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ_SETUP_0 (rw) register accessor: Interrupt setup register 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_setup_0`] +module"] pub type IRQ_SETUP_0 = crate::Reg; #[doc = "Interrupt setup register 0"] pub mod irq_setup_0; -#[doc = "IRQ_SETUP_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ_SETUP_1 (rw) register accessor: Interrupt setup register 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_setup_1`] +module"] pub type IRQ_SETUP_1 = crate::Reg; #[doc = "Interrupt setup register 1"] pub mod irq_setup_1; -#[doc = "RTC_1 (r) register accessor: an alias for `Reg`"] +#[doc = "RTC_1 (r) register accessor: RTC register 1. + +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rtc_1`] +module"] pub type RTC_1 = crate::Reg; #[doc = "RTC register 1."] pub mod rtc_1; -#[doc = "RTC_0 (r) register accessor: an alias for `Reg`"] +#[doc = "RTC_0 (r) register accessor: RTC register 0 + Read this before RTC 1! + +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rtc_0`] +module"] pub type RTC_0 = crate::Reg; #[doc = "RTC register 0 Read this before RTC 1!"] pub mod rtc_0; -#[doc = "INTR (r) register accessor: an alias for `Reg`"] +#[doc = "INTR (r) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/rtc/clkdiv_m1.rs b/src/rtc/clkdiv_m1.rs index f06c8e163..98d5c8afd 100644 --- a/src/rtc/clkdiv_m1.rs +++ b/src/rtc/clkdiv_m1.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLKDIV_M1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLKDIV_M1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLKDIV_M1` reader - "] pub type CLKDIV_M1_R = crate::FieldReader; #[doc = "Field `CLKDIV_M1` writer - "] -pub type CLKDIV_M1_W<'a, const O: u8> = crate::FieldWriter<'a, CLKDIV_M1_SPEC, 16, O, u16>; +pub type CLKDIV_M1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn clkdiv_m1(&mut self) -> CLKDIV_M1_W<0> { + pub fn clkdiv_m1(&mut self) -> CLKDIV_M1_W { CLKDIV_M1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [clkdiv_m1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_m1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_m1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKDIV_M1_SPEC; impl crate::RegisterSpec for CLKDIV_M1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clkdiv_m1::R](R) reader structure"] -impl crate::Readable for CLKDIV_M1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clkdiv_m1::W](W) writer structure"] +#[doc = "`read()` method returns [`clkdiv_m1::R`](R) reader structure"] +impl crate::Readable for CLKDIV_M1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkdiv_m1::W`](W) writer structure"] impl crate::Writable for CLKDIV_M1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/ctrl.rs b/src/rtc/ctrl.rs index 881709d61..0d34daa39 100644 --- a/src/rtc/ctrl.rs +++ b/src/rtc/ctrl.rs @@ -1,55 +1,23 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTC_ENABLE` reader - Enable RTC"] pub type RTC_ENABLE_R = crate::BitReader; #[doc = "Field `RTC_ENABLE` writer - Enable RTC"] -pub type RTC_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type RTC_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTC_ACTIVE` reader - RTC enabled (running)"] pub type RTC_ACTIVE_R = crate::BitReader; #[doc = "Field `LOAD` reader - Load RTC"] pub type LOAD_R = crate::BitReader; #[doc = "Field `LOAD` writer - Load RTC"] -pub type LOAD_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type LOAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FORCE_NOTLEAPYEAR` reader - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] pub type FORCE_NOTLEAPYEAR_R = crate::BitReader; #[doc = "Field `FORCE_NOTLEAPYEAR` writer - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] -pub type FORCE_NOTLEAPYEAR_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type FORCE_NOTLEAPYEAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable RTC"] #[inline(always)] @@ -77,45 +45,44 @@ impl W { #[doc = "Bit 0 - Enable RTC"] #[inline(always)] #[must_use] - pub fn rtc_enable(&mut self) -> RTC_ENABLE_W<0> { + pub fn rtc_enable(&mut self) -> RTC_ENABLE_W { RTC_ENABLE_W::new(self) } #[doc = "Bit 4 - Load RTC"] #[inline(always)] #[must_use] - pub fn load(&mut self) -> LOAD_W<4> { + pub fn load(&mut self) -> LOAD_W { LOAD_W::new(self) } #[doc = "Bit 8 - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] #[inline(always)] #[must_use] - pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W<8> { + pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W { FORCE_NOTLEAPYEAR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "RTC Control and status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/inte.rs b/src/rtc/inte.rs index d7f9fc765..8850462ee 100644 --- a/src/rtc/inte.rs +++ b/src/rtc/inte.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; #[doc = "Field `RTC` writer - "] -pub type RTC_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn rtc(&mut self) -> RTC_W<0> { + pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/intf.rs b/src/rtc/intf.rs index da3f70a53..7ddc8ebcb 100644 --- a/src/rtc/intf.rs +++ b/src/rtc/intf.rs @@ -1,43 +1,11 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; #[doc = "Field `RTC` writer - "] -pub type RTC_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type RTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn rtc(&mut self) -> RTC_W<0> { + pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/intr.rs b/src/rtc/intr.rs index 720e837eb..d63d13592 100644 --- a/src/rtc/intr.rs +++ b/src/rtc/intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/rtc/ints.rs b/src/rtc/ints.rs index 1894b63fa..210b77f29 100644 --- a/src/rtc/ints.rs +++ b/src/rtc/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/rtc/irq_setup_0.rs b/src/rtc/irq_setup_0.rs index 07361b9a5..fa6d060a2 100644 --- a/src/rtc/irq_setup_0.rs +++ b/src/rtc/irq_setup_0.rs @@ -1,67 +1,35 @@ #[doc = "Register `IRQ_SETUP_0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ_SETUP_0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub type DAY_R = crate::FieldReader; #[doc = "Field `DAY` writer - Day of the month (1..31)"] -pub type DAY_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_0_SPEC, 5, O>; +pub type DAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MONTH` reader - Month (1..12)"] pub type MONTH_R = crate::FieldReader; #[doc = "Field `MONTH` writer - Month (1..12)"] -pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_0_SPEC, 4, O>; +pub type MONTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `YEAR` reader - Year"] pub type YEAR_R = crate::FieldReader; #[doc = "Field `YEAR` writer - Year"] -pub type YEAR_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_0_SPEC, 12, O, u16>; +pub type YEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `DAY_ENA` reader - Enable day matching"] pub type DAY_ENA_R = crate::BitReader; #[doc = "Field `DAY_ENA` writer - Enable day matching"] -pub type DAY_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_0_SPEC, O>; +pub type DAY_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MONTH_ENA` reader - Enable month matching"] pub type MONTH_ENA_R = crate::BitReader; #[doc = "Field `MONTH_ENA` writer - Enable month matching"] -pub type MONTH_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_0_SPEC, O>; +pub type MONTH_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `YEAR_ENA` reader - Enable year matching"] pub type YEAR_ENA_R = crate::BitReader; #[doc = "Field `YEAR_ENA` writer - Enable year matching"] -pub type YEAR_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_0_SPEC, O>; +pub type YEAR_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MATCH_ENA` reader - Global match enable. Don't change any other value while this one is enabled"] pub type MATCH_ENA_R = crate::BitReader; #[doc = "Field `MATCH_ENA` writer - Global match enable. Don't change any other value while this one is enabled"] -pub type MATCH_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_0_SPEC, O>; +pub type MATCH_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MATCH_ACTIVE` reader - "] pub type MATCH_ACTIVE_R = crate::BitReader; impl R { @@ -110,68 +78,67 @@ impl W { #[doc = "Bits 0:4 - Day of the month (1..31)"] #[inline(always)] #[must_use] - pub fn day(&mut self) -> DAY_W<0> { + pub fn day(&mut self) -> DAY_W { DAY_W::new(self) } #[doc = "Bits 8:11 - Month (1..12)"] #[inline(always)] #[must_use] - pub fn month(&mut self) -> MONTH_W<8> { + pub fn month(&mut self) -> MONTH_W { MONTH_W::new(self) } #[doc = "Bits 12:23 - Year"] #[inline(always)] #[must_use] - pub fn year(&mut self) -> YEAR_W<12> { + pub fn year(&mut self) -> YEAR_W { YEAR_W::new(self) } #[doc = "Bit 24 - Enable day matching"] #[inline(always)] #[must_use] - pub fn day_ena(&mut self) -> DAY_ENA_W<24> { + pub fn day_ena(&mut self) -> DAY_ENA_W { DAY_ENA_W::new(self) } #[doc = "Bit 25 - Enable month matching"] #[inline(always)] #[must_use] - pub fn month_ena(&mut self) -> MONTH_ENA_W<25> { + pub fn month_ena(&mut self) -> MONTH_ENA_W { MONTH_ENA_W::new(self) } #[doc = "Bit 26 - Enable year matching"] #[inline(always)] #[must_use] - pub fn year_ena(&mut self) -> YEAR_ENA_W<26> { + pub fn year_ena(&mut self) -> YEAR_ENA_W { YEAR_ENA_W::new(self) } #[doc = "Bit 28 - Global match enable. Don't change any other value while this one is enabled"] #[inline(always)] #[must_use] - pub fn match_ena(&mut self) -> MATCH_ENA_W<28> { + pub fn match_ena(&mut self) -> MATCH_ENA_W { MATCH_ENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt setup register 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_setup_0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SETUP_0_SPEC; impl crate::RegisterSpec for IRQ_SETUP_0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq_setup_0::R](R) reader structure"] -impl crate::Readable for IRQ_SETUP_0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq_setup_0::W](W) writer structure"] +#[doc = "`read()` method returns [`irq_setup_0::R`](R) reader structure"] +impl crate::Readable for IRQ_SETUP_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_setup_0::W`](W) writer structure"] impl crate::Writable for IRQ_SETUP_0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/irq_setup_1.rs b/src/rtc/irq_setup_1.rs index b7e9815fc..4ca69bab1 100644 --- a/src/rtc/irq_setup_1.rs +++ b/src/rtc/irq_setup_1.rs @@ -1,71 +1,39 @@ #[doc = "Register `IRQ_SETUP_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ_SETUP_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - Seconds"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - Seconds"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_1_SPEC, 6, O>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MIN` reader - Minutes"] pub type MIN_R = crate::FieldReader; #[doc = "Field `MIN` writer - Minutes"] -pub type MIN_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_1_SPEC, 6, O>; +pub type MIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `HOUR` reader - Hours"] pub type HOUR_R = crate::FieldReader; #[doc = "Field `HOUR` writer - Hours"] -pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_1_SPEC, 5, O>; +pub type HOUR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DOTW` reader - Day of the week"] pub type DOTW_R = crate::FieldReader; #[doc = "Field `DOTW` writer - Day of the week"] -pub type DOTW_W<'a, const O: u8> = crate::FieldWriter<'a, IRQ_SETUP_1_SPEC, 3, O>; +pub type DOTW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SEC_ENA` reader - Enable second matching"] pub type SEC_ENA_R = crate::BitReader; #[doc = "Field `SEC_ENA` writer - Enable second matching"] -pub type SEC_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_1_SPEC, O>; +pub type SEC_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MIN_ENA` reader - Enable minute matching"] pub type MIN_ENA_R = crate::BitReader; #[doc = "Field `MIN_ENA` writer - Enable minute matching"] -pub type MIN_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_1_SPEC, O>; +pub type MIN_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOUR_ENA` reader - Enable hour matching"] pub type HOUR_ENA_R = crate::BitReader; #[doc = "Field `HOUR_ENA` writer - Enable hour matching"] -pub type HOUR_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_1_SPEC, O>; +pub type HOUR_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOTW_ENA` reader - Enable day of the week matching"] pub type DOTW_ENA_R = crate::BitReader; #[doc = "Field `DOTW_ENA` writer - Enable day of the week matching"] -pub type DOTW_ENA_W<'a, const O: u8> = crate::BitWriter<'a, IRQ_SETUP_1_SPEC, O>; +pub type DOTW_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:5 - Seconds"] #[inline(always)] @@ -112,74 +80,73 @@ impl W { #[doc = "Bits 0:5 - Seconds"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Bits 8:13 - Minutes"] #[inline(always)] #[must_use] - pub fn min(&mut self) -> MIN_W<8> { + pub fn min(&mut self) -> MIN_W { MIN_W::new(self) } #[doc = "Bits 16:20 - Hours"] #[inline(always)] #[must_use] - pub fn hour(&mut self) -> HOUR_W<16> { + pub fn hour(&mut self) -> HOUR_W { HOUR_W::new(self) } #[doc = "Bits 24:26 - Day of the week"] #[inline(always)] #[must_use] - pub fn dotw(&mut self) -> DOTW_W<24> { + pub fn dotw(&mut self) -> DOTW_W { DOTW_W::new(self) } #[doc = "Bit 28 - Enable second matching"] #[inline(always)] #[must_use] - pub fn sec_ena(&mut self) -> SEC_ENA_W<28> { + pub fn sec_ena(&mut self) -> SEC_ENA_W { SEC_ENA_W::new(self) } #[doc = "Bit 29 - Enable minute matching"] #[inline(always)] #[must_use] - pub fn min_ena(&mut self) -> MIN_ENA_W<29> { + pub fn min_ena(&mut self) -> MIN_ENA_W { MIN_ENA_W::new(self) } #[doc = "Bit 30 - Enable hour matching"] #[inline(always)] #[must_use] - pub fn hour_ena(&mut self) -> HOUR_ENA_W<30> { + pub fn hour_ena(&mut self) -> HOUR_ENA_W { HOUR_ENA_W::new(self) } #[doc = "Bit 31 - Enable day of the week matching"] #[inline(always)] #[must_use] - pub fn dotw_ena(&mut self) -> DOTW_ENA_W<31> { + pub fn dotw_ena(&mut self) -> DOTW_ENA_W { DOTW_ENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt setup register 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [irq_setup_1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SETUP_1_SPEC; impl crate::RegisterSpec for IRQ_SETUP_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq_setup_1::R](R) reader structure"] -impl crate::Readable for IRQ_SETUP_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq_setup_1::W](W) writer structure"] +#[doc = "`read()` method returns [`irq_setup_1::R`](R) reader structure"] +impl crate::Readable for IRQ_SETUP_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_setup_1::W`](W) writer structure"] impl crate::Writable for IRQ_SETUP_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/rtc_0.rs b/src/rtc/rtc_0.rs index e677da478..3a677f234 100644 --- a/src/rtc/rtc_0.rs +++ b/src/rtc/rtc_0.rs @@ -1,18 +1,5 @@ #[doc = "Register `RTC_0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SEC` reader - Seconds"] pub type SEC_R = crate::FieldReader; #[doc = "Field `MIN` reader - Minutes"] @@ -46,17 +33,13 @@ impl R { #[doc = "RTC register 0 Read this before RTC 1! -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rtc_0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RTC_0_SPEC; impl crate::RegisterSpec for RTC_0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rtc_0::R](R) reader structure"] -impl crate::Readable for RTC_0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rtc_0::R`](R) reader structure"] +impl crate::Readable for RTC_0_SPEC {} #[doc = "`reset()` method sets RTC_0 to value 0"] impl crate::Resettable for RTC_0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/rtc/rtc_1.rs b/src/rtc/rtc_1.rs index 7305368aa..2bc5f9c6a 100644 --- a/src/rtc/rtc_1.rs +++ b/src/rtc/rtc_1.rs @@ -1,18 +1,5 @@ #[doc = "Register `RTC_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub type DAY_R = crate::FieldReader; #[doc = "Field `MONTH` reader - Month (1..12)"] @@ -38,17 +25,13 @@ impl R { } #[doc = "RTC register 1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rtc_1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RTC_1_SPEC; impl crate::RegisterSpec for RTC_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rtc_1::R](R) reader structure"] -impl crate::Readable for RTC_1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rtc_1::R`](R) reader structure"] +impl crate::Readable for RTC_1_SPEC {} #[doc = "`reset()` method sets RTC_1 to value 0"] impl crate::Resettable for RTC_1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/rtc/setup_0.rs b/src/rtc/setup_0.rs index 6f4e1e7bb..f93ad3276 100644 --- a/src/rtc/setup_0.rs +++ b/src/rtc/setup_0.rs @@ -1,51 +1,19 @@ #[doc = "Register `SETUP_0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SETUP_0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub type DAY_R = crate::FieldReader; #[doc = "Field `DAY` writer - Day of the month (1..31)"] -pub type DAY_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_0_SPEC, 5, O>; +pub type DAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MONTH` reader - Month (1..12)"] pub type MONTH_R = crate::FieldReader; #[doc = "Field `MONTH` writer - Month (1..12)"] -pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_0_SPEC, 4, O>; +pub type MONTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `YEAR` reader - Year"] pub type YEAR_R = crate::FieldReader; #[doc = "Field `YEAR` writer - Year"] -pub type YEAR_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_0_SPEC, 12, O, u16>; +pub type YEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:4 - Day of the month (1..31)"] #[inline(always)] @@ -67,44 +35,43 @@ impl W { #[doc = "Bits 0:4 - Day of the month (1..31)"] #[inline(always)] #[must_use] - pub fn day(&mut self) -> DAY_W<0> { + pub fn day(&mut self) -> DAY_W { DAY_W::new(self) } #[doc = "Bits 8:11 - Month (1..12)"] #[inline(always)] #[must_use] - pub fn month(&mut self) -> MONTH_W<8> { + pub fn month(&mut self) -> MONTH_W { MONTH_W::new(self) } #[doc = "Bits 12:23 - Year"] #[inline(always)] #[must_use] - pub fn year(&mut self) -> YEAR_W<12> { + pub fn year(&mut self) -> YEAR_W { YEAR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "RTC setup register 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [setup_0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`setup_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SETUP_0_SPEC; impl crate::RegisterSpec for SETUP_0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [setup_0::R](R) reader structure"] -impl crate::Readable for SETUP_0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [setup_0::W](W) writer structure"] +#[doc = "`read()` method returns [`setup_0::R`](R) reader structure"] +impl crate::Readable for SETUP_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_0::W`](W) writer structure"] impl crate::Writable for SETUP_0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/rtc/setup_1.rs b/src/rtc/setup_1.rs index ff2fed8d6..2db34d73c 100644 --- a/src/rtc/setup_1.rs +++ b/src/rtc/setup_1.rs @@ -1,55 +1,23 @@ #[doc = "Register `SETUP_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SETUP_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - Seconds"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - Seconds"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_1_SPEC, 6, O>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MIN` reader - Minutes"] pub type MIN_R = crate::FieldReader; #[doc = "Field `MIN` writer - Minutes"] -pub type MIN_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_1_SPEC, 6, O>; +pub type MIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `HOUR` reader - Hours"] pub type HOUR_R = crate::FieldReader; #[doc = "Field `HOUR` writer - Hours"] -pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_1_SPEC, 5, O>; +pub type HOUR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DOTW` reader - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7"] pub type DOTW_R = crate::FieldReader; #[doc = "Field `DOTW` writer - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7"] -pub type DOTW_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_1_SPEC, 3, O>; +pub type DOTW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:5 - Seconds"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 0:5 - Seconds"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Bits 8:13 - Minutes"] #[inline(always)] #[must_use] - pub fn min(&mut self) -> MIN_W<8> { + pub fn min(&mut self) -> MIN_W { MIN_W::new(self) } #[doc = "Bits 16:20 - Hours"] #[inline(always)] #[must_use] - pub fn hour(&mut self) -> HOUR_W<16> { + pub fn hour(&mut self) -> HOUR_W { HOUR_W::new(self) } #[doc = "Bits 24:26 - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7"] #[inline(always)] #[must_use] - pub fn dotw(&mut self) -> DOTW_W<24> { + pub fn dotw(&mut self) -> DOTW_W { DOTW_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "RTC setup register 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [setup_1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`setup_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SETUP_1_SPEC; impl crate::RegisterSpec for SETUP_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [setup_1::R](R) reader structure"] -impl crate::Readable for SETUP_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [setup_1::W](W) writer structure"] +#[doc = "`read()` method returns [`setup_1::R`](R) reader structure"] +impl crate::Readable for SETUP_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_1::W`](W) writer structure"] impl crate::Writable for SETUP_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio.rs b/src/sio.rs index 265d4f89f..2b4e2917c 100644 --- a/src/sio.rs +++ b/src/sio.rs @@ -169,84 +169,189 @@ pub struct RegisterBlock { The value returned on success is 0x1 << lock number."] pub spinlock: [SPINLOCK; 32], } -#[doc = "CPUID (r) register accessor: an alias for `Reg`"] +#[doc = "CPUID (r) register accessor: Processor core identifier + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cpuid`] +module"] pub type CPUID = crate::Reg; #[doc = "Processor core identifier Value is 0 when read from processor core 0, and 1 when read from processor core 1."] pub mod cpuid; -#[doc = "GPIO_IN (r) register accessor: an alias for `Reg`"] +#[doc = "GPIO_IN (r) register accessor: Input value for GPIO pins + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_in`] +module"] pub type GPIO_IN = crate::Reg; #[doc = "Input value for GPIO pins"] pub mod gpio_in; -#[doc = "GPIO_HI_IN (r) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_IN (r) register accessor: Input value for QSPI pins + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_in`] +module"] pub type GPIO_HI_IN = crate::Reg; #[doc = "Input value for QSPI pins"] pub mod gpio_hi_in; -#[doc = "GPIO_OUT (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OUT (rw) register accessor: GPIO output value + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out`] +module"] pub type GPIO_OUT = crate::Reg; #[doc = "GPIO output value"] pub mod gpio_out; -#[doc = "GPIO_OUT_SET (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OUT_SET (w) register accessor: GPIO output value set + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_set`] +module"] pub type GPIO_OUT_SET = crate::Reg; #[doc = "GPIO output value set"] pub mod gpio_out_set; -#[doc = "GPIO_OUT_CLR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OUT_CLR (w) register accessor: GPIO output value clear + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_clr`] +module"] pub type GPIO_OUT_CLR = crate::Reg; #[doc = "GPIO output value clear"] pub mod gpio_out_clr; -#[doc = "GPIO_OUT_XOR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OUT_XOR (w) register accessor: GPIO output value XOR + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_xor`] +module"] pub type GPIO_OUT_XOR = crate::Reg; #[doc = "GPIO output value XOR"] pub mod gpio_out_xor; -#[doc = "GPIO_OE (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OE (rw) register accessor: GPIO output enable + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe`] +module"] pub type GPIO_OE = crate::Reg; #[doc = "GPIO output enable"] pub mod gpio_oe; -#[doc = "GPIO_OE_SET (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OE_SET (w) register accessor: GPIO output enable set + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_set`] +module"] pub type GPIO_OE_SET = crate::Reg; #[doc = "GPIO output enable set"] pub mod gpio_oe_set; -#[doc = "GPIO_OE_CLR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OE_CLR (w) register accessor: GPIO output enable clear + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_clr`] +module"] pub type GPIO_OE_CLR = crate::Reg; #[doc = "GPIO output enable clear"] pub mod gpio_oe_clr; -#[doc = "GPIO_OE_XOR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_OE_XOR (w) register accessor: GPIO output enable XOR + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_xor`] +module"] pub type GPIO_OE_XOR = crate::Reg; #[doc = "GPIO output enable XOR"] pub mod gpio_oe_xor; -#[doc = "GPIO_HI_OUT (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OUT (rw) register accessor: QSPI output value + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out`] +module"] pub type GPIO_HI_OUT = crate::Reg; #[doc = "QSPI output value"] pub mod gpio_hi_out; -#[doc = "GPIO_HI_OUT_SET (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OUT_SET (w) register accessor: QSPI output value set + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_set`] +module"] pub type GPIO_HI_OUT_SET = crate::Reg; #[doc = "QSPI output value set"] pub mod gpio_hi_out_set; -#[doc = "GPIO_HI_OUT_CLR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_clr`] +module"] pub type GPIO_HI_OUT_CLR = crate::Reg; #[doc = "QSPI output value clear"] pub mod gpio_hi_out_clr; -#[doc = "GPIO_HI_OUT_XOR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_xor`] +module"] pub type GPIO_HI_OUT_XOR = crate::Reg; #[doc = "QSPI output value XOR"] pub mod gpio_hi_out_xor; -#[doc = "GPIO_HI_OE (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OE (rw) register accessor: QSPI output enable + +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe`] +module"] pub type GPIO_HI_OE = crate::Reg; #[doc = "QSPI output enable"] pub mod gpio_hi_oe; -#[doc = "GPIO_HI_OE_SET (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OE_SET (w) register accessor: QSPI output enable set + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_set`] +module"] pub type GPIO_HI_OE_SET = crate::Reg; #[doc = "QSPI output enable set"] pub mod gpio_hi_oe_set; -#[doc = "GPIO_HI_OE_CLR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_clr`] +module"] pub type GPIO_HI_OE_CLR = crate::Reg; #[doc = "QSPI output enable clear"] pub mod gpio_hi_oe_clr; -#[doc = "GPIO_HI_OE_XOR (w) register accessor: an alias for `Reg`"] +#[doc = "GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_xor`] +module"] pub type GPIO_HI_OE_XOR = crate::Reg; #[doc = "QSPI output enable XOR"] pub mod gpio_hi_oe_xor; -#[doc = "FIFO_ST (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_st`] +module"] pub type FIFO_ST = crate::Reg; #[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. @@ -254,21 +359,47 @@ pub type FIFO_ST = crate::Reg; Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] pub mod fifo_st; -#[doc = "FIFO_WR (w) register accessor: an alias for `Reg`"] +#[doc = "FIFO_WR (w) register accessor: Write access to this core's TX FIFO + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_wr`] +module"] pub type FIFO_WR = crate::Reg; #[doc = "Write access to this core's TX FIFO"] pub mod fifo_wr; -#[doc = "FIFO_RD (r) register accessor: an alias for `Reg`"] +#[doc = "FIFO_RD (r) register accessor: Read access to this core's RX FIFO + +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_rd`] +module"] pub type FIFO_RD = crate::Reg; #[doc = "Read access to this core's RX FIFO"] pub mod fifo_rd; -#[doc = "SPINLOCK_ST (r) register accessor: an alias for `Reg`"] +#[doc = "SPINLOCK_ST (r) register accessor: Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spinlock_st`] +module"] pub type SPINLOCK_ST = crate::Reg; #[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] pub mod spinlock_st; -#[doc = "DIV_UDIVIDEND (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend + Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_udividend`] +module"] pub type DIV_UDIVIDEND = crate::Reg; #[doc = "Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. @@ -276,7 +407,16 @@ pub type DIV_UDIVIDEND = crate::Reg; UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] pub mod div_udividend; -#[doc = "DIV_UDIVISOR (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor + Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_udivisor`] +module"] pub type DIV_UDIVISOR = crate::Reg; #[doc = "Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. @@ -284,17 +424,40 @@ pub type DIV_UDIVISOR = crate::Reg; UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] pub mod div_udivisor; -#[doc = "DIV_SDIVIDEND (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_SDIVIDEND (rw) register accessor: Divider signed dividend + The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_sdividend`] +module"] pub type DIV_SDIVIDEND = crate::Reg; #[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] pub mod div_sdividend; -#[doc = "DIV_SDIVISOR (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_SDIVISOR (rw) register accessor: Divider signed divisor + The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_sdivisor`] +module"] pub type DIV_SDIVISOR = crate::Reg; #[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] pub mod div_sdivisor; -#[doc = "DIV_QUOTIENT (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_QUOTIENT (rw) register accessor: Divider result quotient + The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. + For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order + REMAINDER, QUOTIENT if CSR_DIRTY is used. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_quotient`] +module"] pub type DIV_QUOTIENT = crate::Reg; #[doc = "Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. @@ -304,7 +467,16 @@ pub type DIV_QUOTIENT = crate::Reg; Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used."] pub mod div_quotient; -#[doc = "DIV_REMAINDER (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV_REMAINDER (rw) register accessor: Divider result remainder + The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. + For signed calculations, REMAINDER is negative only when DIVIDEND is negative. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_remainder`] +module"] pub type DIV_REMAINDER = crate::Reg; #[doc = "Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. @@ -312,145 +484,327 @@ pub type DIV_REMAINDER = crate::Reg; This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] pub mod div_remainder; -#[doc = "DIV_CSR (r) register accessor: an alias for `Reg`"] +#[doc = "DIV_CSR (r) register accessor: Control and status register for divider. + +You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div_csr`] +module"] pub type DIV_CSR = crate::Reg; #[doc = "Control and status register for divider."] pub mod div_csr; -#[doc = "INTERP0_ACCUM0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum0`] +module"] pub type INTERP0_ACCUM0 = crate::Reg; #[doc = "Read/write access to accumulator 0"] pub mod interp0_accum0; -#[doc = "INTERP0_ACCUM1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum1`] +module"] pub type INTERP0_ACCUM1 = crate::Reg; #[doc = "Read/write access to accumulator 1"] pub mod interp0_accum1; -#[doc = "INTERP0_BASE0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base0`] +module"] pub type INTERP0_BASE0 = crate::Reg; #[doc = "Read/write access to BASE0 register."] pub mod interp0_base0; -#[doc = "INTERP0_BASE1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base1`] +module"] pub type INTERP0_BASE1 = crate::Reg; #[doc = "Read/write access to BASE1 register."] pub mod interp0_base1; -#[doc = "INTERP0_BASE2 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base2`] +module"] pub type INTERP0_BASE2 = crate::Reg; #[doc = "Read/write access to BASE2 register."] pub mod interp0_base2; -#[doc = "INTERP0_POP_LANE0 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_lane0`] +module"] pub type INTERP0_POP_LANE0 = crate::Reg; #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_lane0; -#[doc = "INTERP0_POP_LANE1 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_lane1`] +module"] pub type INTERP0_POP_LANE1 = crate::Reg; #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_lane1; -#[doc = "INTERP0_POP_FULL (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_full`] +module"] pub type INTERP0_POP_FULL = crate::Reg; #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_full; -#[doc = "INTERP0_PEEK_LANE0 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_lane0`] +module"] pub type INTERP0_PEEK_LANE0 = crate::Reg; #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] pub mod interp0_peek_lane0; -#[doc = "INTERP0_PEEK_LANE1 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_lane1`] +module"] pub type INTERP0_PEEK_LANE1 = crate::Reg; #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] pub mod interp0_peek_lane1; -#[doc = "INTERP0_PEEK_FULL (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_full`] +module"] pub type INTERP0_PEEK_FULL = crate::Reg; #[doc = "Read FULL result, without altering any internal state (PEEK)."] pub mod interp0_peek_full; -#[doc = "INTERP0_CTRL_LANE0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_ctrl_lane0`] +module"] pub type INTERP0_CTRL_LANE0 = crate::Reg; #[doc = "Control register for lane 0"] pub mod interp0_ctrl_lane0; -#[doc = "INTERP0_CTRL_LANE1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_ctrl_lane1`] +module"] pub type INTERP0_CTRL_LANE1 = crate::Reg; #[doc = "Control register for lane 1"] pub mod interp0_ctrl_lane1; -#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum0_add`] +module"] pub type INTERP0_ACCUM0_ADD = crate::Reg; #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] pub mod interp0_accum0_add; -#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum1_add`] +module"] pub type INTERP0_ACCUM1_ADD = crate::Reg; #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] pub mod interp0_accum1_add; -#[doc = "INTERP0_BASE_1AND0 (w) register accessor: an alias for `Reg`"] +#[doc = "INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base_1and0`] +module"] pub type INTERP0_BASE_1AND0 = crate::Reg; #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] pub mod interp0_base_1and0; -#[doc = "INTERP1_ACCUM0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum0`] +module"] pub type INTERP1_ACCUM0 = crate::Reg; #[doc = "Read/write access to accumulator 0"] pub mod interp1_accum0; -#[doc = "INTERP1_ACCUM1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum1`] +module"] pub type INTERP1_ACCUM1 = crate::Reg; #[doc = "Read/write access to accumulator 1"] pub mod interp1_accum1; -#[doc = "INTERP1_BASE0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base0`] +module"] pub type INTERP1_BASE0 = crate::Reg; #[doc = "Read/write access to BASE0 register."] pub mod interp1_base0; -#[doc = "INTERP1_BASE1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base1`] +module"] pub type INTERP1_BASE1 = crate::Reg; #[doc = "Read/write access to BASE1 register."] pub mod interp1_base1; -#[doc = "INTERP1_BASE2 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register. + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base2`] +module"] pub type INTERP1_BASE2 = crate::Reg; #[doc = "Read/write access to BASE2 register."] pub mod interp1_base2; -#[doc = "INTERP1_POP_LANE0 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_lane0`] +module"] pub type INTERP1_POP_LANE0 = crate::Reg; #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_lane0; -#[doc = "INTERP1_POP_LANE1 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_lane1`] +module"] pub type INTERP1_POP_LANE1 = crate::Reg; #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_lane1; -#[doc = "INTERP1_POP_FULL (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_full`] +module"] pub type INTERP1_POP_FULL = crate::Reg; #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_full; -#[doc = "INTERP1_PEEK_LANE0 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_lane0`] +module"] pub type INTERP1_PEEK_LANE0 = crate::Reg; #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] pub mod interp1_peek_lane0; -#[doc = "INTERP1_PEEK_LANE1 (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_lane1`] +module"] pub type INTERP1_PEEK_LANE1 = crate::Reg; #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] pub mod interp1_peek_lane1; -#[doc = "INTERP1_PEEK_FULL (r) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_full`] +module"] pub type INTERP1_PEEK_FULL = crate::Reg; #[doc = "Read FULL result, without altering any internal state (PEEK)."] pub mod interp1_peek_full; -#[doc = "INTERP1_CTRL_LANE0 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_ctrl_lane0`] +module"] pub type INTERP1_CTRL_LANE0 = crate::Reg; #[doc = "Control register for lane 0"] pub mod interp1_ctrl_lane0; -#[doc = "INTERP1_CTRL_LANE1 (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_ctrl_lane1`] +module"] pub type INTERP1_CTRL_LANE1 = crate::Reg; #[doc = "Control register for lane 1"] pub mod interp1_ctrl_lane1; -#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum0_add`] +module"] pub type INTERP1_ACCUM0_ADD = crate::Reg; #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] pub mod interp1_accum0_add; -#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum1_add`] +module"] pub type INTERP1_ACCUM1_ADD = crate::Reg; #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] pub mod interp1_accum1_add; -#[doc = "INTERP1_BASE_1AND0 (w) register accessor: an alias for `Reg`"] +#[doc = "INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base_1and0`] +module"] pub type INTERP1_BASE_1AND0 = crate::Reg; #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] pub mod interp1_base_1and0; -#[doc = "SPINLOCK (rw) register accessor: an alias for `Reg`"] +#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spinlock`] +module"] pub type SPINLOCK = crate::Reg; #[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked diff --git a/src/sio/cpuid.rs b/src/sio/cpuid.rs index dde26603e..0ccade8d8 100644 --- a/src/sio/cpuid.rs +++ b/src/sio/cpuid.rs @@ -1,18 +1,5 @@ #[doc = "Register `CPUID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Processor core identifier Value is 0 when read from processor core 0, and 1 when read from processor core 1. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [cpuid](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPUID_SPEC; impl crate::RegisterSpec for CPUID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cpuid::R](R) reader structure"] -impl crate::Readable for CPUID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] +impl crate::Readable for CPUID_SPEC {} #[doc = "`reset()` method sets CPUID to value 0"] impl crate::Resettable for CPUID_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/div_csr.rs b/src/sio/div_csr.rs index 98f369d82..f1d89ff87 100644 --- a/src/sio/div_csr.rs +++ b/src/sio/div_csr.rs @@ -1,18 +1,5 @@ #[doc = "Register `DIV_CSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `READY` reader - Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. @@ -45,17 +32,13 @@ impl R { } #[doc = "Control and status register for divider. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_csr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_CSR_SPEC; impl crate::RegisterSpec for DIV_CSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_csr::R](R) reader structure"] -impl crate::Readable for DIV_CSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`div_csr::R`](R) reader structure"] +impl crate::Readable for DIV_CSR_SPEC {} #[doc = "`reset()` method sets DIV_CSR to value 0x01"] impl crate::Resettable for DIV_CSR_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/src/sio/div_quotient.rs b/src/sio/div_quotient.rs index c8a441af4..d1b605631 100644 --- a/src/sio/div_quotient.rs +++ b/src/sio/div_quotient.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_QUOTIENT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_QUOTIENT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -60,20 +32,15 @@ impl W { Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_quotient](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_QUOTIENT_SPEC; impl crate::RegisterSpec for DIV_QUOTIENT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_quotient::R](R) reader structure"] -impl crate::Readable for DIV_QUOTIENT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_quotient::W](W) writer structure"] +#[doc = "`read()` method returns [`div_quotient::R`](R) reader structure"] +impl crate::Readable for DIV_QUOTIENT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_quotient::W`](W) writer structure"] impl crate::Writable for DIV_QUOTIENT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/div_remainder.rs b/src/sio/div_remainder.rs index c2cec95e9..457cef51b 100644 --- a/src/sio/div_remainder.rs +++ b/src/sio/div_remainder.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_REMAINDER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_REMAINDER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -58,20 +30,15 @@ impl W { This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_remainder](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_REMAINDER_SPEC; impl crate::RegisterSpec for DIV_REMAINDER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_remainder::R](R) reader structure"] -impl crate::Readable for DIV_REMAINDER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_remainder::W](W) writer structure"] +#[doc = "`read()` method returns [`div_remainder::R`](R) reader structure"] +impl crate::Readable for DIV_REMAINDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_remainder::W`](W) writer structure"] impl crate::Writable for DIV_REMAINDER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/div_sdividend.rs b/src/sio/div_sdividend.rs index aee298e77..f4eba3166 100644 --- a/src/sio/div_sdividend.rs +++ b/src/sio/div_sdividend.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_SDIVIDEND` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_SDIVIDEND` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_sdividend](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SDIVIDEND_SPEC; impl crate::RegisterSpec for DIV_SDIVIDEND_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_sdividend::R](R) reader structure"] -impl crate::Readable for DIV_SDIVIDEND_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_sdividend::W](W) writer structure"] +#[doc = "`read()` method returns [`div_sdividend::R`](R) reader structure"] +impl crate::Readable for DIV_SDIVIDEND_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_sdividend::W`](W) writer structure"] impl crate::Writable for DIV_SDIVIDEND_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/div_sdivisor.rs b/src/sio/div_sdivisor.rs index 546875593..ecb0e1fb8 100644 --- a/src/sio/div_sdivisor.rs +++ b/src/sio/div_sdivisor.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_SDIVISOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_SDIVISOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_sdivisor](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SDIVISOR_SPEC; impl crate::RegisterSpec for DIV_SDIVISOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_sdivisor::R](R) reader structure"] -impl crate::Readable for DIV_SDIVISOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_sdivisor::W](W) writer structure"] +#[doc = "`read()` method returns [`div_sdivisor::R`](R) reader structure"] +impl crate::Readable for DIV_SDIVISOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_sdivisor::W`](W) writer structure"] impl crate::Writable for DIV_SDIVISOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/div_udividend.rs b/src/sio/div_udividend.rs index 14e43bd9c..ffa3d7b49 100644 --- a/src/sio/div_udividend.rs +++ b/src/sio/div_udividend.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_UDIVIDEND` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_UDIVIDEND` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -58,20 +30,15 @@ impl W { UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_udividend](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_UDIVIDEND_SPEC; impl crate::RegisterSpec for DIV_UDIVIDEND_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_udividend::R](R) reader structure"] -impl crate::Readable for DIV_UDIVIDEND_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_udividend::W](W) writer structure"] +#[doc = "`read()` method returns [`div_udividend::R`](R) reader structure"] +impl crate::Readable for DIV_UDIVIDEND_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_udividend::W`](W) writer structure"] impl crate::Writable for DIV_UDIVIDEND_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/div_udivisor.rs b/src/sio/div_udivisor.rs index 4e0e9f1f3..73b0fe657 100644 --- a/src/sio/div_udivisor.rs +++ b/src/sio/div_udivisor.rs @@ -1,39 +1,7 @@ #[doc = "Register `DIV_UDIVISOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV_UDIVISOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -58,20 +30,15 @@ impl W { UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [div_udivisor](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_UDIVISOR_SPEC; impl crate::RegisterSpec for DIV_UDIVISOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div_udivisor::R](R) reader structure"] -impl crate::Readable for DIV_UDIVISOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div_udivisor::W](W) writer structure"] +#[doc = "`read()` method returns [`div_udivisor::R`](R) reader structure"] +impl crate::Readable for DIV_UDIVISOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_udivisor::W`](W) writer structure"] impl crate::Writable for DIV_UDIVISOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/fifo_rd.rs b/src/sio/fifo_rd.rs index afa377a25..8ceba1fe9 100644 --- a/src/sio/fifo_rd.rs +++ b/src/sio/fifo_rd.rs @@ -1,18 +1,5 @@ #[doc = "Register `FIFO_RD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read access to this core's RX FIFO -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fifo_rd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_RD_SPEC; impl crate::RegisterSpec for FIFO_RD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo_rd::R](R) reader structure"] -impl crate::Readable for FIFO_RD_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fifo_rd::R`](R) reader structure"] +impl crate::Readable for FIFO_RD_SPEC {} #[doc = "`reset()` method sets FIFO_RD to value 0"] impl crate::Resettable for FIFO_RD_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs index 12dabf644..af5fcff7c 100644 --- a/src/sio/fifo_st.rs +++ b/src/sio/fifo_st.rs @@ -1,39 +1,7 @@ #[doc = "Register `FIFO_ST` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO_ST` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VLD` reader - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"] pub type VLD_R = crate::BitReader; #[doc = "Field `RDY` reader - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"] @@ -41,11 +9,11 @@ pub type RDY_R = crate::BitReader; #[doc = "Field `WOF` reader - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] pub type WOF_R = crate::BitReader; #[doc = "Field `WOF` writer - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] -pub type WOF_W<'a, const O: u8> = crate::BitWriter1C<'a, FIFO_ST_SPEC, O>; +pub type WOF_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ROE` reader - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] pub type ROE_R = crate::BitReader; #[doc = "Field `ROE` writer - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] -pub type ROE_W<'a, const O: u8> = crate::BitWriter1C<'a, FIFO_ST_SPEC, O>; +pub type ROE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"] #[inline(always)] @@ -72,19 +40,23 @@ impl W { #[doc = "Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] #[inline(always)] #[must_use] - pub fn wof(&mut self) -> WOF_W<2> { + pub fn wof(&mut self) -> WOF_W { WOF_W::new(self) } #[doc = "Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] #[inline(always)] #[must_use] - pub fn roe(&mut self) -> ROE_W<3> { + pub fn roe(&mut self) -> ROE_W { ROE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -94,20 +66,15 @@ impl W { Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fifo_st](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_ST_SPEC; impl crate::RegisterSpec for FIFO_ST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo_st::R](R) reader structure"] -impl crate::Readable for FIFO_ST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo_st::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"] +impl crate::Readable for FIFO_ST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_st::W`](W) writer structure"] impl crate::Writable for FIFO_ST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0c; } diff --git a/src/sio/fifo_wr.rs b/src/sio/fifo_wr.rs index e6945d028..cf04d212a 100644 --- a/src/sio/fifo_wr.rs +++ b/src/sio/fifo_wr.rs @@ -1,49 +1,31 @@ #[doc = "Register `FIFO_WR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Write access to this core's TX FIFO -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [fifo_wr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_WR_SPEC; impl crate::RegisterSpec for FIFO_WR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fifo_wr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fifo_wr::W`](W) writer structure"] impl crate::Writable for FIFO_WR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_in.rs b/src/sio/gpio_hi_in.rs index 2eae47775..11a51c58b 100644 --- a/src/sio/gpio_hi_in.rs +++ b/src/sio/gpio_hi_in.rs @@ -1,18 +1,5 @@ #[doc = "Register `GPIO_HI_IN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO_HI_IN` reader - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3"] pub type GPIO_HI_IN_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Input value for QSPI pins -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_in](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_IN_SPEC; impl crate::RegisterSpec for GPIO_HI_IN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_hi_in::R](R) reader structure"] -impl crate::Readable for GPIO_HI_IN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gpio_hi_in::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_IN_SPEC {} #[doc = "`reset()` method sets GPIO_HI_IN to value 0"] impl crate::Resettable for GPIO_HI_IN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs index c654d3aae..ebfdd5582 100644 --- a/src/sio/gpio_hi_oe.rs +++ b/src/sio/gpio_hi_oe.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_HI_OE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_HI_OE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OE` reader - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), @@ -45,7 +13,7 @@ pub type GPIO_HI_OE_R = crate::FieldReader; If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] -pub type GPIO_HI_OE_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OE_SPEC, 6, O>; +pub type GPIO_HI_OE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. @@ -65,32 +33,31 @@ impl W { and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] - pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W<0> { + pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W { GPIO_HI_OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_oe](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_hi_oe::R](R) reader structure"] -impl crate::Readable for GPIO_HI_OE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_hi_oe::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_hi_oe::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/sio/gpio_hi_oe_clr.rs index d96de456d..b31a19139 100644 --- a/src/sio/gpio_hi_oe_clr.rs +++ b/src/sio/gpio_hi_oe_clr.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OE_CLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_CLR` writer - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"] -pub type GPIO_HI_OE_CLR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OE_CLR_SPEC, 6, O>; +pub type GPIO_HI_OE_CLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_oe_clr(&mut self) -> GPIO_HI_OE_CLR_W<0> { + pub fn gpio_hi_oe_clr(&mut self) -> GPIO_HI_OE_CLR_W { GPIO_HI_OE_CLR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output enable clear -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_oe_clr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_CLR_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_CLR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_oe_clr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_CLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_oe_set.rs b/src/sio/gpio_hi_oe_set.rs index 716f9359c..4f754a08b 100644 --- a/src/sio/gpio_hi_oe_set.rs +++ b/src/sio/gpio_hi_oe_set.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OE_SET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_SET` writer - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`"] -pub type GPIO_HI_OE_SET_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OE_SET_SPEC, 6, O>; +pub type GPIO_HI_OE_SET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_oe_set(&mut self) -> GPIO_HI_OE_SET_W<0> { + pub fn gpio_hi_oe_set(&mut self) -> GPIO_HI_OE_SET_W { GPIO_HI_OE_SET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output enable set -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_oe_set](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_SET_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_SET_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_oe_set::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_SET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/sio/gpio_hi_oe_xor.rs index 07f8e5e95..35e174da2 100644 --- a/src/sio/gpio_hi_oe_xor.rs +++ b/src/sio/gpio_hi_oe_xor.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OE_XOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_XOR` writer - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`"] -pub type GPIO_HI_OE_XOR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OE_XOR_SPEC, 6, O>; +pub type GPIO_HI_OE_XOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_oe_xor(&mut self) -> GPIO_HI_OE_XOR_W<0> { + pub fn gpio_hi_oe_xor(&mut self) -> GPIO_HI_OE_XOR_W { GPIO_HI_OE_XOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output enable XOR -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_oe_xor](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_XOR_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_XOR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_oe_xor::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_XOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs index 86a515e49..541b64f8f 100644 --- a/src/sio/gpio_hi_out.rs +++ b/src/sio/gpio_hi_out.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_HI_OUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_HI_OUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT` reader - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), @@ -45,7 +13,7 @@ pub type GPIO_HI_OUT_R = crate::FieldReader; If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] -pub type GPIO_HI_OUT_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OUT_SPEC, 6, O>; +pub type GPIO_HI_OUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. @@ -65,32 +33,31 @@ impl W { and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] - pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W<0> { + pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W { GPIO_HI_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output value -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_out](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_hi_out::R](R) reader structure"] -impl crate::Readable for GPIO_HI_OUT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_hi_out::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_hi_out::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_out_clr.rs b/src/sio/gpio_hi_out_clr.rs index 7513f025b..e95b86069 100644 --- a/src/sio/gpio_hi_out_clr.rs +++ b/src/sio/gpio_hi_out_clr.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OUT_CLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"] -pub type GPIO_HI_OUT_CLR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OUT_CLR_SPEC, 6, O>; +pub type GPIO_HI_OUT_CLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_out_clr(&mut self) -> GPIO_HI_OUT_CLR_W<0> { + pub fn gpio_hi_out_clr(&mut self) -> GPIO_HI_OUT_CLR_W { GPIO_HI_OUT_CLR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output value clear -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_out_clr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_CLR_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_CLR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_out_clr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_CLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_out_set.rs b/src/sio/gpio_hi_out_set.rs index 806a96b2a..84c491dab 100644 --- a/src/sio/gpio_hi_out_set.rs +++ b/src/sio/gpio_hi_out_set.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OUT_SET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_SET` writer - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`"] -pub type GPIO_HI_OUT_SET_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OUT_SET_SPEC, 6, O>; +pub type GPIO_HI_OUT_SET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_out_set(&mut self) -> GPIO_HI_OUT_SET_W<0> { + pub fn gpio_hi_out_set(&mut self) -> GPIO_HI_OUT_SET_W { GPIO_HI_OUT_SET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output value set -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_out_set](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_SET_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_SET_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_out_set::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_SET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_hi_out_xor.rs b/src/sio/gpio_hi_out_xor.rs index b72aaa48f..238adfbb5 100644 --- a/src/sio/gpio_hi_out_xor.rs +++ b/src/sio/gpio_hi_out_xor.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_HI_OUT_XOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_XOR` writer - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`"] -pub type GPIO_HI_OUT_XOR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_HI_OUT_XOR_SPEC, 6, O>; +pub type GPIO_HI_OUT_XOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl W { #[doc = "Bits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_hi_out_xor(&mut self) -> GPIO_HI_OUT_XOR_W<0> { + pub fn gpio_hi_out_xor(&mut self) -> GPIO_HI_OUT_XOR_W { GPIO_HI_OUT_XOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "QSPI output value XOR -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_hi_out_xor](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_XOR_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_XOR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_hi_out_xor::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_XOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_in.rs b/src/sio/gpio_in.rs index ef840f4a1..9faa5d454 100644 --- a/src/sio/gpio_in.rs +++ b/src/sio/gpio_in.rs @@ -1,18 +1,5 @@ #[doc = "Register `GPIO_IN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GPIO_IN` reader - Input value for GPIO0...29"] pub type GPIO_IN_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Input value for GPIO pins -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_in](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_IN_SPEC; impl crate::RegisterSpec for GPIO_IN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_in::R](R) reader structure"] -impl crate::Readable for GPIO_IN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gpio_in::R`](R) reader structure"] +impl crate::Readable for GPIO_IN_SPEC {} #[doc = "`reset()` method sets GPIO_IN to value 0"] impl crate::Resettable for GPIO_IN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs index 6d5367fbb..d7c4177ee 100644 --- a/src/sio/gpio_oe.rs +++ b/src/sio/gpio_oe.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_OE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_OE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OE` reader - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), @@ -45,7 +13,7 @@ pub type GPIO_OE_R = crate::FieldReader; If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] -pub type GPIO_OE_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OE_SPEC, 30, O, u32>; +pub type GPIO_OE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. @@ -65,32 +33,31 @@ impl W { and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] - pub fn gpio_oe(&mut self) -> GPIO_OE_W<0> { + pub fn gpio_oe(&mut self) -> GPIO_OE_W { GPIO_OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_oe](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_SPEC; impl crate::RegisterSpec for GPIO_OE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_oe::R](R) reader structure"] -impl crate::Readable for GPIO_OE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_oe::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_oe::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_oe::W`](W) writer structure"] impl crate::Writable for GPIO_OE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_oe_clr.rs b/src/sio/gpio_oe_clr.rs index 7019365a5..8c92ed2aa 100644 --- a/src/sio/gpio_oe_clr.rs +++ b/src/sio/gpio_oe_clr.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OE_CLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OE_CLR` writer - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"] -pub type GPIO_OE_CLR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OE_CLR_SPEC, 30, O, u32>; +pub type GPIO_OE_CLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"] #[inline(always)] #[must_use] - pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W<0> { + pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W { GPIO_OE_CLR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output enable clear -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_oe_clr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_CLR_SPEC; impl crate::RegisterSpec for GPIO_OE_CLR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_oe_clr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OE_CLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_oe_set.rs b/src/sio/gpio_oe_set.rs index f570a702c..94abc7b39 100644 --- a/src/sio/gpio_oe_set.rs +++ b/src/sio/gpio_oe_set.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OE_SET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OE_SET` writer - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"] -pub type GPIO_OE_SET_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OE_SET_SPEC, 30, O, u32>; +pub type GPIO_OE_SET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W<0> { + pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W { GPIO_OE_SET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output enable set -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_oe_set](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_SET_SPEC; impl crate::RegisterSpec for GPIO_OE_SET_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_oe_set::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_OE_SET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_oe_xor.rs b/src/sio/gpio_oe_xor.rs index ef4a80d87..7b58dc153 100644 --- a/src/sio/gpio_oe_xor.rs +++ b/src/sio/gpio_oe_xor.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OE_XOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OE_XOR` writer - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"] -pub type GPIO_OE_XOR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OE_XOR_SPEC, 30, O, u32>; +pub type GPIO_OE_XOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W<0> { + pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W { GPIO_OE_XOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output enable XOR -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_oe_xor](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_XOR_SPEC; impl crate::RegisterSpec for GPIO_OE_XOR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_oe_xor::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OE_XOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs index 4f7df7058..9153968a6 100644 --- a/src/sio/gpio_out.rs +++ b/src/sio/gpio_out.rs @@ -1,39 +1,7 @@ #[doc = "Register `GPIO_OUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_OUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OUT` reader - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), @@ -45,7 +13,7 @@ pub type GPIO_OUT_R = crate::FieldReader; If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] -pub type GPIO_OUT_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OUT_SPEC, 30, O, u32>; +pub type GPIO_OUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. @@ -65,32 +33,31 @@ impl W { and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] - pub fn gpio_out(&mut self) -> GPIO_OUT_W<0> { + pub fn gpio_out(&mut self) -> GPIO_OUT_W { GPIO_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output value -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_out](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_SPEC; impl crate::RegisterSpec for GPIO_OUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_out::R](R) reader structure"] -impl crate::Readable for GPIO_OUT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_out::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_out::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_out::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_out_clr.rs b/src/sio/gpio_out_clr.rs index b1563744f..2df72de3c 100644 --- a/src/sio/gpio_out_clr.rs +++ b/src/sio/gpio_out_clr.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OUT_CLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"] -pub type GPIO_OUT_CLR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OUT_CLR_SPEC, 30, O, u32>; +pub type GPIO_OUT_CLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"] #[inline(always)] #[must_use] - pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W<0> { + pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W { GPIO_OUT_CLR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output value clear -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_out_clr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_CLR_SPEC; impl crate::RegisterSpec for GPIO_OUT_CLR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_out_clr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_CLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_out_set.rs b/src/sio/gpio_out_set.rs index aa457c9bf..e3be66e34 100644 --- a/src/sio/gpio_out_set.rs +++ b/src/sio/gpio_out_set.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OUT_SET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OUT_SET` writer - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"] -pub type GPIO_OUT_SET_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OUT_SET_SPEC, 30, O, u32>; +pub type GPIO_OUT_SET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W<0> { + pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W { GPIO_OUT_SET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output value set -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_out_set](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_SET_SPEC; impl crate::RegisterSpec for GPIO_OUT_SET_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_out_set::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_SET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/gpio_out_xor.rs b/src/sio/gpio_out_xor.rs index 305f62a61..962a930e8 100644 --- a/src/sio/gpio_out_xor.rs +++ b/src/sio/gpio_out_xor.rs @@ -1,52 +1,34 @@ #[doc = "Register `GPIO_OUT_XOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_OUT_XOR` writer - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"] -pub type GPIO_OUT_XOR_W<'a, const O: u8> = crate::FieldWriter<'a, GPIO_OUT_XOR_SPEC, 30, O, u32>; +pub type GPIO_OUT_XOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl W { #[doc = "Bits 0:29 - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"] #[inline(always)] #[must_use] - pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W<0> { + pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W { GPIO_OUT_XOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "GPIO output value XOR -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gpio_out_xor](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_XOR_SPEC; impl crate::RegisterSpec for GPIO_OUT_XOR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpio_out_xor::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpio_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_XOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_accum0.rs b/src/sio/interp0_accum0.rs index ad2b152d7..a46ba10ad 100644 --- a/src/sio/interp0_accum0.rs +++ b/src/sio/interp0_accum0.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP0_ACCUM0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to accumulator 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_accum0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM0_SPEC; impl crate::RegisterSpec for INTERP0_ACCUM0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_accum0::R](R) reader structure"] -impl crate::Readable for INTERP0_ACCUM0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_accum0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_accum0::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum0::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs index 203b4c5a2..94f188900 100644 --- a/src/sio/interp0_accum0_add.rs +++ b/src/sio/interp0_accum0_add.rs @@ -1,44 +1,11 @@ #[doc = "Register `INTERP0_ACCUM0_ADD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM0_ADD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERP0_ACCUM0_ADD` reader - "] pub type INTERP0_ACCUM0_ADD_R = crate::FieldReader; #[doc = "Field `INTERP0_ACCUM0_ADD` writer - "] -pub type INTERP0_ACCUM0_ADD_W<'a, const O: u8> = - crate::FieldWriter<'a, INTERP0_ACCUM0_ADD_SPEC, 24, O, u32>; +pub type INTERP0_ACCUM0_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23"] #[inline(always)] @@ -50,33 +17,32 @@ impl W { #[doc = "Bits 0:23"] #[inline(always)] #[must_use] - pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W<0> { + pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W { INTERP0_ACCUM0_ADD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_accum0_add](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM0_ADD_SPEC; impl crate::RegisterSpec for INTERP0_ACCUM0_ADD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_accum0_add::R](R) reader structure"] -impl crate::Readable for INTERP0_ACCUM0_ADD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_accum0_add::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_accum0_add::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM0_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum0_add::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM0_ADD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_accum1.rs b/src/sio/interp0_accum1.rs index 2233bb61a..784c595cd 100644 --- a/src/sio/interp0_accum1.rs +++ b/src/sio/interp0_accum1.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP0_ACCUM1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to accumulator 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_accum1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM1_SPEC; impl crate::RegisterSpec for INTERP0_ACCUM1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_accum1::R](R) reader structure"] -impl crate::Readable for INTERP0_ACCUM1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_accum1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_accum1::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum1::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs index 2cc7a3bc9..d811092cb 100644 --- a/src/sio/interp0_accum1_add.rs +++ b/src/sio/interp0_accum1_add.rs @@ -1,44 +1,11 @@ #[doc = "Register `INTERP0_ACCUM1_ADD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM1_ADD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERP0_ACCUM1_ADD` reader - "] pub type INTERP0_ACCUM1_ADD_R = crate::FieldReader; #[doc = "Field `INTERP0_ACCUM1_ADD` writer - "] -pub type INTERP0_ACCUM1_ADD_W<'a, const O: u8> = - crate::FieldWriter<'a, INTERP0_ACCUM1_ADD_SPEC, 24, O, u32>; +pub type INTERP0_ACCUM1_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23"] #[inline(always)] @@ -50,33 +17,32 @@ impl W { #[doc = "Bits 0:23"] #[inline(always)] #[must_use] - pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W<0> { + pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W { INTERP0_ACCUM1_ADD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_accum1_add](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM1_ADD_SPEC; impl crate::RegisterSpec for INTERP0_ACCUM1_ADD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_accum1_add::R](R) reader structure"] -impl crate::Readable for INTERP0_ACCUM1_ADD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_accum1_add::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_accum1_add::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM1_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum1_add::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM1_ADD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_base0.rs b/src/sio/interp0_base0.rs index b96df0ead..9fe3d2531 100644 --- a/src/sio/interp0_base0.rs +++ b/src/sio/interp0_base0.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP0_BASE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_BASE0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE0 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_base0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_BASE0_SPEC; impl crate::RegisterSpec for INTERP0_BASE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_base0::R](R) reader structure"] -impl crate::Readable for INTERP0_BASE0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_base0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_base0::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base0::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_base1.rs b/src/sio/interp0_base1.rs index a039541df..830d4e9fe 100644 --- a/src/sio/interp0_base1.rs +++ b/src/sio/interp0_base1.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP0_BASE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_BASE1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE1 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_base1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_BASE1_SPEC; impl crate::RegisterSpec for INTERP0_BASE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_base1::R](R) reader structure"] -impl crate::Readable for INTERP0_BASE1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_base1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_base1::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base1::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_base2.rs b/src/sio/interp0_base2.rs index 6957bc9d3..3064d8173 100644 --- a/src/sio/interp0_base2.rs +++ b/src/sio/interp0_base2.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP0_BASE2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_BASE2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE2 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_base2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_BASE2_SPEC; impl crate::RegisterSpec for INTERP0_BASE2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_base2::R](R) reader structure"] -impl crate::Readable for INTERP0_BASE2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_base2::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_base2::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base2::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_base_1and0.rs b/src/sio/interp0_base_1and0.rs index 31855fbf3..c58cd11ae 100644 --- a/src/sio/interp0_base_1and0.rs +++ b/src/sio/interp0_base_1and0.rs @@ -1,50 +1,32 @@ #[doc = "Register `INTERP0_BASE_1AND0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_base_1and0](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_BASE_1AND0_SPEC; impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [interp0_base_1and0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`interp0_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE_1AND0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs index 55d13f21b..ca5b6eeaf 100644 --- a/src/sio/interp0_ctrl_lane0.rs +++ b/src/sio/interp0_ctrl_lane0.rs @@ -1,73 +1,41 @@ #[doc = "Register `INTERP0_CTRL_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_CTRL_LANE0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub type SHIFT_R = crate::FieldReader; #[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"] -pub type SHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE0_SPEC, 5, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] -pub type MASK_LSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE0_SPEC, 5, O>; +pub type MASK_LSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; #[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] -pub type MASK_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE0_SPEC, 5, O>; +pub type MASK_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; #[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] -pub type SIGNED_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE0_SPEC, O>; +pub type SIGNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; #[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] -pub type CROSS_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE0_SPEC, O>; +pub type CROSS_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; #[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] -pub type CROSS_RESULT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE0_SPEC, O>; +pub type CROSS_RESULT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] -pub type ADD_RAW_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE0_SPEC, O>; +pub type ADD_RAW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] @@ -75,7 +43,7 @@ pub type FORCE_MSB_R = crate::FieldReader; #[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] -pub type FORCE_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE0_SPEC, 2, O>; +pub type FORCE_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `BLEND` reader - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between @@ -91,7 +59,7 @@ pub type BLEND_R = crate::BitReader; - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] -pub type BLEND_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE0_SPEC, O>; +pub type BLEND_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub type OVERF0_R = crate::BitReader; #[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] @@ -175,46 +143,46 @@ impl W { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<0> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] #[inline(always)] #[must_use] - pub fn mask_lsb(&mut self) -> MASK_LSB_W<5> { + pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self) } #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] - pub fn mask_msb(&mut self) -> MASK_MSB_W<10> { + pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self) } #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] - pub fn signed(&mut self) -> SIGNED_W<15> { + pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self) } #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] - pub fn cross_input(&mut self) -> CROSS_INPUT_W<16> { + pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W::new(self) } #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] #[inline(always)] #[must_use] - pub fn cross_result(&mut self) -> CROSS_RESULT_W<17> { + pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W::new(self) } #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] #[inline(always)] #[must_use] - pub fn add_raw(&mut self) -> ADD_RAW_W<18> { + pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self) } #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. @@ -222,7 +190,7 @@ impl W { of pointers into flash or SRAM."] #[inline(always)] #[must_use] - pub fn force_msb(&mut self) -> FORCE_MSB_W<19> { + pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self) } #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: @@ -234,32 +202,31 @@ impl W { LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] #[inline(always)] #[must_use] - pub fn blend(&mut self) -> BLEND_W<21> { + pub fn blend(&mut self) -> BLEND_W { BLEND_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register for lane 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_ctrl_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_CTRL_LANE0_SPEC; impl crate::RegisterSpec for INTERP0_CTRL_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_ctrl_lane0::R](R) reader structure"] -impl crate::Readable for INTERP0_CTRL_LANE0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_ctrl_lane0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_ctrl_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_CTRL_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane0::W`](W) writer structure"] impl crate::Writable for INTERP0_CTRL_LANE0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs index ab476b380..2c8f6f976 100644 --- a/src/sio/interp0_ctrl_lane1.rs +++ b/src/sio/interp0_ctrl_lane1.rs @@ -1,73 +1,41 @@ #[doc = "Register `INTERP0_CTRL_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP0_CTRL_LANE1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub type SHIFT_R = crate::FieldReader; #[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"] -pub type SHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE1_SPEC, 5, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] -pub type MASK_LSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE1_SPEC, 5, O>; +pub type MASK_LSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; #[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] -pub type MASK_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE1_SPEC, 5, O>; +pub type MASK_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; #[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] -pub type SIGNED_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE1_SPEC, O>; +pub type SIGNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; #[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] -pub type CROSS_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE1_SPEC, O>; +pub type CROSS_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; #[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] -pub type CROSS_RESULT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE1_SPEC, O>; +pub type CROSS_RESULT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] -pub type ADD_RAW_W<'a, const O: u8> = crate::BitWriter<'a, INTERP0_CTRL_LANE1_SPEC, O>; +pub type ADD_RAW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] @@ -75,7 +43,7 @@ pub type FORCE_MSB_R = crate::FieldReader; #[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] -pub type FORCE_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP0_CTRL_LANE1_SPEC, 2, O>; +pub type FORCE_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] @@ -127,46 +95,46 @@ impl W { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<0> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] #[inline(always)] #[must_use] - pub fn mask_lsb(&mut self) -> MASK_LSB_W<5> { + pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self) } #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] - pub fn mask_msb(&mut self) -> MASK_MSB_W<10> { + pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self) } #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] - pub fn signed(&mut self) -> SIGNED_W<15> { + pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self) } #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] - pub fn cross_input(&mut self) -> CROSS_INPUT_W<16> { + pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W::new(self) } #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] #[inline(always)] #[must_use] - pub fn cross_result(&mut self) -> CROSS_RESULT_W<17> { + pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W::new(self) } #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] #[inline(always)] #[must_use] - pub fn add_raw(&mut self) -> ADD_RAW_W<18> { + pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self) } #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. @@ -174,32 +142,31 @@ impl W { of pointers into flash or SRAM."] #[inline(always)] #[must_use] - pub fn force_msb(&mut self) -> FORCE_MSB_W<19> { + pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register for lane 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_ctrl_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_CTRL_LANE1_SPEC; impl crate::RegisterSpec for INTERP0_CTRL_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_ctrl_lane1::R](R) reader structure"] -impl crate::Readable for INTERP0_CTRL_LANE1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp0_ctrl_lane1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp0_ctrl_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_CTRL_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane1::W`](W) writer structure"] impl crate::Writable for INTERP0_CTRL_LANE1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp0_peek_full.rs b/src/sio/interp0_peek_full.rs index 9b752557c..b665b3ac0 100644 --- a/src/sio/interp0_peek_full.rs +++ b/src/sio/interp0_peek_full.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_PEEK_FULL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read FULL result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_peek_full](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_FULL_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_FULL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_peek_full::R](R) reader structure"] -impl crate::Readable for INTERP0_PEEK_FULL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_peek_full::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_FULL_SPEC {} #[doc = "`reset()` method sets INTERP0_PEEK_FULL to value 0"] impl crate::Resettable for INTERP0_PEEK_FULL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp0_peek_lane0.rs b/src/sio/interp0_peek_lane0.rs index d676d794f..361c2ddd4 100644 --- a/src/sio/interp0_peek_lane0.rs +++ b/src/sio/interp0_peek_lane0.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_PEEK_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE0 result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_peek_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_LANE0_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_peek_lane0::R](R) reader structure"] -impl crate::Readable for INTERP0_PEEK_LANE0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_peek_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_LANE0_SPEC {} #[doc = "`reset()` method sets INTERP0_PEEK_LANE0 to value 0"] impl crate::Resettable for INTERP0_PEEK_LANE0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp0_peek_lane1.rs b/src/sio/interp0_peek_lane1.rs index 7debd0f7f..84e509bab 100644 --- a/src/sio/interp0_peek_lane1.rs +++ b/src/sio/interp0_peek_lane1.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_PEEK_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE1 result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_peek_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_LANE1_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_peek_lane1::R](R) reader structure"] -impl crate::Readable for INTERP0_PEEK_LANE1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_peek_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_LANE1_SPEC {} #[doc = "`reset()` method sets INTERP0_PEEK_LANE1 to value 0"] impl crate::Resettable for INTERP0_PEEK_LANE1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp0_pop_full.rs b/src/sio/interp0_pop_full.rs index 20c92e2e8..3866c23f4 100644 --- a/src/sio/interp0_pop_full.rs +++ b/src/sio/interp0_pop_full.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_POP_FULL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_pop_full](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_FULL_SPEC; impl crate::RegisterSpec for INTERP0_POP_FULL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_pop_full::R](R) reader structure"] -impl crate::Readable for INTERP0_POP_FULL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_pop_full::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_FULL_SPEC {} #[doc = "`reset()` method sets INTERP0_POP_FULL to value 0"] impl crate::Resettable for INTERP0_POP_FULL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp0_pop_lane0.rs b/src/sio/interp0_pop_lane0.rs index 1359db580..4da9bd6bb 100644 --- a/src/sio/interp0_pop_lane0.rs +++ b/src/sio/interp0_pop_lane0.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_POP_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_pop_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_LANE0_SPEC; impl crate::RegisterSpec for INTERP0_POP_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_pop_lane0::R](R) reader structure"] -impl crate::Readable for INTERP0_POP_LANE0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_pop_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_LANE0_SPEC {} #[doc = "`reset()` method sets INTERP0_POP_LANE0 to value 0"] impl crate::Resettable for INTERP0_POP_LANE0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp0_pop_lane1.rs b/src/sio/interp0_pop_lane1.rs index 4f811151e..4b755df5f 100644 --- a/src/sio/interp0_pop_lane1.rs +++ b/src/sio/interp0_pop_lane1.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP0_POP_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp0_pop_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_LANE1_SPEC; impl crate::RegisterSpec for INTERP0_POP_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp0_pop_lane1::R](R) reader structure"] -impl crate::Readable for INTERP0_POP_LANE1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp0_pop_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_LANE1_SPEC {} #[doc = "`reset()` method sets INTERP0_POP_LANE1 to value 0"] impl crate::Resettable for INTERP0_POP_LANE1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_accum0.rs b/src/sio/interp1_accum0.rs index 0eb522634..61af50709 100644 --- a/src/sio/interp1_accum0.rs +++ b/src/sio/interp1_accum0.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP1_ACCUM0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to accumulator 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_accum0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM0_SPEC; impl crate::RegisterSpec for INTERP1_ACCUM0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_accum0::R](R) reader structure"] -impl crate::Readable for INTERP1_ACCUM0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_accum0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_accum0::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum0::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs index b928b5939..32a93ce4a 100644 --- a/src/sio/interp1_accum0_add.rs +++ b/src/sio/interp1_accum0_add.rs @@ -1,44 +1,11 @@ #[doc = "Register `INTERP1_ACCUM0_ADD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM0_ADD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERP1_ACCUM0_ADD` reader - "] pub type INTERP1_ACCUM0_ADD_R = crate::FieldReader; #[doc = "Field `INTERP1_ACCUM0_ADD` writer - "] -pub type INTERP1_ACCUM0_ADD_W<'a, const O: u8> = - crate::FieldWriter<'a, INTERP1_ACCUM0_ADD_SPEC, 24, O, u32>; +pub type INTERP1_ACCUM0_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23"] #[inline(always)] @@ -50,33 +17,32 @@ impl W { #[doc = "Bits 0:23"] #[inline(always)] #[must_use] - pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W<0> { + pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W { INTERP1_ACCUM0_ADD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_accum0_add](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM0_ADD_SPEC; impl crate::RegisterSpec for INTERP1_ACCUM0_ADD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_accum0_add::R](R) reader structure"] -impl crate::Readable for INTERP1_ACCUM0_ADD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_accum0_add::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_accum0_add::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM0_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum0_add::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM0_ADD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_accum1.rs b/src/sio/interp1_accum1.rs index 09d91b2a1..61cc25f6a 100644 --- a/src/sio/interp1_accum1.rs +++ b/src/sio/interp1_accum1.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP1_ACCUM1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to accumulator 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_accum1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM1_SPEC; impl crate::RegisterSpec for INTERP1_ACCUM1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_accum1::R](R) reader structure"] -impl crate::Readable for INTERP1_ACCUM1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_accum1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_accum1::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum1::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs index 617f80588..f6af5e1f2 100644 --- a/src/sio/interp1_accum1_add.rs +++ b/src/sio/interp1_accum1_add.rs @@ -1,44 +1,11 @@ #[doc = "Register `INTERP1_ACCUM1_ADD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM1_ADD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERP1_ACCUM1_ADD` reader - "] pub type INTERP1_ACCUM1_ADD_R = crate::FieldReader; #[doc = "Field `INTERP1_ACCUM1_ADD` writer - "] -pub type INTERP1_ACCUM1_ADD_W<'a, const O: u8> = - crate::FieldWriter<'a, INTERP1_ACCUM1_ADD_SPEC, 24, O, u32>; +pub type INTERP1_ACCUM1_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23"] #[inline(always)] @@ -50,33 +17,32 @@ impl W { #[doc = "Bits 0:23"] #[inline(always)] #[must_use] - pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W<0> { + pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W { INTERP1_ACCUM1_ADD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_accum1_add](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM1_ADD_SPEC; impl crate::RegisterSpec for INTERP1_ACCUM1_ADD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_accum1_add::R](R) reader structure"] -impl crate::Readable for INTERP1_ACCUM1_ADD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_accum1_add::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_accum1_add::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM1_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum1_add::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM1_ADD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_base0.rs b/src/sio/interp1_base0.rs index 61e9e3ab5..01349190d 100644 --- a/src/sio/interp1_base0.rs +++ b/src/sio/interp1_base0.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP1_BASE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_BASE0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE0 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_base0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_BASE0_SPEC; impl crate::RegisterSpec for INTERP1_BASE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_base0::R](R) reader structure"] -impl crate::Readable for INTERP1_BASE0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_base0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_base0::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base0::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_base1.rs b/src/sio/interp1_base1.rs index 9994c095a..38f3fc76d 100644 --- a/src/sio/interp1_base1.rs +++ b/src/sio/interp1_base1.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP1_BASE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_BASE1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE1 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_base1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_BASE1_SPEC; impl crate::RegisterSpec for INTERP1_BASE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_base1::R](R) reader structure"] -impl crate::Readable for INTERP1_BASE1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_base1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_base1::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base1::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_base2.rs b/src/sio/interp1_base2.rs index 313b1812b..c252b7deb 100644 --- a/src/sio/interp1_base2.rs +++ b/src/sio/interp1_base2.rs @@ -1,39 +1,7 @@ #[doc = "Register `INTERP1_BASE2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_BASE2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Read/write access to BASE2 register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_base2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_BASE2_SPEC; impl crate::RegisterSpec for INTERP1_BASE2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_base2::R](R) reader structure"] -impl crate::Readable for INTERP1_BASE2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_base2::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_base2::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base2::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_base_1and0.rs b/src/sio/interp1_base_1and0.rs index 7e24defd8..c67a8e166 100644 --- a/src/sio/interp1_base_1and0.rs +++ b/src/sio/interp1_base_1and0.rs @@ -1,50 +1,32 @@ #[doc = "Register `INTERP1_BASE_1AND0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_base_1and0](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_BASE_1AND0_SPEC; impl crate::RegisterSpec for INTERP1_BASE_1AND0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [interp1_base_1and0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`interp1_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE_1AND0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs index 17989bb60..9bb997a6b 100644 --- a/src/sio/interp1_ctrl_lane0.rs +++ b/src/sio/interp1_ctrl_lane0.rs @@ -1,73 +1,41 @@ #[doc = "Register `INTERP1_CTRL_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_CTRL_LANE0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub type SHIFT_R = crate::FieldReader; #[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"] -pub type SHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE0_SPEC, 5, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] -pub type MASK_LSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE0_SPEC, 5, O>; +pub type MASK_LSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; #[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] -pub type MASK_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE0_SPEC, 5, O>; +pub type MASK_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; #[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] -pub type SIGNED_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE0_SPEC, O>; +pub type SIGNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; #[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] -pub type CROSS_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE0_SPEC, O>; +pub type CROSS_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; #[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] -pub type CROSS_RESULT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE0_SPEC, O>; +pub type CROSS_RESULT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] -pub type ADD_RAW_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE0_SPEC, O>; +pub type ADD_RAW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] @@ -75,7 +43,7 @@ pub type FORCE_MSB_R = crate::FieldReader; #[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] -pub type FORCE_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE0_SPEC, 2, O>; +pub type FORCE_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CLAMP` reader - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. @@ -85,7 +53,7 @@ pub type CLAMP_R = crate::BitReader; - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] -pub type CLAMP_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE0_SPEC, O>; +pub type CLAMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub type OVERF0_R = crate::BitReader; #[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] @@ -166,46 +134,46 @@ impl W { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<0> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] #[inline(always)] #[must_use] - pub fn mask_lsb(&mut self) -> MASK_LSB_W<5> { + pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self) } #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] - pub fn mask_msb(&mut self) -> MASK_MSB_W<10> { + pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self) } #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] - pub fn signed(&mut self) -> SIGNED_W<15> { + pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self) } #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] - pub fn cross_input(&mut self) -> CROSS_INPUT_W<16> { + pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W::new(self) } #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] #[inline(always)] #[must_use] - pub fn cross_result(&mut self) -> CROSS_RESULT_W<17> { + pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W::new(self) } #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] #[inline(always)] #[must_use] - pub fn add_raw(&mut self) -> ADD_RAW_W<18> { + pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self) } #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. @@ -213,7 +181,7 @@ impl W { of pointers into flash or SRAM."] #[inline(always)] #[must_use] - pub fn force_msb(&mut self) -> FORCE_MSB_W<19> { + pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self) } #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: @@ -222,32 +190,31 @@ impl W { - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] #[inline(always)] #[must_use] - pub fn clamp(&mut self) -> CLAMP_W<22> { + pub fn clamp(&mut self) -> CLAMP_W { CLAMP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register for lane 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_ctrl_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_CTRL_LANE0_SPEC; impl crate::RegisterSpec for INTERP1_CTRL_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_ctrl_lane0::R](R) reader structure"] -impl crate::Readable for INTERP1_CTRL_LANE0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_ctrl_lane0::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_ctrl_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_CTRL_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane0::W`](W) writer structure"] impl crate::Writable for INTERP1_CTRL_LANE0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs index 503b3fe52..cb069218a 100644 --- a/src/sio/interp1_ctrl_lane1.rs +++ b/src/sio/interp1_ctrl_lane1.rs @@ -1,73 +1,41 @@ #[doc = "Register `INTERP1_CTRL_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERP1_CTRL_LANE1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub type SHIFT_R = crate::FieldReader; #[doc = "Field `SHIFT` writer - Logical right-shift applied to accumulator before masking"] -pub type SHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE1_SPEC, 5, O>; +pub type SHIFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] -pub type MASK_LSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE1_SPEC, 5, O>; +pub type MASK_LSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; #[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] -pub type MASK_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE1_SPEC, 5, O>; +pub type MASK_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; #[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] -pub type SIGNED_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE1_SPEC, O>; +pub type SIGNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; #[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] -pub type CROSS_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE1_SPEC, O>; +pub type CROSS_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; #[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] -pub type CROSS_RESULT_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE1_SPEC, O>; +pub type CROSS_RESULT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] -pub type ADD_RAW_W<'a, const O: u8> = crate::BitWriter<'a, INTERP1_CTRL_LANE1_SPEC, O>; +pub type ADD_RAW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] @@ -75,7 +43,7 @@ pub type FORCE_MSB_R = crate::FieldReader; #[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] -pub type FORCE_MSB_W<'a, const O: u8> = crate::FieldWriter<'a, INTERP1_CTRL_LANE1_SPEC, 2, O>; +pub type FORCE_MSB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] @@ -127,46 +95,46 @@ impl W { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] #[inline(always)] #[must_use] - pub fn shift(&mut self) -> SHIFT_W<0> { + pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self) } #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] #[inline(always)] #[must_use] - pub fn mask_lsb(&mut self) -> MASK_LSB_W<5> { + pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self) } #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] - pub fn mask_msb(&mut self) -> MASK_MSB_W<10> { + pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self) } #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] - pub fn signed(&mut self) -> SIGNED_W<15> { + pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self) } #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] - pub fn cross_input(&mut self) -> CROSS_INPUT_W<16> { + pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W::new(self) } #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] #[inline(always)] #[must_use] - pub fn cross_result(&mut self) -> CROSS_RESULT_W<17> { + pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W::new(self) } #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] #[inline(always)] #[must_use] - pub fn add_raw(&mut self) -> ADD_RAW_W<18> { + pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self) } #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. @@ -174,32 +142,31 @@ impl W { of pointers into flash or SRAM."] #[inline(always)] #[must_use] - pub fn force_msb(&mut self) -> FORCE_MSB_W<19> { + pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register for lane 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_ctrl_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_CTRL_LANE1_SPEC; impl crate::RegisterSpec for INTERP1_CTRL_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_ctrl_lane1::R](R) reader structure"] -impl crate::Readable for INTERP1_CTRL_LANE1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interp1_ctrl_lane1::W](W) writer structure"] +#[doc = "`read()` method returns [`interp1_ctrl_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_CTRL_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane1::W`](W) writer structure"] impl crate::Writable for INTERP1_CTRL_LANE1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/interp1_peek_full.rs b/src/sio/interp1_peek_full.rs index c7d4adfeb..5aedf5ccb 100644 --- a/src/sio/interp1_peek_full.rs +++ b/src/sio/interp1_peek_full.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_PEEK_FULL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read FULL result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_peek_full](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_FULL_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_FULL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_peek_full::R](R) reader structure"] -impl crate::Readable for INTERP1_PEEK_FULL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_peek_full::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_FULL_SPEC {} #[doc = "`reset()` method sets INTERP1_PEEK_FULL to value 0"] impl crate::Resettable for INTERP1_PEEK_FULL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_peek_lane0.rs b/src/sio/interp1_peek_lane0.rs index 8dc4f81ca..85db913f1 100644 --- a/src/sio/interp1_peek_lane0.rs +++ b/src/sio/interp1_peek_lane0.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_PEEK_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE0 result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_peek_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_LANE0_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_peek_lane0::R](R) reader structure"] -impl crate::Readable for INTERP1_PEEK_LANE0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_peek_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_LANE0_SPEC {} #[doc = "`reset()` method sets INTERP1_PEEK_LANE0 to value 0"] impl crate::Resettable for INTERP1_PEEK_LANE0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_peek_lane1.rs b/src/sio/interp1_peek_lane1.rs index 9fc706aac..53e0dacb7 100644 --- a/src/sio/interp1_peek_lane1.rs +++ b/src/sio/interp1_peek_lane1.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_PEEK_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE1 result, without altering any internal state (PEEK). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_peek_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_LANE1_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_peek_lane1::R](R) reader structure"] -impl crate::Readable for INTERP1_PEEK_LANE1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_peek_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_LANE1_SPEC {} #[doc = "`reset()` method sets INTERP1_PEEK_LANE1 to value 0"] impl crate::Resettable for INTERP1_PEEK_LANE1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_pop_full.rs b/src/sio/interp1_pop_full.rs index 6e9f18ce8..62f9f0000 100644 --- a/src/sio/interp1_pop_full.rs +++ b/src/sio/interp1_pop_full.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_POP_FULL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_pop_full](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_FULL_SPEC; impl crate::RegisterSpec for INTERP1_POP_FULL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_pop_full::R](R) reader structure"] -impl crate::Readable for INTERP1_POP_FULL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_pop_full::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_FULL_SPEC {} #[doc = "`reset()` method sets INTERP1_POP_FULL to value 0"] impl crate::Resettable for INTERP1_POP_FULL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_pop_lane0.rs b/src/sio/interp1_pop_lane0.rs index c7084a212..e8e9bdbf5 100644 --- a/src/sio/interp1_pop_lane0.rs +++ b/src/sio/interp1_pop_lane0.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_POP_LANE0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_pop_lane0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_LANE0_SPEC; impl crate::RegisterSpec for INTERP1_POP_LANE0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_pop_lane0::R](R) reader structure"] -impl crate::Readable for INTERP1_POP_LANE0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_pop_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_LANE0_SPEC {} #[doc = "`reset()` method sets INTERP1_POP_LANE0 to value 0"] impl crate::Resettable for INTERP1_POP_LANE0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/interp1_pop_lane1.rs b/src/sio/interp1_pop_lane1.rs index cd18791a1..7337359ea 100644 --- a/src/sio/interp1_pop_lane1.rs +++ b/src/sio/interp1_pop_lane1.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTERP1_POP_LANE1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [interp1_pop_lane1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_LANE1_SPEC; impl crate::RegisterSpec for INTERP1_POP_LANE1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interp1_pop_lane1::R](R) reader structure"] -impl crate::Readable for INTERP1_POP_LANE1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`interp1_pop_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_LANE1_SPEC {} #[doc = "`reset()` method sets INTERP1_POP_LANE1 to value 0"] impl crate::Resettable for INTERP1_POP_LANE1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sio/spinlock.rs b/src/sio/spinlock.rs index 06a67374a..23efd2789 100644 --- a/src/sio/spinlock.rs +++ b/src/sio/spinlock.rs @@ -1,39 +1,7 @@ #[doc = "Register `SPINLOCK%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SPINLOCK%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -60,20 +32,15 @@ impl W { If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [spinlock](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPINLOCK_SPEC; impl crate::RegisterSpec for SPINLOCK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spinlock::R](R) reader structure"] -impl crate::Readable for SPINLOCK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [spinlock::W](W) writer structure"] +#[doc = "`read()` method returns [`spinlock::R`](R) reader structure"] +impl crate::Readable for SPINLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spinlock::W`](W) writer structure"] impl crate::Writable for SPINLOCK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sio/spinlock_st.rs b/src/sio/spinlock_st.rs index 59c5ae7f9..58cbb25ba 100644 --- a/src/sio/spinlock_st.rs +++ b/src/sio/spinlock_st.rs @@ -1,18 +1,5 @@ #[doc = "Register `SPINLOCK_ST` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -27,17 +14,13 @@ impl core::fmt::Debug for crate::generic::Reg { A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [spinlock_st](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPINLOCK_ST_SPEC; impl crate::RegisterSpec for SPINLOCK_ST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spinlock_st::R](R) reader structure"] -impl crate::Readable for SPINLOCK_ST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`spinlock_st::R`](R) reader structure"] +impl crate::Readable for SPINLOCK_ST_SPEC {} #[doc = "`reset()` method sets SPINLOCK_ST to value 0"] impl crate::Resettable for SPINLOCK_ST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/spi0.rs b/src/spi0.rs index ee1151b12..ece53e513 100644 --- a/src/spi0.rs +++ b/src/spi0.rs @@ -39,75 +39,165 @@ pub struct RegisterBlock { #[doc = "0xffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub ssppcellid3: SSPPCELLID3, } -#[doc = "SSPCR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPCR0 (rw) register accessor: Control register 0, SSPCR0 on page 3-4 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspcr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcr0`] +module"] pub type SSPCR0 = crate::Reg; #[doc = "Control register 0, SSPCR0 on page 3-4"] pub mod sspcr0; -#[doc = "SSPCR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPCR1 (rw) register accessor: Control register 1, SSPCR1 on page 3-5 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspcr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcr1`] +module"] pub type SSPCR1 = crate::Reg; #[doc = "Control register 1, SSPCR1 on page 3-5"] pub mod sspcr1; -#[doc = "SSPDR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPDR (rw) register accessor: Data register, SSPDR on page 3-6 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspdr`] +module"] pub type SSPDR = crate::Reg; #[doc = "Data register, SSPDR on page 3-6"] pub mod sspdr; -#[doc = "SSPSR (r) register accessor: an alias for `Reg`"] +#[doc = "SSPSR (r) register accessor: Status register, SSPSR on page 3-7 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspsr`] +module"] pub type SSPSR = crate::Reg; #[doc = "Status register, SSPSR on page 3-7"] pub mod sspsr; -#[doc = "SSPCPSR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPCPSR (rw) register accessor: Clock prescale register, SSPCPSR on page 3-8 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspcpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcpsr`] +module"] pub type SSPCPSR = crate::Reg; #[doc = "Clock prescale register, SSPCPSR on page 3-8"] pub mod sspcpsr; -#[doc = "SSPIMSC (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPIMSC (rw) register accessor: Interrupt mask set or clear register, SSPIMSC on page 3-9 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspimsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspimsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspimsc`] +module"] pub type SSPIMSC = crate::Reg; #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"] pub mod sspimsc; -#[doc = "SSPRIS (r) register accessor: an alias for `Reg`"] +#[doc = "SSPRIS (r) register accessor: Raw interrupt status register, SSPRIS on page 3-10 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspris`] +module"] pub type SSPRIS = crate::Reg; #[doc = "Raw interrupt status register, SSPRIS on page 3-10"] pub mod sspris; -#[doc = "SSPMIS (r) register accessor: an alias for `Reg`"] +#[doc = "SSPMIS (r) register accessor: Masked interrupt status register, SSPMIS on page 3-11 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspmis`] +module"] pub type SSPMIS = crate::Reg; #[doc = "Masked interrupt status register, SSPMIS on page 3-11"] pub mod sspmis; -#[doc = "SSPICR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPICR (rw) register accessor: Interrupt clear register, SSPICR on page 3-11 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspicr`] +module"] pub type SSPICR = crate::Reg; #[doc = "Interrupt clear register, SSPICR on page 3-11"] pub mod sspicr; -#[doc = "SSPDMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPDMACR (rw) register accessor: DMA control register, SSPDMACR on page 3-12 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspdmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspdmacr`] +module"] pub type SSPDMACR = crate::Reg; #[doc = "DMA control register, SSPDMACR on page 3-12"] pub mod sspdmacr; -#[doc = "SSPPERIPHID0 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPERIPHID0 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid0`] +module"] pub type SSPPERIPHID0 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid0; -#[doc = "SSPPERIPHID1 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPERIPHID1 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid1`] +module"] pub type SSPPERIPHID1 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid1; -#[doc = "SSPPERIPHID2 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPERIPHID2 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid2`] +module"] pub type SSPPERIPHID2 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid2; -#[doc = "SSPPERIPHID3 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPERIPHID3 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid3`] +module"] pub type SSPPERIPHID3 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid3; -#[doc = "SSPPCELLID0 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPCELLID0 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid0`] +module"] pub type SSPPCELLID0 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid0; -#[doc = "SSPPCELLID1 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPCELLID1 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid1`] +module"] pub type SSPPCELLID1 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid1; -#[doc = "SSPPCELLID2 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPCELLID2 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid2`] +module"] pub type SSPPCELLID2 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid2; -#[doc = "SSPPCELLID3 (r) register accessor: an alias for `Reg`"] +#[doc = "SSPPCELLID3 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid3`] +module"] pub type SSPPCELLID3 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid3; diff --git a/src/spi0/sspcpsr.rs b/src/spi0/sspcpsr.rs index 7170d591c..e1b6f3dd0 100644 --- a/src/spi0/sspcpsr.rs +++ b/src/spi0/sspcpsr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SSPCPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPCPSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPSDVSR` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `CPSDVSR` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, const O: u8> = crate::FieldWriter<'a, SSPCPSR_SPEC, 8, O>; +pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W<0> { + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { CPSDVSR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Clock prescale register, SSPCPSR on page 3-8 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspcpsr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspcpsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPCPSR_SPEC; impl crate::RegisterSpec for SSPCPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspcpsr::R](R) reader structure"] -impl crate::Readable for SSPCPSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspcpsr::W](W) writer structure"] +#[doc = "`read()` method returns [`sspcpsr::R`](R) reader structure"] +impl crate::Readable for SSPCPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcpsr::W`](W) writer structure"] impl crate::Writable for SSPCPSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs index e7674b1b2..04f04e388 100644 --- a/src/spi0/sspcr0.rs +++ b/src/spi0/sspcr0.rs @@ -1,43 +1,11 @@ #[doc = "Register `SSPCR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPCR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSS` reader - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] pub type DSS_R = crate::FieldReader; #[doc = "Field `DSS` writer - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] -pub type DSS_W<'a, const O: u8> = crate::FieldWriter<'a, SSPCR0_SPEC, 4, O>; +pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FRF` reader - Frame format."] pub type FRF_R = crate::FieldReader; #[doc = "Frame format. @@ -65,7 +33,7 @@ impl crate::FieldSpec for FRF_A { impl FRF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(FRF_A::MOTOROLA), 1 => Some(FRF_A::TEXAS_INSTRUMENTS), @@ -73,53 +41,57 @@ impl FRF_R { _ => None, } } - #[doc = "Checks if the value of the field is `MOTOROLA`"] + #[doc = "Motorola SPI frame format"] #[inline(always)] pub fn is_motorola(&self) -> bool { *self == FRF_A::MOTOROLA } - #[doc = "Checks if the value of the field is `TEXAS_INSTRUMENTS`"] + #[doc = "Texas Instruments synchronous serial frame format"] #[inline(always)] pub fn is_texas_instruments(&self) -> bool { *self == FRF_A::TEXAS_INSTRUMENTS } - #[doc = "Checks if the value of the field is `NATIONAL_SEMICONDUCTOR_MICROWIRE`"] + #[doc = "National Semiconductor Microwire frame format"] #[inline(always)] pub fn is_national_semiconductor_microwire(&self) -> bool { *self == FRF_A::NATIONAL_SEMICONDUCTOR_MICROWIRE } } #[doc = "Field `FRF` writer - Frame format."] -pub type FRF_W<'a, const O: u8> = crate::FieldWriter<'a, SSPCR0_SPEC, 2, O, FRF_A>; -impl<'a, const O: u8> FRF_W<'a, O> { +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, FRF_A>; +impl<'a, REG, const O: u8> FRF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Motorola SPI frame format"] #[inline(always)] - pub fn motorola(self) -> &'a mut W { + pub fn motorola(self) -> &'a mut crate::W { self.variant(FRF_A::MOTOROLA) } #[doc = "Texas Instruments synchronous serial frame format"] #[inline(always)] - pub fn texas_instruments(self) -> &'a mut W { + pub fn texas_instruments(self) -> &'a mut crate::W { self.variant(FRF_A::TEXAS_INSTRUMENTS) } #[doc = "National Semiconductor Microwire frame format"] #[inline(always)] - pub fn national_semiconductor_microwire(self) -> &'a mut W { + pub fn national_semiconductor_microwire(self) -> &'a mut crate::W { self.variant(FRF_A::NATIONAL_SEMICONDUCTOR_MICROWIRE) } } #[doc = "Field `SPO` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] pub type SPO_R = crate::BitReader; #[doc = "Field `SPO` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] -pub type SPO_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR0_SPEC, O>; +pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPH` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] pub type SPH_R = crate::BitReader; #[doc = "Field `SPH` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] -pub type SPH_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR0_SPEC, O>; +pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCR` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] pub type SCR_R = crate::FieldReader; #[doc = "Field `SCR` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] -pub type SCR_W<'a, const O: u8> = crate::FieldWriter<'a, SSPCR0_SPEC, 8, O>; +pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] #[inline(always)] @@ -151,56 +123,55 @@ impl W { #[doc = "Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W<0> { + pub fn dss(&mut self) -> DSS_W { DSS_W::new(self) } #[doc = "Bits 4:5 - Frame format."] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W<4> { + pub fn frf(&mut self) -> FRF_W { FRF_W::new(self) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W<6> { + pub fn spo(&mut self) -> SPO_W { SPO_W::new(self) } #[doc = "Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W<7> { + pub fn sph(&mut self) -> SPH_W { SPH_W::new(self) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W<8> { + pub fn scr(&mut self) -> SCR_W { SCR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register 0, SSPCR0 on page 3-4 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspcr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspcr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPCR0_SPEC; impl crate::RegisterSpec for SSPCR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspcr0::R](R) reader structure"] -impl crate::Readable for SSPCR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspcr0::W](W) writer structure"] +#[doc = "`read()` method returns [`sspcr0::R`](R) reader structure"] +impl crate::Readable for SSPCR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcr0::W`](W) writer structure"] impl crate::Writable for SSPCR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspcr1.rs b/src/spi0/sspcr1.rs index 816c29259..8912bc2ef 100644 --- a/src/spi0/sspcr1.rs +++ b/src/spi0/sspcr1.rs @@ -1,55 +1,23 @@ #[doc = "Register `SSPCR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPCR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LBM` reader - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] pub type LBM_R = crate::BitReader; #[doc = "Field `LBM` writer - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] -pub type LBM_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR1_SPEC, O>; +pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SSE` reader - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] pub type SSE_R = crate::BitReader; #[doc = "Field `SSE` writer - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] -pub type SSE_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR1_SPEC, O>; +pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MS` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] pub type MS_R = crate::BitReader; #[doc = "Field `MS` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] -pub type MS_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR1_SPEC, O>; +pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOD` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] pub type SOD_R = crate::BitReader; #[doc = "Field `SOD` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] -pub type SOD_W<'a, const O: u8> = crate::BitWriter<'a, SSPCR1_SPEC, O>; +pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W<0> { + pub fn lbm(&mut self) -> LBM_W { LBM_W::new(self) } #[doc = "Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W<1> { + pub fn sse(&mut self) -> SSE_W { SSE_W::new(self) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W<2> { + pub fn ms(&mut self) -> MS_W { MS_W::new(self) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W<3> { + pub fn sod(&mut self) -> SOD_W { SOD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register 1, SSPCR1 on page 3-5 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspcr1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspcr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPCR1_SPEC; impl crate::RegisterSpec for SSPCR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspcr1::R](R) reader structure"] -impl crate::Readable for SSPCR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspcr1::W](W) writer structure"] +#[doc = "`read()` method returns [`sspcr1::R`](R) reader structure"] +impl crate::Readable for SSPCR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcr1::W`](W) writer structure"] impl crate::Writable for SSPCR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspdmacr.rs b/src/spi0/sspdmacr.rs index b83d8ccb8..775c9f51e 100644 --- a/src/spi0/sspdmacr.rs +++ b/src/spi0/sspdmacr.rs @@ -1,47 +1,15 @@ #[doc = "Register `SSPDMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPDMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXDMAE` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `RXDMAE` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, SSPDMACR_SPEC, O>; +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMAE` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `TXDMAE` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, SSPDMACR_SPEC, O>; +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + pub fn rxdmae(&mut self) -> RXDMAE_W { RXDMAE_W::new(self) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W<1> { + pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA control register, SSPDMACR on page 3-12 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspdmacr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspdmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPDMACR_SPEC; impl crate::RegisterSpec for SSPDMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspdmacr::R](R) reader structure"] -impl crate::Readable for SSPDMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspdmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`sspdmacr::R`](R) reader structure"] +impl crate::Readable for SSPDMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspdmacr::W`](W) writer structure"] impl crate::Writable for SSPDMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs index d18ef8154..7feeebdd8 100644 --- a/src/spi0/sspdr.rs +++ b/src/spi0/sspdr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SSPDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, SSPDR_SPEC, 16, O, u16>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Data register, SSPDR on page 3-6 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspdr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPDR_SPEC; impl crate::RegisterSpec for SSPDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspdr::R](R) reader structure"] -impl crate::Readable for SSPDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspdr::W](W) writer structure"] +#[doc = "`read()` method returns [`sspdr::R`](R) reader structure"] +impl crate::Readable for SSPDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspdr::W`](W) writer structure"] impl crate::Writable for SSPDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspicr.rs b/src/spi0/sspicr.rs index 513688352..60cf05f93 100644 --- a/src/spi0/sspicr.rs +++ b/src/spi0/sspicr.rs @@ -1,47 +1,15 @@ #[doc = "Register `SSPICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RORIC` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `RORIC` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, const O: u8> = crate::BitWriter1C<'a, SSPICR_SPEC, O>; +pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RTIC` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `RTIC` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, const O: u8> = crate::BitWriter1C<'a, SSPICR_SPEC, O>; +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W<0> { + pub fn roric(&mut self) -> RORIC_W { RORIC_W::new(self) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W<1> { + pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt clear register, SSPICR on page 3-11 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspicr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPICR_SPEC; impl crate::RegisterSpec for SSPICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspicr::R](R) reader structure"] -impl crate::Readable for SSPICR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspicr::W](W) writer structure"] +#[doc = "`read()` method returns [`sspicr::R`](R) reader structure"] +impl crate::Readable for SSPICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspicr::W`](W) writer structure"] impl crate::Writable for SSPICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03; } diff --git a/src/spi0/sspimsc.rs b/src/spi0/sspimsc.rs index da29bb5f4..c18b9549d 100644 --- a/src/spi0/sspimsc.rs +++ b/src/spi0/sspimsc.rs @@ -1,55 +1,23 @@ #[doc = "Register `SSPIMSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPIMSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RORIM` reader - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] pub type RORIM_R = crate::BitReader; #[doc = "Field `RORIM` writer - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] -pub type RORIM_W<'a, const O: u8> = crate::BitWriter<'a, SSPIMSC_SPEC, O>; +pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIM` reader - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] pub type RTIM_R = crate::BitReader; #[doc = "Field `RTIM` writer - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] -pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, SSPIMSC_SPEC, O>; +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIM` reader - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] pub type RXIM_R = crate::BitReader; #[doc = "Field `RXIM` writer - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] -pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, SSPIMSC_SPEC, O>; +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIM` reader - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] pub type TXIM_R = crate::BitReader; #[doc = "Field `TXIM` writer - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] -pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, SSPIMSC_SPEC, O>; +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W<0> { + pub fn rorim(&mut self) -> RORIM_W { RORIM_W::new(self) } #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W<1> { + pub fn rtim(&mut self) -> RTIM_W { RTIM_W::new(self) } #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W<2> { + pub fn rxim(&mut self) -> RXIM_W { RXIM_W::new(self) } #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W<3> { + pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspimsc](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspimsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPIMSC_SPEC; impl crate::RegisterSpec for SSPIMSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspimsc::R](R) reader structure"] -impl crate::Readable for SSPIMSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspimsc::W](W) writer structure"] +#[doc = "`read()` method returns [`sspimsc::R`](R) reader structure"] +impl crate::Readable for SSPIMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspimsc::W`](W) writer structure"] impl crate::Writable for SSPIMSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/spi0/sspmis.rs b/src/spi0/sspmis.rs index 65caab0ae..03d579a51 100644 --- a/src/spi0/sspmis.rs +++ b/src/spi0/sspmis.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPMIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RORMIS` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] pub type RORMIS_R = crate::BitReader; #[doc = "Field `RTMIS` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] @@ -45,17 +32,13 @@ impl R { } #[doc = "Masked interrupt status register, SSPMIS on page 3-11 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspmis](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPMIS_SPEC; impl crate::RegisterSpec for SSPMIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspmis::R](R) reader structure"] -impl crate::Readable for SSPMIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspmis::R`](R) reader structure"] +impl crate::Readable for SSPMIS_SPEC {} #[doc = "`reset()` method sets SSPMIS to value 0"] impl crate::Resettable for SSPMIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/spi0/ssppcellid0.rs b/src/spi0/ssppcellid0.rs index 5c753d111..fbc5c29ab 100644 --- a/src/spi0/ssppcellid0.rs +++ b/src/spi0/ssppcellid0.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPCELLID0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SSPPCELLID0` reader - These bits read back as 0x0D"] pub type SSPPCELLID0_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssppcellid0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID0_SPEC; impl crate::RegisterSpec for SSPPCELLID0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssppcellid0::R](R) reader structure"] -impl crate::Readable for SSPPCELLID0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ssppcellid0::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID0_SPEC {} #[doc = "`reset()` method sets SSPPCELLID0 to value 0x0d"] impl crate::Resettable for SSPPCELLID0_SPEC { const RESET_VALUE: Self::Ux = 0x0d; diff --git a/src/spi0/ssppcellid1.rs b/src/spi0/ssppcellid1.rs index b8bbea89e..d234a342b 100644 --- a/src/spi0/ssppcellid1.rs +++ b/src/spi0/ssppcellid1.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPCELLID1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SSPPCELLID1` reader - These bits read back as 0xF0"] pub type SSPPCELLID1_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssppcellid1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID1_SPEC; impl crate::RegisterSpec for SSPPCELLID1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssppcellid1::R](R) reader structure"] -impl crate::Readable for SSPPCELLID1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ssppcellid1::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID1_SPEC {} #[doc = "`reset()` method sets SSPPCELLID1 to value 0xf0"] impl crate::Resettable for SSPPCELLID1_SPEC { const RESET_VALUE: Self::Ux = 0xf0; diff --git a/src/spi0/ssppcellid2.rs b/src/spi0/ssppcellid2.rs index 36abe6066..ecc05b012 100644 --- a/src/spi0/ssppcellid2.rs +++ b/src/spi0/ssppcellid2.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPCELLID2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SSPPCELLID2` reader - These bits read back as 0x05"] pub type SSPPCELLID2_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssppcellid2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID2_SPEC; impl crate::RegisterSpec for SSPPCELLID2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssppcellid2::R](R) reader structure"] -impl crate::Readable for SSPPCELLID2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ssppcellid2::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID2_SPEC {} #[doc = "`reset()` method sets SSPPCELLID2 to value 0x05"] impl crate::Resettable for SSPPCELLID2_SPEC { const RESET_VALUE: Self::Ux = 0x05; diff --git a/src/spi0/ssppcellid3.rs b/src/spi0/ssppcellid3.rs index d3f3c59ac..bb712db9f 100644 --- a/src/spi0/ssppcellid3.rs +++ b/src/spi0/ssppcellid3.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPCELLID3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SSPPCELLID3` reader - These bits read back as 0xB1"] pub type SSPPCELLID3_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssppcellid3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID3_SPEC; impl crate::RegisterSpec for SSPPCELLID3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssppcellid3::R](R) reader structure"] -impl crate::Readable for SSPPCELLID3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ssppcellid3::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID3_SPEC {} #[doc = "`reset()` method sets SSPPCELLID3 to value 0xb1"] impl crate::Resettable for SSPPCELLID3_SPEC { const RESET_VALUE: Self::Ux = 0xb1; diff --git a/src/spi0/sspperiphid0.rs b/src/spi0/sspperiphid0.rs index 93899a397..5cce0df5c 100644 --- a/src/spi0/sspperiphid0.rs +++ b/src/spi0/sspperiphid0.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPERIPHID0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x22"] pub type PARTNUMBER0_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspperiphid0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID0_SPEC; impl crate::RegisterSpec for SSPPERIPHID0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspperiphid0::R](R) reader structure"] -impl crate::Readable for SSPPERIPHID0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspperiphid0::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID0_SPEC {} #[doc = "`reset()` method sets SSPPERIPHID0 to value 0x22"] impl crate::Resettable for SSPPERIPHID0_SPEC { const RESET_VALUE: Self::Ux = 0x22; diff --git a/src/spi0/sspperiphid1.rs b/src/spi0/sspperiphid1.rs index f601e7dfa..591a0c472 100644 --- a/src/spi0/sspperiphid1.rs +++ b/src/spi0/sspperiphid1.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPERIPHID1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub type PARTNUMBER1_R = crate::FieldReader; #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] @@ -31,17 +18,13 @@ impl R { } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspperiphid1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID1_SPEC; impl crate::RegisterSpec for SSPPERIPHID1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspperiphid1::R](R) reader structure"] -impl crate::Readable for SSPPERIPHID1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspperiphid1::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID1_SPEC {} #[doc = "`reset()` method sets SSPPERIPHID1 to value 0x10"] impl crate::Resettable for SSPPERIPHID1_SPEC { const RESET_VALUE: Self::Ux = 0x10; diff --git a/src/spi0/sspperiphid2.rs b/src/spi0/sspperiphid2.rs index 68dd4cd26..11e2551bc 100644 --- a/src/spi0/sspperiphid2.rs +++ b/src/spi0/sspperiphid2.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPERIPHID2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub type DESIGNER1_R = crate::FieldReader; #[doc = "Field `REVISION` reader - These bits return the peripheral revision"] @@ -31,17 +18,13 @@ impl R { } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspperiphid2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID2_SPEC; impl crate::RegisterSpec for SSPPERIPHID2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspperiphid2::R](R) reader structure"] -impl crate::Readable for SSPPERIPHID2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspperiphid2::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID2_SPEC {} #[doc = "`reset()` method sets SSPPERIPHID2 to value 0x34"] impl crate::Resettable for SSPPERIPHID2_SPEC { const RESET_VALUE: Self::Ux = 0x34; diff --git a/src/spi0/sspperiphid3.rs b/src/spi0/sspperiphid3.rs index 20338538b..7082b4ac5 100644 --- a/src/spi0/sspperiphid3.rs +++ b/src/spi0/sspperiphid3.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPPERIPHID3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub type CONFIGURATION_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspperiphid3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID3_SPEC; impl crate::RegisterSpec for SSPPERIPHID3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspperiphid3::R](R) reader structure"] -impl crate::Readable for SSPPERIPHID3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspperiphid3::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID3_SPEC {} #[doc = "`reset()` method sets SSPPERIPHID3 to value 0"] impl crate::Resettable for SSPPERIPHID3_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/spi0/sspris.rs b/src/spi0/sspris.rs index 32d772e7f..e6d47221c 100644 --- a/src/spi0/sspris.rs +++ b/src/spi0/sspris.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPRIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RORRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] pub type RORRIS_R = crate::BitReader; #[doc = "Field `RTRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] @@ -45,17 +32,13 @@ impl R { } #[doc = "Raw interrupt status register, SSPRIS on page 3-10 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspris](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPRIS_SPEC; impl crate::RegisterSpec for SSPRIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspris::R](R) reader structure"] -impl crate::Readable for SSPRIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspris::R`](R) reader structure"] +impl crate::Readable for SSPRIS_SPEC {} #[doc = "`reset()` method sets SSPRIS to value 0x08"] impl crate::Resettable for SSPRIS_SPEC { const RESET_VALUE: Self::Ux = 0x08; diff --git a/src/spi0/sspsr.rs b/src/spi0/sspsr.rs index 613deeeb3..14bb8808c 100644 --- a/src/spi0/sspsr.rs +++ b/src/spi0/sspsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TFE` reader - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."] pub type TFE_R = crate::BitReader; #[doc = "Field `TNF` reader - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."] @@ -52,17 +39,13 @@ impl R { } #[doc = "Status register, SSPSR on page 3-7 -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sspsr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPSR_SPEC; impl crate::RegisterSpec for SSPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspsr::R](R) reader structure"] -impl crate::Readable for SSPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sspsr::R`](R) reader structure"] +impl crate::Readable for SSPSR_SPEC {} #[doc = "`reset()` method sets SSPSR to value 0x03"] impl crate::Resettable for SSPSR_SPEC { const RESET_VALUE: Self::Ux = 0x03; diff --git a/src/syscfg.rs b/src/syscfg.rs index d4a4b0bc1..262a4e205 100644 --- a/src/syscfg.rs +++ b/src/syscfg.rs @@ -27,21 +27,47 @@ pub struct RegisterBlock { Use with extreme caution"] pub mempowerdown: MEMPOWERDOWN, } -#[doc = "PROC0_NMI_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask + Set a bit high to enable NMI from that IRQ + +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_nmi_mask`] +module"] pub type PROC0_NMI_MASK = crate::Reg; #[doc = "Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ"] pub mod proc0_nmi_mask; -#[doc = "PROC1_NMI_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask + Set a bit high to enable NMI from that IRQ + +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_nmi_mask`] +module"] pub type PROC1_NMI_MASK = crate::Reg; #[doc = "Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ"] pub mod proc1_nmi_mask; -#[doc = "PROC_CONFIG (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC_CONFIG (rw) register accessor: Configuration for processors + +You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc_config`] +module"] pub type PROC_CONFIG = crate::Reg; #[doc = "Configuration for processors"] pub mod proc_config; -#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: an alias for `Reg`"] +#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...29. + +You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc_in_sync_bypass`] +module"] pub type PROC_IN_SYNC_BYPASS = crate::Reg; #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -49,7 +75,16 @@ pub type PROC_IN_SYNC_BYPASS = crate::Reg; #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -57,11 +92,22 @@ pub type PROC_IN_SYNC_BYPASS_HI = crate::Reg; #[doc = "Directly control the SWD debug port of either processor"] pub mod dbgforce; -#[doc = "MEMPOWERDOWN (rw) register accessor: an alias for `Reg`"] +#[doc = "MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories. + Use with extreme caution + +You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mempowerdown`] +module"] pub type MEMPOWERDOWN = crate::Reg; #[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution"] diff --git a/src/syscfg/dbgforce.rs b/src/syscfg/dbgforce.rs index 7fcd22b35..2ac76b3bd 100644 --- a/src/syscfg/dbgforce.rs +++ b/src/syscfg/dbgforce.rs @@ -1,67 +1,35 @@ #[doc = "Register `DBGFORCE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBGFORCE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROC0_SWDO` reader - Observe the value of processor 0 SWDIO output."] pub type PROC0_SWDO_R = crate::BitReader; #[doc = "Field `PROC0_SWDI` reader - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set"] pub type PROC0_SWDI_R = crate::BitReader; #[doc = "Field `PROC0_SWDI` writer - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set"] -pub type PROC0_SWDI_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC0_SWDI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC0_SWCLK` reader - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set"] pub type PROC0_SWCLK_R = crate::BitReader; #[doc = "Field `PROC0_SWCLK` writer - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set"] -pub type PROC0_SWCLK_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC0_SWCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC0_ATTACH` reader - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads."] pub type PROC0_ATTACH_R = crate::BitReader; #[doc = "Field `PROC0_ATTACH` writer - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads."] -pub type PROC0_ATTACH_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC0_ATTACH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC1_SWDO` reader - Observe the value of processor 1 SWDIO output."] pub type PROC1_SWDO_R = crate::BitReader; #[doc = "Field `PROC1_SWDI` reader - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set"] pub type PROC1_SWDI_R = crate::BitReader; #[doc = "Field `PROC1_SWDI` writer - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set"] -pub type PROC1_SWDI_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC1_SWDI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC1_SWCLK` reader - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set"] pub type PROC1_SWCLK_R = crate::BitReader; #[doc = "Field `PROC1_SWCLK` writer - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set"] -pub type PROC1_SWCLK_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC1_SWCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROC1_ATTACH` reader - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads."] pub type PROC1_ATTACH_R = crate::BitReader; #[doc = "Field `PROC1_ATTACH` writer - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads."] -pub type PROC1_ATTACH_W<'a, const O: u8> = crate::BitWriter<'a, DBGFORCE_SPEC, O>; +pub type PROC1_ATTACH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Observe the value of processor 0 SWDIO output."] #[inline(always)] @@ -108,62 +76,61 @@ impl W { #[doc = "Bit 1 - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set"] #[inline(always)] #[must_use] - pub fn proc0_swdi(&mut self) -> PROC0_SWDI_W<1> { + pub fn proc0_swdi(&mut self) -> PROC0_SWDI_W { PROC0_SWDI_W::new(self) } #[doc = "Bit 2 - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set"] #[inline(always)] #[must_use] - pub fn proc0_swclk(&mut self) -> PROC0_SWCLK_W<2> { + pub fn proc0_swclk(&mut self) -> PROC0_SWCLK_W { PROC0_SWCLK_W::new(self) } #[doc = "Bit 3 - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads."] #[inline(always)] #[must_use] - pub fn proc0_attach(&mut self) -> PROC0_ATTACH_W<3> { + pub fn proc0_attach(&mut self) -> PROC0_ATTACH_W { PROC0_ATTACH_W::new(self) } #[doc = "Bit 5 - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set"] #[inline(always)] #[must_use] - pub fn proc1_swdi(&mut self) -> PROC1_SWDI_W<5> { + pub fn proc1_swdi(&mut self) -> PROC1_SWDI_W { PROC1_SWDI_W::new(self) } #[doc = "Bit 6 - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set"] #[inline(always)] #[must_use] - pub fn proc1_swclk(&mut self) -> PROC1_SWCLK_W<6> { + pub fn proc1_swclk(&mut self) -> PROC1_SWCLK_W { PROC1_SWCLK_W::new(self) } #[doc = "Bit 7 - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads."] #[inline(always)] #[must_use] - pub fn proc1_attach(&mut self) -> PROC1_ATTACH_W<7> { + pub fn proc1_attach(&mut self) -> PROC1_ATTACH_W { PROC1_ATTACH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Directly control the SWD debug port of either processor -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dbgforce](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dbgforce::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgforce::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBGFORCE_SPEC; impl crate::RegisterSpec for DBGFORCE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbgforce::R](R) reader structure"] -impl crate::Readable for DBGFORCE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbgforce::W](W) writer structure"] +#[doc = "`read()` method returns [`dbgforce::R`](R) reader structure"] +impl crate::Readable for DBGFORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbgforce::W`](W) writer structure"] impl crate::Writable for DBGFORCE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs index 82ef58c76..f1260a8d3 100644 --- a/src/syscfg/mempowerdown.rs +++ b/src/syscfg/mempowerdown.rs @@ -1,71 +1,39 @@ #[doc = "Register `MEMPOWERDOWN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MEMPOWERDOWN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRAM0` reader - "] pub type SRAM0_R = crate::BitReader; #[doc = "Field `SRAM0` writer - "] -pub type SRAM0_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRAM1` reader - "] pub type SRAM1_R = crate::BitReader; #[doc = "Field `SRAM1` writer - "] -pub type SRAM1_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRAM2` reader - "] pub type SRAM2_R = crate::BitReader; #[doc = "Field `SRAM2` writer - "] -pub type SRAM2_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRAM3` reader - "] pub type SRAM3_R = crate::BitReader; #[doc = "Field `SRAM3` writer - "] -pub type SRAM3_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRAM4` reader - "] pub type SRAM4_R = crate::BitReader; #[doc = "Field `SRAM4` writer - "] -pub type SRAM4_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRAM5` reader - "] pub type SRAM5_R = crate::BitReader; #[doc = "Field `SRAM5` writer - "] -pub type SRAM5_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type SRAM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USB` reader - "] pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - "] -pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROM` reader - "] pub type ROM_R = crate::BitReader; #[doc = "Field `ROM` writer - "] -pub type ROM_W<'a, const O: u8> = crate::BitWriter<'a, MEMPOWERDOWN_SPEC, O>; +pub type ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -112,75 +80,74 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn sram0(&mut self) -> SRAM0_W<0> { + pub fn sram0(&mut self) -> SRAM0_W { SRAM0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn sram1(&mut self) -> SRAM1_W<1> { + pub fn sram1(&mut self) -> SRAM1_W { SRAM1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn sram2(&mut self) -> SRAM2_W<2> { + pub fn sram2(&mut self) -> SRAM2_W { SRAM2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn sram3(&mut self) -> SRAM3_W<3> { + pub fn sram3(&mut self) -> SRAM3_W { SRAM3_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn sram4(&mut self) -> SRAM4_W<4> { + pub fn sram4(&mut self) -> SRAM4_W { SRAM4_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn sram5(&mut self) -> SRAM5_W<5> { + pub fn sram5(&mut self) -> SRAM5_W { SRAM5_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<6> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn rom(&mut self) -> ROM_W<7> { + pub fn rom(&mut self) -> ROM_W { ROM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mempowerdown](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MEMPOWERDOWN_SPEC; impl crate::RegisterSpec for MEMPOWERDOWN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mempowerdown::R](R) reader structure"] -impl crate::Readable for MEMPOWERDOWN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mempowerdown::W](W) writer structure"] +#[doc = "`read()` method returns [`mempowerdown::R`](R) reader structure"] +impl crate::Readable for MEMPOWERDOWN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mempowerdown::W`](W) writer structure"] impl crate::Writable for MEMPOWERDOWN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/proc0_nmi_mask.rs b/src/syscfg/proc0_nmi_mask.rs index 496d77a68..eccb18315 100644 --- a/src/syscfg/proc0_nmi_mask.rs +++ b/src/syscfg/proc0_nmi_mask.rs @@ -1,39 +1,7 @@ #[doc = "Register `PROC0_NMI_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC0_NMI_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc0_nmi_mask](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_NMI_MASK_SPEC; impl crate::RegisterSpec for PROC0_NMI_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc0_nmi_mask::R](R) reader structure"] -impl crate::Readable for PROC0_NMI_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc0_nmi_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`proc0_nmi_mask::R`](R) reader structure"] +impl crate::Readable for PROC0_NMI_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_nmi_mask::W`](W) writer structure"] impl crate::Writable for PROC0_NMI_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/proc1_nmi_mask.rs b/src/syscfg/proc1_nmi_mask.rs index 78f4e1f28..e73edc650 100644 --- a/src/syscfg/proc1_nmi_mask.rs +++ b/src/syscfg/proc1_nmi_mask.rs @@ -1,39 +1,7 @@ #[doc = "Register `PROC1_NMI_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC1_NMI_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,30 +13,29 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc1_nmi_mask](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_NMI_MASK_SPEC; impl crate::RegisterSpec for PROC1_NMI_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc1_nmi_mask::R](R) reader structure"] -impl crate::Readable for PROC1_NMI_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc1_nmi_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`proc1_nmi_mask::R`](R) reader structure"] +impl crate::Readable for PROC1_NMI_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_nmi_mask::W`](W) writer structure"] impl crate::Writable for PROC1_NMI_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs index 40d3af878..d48f920f0 100644 --- a/src/syscfg/proc_config.rs +++ b/src/syscfg/proc_config.rs @@ -1,39 +1,7 @@ #[doc = "Register `PROC_CONFIG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC_CONFIG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROC0_HALTED` reader - Indication that proc0 has halted"] pub type PROC0_HALTED_R = crate::BitReader; #[doc = "Field `PROC1_HALTED` reader - Indication that proc1 has halted"] @@ -45,7 +13,7 @@ pub type PROC0_DAP_INSTID_R = crate::FieldReader; #[doc = "Field `PROC0_DAP_INSTID` writer - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] -pub type PROC0_DAP_INSTID_W<'a, const O: u8> = crate::FieldWriter<'a, PROC_CONFIG_SPEC, 4, O>; +pub type PROC0_DAP_INSTID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PROC1_DAP_INSTID` reader - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] @@ -53,7 +21,7 @@ pub type PROC1_DAP_INSTID_R = crate::FieldReader; #[doc = "Field `PROC1_DAP_INSTID` writer - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] -pub type PROC1_DAP_INSTID_W<'a, const O: u8> = crate::FieldWriter<'a, PROC_CONFIG_SPEC, 4, O>; +pub type PROC1_DAP_INSTID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Indication that proc0 has halted"] #[inline(always)] @@ -86,7 +54,7 @@ impl W { WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] #[must_use] - pub fn proc0_dap_instid(&mut self) -> PROC0_DAP_INSTID_W<24> { + pub fn proc0_dap_instid(&mut self) -> PROC0_DAP_INSTID_W { PROC0_DAP_INSTID_W::new(self) } #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. @@ -94,32 +62,31 @@ impl W { WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] #[must_use] - pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W<28> { + pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W { PROC1_DAP_INSTID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Configuration for processors -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc_config](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC_CONFIG_SPEC; impl crate::RegisterSpec for PROC_CONFIG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc_config::R](R) reader structure"] -impl crate::Readable for PROC_CONFIG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc_config::W](W) writer structure"] +#[doc = "`read()` method returns [`proc_config::R`](R) reader structure"] +impl crate::Readable for PROC_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_config::W`](W) writer structure"] impl crate::Writable for PROC_CONFIG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs index d025f7033..53e259597 100644 --- a/src/syscfg/proc_in_sync_bypass.rs +++ b/src/syscfg/proc_in_sync_bypass.rs @@ -1,44 +1,11 @@ #[doc = "Register `PROC_IN_SYNC_BYPASS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC_IN_SYNC_BYPASS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROC_IN_SYNC_BYPASS` reader - "] pub type PROC_IN_SYNC_BYPASS_R = crate::FieldReader; #[doc = "Field `PROC_IN_SYNC_BYPASS` writer - "] -pub type PROC_IN_SYNC_BYPASS_W<'a, const O: u8> = - crate::FieldWriter<'a, PROC_IN_SYNC_BYPASS_SPEC, 30, O, u32>; +pub type PROC_IN_SYNC_BYPASS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 0:29"] #[inline(always)] @@ -50,13 +17,17 @@ impl W { #[doc = "Bits 0:29"] #[inline(always)] #[must_use] - pub fn proc_in_sync_bypass(&mut self) -> PROC_IN_SYNC_BYPASS_W<0> { + pub fn proc_in_sync_bypass(&mut self) -> PROC_IN_SYNC_BYPASS_W { PROC_IN_SYNC_BYPASS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -66,20 +37,15 @@ impl W { If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc_in_sync_bypass](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC_IN_SYNC_BYPASS_SPEC; impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc_in_sync_bypass::R](R) reader structure"] -impl crate::Readable for PROC_IN_SYNC_BYPASS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc_in_sync_bypass::W](W) writer structure"] +#[doc = "`read()` method returns [`proc_in_sync_bypass::R`](R) reader structure"] +impl crate::Readable for PROC_IN_SYNC_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass::W`](W) writer structure"] impl crate::Writable for PROC_IN_SYNC_BYPASS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs index dc035954c..52ab0e5f9 100644 --- a/src/syscfg/proc_in_sync_bypass_hi.rs +++ b/src/syscfg/proc_in_sync_bypass_hi.rs @@ -1,44 +1,11 @@ #[doc = "Register `PROC_IN_SYNC_BYPASS_HI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PROC_IN_SYNC_BYPASS_HI` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROC_IN_SYNC_BYPASS_HI` reader - "] pub type PROC_IN_SYNC_BYPASS_HI_R = crate::FieldReader; #[doc = "Field `PROC_IN_SYNC_BYPASS_HI` writer - "] -pub type PROC_IN_SYNC_BYPASS_HI_W<'a, const O: u8> = - crate::FieldWriter<'a, PROC_IN_SYNC_BYPASS_HI_SPEC, 6, O>; +pub type PROC_IN_SYNC_BYPASS_HI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -50,13 +17,19 @@ impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn proc_in_sync_bypass_hi(&mut self) -> PROC_IN_SYNC_BYPASS_HI_W<0> { + pub fn proc_in_sync_bypass_hi( + &mut self, + ) -> PROC_IN_SYNC_BYPASS_HI_W { PROC_IN_SYNC_BYPASS_HI_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -66,20 +39,15 @@ impl W { If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs). -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [proc_in_sync_bypass_hi](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC_IN_SYNC_BYPASS_HI_SPEC; impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_HI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [proc_in_sync_bypass_hi::R](R) reader structure"] -impl crate::Readable for PROC_IN_SYNC_BYPASS_HI_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [proc_in_sync_bypass_hi::W](W) writer structure"] +#[doc = "`read()` method returns [`proc_in_sync_bypass_hi::R`](R) reader structure"] +impl crate::Readable for PROC_IN_SYNC_BYPASS_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass_hi::W`](W) writer structure"] impl crate::Writable for PROC_IN_SYNC_BYPASS_HI_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/sysinfo.rs b/src/sysinfo.rs index 4879258fe..0fbd98119 100644 --- a/src/sysinfo.rs +++ b/src/sysinfo.rs @@ -9,15 +9,30 @@ pub struct RegisterBlock { #[doc = "0x40 - Git hash of the chip source. Used to identify chip version."] pub gitref_rp2040: GITREF_RP2040, } -#[doc = "CHIP_ID (r) register accessor: an alias for `Reg`"] +#[doc = "CHIP_ID (r) register accessor: JEDEC JEP-106 compliant chip identifier. + +You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chip_id`] +module"] pub type CHIP_ID = crate::Reg; #[doc = "JEDEC JEP-106 compliant chip identifier."] pub mod chip_id; -#[doc = "PLATFORM (r) register accessor: an alias for `Reg`"] +#[doc = "PLATFORM (r) register accessor: Platform register. Allows software to know what environment it is running in. + +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@platform`] +module"] pub type PLATFORM = crate::Reg; #[doc = "Platform register. Allows software to know what environment it is running in."] pub mod platform; -#[doc = "GITREF_RP2040 (r) register accessor: an alias for `Reg`"] +#[doc = "GITREF_RP2040 (r) register accessor: Git hash of the chip source. Used to identify chip version. + +You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gitref_rp2040`] +module"] pub type GITREF_RP2040 = crate::Reg; #[doc = "Git hash of the chip source. Used to identify chip version."] pub mod gitref_rp2040; diff --git a/src/sysinfo/chip_id.rs b/src/sysinfo/chip_id.rs index ebf7ff245..e5f682a1d 100644 --- a/src/sysinfo/chip_id.rs +++ b/src/sysinfo/chip_id.rs @@ -1,18 +1,5 @@ #[doc = "Register `CHIP_ID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MANUFACTURER` reader - "] pub type MANUFACTURER_R = crate::FieldReader; #[doc = "Field `PART` reader - "] @@ -38,17 +25,13 @@ impl R { } #[doc = "JEDEC JEP-106 compliant chip identifier. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [chip_id](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHIP_ID_SPEC; impl crate::RegisterSpec for CHIP_ID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chip_id::R](R) reader structure"] -impl crate::Readable for CHIP_ID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chip_id::R`](R) reader structure"] +impl crate::Readable for CHIP_ID_SPEC {} #[doc = "`reset()` method sets CHIP_ID to value 0"] impl crate::Resettable for CHIP_ID_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sysinfo/gitref_rp2040.rs b/src/sysinfo/gitref_rp2040.rs index 6a4f06ab6..ee9ac9460 100644 --- a/src/sysinfo/gitref_rp2040.rs +++ b/src/sysinfo/gitref_rp2040.rs @@ -1,18 +1,5 @@ #[doc = "Register `GITREF_RP2040` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Git hash of the chip source. Used to identify chip version. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [gitref_rp2040](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GITREF_RP2040_SPEC; impl crate::RegisterSpec for GITREF_RP2040_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gitref_rp2040::R](R) reader structure"] -impl crate::Readable for GITREF_RP2040_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gitref_rp2040::R`](R) reader structure"] +impl crate::Readable for GITREF_RP2040_SPEC {} #[doc = "`reset()` method sets GITREF_RP2040 to value 0"] impl crate::Resettable for GITREF_RP2040_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/sysinfo/platform.rs b/src/sysinfo/platform.rs index 971e9d6d9..48cbd8c1e 100644 --- a/src/sysinfo/platform.rs +++ b/src/sysinfo/platform.rs @@ -1,18 +1,5 @@ #[doc = "Register `PLATFORM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FPGA` reader - "] pub type FPGA_R = crate::BitReader; #[doc = "Field `ASIC` reader - "] @@ -31,17 +18,13 @@ impl R { } #[doc = "Platform register. Allows software to know what environment it is running in. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [platform](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PLATFORM_SPEC; impl crate::RegisterSpec for PLATFORM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [platform::R](R) reader structure"] -impl crate::Readable for PLATFORM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`platform::R`](R) reader structure"] +impl crate::Readable for PLATFORM_SPEC {} #[doc = "`reset()` method sets PLATFORM to value 0"] impl crate::Resettable for PLATFORM_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/tbman.rs b/src/tbman.rs index 8d8465f4d..95b0daffc 100644 --- a/src/tbman.rs +++ b/src/tbman.rs @@ -4,7 +4,12 @@ pub struct RegisterBlock { #[doc = "0x00 - Indicates the type of platform in use"] pub platform: PLATFORM, } -#[doc = "PLATFORM (r) register accessor: an alias for `Reg`"] +#[doc = "PLATFORM (r) register accessor: Indicates the type of platform in use + +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@platform`] +module"] pub type PLATFORM = crate::Reg; #[doc = "Indicates the type of platform in use"] pub mod platform; diff --git a/src/tbman/platform.rs b/src/tbman/platform.rs index ed2289c6c..095b18069 100644 --- a/src/tbman/platform.rs +++ b/src/tbman/platform.rs @@ -1,18 +1,5 @@ #[doc = "Register `PLATFORM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ASIC` reader - Indicates the platform is an ASIC"] pub type ASIC_R = crate::BitReader; #[doc = "Field `FPGA` reader - Indicates the platform is an FPGA"] @@ -31,17 +18,13 @@ impl R { } #[doc = "Indicates the type of platform in use -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [platform](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PLATFORM_SPEC; impl crate::RegisterSpec for PLATFORM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [platform::R](R) reader structure"] -impl crate::Readable for PLATFORM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`platform::R`](R) reader structure"] +impl crate::Readable for PLATFORM_SPEC {} #[doc = "`reset()` method sets PLATFORM to value 0x05"] impl crate::Resettable for PLATFORM_SPEC { const RESET_VALUE: Self::Ux = 0x05; diff --git a/src/timer.rs b/src/timer.rs index daf4c9785..df118c7f0 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -54,89 +54,192 @@ pub struct RegisterBlock { #[doc = "0x40 - Interrupt status after masking & forcing"] pub ints: INTS, } -#[doc = "TIMEHW (w) register accessor: an alias for `Reg`"] +#[doc = "TIMEHW (w) register accessor: Write to bits 63:32 of time + always write timelw before timehw + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timehw`] +module"] pub type TIMEHW = crate::Reg; #[doc = "Write to bits 63:32 of time always write timelw before timehw"] pub mod timehw; -#[doc = "TIMELW (w) register accessor: an alias for `Reg`"] +#[doc = "TIMELW (w) register accessor: Write to bits 31:0 of time + writes do not get copied to time until timehw is written + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timelw`] +module"] pub type TIMELW = crate::Reg; #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"] pub mod timelw; -#[doc = "TIMEHR (r) register accessor: an alias for `Reg`"] +#[doc = "TIMEHR (r) register accessor: Read from bits 63:32 of time + always read timelr before timehr + +You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timehr`] +module"] pub type TIMEHR = crate::Reg; #[doc = "Read from bits 63:32 of time always read timelr before timehr"] pub mod timehr; -#[doc = "TIMELR (r) register accessor: an alias for `Reg`"] +#[doc = "TIMELR (r) register accessor: Read from bits 31:0 of time + +You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timelr`] +module"] pub type TIMELR = crate::Reg; #[doc = "Read from bits 31:0 of time"] pub mod timelr; -#[doc = "ALARM0 (rw) register accessor: an alias for `Reg`"] +#[doc = "ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + +You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm0`] +module"] pub type ALARM0 = crate::Reg; #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm0; -#[doc = "ALARM1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + +You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm1`] +module"] pub type ALARM1 = crate::Reg; #[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm1; -#[doc = "ALARM2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + +You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm2`] +module"] pub type ALARM2 = crate::Reg; #[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm2; -#[doc = "ALARM3 (rw) register accessor: an alias for `Reg`"] +#[doc = "ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + +You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm3`] +module"] pub type ALARM3 = crate::Reg; #[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm3; -#[doc = "ARMED (rw) register accessor: an alias for `Reg`"] +#[doc = "ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm. + A write to the corresponding ALARMx register arms the alarm. + Alarms automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. + +You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@armed`] +module"] pub type ARMED = crate::Reg; #[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] pub mod armed; -#[doc = "TIMERAWH (r) register accessor: an alias for `Reg`"] +#[doc = "TIMERAWH (r) register accessor: Raw read from bits 63:32 of time (no side effects) + +You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timerawh`] +module"] pub type TIMERAWH = crate::Reg; #[doc = "Raw read from bits 63:32 of time (no side effects)"] pub mod timerawh; -#[doc = "TIMERAWL (r) register accessor: an alias for `Reg`"] +#[doc = "TIMERAWL (r) register accessor: Raw read from bits 31:0 of time (no side effects) + +You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timerawl`] +module"] pub type TIMERAWL = crate::Reg; #[doc = "Raw read from bits 31:0 of time (no side effects)"] pub mod timerawl; -#[doc = "DBGPAUSE (rw) register accessor: an alias for `Reg`"] +#[doc = "DBGPAUSE (rw) register accessor: Set bits high to enable pause when the corresponding debug ports are active + +You can [`read`](crate::generic::Reg::read) this register and get [`dbgpause::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgpause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbgpause`] +module"] pub type DBGPAUSE = crate::Reg; #[doc = "Set bits high to enable pause when the corresponding debug ports are active"] pub mod dbgpause; -#[doc = "PAUSE (rw) register accessor: an alias for `Reg`"] +#[doc = "PAUSE (rw) register accessor: Set high to pause the timer + +You can [`read`](crate::generic::Reg::read) this register and get [`pause::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pause`] +module"] pub type PAUSE = crate::Reg; #[doc = "Set high to pause the timer"] pub mod pause; -#[doc = "INTR (rw) register accessor: an alias for `Reg`"] +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/timer/alarm0.rs b/src/timer/alarm0.rs index 5380e8549..4a72b17a1 100644 --- a/src/timer/alarm0.rs +++ b/src/timer/alarm0.rs @@ -1,39 +1,7 @@ #[doc = "Register `ALARM0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ALARM0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [alarm0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM0_SPEC; impl crate::RegisterSpec for ALARM0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [alarm0::R](R) reader structure"] -impl crate::Readable for ALARM0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [alarm0::W](W) writer structure"] +#[doc = "`read()` method returns [`alarm0::R`](R) reader structure"] +impl crate::Readable for ALARM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm0::W`](W) writer structure"] impl crate::Writable for ALARM0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/alarm1.rs b/src/timer/alarm1.rs index 73678609e..02dbdee1c 100644 --- a/src/timer/alarm1.rs +++ b/src/timer/alarm1.rs @@ -1,39 +1,7 @@ #[doc = "Register `ALARM1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ALARM1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [alarm1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM1_SPEC; impl crate::RegisterSpec for ALARM1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [alarm1::R](R) reader structure"] -impl crate::Readable for ALARM1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [alarm1::W](W) writer structure"] +#[doc = "`read()` method returns [`alarm1::R`](R) reader structure"] +impl crate::Readable for ALARM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm1::W`](W) writer structure"] impl crate::Writable for ALARM1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/alarm2.rs b/src/timer/alarm2.rs index c2142fe6d..9fbe78cda 100644 --- a/src/timer/alarm2.rs +++ b/src/timer/alarm2.rs @@ -1,39 +1,7 @@ #[doc = "Register `ALARM2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ALARM2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [alarm2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM2_SPEC; impl crate::RegisterSpec for ALARM2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [alarm2::R](R) reader structure"] -impl crate::Readable for ALARM2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [alarm2::W](W) writer structure"] +#[doc = "`read()` method returns [`alarm2::R`](R) reader structure"] +impl crate::Readable for ALARM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm2::W`](W) writer structure"] impl crate::Writable for ALARM2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/alarm3.rs b/src/timer/alarm3.rs index acec6778c..6dd1e40f5 100644 --- a/src/timer/alarm3.rs +++ b/src/timer/alarm3.rs @@ -1,39 +1,7 @@ #[doc = "Register `ALARM3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ALARM3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [alarm3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM3_SPEC; impl crate::RegisterSpec for ALARM3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [alarm3::R](R) reader structure"] -impl crate::Readable for ALARM3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [alarm3::W](W) writer structure"] +#[doc = "`read()` method returns [`alarm3::R`](R) reader structure"] +impl crate::Readable for ALARM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm3::W`](W) writer structure"] impl crate::Writable for ALARM3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/armed.rs b/src/timer/armed.rs index fb175af7c..dfc87229c 100644 --- a/src/timer/armed.rs +++ b/src/timer/armed.rs @@ -1,43 +1,11 @@ #[doc = "Register `ARMED` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARMED` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ARMED` reader - "] pub type ARMED_R = crate::FieldReader; #[doc = "Field `ARMED` writer - "] -pub type ARMED_W<'a, const O: u8> = crate::FieldWriter<'a, ARMED_SPEC, 4, O>; +pub type ARMED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3"] #[inline(always)] @@ -49,13 +17,17 @@ impl W { #[doc = "Bits 0:3"] #[inline(always)] #[must_use] - pub fn armed(&mut self) -> ARMED_W<0> { + pub fn armed(&mut self) -> ARMED_W { ARMED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -64,20 +36,15 @@ impl W { Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [armed](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARMED_SPEC; impl crate::RegisterSpec for ARMED_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [armed::R](R) reader structure"] -impl crate::Readable for ARMED_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [armed::W](W) writer structure"] +#[doc = "`read()` method returns [`armed::R`](R) reader structure"] +impl crate::Readable for ARMED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`armed::W`](W) writer structure"] impl crate::Writable for ARMED_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/src/timer/dbgpause.rs b/src/timer/dbgpause.rs index 34951c867..164c27735 100644 --- a/src/timer/dbgpause.rs +++ b/src/timer/dbgpause.rs @@ -1,47 +1,15 @@ #[doc = "Register `DBGPAUSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBGPAUSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DBG0` reader - Pause when processor 0 is in debug mode"] pub type DBG0_R = crate::BitReader; #[doc = "Field `DBG0` writer - Pause when processor 0 is in debug mode"] -pub type DBG0_W<'a, const O: u8> = crate::BitWriter<'a, DBGPAUSE_SPEC, O>; +pub type DBG0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DBG1` reader - Pause when processor 1 is in debug mode"] pub type DBG1_R = crate::BitReader; #[doc = "Field `DBG1` writer - Pause when processor 1 is in debug mode"] -pub type DBG1_W<'a, const O: u8> = crate::BitWriter<'a, DBGPAUSE_SPEC, O>; +pub type DBG1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Pause when processor 0 is in debug mode"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bit 1 - Pause when processor 0 is in debug mode"] #[inline(always)] #[must_use] - pub fn dbg0(&mut self) -> DBG0_W<1> { + pub fn dbg0(&mut self) -> DBG0_W { DBG0_W::new(self) } #[doc = "Bit 2 - Pause when processor 1 is in debug mode"] #[inline(always)] #[must_use] - pub fn dbg1(&mut self) -> DBG1_W<2> { + pub fn dbg1(&mut self) -> DBG1_W { DBG1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Set bits high to enable pause when the corresponding debug ports are active -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dbgpause](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dbgpause::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgpause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBGPAUSE_SPEC; impl crate::RegisterSpec for DBGPAUSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbgpause::R](R) reader structure"] -impl crate::Readable for DBGPAUSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbgpause::W](W) writer structure"] +#[doc = "`read()` method returns [`dbgpause::R`](R) reader structure"] +impl crate::Readable for DBGPAUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbgpause::W`](W) writer structure"] impl crate::Writable for DBGPAUSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/inte.rs b/src/timer/inte.rs index 18852e558..dabf52841 100644 --- a/src/timer/inte.rs +++ b/src/timer/inte.rs @@ -1,55 +1,23 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALARM_0` reader - "] pub type ALARM_0_R = crate::BitReader; #[doc = "Field `ALARM_0` writer - "] -pub type ALARM_0_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ALARM_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_1` reader - "] pub type ALARM_1_R = crate::BitReader; #[doc = "Field `ALARM_1` writer - "] -pub type ALARM_1_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ALARM_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_2` reader - "] pub type ALARM_2_R = crate::BitReader; #[doc = "Field `ALARM_2` writer - "] -pub type ALARM_2_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ALARM_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_3` reader - "] pub type ALARM_3_R = crate::BitReader; #[doc = "Field `ALARM_3` writer - "] -pub type ALARM_3_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ALARM_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn alarm_0(&mut self) -> ALARM_0_W<0> { + pub fn alarm_0(&mut self) -> ALARM_0_W { ALARM_0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn alarm_1(&mut self) -> ALARM_1_W<1> { + pub fn alarm_1(&mut self) -> ALARM_1_W { ALARM_1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn alarm_2(&mut self) -> ALARM_2_W<2> { + pub fn alarm_2(&mut self) -> ALARM_2_W { ALARM_2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn alarm_3(&mut self) -> ALARM_3_W<3> { + pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/intf.rs b/src/timer/intf.rs index 99eb1e47d..fd7d95447 100644 --- a/src/timer/intf.rs +++ b/src/timer/intf.rs @@ -1,55 +1,23 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALARM_0` reader - "] pub type ALARM_0_R = crate::BitReader; #[doc = "Field `ALARM_0` writer - "] -pub type ALARM_0_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ALARM_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_1` reader - "] pub type ALARM_1_R = crate::BitReader; #[doc = "Field `ALARM_1` writer - "] -pub type ALARM_1_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ALARM_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_2` reader - "] pub type ALARM_2_R = crate::BitReader; #[doc = "Field `ALARM_2` writer - "] -pub type ALARM_2_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ALARM_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALARM_3` reader - "] pub type ALARM_3_R = crate::BitReader; #[doc = "Field `ALARM_3` writer - "] -pub type ALARM_3_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ALARM_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn alarm_0(&mut self) -> ALARM_0_W<0> { + pub fn alarm_0(&mut self) -> ALARM_0_W { ALARM_0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn alarm_1(&mut self) -> ALARM_1_W<1> { + pub fn alarm_1(&mut self) -> ALARM_1_W { ALARM_1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn alarm_2(&mut self) -> ALARM_2_W<2> { + pub fn alarm_2(&mut self) -> ALARM_2_W { ALARM_2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn alarm_3(&mut self) -> ALARM_3_W<3> { + pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/intr.rs b/src/timer/intr.rs index f396b3faf..9f0bd3afd 100644 --- a/src/timer/intr.rs +++ b/src/timer/intr.rs @@ -1,55 +1,23 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALARM_0` reader - "] pub type ALARM_0_R = crate::BitReader; #[doc = "Field `ALARM_0` writer - "] -pub type ALARM_0_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type ALARM_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ALARM_1` reader - "] pub type ALARM_1_R = crate::BitReader; #[doc = "Field `ALARM_1` writer - "] -pub type ALARM_1_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type ALARM_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ALARM_2` reader - "] pub type ALARM_2_R = crate::BitReader; #[doc = "Field `ALARM_2` writer - "] -pub type ALARM_2_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type ALARM_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ALARM_3` reader - "] pub type ALARM_3_R = crate::BitReader; #[doc = "Field `ALARM_3` writer - "] -pub type ALARM_3_W<'a, const O: u8> = crate::BitWriter1C<'a, INTR_SPEC, O>; +pub type ALARM_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn alarm_0(&mut self) -> ALARM_0_W<0> { + pub fn alarm_0(&mut self) -> ALARM_0_W { ALARM_0_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn alarm_1(&mut self) -> ALARM_1_W<1> { + pub fn alarm_1(&mut self) -> ALARM_1_W { ALARM_1_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn alarm_2(&mut self) -> ALARM_2_W<2> { + pub fn alarm_2(&mut self) -> ALARM_2_W { ALARM_2_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn alarm_3(&mut self) -> ALARM_3_W<3> { + pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intr::W](W) writer structure"] +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/src/timer/ints.rs b/src/timer/ints.rs index f2216fb8b..e402b7425 100644 --- a/src/timer/ints.rs +++ b/src/timer/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ALARM_0` reader - "] pub type ALARM_0_R = crate::BitReader; #[doc = "Field `ALARM_1` reader - "] @@ -45,17 +32,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/timer/pause.rs b/src/timer/pause.rs index e498b8bfc..287492dfe 100644 --- a/src/timer/pause.rs +++ b/src/timer/pause.rs @@ -1,43 +1,11 @@ #[doc = "Register `PAUSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PAUSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PAUSE` reader - "] pub type PAUSE_R = crate::BitReader; #[doc = "Field `PAUSE` writer - "] -pub type PAUSE_W<'a, const O: u8> = crate::BitWriter<'a, PAUSE_SPEC, O>; +pub type PAUSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn pause(&mut self) -> PAUSE_W<0> { + pub fn pause(&mut self) -> PAUSE_W { PAUSE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Set high to pause the timer -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [pause](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`pause::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PAUSE_SPEC; impl crate::RegisterSpec for PAUSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pause::R](R) reader structure"] -impl crate::Readable for PAUSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pause::W](W) writer structure"] +#[doc = "`read()` method returns [`pause::R`](R) reader structure"] +impl crate::Readable for PAUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pause::W`](W) writer structure"] impl crate::Writable for PAUSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/timehr.rs b/src/timer/timehr.rs index 54db3b0b3..85aaa63fa 100644 --- a/src/timer/timehr.rs +++ b/src/timer/timehr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TIMEHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -26,17 +13,13 @@ impl core::fmt::Debug for crate::generic::Reg { #[doc = "Read from bits 63:32 of time always read timelr before timehr -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timehr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEHR_SPEC; impl crate::RegisterSpec for TIMEHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timehr::R](R) reader structure"] -impl crate::Readable for TIMEHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`timehr::R`](R) reader structure"] +impl crate::Readable for TIMEHR_SPEC {} #[doc = "`reset()` method sets TIMEHR to value 0"] impl crate::Resettable for TIMEHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/timer/timehw.rs b/src/timer/timehw.rs index 5e6d1c135..849ba2c7f 100644 --- a/src/timer/timehw.rs +++ b/src/timer/timehw.rs @@ -1,50 +1,32 @@ #[doc = "Register `TIMEHW` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Write to bits 63:32 of time always write timelw before timehw -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timehw](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEHW_SPEC; impl crate::RegisterSpec for TIMEHW_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [timehw::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`timehw::W`](W) writer structure"] impl crate::Writable for TIMEHW_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/timelr.rs b/src/timer/timelr.rs index 7479106c1..a7749b9fb 100644 --- a/src/timer/timelr.rs +++ b/src/timer/timelr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TIMELR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Read from bits 31:0 of time -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timelr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMELR_SPEC; impl crate::RegisterSpec for TIMELR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timelr::R](R) reader structure"] -impl crate::Readable for TIMELR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`timelr::R`](R) reader structure"] +impl crate::Readable for TIMELR_SPEC {} #[doc = "`reset()` method sets TIMELR to value 0"] impl crate::Resettable for TIMELR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/timer/timelw.rs b/src/timer/timelw.rs index 97bab2742..d6f73cf81 100644 --- a/src/timer/timelw.rs +++ b/src/timer/timelw.rs @@ -1,50 +1,32 @@ #[doc = "Register `TIMELW` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timelw](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMELW_SPEC; impl crate::RegisterSpec for TIMELW_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [timelw::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`timelw::W`](W) writer structure"] impl crate::Writable for TIMELW_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/timer/timerawh.rs b/src/timer/timerawh.rs index ac37396ae..08742e9c0 100644 --- a/src/timer/timerawh.rs +++ b/src/timer/timerawh.rs @@ -1,18 +1,5 @@ #[doc = "Register `TIMERAWH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Raw read from bits 63:32 of time (no side effects) -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timerawh](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMERAWH_SPEC; impl crate::RegisterSpec for TIMERAWH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timerawh::R](R) reader structure"] -impl crate::Readable for TIMERAWH_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`timerawh::R`](R) reader structure"] +impl crate::Readable for TIMERAWH_SPEC {} #[doc = "`reset()` method sets TIMERAWH to value 0"] impl crate::Resettable for TIMERAWH_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/timer/timerawl.rs b/src/timer/timerawl.rs index c8daae4a7..57dcc1d89 100644 --- a/src/timer/timerawl.rs +++ b/src/timer/timerawl.rs @@ -1,18 +1,5 @@ #[doc = "Register `TIMERAWL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -25,17 +12,13 @@ impl core::fmt::Debug for crate::generic::Reg { } #[doc = "Raw read from bits 31:0 of time (no side effects) -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [timerawl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMERAWL_SPEC; impl crate::RegisterSpec for TIMERAWL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timerawl::R](R) reader structure"] -impl crate::Readable for TIMERAWL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`timerawl::R`](R) reader structure"] +impl crate::Readable for TIMERAWL_SPEC {} #[doc = "`reset()` method sets TIMERAWL to value 0"] impl crate::Resettable for TIMERAWL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/uart0.rs b/src/uart0.rs index 3007ce41d..080ea1c39 100644 --- a/src/uart0.rs +++ b/src/uart0.rs @@ -49,91 +49,201 @@ pub struct RegisterBlock { #[doc = "0xffc - UARTPCellID3 Register"] pub uartpcellid3: UARTPCELLID3, } -#[doc = "UARTDR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTDR (rw) register accessor: Data Register, UARTDR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartdr`] +module"] pub type UARTDR = crate::Reg; #[doc = "Data Register, UARTDR"] pub mod uartdr; -#[doc = "UARTRSR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTRSR (rw) register accessor: Receive Status Register/Error Clear Register, UARTRSR/UARTECR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartrsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartrsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartrsr`] +module"] pub type UARTRSR = crate::Reg; #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] pub mod uartrsr; -#[doc = "UARTFR (r) register accessor: an alias for `Reg`"] +#[doc = "UARTFR (r) register accessor: Flag Register, UARTFR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartfr`] +module"] pub type UARTFR = crate::Reg; #[doc = "Flag Register, UARTFR"] pub mod uartfr; -#[doc = "UARTILPR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTILPR (rw) register accessor: IrDA Low-Power Counter Register, UARTILPR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartilpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartilpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartilpr`] +module"] pub type UARTILPR = crate::Reg; #[doc = "IrDA Low-Power Counter Register, UARTILPR"] pub mod uartilpr; -#[doc = "UARTIBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTIBRD (rw) register accessor: Integer Baud Rate Register, UARTIBRD + +You can [`read`](crate::generic::Reg::read) this register and get [`uartibrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartibrd`] +module"] pub type UARTIBRD = crate::Reg; #[doc = "Integer Baud Rate Register, UARTIBRD"] pub mod uartibrd; -#[doc = "UARTFBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTFBRD (rw) register accessor: Fractional Baud Rate Register, UARTFBRD + +You can [`read`](crate::generic::Reg::read) this register and get [`uartfbrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartfbrd`] +module"] pub type UARTFBRD = crate::Reg; #[doc = "Fractional Baud Rate Register, UARTFBRD"] pub mod uartfbrd; -#[doc = "UARTLCR_H (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTLCR_H (rw) register accessor: Line Control Register, UARTLCR_H + +You can [`read`](crate::generic::Reg::read) this register and get [`uartlcr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartlcr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartlcr_h`] +module"] pub type UARTLCR_H = crate::Reg; #[doc = "Line Control Register, UARTLCR_H"] pub mod uartlcr_h; -#[doc = "UARTCR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTCR (rw) register accessor: Control Register, UARTCR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartcr`] +module"] pub type UARTCR = crate::Reg; #[doc = "Control Register, UARTCR"] pub mod uartcr; -#[doc = "UARTIFLS (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTIFLS (rw) register accessor: Interrupt FIFO Level Select Register, UARTIFLS + +You can [`read`](crate::generic::Reg::read) this register and get [`uartifls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartifls`] +module"] pub type UARTIFLS = crate::Reg; #[doc = "Interrupt FIFO Level Select Register, UARTIFLS"] pub mod uartifls; -#[doc = "UARTIMSC (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTIMSC (rw) register accessor: Interrupt Mask Set/Clear Register, UARTIMSC + +You can [`read`](crate::generic::Reg::read) this register and get [`uartimsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartimsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartimsc`] +module"] pub type UARTIMSC = crate::Reg; #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"] pub mod uartimsc; -#[doc = "UARTRIS (r) register accessor: an alias for `Reg`"] +#[doc = "UARTRIS (r) register accessor: Raw Interrupt Status Register, UARTRIS + +You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartris`] +module"] pub type UARTRIS = crate::Reg; #[doc = "Raw Interrupt Status Register, UARTRIS"] pub mod uartris; -#[doc = "UARTMIS (r) register accessor: an alias for `Reg`"] +#[doc = "UARTMIS (r) register accessor: Masked Interrupt Status Register, UARTMIS + +You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartmis`] +module"] pub type UARTMIS = crate::Reg; #[doc = "Masked Interrupt Status Register, UARTMIS"] pub mod uartmis; -#[doc = "UARTICR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTICR (rw) register accessor: Interrupt Clear Register, UARTICR + +You can [`read`](crate::generic::Reg::read) this register and get [`uarticr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uarticr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uarticr`] +module"] pub type UARTICR = crate::Reg; #[doc = "Interrupt Clear Register, UARTICR"] pub mod uarticr; -#[doc = "UARTDMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "UARTDMACR (rw) register accessor: DMA Control Register, UARTDMACR + +You can [`read`](crate::generic::Reg::read) this register and get [`uartdmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartdmacr`] +module"] pub type UARTDMACR = crate::Reg; #[doc = "DMA Control Register, UARTDMACR"] pub mod uartdmacr; -#[doc = "UARTPERIPHID0 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPERIPHID0 (r) register accessor: UARTPeriphID0 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid0`] +module"] pub type UARTPERIPHID0 = crate::Reg; #[doc = "UARTPeriphID0 Register"] pub mod uartperiphid0; -#[doc = "UARTPERIPHID1 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPERIPHID1 (r) register accessor: UARTPeriphID1 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid1`] +module"] pub type UARTPERIPHID1 = crate::Reg; #[doc = "UARTPeriphID1 Register"] pub mod uartperiphid1; -#[doc = "UARTPERIPHID2 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPERIPHID2 (r) register accessor: UARTPeriphID2 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid2`] +module"] pub type UARTPERIPHID2 = crate::Reg; #[doc = "UARTPeriphID2 Register"] pub mod uartperiphid2; -#[doc = "UARTPERIPHID3 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPERIPHID3 (r) register accessor: UARTPeriphID3 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid3`] +module"] pub type UARTPERIPHID3 = crate::Reg; #[doc = "UARTPeriphID3 Register"] pub mod uartperiphid3; -#[doc = "UARTPCELLID0 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPCELLID0 (r) register accessor: UARTPCellID0 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid0`] +module"] pub type UARTPCELLID0 = crate::Reg; #[doc = "UARTPCellID0 Register"] pub mod uartpcellid0; -#[doc = "UARTPCELLID1 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPCELLID1 (r) register accessor: UARTPCellID1 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid1`] +module"] pub type UARTPCELLID1 = crate::Reg; #[doc = "UARTPCellID1 Register"] pub mod uartpcellid1; -#[doc = "UARTPCELLID2 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPCELLID2 (r) register accessor: UARTPCellID2 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid2`] +module"] pub type UARTPCELLID2 = crate::Reg; #[doc = "UARTPCellID2 Register"] pub mod uartpcellid2; -#[doc = "UARTPCELLID3 (r) register accessor: an alias for `Reg`"] +#[doc = "UARTPCELLID3 (r) register accessor: UARTPCellID3 Register + +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid3`] +module"] pub type UARTPCELLID3 = crate::Reg; #[doc = "UARTPCellID3 Register"] pub mod uartpcellid3; diff --git a/src/uart0/uartcr.rs b/src/uart0/uartcr.rs index be8af5e2c..d89e9adea 100644 --- a/src/uart0/uartcr.rs +++ b/src/uart0/uartcr.rs @@ -1,87 +1,55 @@ #[doc = "Register `UARTCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UARTEN` reader - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] pub type UARTEN_R = crate::BitReader; #[doc = "Field `UARTEN` writer - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] -pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type UARTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIREN` reader - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] pub type SIREN_R = crate::BitReader; #[doc = "Field `SIREN` writer - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] -pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type SIREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIRLP` reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] pub type SIRLP_R = crate::BitReader; #[doc = "Field `SIRLP` writer - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] -pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type SIRLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LBE` reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] pub type LBE_R = crate::BitReader; #[doc = "Field `LBE` writer - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] -pub type LBE_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type LBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE` reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] pub type TXE_R = crate::BitReader; #[doc = "Field `TXE` writer - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] -pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type TXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXE` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] pub type RXE_R = crate::BitReader; #[doc = "Field `RXE` writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] -pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type RXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTR` reader - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] pub type DTR_R = crate::BitReader; #[doc = "Field `DTR` writer - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] -pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS` reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT1` reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] pub type OUT1_R = crate::BitReader; #[doc = "Field `OUT1` writer - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] -pub type OUT1_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT2` reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] pub type OUT2_R = crate::BitReader; #[doc = "Field `OUT2` writer - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] -pub type OUT2_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSEN` reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] pub type RTSEN_R = crate::BitReader; #[doc = "Field `RTSEN` writer - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] -pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type RTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSEN` reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] pub type CTSEN_R = crate::BitReader; #[doc = "Field `CTSEN` writer - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] -pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, UARTCR_SPEC, O>; +pub type CTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] #[inline(always)] @@ -148,98 +116,97 @@ impl W { #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] #[inline(always)] #[must_use] - pub fn uarten(&mut self) -> UARTEN_W<0> { + pub fn uarten(&mut self) -> UARTEN_W { UARTEN_W::new(self) } #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] #[inline(always)] #[must_use] - pub fn siren(&mut self) -> SIREN_W<1> { + pub fn siren(&mut self) -> SIREN_W { SIREN_W::new(self) } #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] #[inline(always)] #[must_use] - pub fn sirlp(&mut self) -> SIRLP_W<2> { + pub fn sirlp(&mut self) -> SIRLP_W { SIRLP_W::new(self) } #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] #[inline(always)] #[must_use] - pub fn lbe(&mut self) -> LBE_W<7> { + pub fn lbe(&mut self) -> LBE_W { LBE_W::new(self) } #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] #[inline(always)] #[must_use] - pub fn txe(&mut self) -> TXE_W<8> { + pub fn txe(&mut self) -> TXE_W { TXE_W::new(self) } #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] #[inline(always)] #[must_use] - pub fn rxe(&mut self) -> RXE_W<9> { + pub fn rxe(&mut self) -> RXE_W { RXE_W::new(self) } #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W<10> { + pub fn dtr(&mut self) -> DTR_W { DTR_W::new(self) } #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<11> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W<12> { + pub fn out1(&mut self) -> OUT1_W { OUT1_W::new(self) } #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W<13> { + pub fn out2(&mut self) -> OUT2_W { OUT2_W::new(self) } #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] #[inline(always)] #[must_use] - pub fn rtsen(&mut self) -> RTSEN_W<14> { + pub fn rtsen(&mut self) -> RTSEN_W { RTSEN_W::new(self) } #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] #[inline(always)] #[must_use] - pub fn ctsen(&mut self) -> CTSEN_W<15> { + pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control Register, UARTCR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTCR_SPEC; impl crate::RegisterSpec for UARTCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartcr::R](R) reader structure"] -impl crate::Readable for UARTCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartcr::W](W) writer structure"] +#[doc = "`read()` method returns [`uartcr::R`](R) reader structure"] +impl crate::Readable for UARTCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartcr::W`](W) writer structure"] impl crate::Writable for UARTCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartdmacr.rs b/src/uart0/uartdmacr.rs index 8f7c8cc98..884875a75 100644 --- a/src/uart0/uartdmacr.rs +++ b/src/uart0/uartdmacr.rs @@ -1,51 +1,19 @@ #[doc = "Register `UARTDMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTDMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXDMAE` reader - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `RXDMAE` writer - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, UARTDMACR_SPEC, O>; +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMAE` reader - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `TXDMAE` writer - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, UARTDMACR_SPEC, O>; +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAONERR` reader - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] pub type DMAONERR_R = crate::BitReader; #[doc = "Field `DMAONERR` writer - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] -pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, UARTDMACR_SPEC, O>; +pub type DMAONERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -67,44 +35,43 @@ impl W { #[doc = "Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + pub fn rxdmae(&mut self) -> RXDMAE_W { RXDMAE_W::new(self) } #[doc = "Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W<1> { + pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self) } #[doc = "Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] #[inline(always)] #[must_use] - pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + pub fn dmaonerr(&mut self) -> DMAONERR_W { DMAONERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA Control Register, UARTDMACR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartdmacr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartdmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTDMACR_SPEC; impl crate::RegisterSpec for UARTDMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartdmacr::R](R) reader structure"] -impl crate::Readable for UARTDMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartdmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`uartdmacr::R`](R) reader structure"] +impl crate::Readable for UARTDMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartdmacr::W`](W) writer structure"] impl crate::Writable for UARTDMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs index a38f58591..cb154552c 100644 --- a/src/uart0/uartdr.rs +++ b/src/uart0/uartdr.rs @@ -1,43 +1,11 @@ #[doc = "Register `UARTDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Receive (read) data character. Transmit (write) data character."] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Receive (read) data character. Transmit (write) data character."] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, UARTDR_SPEC, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."] pub type FE_R = crate::BitReader; #[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."] @@ -77,32 +45,31 @@ impl W { #[doc = "Bits 0:7 - Receive (read) data character. Transmit (write) data character."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Data Register, UARTDR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartdr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTDR_SPEC; impl crate::RegisterSpec for UARTDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartdr::R](R) reader structure"] -impl crate::Readable for UARTDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartdr::W](W) writer structure"] +#[doc = "`read()` method returns [`uartdr::R`](R) reader structure"] +impl crate::Readable for UARTDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartdr::W`](W) writer structure"] impl crate::Writable for UARTDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartfbrd.rs b/src/uart0/uartfbrd.rs index 7f8b49b45..40027be8f 100644 --- a/src/uart0/uartfbrd.rs +++ b/src/uart0/uartfbrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `UARTFBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTFBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUD_DIVFRAC` reader - The fractional baud rate divisor. These bits are cleared to 0 on reset."] pub type BAUD_DIVFRAC_R = crate::FieldReader; #[doc = "Field `BAUD_DIVFRAC` writer - The fractional baud rate divisor. These bits are cleared to 0 on reset."] -pub type BAUD_DIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, UARTFBRD_SPEC, 6, O>; +pub type BAUD_DIVFRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset."] #[inline(always)] #[must_use] - pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W<0> { + pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W { BAUD_DIVFRAC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Fractional Baud Rate Register, UARTFBRD -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartfbrd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartfbrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTFBRD_SPEC; impl crate::RegisterSpec for UARTFBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartfbrd::R](R) reader structure"] -impl crate::Readable for UARTFBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartfbrd::W](W) writer structure"] +#[doc = "`read()` method returns [`uartfbrd::R`](R) reader structure"] +impl crate::Readable for UARTFBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartfbrd::W`](W) writer structure"] impl crate::Writable for UARTFBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartfr.rs b/src/uart0/uartfr.rs index 525d7a145..dd4c24da6 100644 --- a/src/uart0/uartfr.rs +++ b/src/uart0/uartfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."] pub type CTS_R = crate::BitReader; #[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."] @@ -80,17 +67,13 @@ impl R { } #[doc = "Flag Register, UARTFR -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartfr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTFR_SPEC; impl crate::RegisterSpec for UARTFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartfr::R](R) reader structure"] -impl crate::Readable for UARTFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartfr::R`](R) reader structure"] +impl crate::Readable for UARTFR_SPEC {} #[doc = "`reset()` method sets UARTFR to value 0x90"] impl crate::Resettable for UARTFR_SPEC { const RESET_VALUE: Self::Ux = 0x90; diff --git a/src/uart0/uartibrd.rs b/src/uart0/uartibrd.rs index ab5cd72ba..00be9b245 100644 --- a/src/uart0/uartibrd.rs +++ b/src/uart0/uartibrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `UARTIBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTIBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUD_DIVINT` reader - The integer baud rate divisor. These bits are cleared to 0 on reset."] pub type BAUD_DIVINT_R = crate::FieldReader; #[doc = "Field `BAUD_DIVINT` writer - The integer baud rate divisor. These bits are cleared to 0 on reset."] -pub type BAUD_DIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, UARTIBRD_SPEC, 16, O, u16>; +pub type BAUD_DIVINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset."] #[inline(always)] #[must_use] - pub fn baud_divint(&mut self) -> BAUD_DIVINT_W<0> { + pub fn baud_divint(&mut self) -> BAUD_DIVINT_W { BAUD_DIVINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Integer Baud Rate Register, UARTIBRD -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartibrd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartibrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTIBRD_SPEC; impl crate::RegisterSpec for UARTIBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartibrd::R](R) reader structure"] -impl crate::Readable for UARTIBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartibrd::W](W) writer structure"] +#[doc = "`read()` method returns [`uartibrd::R`](R) reader structure"] +impl crate::Readable for UARTIBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartibrd::W`](W) writer structure"] impl crate::Writable for UARTIBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uarticr.rs b/src/uart0/uarticr.rs index cc9a9c18b..123dc5d42 100644 --- a/src/uart0/uarticr.rs +++ b/src/uart0/uarticr.rs @@ -1,83 +1,51 @@ #[doc = "Register `UARTICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIC` reader - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] pub type RIMIC_R = crate::BitReader; #[doc = "Field `RIMIC` writer - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] -pub type RIMIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type RIMIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CTSMIC` reader - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] pub type CTSMIC_R = crate::BitReader; #[doc = "Field `CTSMIC` writer - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] -pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type CTSMIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DCDMIC` reader - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] pub type DCDMIC_R = crate::BitReader; #[doc = "Field `DCDMIC` writer - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] -pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type DCDMIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSRMIC` reader - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] pub type DSRMIC_R = crate::BitReader; #[doc = "Field `DSRMIC` writer - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] -pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type DSRMIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RXIC` reader - Receive interrupt clear. Clears the UARTRXINTR interrupt."] pub type RXIC_R = crate::BitReader; #[doc = "Field `RXIC` writer - Receive interrupt clear. Clears the UARTRXINTR interrupt."] -pub type RXIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type RXIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TXIC` reader - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] pub type TXIC_R = crate::BitReader; #[doc = "Field `TXIC` writer - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] -pub type TXIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type TXIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RTIC` reader - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] pub type RTIC_R = crate::BitReader; #[doc = "Field `RTIC` writer - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] -pub type RTIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `FEIC` reader - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] pub type FEIC_R = crate::BitReader; #[doc = "Field `FEIC` writer - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] -pub type FEIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type FEIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PEIC` reader - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] pub type PEIC_R = crate::BitReader; #[doc = "Field `PEIC` writer - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] -pub type PEIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type PEIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `BEIC` reader - Break error interrupt clear. Clears the UARTBEINTR interrupt."] pub type BEIC_R = crate::BitReader; #[doc = "Field `BEIC` writer - Break error interrupt clear. Clears the UARTBEINTR interrupt."] -pub type BEIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type BEIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `OEIC` reader - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] pub type OEIC_R = crate::BitReader; #[doc = "Field `OEIC` writer - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] -pub type OEIC_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTICR_SPEC, O>; +pub type OEIC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] #[inline(always)] @@ -139,92 +107,91 @@ impl W { #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] #[inline(always)] #[must_use] - pub fn rimic(&mut self) -> RIMIC_W<0> { + pub fn rimic(&mut self) -> RIMIC_W { RIMIC_W::new(self) } #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] #[inline(always)] #[must_use] - pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + pub fn ctsmic(&mut self) -> CTSMIC_W { CTSMIC_W::new(self) } #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] #[inline(always)] #[must_use] - pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + pub fn dcdmic(&mut self) -> DCDMIC_W { DCDMIC_W::new(self) } #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] #[inline(always)] #[must_use] - pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + pub fn dsrmic(&mut self) -> DSRMIC_W { DSRMIC_W::new(self) } #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."] #[inline(always)] #[must_use] - pub fn rxic(&mut self) -> RXIC_W<4> { + pub fn rxic(&mut self) -> RXIC_W { RXIC_W::new(self) } #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] #[inline(always)] #[must_use] - pub fn txic(&mut self) -> TXIC_W<5> { + pub fn txic(&mut self) -> TXIC_W { TXIC_W::new(self) } #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W<6> { + pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self) } #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] #[inline(always)] #[must_use] - pub fn feic(&mut self) -> FEIC_W<7> { + pub fn feic(&mut self) -> FEIC_W { FEIC_W::new(self) } #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] #[inline(always)] #[must_use] - pub fn peic(&mut self) -> PEIC_W<8> { + pub fn peic(&mut self) -> PEIC_W { PEIC_W::new(self) } #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."] #[inline(always)] #[must_use] - pub fn beic(&mut self) -> BEIC_W<9> { + pub fn beic(&mut self) -> BEIC_W { BEIC_W::new(self) } #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] #[inline(always)] #[must_use] - pub fn oeic(&mut self) -> OEIC_W<10> { + pub fn oeic(&mut self) -> OEIC_W { OEIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Clear Register, UARTICR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uarticr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uarticr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uarticr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTICR_SPEC; impl crate::RegisterSpec for UARTICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uarticr::R](R) reader structure"] -impl crate::Readable for UARTICR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uarticr::W](W) writer structure"] +#[doc = "`read()` method returns [`uarticr::R`](R) reader structure"] +impl crate::Readable for UARTICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uarticr::W`](W) writer structure"] impl crate::Writable for UARTICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x07ff; } diff --git a/src/uart0/uartifls.rs b/src/uart0/uartifls.rs index 3ff94ce4b..76112c0c8 100644 --- a/src/uart0/uartifls.rs +++ b/src/uart0/uartifls.rs @@ -1,47 +1,15 @@ #[doc = "Register `UARTIFLS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTIFLS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] pub type TXIFLSEL_R = crate::FieldReader; #[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] -pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, UARTIFLS_SPEC, 3, O>; +pub type TXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] pub type RXIFLSEL_R = crate::FieldReader; #[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] -pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, UARTIFLS_SPEC, 3, O>; +pub type RXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] #[inline(always)] #[must_use] - pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + pub fn txiflsel(&mut self) -> TXIFLSEL_W { TXIFLSEL_W::new(self) } #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] #[inline(always)] #[must_use] - pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + pub fn rxiflsel(&mut self) -> RXIFLSEL_W { RXIFLSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt FIFO Level Select Register, UARTIFLS -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartifls](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartifls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTIFLS_SPEC; impl crate::RegisterSpec for UARTIFLS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartifls::R](R) reader structure"] -impl crate::Readable for UARTIFLS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartifls::W](W) writer structure"] +#[doc = "`read()` method returns [`uartifls::R`](R) reader structure"] +impl crate::Readable for UARTIFLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartifls::W`](W) writer structure"] impl crate::Writable for UARTIFLS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartilpr.rs b/src/uart0/uartilpr.rs index ad39f70b4..c93d103ca 100644 --- a/src/uart0/uartilpr.rs +++ b/src/uart0/uartilpr.rs @@ -1,43 +1,11 @@ #[doc = "Register `UARTILPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTILPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ILPDVSR` reader - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] pub type ILPDVSR_R = crate::FieldReader; #[doc = "Field `ILPDVSR` writer - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] -pub type ILPDVSR_W<'a, const O: u8> = crate::FieldWriter<'a, UARTILPR_SPEC, 8, O>; +pub type ILPDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] #[inline(always)] #[must_use] - pub fn ilpdvsr(&mut self) -> ILPDVSR_W<0> { + pub fn ilpdvsr(&mut self) -> ILPDVSR_W { ILPDVSR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "IrDA Low-Power Counter Register, UARTILPR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartilpr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartilpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartilpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTILPR_SPEC; impl crate::RegisterSpec for UARTILPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartilpr::R](R) reader structure"] -impl crate::Readable for UARTILPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartilpr::W](W) writer structure"] +#[doc = "`read()` method returns [`uartilpr::R`](R) reader structure"] +impl crate::Readable for UARTILPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartilpr::W`](W) writer structure"] impl crate::Writable for UARTILPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartimsc.rs b/src/uart0/uartimsc.rs index 2006721f6..4ede3a4a7 100644 --- a/src/uart0/uartimsc.rs +++ b/src/uart0/uartimsc.rs @@ -1,83 +1,51 @@ #[doc = "Register `UARTIMSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTIMSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIM` reader - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] pub type RIMIM_R = crate::BitReader; #[doc = "Field `RIMIM` writer - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] -pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type RIMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIM` reader - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] pub type CTSMIM_R = crate::BitReader; #[doc = "Field `CTSMIM` writer - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] -pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type CTSMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIM` reader - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] pub type DCDMIM_R = crate::BitReader; #[doc = "Field `DCDMIM` writer - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] -pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type DCDMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIM` reader - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] pub type DSRMIM_R = crate::BitReader; #[doc = "Field `DSRMIM` writer - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] -pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type DSRMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIM` reader - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] pub type RXIM_R = crate::BitReader; #[doc = "Field `RXIM` writer - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] -pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIM` reader - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] pub type TXIM_R = crate::BitReader; #[doc = "Field `TXIM` writer - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] -pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIM` reader - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] pub type RTIM_R = crate::BitReader; #[doc = "Field `RTIM` writer - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] -pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIM` reader - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] pub type FEIM_R = crate::BitReader; #[doc = "Field `FEIM` writer - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] -pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type FEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIM` reader - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] pub type PEIM_R = crate::BitReader; #[doc = "Field `PEIM` writer - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] -pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type PEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIM` reader - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] pub type BEIM_R = crate::BitReader; #[doc = "Field `BEIM` writer - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] -pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type BEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIM` reader - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] pub type OEIM_R = crate::BitReader; #[doc = "Field `OEIM` writer - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] -pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, UARTIMSC_SPEC, O>; +pub type OEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] @@ -139,92 +107,91 @@ impl W { #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn rimim(&mut self) -> RIMIM_W<0> { + pub fn rimim(&mut self) -> RIMIM_W { RIMIM_W::new(self) } #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + pub fn ctsmim(&mut self) -> CTSMIM_W { CTSMIM_W::new(self) } #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + pub fn dcdmim(&mut self) -> DCDMIM_W { DCDMIM_W::new(self) } #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + pub fn dsrmim(&mut self) -> DSRMIM_W { DSRMIM_W::new(self) } #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W<4> { + pub fn rxim(&mut self) -> RXIM_W { RXIM_W::new(self) } #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W<5> { + pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self) } #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W<6> { + pub fn rtim(&mut self) -> RTIM_W { RTIM_W::new(self) } #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn feim(&mut self) -> FEIM_W<7> { + pub fn feim(&mut self) -> FEIM_W { FEIM_W::new(self) } #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn peim(&mut self) -> PEIM_W<8> { + pub fn peim(&mut self) -> PEIM_W { PEIM_W::new(self) } #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn beim(&mut self) -> BEIM_W<9> { + pub fn beim(&mut self) -> BEIM_W { BEIM_W::new(self) } #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] #[inline(always)] #[must_use] - pub fn oeim(&mut self) -> OEIM_W<10> { + pub fn oeim(&mut self) -> OEIM_W { OEIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartimsc](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartimsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTIMSC_SPEC; impl crate::RegisterSpec for UARTIMSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartimsc::R](R) reader structure"] -impl crate::Readable for UARTIMSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartimsc::W](W) writer structure"] +#[doc = "`read()` method returns [`uartimsc::R`](R) reader structure"] +impl crate::Readable for UARTIMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartimsc::W`](W) writer structure"] impl crate::Writable for UARTIMSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartlcr_h.rs b/src/uart0/uartlcr_h.rs index 7ee7a0b24..f390f85cc 100644 --- a/src/uart0/uartlcr_h.rs +++ b/src/uart0/uartlcr_h.rs @@ -1,67 +1,35 @@ #[doc = "Register `UARTLCR_H` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTLCR_H` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BRK` reader - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] pub type BRK_R = crate::BitReader; #[doc = "Field `BRK` writer - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] -pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type BRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN` reader - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] pub type PEN_R = crate::BitReader; #[doc = "Field `PEN` writer - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] -pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPS` reader - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] pub type EPS_R = crate::BitReader; #[doc = "Field `EPS` writer - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] -pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STP2` reader - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] pub type STP2_R = crate::BitReader; #[doc = "Field `STP2` writer - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] -pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type STP2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN` reader - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] pub type FEN_R = crate::BitReader; #[doc = "Field `FEN` writer - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] -pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type FEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WLEN` reader - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] pub type WLEN_R = crate::FieldReader; #[doc = "Field `WLEN` writer - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] -pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, UARTLCR_H_SPEC, 2, O>; +pub type WLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `SPS` reader - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] pub type SPS_R = crate::BitReader; #[doc = "Field `SPS` writer - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] -pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, UARTLCR_H_SPEC, O>; +pub type SPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] #[inline(always)] @@ -103,68 +71,67 @@ impl W { #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] #[inline(always)] #[must_use] - pub fn brk(&mut self) -> BRK_W<0> { + pub fn brk(&mut self) -> BRK_W { BRK_W::new(self) } #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W<1> { + pub fn pen(&mut self) -> PEN_W { PEN_W::new(self) } #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W<2> { + pub fn eps(&mut self) -> EPS_W { EPS_W::new(self) } #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] #[inline(always)] #[must_use] - pub fn stp2(&mut self) -> STP2_W<3> { + pub fn stp2(&mut self) -> STP2_W { STP2_W::new(self) } #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] #[inline(always)] #[must_use] - pub fn fen(&mut self) -> FEN_W<4> { + pub fn fen(&mut self) -> FEN_W { FEN_W::new(self) } #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] #[inline(always)] #[must_use] - pub fn wlen(&mut self) -> WLEN_W<5> { + pub fn wlen(&mut self) -> WLEN_W { WLEN_W::new(self) } #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] #[inline(always)] #[must_use] - pub fn sps(&mut self) -> SPS_W<7> { + pub fn sps(&mut self) -> SPS_W { SPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Line Control Register, UARTLCR_H -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartlcr_h](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartlcr_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartlcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTLCR_H_SPEC; impl crate::RegisterSpec for UARTLCR_H_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartlcr_h::R](R) reader structure"] -impl crate::Readable for UARTLCR_H_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartlcr_h::W](W) writer structure"] +#[doc = "`read()` method returns [`uartlcr_h::R`](R) reader structure"] +impl crate::Readable for UARTLCR_H_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartlcr_h::W`](W) writer structure"] impl crate::Writable for UARTLCR_H_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/uart0/uartmis.rs b/src/uart0/uartmis.rs index aea2355b2..7db5c00a7 100644 --- a/src/uart0/uartmis.rs +++ b/src/uart0/uartmis.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTMIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIMMIS` reader - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."] pub type RIMMIS_R = crate::BitReader; #[doc = "Field `CTSMMIS` reader - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."] @@ -94,17 +81,13 @@ impl R { } #[doc = "Masked Interrupt Status Register, UARTMIS -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartmis](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTMIS_SPEC; impl crate::RegisterSpec for UARTMIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartmis::R](R) reader structure"] -impl crate::Readable for UARTMIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartmis::R`](R) reader structure"] +impl crate::Readable for UARTMIS_SPEC {} #[doc = "`reset()` method sets UARTMIS to value 0"] impl crate::Resettable for UARTMIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/uart0/uartpcellid0.rs b/src/uart0/uartpcellid0.rs index 1adff354d..a0a223037 100644 --- a/src/uart0/uartpcellid0.rs +++ b/src/uart0/uartpcellid0.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPCELLID0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UARTPCELLID0` reader - These bits read back as 0x0D"] pub type UARTPCELLID0_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPCellID0 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartpcellid0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID0_SPEC; impl crate::RegisterSpec for UARTPCELLID0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartpcellid0::R](R) reader structure"] -impl crate::Readable for UARTPCELLID0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartpcellid0::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID0_SPEC {} #[doc = "`reset()` method sets UARTPCELLID0 to value 0x0d"] impl crate::Resettable for UARTPCELLID0_SPEC { const RESET_VALUE: Self::Ux = 0x0d; diff --git a/src/uart0/uartpcellid1.rs b/src/uart0/uartpcellid1.rs index 8d05b4a31..3eec7b6cd 100644 --- a/src/uart0/uartpcellid1.rs +++ b/src/uart0/uartpcellid1.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPCELLID1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UARTPCELLID1` reader - These bits read back as 0xF0"] pub type UARTPCELLID1_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPCellID1 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartpcellid1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID1_SPEC; impl crate::RegisterSpec for UARTPCELLID1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartpcellid1::R](R) reader structure"] -impl crate::Readable for UARTPCELLID1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartpcellid1::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID1_SPEC {} #[doc = "`reset()` method sets UARTPCELLID1 to value 0xf0"] impl crate::Resettable for UARTPCELLID1_SPEC { const RESET_VALUE: Self::Ux = 0xf0; diff --git a/src/uart0/uartpcellid2.rs b/src/uart0/uartpcellid2.rs index 9d1f1360f..d9a2fd3c7 100644 --- a/src/uart0/uartpcellid2.rs +++ b/src/uart0/uartpcellid2.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPCELLID2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UARTPCELLID2` reader - These bits read back as 0x05"] pub type UARTPCELLID2_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPCellID2 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartpcellid2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID2_SPEC; impl crate::RegisterSpec for UARTPCELLID2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartpcellid2::R](R) reader structure"] -impl crate::Readable for UARTPCELLID2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartpcellid2::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID2_SPEC {} #[doc = "`reset()` method sets UARTPCELLID2 to value 0x05"] impl crate::Resettable for UARTPCELLID2_SPEC { const RESET_VALUE: Self::Ux = 0x05; diff --git a/src/uart0/uartpcellid3.rs b/src/uart0/uartpcellid3.rs index bebfb2376..6d607277d 100644 --- a/src/uart0/uartpcellid3.rs +++ b/src/uart0/uartpcellid3.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPCELLID3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UARTPCELLID3` reader - These bits read back as 0xB1"] pub type UARTPCELLID3_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPCellID3 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartpcellid3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID3_SPEC; impl crate::RegisterSpec for UARTPCELLID3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartpcellid3::R](R) reader structure"] -impl crate::Readable for UARTPCELLID3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartpcellid3::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID3_SPEC {} #[doc = "`reset()` method sets UARTPCELLID3 to value 0xb1"] impl crate::Resettable for UARTPCELLID3_SPEC { const RESET_VALUE: Self::Ux = 0xb1; diff --git a/src/uart0/uartperiphid0.rs b/src/uart0/uartperiphid0.rs index 9e222d232..9ec22ab40 100644 --- a/src/uart0/uartperiphid0.rs +++ b/src/uart0/uartperiphid0.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPERIPHID0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x11"] pub type PARTNUMBER0_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPeriphID0 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartperiphid0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID0_SPEC; impl crate::RegisterSpec for UARTPERIPHID0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartperiphid0::R](R) reader structure"] -impl crate::Readable for UARTPERIPHID0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartperiphid0::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID0_SPEC {} #[doc = "`reset()` method sets UARTPERIPHID0 to value 0x11"] impl crate::Resettable for UARTPERIPHID0_SPEC { const RESET_VALUE: Self::Ux = 0x11; diff --git a/src/uart0/uartperiphid1.rs b/src/uart0/uartperiphid1.rs index c4056182f..d214acffe 100644 --- a/src/uart0/uartperiphid1.rs +++ b/src/uart0/uartperiphid1.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPERIPHID1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub type PARTNUMBER1_R = crate::FieldReader; #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] @@ -31,17 +18,13 @@ impl R { } #[doc = "UARTPeriphID1 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartperiphid1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID1_SPEC; impl crate::RegisterSpec for UARTPERIPHID1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartperiphid1::R](R) reader structure"] -impl crate::Readable for UARTPERIPHID1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartperiphid1::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID1_SPEC {} #[doc = "`reset()` method sets UARTPERIPHID1 to value 0x10"] impl crate::Resettable for UARTPERIPHID1_SPEC { const RESET_VALUE: Self::Ux = 0x10; diff --git a/src/uart0/uartperiphid2.rs b/src/uart0/uartperiphid2.rs index 27f1db0cf..5a5fad1a6 100644 --- a/src/uart0/uartperiphid2.rs +++ b/src/uart0/uartperiphid2.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPERIPHID2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub type DESIGNER1_R = crate::FieldReader; #[doc = "Field `REVISION` reader - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"] @@ -31,17 +18,13 @@ impl R { } #[doc = "UARTPeriphID2 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartperiphid2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID2_SPEC; impl crate::RegisterSpec for UARTPERIPHID2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartperiphid2::R](R) reader structure"] -impl crate::Readable for UARTPERIPHID2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartperiphid2::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID2_SPEC {} #[doc = "`reset()` method sets UARTPERIPHID2 to value 0x34"] impl crate::Resettable for UARTPERIPHID2_SPEC { const RESET_VALUE: Self::Ux = 0x34; diff --git a/src/uart0/uartperiphid3.rs b/src/uart0/uartperiphid3.rs index 5952182d4..690b50707 100644 --- a/src/uart0/uartperiphid3.rs +++ b/src/uart0/uartperiphid3.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTPERIPHID3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub type CONFIGURATION_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "UARTPeriphID3 Register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartperiphid3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID3_SPEC; impl crate::RegisterSpec for UARTPERIPHID3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartperiphid3::R](R) reader structure"] -impl crate::Readable for UARTPERIPHID3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartperiphid3::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID3_SPEC {} #[doc = "`reset()` method sets UARTPERIPHID3 to value 0"] impl crate::Resettable for UARTPERIPHID3_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/uart0/uartris.rs b/src/uart0/uartris.rs index 64eb4e89c..314996a3a 100644 --- a/src/uart0/uartris.rs +++ b/src/uart0/uartris.rs @@ -1,18 +1,5 @@ #[doc = "Register `UARTRIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIRMIS` reader - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."] pub type RIRMIS_R = crate::BitReader; #[doc = "Field `CTSRMIS` reader - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."] @@ -94,17 +81,13 @@ impl R { } #[doc = "Raw Interrupt Status Register, UARTRIS -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartris](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTRIS_SPEC; impl crate::RegisterSpec for UARTRIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartris::R](R) reader structure"] -impl crate::Readable for UARTRIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uartris::R`](R) reader structure"] +impl crate::Readable for UARTRIS_SPEC {} #[doc = "`reset()` method sets UARTRIS to value 0"] impl crate::Resettable for UARTRIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/uart0/uartrsr.rs b/src/uart0/uartrsr.rs index b65a89f2f..dc30c16ba 100644 --- a/src/uart0/uartrsr.rs +++ b/src/uart0/uartrsr.rs @@ -1,55 +1,23 @@ #[doc = "Register `UARTRSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UARTRSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] pub type FE_R = crate::BitReader; #[doc = "Field `FE` writer - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] -pub type FE_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTRSR_SPEC, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] pub type PE_R = crate::BitReader; #[doc = "Field `PE` writer - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] -pub type PE_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTRSR_SPEC, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] pub type BE_R = crate::BitReader; #[doc = "Field `BE` writer - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] -pub type BE_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTRSR_SPEC, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] pub type OE_R = crate::BitReader; #[doc = "Field `OE` writer - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] -pub type OE_W<'a, const O: u8> = crate::BitWriter1C<'a, UARTRSR_SPEC, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<0> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<1> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<2> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<3> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [uartrsr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`uartrsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartrsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTRSR_SPEC; impl crate::RegisterSpec for UARTRSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uartrsr::R](R) reader structure"] -impl crate::Readable for UARTRSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [uartrsr::W](W) writer structure"] +#[doc = "`read()` method returns [`uartrsr::R`](R) reader structure"] +impl crate::Readable for UARTRSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartrsr::W`](W) writer structure"] impl crate::Writable for UARTRSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/src/usbctrl_dpram.rs b/src/usbctrl_dpram.rs index 2f97e9c41..fc6d9279d 100644 --- a/src/usbctrl_dpram.rs +++ b/src/usbctrl_dpram.rs @@ -12,23 +12,48 @@ pub struct RegisterBlock { #[doc = "0x100 - EPx Control (Host-mode only!)"] pub epx_control: EPX_CONTROL, } -#[doc = "SETUP_PACKET_LOW (rw) register accessor: an alias for `Reg`"] +#[doc = "SETUP_PACKET_LOW (rw) register accessor: Bytes 0-3 of the SETUP packet from the host. + +You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_packet_low`] +module"] pub type SETUP_PACKET_LOW = crate::Reg; #[doc = "Bytes 0-3 of the SETUP packet from the host."] pub mod setup_packet_low; -#[doc = "SETUP_PACKET_HIGH (rw) register accessor: an alias for `Reg`"] +#[doc = "SETUP_PACKET_HIGH (rw) register accessor: Bytes 4-7 of the setup packet from the host. + +You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_packet_high`] +module"] pub type SETUP_PACKET_HIGH = crate::Reg; #[doc = "Bytes 4-7 of the setup packet from the host."] pub mod setup_packet_high; -#[doc = "EP_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_CONTROL (rw) register accessor: - + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_control`] +module"] pub type EP_CONTROL = crate::Reg; #[doc = "-"] pub mod ep_control; -#[doc = "EP_BUFFER_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_BUFFER_CONTROL (rw) register accessor: - + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_buffer_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_buffer_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_buffer_control`] +module"] pub type EP_BUFFER_CONTROL = crate::Reg; #[doc = "-"] pub mod ep_buffer_control; -#[doc = "EPX_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "EPX_CONTROL (rw) register accessor: EPx Control (Host-mode only!) + +You can [`read`](crate::generic::Reg::read) this register and get [`epx_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`epx_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@epx_control`] +module"] pub type EPX_CONTROL = crate::Reg; #[doc = "EPx Control (Host-mode only!)"] pub mod epx_control; diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs index a3e56c970..a26702ebb 100644 --- a/src/usbctrl_dpram/ep_buffer_control.rs +++ b/src/usbctrl_dpram/ep_buffer_control.rs @@ -1,75 +1,43 @@ #[doc = "Register `EP_BUFFER_CONTROL%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_BUFFER_CONTROL%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LENGTH_0` reader - The length of the data in buffer 0."] pub type LENGTH_0_R = crate::FieldReader; #[doc = "Field `LENGTH_0` writer - The length of the data in buffer 0."] -pub type LENGTH_0_W<'a, const O: u8> = crate::FieldWriter<'a, EP_BUFFER_CONTROL_SPEC, 10, O, u16>; +pub type LENGTH_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `AVAILABLE_0` reader - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub type AVAILABLE_0_R = crate::BitReader; #[doc = "Field `AVAILABLE_0` writer - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] -pub type AVAILABLE_0_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type AVAILABLE_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - Reply with a stall (valid for both buffers)."] pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Reply with a stall (valid for both buffers)."] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESET` reader - Reset the buffer selector to buffer 0."] pub type RESET_R = crate::BitReader; #[doc = "Field `RESET` writer - Reset the buffer selector to buffer 0."] -pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID_0` reader - The data pid of buffer 0."] pub type PID_0_R = crate::BitReader; #[doc = "Field `PID_0` writer - The data pid of buffer 0."] -pub type PID_0_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type PID_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LAST_0` reader - Buffer 0 is the last buffer of the transfer."] pub type LAST_0_R = crate::BitReader; #[doc = "Field `LAST_0` writer - Buffer 0 is the last buffer of the transfer."] -pub type LAST_0_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type LAST_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FULL_0` reader - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] pub type FULL_0_R = crate::BitReader; #[doc = "Field `FULL_0` writer - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] -pub type FULL_0_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type FULL_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LENGTH_1` reader - The length of the data in buffer 1."] pub type LENGTH_1_R = crate::FieldReader; #[doc = "Field `LENGTH_1` writer - The length of the data in buffer 1."] -pub type LENGTH_1_W<'a, const O: u8> = crate::FieldWriter<'a, EP_BUFFER_CONTROL_SPEC, 10, O, u16>; +pub type LENGTH_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `AVAILABLE_1` reader - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub type AVAILABLE_1_R = crate::BitReader; #[doc = "Field `AVAILABLE_1` writer - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] -pub type AVAILABLE_1_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type AVAILABLE_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader; @@ -101,7 +69,7 @@ impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A { impl DOUBLE_BUFFER_ISO_OFFSET_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOUBLE_BUFFER_ISO_OFFSET_A { + pub const fn variant(&self) -> DOUBLE_BUFFER_ISO_OFFSET_A { match self.bits { 0 => DOUBLE_BUFFER_ISO_OFFSET_A::_128, 1 => DOUBLE_BUFFER_ISO_OFFSET_A::_256, @@ -110,22 +78,22 @@ impl DOUBLE_BUFFER_ISO_OFFSET_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_128`"] + #[doc = "`0`"] #[inline(always)] pub fn is_128(&self) -> bool { *self == DOUBLE_BUFFER_ISO_OFFSET_A::_128 } - #[doc = "Checks if the value of the field is `_256`"] + #[doc = "`1`"] #[inline(always)] pub fn is_256(&self) -> bool { *self == DOUBLE_BUFFER_ISO_OFFSET_A::_256 } - #[doc = "Checks if the value of the field is `_512`"] + #[doc = "`10`"] #[inline(always)] pub fn is_512(&self) -> bool { *self == DOUBLE_BUFFER_ISO_OFFSET_A::_512 } - #[doc = "Checks if the value of the field is `_1024`"] + #[doc = "`11`"] #[inline(always)] pub fn is_1024(&self) -> bool { *self == DOUBLE_BUFFER_ISO_OFFSET_A::_1024 @@ -133,42 +101,46 @@ impl DOUBLE_BUFFER_ISO_OFFSET_R { } #[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] -pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, EP_BUFFER_CONTROL_SPEC, 2, O, DOUBLE_BUFFER_ISO_OFFSET_A>; -impl<'a, const O: u8> DOUBLE_BUFFER_ISO_OFFSET_W<'a, O> { +pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, DOUBLE_BUFFER_ISO_OFFSET_A>; +impl<'a, REG, const O: u8> DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _128(self) -> &'a mut W { + pub fn _128(self) -> &'a mut crate::W { self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_128) } #[doc = "`1`"] #[inline(always)] - pub fn _256(self) -> &'a mut W { + pub fn _256(self) -> &'a mut crate::W { self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_256) } #[doc = "`10`"] #[inline(always)] - pub fn _512(self) -> &'a mut W { + pub fn _512(self) -> &'a mut crate::W { self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_512) } #[doc = "`11`"] #[inline(always)] - pub fn _1024(self) -> &'a mut W { + pub fn _1024(self) -> &'a mut crate::W { self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_1024) } } #[doc = "Field `PID_1` reader - The data pid of buffer 1."] pub type PID_1_R = crate::BitReader; #[doc = "Field `PID_1` writer - The data pid of buffer 1."] -pub type PID_1_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type PID_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LAST_1` reader - Buffer 1 is the last buffer of the transfer."] pub type LAST_1_R = crate::BitReader; #[doc = "Field `LAST_1` writer - Buffer 1 is the last buffer of the transfer."] -pub type LAST_1_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type LAST_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FULL_1` reader - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] pub type FULL_1_R = crate::BitReader; #[doc = "Field `FULL_1` writer - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] -pub type FULL_1_W<'a, const O: u8> = crate::BitWriter<'a, EP_BUFFER_CONTROL_SPEC, O>; +pub type FULL_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:9 - The length of the data in buffer 0."] #[inline(always)] @@ -241,105 +213,106 @@ impl W { #[doc = "Bits 0:9 - The length of the data in buffer 0."] #[inline(always)] #[must_use] - pub fn length_0(&mut self) -> LENGTH_0_W<0> { + pub fn length_0(&mut self) -> LENGTH_0_W { LENGTH_0_W::new(self) } #[doc = "Bit 10 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] #[inline(always)] #[must_use] - pub fn available_0(&mut self) -> AVAILABLE_0_W<10> { + pub fn available_0(&mut self) -> AVAILABLE_0_W { AVAILABLE_0_W::new(self) } #[doc = "Bit 11 - Reply with a stall (valid for both buffers)."] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<11> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 12 - Reset the buffer selector to buffer 0."] #[inline(always)] #[must_use] - pub fn reset(&mut self) -> RESET_W<12> { + pub fn reset(&mut self) -> RESET_W { RESET_W::new(self) } #[doc = "Bit 13 - The data pid of buffer 0."] #[inline(always)] #[must_use] - pub fn pid_0(&mut self) -> PID_0_W<13> { + pub fn pid_0(&mut self) -> PID_0_W { PID_0_W::new(self) } #[doc = "Bit 14 - Buffer 0 is the last buffer of the transfer."] #[inline(always)] #[must_use] - pub fn last_0(&mut self) -> LAST_0_W<14> { + pub fn last_0(&mut self) -> LAST_0_W { LAST_0_W::new(self) } #[doc = "Bit 15 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] #[inline(always)] #[must_use] - pub fn full_0(&mut self) -> FULL_0_W<15> { + pub fn full_0(&mut self) -> FULL_0_W { FULL_0_W::new(self) } #[doc = "Bits 16:25 - The length of the data in buffer 1."] #[inline(always)] #[must_use] - pub fn length_1(&mut self) -> LENGTH_1_W<16> { + pub fn length_1(&mut self) -> LENGTH_1_W { LENGTH_1_W::new(self) } #[doc = "Bit 26 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] #[inline(always)] #[must_use] - pub fn available_1(&mut self) -> AVAILABLE_1_W<26> { + pub fn available_1(&mut self) -> AVAILABLE_1_W { AVAILABLE_1_W::new(self) } #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] #[inline(always)] #[must_use] - pub fn double_buffer_iso_offset(&mut self) -> DOUBLE_BUFFER_ISO_OFFSET_W<27> { + pub fn double_buffer_iso_offset( + &mut self, + ) -> DOUBLE_BUFFER_ISO_OFFSET_W { DOUBLE_BUFFER_ISO_OFFSET_W::new(self) } #[doc = "Bit 29 - The data pid of buffer 1."] #[inline(always)] #[must_use] - pub fn pid_1(&mut self) -> PID_1_W<29> { + pub fn pid_1(&mut self) -> PID_1_W { PID_1_W::new(self) } #[doc = "Bit 30 - Buffer 1 is the last buffer of the transfer."] #[inline(always)] #[must_use] - pub fn last_1(&mut self) -> LAST_1_W<30> { + pub fn last_1(&mut self) -> LAST_1_W { LAST_1_W::new(self) } #[doc = "Bit 31 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] #[inline(always)] #[must_use] - pub fn full_1(&mut self) -> FULL_1_W<31> { + pub fn full_1(&mut self) -> FULL_1_W { FULL_1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "- -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_buffer_control](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_buffer_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_buffer_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_BUFFER_CONTROL_SPEC; impl crate::RegisterSpec for EP_BUFFER_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_buffer_control::R](R) reader structure"] -impl crate::Readable for EP_BUFFER_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_buffer_control::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_buffer_control::R`](R) reader structure"] +impl crate::Readable for EP_BUFFER_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_buffer_control::W`](W) writer structure"] impl crate::Writable for EP_BUFFER_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_dpram/ep_control.rs b/src/usbctrl_dpram/ep_control.rs index fd0ce44d5..5afb95155 100644 --- a/src/usbctrl_dpram/ep_control.rs +++ b/src/usbctrl_dpram/ep_control.rs @@ -1,56 +1,23 @@ #[doc = "Register `EP_CONTROL%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_CONTROL%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] pub type BUFFER_ADDRESS_R = crate::FieldReader; #[doc = "Field `BUFFER_ADDRESS` writer - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] -pub type BUFFER_ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, EP_CONTROL_SPEC, 16, O, u16>; +pub type BUFFER_ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."] pub type INTERRUPT_ON_NAK_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_NAK` writer - Trigger an interrupt if a NAK is sent. Intended for debug only."] -pub type INTERRUPT_ON_NAK_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type INTERRUPT_ON_NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_POLL_INTERVAL` reader - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."] pub type HOST_POLL_INTERVAL_R = crate::FieldReader; #[doc = "Field `HOST_POLL_INTERVAL` writer - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."] -pub type HOST_POLL_INTERVAL_W<'a, const O: u8> = - crate::FieldWriter<'a, EP_CONTROL_SPEC, 10, O, u16>; +pub type HOST_POLL_INTERVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."] pub type INTERRUPT_ON_STALL_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."] -pub type INTERRUPT_ON_STALL_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type INTERRUPT_ON_STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDPOINT_TYPE` reader - "] pub type ENDPOINT_TYPE_R = crate::FieldReader; #[doc = " @@ -80,7 +47,7 @@ impl crate::FieldSpec for ENDPOINT_TYPE_A { impl ENDPOINT_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ENDPOINT_TYPE_A { + pub const fn variant(&self) -> ENDPOINT_TYPE_A { match self.bits { 0 => ENDPOINT_TYPE_A::CONTROL, 1 => ENDPOINT_TYPE_A::ISOCHRONOUS, @@ -89,68 +56,72 @@ impl ENDPOINT_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CONTROL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_control(&self) -> bool { *self == ENDPOINT_TYPE_A::CONTROL } - #[doc = "Checks if the value of the field is `ISOCHRONOUS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_isochronous(&self) -> bool { *self == ENDPOINT_TYPE_A::ISOCHRONOUS } - #[doc = "Checks if the value of the field is `BULK`"] + #[doc = "`10`"] #[inline(always)] pub fn is_bulk(&self) -> bool { *self == ENDPOINT_TYPE_A::BULK } - #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[doc = "`11`"] #[inline(always)] pub fn is_interrupt(&self) -> bool { *self == ENDPOINT_TYPE_A::INTERRUPT } } #[doc = "Field `ENDPOINT_TYPE` writer - "] -pub type ENDPOINT_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, EP_CONTROL_SPEC, 2, O, ENDPOINT_TYPE_A>; -impl<'a, const O: u8> ENDPOINT_TYPE_W<'a, O> { +pub type ENDPOINT_TYPE_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, ENDPOINT_TYPE_A>; +impl<'a, REG, const O: u8> ENDPOINT_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn control(self) -> &'a mut W { + pub fn control(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::CONTROL) } #[doc = "`1`"] #[inline(always)] - pub fn isochronous(self) -> &'a mut W { + pub fn isochronous(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::ISOCHRONOUS) } #[doc = "`10`"] #[inline(always)] - pub fn bulk(self) -> &'a mut W { + pub fn bulk(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::BULK) } #[doc = "`11`"] #[inline(always)] - pub fn interrupt(self) -> &'a mut W { + pub fn interrupt(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::INTERRUPT) } } #[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] pub type INTERRUPT_PER_DOUBLE_BUFF_R = crate::BitReader; #[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` writer - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] -pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."] pub type INTERRUPT_PER_BUFF_R = crate::BitReader; #[doc = "Field `INTERRUPT_PER_BUFF` writer - Trigger an interrupt each time a buffer is done."] -pub type INTERRUPT_PER_BUFF_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type INTERRUPT_PER_BUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."] pub type DOUBLE_BUFFERED_R = crate::BitReader; #[doc = "Field `DOUBLE_BUFFERED` writer - This endpoint is double buffered."] -pub type DOUBLE_BUFFERED_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type DOUBLE_BUFFERED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, EP_CONTROL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] #[inline(always)] @@ -202,80 +173,81 @@ impl W { #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] #[inline(always)] #[must_use] - pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W<0> { + pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W { BUFFER_ADDRESS_W::new(self) } #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."] #[inline(always)] #[must_use] - pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W<16> { + pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W { INTERRUPT_ON_NAK_W::new(self) } #[doc = "Bits 16:25 - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms."] #[inline(always)] #[must_use] - pub fn host_poll_interval(&mut self) -> HOST_POLL_INTERVAL_W<16> { + pub fn host_poll_interval(&mut self) -> HOST_POLL_INTERVAL_W { HOST_POLL_INTERVAL_W::new(self) } #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."] #[inline(always)] #[must_use] - pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W<17> { + pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W { INTERRUPT_ON_STALL_W::new(self) } #[doc = "Bits 26:27"] #[inline(always)] #[must_use] - pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W<26> { + pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W { ENDPOINT_TYPE_W::new(self) } #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] #[inline(always)] #[must_use] - pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W<28> { + pub fn interrupt_per_double_buff( + &mut self, + ) -> INTERRUPT_PER_DOUBLE_BUFF_W { INTERRUPT_PER_DOUBLE_BUFF_W::new(self) } #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."] #[inline(always)] #[must_use] - pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W<29> { + pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W { INTERRUPT_PER_BUFF_W::new(self) } #[doc = "Bit 30 - This endpoint is double buffered."] #[inline(always)] #[must_use] - pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W<30> { + pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W { DOUBLE_BUFFERED_W::new(self) } #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<31> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "- -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_control](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_CONTROL_SPEC; impl crate::RegisterSpec for EP_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_control::R](R) reader structure"] -impl crate::Readable for EP_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_control::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_control::R`](R) reader structure"] +impl crate::Readable for EP_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_control::W`](W) writer structure"] impl crate::Writable for EP_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_dpram/epx_control.rs b/src/usbctrl_dpram/epx_control.rs index 8e8432311..d8e079563 100644 --- a/src/usbctrl_dpram/epx_control.rs +++ b/src/usbctrl_dpram/epx_control.rs @@ -1,51 +1,19 @@ #[doc = "Register `EPX_CONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EPX_CONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] pub type BUFFER_ADDRESS_R = crate::FieldReader; #[doc = "Field `BUFFER_ADDRESS` writer - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] -pub type BUFFER_ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, EPX_CONTROL_SPEC, 16, O, u16>; +pub type BUFFER_ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."] pub type INTERRUPT_ON_NAK_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_NAK` writer - Trigger an interrupt if a NAK is sent. Intended for debug only."] -pub type INTERRUPT_ON_NAK_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type INTERRUPT_ON_NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."] pub type INTERRUPT_ON_STALL_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."] -pub type INTERRUPT_ON_STALL_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type INTERRUPT_ON_STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDPOINT_TYPE` reader - "] pub type ENDPOINT_TYPE_R = crate::FieldReader; #[doc = " @@ -75,7 +43,7 @@ impl crate::FieldSpec for ENDPOINT_TYPE_A { impl ENDPOINT_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ENDPOINT_TYPE_A { + pub const fn variant(&self) -> ENDPOINT_TYPE_A { match self.bits { 0 => ENDPOINT_TYPE_A::CONTROL, 1 => ENDPOINT_TYPE_A::ISOCHRONOUS, @@ -84,68 +52,72 @@ impl ENDPOINT_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CONTROL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_control(&self) -> bool { *self == ENDPOINT_TYPE_A::CONTROL } - #[doc = "Checks if the value of the field is `ISOCHRONOUS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_isochronous(&self) -> bool { *self == ENDPOINT_TYPE_A::ISOCHRONOUS } - #[doc = "Checks if the value of the field is `BULK`"] + #[doc = "`10`"] #[inline(always)] pub fn is_bulk(&self) -> bool { *self == ENDPOINT_TYPE_A::BULK } - #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[doc = "`11`"] #[inline(always)] pub fn is_interrupt(&self) -> bool { *self == ENDPOINT_TYPE_A::INTERRUPT } } #[doc = "Field `ENDPOINT_TYPE` writer - "] -pub type ENDPOINT_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, EPX_CONTROL_SPEC, 2, O, ENDPOINT_TYPE_A>; -impl<'a, const O: u8> ENDPOINT_TYPE_W<'a, O> { +pub type ENDPOINT_TYPE_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, ENDPOINT_TYPE_A>; +impl<'a, REG, const O: u8> ENDPOINT_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn control(self) -> &'a mut W { + pub fn control(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::CONTROL) } #[doc = "`1`"] #[inline(always)] - pub fn isochronous(self) -> &'a mut W { + pub fn isochronous(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::ISOCHRONOUS) } #[doc = "`10`"] #[inline(always)] - pub fn bulk(self) -> &'a mut W { + pub fn bulk(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::BULK) } #[doc = "`11`"] #[inline(always)] - pub fn interrupt(self) -> &'a mut W { + pub fn interrupt(self) -> &'a mut crate::W { self.variant(ENDPOINT_TYPE_A::INTERRUPT) } } #[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] pub type INTERRUPT_PER_DOUBLE_BUFF_R = crate::BitReader; #[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` writer - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] -pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."] pub type INTERRUPT_PER_BUFF_R = crate::BitReader; #[doc = "Field `INTERRUPT_PER_BUFF` writer - Trigger an interrupt each time a buffer is done."] -pub type INTERRUPT_PER_BUFF_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type INTERRUPT_PER_BUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."] pub type DOUBLE_BUFFERED_R = crate::BitReader; #[doc = "Field `DOUBLE_BUFFERED` writer - This endpoint is double buffered."] -pub type DOUBLE_BUFFERED_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type DOUBLE_BUFFERED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, EPX_CONTROL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] #[inline(always)] @@ -192,74 +164,75 @@ impl W { #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] #[inline(always)] #[must_use] - pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W<0> { + pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W { BUFFER_ADDRESS_W::new(self) } #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."] #[inline(always)] #[must_use] - pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W<16> { + pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W { INTERRUPT_ON_NAK_W::new(self) } #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."] #[inline(always)] #[must_use] - pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W<17> { + pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W { INTERRUPT_ON_STALL_W::new(self) } #[doc = "Bits 26:27"] #[inline(always)] #[must_use] - pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W<26> { + pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W { ENDPOINT_TYPE_W::new(self) } #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] #[inline(always)] #[must_use] - pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W<28> { + pub fn interrupt_per_double_buff( + &mut self, + ) -> INTERRUPT_PER_DOUBLE_BUFF_W { INTERRUPT_PER_DOUBLE_BUFF_W::new(self) } #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."] #[inline(always)] #[must_use] - pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W<29> { + pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W { INTERRUPT_PER_BUFF_W::new(self) } #[doc = "Bit 30 - This endpoint is double buffered."] #[inline(always)] #[must_use] - pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W<30> { + pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W { DOUBLE_BUFFERED_W::new(self) } #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<31> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "EPx Control (Host-mode only!) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [epx_control](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`epx_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`epx_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EPX_CONTROL_SPEC; impl crate::RegisterSpec for EPX_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [epx_control::R](R) reader structure"] -impl crate::Readable for EPX_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [epx_control::W](W) writer structure"] +#[doc = "`read()` method returns [`epx_control::R`](R) reader structure"] +impl crate::Readable for EPX_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`epx_control::W`](W) writer structure"] impl crate::Writable for EPX_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_dpram/setup_packet_high.rs b/src/usbctrl_dpram/setup_packet_high.rs index d989c482e..ddcd1556e 100644 --- a/src/usbctrl_dpram/setup_packet_high.rs +++ b/src/usbctrl_dpram/setup_packet_high.rs @@ -1,47 +1,15 @@ #[doc = "Register `SETUP_PACKET_HIGH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SETUP_PACKET_HIGH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WINDEX` reader - "] pub type WINDEX_R = crate::FieldReader; #[doc = "Field `WINDEX` writer - "] -pub type WINDEX_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_PACKET_HIGH_SPEC, 16, O, u16>; +pub type WINDEX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `WLENGTH` reader - "] pub type WLENGTH_R = crate::FieldReader; #[doc = "Field `WLENGTH` writer - "] -pub type WLENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_PACKET_HIGH_SPEC, 16, O, u16>; +pub type WLENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:15"] #[inline(always)] #[must_use] - pub fn windex(&mut self) -> WINDEX_W<0> { + pub fn windex(&mut self) -> WINDEX_W { WINDEX_W::new(self) } #[doc = "Bits 16:31"] #[inline(always)] #[must_use] - pub fn wlength(&mut self) -> WLENGTH_W<16> { + pub fn wlength(&mut self) -> WLENGTH_W { WLENGTH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bytes 4-7 of the setup packet from the host. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [setup_packet_high](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SETUP_PACKET_HIGH_SPEC; impl crate::RegisterSpec for SETUP_PACKET_HIGH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [setup_packet_high::R](R) reader structure"] -impl crate::Readable for SETUP_PACKET_HIGH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [setup_packet_high::W](W) writer structure"] +#[doc = "`read()` method returns [`setup_packet_high::R`](R) reader structure"] +impl crate::Readable for SETUP_PACKET_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_packet_high::W`](W) writer structure"] impl crate::Writable for SETUP_PACKET_HIGH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_dpram/setup_packet_low.rs b/src/usbctrl_dpram/setup_packet_low.rs index fa9af8be2..84820de9d 100644 --- a/src/usbctrl_dpram/setup_packet_low.rs +++ b/src/usbctrl_dpram/setup_packet_low.rs @@ -1,51 +1,19 @@ #[doc = "Register `SETUP_PACKET_LOW` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SETUP_PACKET_LOW` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BMREQUESTTYPE` reader - "] pub type BMREQUESTTYPE_R = crate::FieldReader; #[doc = "Field `BMREQUESTTYPE` writer - "] -pub type BMREQUESTTYPE_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_PACKET_LOW_SPEC, 8, O>; +pub type BMREQUESTTYPE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `BREQUEST` reader - "] pub type BREQUEST_R = crate::FieldReader; #[doc = "Field `BREQUEST` writer - "] -pub type BREQUEST_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_PACKET_LOW_SPEC, 8, O>; +pub type BREQUEST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `WVALUE` reader - "] pub type WVALUE_R = crate::FieldReader; #[doc = "Field `WVALUE` writer - "] -pub type WVALUE_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_PACKET_LOW_SPEC, 16, O, u16>; +pub type WVALUE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:7"] #[inline(always)] @@ -67,44 +35,43 @@ impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn bmrequesttype(&mut self) -> BMREQUESTTYPE_W<0> { + pub fn bmrequesttype(&mut self) -> BMREQUESTTYPE_W { BMREQUESTTYPE_W::new(self) } #[doc = "Bits 8:15"] #[inline(always)] #[must_use] - pub fn brequest(&mut self) -> BREQUEST_W<8> { + pub fn brequest(&mut self) -> BREQUEST_W { BREQUEST_W::new(self) } #[doc = "Bits 16:31"] #[inline(always)] #[must_use] - pub fn wvalue(&mut self) -> WVALUE_W<16> { + pub fn wvalue(&mut self) -> WVALUE_W { WVALUE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Bytes 0-3 of the SETUP packet from the host. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [setup_packet_low](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SETUP_PACKET_LOW_SPEC; impl crate::RegisterSpec for SETUP_PACKET_LOW_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [setup_packet_low::R](R) reader structure"] -impl crate::Readable for SETUP_PACKET_LOW_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [setup_packet_low::W](W) writer structure"] +#[doc = "`read()` method returns [`setup_packet_low::R`](R) reader structure"] +impl crate::Readable for SETUP_PACKET_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_packet_low::W`](W) writer structure"] impl crate::Writable for SETUP_PACKET_LOW_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs.rs b/src/usbctrl_regs.rs index dbee445dd..70ae05267 100644 --- a/src/usbctrl_regs.rs +++ b/src/usbctrl_regs.rs @@ -128,99 +128,219 @@ impl RegisterBlock { &self.host_addr_endp[14] } } -#[doc = "ADDR_ENDP (rw) register accessor: an alias for `Reg`"] +#[doc = "ADDR_ENDP (rw) register accessor: Device address and endpoint control + +You can [`read`](crate::generic::Reg::read) this register and get [`addr_endp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@addr_endp`] +module"] pub type ADDR_ENDP = crate::Reg; #[doc = "Device address and endpoint control"] pub mod addr_endp; -#[doc = "HOST_ADDR_ENDP (rw) register accessor: an alias for `Reg`"] +#[doc = "HOST_ADDR_ENDP (rw) register accessor: Interrupt endpoints. Only valid in HOST mode. + +You can [`read`](crate::generic::Reg::read) this register and get [`host_addr_endp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@host_addr_endp`] +module"] pub type HOST_ADDR_ENDP = crate::Reg; #[doc = "Interrupt endpoints. Only valid in HOST mode."] pub mod host_addr_endp; -#[doc = "MAIN_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "MAIN_CTRL (rw) register accessor: Main control register + +You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@main_ctrl`] +module"] pub type MAIN_CTRL = crate::Reg; #[doc = "Main control register"] pub mod main_ctrl; -#[doc = "SOF_WR (w) register accessor: an alias for `Reg`"] +#[doc = "SOF_WR (w) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_wr`] +module"] pub type SOF_WR = crate::Reg; #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] pub mod sof_wr; -#[doc = "SOF_RD (r) register accessor: an alias for `Reg`"] +#[doc = "SOF_RD (r) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + +You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_rd`] +module"] pub type SOF_RD = crate::Reg; #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."] pub mod sof_rd; -#[doc = "SIE_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "SIE_CTRL (rw) register accessor: SIE control register + +You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sie_ctrl`] +module"] pub type SIE_CTRL = crate::Reg; #[doc = "SIE control register"] pub mod sie_ctrl; -#[doc = "SIE_STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "SIE_STATUS (rw) register accessor: SIE status register + +You can [`read`](crate::generic::Reg::read) this register and get [`sie_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sie_status`] +module"] pub type SIE_STATUS = crate::Reg; #[doc = "SIE status register"] pub mod sie_status; -#[doc = "INT_EP_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "INT_EP_CTRL (rw) register accessor: interrupt endpoint control register + +You can [`read`](crate::generic::Reg::read) this register and get [`int_ep_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ep_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@int_ep_ctrl`] +module"] pub type INT_EP_CTRL = crate::Reg; #[doc = "interrupt endpoint control register"] pub mod int_ep_ctrl; -#[doc = "BUFF_STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "BUFF_STATUS (rw) register accessor: Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + +You can [`read`](crate::generic::Reg::read) this register and get [`buff_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@buff_status`] +module"] pub type BUFF_STATUS = crate::Reg; #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] pub mod buff_status; -#[doc = "BUFF_CPU_SHOULD_HANDLE (r) register accessor: an alias for `Reg`"] +#[doc = "BUFF_CPU_SHOULD_HANDLE (r) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + +You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@buff_cpu_should_handle`] +module"] pub type BUFF_CPU_SHOULD_HANDLE = crate::Reg; #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."] pub mod buff_cpu_should_handle; -#[doc = "EP_ABORT (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_ABORT (rw) register accessor: Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_abort`] +module"] pub type EP_ABORT = crate::Reg; #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."] pub mod ep_abort; -#[doc = "EP_ABORT_DONE (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_ABORT_DONE (rw) register accessor: Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_abort_done`] +module"] pub type EP_ABORT_DONE = crate::Reg; #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."] pub mod ep_abort_done; -#[doc = "EP_STALL_ARM (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_STALL_ARM (rw) register accessor: Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_stall_arm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_stall_arm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_stall_arm`] +module"] pub type EP_STALL_ARM = crate::Reg; #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."] pub mod ep_stall_arm; -#[doc = "NAK_POLL (rw) register accessor: an alias for `Reg`"] +#[doc = "NAK_POLL (rw) register accessor: Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + +You can [`read`](crate::generic::Reg::read) this register and get [`nak_poll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nak_poll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nak_poll`] +module"] pub type NAK_POLL = crate::Reg; #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."] pub mod nak_poll; -#[doc = "EP_STATUS_STALL_NAK (rw) register accessor: an alias for `Reg`"] +#[doc = "EP_STATUS_STALL_NAK (rw) register accessor: Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + +You can [`read`](crate::generic::Reg::read) this register and get [`ep_status_stall_nak::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_status_stall_nak`] +module"] pub type EP_STATUS_STALL_NAK = crate::Reg; #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."] pub mod ep_status_stall_nak; -#[doc = "USB_MUXING (rw) register accessor: an alias for `Reg`"] +#[doc = "USB_MUXING (rw) register accessor: Where to connect the USB controller. Should be to_phy by default. + +You can [`read`](crate::generic::Reg::read) this register and get [`usb_muxing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_muxing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_muxing`] +module"] pub type USB_MUXING = crate::Reg; #[doc = "Where to connect the USB controller. Should be to_phy by default."] pub mod usb_muxing; -#[doc = "USB_PWR (rw) register accessor: an alias for `Reg`"] +#[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + +You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_pwr`] +module"] pub type USB_PWR = crate::Reg; #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] pub mod usb_pwr; -#[doc = "USBPHY_DIRECT (rw) register accessor: an alias for `Reg`"] +#[doc = "USBPHY_DIRECT (rw) register accessor: This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_direct`] +module"] pub type USBPHY_DIRECT = crate::Reg; #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] pub mod usbphy_direct; -#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: an alias for `Reg`"] +#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: Override enable for each control in usbphy_direct + +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_direct_override`] +module"] pub type USBPHY_DIRECT_OVERRIDE = crate::Reg; #[doc = "Override enable for each control in usbphy_direct"] pub mod usbphy_direct_override; -#[doc = "USBPHY_TRIM (rw) register accessor: an alias for `Reg`"] +#[doc = "USBPHY_TRIM (rw) register accessor: Used to adjust trim values of USB phy pull down resistors. + +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_trim`] +module"] pub type USBPHY_TRIM = crate::Reg; #[doc = "Used to adjust trim values of USB phy pull down resistors."] pub mod usbphy_trim; -#[doc = "INTR (r) register accessor: an alias for `Reg`"] +#[doc = "INTR (r) register accessor: Raw Interrupts + +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] pub type INTR = crate::Reg; #[doc = "Raw Interrupts"] pub mod intr; -#[doc = "INTE (rw) register accessor: an alias for `Reg`"] +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] pub type INTE = crate::Reg; #[doc = "Interrupt Enable"] pub mod inte; -#[doc = "INTF (rw) register accessor: an alias for `Reg`"] +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: an alias for `Reg`"] +#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] pub type INTS = crate::Reg; #[doc = "Interrupt status after masking & forcing"] pub mod ints; diff --git a/src/usbctrl_regs/addr_endp.rs b/src/usbctrl_regs/addr_endp.rs index 1400f804c..b2d538d42 100644 --- a/src/usbctrl_regs/addr_endp.rs +++ b/src/usbctrl_regs/addr_endp.rs @@ -1,47 +1,15 @@ #[doc = "Register `ADDR_ENDP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ADDR_ENDP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDRESS` reader - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `ADDRESS` writer - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] -pub type ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, ADDR_ENDP_SPEC, 7, O>; +pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ENDPOINT` reader - Device endpoint to send data to. Only valid for HOST mode."] pub type ENDPOINT_R = crate::FieldReader; #[doc = "Field `ENDPOINT` writer - Device endpoint to send data to. Only valid for HOST mode."] -pub type ENDPOINT_W<'a, const O: u8> = crate::FieldWriter<'a, ADDR_ENDP_SPEC, 4, O>; +pub type ENDPOINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W<0> { + pub fn address(&mut self) -> ADDRESS_W { ADDRESS_W::new(self) } #[doc = "Bits 16:19 - Device endpoint to send data to. Only valid for HOST mode."] #[inline(always)] #[must_use] - pub fn endpoint(&mut self) -> ENDPOINT_W<16> { + pub fn endpoint(&mut self) -> ENDPOINT_W { ENDPOINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Device address and endpoint control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [addr_endp](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`addr_endp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_endp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ADDR_ENDP_SPEC; impl crate::RegisterSpec for ADDR_ENDP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [addr_endp::R](R) reader structure"] -impl crate::Readable for ADDR_ENDP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [addr_endp::W](W) writer structure"] +#[doc = "`read()` method returns [`addr_endp::R`](R) reader structure"] +impl crate::Readable for ADDR_ENDP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`addr_endp::W`](W) writer structure"] impl crate::Writable for ADDR_ENDP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/buff_cpu_should_handle.rs b/src/usbctrl_regs/buff_cpu_should_handle.rs index 5884b4d25..7adee91de 100644 --- a/src/usbctrl_regs/buff_cpu_should_handle.rs +++ b/src/usbctrl_regs/buff_cpu_should_handle.rs @@ -1,18 +1,5 @@ #[doc = "Register `BUFF_CPU_SHOULD_HANDLE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_OUT` reader - "] @@ -241,17 +228,13 @@ impl R { } #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [buff_cpu_should_handle](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUFF_CPU_SHOULD_HANDLE_SPEC; impl crate::RegisterSpec for BUFF_CPU_SHOULD_HANDLE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [buff_cpu_should_handle::R](R) reader structure"] -impl crate::Readable for BUFF_CPU_SHOULD_HANDLE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`buff_cpu_should_handle::R`](R) reader structure"] +impl crate::Readable for BUFF_CPU_SHOULD_HANDLE_SPEC {} #[doc = "`reset()` method sets BUFF_CPU_SHOULD_HANDLE to value 0"] impl crate::Resettable for BUFF_CPU_SHOULD_HANDLE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/usbctrl_regs/buff_status.rs b/src/usbctrl_regs/buff_status.rs index 591c00634..96f612b07 100644 --- a/src/usbctrl_regs/buff_status.rs +++ b/src/usbctrl_regs/buff_status.rs @@ -1,167 +1,135 @@ #[doc = "Register `BUFF_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BUFF_STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_IN` writer - "] -pub type EP0_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP0_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP0_OUT` reader - "] pub type EP0_OUT_R = crate::BitReader; #[doc = "Field `EP0_OUT` writer - "] -pub type EP0_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP0_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_IN` reader - "] pub type EP1_IN_R = crate::BitReader; #[doc = "Field `EP1_IN` writer - "] -pub type EP1_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP1_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_OUT` reader - "] pub type EP1_OUT_R = crate::BitReader; #[doc = "Field `EP1_OUT` writer - "] -pub type EP1_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP1_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_IN` reader - "] pub type EP2_IN_R = crate::BitReader; #[doc = "Field `EP2_IN` writer - "] -pub type EP2_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP2_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_OUT` reader - "] pub type EP2_OUT_R = crate::BitReader; #[doc = "Field `EP2_OUT` writer - "] -pub type EP2_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP2_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_IN` reader - "] pub type EP3_IN_R = crate::BitReader; #[doc = "Field `EP3_IN` writer - "] -pub type EP3_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP3_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_OUT` reader - "] pub type EP3_OUT_R = crate::BitReader; #[doc = "Field `EP3_OUT` writer - "] -pub type EP3_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP3_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_IN` reader - "] pub type EP4_IN_R = crate::BitReader; #[doc = "Field `EP4_IN` writer - "] -pub type EP4_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP4_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_OUT` reader - "] pub type EP4_OUT_R = crate::BitReader; #[doc = "Field `EP4_OUT` writer - "] -pub type EP4_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP4_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_IN` reader - "] pub type EP5_IN_R = crate::BitReader; #[doc = "Field `EP5_IN` writer - "] -pub type EP5_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP5_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_OUT` reader - "] pub type EP5_OUT_R = crate::BitReader; #[doc = "Field `EP5_OUT` writer - "] -pub type EP5_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP5_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_IN` reader - "] pub type EP6_IN_R = crate::BitReader; #[doc = "Field `EP6_IN` writer - "] -pub type EP6_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP6_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_OUT` reader - "] pub type EP6_OUT_R = crate::BitReader; #[doc = "Field `EP6_OUT` writer - "] -pub type EP6_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP6_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_IN` reader - "] pub type EP7_IN_R = crate::BitReader; #[doc = "Field `EP7_IN` writer - "] -pub type EP7_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP7_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_OUT` reader - "] pub type EP7_OUT_R = crate::BitReader; #[doc = "Field `EP7_OUT` writer - "] -pub type EP7_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP7_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_IN` reader - "] pub type EP8_IN_R = crate::BitReader; #[doc = "Field `EP8_IN` writer - "] -pub type EP8_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP8_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_OUT` reader - "] pub type EP8_OUT_R = crate::BitReader; #[doc = "Field `EP8_OUT` writer - "] -pub type EP8_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP8_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_IN` reader - "] pub type EP9_IN_R = crate::BitReader; #[doc = "Field `EP9_IN` writer - "] -pub type EP9_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP9_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_OUT` reader - "] pub type EP9_OUT_R = crate::BitReader; #[doc = "Field `EP9_OUT` writer - "] -pub type EP9_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP9_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_IN` reader - "] pub type EP10_IN_R = crate::BitReader; #[doc = "Field `EP10_IN` writer - "] -pub type EP10_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP10_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_OUT` reader - "] pub type EP10_OUT_R = crate::BitReader; #[doc = "Field `EP10_OUT` writer - "] -pub type EP10_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP10_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_IN` reader - "] pub type EP11_IN_R = crate::BitReader; #[doc = "Field `EP11_IN` writer - "] -pub type EP11_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP11_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_OUT` reader - "] pub type EP11_OUT_R = crate::BitReader; #[doc = "Field `EP11_OUT` writer - "] -pub type EP11_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP11_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_IN` reader - "] pub type EP12_IN_R = crate::BitReader; #[doc = "Field `EP12_IN` writer - "] -pub type EP12_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP12_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_OUT` reader - "] pub type EP12_OUT_R = crate::BitReader; #[doc = "Field `EP12_OUT` writer - "] -pub type EP12_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP12_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_IN` reader - "] pub type EP13_IN_R = crate::BitReader; #[doc = "Field `EP13_IN` writer - "] -pub type EP13_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP13_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_OUT` reader - "] pub type EP13_OUT_R = crate::BitReader; #[doc = "Field `EP13_OUT` writer - "] -pub type EP13_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP13_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_IN` reader - "] pub type EP14_IN_R = crate::BitReader; #[doc = "Field `EP14_IN` writer - "] -pub type EP14_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP14_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_OUT` reader - "] pub type EP14_OUT_R = crate::BitReader; #[doc = "Field `EP14_OUT` writer - "] -pub type EP14_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP14_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_IN` reader - "] pub type EP15_IN_R = crate::BitReader; #[doc = "Field `EP15_IN` writer - "] -pub type EP15_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP15_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_OUT` reader - "] pub type EP15_OUT_R = crate::BitReader; #[doc = "Field `EP15_OUT` writer - "] -pub type EP15_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, BUFF_STATUS_SPEC, O>; +pub type EP15_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ep0_in(&mut self) -> EP0_IN_W<0> { + pub fn ep0_in(&mut self) -> EP0_IN_W { EP0_IN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ep0_out(&mut self) -> EP0_OUT_W<1> { + pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ep1_in(&mut self) -> EP1_IN_W<2> { + pub fn ep1_in(&mut self) -> EP1_IN_W { EP1_IN_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ep1_out(&mut self) -> EP1_OUT_W<3> { + pub fn ep1_out(&mut self) -> EP1_OUT_W { EP1_OUT_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ep2_in(&mut self) -> EP2_IN_W<4> { + pub fn ep2_in(&mut self) -> EP2_IN_W { EP2_IN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ep2_out(&mut self) -> EP2_OUT_W<5> { + pub fn ep2_out(&mut self) -> EP2_OUT_W { EP2_OUT_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ep3_in(&mut self) -> EP3_IN_W<6> { + pub fn ep3_in(&mut self) -> EP3_IN_W { EP3_IN_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ep3_out(&mut self) -> EP3_OUT_W<7> { + pub fn ep3_out(&mut self) -> EP3_OUT_W { EP3_OUT_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn ep4_in(&mut self) -> EP4_IN_W<8> { + pub fn ep4_in(&mut self) -> EP4_IN_W { EP4_IN_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn ep4_out(&mut self) -> EP4_OUT_W<9> { + pub fn ep4_out(&mut self) -> EP4_OUT_W { EP4_OUT_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn ep5_in(&mut self) -> EP5_IN_W<10> { + pub fn ep5_in(&mut self) -> EP5_IN_W { EP5_IN_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn ep5_out(&mut self) -> EP5_OUT_W<11> { + pub fn ep5_out(&mut self) -> EP5_OUT_W { EP5_OUT_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn ep6_in(&mut self) -> EP6_IN_W<12> { + pub fn ep6_in(&mut self) -> EP6_IN_W { EP6_IN_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn ep6_out(&mut self) -> EP6_OUT_W<13> { + pub fn ep6_out(&mut self) -> EP6_OUT_W { EP6_OUT_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn ep7_in(&mut self) -> EP7_IN_W<14> { + pub fn ep7_in(&mut self) -> EP7_IN_W { EP7_IN_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn ep7_out(&mut self) -> EP7_OUT_W<15> { + pub fn ep7_out(&mut self) -> EP7_OUT_W { EP7_OUT_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn ep8_in(&mut self) -> EP8_IN_W<16> { + pub fn ep8_in(&mut self) -> EP8_IN_W { EP8_IN_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn ep8_out(&mut self) -> EP8_OUT_W<17> { + pub fn ep8_out(&mut self) -> EP8_OUT_W { EP8_OUT_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn ep9_in(&mut self) -> EP9_IN_W<18> { + pub fn ep9_in(&mut self) -> EP9_IN_W { EP9_IN_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn ep9_out(&mut self) -> EP9_OUT_W<19> { + pub fn ep9_out(&mut self) -> EP9_OUT_W { EP9_OUT_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn ep10_in(&mut self) -> EP10_IN_W<20> { + pub fn ep10_in(&mut self) -> EP10_IN_W { EP10_IN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn ep10_out(&mut self) -> EP10_OUT_W<21> { + pub fn ep10_out(&mut self) -> EP10_OUT_W { EP10_OUT_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn ep11_in(&mut self) -> EP11_IN_W<22> { + pub fn ep11_in(&mut self) -> EP11_IN_W { EP11_IN_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn ep11_out(&mut self) -> EP11_OUT_W<23> { + pub fn ep11_out(&mut self) -> EP11_OUT_W { EP11_OUT_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn ep12_in(&mut self) -> EP12_IN_W<24> { + pub fn ep12_in(&mut self) -> EP12_IN_W { EP12_IN_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn ep12_out(&mut self) -> EP12_OUT_W<25> { + pub fn ep12_out(&mut self) -> EP12_OUT_W { EP12_OUT_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn ep13_in(&mut self) -> EP13_IN_W<26> { + pub fn ep13_in(&mut self) -> EP13_IN_W { EP13_IN_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn ep13_out(&mut self) -> EP13_OUT_W<27> { + pub fn ep13_out(&mut self) -> EP13_OUT_W { EP13_OUT_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn ep14_in(&mut self) -> EP14_IN_W<28> { + pub fn ep14_in(&mut self) -> EP14_IN_W { EP14_IN_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn ep14_out(&mut self) -> EP14_OUT_W<29> { + pub fn ep14_out(&mut self) -> EP14_OUT_W { EP14_OUT_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn ep15_in(&mut self) -> EP15_IN_W<30> { + pub fn ep15_in(&mut self) -> EP15_IN_W { EP15_IN_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn ep15_out(&mut self) -> EP15_OUT_W<31> { + pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [buff_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`buff_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUFF_STATUS_SPEC; impl crate::RegisterSpec for BUFF_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [buff_status::R](R) reader structure"] -impl crate::Readable for BUFF_STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [buff_status::W](W) writer structure"] +#[doc = "`read()` method returns [`buff_status::R`](R) reader structure"] +impl crate::Readable for BUFF_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buff_status::W`](W) writer structure"] impl crate::Writable for BUFF_STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/src/usbctrl_regs/ep_abort.rs b/src/usbctrl_regs/ep_abort.rs index 3e09e66c9..750655651 100644 --- a/src/usbctrl_regs/ep_abort.rs +++ b/src/usbctrl_regs/ep_abort.rs @@ -1,167 +1,135 @@ #[doc = "Register `EP_ABORT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_ABORT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_IN` writer - "] -pub type EP0_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP0_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_OUT` reader - "] pub type EP0_OUT_R = crate::BitReader; #[doc = "Field `EP0_OUT` writer - "] -pub type EP0_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP0_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP1_IN` reader - "] pub type EP1_IN_R = crate::BitReader; #[doc = "Field `EP1_IN` writer - "] -pub type EP1_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP1_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP1_OUT` reader - "] pub type EP1_OUT_R = crate::BitReader; #[doc = "Field `EP1_OUT` writer - "] -pub type EP1_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP1_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP2_IN` reader - "] pub type EP2_IN_R = crate::BitReader; #[doc = "Field `EP2_IN` writer - "] -pub type EP2_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP2_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP2_OUT` reader - "] pub type EP2_OUT_R = crate::BitReader; #[doc = "Field `EP2_OUT` writer - "] -pub type EP2_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP2_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP3_IN` reader - "] pub type EP3_IN_R = crate::BitReader; #[doc = "Field `EP3_IN` writer - "] -pub type EP3_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP3_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP3_OUT` reader - "] pub type EP3_OUT_R = crate::BitReader; #[doc = "Field `EP3_OUT` writer - "] -pub type EP3_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP3_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP4_IN` reader - "] pub type EP4_IN_R = crate::BitReader; #[doc = "Field `EP4_IN` writer - "] -pub type EP4_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP4_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP4_OUT` reader - "] pub type EP4_OUT_R = crate::BitReader; #[doc = "Field `EP4_OUT` writer - "] -pub type EP4_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP4_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP5_IN` reader - "] pub type EP5_IN_R = crate::BitReader; #[doc = "Field `EP5_IN` writer - "] -pub type EP5_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP5_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP5_OUT` reader - "] pub type EP5_OUT_R = crate::BitReader; #[doc = "Field `EP5_OUT` writer - "] -pub type EP5_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP5_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP6_IN` reader - "] pub type EP6_IN_R = crate::BitReader; #[doc = "Field `EP6_IN` writer - "] -pub type EP6_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP6_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP6_OUT` reader - "] pub type EP6_OUT_R = crate::BitReader; #[doc = "Field `EP6_OUT` writer - "] -pub type EP6_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP6_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP7_IN` reader - "] pub type EP7_IN_R = crate::BitReader; #[doc = "Field `EP7_IN` writer - "] -pub type EP7_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP7_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP7_OUT` reader - "] pub type EP7_OUT_R = crate::BitReader; #[doc = "Field `EP7_OUT` writer - "] -pub type EP7_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP7_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP8_IN` reader - "] pub type EP8_IN_R = crate::BitReader; #[doc = "Field `EP8_IN` writer - "] -pub type EP8_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP8_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP8_OUT` reader - "] pub type EP8_OUT_R = crate::BitReader; #[doc = "Field `EP8_OUT` writer - "] -pub type EP8_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP8_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP9_IN` reader - "] pub type EP9_IN_R = crate::BitReader; #[doc = "Field `EP9_IN` writer - "] -pub type EP9_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP9_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP9_OUT` reader - "] pub type EP9_OUT_R = crate::BitReader; #[doc = "Field `EP9_OUT` writer - "] -pub type EP9_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP9_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP10_IN` reader - "] pub type EP10_IN_R = crate::BitReader; #[doc = "Field `EP10_IN` writer - "] -pub type EP10_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP10_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP10_OUT` reader - "] pub type EP10_OUT_R = crate::BitReader; #[doc = "Field `EP10_OUT` writer - "] -pub type EP10_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP10_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP11_IN` reader - "] pub type EP11_IN_R = crate::BitReader; #[doc = "Field `EP11_IN` writer - "] -pub type EP11_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP11_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP11_OUT` reader - "] pub type EP11_OUT_R = crate::BitReader; #[doc = "Field `EP11_OUT` writer - "] -pub type EP11_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP11_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP12_IN` reader - "] pub type EP12_IN_R = crate::BitReader; #[doc = "Field `EP12_IN` writer - "] -pub type EP12_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP12_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP12_OUT` reader - "] pub type EP12_OUT_R = crate::BitReader; #[doc = "Field `EP12_OUT` writer - "] -pub type EP12_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP12_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP13_IN` reader - "] pub type EP13_IN_R = crate::BitReader; #[doc = "Field `EP13_IN` writer - "] -pub type EP13_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP13_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP13_OUT` reader - "] pub type EP13_OUT_R = crate::BitReader; #[doc = "Field `EP13_OUT` writer - "] -pub type EP13_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP13_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP14_IN` reader - "] pub type EP14_IN_R = crate::BitReader; #[doc = "Field `EP14_IN` writer - "] -pub type EP14_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP14_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP14_OUT` reader - "] pub type EP14_OUT_R = crate::BitReader; #[doc = "Field `EP14_OUT` writer - "] -pub type EP14_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP14_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP15_IN` reader - "] pub type EP15_IN_R = crate::BitReader; #[doc = "Field `EP15_IN` writer - "] -pub type EP15_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP15_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP15_OUT` reader - "] pub type EP15_OUT_R = crate::BitReader; #[doc = "Field `EP15_OUT` writer - "] -pub type EP15_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_ABORT_SPEC, O>; +pub type EP15_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ep0_in(&mut self) -> EP0_IN_W<0> { + pub fn ep0_in(&mut self) -> EP0_IN_W { EP0_IN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ep0_out(&mut self) -> EP0_OUT_W<1> { + pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ep1_in(&mut self) -> EP1_IN_W<2> { + pub fn ep1_in(&mut self) -> EP1_IN_W { EP1_IN_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ep1_out(&mut self) -> EP1_OUT_W<3> { + pub fn ep1_out(&mut self) -> EP1_OUT_W { EP1_OUT_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ep2_in(&mut self) -> EP2_IN_W<4> { + pub fn ep2_in(&mut self) -> EP2_IN_W { EP2_IN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ep2_out(&mut self) -> EP2_OUT_W<5> { + pub fn ep2_out(&mut self) -> EP2_OUT_W { EP2_OUT_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ep3_in(&mut self) -> EP3_IN_W<6> { + pub fn ep3_in(&mut self) -> EP3_IN_W { EP3_IN_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ep3_out(&mut self) -> EP3_OUT_W<7> { + pub fn ep3_out(&mut self) -> EP3_OUT_W { EP3_OUT_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn ep4_in(&mut self) -> EP4_IN_W<8> { + pub fn ep4_in(&mut self) -> EP4_IN_W { EP4_IN_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn ep4_out(&mut self) -> EP4_OUT_W<9> { + pub fn ep4_out(&mut self) -> EP4_OUT_W { EP4_OUT_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn ep5_in(&mut self) -> EP5_IN_W<10> { + pub fn ep5_in(&mut self) -> EP5_IN_W { EP5_IN_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn ep5_out(&mut self) -> EP5_OUT_W<11> { + pub fn ep5_out(&mut self) -> EP5_OUT_W { EP5_OUT_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn ep6_in(&mut self) -> EP6_IN_W<12> { + pub fn ep6_in(&mut self) -> EP6_IN_W { EP6_IN_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn ep6_out(&mut self) -> EP6_OUT_W<13> { + pub fn ep6_out(&mut self) -> EP6_OUT_W { EP6_OUT_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn ep7_in(&mut self) -> EP7_IN_W<14> { + pub fn ep7_in(&mut self) -> EP7_IN_W { EP7_IN_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn ep7_out(&mut self) -> EP7_OUT_W<15> { + pub fn ep7_out(&mut self) -> EP7_OUT_W { EP7_OUT_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn ep8_in(&mut self) -> EP8_IN_W<16> { + pub fn ep8_in(&mut self) -> EP8_IN_W { EP8_IN_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn ep8_out(&mut self) -> EP8_OUT_W<17> { + pub fn ep8_out(&mut self) -> EP8_OUT_W { EP8_OUT_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn ep9_in(&mut self) -> EP9_IN_W<18> { + pub fn ep9_in(&mut self) -> EP9_IN_W { EP9_IN_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn ep9_out(&mut self) -> EP9_OUT_W<19> { + pub fn ep9_out(&mut self) -> EP9_OUT_W { EP9_OUT_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn ep10_in(&mut self) -> EP10_IN_W<20> { + pub fn ep10_in(&mut self) -> EP10_IN_W { EP10_IN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn ep10_out(&mut self) -> EP10_OUT_W<21> { + pub fn ep10_out(&mut self) -> EP10_OUT_W { EP10_OUT_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn ep11_in(&mut self) -> EP11_IN_W<22> { + pub fn ep11_in(&mut self) -> EP11_IN_W { EP11_IN_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn ep11_out(&mut self) -> EP11_OUT_W<23> { + pub fn ep11_out(&mut self) -> EP11_OUT_W { EP11_OUT_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn ep12_in(&mut self) -> EP12_IN_W<24> { + pub fn ep12_in(&mut self) -> EP12_IN_W { EP12_IN_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn ep12_out(&mut self) -> EP12_OUT_W<25> { + pub fn ep12_out(&mut self) -> EP12_OUT_W { EP12_OUT_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn ep13_in(&mut self) -> EP13_IN_W<26> { + pub fn ep13_in(&mut self) -> EP13_IN_W { EP13_IN_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn ep13_out(&mut self) -> EP13_OUT_W<27> { + pub fn ep13_out(&mut self) -> EP13_OUT_W { EP13_OUT_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn ep14_in(&mut self) -> EP14_IN_W<28> { + pub fn ep14_in(&mut self) -> EP14_IN_W { EP14_IN_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn ep14_out(&mut self) -> EP14_OUT_W<29> { + pub fn ep14_out(&mut self) -> EP14_OUT_W { EP14_OUT_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn ep15_in(&mut self) -> EP15_IN_W<30> { + pub fn ep15_in(&mut self) -> EP15_IN_W { EP15_IN_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn ep15_out(&mut self) -> EP15_OUT_W<31> { + pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_abort](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_ABORT_SPEC; impl crate::RegisterSpec for EP_ABORT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_abort::R](R) reader structure"] -impl crate::Readable for EP_ABORT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_abort::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_abort::R`](R) reader structure"] +impl crate::Readable for EP_ABORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_abort::W`](W) writer structure"] impl crate::Writable for EP_ABORT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/ep_abort_done.rs b/src/usbctrl_regs/ep_abort_done.rs index 0e8ff3f70..9b91bf39f 100644 --- a/src/usbctrl_regs/ep_abort_done.rs +++ b/src/usbctrl_regs/ep_abort_done.rs @@ -1,167 +1,135 @@ #[doc = "Register `EP_ABORT_DONE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_ABORT_DONE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_IN` writer - "] -pub type EP0_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP0_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP0_OUT` reader - "] pub type EP0_OUT_R = crate::BitReader; #[doc = "Field `EP0_OUT` writer - "] -pub type EP0_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP0_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_IN` reader - "] pub type EP1_IN_R = crate::BitReader; #[doc = "Field `EP1_IN` writer - "] -pub type EP1_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP1_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_OUT` reader - "] pub type EP1_OUT_R = crate::BitReader; #[doc = "Field `EP1_OUT` writer - "] -pub type EP1_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP1_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_IN` reader - "] pub type EP2_IN_R = crate::BitReader; #[doc = "Field `EP2_IN` writer - "] -pub type EP2_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP2_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_OUT` reader - "] pub type EP2_OUT_R = crate::BitReader; #[doc = "Field `EP2_OUT` writer - "] -pub type EP2_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP2_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_IN` reader - "] pub type EP3_IN_R = crate::BitReader; #[doc = "Field `EP3_IN` writer - "] -pub type EP3_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP3_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_OUT` reader - "] pub type EP3_OUT_R = crate::BitReader; #[doc = "Field `EP3_OUT` writer - "] -pub type EP3_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP3_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_IN` reader - "] pub type EP4_IN_R = crate::BitReader; #[doc = "Field `EP4_IN` writer - "] -pub type EP4_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP4_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_OUT` reader - "] pub type EP4_OUT_R = crate::BitReader; #[doc = "Field `EP4_OUT` writer - "] -pub type EP4_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP4_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_IN` reader - "] pub type EP5_IN_R = crate::BitReader; #[doc = "Field `EP5_IN` writer - "] -pub type EP5_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP5_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_OUT` reader - "] pub type EP5_OUT_R = crate::BitReader; #[doc = "Field `EP5_OUT` writer - "] -pub type EP5_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP5_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_IN` reader - "] pub type EP6_IN_R = crate::BitReader; #[doc = "Field `EP6_IN` writer - "] -pub type EP6_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP6_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_OUT` reader - "] pub type EP6_OUT_R = crate::BitReader; #[doc = "Field `EP6_OUT` writer - "] -pub type EP6_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP6_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_IN` reader - "] pub type EP7_IN_R = crate::BitReader; #[doc = "Field `EP7_IN` writer - "] -pub type EP7_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP7_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_OUT` reader - "] pub type EP7_OUT_R = crate::BitReader; #[doc = "Field `EP7_OUT` writer - "] -pub type EP7_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP7_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_IN` reader - "] pub type EP8_IN_R = crate::BitReader; #[doc = "Field `EP8_IN` writer - "] -pub type EP8_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP8_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_OUT` reader - "] pub type EP8_OUT_R = crate::BitReader; #[doc = "Field `EP8_OUT` writer - "] -pub type EP8_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP8_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_IN` reader - "] pub type EP9_IN_R = crate::BitReader; #[doc = "Field `EP9_IN` writer - "] -pub type EP9_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP9_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_OUT` reader - "] pub type EP9_OUT_R = crate::BitReader; #[doc = "Field `EP9_OUT` writer - "] -pub type EP9_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP9_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_IN` reader - "] pub type EP10_IN_R = crate::BitReader; #[doc = "Field `EP10_IN` writer - "] -pub type EP10_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP10_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_OUT` reader - "] pub type EP10_OUT_R = crate::BitReader; #[doc = "Field `EP10_OUT` writer - "] -pub type EP10_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP10_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_IN` reader - "] pub type EP11_IN_R = crate::BitReader; #[doc = "Field `EP11_IN` writer - "] -pub type EP11_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP11_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_OUT` reader - "] pub type EP11_OUT_R = crate::BitReader; #[doc = "Field `EP11_OUT` writer - "] -pub type EP11_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP11_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_IN` reader - "] pub type EP12_IN_R = crate::BitReader; #[doc = "Field `EP12_IN` writer - "] -pub type EP12_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP12_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_OUT` reader - "] pub type EP12_OUT_R = crate::BitReader; #[doc = "Field `EP12_OUT` writer - "] -pub type EP12_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP12_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_IN` reader - "] pub type EP13_IN_R = crate::BitReader; #[doc = "Field `EP13_IN` writer - "] -pub type EP13_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP13_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_OUT` reader - "] pub type EP13_OUT_R = crate::BitReader; #[doc = "Field `EP13_OUT` writer - "] -pub type EP13_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP13_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_IN` reader - "] pub type EP14_IN_R = crate::BitReader; #[doc = "Field `EP14_IN` writer - "] -pub type EP14_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP14_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_OUT` reader - "] pub type EP14_OUT_R = crate::BitReader; #[doc = "Field `EP14_OUT` writer - "] -pub type EP14_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP14_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_IN` reader - "] pub type EP15_IN_R = crate::BitReader; #[doc = "Field `EP15_IN` writer - "] -pub type EP15_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP15_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_OUT` reader - "] pub type EP15_OUT_R = crate::BitReader; #[doc = "Field `EP15_OUT` writer - "] -pub type EP15_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_ABORT_DONE_SPEC, O>; +pub type EP15_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ep0_in(&mut self) -> EP0_IN_W<0> { + pub fn ep0_in(&mut self) -> EP0_IN_W { EP0_IN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ep0_out(&mut self) -> EP0_OUT_W<1> { + pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ep1_in(&mut self) -> EP1_IN_W<2> { + pub fn ep1_in(&mut self) -> EP1_IN_W { EP1_IN_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ep1_out(&mut self) -> EP1_OUT_W<3> { + pub fn ep1_out(&mut self) -> EP1_OUT_W { EP1_OUT_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ep2_in(&mut self) -> EP2_IN_W<4> { + pub fn ep2_in(&mut self) -> EP2_IN_W { EP2_IN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ep2_out(&mut self) -> EP2_OUT_W<5> { + pub fn ep2_out(&mut self) -> EP2_OUT_W { EP2_OUT_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ep3_in(&mut self) -> EP3_IN_W<6> { + pub fn ep3_in(&mut self) -> EP3_IN_W { EP3_IN_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ep3_out(&mut self) -> EP3_OUT_W<7> { + pub fn ep3_out(&mut self) -> EP3_OUT_W { EP3_OUT_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn ep4_in(&mut self) -> EP4_IN_W<8> { + pub fn ep4_in(&mut self) -> EP4_IN_W { EP4_IN_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn ep4_out(&mut self) -> EP4_OUT_W<9> { + pub fn ep4_out(&mut self) -> EP4_OUT_W { EP4_OUT_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn ep5_in(&mut self) -> EP5_IN_W<10> { + pub fn ep5_in(&mut self) -> EP5_IN_W { EP5_IN_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn ep5_out(&mut self) -> EP5_OUT_W<11> { + pub fn ep5_out(&mut self) -> EP5_OUT_W { EP5_OUT_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn ep6_in(&mut self) -> EP6_IN_W<12> { + pub fn ep6_in(&mut self) -> EP6_IN_W { EP6_IN_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn ep6_out(&mut self) -> EP6_OUT_W<13> { + pub fn ep6_out(&mut self) -> EP6_OUT_W { EP6_OUT_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn ep7_in(&mut self) -> EP7_IN_W<14> { + pub fn ep7_in(&mut self) -> EP7_IN_W { EP7_IN_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn ep7_out(&mut self) -> EP7_OUT_W<15> { + pub fn ep7_out(&mut self) -> EP7_OUT_W { EP7_OUT_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn ep8_in(&mut self) -> EP8_IN_W<16> { + pub fn ep8_in(&mut self) -> EP8_IN_W { EP8_IN_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn ep8_out(&mut self) -> EP8_OUT_W<17> { + pub fn ep8_out(&mut self) -> EP8_OUT_W { EP8_OUT_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn ep9_in(&mut self) -> EP9_IN_W<18> { + pub fn ep9_in(&mut self) -> EP9_IN_W { EP9_IN_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn ep9_out(&mut self) -> EP9_OUT_W<19> { + pub fn ep9_out(&mut self) -> EP9_OUT_W { EP9_OUT_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn ep10_in(&mut self) -> EP10_IN_W<20> { + pub fn ep10_in(&mut self) -> EP10_IN_W { EP10_IN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn ep10_out(&mut self) -> EP10_OUT_W<21> { + pub fn ep10_out(&mut self) -> EP10_OUT_W { EP10_OUT_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn ep11_in(&mut self) -> EP11_IN_W<22> { + pub fn ep11_in(&mut self) -> EP11_IN_W { EP11_IN_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn ep11_out(&mut self) -> EP11_OUT_W<23> { + pub fn ep11_out(&mut self) -> EP11_OUT_W { EP11_OUT_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn ep12_in(&mut self) -> EP12_IN_W<24> { + pub fn ep12_in(&mut self) -> EP12_IN_W { EP12_IN_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn ep12_out(&mut self) -> EP12_OUT_W<25> { + pub fn ep12_out(&mut self) -> EP12_OUT_W { EP12_OUT_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn ep13_in(&mut self) -> EP13_IN_W<26> { + pub fn ep13_in(&mut self) -> EP13_IN_W { EP13_IN_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn ep13_out(&mut self) -> EP13_OUT_W<27> { + pub fn ep13_out(&mut self) -> EP13_OUT_W { EP13_OUT_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn ep14_in(&mut self) -> EP14_IN_W<28> { + pub fn ep14_in(&mut self) -> EP14_IN_W { EP14_IN_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn ep14_out(&mut self) -> EP14_OUT_W<29> { + pub fn ep14_out(&mut self) -> EP14_OUT_W { EP14_OUT_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn ep15_in(&mut self) -> EP15_IN_W<30> { + pub fn ep15_in(&mut self) -> EP15_IN_W { EP15_IN_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn ep15_out(&mut self) -> EP15_OUT_W<31> { + pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_abort_done](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort_done::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort_done::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_ABORT_DONE_SPEC; impl crate::RegisterSpec for EP_ABORT_DONE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_abort_done::R](R) reader structure"] -impl crate::Readable for EP_ABORT_DONE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_abort_done::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_abort_done::R`](R) reader structure"] +impl crate::Readable for EP_ABORT_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_abort_done::W`](W) writer structure"] impl crate::Writable for EP_ABORT_DONE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/src/usbctrl_regs/ep_stall_arm.rs b/src/usbctrl_regs/ep_stall_arm.rs index 53d0ee528..cb65afec1 100644 --- a/src/usbctrl_regs/ep_stall_arm.rs +++ b/src/usbctrl_regs/ep_stall_arm.rs @@ -1,47 +1,15 @@ #[doc = "Register `EP_STALL_ARM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_STALL_ARM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_IN` writer - "] -pub type EP0_IN_W<'a, const O: u8> = crate::BitWriter<'a, EP_STALL_ARM_SPEC, O>; +pub type EP0_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_OUT` reader - "] pub type EP0_OUT_R = crate::BitReader; #[doc = "Field `EP0_OUT` writer - "] -pub type EP0_OUT_W<'a, const O: u8> = crate::BitWriter<'a, EP_STALL_ARM_SPEC, O>; +pub type EP0_OUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ep0_in(&mut self) -> EP0_IN_W<0> { + pub fn ep0_in(&mut self) -> EP0_IN_W { EP0_IN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ep0_out(&mut self) -> EP0_OUT_W<1> { + pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_stall_arm](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_stall_arm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_stall_arm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_STALL_ARM_SPEC; impl crate::RegisterSpec for EP_STALL_ARM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_stall_arm::R](R) reader structure"] -impl crate::Readable for EP_STALL_ARM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_stall_arm::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_stall_arm::R`](R) reader structure"] +impl crate::Readable for EP_STALL_ARM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_stall_arm::W`](W) writer structure"] impl crate::Writable for EP_STALL_ARM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/ep_status_stall_nak.rs b/src/usbctrl_regs/ep_status_stall_nak.rs index 4dd454c7b..0d159235c 100644 --- a/src/usbctrl_regs/ep_status_stall_nak.rs +++ b/src/usbctrl_regs/ep_status_stall_nak.rs @@ -1,167 +1,135 @@ #[doc = "Register `EP_STATUS_STALL_NAK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EP_STATUS_STALL_NAK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_IN` writer - "] -pub type EP0_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP0_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP0_OUT` reader - "] pub type EP0_OUT_R = crate::BitReader; #[doc = "Field `EP0_OUT` writer - "] -pub type EP0_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP0_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_IN` reader - "] pub type EP1_IN_R = crate::BitReader; #[doc = "Field `EP1_IN` writer - "] -pub type EP1_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP1_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP1_OUT` reader - "] pub type EP1_OUT_R = crate::BitReader; #[doc = "Field `EP1_OUT` writer - "] -pub type EP1_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP1_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_IN` reader - "] pub type EP2_IN_R = crate::BitReader; #[doc = "Field `EP2_IN` writer - "] -pub type EP2_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP2_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP2_OUT` reader - "] pub type EP2_OUT_R = crate::BitReader; #[doc = "Field `EP2_OUT` writer - "] -pub type EP2_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP2_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_IN` reader - "] pub type EP3_IN_R = crate::BitReader; #[doc = "Field `EP3_IN` writer - "] -pub type EP3_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP3_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP3_OUT` reader - "] pub type EP3_OUT_R = crate::BitReader; #[doc = "Field `EP3_OUT` writer - "] -pub type EP3_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP3_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_IN` reader - "] pub type EP4_IN_R = crate::BitReader; #[doc = "Field `EP4_IN` writer - "] -pub type EP4_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP4_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP4_OUT` reader - "] pub type EP4_OUT_R = crate::BitReader; #[doc = "Field `EP4_OUT` writer - "] -pub type EP4_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP4_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_IN` reader - "] pub type EP5_IN_R = crate::BitReader; #[doc = "Field `EP5_IN` writer - "] -pub type EP5_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP5_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP5_OUT` reader - "] pub type EP5_OUT_R = crate::BitReader; #[doc = "Field `EP5_OUT` writer - "] -pub type EP5_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP5_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_IN` reader - "] pub type EP6_IN_R = crate::BitReader; #[doc = "Field `EP6_IN` writer - "] -pub type EP6_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP6_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP6_OUT` reader - "] pub type EP6_OUT_R = crate::BitReader; #[doc = "Field `EP6_OUT` writer - "] -pub type EP6_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP6_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_IN` reader - "] pub type EP7_IN_R = crate::BitReader; #[doc = "Field `EP7_IN` writer - "] -pub type EP7_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP7_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP7_OUT` reader - "] pub type EP7_OUT_R = crate::BitReader; #[doc = "Field `EP7_OUT` writer - "] -pub type EP7_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP7_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_IN` reader - "] pub type EP8_IN_R = crate::BitReader; #[doc = "Field `EP8_IN` writer - "] -pub type EP8_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP8_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP8_OUT` reader - "] pub type EP8_OUT_R = crate::BitReader; #[doc = "Field `EP8_OUT` writer - "] -pub type EP8_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP8_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_IN` reader - "] pub type EP9_IN_R = crate::BitReader; #[doc = "Field `EP9_IN` writer - "] -pub type EP9_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP9_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP9_OUT` reader - "] pub type EP9_OUT_R = crate::BitReader; #[doc = "Field `EP9_OUT` writer - "] -pub type EP9_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP9_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_IN` reader - "] pub type EP10_IN_R = crate::BitReader; #[doc = "Field `EP10_IN` writer - "] -pub type EP10_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP10_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP10_OUT` reader - "] pub type EP10_OUT_R = crate::BitReader; #[doc = "Field `EP10_OUT` writer - "] -pub type EP10_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP10_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_IN` reader - "] pub type EP11_IN_R = crate::BitReader; #[doc = "Field `EP11_IN` writer - "] -pub type EP11_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP11_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP11_OUT` reader - "] pub type EP11_OUT_R = crate::BitReader; #[doc = "Field `EP11_OUT` writer - "] -pub type EP11_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP11_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_IN` reader - "] pub type EP12_IN_R = crate::BitReader; #[doc = "Field `EP12_IN` writer - "] -pub type EP12_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP12_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP12_OUT` reader - "] pub type EP12_OUT_R = crate::BitReader; #[doc = "Field `EP12_OUT` writer - "] -pub type EP12_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP12_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_IN` reader - "] pub type EP13_IN_R = crate::BitReader; #[doc = "Field `EP13_IN` writer - "] -pub type EP13_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP13_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP13_OUT` reader - "] pub type EP13_OUT_R = crate::BitReader; #[doc = "Field `EP13_OUT` writer - "] -pub type EP13_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP13_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_IN` reader - "] pub type EP14_IN_R = crate::BitReader; #[doc = "Field `EP14_IN` writer - "] -pub type EP14_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP14_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP14_OUT` reader - "] pub type EP14_OUT_R = crate::BitReader; #[doc = "Field `EP14_OUT` writer - "] -pub type EP14_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP14_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_IN` reader - "] pub type EP15_IN_R = crate::BitReader; #[doc = "Field `EP15_IN` writer - "] -pub type EP15_IN_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP15_IN_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EP15_OUT` reader - "] pub type EP15_OUT_R = crate::BitReader; #[doc = "Field `EP15_OUT` writer - "] -pub type EP15_OUT_W<'a, const O: u8> = crate::BitWriter1C<'a, EP_STATUS_STALL_NAK_SPEC, O>; +pub type EP15_OUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -328,218 +296,217 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn ep0_in(&mut self) -> EP0_IN_W<0> { + pub fn ep0_in(&mut self) -> EP0_IN_W { EP0_IN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn ep0_out(&mut self) -> EP0_OUT_W<1> { + pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn ep1_in(&mut self) -> EP1_IN_W<2> { + pub fn ep1_in(&mut self) -> EP1_IN_W { EP1_IN_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn ep1_out(&mut self) -> EP1_OUT_W<3> { + pub fn ep1_out(&mut self) -> EP1_OUT_W { EP1_OUT_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn ep2_in(&mut self) -> EP2_IN_W<4> { + pub fn ep2_in(&mut self) -> EP2_IN_W { EP2_IN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn ep2_out(&mut self) -> EP2_OUT_W<5> { + pub fn ep2_out(&mut self) -> EP2_OUT_W { EP2_OUT_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn ep3_in(&mut self) -> EP3_IN_W<6> { + pub fn ep3_in(&mut self) -> EP3_IN_W { EP3_IN_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn ep3_out(&mut self) -> EP3_OUT_W<7> { + pub fn ep3_out(&mut self) -> EP3_OUT_W { EP3_OUT_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn ep4_in(&mut self) -> EP4_IN_W<8> { + pub fn ep4_in(&mut self) -> EP4_IN_W { EP4_IN_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn ep4_out(&mut self) -> EP4_OUT_W<9> { + pub fn ep4_out(&mut self) -> EP4_OUT_W { EP4_OUT_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn ep5_in(&mut self) -> EP5_IN_W<10> { + pub fn ep5_in(&mut self) -> EP5_IN_W { EP5_IN_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn ep5_out(&mut self) -> EP5_OUT_W<11> { + pub fn ep5_out(&mut self) -> EP5_OUT_W { EP5_OUT_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn ep6_in(&mut self) -> EP6_IN_W<12> { + pub fn ep6_in(&mut self) -> EP6_IN_W { EP6_IN_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn ep6_out(&mut self) -> EP6_OUT_W<13> { + pub fn ep6_out(&mut self) -> EP6_OUT_W { EP6_OUT_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn ep7_in(&mut self) -> EP7_IN_W<14> { + pub fn ep7_in(&mut self) -> EP7_IN_W { EP7_IN_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn ep7_out(&mut self) -> EP7_OUT_W<15> { + pub fn ep7_out(&mut self) -> EP7_OUT_W { EP7_OUT_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn ep8_in(&mut self) -> EP8_IN_W<16> { + pub fn ep8_in(&mut self) -> EP8_IN_W { EP8_IN_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn ep8_out(&mut self) -> EP8_OUT_W<17> { + pub fn ep8_out(&mut self) -> EP8_OUT_W { EP8_OUT_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn ep9_in(&mut self) -> EP9_IN_W<18> { + pub fn ep9_in(&mut self) -> EP9_IN_W { EP9_IN_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn ep9_out(&mut self) -> EP9_OUT_W<19> { + pub fn ep9_out(&mut self) -> EP9_OUT_W { EP9_OUT_W::new(self) } #[doc = "Bit 20"] #[inline(always)] #[must_use] - pub fn ep10_in(&mut self) -> EP10_IN_W<20> { + pub fn ep10_in(&mut self) -> EP10_IN_W { EP10_IN_W::new(self) } #[doc = "Bit 21"] #[inline(always)] #[must_use] - pub fn ep10_out(&mut self) -> EP10_OUT_W<21> { + pub fn ep10_out(&mut self) -> EP10_OUT_W { EP10_OUT_W::new(self) } #[doc = "Bit 22"] #[inline(always)] #[must_use] - pub fn ep11_in(&mut self) -> EP11_IN_W<22> { + pub fn ep11_in(&mut self) -> EP11_IN_W { EP11_IN_W::new(self) } #[doc = "Bit 23"] #[inline(always)] #[must_use] - pub fn ep11_out(&mut self) -> EP11_OUT_W<23> { + pub fn ep11_out(&mut self) -> EP11_OUT_W { EP11_OUT_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn ep12_in(&mut self) -> EP12_IN_W<24> { + pub fn ep12_in(&mut self) -> EP12_IN_W { EP12_IN_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn ep12_out(&mut self) -> EP12_OUT_W<25> { + pub fn ep12_out(&mut self) -> EP12_OUT_W { EP12_OUT_W::new(self) } #[doc = "Bit 26"] #[inline(always)] #[must_use] - pub fn ep13_in(&mut self) -> EP13_IN_W<26> { + pub fn ep13_in(&mut self) -> EP13_IN_W { EP13_IN_W::new(self) } #[doc = "Bit 27"] #[inline(always)] #[must_use] - pub fn ep13_out(&mut self) -> EP13_OUT_W<27> { + pub fn ep13_out(&mut self) -> EP13_OUT_W { EP13_OUT_W::new(self) } #[doc = "Bit 28"] #[inline(always)] #[must_use] - pub fn ep14_in(&mut self) -> EP14_IN_W<28> { + pub fn ep14_in(&mut self) -> EP14_IN_W { EP14_IN_W::new(self) } #[doc = "Bit 29"] #[inline(always)] #[must_use] - pub fn ep14_out(&mut self) -> EP14_OUT_W<29> { + pub fn ep14_out(&mut self) -> EP14_OUT_W { EP14_OUT_W::new(self) } #[doc = "Bit 30"] #[inline(always)] #[must_use] - pub fn ep15_in(&mut self) -> EP15_IN_W<30> { + pub fn ep15_in(&mut self) -> EP15_IN_W { EP15_IN_W::new(self) } #[doc = "Bit 31"] #[inline(always)] #[must_use] - pub fn ep15_out(&mut self) -> EP15_OUT_W<31> { + pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ep_status_stall_nak](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ep_status_stall_nak::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EP_STATUS_STALL_NAK_SPEC; impl crate::RegisterSpec for EP_STATUS_STALL_NAK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ep_status_stall_nak::R](R) reader structure"] -impl crate::Readable for EP_STATUS_STALL_NAK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ep_status_stall_nak::W](W) writer structure"] +#[doc = "`read()` method returns [`ep_status_stall_nak::R`](R) reader structure"] +impl crate::Readable for EP_STATUS_STALL_NAK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_status_stall_nak::W`](W) writer structure"] impl crate::Writable for EP_STATUS_STALL_NAK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/src/usbctrl_regs/host_addr_endp.rs b/src/usbctrl_regs/host_addr_endp.rs index 0cd24e1c3..3696e9caa 100644 --- a/src/usbctrl_regs/host_addr_endp.rs +++ b/src/usbctrl_regs/host_addr_endp.rs @@ -1,55 +1,23 @@ #[doc = "Register `HOST_ADDR_ENDP%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HOST_ADDR_ENDP%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDRESS` reader - Device address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `ADDRESS` writer - Device address"] -pub type ADDRESS_W<'a, const O: u8> = crate::FieldWriter<'a, HOST_ADDR_ENDP_SPEC, 7, O>; +pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub type ENDPOINT_R = crate::FieldReader; #[doc = "Field `ENDPOINT` writer - Endpoint number of the interrupt endpoint"] -pub type ENDPOINT_W<'a, const O: u8> = crate::FieldWriter<'a, HOST_ADDR_ENDP_SPEC, 4, O>; +pub type ENDPOINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub type INTEP_DIR_R = crate::BitReader; #[doc = "Field `INTEP_DIR` writer - Direction of the interrupt endpoint. In=0, Out=1"] -pub type INTEP_DIR_W<'a, const O: u8> = crate::BitWriter<'a, HOST_ADDR_ENDP_SPEC, O>; +pub type INTEP_DIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub type INTEP_PREAMBLE_R = crate::BitReader; #[doc = "Field `INTEP_PREAMBLE` writer - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] -pub type INTEP_PREAMBLE_W<'a, const O: u8> = crate::BitWriter<'a, HOST_ADDR_ENDP_SPEC, O>; +pub type INTEP_PREAMBLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Device address"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bits 0:6 - Device address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W<0> { + pub fn address(&mut self) -> ADDRESS_W { ADDRESS_W::new(self) } #[doc = "Bits 16:19 - Endpoint number of the interrupt endpoint"] #[inline(always)] #[must_use] - pub fn endpoint(&mut self) -> ENDPOINT_W<16> { + pub fn endpoint(&mut self) -> ENDPOINT_W { ENDPOINT_W::new(self) } #[doc = "Bit 25 - Direction of the interrupt endpoint. In=0, Out=1"] #[inline(always)] #[must_use] - pub fn intep_dir(&mut self) -> INTEP_DIR_W<25> { + pub fn intep_dir(&mut self) -> INTEP_DIR_W { INTEP_DIR_W::new(self) } #[doc = "Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] #[inline(always)] #[must_use] - pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<26> { + pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W { INTEP_PREAMBLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt endpoints. Only valid in HOST mode. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [host_addr_endp](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`host_addr_endp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_addr_endp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HOST_ADDR_ENDP_SPEC; impl crate::RegisterSpec for HOST_ADDR_ENDP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [host_addr_endp::R](R) reader structure"] -impl crate::Readable for HOST_ADDR_ENDP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [host_addr_endp::W](W) writer structure"] +#[doc = "`read()` method returns [`host_addr_endp::R`](R) reader structure"] +impl crate::Readable for HOST_ADDR_ENDP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_addr_endp::W`](W) writer structure"] impl crate::Writable for HOST_ADDR_ENDP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/int_ep_ctrl.rs b/src/usbctrl_regs/int_ep_ctrl.rs index 359c8d0c1..984b57422 100644 --- a/src/usbctrl_regs/int_ep_ctrl.rs +++ b/src/usbctrl_regs/int_ep_ctrl.rs @@ -1,43 +1,11 @@ #[doc = "Register `INT_EP_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INT_EP_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT_EP_ACTIVE` reader - Host: Enable interrupt endpoint 1 -> 15"] pub type INT_EP_ACTIVE_R = crate::FieldReader; #[doc = "Field `INT_EP_ACTIVE` writer - Host: Enable interrupt endpoint 1 -> 15"] -pub type INT_EP_ACTIVE_W<'a, const O: u8> = crate::FieldWriter<'a, INT_EP_CTRL_SPEC, 15, O, u16>; +pub type INT_EP_ACTIVE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 15, O, u16>; impl R { #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] #[inline(always)] #[must_use] - pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W<1> { + pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W { INT_EP_ACTIVE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "interrupt endpoint control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [int_ep_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`int_ep_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ep_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EP_CTRL_SPEC; impl crate::RegisterSpec for INT_EP_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [int_ep_ctrl::R](R) reader structure"] -impl crate::Readable for INT_EP_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [int_ep_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`int_ep_ctrl::R`](R) reader structure"] +impl crate::Readable for INT_EP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ep_ctrl::W`](W) writer structure"] impl crate::Writable for INT_EP_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/inte.rs b/src/usbctrl_regs/inte.rs index a72b6cf31..314bceb04 100644 --- a/src/usbctrl_regs/inte.rs +++ b/src/usbctrl_regs/inte.rs @@ -1,119 +1,87 @@ #[doc = "Register `INTE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] -pub type HOST_CONN_DIS_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type HOST_CONN_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub type HOST_RESUME_R = crate::BitReader; #[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] -pub type HOST_RESUME_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type HOST_RESUME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; #[doc = "Field `HOST_SOF` writer - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] -pub type HOST_SOF_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type HOST_SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub type TRANS_COMPLETE_R = crate::BitReader; #[doc = "Field `TRANS_COMPLETE` writer - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] -pub type TRANS_COMPLETE_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type TRANS_COMPLETE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub type BUFF_STATUS_R = crate::BitReader; #[doc = "Field `BUFF_STATUS` writer - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] -pub type BUFF_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type BUFF_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub type ERROR_DATA_SEQ_R = crate::BitReader; #[doc = "Field `ERROR_DATA_SEQ` writer - Source: SIE_STATUS.DATA_SEQ_ERROR"] -pub type ERROR_DATA_SEQ_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ERROR_DATA_SEQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub type ERROR_RX_TIMEOUT_R = crate::BitReader; #[doc = "Field `ERROR_RX_TIMEOUT` writer - Source: SIE_STATUS.RX_TIMEOUT"] -pub type ERROR_RX_TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ERROR_RX_TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub type ERROR_RX_OVERFLOW_R = crate::BitReader; #[doc = "Field `ERROR_RX_OVERFLOW` writer - Source: SIE_STATUS.RX_OVERFLOW"] -pub type ERROR_RX_OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ERROR_RX_OVERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub type ERROR_BIT_STUFF_R = crate::BitReader; #[doc = "Field `ERROR_BIT_STUFF` writer - Source: SIE_STATUS.BIT_STUFF_ERROR"] -pub type ERROR_BIT_STUFF_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ERROR_BIT_STUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub type ERROR_CRC_R = crate::BitReader; #[doc = "Field `ERROR_CRC` writer - Source: SIE_STATUS.CRC_ERROR"] -pub type ERROR_CRC_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ERROR_CRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub type VBUS_DETECT_R = crate::BitReader; #[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] -pub type VBUS_DETECT_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type VBUS_DETECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; #[doc = "Field `BUS_RESET` writer - Source: SIE_STATUS.BUS_RESET"] -pub type BUS_RESET_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type BUS_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub type DEV_CONN_DIS_R = crate::BitReader; #[doc = "Field `DEV_CONN_DIS` writer - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] -pub type DEV_CONN_DIS_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type DEV_CONN_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] -pub type DEV_SUSPEND_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type DEV_SUSPEND_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; #[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] -pub type DEV_RESUME_FROM_HOST_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type DEV_RESUME_FROM_HOST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; #[doc = "Field `SETUP_REQ` writer - Device. Source: SIE_STATUS.SETUP_REC"] -pub type SETUP_REQ_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type SETUP_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub type DEV_SOF_R = crate::BitReader; #[doc = "Field `DEV_SOF` writer - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] -pub type DEV_SOF_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type DEV_SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub type ABORT_DONE_R = crate::BitReader; #[doc = "Field `ABORT_DONE` writer - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] -pub type ABORT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type ABORT_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub type EP_STALL_NAK_R = crate::BitReader; #[doc = "Field `EP_STALL_NAK` writer - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] -pub type EP_STALL_NAK_W<'a, const O: u8> = crate::BitWriter<'a, INTE_SPEC, O>; +pub type EP_STALL_NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] #[inline(always)] @@ -220,146 +188,145 @@ impl W { #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] #[inline(always)] #[must_use] - pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<0> { + pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { HOST_CONN_DIS_W::new(self) } #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] #[inline(always)] #[must_use] - pub fn host_resume(&mut self) -> HOST_RESUME_W<1> { + pub fn host_resume(&mut self) -> HOST_RESUME_W { HOST_RESUME_W::new(self) } #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] #[inline(always)] #[must_use] - pub fn host_sof(&mut self) -> HOST_SOF_W<2> { + pub fn host_sof(&mut self) -> HOST_SOF_W { HOST_SOF_W::new(self) } #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] #[inline(always)] #[must_use] - pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<3> { + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { TRANS_COMPLETE_W::new(self) } #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] #[inline(always)] #[must_use] - pub fn buff_status(&mut self) -> BUFF_STATUS_W<4> { + pub fn buff_status(&mut self) -> BUFF_STATUS_W { BUFF_STATUS_W::new(self) } #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] #[inline(always)] #[must_use] - pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<5> { + pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W { ERROR_DATA_SEQ_W::new(self) } #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] #[inline(always)] #[must_use] - pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<6> { + pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W { ERROR_RX_TIMEOUT_W::new(self) } #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] #[inline(always)] #[must_use] - pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<7> { + pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W { ERROR_RX_OVERFLOW_W::new(self) } #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] #[inline(always)] #[must_use] - pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<8> { + pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W { ERROR_BIT_STUFF_W::new(self) } #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] #[inline(always)] #[must_use] - pub fn error_crc(&mut self) -> ERROR_CRC_W<9> { + pub fn error_crc(&mut self) -> ERROR_CRC_W { ERROR_CRC_W::new(self) } #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<10> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] #[inline(always)] #[must_use] - pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<11> { + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { VBUS_DETECT_W::new(self) } #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] #[inline(always)] #[must_use] - pub fn bus_reset(&mut self) -> BUS_RESET_W<12> { + pub fn bus_reset(&mut self) -> BUS_RESET_W { BUS_RESET_W::new(self) } #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] #[inline(always)] #[must_use] - pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<13> { + pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W { DEV_CONN_DIS_W::new(self) } #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] #[inline(always)] #[must_use] - pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<14> { + pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { DEV_SUSPEND_W::new(self) } #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] #[inline(always)] #[must_use] - pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<15> { + pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { DEV_RESUME_FROM_HOST_W::new(self) } #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] #[inline(always)] #[must_use] - pub fn setup_req(&mut self) -> SETUP_REQ_W<16> { + pub fn setup_req(&mut self) -> SETUP_REQ_W { SETUP_REQ_W::new(self) } #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] #[inline(always)] #[must_use] - pub fn dev_sof(&mut self) -> DEV_SOF_W<17> { + pub fn dev_sof(&mut self) -> DEV_SOF_W { DEV_SOF_W::new(self) } #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] #[inline(always)] #[must_use] - pub fn abort_done(&mut self) -> ABORT_DONE_W<18> { + pub fn abort_done(&mut self) -> ABORT_DONE_W { ABORT_DONE_W::new(self) } #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] #[inline(always)] #[must_use] - pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<19> { + pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { EP_STALL_NAK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [inte](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTE_SPEC; impl crate::RegisterSpec for INTE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [inte::R](R) reader structure"] -impl crate::Readable for INTE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [inte::W](W) writer structure"] +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/intf.rs b/src/usbctrl_regs/intf.rs index b32ebb828..ebc688c2a 100644 --- a/src/usbctrl_regs/intf.rs +++ b/src/usbctrl_regs/intf.rs @@ -1,119 +1,87 @@ #[doc = "Register `INTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] -pub type HOST_CONN_DIS_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type HOST_CONN_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub type HOST_RESUME_R = crate::BitReader; #[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] -pub type HOST_RESUME_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type HOST_RESUME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; #[doc = "Field `HOST_SOF` writer - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] -pub type HOST_SOF_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type HOST_SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub type TRANS_COMPLETE_R = crate::BitReader; #[doc = "Field `TRANS_COMPLETE` writer - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] -pub type TRANS_COMPLETE_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type TRANS_COMPLETE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub type BUFF_STATUS_R = crate::BitReader; #[doc = "Field `BUFF_STATUS` writer - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] -pub type BUFF_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type BUFF_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub type ERROR_DATA_SEQ_R = crate::BitReader; #[doc = "Field `ERROR_DATA_SEQ` writer - Source: SIE_STATUS.DATA_SEQ_ERROR"] -pub type ERROR_DATA_SEQ_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ERROR_DATA_SEQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub type ERROR_RX_TIMEOUT_R = crate::BitReader; #[doc = "Field `ERROR_RX_TIMEOUT` writer - Source: SIE_STATUS.RX_TIMEOUT"] -pub type ERROR_RX_TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ERROR_RX_TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub type ERROR_RX_OVERFLOW_R = crate::BitReader; #[doc = "Field `ERROR_RX_OVERFLOW` writer - Source: SIE_STATUS.RX_OVERFLOW"] -pub type ERROR_RX_OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ERROR_RX_OVERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub type ERROR_BIT_STUFF_R = crate::BitReader; #[doc = "Field `ERROR_BIT_STUFF` writer - Source: SIE_STATUS.BIT_STUFF_ERROR"] -pub type ERROR_BIT_STUFF_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ERROR_BIT_STUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub type ERROR_CRC_R = crate::BitReader; #[doc = "Field `ERROR_CRC` writer - Source: SIE_STATUS.CRC_ERROR"] -pub type ERROR_CRC_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ERROR_CRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub type VBUS_DETECT_R = crate::BitReader; #[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] -pub type VBUS_DETECT_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type VBUS_DETECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; #[doc = "Field `BUS_RESET` writer - Source: SIE_STATUS.BUS_RESET"] -pub type BUS_RESET_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type BUS_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub type DEV_CONN_DIS_R = crate::BitReader; #[doc = "Field `DEV_CONN_DIS` writer - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] -pub type DEV_CONN_DIS_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type DEV_CONN_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] -pub type DEV_SUSPEND_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type DEV_SUSPEND_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; #[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] -pub type DEV_RESUME_FROM_HOST_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type DEV_RESUME_FROM_HOST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; #[doc = "Field `SETUP_REQ` writer - Device. Source: SIE_STATUS.SETUP_REC"] -pub type SETUP_REQ_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type SETUP_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub type DEV_SOF_R = crate::BitReader; #[doc = "Field `DEV_SOF` writer - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] -pub type DEV_SOF_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type DEV_SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub type ABORT_DONE_R = crate::BitReader; #[doc = "Field `ABORT_DONE` writer - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] -pub type ABORT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type ABORT_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub type EP_STALL_NAK_R = crate::BitReader; #[doc = "Field `EP_STALL_NAK` writer - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] -pub type EP_STALL_NAK_W<'a, const O: u8> = crate::BitWriter<'a, INTF_SPEC, O>; +pub type EP_STALL_NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] #[inline(always)] @@ -220,146 +188,145 @@ impl W { #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] #[inline(always)] #[must_use] - pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<0> { + pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { HOST_CONN_DIS_W::new(self) } #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] #[inline(always)] #[must_use] - pub fn host_resume(&mut self) -> HOST_RESUME_W<1> { + pub fn host_resume(&mut self) -> HOST_RESUME_W { HOST_RESUME_W::new(self) } #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] #[inline(always)] #[must_use] - pub fn host_sof(&mut self) -> HOST_SOF_W<2> { + pub fn host_sof(&mut self) -> HOST_SOF_W { HOST_SOF_W::new(self) } #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] #[inline(always)] #[must_use] - pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<3> { + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { TRANS_COMPLETE_W::new(self) } #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] #[inline(always)] #[must_use] - pub fn buff_status(&mut self) -> BUFF_STATUS_W<4> { + pub fn buff_status(&mut self) -> BUFF_STATUS_W { BUFF_STATUS_W::new(self) } #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] #[inline(always)] #[must_use] - pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<5> { + pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W { ERROR_DATA_SEQ_W::new(self) } #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] #[inline(always)] #[must_use] - pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<6> { + pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W { ERROR_RX_TIMEOUT_W::new(self) } #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] #[inline(always)] #[must_use] - pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<7> { + pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W { ERROR_RX_OVERFLOW_W::new(self) } #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] #[inline(always)] #[must_use] - pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<8> { + pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W { ERROR_BIT_STUFF_W::new(self) } #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] #[inline(always)] #[must_use] - pub fn error_crc(&mut self) -> ERROR_CRC_W<9> { + pub fn error_crc(&mut self) -> ERROR_CRC_W { ERROR_CRC_W::new(self) } #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<10> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] #[inline(always)] #[must_use] - pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<11> { + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { VBUS_DETECT_W::new(self) } #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] #[inline(always)] #[must_use] - pub fn bus_reset(&mut self) -> BUS_RESET_W<12> { + pub fn bus_reset(&mut self) -> BUS_RESET_W { BUS_RESET_W::new(self) } #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] #[inline(always)] #[must_use] - pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<13> { + pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W { DEV_CONN_DIS_W::new(self) } #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] #[inline(always)] #[must_use] - pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<14> { + pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { DEV_SUSPEND_W::new(self) } #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] #[inline(always)] #[must_use] - pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<15> { + pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { DEV_RESUME_FROM_HOST_W::new(self) } #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] #[inline(always)] #[must_use] - pub fn setup_req(&mut self) -> SETUP_REQ_W<16> { + pub fn setup_req(&mut self) -> SETUP_REQ_W { SETUP_REQ_W::new(self) } #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] #[inline(always)] #[must_use] - pub fn dev_sof(&mut self) -> DEV_SOF_W<17> { + pub fn dev_sof(&mut self) -> DEV_SOF_W { DEV_SOF_W::new(self) } #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] #[inline(always)] #[must_use] - pub fn abort_done(&mut self) -> ABORT_DONE_W<18> { + pub fn abort_done(&mut self) -> ABORT_DONE_W { ABORT_DONE_W::new(self) } #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] #[inline(always)] #[must_use] - pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<19> { + pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { EP_STALL_NAK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt Force -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intf](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTF_SPEC; impl crate::RegisterSpec for INTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intf::R](R) reader structure"] -impl crate::Readable for INTF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [intf::W](W) writer structure"] +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/intr.rs b/src/usbctrl_regs/intr.rs index 2a068b698..16a5b4683 100644 --- a/src/usbctrl_regs/intr.rs +++ b/src/usbctrl_regs/intr.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] @@ -157,17 +144,13 @@ impl R { } #[doc = "Raw Interrupts -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [intr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [intr::R](R) reader structure"] -impl crate::Readable for INTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/usbctrl_regs/ints.rs b/src/usbctrl_regs/ints.rs index 1a4eb7a1b..581ee6279 100644 --- a/src/usbctrl_regs/ints.rs +++ b/src/usbctrl_regs/ints.rs @@ -1,18 +1,5 @@ #[doc = "Register `INTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] @@ -157,17 +144,13 @@ impl R { } #[doc = "Interrupt status after masking & forcing -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ints](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ints::R](R) reader structure"] -impl crate::Readable for INTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/usbctrl_regs/main_ctrl.rs b/src/usbctrl_regs/main_ctrl.rs index 05ac3ee3f..48aa5a034 100644 --- a/src/usbctrl_regs/main_ctrl.rs +++ b/src/usbctrl_regs/main_ctrl.rs @@ -1,51 +1,19 @@ #[doc = "Register `MAIN_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MAIN_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CONTROLLER_EN` reader - Enable controller"] pub type CONTROLLER_EN_R = crate::BitReader; #[doc = "Field `CONTROLLER_EN` writer - Enable controller"] -pub type CONTROLLER_EN_W<'a, const O: u8> = crate::BitWriter<'a, MAIN_CTRL_SPEC, O>; +pub type CONTROLLER_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOST_NDEVICE` reader - Device mode = 0, Host mode = 1"] pub type HOST_NDEVICE_R = crate::BitReader; #[doc = "Field `HOST_NDEVICE` writer - Device mode = 0, Host mode = 1"] -pub type HOST_NDEVICE_W<'a, const O: u8> = crate::BitWriter<'a, MAIN_CTRL_SPEC, O>; +pub type HOST_NDEVICE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIM_TIMING` reader - Reduced timings for simulation"] pub type SIM_TIMING_R = crate::BitReader; #[doc = "Field `SIM_TIMING` writer - Reduced timings for simulation"] -pub type SIM_TIMING_W<'a, const O: u8> = crate::BitWriter<'a, MAIN_CTRL_SPEC, O>; +pub type SIM_TIMING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable controller"] #[inline(always)] @@ -67,44 +35,43 @@ impl W { #[doc = "Bit 0 - Enable controller"] #[inline(always)] #[must_use] - pub fn controller_en(&mut self) -> CONTROLLER_EN_W<0> { + pub fn controller_en(&mut self) -> CONTROLLER_EN_W { CONTROLLER_EN_W::new(self) } #[doc = "Bit 1 - Device mode = 0, Host mode = 1"] #[inline(always)] #[must_use] - pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W<1> { + pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W { HOST_NDEVICE_W::new(self) } #[doc = "Bit 31 - Reduced timings for simulation"] #[inline(always)] #[must_use] - pub fn sim_timing(&mut self) -> SIM_TIMING_W<31> { + pub fn sim_timing(&mut self) -> SIM_TIMING_W { SIM_TIMING_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Main control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [main_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MAIN_CTRL_SPEC; impl crate::RegisterSpec for MAIN_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [main_ctrl::R](R) reader structure"] -impl crate::Readable for MAIN_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [main_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`main_ctrl::R`](R) reader structure"] +impl crate::Readable for MAIN_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`main_ctrl::W`](W) writer structure"] impl crate::Writable for MAIN_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/nak_poll.rs b/src/usbctrl_regs/nak_poll.rs index 2d4155553..ab8eaf172 100644 --- a/src/usbctrl_regs/nak_poll.rs +++ b/src/usbctrl_regs/nak_poll.rs @@ -1,47 +1,15 @@ #[doc = "Register `NAK_POLL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NAK_POLL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DELAY_LS` reader - NAK polling interval for a low speed device"] pub type DELAY_LS_R = crate::FieldReader; #[doc = "Field `DELAY_LS` writer - NAK polling interval for a low speed device"] -pub type DELAY_LS_W<'a, const O: u8> = crate::FieldWriter<'a, NAK_POLL_SPEC, 10, O, u16>; +pub type DELAY_LS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `DELAY_FS` reader - NAK polling interval for a full speed device"] pub type DELAY_FS_R = crate::FieldReader; #[doc = "Field `DELAY_FS` writer - NAK polling interval for a full speed device"] -pub type DELAY_FS_W<'a, const O: u8> = crate::FieldWriter<'a, NAK_POLL_SPEC, 10, O, u16>; +pub type DELAY_FS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; impl R { #[doc = "Bits 0:9 - NAK polling interval for a low speed device"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:9 - NAK polling interval for a low speed device"] #[inline(always)] #[must_use] - pub fn delay_ls(&mut self) -> DELAY_LS_W<0> { + pub fn delay_ls(&mut self) -> DELAY_LS_W { DELAY_LS_W::new(self) } #[doc = "Bits 16:25 - NAK polling interval for a full speed device"] #[inline(always)] #[must_use] - pub fn delay_fs(&mut self) -> DELAY_FS_W<16> { + pub fn delay_fs(&mut self) -> DELAY_FS_W { DELAY_FS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [nak_poll](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`nak_poll::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nak_poll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NAK_POLL_SPEC; impl crate::RegisterSpec for NAK_POLL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nak_poll::R](R) reader structure"] -impl crate::Readable for NAK_POLL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nak_poll::W](W) writer structure"] +#[doc = "`read()` method returns [`nak_poll::R`](R) reader structure"] +impl crate::Readable for NAK_POLL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nak_poll::W`](W) writer structure"] impl crate::Writable for NAK_POLL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/sie_ctrl.rs b/src/usbctrl_regs/sie_ctrl.rs index 2827ab44b..0844e339a 100644 --- a/src/usbctrl_regs/sie_ctrl.rs +++ b/src/usbctrl_regs/sie_ctrl.rs @@ -1,135 +1,103 @@ #[doc = "Register `SIE_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SIE_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `START_TRANS` reader - Host: Start transaction"] pub type START_TRANS_R = crate::BitReader; #[doc = "Field `START_TRANS` writer - Host: Start transaction"] -pub type START_TRANS_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type START_TRANS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SEND_SETUP` reader - Host: Send Setup packet"] pub type SEND_SETUP_R = crate::BitReader; #[doc = "Field `SEND_SETUP` writer - Host: Send Setup packet"] -pub type SEND_SETUP_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type SEND_SETUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SEND_DATA` reader - Host: Send transaction (OUT from host)"] pub type SEND_DATA_R = crate::BitReader; #[doc = "Field `SEND_DATA` writer - Host: Send transaction (OUT from host)"] -pub type SEND_DATA_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type SEND_DATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RECEIVE_DATA` reader - Host: Receive transaction (IN to host)"] pub type RECEIVE_DATA_R = crate::BitReader; #[doc = "Field `RECEIVE_DATA` writer - Host: Receive transaction (IN to host)"] -pub type RECEIVE_DATA_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type RECEIVE_DATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STOP_TRANS` reader - Host: Stop transaction"] pub type STOP_TRANS_R = crate::BitReader; #[doc = "Field `STOP_TRANS` writer - Host: Stop transaction"] -pub type STOP_TRANS_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type STOP_TRANS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PREAMBLE_EN` reader - Host: Preable enable for LS device on FS hub"] pub type PREAMBLE_EN_R = crate::BitReader; #[doc = "Field `PREAMBLE_EN` writer - Host: Preable enable for LS device on FS hub"] -pub type PREAMBLE_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type PREAMBLE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOF_SYNC` reader - Host: Delay packet(s) until after SOF"] pub type SOF_SYNC_R = crate::BitReader; #[doc = "Field `SOF_SYNC` writer - Host: Delay packet(s) until after SOF"] -pub type SOF_SYNC_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type SOF_SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOF_EN` reader - Host: Enable SOF generation (for full speed bus)"] pub type SOF_EN_R = crate::BitReader; #[doc = "Field `SOF_EN` writer - Host: Enable SOF generation (for full speed bus)"] -pub type SOF_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type SOF_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KEEP_ALIVE_EN` reader - Host: Enable keep alive packet (for low speed bus)"] pub type KEEP_ALIVE_EN_R = crate::BitReader; #[doc = "Field `KEEP_ALIVE_EN` writer - Host: Enable keep alive packet (for low speed bus)"] -pub type KEEP_ALIVE_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type KEEP_ALIVE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_EN` reader - Host: Enable VBUS"] pub type VBUS_EN_R = crate::BitReader; #[doc = "Field `VBUS_EN` writer - Host: Enable VBUS"] -pub type VBUS_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type VBUS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESUME` reader - Device: Remote wakeup. Device can initiate its own resume after suspend."] pub type RESUME_R = crate::BitReader; #[doc = "Field `RESUME` writer - Device: Remote wakeup. Device can initiate its own resume after suspend."] -pub type RESUME_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type RESUME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESET_BUS` reader - Host: Reset bus"] pub type RESET_BUS_R = crate::BitReader; #[doc = "Field `RESET_BUS` writer - Host: Reset bus"] -pub type RESET_BUS_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type RESET_BUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PULLDOWN_EN` reader - Host: Enable pull down resistors"] pub type PULLDOWN_EN_R = crate::BitReader; #[doc = "Field `PULLDOWN_EN` writer - Host: Enable pull down resistors"] -pub type PULLDOWN_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type PULLDOWN_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PULLUP_EN` reader - Device: Enable pull up resistor"] pub type PULLUP_EN_R = crate::BitReader; #[doc = "Field `PULLUP_EN` writer - Device: Enable pull up resistor"] -pub type PULLUP_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type PULLUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RPU_OPT` reader - Device: Pull-up strength (0=1K2, 1=2k3)"] pub type RPU_OPT_R = crate::BitReader; #[doc = "Field `RPU_OPT` writer - Device: Pull-up strength (0=1K2, 1=2k3)"] -pub type RPU_OPT_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type RPU_OPT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRANSCEIVER_PD` reader - Power down bus transceiver"] pub type TRANSCEIVER_PD_R = crate::BitReader; #[doc = "Field `TRANSCEIVER_PD` writer - Power down bus transceiver"] -pub type TRANSCEIVER_PD_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type TRANSCEIVER_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIRECT_DM` reader - Direct control of DM"] pub type DIRECT_DM_R = crate::BitReader; #[doc = "Field `DIRECT_DM` writer - Direct control of DM"] -pub type DIRECT_DM_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type DIRECT_DM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIRECT_DP` reader - Direct control of DP"] pub type DIRECT_DP_R = crate::BitReader; #[doc = "Field `DIRECT_DP` writer - Direct control of DP"] -pub type DIRECT_DP_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type DIRECT_DP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIRECT_EN` reader - Direct bus drive enable"] pub type DIRECT_EN_R = crate::BitReader; #[doc = "Field `DIRECT_EN` writer - Direct bus drive enable"] -pub type DIRECT_EN_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type DIRECT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_INT_NAK` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] pub type EP0_INT_NAK_R = crate::BitReader; #[doc = "Field `EP0_INT_NAK` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] -pub type EP0_INT_NAK_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type EP0_INT_NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_INT_2BUF` reader - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] pub type EP0_INT_2BUF_R = crate::BitReader; #[doc = "Field `EP0_INT_2BUF` writer - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] -pub type EP0_INT_2BUF_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type EP0_INT_2BUF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_INT_1BUF` reader - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] pub type EP0_INT_1BUF_R = crate::BitReader; #[doc = "Field `EP0_INT_1BUF` writer - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] -pub type EP0_INT_1BUF_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type EP0_INT_1BUF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_DOUBLE_BUF` reader - Device: EP0 single buffered = 0, double buffered = 1"] pub type EP0_DOUBLE_BUF_R = crate::BitReader; #[doc = "Field `EP0_DOUBLE_BUF` writer - Device: EP0 single buffered = 0, double buffered = 1"] -pub type EP0_DOUBLE_BUF_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type EP0_DOUBLE_BUF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP0_INT_STALL` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] pub type EP0_INT_STALL_R = crate::BitReader; #[doc = "Field `EP0_INT_STALL` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] -pub type EP0_INT_STALL_W<'a, const O: u8> = crate::BitWriter<'a, SIE_CTRL_SPEC, O>; +pub type EP0_INT_STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Host: Start transaction"] #[inline(always)] @@ -256,170 +224,169 @@ impl W { #[doc = "Bit 0 - Host: Start transaction"] #[inline(always)] #[must_use] - pub fn start_trans(&mut self) -> START_TRANS_W<0> { + pub fn start_trans(&mut self) -> START_TRANS_W { START_TRANS_W::new(self) } #[doc = "Bit 1 - Host: Send Setup packet"] #[inline(always)] #[must_use] - pub fn send_setup(&mut self) -> SEND_SETUP_W<1> { + pub fn send_setup(&mut self) -> SEND_SETUP_W { SEND_SETUP_W::new(self) } #[doc = "Bit 2 - Host: Send transaction (OUT from host)"] #[inline(always)] #[must_use] - pub fn send_data(&mut self) -> SEND_DATA_W<2> { + pub fn send_data(&mut self) -> SEND_DATA_W { SEND_DATA_W::new(self) } #[doc = "Bit 3 - Host: Receive transaction (IN to host)"] #[inline(always)] #[must_use] - pub fn receive_data(&mut self) -> RECEIVE_DATA_W<3> { + pub fn receive_data(&mut self) -> RECEIVE_DATA_W { RECEIVE_DATA_W::new(self) } #[doc = "Bit 4 - Host: Stop transaction"] #[inline(always)] #[must_use] - pub fn stop_trans(&mut self) -> STOP_TRANS_W<4> { + pub fn stop_trans(&mut self) -> STOP_TRANS_W { STOP_TRANS_W::new(self) } #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"] #[inline(always)] #[must_use] - pub fn preamble_en(&mut self) -> PREAMBLE_EN_W<6> { + pub fn preamble_en(&mut self) -> PREAMBLE_EN_W { PREAMBLE_EN_W::new(self) } #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"] #[inline(always)] #[must_use] - pub fn sof_sync(&mut self) -> SOF_SYNC_W<8> { + pub fn sof_sync(&mut self) -> SOF_SYNC_W { SOF_SYNC_W::new(self) } #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"] #[inline(always)] #[must_use] - pub fn sof_en(&mut self) -> SOF_EN_W<9> { + pub fn sof_en(&mut self) -> SOF_EN_W { SOF_EN_W::new(self) } #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"] #[inline(always)] #[must_use] - pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W<10> { + pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W { KEEP_ALIVE_EN_W::new(self) } #[doc = "Bit 11 - Host: Enable VBUS"] #[inline(always)] #[must_use] - pub fn vbus_en(&mut self) -> VBUS_EN_W<11> { + pub fn vbus_en(&mut self) -> VBUS_EN_W { VBUS_EN_W::new(self) } #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."] #[inline(always)] #[must_use] - pub fn resume(&mut self) -> RESUME_W<12> { + pub fn resume(&mut self) -> RESUME_W { RESUME_W::new(self) } #[doc = "Bit 13 - Host: Reset bus"] #[inline(always)] #[must_use] - pub fn reset_bus(&mut self) -> RESET_BUS_W<13> { + pub fn reset_bus(&mut self) -> RESET_BUS_W { RESET_BUS_W::new(self) } #[doc = "Bit 15 - Host: Enable pull down resistors"] #[inline(always)] #[must_use] - pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W<15> { + pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W { PULLDOWN_EN_W::new(self) } #[doc = "Bit 16 - Device: Enable pull up resistor"] #[inline(always)] #[must_use] - pub fn pullup_en(&mut self) -> PULLUP_EN_W<16> { + pub fn pullup_en(&mut self) -> PULLUP_EN_W { PULLUP_EN_W::new(self) } #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"] #[inline(always)] #[must_use] - pub fn rpu_opt(&mut self) -> RPU_OPT_W<17> { + pub fn rpu_opt(&mut self) -> RPU_OPT_W { RPU_OPT_W::new(self) } #[doc = "Bit 18 - Power down bus transceiver"] #[inline(always)] #[must_use] - pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W<18> { + pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W { TRANSCEIVER_PD_W::new(self) } #[doc = "Bit 24 - Direct control of DM"] #[inline(always)] #[must_use] - pub fn direct_dm(&mut self) -> DIRECT_DM_W<24> { + pub fn direct_dm(&mut self) -> DIRECT_DM_W { DIRECT_DM_W::new(self) } #[doc = "Bit 25 - Direct control of DP"] #[inline(always)] #[must_use] - pub fn direct_dp(&mut self) -> DIRECT_DP_W<25> { + pub fn direct_dp(&mut self) -> DIRECT_DP_W { DIRECT_DP_W::new(self) } #[doc = "Bit 26 - Direct bus drive enable"] #[inline(always)] #[must_use] - pub fn direct_en(&mut self) -> DIRECT_EN_W<26> { + pub fn direct_en(&mut self) -> DIRECT_EN_W { DIRECT_EN_W::new(self) } #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] #[inline(always)] #[must_use] - pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W<27> { + pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W { EP0_INT_NAK_W::new(self) } #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] #[inline(always)] #[must_use] - pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W<28> { + pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W { EP0_INT_2BUF_W::new(self) } #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] #[inline(always)] #[must_use] - pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W<29> { + pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W { EP0_INT_1BUF_W::new(self) } #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"] #[inline(always)] #[must_use] - pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W<30> { + pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W { EP0_DOUBLE_BUF_W::new(self) } #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] #[inline(always)] #[must_use] - pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W<31> { + pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W { EP0_INT_STALL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "SIE control register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sie_ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SIE_CTRL_SPEC; impl crate::RegisterSpec for SIE_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sie_ctrl::R](R) reader structure"] -impl crate::Readable for SIE_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sie_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`sie_ctrl::R`](R) reader structure"] +impl crate::Readable for SIE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sie_ctrl::W`](W) writer structure"] impl crate::Writable for SIE_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs index 3cb99302b..3627efe52 100644 --- a/src/usbctrl_regs/sie_status.rs +++ b/src/usbctrl_regs/sie_status.rs @@ -1,39 +1,7 @@ #[doc = "Register `SIE_STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SIE_STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VBUS_DETECTED` reader - Device: VBUS Detected"] pub type VBUS_DETECTED_R = crate::BitReader; #[doc = "Field `LINE_STATE` reader - USB bus line state"] @@ -65,7 +33,7 @@ impl crate::FieldSpec for LINE_STATE_A { impl LINE_STATE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> LINE_STATE_A { + pub const fn variant(&self) -> LINE_STATE_A { match self.bits { 0 => LINE_STATE_A::SE0, 1 => LINE_STATE_A::J, @@ -74,22 +42,22 @@ impl LINE_STATE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SE0`"] + #[doc = "SE0"] #[inline(always)] pub fn is_se0(&self) -> bool { *self == LINE_STATE_A::SE0 } - #[doc = "Checks if the value of the field is `J`"] + #[doc = "J"] #[inline(always)] pub fn is_j(&self) -> bool { *self == LINE_STATE_A::J } - #[doc = "Checks if the value of the field is `K`"] + #[doc = "K"] #[inline(always)] pub fn is_k(&self) -> bool { *self == LINE_STATE_A::K } - #[doc = "Checks if the value of the field is `SE1`"] + #[doc = "SE1"] #[inline(always)] pub fn is_se1(&self) -> bool { *self == LINE_STATE_A::SE1 @@ -98,25 +66,25 @@ impl LINE_STATE_R { #[doc = "Field `SUSPENDED` reader - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled."] pub type SUSPENDED_R = crate::BitReader; #[doc = "Field `SUSPENDED` writer - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled."] -pub type SUSPENDED_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type SUSPENDED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPEED` reader - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `SPEED` writer - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] -pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, SIE_STATUS_SPEC, 2, O>; +pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `VBUS_OVER_CURR` reader - VBUS over current detected"] pub type VBUS_OVER_CURR_R = crate::BitReader; #[doc = "Field `RESUME` reader - Host: Device has initiated a remote resume. Device: host has initiated a resume."] pub type RESUME_R = crate::BitReader; #[doc = "Field `RESUME` writer - Host: Device has initiated a remote resume. Device: host has initiated a resume."] -pub type RESUME_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type RESUME_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CONNECTED` reader - Device: connected"] pub type CONNECTED_R = crate::BitReader; #[doc = "Field `CONNECTED` writer - Device: connected"] -pub type CONNECTED_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type CONNECTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SETUP_REC` reader - Device: Setup packet received"] pub type SETUP_REC_R = crate::BitReader; #[doc = "Field `SETUP_REC` writer - Device: Setup packet received"] -pub type SETUP_REC_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type SETUP_REC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANS_COMPLETE` reader - Transaction complete. Raised by device if: @@ -136,39 +104,39 @@ pub type TRANS_COMPLETE_R = crate::BitReader; Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] -pub type TRANS_COMPLETE_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type TRANS_COMPLETE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `BUS_RESET` reader - Device: bus reset received"] pub type BUS_RESET_R = crate::BitReader; #[doc = "Field `BUS_RESET` writer - Device: bus reset received"] -pub type BUS_RESET_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type BUS_RESET_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CRC_ERROR` reader - CRC Error. Raised by the Serial RX engine."] pub type CRC_ERROR_R = crate::BitReader; #[doc = "Field `CRC_ERROR` writer - CRC Error. Raised by the Serial RX engine."] -pub type CRC_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type CRC_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `BIT_STUFF_ERROR` reader - Bit Stuff Error. Raised by the Serial RX engine."] pub type BIT_STUFF_ERROR_R = crate::BitReader; #[doc = "Field `BIT_STUFF_ERROR` writer - Bit Stuff Error. Raised by the Serial RX engine."] -pub type BIT_STUFF_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type BIT_STUFF_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RX_OVERFLOW` reader - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] pub type RX_OVERFLOW_R = crate::BitReader; #[doc = "Field `RX_OVERFLOW` writer - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] -pub type RX_OVERFLOW_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type RX_OVERFLOW_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RX_TIMEOUT` reader - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] pub type RX_TIMEOUT_R = crate::BitReader; #[doc = "Field `RX_TIMEOUT` writer - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] -pub type RX_TIMEOUT_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type RX_TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `NAK_REC` reader - Host: NAK received"] pub type NAK_REC_R = crate::BitReader; #[doc = "Field `NAK_REC` writer - Host: NAK received"] -pub type NAK_REC_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type NAK_REC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `STALL_REC` reader - Host: STALL received"] pub type STALL_REC_R = crate::BitReader; #[doc = "Field `STALL_REC` writer - Host: STALL received"] -pub type STALL_REC_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type STALL_REC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ACK_REC` reader - ACK received. Raised by both host and device."] pub type ACK_REC_R = crate::BitReader; #[doc = "Field `ACK_REC` writer - ACK received. Raised by both host and device."] -pub type ACK_REC_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type ACK_REC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DATA_SEQ_ERROR` reader - Data Sequence Error. The device can raise a sequence error in the following conditions: @@ -188,7 +156,7 @@ pub type DATA_SEQ_ERROR_R = crate::BitReader; The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] -pub type DATA_SEQ_ERROR_W<'a, const O: u8> = crate::BitWriter1C<'a, SIE_STATUS_SPEC, O>; +pub type DATA_SEQ_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Device: VBUS Detected"] #[inline(always)] @@ -301,31 +269,31 @@ impl W { #[doc = "Bit 4 - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled."] #[inline(always)] #[must_use] - pub fn suspended(&mut self) -> SUSPENDED_W<4> { + pub fn suspended(&mut self) -> SUSPENDED_W { SUSPENDED_W::new(self) } #[doc = "Bits 8:9 - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W<8> { + pub fn speed(&mut self) -> SPEED_W { SPEED_W::new(self) } #[doc = "Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume."] #[inline(always)] #[must_use] - pub fn resume(&mut self) -> RESUME_W<11> { + pub fn resume(&mut self) -> RESUME_W { RESUME_W::new(self) } #[doc = "Bit 16 - Device: connected"] #[inline(always)] #[must_use] - pub fn connected(&mut self) -> CONNECTED_W<16> { + pub fn connected(&mut self) -> CONNECTED_W { CONNECTED_W::new(self) } #[doc = "Bit 17 - Device: Setup packet received"] #[inline(always)] #[must_use] - pub fn setup_rec(&mut self) -> SETUP_REC_W<17> { + pub fn setup_rec(&mut self) -> SETUP_REC_W { SETUP_REC_W::new(self) } #[doc = "Bit 18 - Transaction complete. @@ -339,55 +307,55 @@ impl W { * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] #[inline(always)] #[must_use] - pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<18> { + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { TRANS_COMPLETE_W::new(self) } #[doc = "Bit 19 - Device: bus reset received"] #[inline(always)] #[must_use] - pub fn bus_reset(&mut self) -> BUS_RESET_W<19> { + pub fn bus_reset(&mut self) -> BUS_RESET_W { BUS_RESET_W::new(self) } #[doc = "Bit 24 - CRC Error. Raised by the Serial RX engine."] #[inline(always)] #[must_use] - pub fn crc_error(&mut self) -> CRC_ERROR_W<24> { + pub fn crc_error(&mut self) -> CRC_ERROR_W { CRC_ERROR_W::new(self) } #[doc = "Bit 25 - Bit Stuff Error. Raised by the Serial RX engine."] #[inline(always)] #[must_use] - pub fn bit_stuff_error(&mut self) -> BIT_STUFF_ERROR_W<25> { + pub fn bit_stuff_error(&mut self) -> BIT_STUFF_ERROR_W { BIT_STUFF_ERROR_W::new(self) } #[doc = "Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] #[inline(always)] #[must_use] - pub fn rx_overflow(&mut self) -> RX_OVERFLOW_W<26> { + pub fn rx_overflow(&mut self) -> RX_OVERFLOW_W { RX_OVERFLOW_W::new(self) } #[doc = "Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] #[inline(always)] #[must_use] - pub fn rx_timeout(&mut self) -> RX_TIMEOUT_W<27> { + pub fn rx_timeout(&mut self) -> RX_TIMEOUT_W { RX_TIMEOUT_W::new(self) } #[doc = "Bit 28 - Host: NAK received"] #[inline(always)] #[must_use] - pub fn nak_rec(&mut self) -> NAK_REC_W<28> { + pub fn nak_rec(&mut self) -> NAK_REC_W { NAK_REC_W::new(self) } #[doc = "Bit 29 - Host: STALL received"] #[inline(always)] #[must_use] - pub fn stall_rec(&mut self) -> STALL_REC_W<29> { + pub fn stall_rec(&mut self) -> STALL_REC_W { STALL_REC_W::new(self) } #[doc = "Bit 30 - ACK received. Raised by both host and device."] #[inline(always)] #[must_use] - pub fn ack_rec(&mut self) -> ACK_REC_W<30> { + pub fn ack_rec(&mut self) -> ACK_REC_W { ACK_REC_W::new(self) } #[doc = "Bit 31 - Data Sequence Error. @@ -401,32 +369,31 @@ impl W { * An IN packet from the device has the wrong data PID"] #[inline(always)] #[must_use] - pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W<31> { + pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W { DATA_SEQ_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "SIE status register -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sie_status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sie_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SIE_STATUS_SPEC; impl crate::RegisterSpec for SIE_STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sie_status::R](R) reader structure"] -impl crate::Readable for SIE_STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sie_status::W](W) writer structure"] +#[doc = "`read()` method returns [`sie_status::R`](R) reader structure"] +impl crate::Readable for SIE_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sie_status::W`](W) writer structure"] impl crate::Writable for SIE_STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff0f_0b10; } diff --git a/src/usbctrl_regs/sof_rd.rs b/src/usbctrl_regs/sof_rd.rs index 1bac8c138..875c87b0a 100644 --- a/src/usbctrl_regs/sof_rd.rs +++ b/src/usbctrl_regs/sof_rd.rs @@ -1,18 +1,5 @@ #[doc = "Register `SOF_RD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `COUNT` reader - "] pub type COUNT_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sof_rd](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOF_RD_SPEC; impl crate::RegisterSpec for SOF_RD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sof_rd::R](R) reader structure"] -impl crate::Readable for SOF_RD_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sof_rd::R`](R) reader structure"] +impl crate::Readable for SOF_RD_SPEC {} #[doc = "`reset()` method sets SOF_RD to value 0"] impl crate::Resettable for SOF_RD_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/usbctrl_regs/sof_wr.rs b/src/usbctrl_regs/sof_wr.rs index 2e897f66a..291e30b85 100644 --- a/src/usbctrl_regs/sof_wr.rs +++ b/src/usbctrl_regs/sof_wr.rs @@ -1,52 +1,34 @@ #[doc = "Register `SOF_WR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `COUNT` writer - "] -pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, SOF_WR_SPEC, 11, O, u16>; +pub type COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; impl W { #[doc = "Bits 0:10"] #[inline(always)] #[must_use] - pub fn count(&mut self) -> COUNT_W<0> { + pub fn count(&mut self) -> COUNT_W { COUNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sof_wr](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOF_WR_SPEC; impl crate::RegisterSpec for SOF_WR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [sof_wr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`sof_wr::W`](W) writer structure"] impl crate::Writable for SOF_WR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/usb_muxing.rs b/src/usbctrl_regs/usb_muxing.rs index 212c0941a..2d41cf72d 100644 --- a/src/usbctrl_regs/usb_muxing.rs +++ b/src/usbctrl_regs/usb_muxing.rs @@ -1,55 +1,23 @@ #[doc = "Register `USB_MUXING` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USB_MUXING` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TO_PHY` reader - "] pub type TO_PHY_R = crate::BitReader; #[doc = "Field `TO_PHY` writer - "] -pub type TO_PHY_W<'a, const O: u8> = crate::BitWriter<'a, USB_MUXING_SPEC, O>; +pub type TO_PHY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TO_EXTPHY` reader - "] pub type TO_EXTPHY_R = crate::BitReader; #[doc = "Field `TO_EXTPHY` writer - "] -pub type TO_EXTPHY_W<'a, const O: u8> = crate::BitWriter<'a, USB_MUXING_SPEC, O>; +pub type TO_EXTPHY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TO_DIGITAL_PAD` reader - "] pub type TO_DIGITAL_PAD_R = crate::BitReader; #[doc = "Field `TO_DIGITAL_PAD` writer - "] -pub type TO_DIGITAL_PAD_W<'a, const O: u8> = crate::BitWriter<'a, USB_MUXING_SPEC, O>; +pub type TO_DIGITAL_PAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFTCON` reader - "] pub type SOFTCON_R = crate::BitReader; #[doc = "Field `SOFTCON` writer - "] -pub type SOFTCON_W<'a, const O: u8> = crate::BitWriter<'a, USB_MUXING_SPEC, O>; +pub type SOFTCON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -76,50 +44,49 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn to_phy(&mut self) -> TO_PHY_W<0> { + pub fn to_phy(&mut self) -> TO_PHY_W { TO_PHY_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn to_extphy(&mut self) -> TO_EXTPHY_W<1> { + pub fn to_extphy(&mut self) -> TO_EXTPHY_W { TO_EXTPHY_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn to_digital_pad(&mut self) -> TO_DIGITAL_PAD_W<2> { + pub fn to_digital_pad(&mut self) -> TO_DIGITAL_PAD_W { TO_DIGITAL_PAD_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn softcon(&mut self) -> SOFTCON_W<3> { + pub fn softcon(&mut self) -> SOFTCON_W { SOFTCON_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Where to connect the USB controller. Should be to_phy by default. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [usb_muxing](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`usb_muxing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_muxing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USB_MUXING_SPEC; impl crate::RegisterSpec for USB_MUXING_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usb_muxing::R](R) reader structure"] -impl crate::Readable for USB_MUXING_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usb_muxing::W](W) writer structure"] +#[doc = "`read()` method returns [`usb_muxing::R`](R) reader structure"] +impl crate::Readable for USB_MUXING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_muxing::W`](W) writer structure"] impl crate::Writable for USB_MUXING_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/usb_pwr.rs b/src/usbctrl_regs/usb_pwr.rs index 7fcf7c6d9..034ecb2cc 100644 --- a/src/usbctrl_regs/usb_pwr.rs +++ b/src/usbctrl_regs/usb_pwr.rs @@ -1,63 +1,31 @@ #[doc = "Register `USB_PWR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USB_PWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VBUS_EN` reader - "] pub type VBUS_EN_R = crate::BitReader; #[doc = "Field `VBUS_EN` writer - "] -pub type VBUS_EN_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type VBUS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_EN_OVERRIDE_EN` reader - "] pub type VBUS_EN_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `VBUS_EN_OVERRIDE_EN` writer - "] -pub type VBUS_EN_OVERRIDE_EN_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type VBUS_EN_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_DETECT` reader - "] pub type VBUS_DETECT_R = crate::BitReader; #[doc = "Field `VBUS_DETECT` writer - "] -pub type VBUS_DETECT_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type VBUS_DETECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUS_DETECT_OVERRIDE_EN` reader - "] pub type VBUS_DETECT_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `VBUS_DETECT_OVERRIDE_EN` writer - "] -pub type VBUS_DETECT_OVERRIDE_EN_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type VBUS_DETECT_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERCURR_DETECT` reader - "] pub type OVERCURR_DETECT_R = crate::BitReader; #[doc = "Field `OVERCURR_DETECT` writer - "] -pub type OVERCURR_DETECT_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type OVERCURR_DETECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERCURR_DETECT_EN` reader - "] pub type OVERCURR_DETECT_EN_R = crate::BitReader; #[doc = "Field `OVERCURR_DETECT_EN` writer - "] -pub type OVERCURR_DETECT_EN_W<'a, const O: u8> = crate::BitWriter<'a, USB_PWR_SPEC, O>; +pub type OVERCURR_DETECT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -94,62 +62,61 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn vbus_en(&mut self) -> VBUS_EN_W<0> { + pub fn vbus_en(&mut self) -> VBUS_EN_W { VBUS_EN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn vbus_en_override_en(&mut self) -> VBUS_EN_OVERRIDE_EN_W<1> { + pub fn vbus_en_override_en(&mut self) -> VBUS_EN_OVERRIDE_EN_W { VBUS_EN_OVERRIDE_EN_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<2> { + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { VBUS_DETECT_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn vbus_detect_override_en(&mut self) -> VBUS_DETECT_OVERRIDE_EN_W<3> { + pub fn vbus_detect_override_en(&mut self) -> VBUS_DETECT_OVERRIDE_EN_W { VBUS_DETECT_OVERRIDE_EN_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn overcurr_detect(&mut self) -> OVERCURR_DETECT_W<4> { + pub fn overcurr_detect(&mut self) -> OVERCURR_DETECT_W { OVERCURR_DETECT_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W<5> { + pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W { OVERCURR_DETECT_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [usb_pwr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USB_PWR_SPEC; impl crate::RegisterSpec for USB_PWR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usb_pwr::R](R) reader structure"] -impl crate::Readable for USB_PWR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usb_pwr::W](W) writer structure"] +#[doc = "`read()` method returns [`usb_pwr::R`](R) reader structure"] +impl crate::Readable for USB_PWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_pwr::W`](W) writer structure"] impl crate::Writable for USB_PWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/usbphy_direct.rs b/src/usbctrl_regs/usbphy_direct.rs index afe6373bc..19aece832 100644 --- a/src/usbctrl_regs/usbphy_direct.rs +++ b/src/usbctrl_regs/usbphy_direct.rs @@ -1,107 +1,75 @@ #[doc = "Register `USBPHY_DIRECT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USBPHY_DIRECT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DP_PULLUP_HISEL` reader - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DP_PULLUP_HISEL_R = crate::BitReader; #[doc = "Field `DP_PULLUP_HISEL` writer - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] -pub type DP_PULLUP_HISEL_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DP_PULLUP_HISEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DP_PULLUP_EN` reader - DP pull up enable"] pub type DP_PULLUP_EN_R = crate::BitReader; #[doc = "Field `DP_PULLUP_EN` writer - DP pull up enable"] -pub type DP_PULLUP_EN_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DP_PULLUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DP_PULLDN_EN` reader - DP pull down enable"] pub type DP_PULLDN_EN_R = crate::BitReader; #[doc = "Field `DP_PULLDN_EN` writer - DP pull down enable"] -pub type DP_PULLDN_EN_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DP_PULLDN_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLUP_HISEL` reader - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DM_PULLUP_HISEL_R = crate::BitReader; #[doc = "Field `DM_PULLUP_HISEL` writer - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] -pub type DM_PULLUP_HISEL_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DM_PULLUP_HISEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLUP_EN` reader - DM pull up enable"] pub type DM_PULLUP_EN_R = crate::BitReader; #[doc = "Field `DM_PULLUP_EN` writer - DM pull up enable"] -pub type DM_PULLUP_EN_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DM_PULLUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLDN_EN` reader - DM pull down enable"] pub type DM_PULLDN_EN_R = crate::BitReader; #[doc = "Field `DM_PULLDN_EN` writer - DM pull down enable"] -pub type DM_PULLDN_EN_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type DM_PULLDN_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DP_OE` reader - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] pub type TX_DP_OE_R = crate::BitReader; #[doc = "Field `TX_DP_OE` writer - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] -pub type TX_DP_OE_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_DP_OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DM_OE` reader - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] pub type TX_DM_OE_R = crate::BitReader; #[doc = "Field `TX_DM_OE` writer - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] -pub type TX_DM_OE_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_DM_OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DP` reader - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] pub type TX_DP_R = crate::BitReader; #[doc = "Field `TX_DP` writer - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] -pub type TX_DP_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_DP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DM` reader - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] pub type TX_DM_R = crate::BitReader; #[doc = "Field `TX_DM` writer - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] -pub type TX_DM_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_DM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_PD` reader - RX power down override (if override enable is set). 1 = powered down."] pub type RX_PD_R = crate::BitReader; #[doc = "Field `RX_PD` writer - RX power down override (if override enable is set). 1 = powered down."] -pub type RX_PD_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type RX_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_PD` reader - TX power down override (if override enable is set). 1 = powered down."] pub type TX_PD_R = crate::BitReader; #[doc = "Field `TX_PD` writer - TX power down override (if override enable is set). 1 = powered down."] -pub type TX_PD_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FSSLEW` reader - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] pub type TX_FSSLEW_R = crate::BitReader; #[doc = "Field `TX_FSSLEW` writer - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] -pub type TX_FSSLEW_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_FSSLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DIFFMODE` reader - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] pub type TX_DIFFMODE_R = crate::BitReader; #[doc = "Field `TX_DIFFMODE` writer - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] -pub type TX_DIFFMODE_W<'a, const O: u8> = crate::BitWriter<'a, USBPHY_DIRECT_SPEC, O>; +pub type TX_DIFFMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_DD` reader - Differential RX"] pub type RX_DD_R = crate::BitReader; #[doc = "Field `RX_DP` reader - DPP pin state"] @@ -233,116 +201,115 @@ impl W { #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] #[must_use] - pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W<0> { + pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W { DP_PULLUP_HISEL_W::new(self) } #[doc = "Bit 1 - DP pull up enable"] #[inline(always)] #[must_use] - pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W<1> { + pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W { DP_PULLUP_EN_W::new(self) } #[doc = "Bit 2 - DP pull down enable"] #[inline(always)] #[must_use] - pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W<2> { + pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W { DP_PULLDN_EN_W::new(self) } #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] #[must_use] - pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W<4> { + pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W { DM_PULLUP_HISEL_W::new(self) } #[doc = "Bit 5 - DM pull up enable"] #[inline(always)] #[must_use] - pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W<5> { + pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W { DM_PULLUP_EN_W::new(self) } #[doc = "Bit 6 - DM pull down enable"] #[inline(always)] #[must_use] - pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W<6> { + pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W { DM_PULLDN_EN_W::new(self) } #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] #[inline(always)] #[must_use] - pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W<8> { + pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W { TX_DP_OE_W::new(self) } #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] #[inline(always)] #[must_use] - pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W<9> { + pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W { TX_DM_OE_W::new(self) } #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] #[inline(always)] #[must_use] - pub fn tx_dp(&mut self) -> TX_DP_W<10> { + pub fn tx_dp(&mut self) -> TX_DP_W { TX_DP_W::new(self) } #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] #[inline(always)] #[must_use] - pub fn tx_dm(&mut self) -> TX_DM_W<11> { + pub fn tx_dm(&mut self) -> TX_DM_W { TX_DM_W::new(self) } #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."] #[inline(always)] #[must_use] - pub fn rx_pd(&mut self) -> RX_PD_W<12> { + pub fn rx_pd(&mut self) -> RX_PD_W { RX_PD_W::new(self) } #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."] #[inline(always)] #[must_use] - pub fn tx_pd(&mut self) -> TX_PD_W<13> { + pub fn tx_pd(&mut self) -> TX_PD_W { TX_PD_W::new(self) } #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] #[inline(always)] #[must_use] - pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W<14> { + pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W { TX_FSSLEW_W::new(self) } #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] #[inline(always)] #[must_use] - pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W<15> { + pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W { TX_DIFFMODE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [usbphy_direct](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_DIRECT_SPEC; impl crate::RegisterSpec for USBPHY_DIRECT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usbphy_direct::R](R) reader structure"] -impl crate::Readable for USBPHY_DIRECT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usbphy_direct::W](W) writer structure"] +#[doc = "`read()` method returns [`usbphy_direct::R`](R) reader structure"] +impl crate::Readable for USBPHY_DIRECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_direct::W`](W) writer structure"] impl crate::Writable for USBPHY_DIRECT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/usbphy_direct_override.rs b/src/usbctrl_regs/usbphy_direct_override.rs index 9f50c4e93..9a308c9fd 100644 --- a/src/usbctrl_regs/usbphy_direct_override.rs +++ b/src/usbctrl_regs/usbphy_direct_override.rs @@ -1,109 +1,63 @@ #[doc = "Register `USBPHY_DIRECT_OVERRIDE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USBPHY_DIRECT_OVERRIDE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DP_PULLUP_HISEL_OVERRIDE_EN` reader - "] pub type DP_PULLUP_HISEL_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DP_PULLUP_HISEL_OVERRIDE_EN` writer - "] -pub type DP_PULLUP_HISEL_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DP_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` reader - "] pub type DM_PULLUP_HISEL_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` writer - "] -pub type DM_PULLUP_HISEL_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DM_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` reader - "] pub type DP_PULLUP_EN_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` writer - "] -pub type DP_PULLUP_EN_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DP_PULLUP_EN_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` reader - "] pub type DP_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` writer - "] -pub type DP_PULLDN_EN_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DP_PULLDN_EN_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` reader - "] pub type DM_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` writer - "] -pub type DM_PULLDN_EN_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DM_PULLDN_EN_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DP_OE_OVERRIDE_EN` reader - "] pub type TX_DP_OE_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_DP_OE_OVERRIDE_EN` writer - "] -pub type TX_DP_OE_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_DP_OE_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DM_OE_OVERRIDE_EN` reader - "] pub type TX_DM_OE_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_DM_OE_OVERRIDE_EN` writer - "] -pub type TX_DM_OE_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_DM_OE_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DP_OVERRIDE_EN` reader - "] pub type TX_DP_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_DP_OVERRIDE_EN` writer - "] -pub type TX_DP_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_DP_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DM_OVERRIDE_EN` reader - "] pub type TX_DM_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_DM_OVERRIDE_EN` writer - "] -pub type TX_DM_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_DM_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_PD_OVERRIDE_EN` reader - "] pub type RX_PD_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `RX_PD_OVERRIDE_EN` writer - "] -pub type RX_PD_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type RX_PD_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_PD_OVERRIDE_EN` reader - "] pub type TX_PD_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_PD_OVERRIDE_EN` writer - "] -pub type TX_PD_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_PD_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FSSLEW_OVERRIDE_EN` reader - "] pub type TX_FSSLEW_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_FSSLEW_OVERRIDE_EN` writer - "] -pub type TX_FSSLEW_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_FSSLEW_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DM_PULLUP_OVERRIDE_EN` reader - "] pub type DM_PULLUP_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DM_PULLUP_OVERRIDE_EN` writer - "] -pub type DM_PULLUP_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type DM_PULLUP_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DIFFMODE_OVERRIDE_EN` reader - "] pub type TX_DIFFMODE_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `TX_DIFFMODE_OVERRIDE_EN` writer - "] -pub type TX_DIFFMODE_OVERRIDE_EN_W<'a, const O: u8> = - crate::BitWriter<'a, USBPHY_DIRECT_OVERRIDE_SPEC, O>; +pub type TX_DIFFMODE_OVERRIDE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -180,110 +134,129 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn dp_pullup_hisel_override_en(&mut self) -> DP_PULLUP_HISEL_OVERRIDE_EN_W<0> { + pub fn dp_pullup_hisel_override_en( + &mut self, + ) -> DP_PULLUP_HISEL_OVERRIDE_EN_W { DP_PULLUP_HISEL_OVERRIDE_EN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn dm_pullup_hisel_override_en(&mut self) -> DM_PULLUP_HISEL_OVERRIDE_EN_W<1> { + pub fn dm_pullup_hisel_override_en( + &mut self, + ) -> DM_PULLUP_HISEL_OVERRIDE_EN_W { DM_PULLUP_HISEL_OVERRIDE_EN_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn dp_pullup_en_override_en(&mut self) -> DP_PULLUP_EN_OVERRIDE_EN_W<2> { + pub fn dp_pullup_en_override_en( + &mut self, + ) -> DP_PULLUP_EN_OVERRIDE_EN_W { DP_PULLUP_EN_OVERRIDE_EN_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn dp_pulldn_en_override_en(&mut self) -> DP_PULLDN_EN_OVERRIDE_EN_W<3> { + pub fn dp_pulldn_en_override_en( + &mut self, + ) -> DP_PULLDN_EN_OVERRIDE_EN_W { DP_PULLDN_EN_OVERRIDE_EN_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn dm_pulldn_en_override_en(&mut self) -> DM_PULLDN_EN_OVERRIDE_EN_W<4> { + pub fn dm_pulldn_en_override_en( + &mut self, + ) -> DM_PULLDN_EN_OVERRIDE_EN_W { DM_PULLDN_EN_OVERRIDE_EN_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn tx_dp_oe_override_en(&mut self) -> TX_DP_OE_OVERRIDE_EN_W<5> { + pub fn tx_dp_oe_override_en( + &mut self, + ) -> TX_DP_OE_OVERRIDE_EN_W { TX_DP_OE_OVERRIDE_EN_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn tx_dm_oe_override_en(&mut self) -> TX_DM_OE_OVERRIDE_EN_W<6> { + pub fn tx_dm_oe_override_en( + &mut self, + ) -> TX_DM_OE_OVERRIDE_EN_W { TX_DM_OE_OVERRIDE_EN_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W<7> { + pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W { TX_DP_OVERRIDE_EN_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W<8> { + pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W { TX_DM_OVERRIDE_EN_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn rx_pd_override_en(&mut self) -> RX_PD_OVERRIDE_EN_W<9> { + pub fn rx_pd_override_en(&mut self) -> RX_PD_OVERRIDE_EN_W { RX_PD_OVERRIDE_EN_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn tx_pd_override_en(&mut self) -> TX_PD_OVERRIDE_EN_W<10> { + pub fn tx_pd_override_en(&mut self) -> TX_PD_OVERRIDE_EN_W { TX_PD_OVERRIDE_EN_W::new(self) } #[doc = "Bit 11"] #[inline(always)] #[must_use] - pub fn tx_fsslew_override_en(&mut self) -> TX_FSSLEW_OVERRIDE_EN_W<11> { + pub fn tx_fsslew_override_en( + &mut self, + ) -> TX_FSSLEW_OVERRIDE_EN_W { TX_FSSLEW_OVERRIDE_EN_W::new(self) } #[doc = "Bit 12"] #[inline(always)] #[must_use] - pub fn dm_pullup_override_en(&mut self) -> DM_PULLUP_OVERRIDE_EN_W<12> { + pub fn dm_pullup_override_en( + &mut self, + ) -> DM_PULLUP_OVERRIDE_EN_W { DM_PULLUP_OVERRIDE_EN_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn tx_diffmode_override_en(&mut self) -> TX_DIFFMODE_OVERRIDE_EN_W<15> { + pub fn tx_diffmode_override_en( + &mut self, + ) -> TX_DIFFMODE_OVERRIDE_EN_W { TX_DIFFMODE_OVERRIDE_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Override enable for each control in usbphy_direct -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [usbphy_direct_override](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_DIRECT_OVERRIDE_SPEC; impl crate::RegisterSpec for USBPHY_DIRECT_OVERRIDE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usbphy_direct_override::R](R) reader structure"] -impl crate::Readable for USBPHY_DIRECT_OVERRIDE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usbphy_direct_override::W](W) writer structure"] +#[doc = "`read()` method returns [`usbphy_direct_override::R`](R) reader structure"] +impl crate::Readable for USBPHY_DIRECT_OVERRIDE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_direct_override::W`](W) writer structure"] impl crate::Writable for USBPHY_DIRECT_OVERRIDE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/usbctrl_regs/usbphy_trim.rs b/src/usbctrl_regs/usbphy_trim.rs index 95b7bc5c4..cd1e7d4d3 100644 --- a/src/usbctrl_regs/usbphy_trim.rs +++ b/src/usbctrl_regs/usbphy_trim.rs @@ -1,39 +1,7 @@ #[doc = "Register `USBPHY_TRIM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USBPHY_TRIM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DP_PULLDN_TRIM` reader - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] @@ -41,7 +9,7 @@ pub type DP_PULLDN_TRIM_R = crate::FieldReader; #[doc = "Field `DP_PULLDN_TRIM` writer - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] -pub type DP_PULLDN_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, USBPHY_TRIM_SPEC, 5, O>; +pub type DP_PULLDN_TRIM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DM_PULLDN_TRIM` reader - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] @@ -49,7 +17,7 @@ pub type DM_PULLDN_TRIM_R = crate::FieldReader; #[doc = "Field `DM_PULLDN_TRIM` writer - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] -pub type DM_PULLDN_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, USBPHY_TRIM_SPEC, 5, O>; +pub type DM_PULLDN_TRIM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; impl R { #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control @@ -72,7 +40,7 @@ impl W { Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] #[must_use] - pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W<0> { + pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W { DP_PULLDN_TRIM_W::new(self) } #[doc = "Bits 8:12 - Value to drive to USB PHY @@ -80,32 +48,31 @@ impl W { Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] #[must_use] - pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W<8> { + pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W { DM_PULLDN_TRIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Used to adjust trim values of USB phy pull down resistors. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [usbphy_trim](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_TRIM_SPEC; impl crate::RegisterSpec for USBPHY_TRIM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usbphy_trim::R](R) reader structure"] -impl crate::Readable for USBPHY_TRIM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usbphy_trim::W](W) writer structure"] +#[doc = "`read()` method returns [`usbphy_trim::R`](R) reader structure"] +impl crate::Readable for USBPHY_TRIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_trim::W`](W) writer structure"] impl crate::Writable for USBPHY_TRIM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/vreg_and_chip_reset.rs b/src/vreg_and_chip_reset.rs index 46d2d0c21..b707543a1 100644 --- a/src/vreg_and_chip_reset.rs +++ b/src/vreg_and_chip_reset.rs @@ -8,15 +8,30 @@ pub struct RegisterBlock { #[doc = "0x08 - Chip reset control and status"] pub chip_reset: CHIP_RESET, } -#[doc = "VREG (rw) register accessor: an alias for `Reg`"] +#[doc = "VREG (rw) register accessor: Voltage regulator control and status + +You can [`read`](crate::generic::Reg::read) this register and get [`vreg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vreg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg`] +module"] pub type VREG = crate::Reg; #[doc = "Voltage regulator control and status"] pub mod vreg; -#[doc = "BOD (rw) register accessor: an alias for `Reg`"] +#[doc = "BOD (rw) register accessor: brown-out detection control + +You can [`read`](crate::generic::Reg::read) this register and get [`bod::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bod`] +module"] pub type BOD = crate::Reg; #[doc = "brown-out detection control"] pub mod bod; -#[doc = "CHIP_RESET (rw) register accessor: an alias for `Reg`"] +#[doc = "CHIP_RESET (rw) register accessor: Chip reset control and status + +You can [`read`](crate::generic::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chip_reset`] +module"] pub type CHIP_RESET = crate::Reg; #[doc = "Chip reset control and status"] pub mod chip_reset; diff --git a/src/vreg_and_chip_reset/bod.rs b/src/vreg_and_chip_reset/bod.rs index 1dfd93bfe..7bf85de1f 100644 --- a/src/vreg_and_chip_reset/bod.rs +++ b/src/vreg_and_chip_reset/bod.rs @@ -1,45 +1,13 @@ #[doc = "Register `BOD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BOD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - enable 0=not enabled, 1=enabled"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - enable 0=not enabled, 1=enabled"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, BOD_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VSEL` reader - threshold select 0000 - 0.473V 0001 - 0.516V @@ -75,7 +43,7 @@ pub type VSEL_R = crate::FieldReader; 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] -pub type VSEL_W<'a, const O: u8> = crate::FieldWriter<'a, BOD_SPEC, 4, O>; +pub type VSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] @@ -110,7 +78,7 @@ impl W { 0=not enabled, 1=enabled"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bits 4:7 - threshold select @@ -132,32 +100,31 @@ impl W { 1111 - 1.118V"] #[inline(always)] #[must_use] - pub fn vsel(&mut self) -> VSEL_W<4> { + pub fn vsel(&mut self) -> VSEL_W { VSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "brown-out detection control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [bod](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`bod::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BOD_SPEC; impl crate::RegisterSpec for BOD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bod::R](R) reader structure"] -impl crate::Readable for BOD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [bod::W](W) writer structure"] +#[doc = "`read()` method returns [`bod::R`](R) reader structure"] +impl crate::Readable for BOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bod::W`](W) writer structure"] impl crate::Writable for BOD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/vreg_and_chip_reset/chip_reset.rs b/src/vreg_and_chip_reset/chip_reset.rs index f6b6afb8a..4bf065049 100644 --- a/src/vreg_and_chip_reset/chip_reset.rs +++ b/src/vreg_and_chip_reset/chip_reset.rs @@ -1,39 +1,7 @@ #[doc = "Register `CHIP_RESET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CHIP_RESET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HAD_POR` reader - Last reset was from the power-on reset or brown-out detection blocks"] pub type HAD_POR_R = crate::BitReader; #[doc = "Field `HAD_RUN` reader - Last reset was from the RUN pin"] @@ -47,7 +15,7 @@ pub type PSM_RESTART_FLAG_R = crate::BitReader; #[doc = "Field `PSM_RESTART_FLAG` writer - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] -pub type PSM_RESTART_FLAG_W<'a, const O: u8> = crate::BitWriter1C<'a, CHIP_RESET_SPEC, O>; +pub type PSM_RESTART_FLAG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 8 - Last reset was from the power-on reset or brown-out detection blocks"] #[inline(always)] @@ -78,32 +46,31 @@ impl W { In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] #[inline(always)] #[must_use] - pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W<24> { + pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W { PSM_RESTART_FLAG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Chip reset control and status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [chip_reset](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHIP_RESET_SPEC; impl crate::RegisterSpec for CHIP_RESET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chip_reset::R](R) reader structure"] -impl crate::Readable for CHIP_RESET_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [chip_reset::W](W) writer structure"] +#[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"] +impl crate::Readable for CHIP_RESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"] impl crate::Writable for CHIP_RESET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0100_0000; } diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs index 3a7a1e5a6..5a375bc51 100644 --- a/src/vreg_and_chip_reset/vreg.rs +++ b/src/vreg_and_chip_reset/vreg.rs @@ -1,51 +1,19 @@ #[doc = "Register `VREG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `VREG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - enable 0=not enabled, 1=enabled"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - enable 0=not enabled, 1=enabled"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, VREG_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HIZ` reader - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] pub type HIZ_R = crate::BitReader; #[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] -pub type HIZ_W<'a, const O: u8> = crate::BitWriter<'a, VREG_SPEC, O>; +pub type HIZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VSEL` reader - output voltage select 0000 to 0101 - 0.80V 0110 - 0.85V @@ -71,7 +39,7 @@ pub type VSEL_R = crate::FieldReader; 1101 - 1.20V 1110 - 1.25V 1111 - 1.30V"] -pub type VSEL_W<'a, const O: u8> = crate::FieldWriter<'a, VREG_SPEC, 4, O>; +pub type VSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `ROK` reader - regulation status 0=not in regulation, 1=in regulation"] pub type ROK_R = crate::BitReader; @@ -116,14 +84,14 @@ impl W { 0=not enabled, 1=enabled"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] #[inline(always)] #[must_use] - pub fn hiz(&mut self) -> HIZ_W<1> { + pub fn hiz(&mut self) -> HIZ_W { HIZ_W::new(self) } #[doc = "Bits 4:7 - output voltage select @@ -140,32 +108,31 @@ impl W { 1111 - 1.30V"] #[inline(always)] #[must_use] - pub fn vsel(&mut self) -> VSEL_W<4> { + pub fn vsel(&mut self) -> VSEL_W { VSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Voltage regulator control and status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [vreg](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`vreg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VREG_SPEC; impl crate::RegisterSpec for VREG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vreg::R](R) reader structure"] -impl crate::Readable for VREG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +#[doc = "`read()` method returns [`vreg::R`](R) reader structure"] +impl crate::Readable for VREG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"] impl crate::Writable for VREG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog.rs b/src/watchdog.rs index 227684eca..590079b34 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -28,53 +28,115 @@ pub struct RegisterBlock { #[doc = "0x2c - Controls the tick generator"] pub tick: TICK, } -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] pub mod ctrl; -#[doc = "LOAD (w) register accessor: an alias for `Reg`"] +#[doc = "LOAD (w) register accessor: Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@load`] +module"] pub type LOAD = crate::Reg; #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1)."] pub mod load; -#[doc = "REASON (r) register accessor: an alias for `Reg`"] +#[doc = "REASON (r) register accessor: Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + +You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reason`] +module"] pub type REASON = crate::Reg; #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset."] pub mod reason; -#[doc = "SCRATCH0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH0 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch0`] +module"] pub type SCRATCH0 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch0; -#[doc = "SCRATCH1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH1 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch1`] +module"] pub type SCRATCH1 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch1; -#[doc = "SCRATCH2 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH2 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch2`] +module"] pub type SCRATCH2 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch2; -#[doc = "SCRATCH3 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH3 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch3`] +module"] pub type SCRATCH3 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch3; -#[doc = "SCRATCH4 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH4 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch4`] +module"] pub type SCRATCH4 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch4; -#[doc = "SCRATCH5 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH5 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch5`] +module"] pub type SCRATCH5 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch5; -#[doc = "SCRATCH6 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH6 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch6`] +module"] pub type SCRATCH6 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch6; -#[doc = "SCRATCH7 (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH7 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch7`] +module"] pub type SCRATCH7 = crate::Reg; #[doc = "Scratch register. Information persists through soft reset of the chip."] pub mod scratch7; -#[doc = "TICK (rw) register accessor: an alias for `Reg`"] +#[doc = "TICK (rw) register accessor: Controls the tick generator + +You can [`read`](crate::generic::Reg::read) this register and get [`tick::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tick::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tick`] +module"] pub type TICK = crate::Reg; #[doc = "Controls the tick generator"] pub mod tick; diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs index 5d6bda072..0305b9d73 100644 --- a/src/watchdog/ctrl.rs +++ b/src/watchdog/ctrl.rs @@ -1,61 +1,29 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIME` reader - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered"] pub type TIME_R = crate::FieldReader; #[doc = "Field `PAUSE_JTAG` reader - Pause the watchdog timer when JTAG is accessing the bus fabric"] pub type PAUSE_JTAG_R = crate::BitReader; #[doc = "Field `PAUSE_JTAG` writer - Pause the watchdog timer when JTAG is accessing the bus fabric"] -pub type PAUSE_JTAG_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type PAUSE_JTAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PAUSE_DBG0` reader - Pause the watchdog timer when processor 0 is in debug mode"] pub type PAUSE_DBG0_R = crate::BitReader; #[doc = "Field `PAUSE_DBG0` writer - Pause the watchdog timer when processor 0 is in debug mode"] -pub type PAUSE_DBG0_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type PAUSE_DBG0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PAUSE_DBG1` reader - Pause the watchdog timer when processor 1 is in debug mode"] pub type PAUSE_DBG1_R = crate::BitReader; #[doc = "Field `PAUSE_DBG1` writer - Pause the watchdog timer when processor 1 is in debug mode"] -pub type PAUSE_DBG1_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type PAUSE_DBG1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - When not enabled the watchdog timer is paused"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - When not enabled the watchdog timer is paused"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRIGGER` reader - Trigger a watchdog reset"] pub type TRIGGER_R = crate::BitReader; #[doc = "Field `TRIGGER` writer - Trigger a watchdog reset"] -pub type TRIGGER_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type TRIGGER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:23 - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered"] #[inline(always)] @@ -92,37 +60,41 @@ impl W { #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"] #[inline(always)] #[must_use] - pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W<24> { + pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W { PAUSE_JTAG_W::new(self) } #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"] #[inline(always)] #[must_use] - pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W<25> { + pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W { PAUSE_DBG0_W::new(self) } #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"] #[inline(always)] #[must_use] - pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W<26> { + pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W { PAUSE_DBG1_W::new(self) } #[doc = "Bit 30 - When not enabled the watchdog timer is paused"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<30> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 31 - Trigger a watchdog reset"] #[inline(always)] #[must_use] - pub fn trigger(&mut self) -> TRIGGER_W<31> { + pub fn trigger(&mut self) -> TRIGGER_W { TRIGGER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -130,20 +102,15 @@ impl W { The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/load.rs b/src/watchdog/load.rs index 063631941..f70d37784 100644 --- a/src/watchdog/load.rs +++ b/src/watchdog/load.rs @@ -1,52 +1,34 @@ #[doc = "Register `LOAD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOAD` writer - "] -pub type LOAD_W<'a, const O: u8> = crate::FieldWriter<'a, LOAD_SPEC, 24, O, u32>; +pub type LOAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl W { #[doc = "Bits 0:23"] #[inline(always)] #[must_use] - pub fn load(&mut self) -> LOAD_W<0> { + pub fn load(&mut self) -> LOAD_W { LOAD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). -This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [load](index.html) module"] +You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LOAD_SPEC; impl crate::RegisterSpec for LOAD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [load::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"] impl crate::Writable for LOAD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/reason.rs b/src/watchdog/reason.rs index a843c1284..03699afc4 100644 --- a/src/watchdog/reason.rs +++ b/src/watchdog/reason.rs @@ -1,18 +1,5 @@ #[doc = "Register `REASON` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER` reader - "] pub type TIMER_R = crate::BitReader; #[doc = "Field `FORCE` reader - "] @@ -31,17 +18,13 @@ impl R { } #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [reason](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct REASON_SPEC; impl crate::RegisterSpec for REASON_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [reason::R](R) reader structure"] -impl crate::Readable for REASON_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`reason::R`](R) reader structure"] +impl crate::Readable for REASON_SPEC {} #[doc = "`reset()` method sets REASON to value 0"] impl crate::Resettable for REASON_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/watchdog/scratch0.rs b/src/watchdog/scratch0.rs index 27b88597b..3adddd4e8 100644 --- a/src/watchdog/scratch0.rs +++ b/src/watchdog/scratch0.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH0_SPEC; impl crate::RegisterSpec for SCRATCH0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch0::R](R) reader structure"] -impl crate::Readable for SCRATCH0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch0::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch0::R`](R) reader structure"] +impl crate::Readable for SCRATCH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch0::W`](W) writer structure"] impl crate::Writable for SCRATCH0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch1.rs b/src/watchdog/scratch1.rs index 34632010c..91800f6a3 100644 --- a/src/watchdog/scratch1.rs +++ b/src/watchdog/scratch1.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH1_SPEC; impl crate::RegisterSpec for SCRATCH1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch1::R](R) reader structure"] -impl crate::Readable for SCRATCH1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch1::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch1::R`](R) reader structure"] +impl crate::Readable for SCRATCH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch1::W`](W) writer structure"] impl crate::Writable for SCRATCH1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch2.rs b/src/watchdog/scratch2.rs index 56a64d3a0..640674e3c 100644 --- a/src/watchdog/scratch2.rs +++ b/src/watchdog/scratch2.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch2](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH2_SPEC; impl crate::RegisterSpec for SCRATCH2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch2::R](R) reader structure"] -impl crate::Readable for SCRATCH2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch2::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch2::R`](R) reader structure"] +impl crate::Readable for SCRATCH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch2::W`](W) writer structure"] impl crate::Writable for SCRATCH2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch3.rs b/src/watchdog/scratch3.rs index afb4e2b84..fd81ff3df 100644 --- a/src/watchdog/scratch3.rs +++ b/src/watchdog/scratch3.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch3](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH3_SPEC; impl crate::RegisterSpec for SCRATCH3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch3::R](R) reader structure"] -impl crate::Readable for SCRATCH3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch3::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch3::R`](R) reader structure"] +impl crate::Readable for SCRATCH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch3::W`](W) writer structure"] impl crate::Writable for SCRATCH3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch4.rs b/src/watchdog/scratch4.rs index ad9a5851b..710fddb98 100644 --- a/src/watchdog/scratch4.rs +++ b/src/watchdog/scratch4.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch4](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH4_SPEC; impl crate::RegisterSpec for SCRATCH4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch4::R](R) reader structure"] -impl crate::Readable for SCRATCH4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch4::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch4::R`](R) reader structure"] +impl crate::Readable for SCRATCH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch4::W`](W) writer structure"] impl crate::Writable for SCRATCH4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch5.rs b/src/watchdog/scratch5.rs index 52f32ec52..57c186d18 100644 --- a/src/watchdog/scratch5.rs +++ b/src/watchdog/scratch5.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch5](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH5_SPEC; impl crate::RegisterSpec for SCRATCH5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch5::R](R) reader structure"] -impl crate::Readable for SCRATCH5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch5::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch5::R`](R) reader structure"] +impl crate::Readable for SCRATCH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch5::W`](W) writer structure"] impl crate::Writable for SCRATCH5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch6.rs b/src/watchdog/scratch6.rs index 2806471be..112f45048 100644 --- a/src/watchdog/scratch6.rs +++ b/src/watchdog/scratch6.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch6](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH6_SPEC; impl crate::RegisterSpec for SCRATCH6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch6::R](R) reader structure"] -impl crate::Readable for SCRATCH6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch6::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch6::R`](R) reader structure"] +impl crate::Readable for SCRATCH6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch6::W`](W) writer structure"] impl crate::Writable for SCRATCH6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/scratch7.rs b/src/watchdog/scratch7.rs index 39f262ebb..dbfd64c8d 100644 --- a/src/watchdog/scratch7.rs +++ b/src/watchdog/scratch7.rs @@ -1,39 +1,7 @@ #[doc = "Register `SCRATCH7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,29 +13,28 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Scratch register. Information persists through soft reset of the chip. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [scratch7](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH7_SPEC; impl crate::RegisterSpec for SCRATCH7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scratch7::R](R) reader structure"] -impl crate::Readable for SCRATCH7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch7::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch7::R`](R) reader structure"] +impl crate::Readable for SCRATCH7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch7::W`](W) writer structure"] impl crate::Writable for SCRATCH7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/watchdog/tick.rs b/src/watchdog/tick.rs index 4b3360803..01a3b7028 100644 --- a/src/watchdog/tick.rs +++ b/src/watchdog/tick.rs @@ -1,47 +1,15 @@ #[doc = "Register `TICK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TICK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CYCLES` reader - Total number of clk_tick cycles before the next tick."] pub type CYCLES_R = crate::FieldReader; #[doc = "Field `CYCLES` writer - Total number of clk_tick cycles before the next tick."] -pub type CYCLES_W<'a, const O: u8> = crate::FieldWriter<'a, TICK_SPEC, 9, O, u16>; +pub type CYCLES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `ENABLE` reader - start / stop tick generation"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - start / stop tick generation"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, TICK_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RUNNING` reader - Is the tick generator running?"] pub type RUNNING_R = crate::BitReader; #[doc = "Field `COUNT` reader - Count down timer: the remaining number clk_tick cycles before the next tick is generated."] @@ -72,38 +40,37 @@ impl W { #[doc = "Bits 0:8 - Total number of clk_tick cycles before the next tick."] #[inline(always)] #[must_use] - pub fn cycles(&mut self) -> CYCLES_W<0> { + pub fn cycles(&mut self) -> CYCLES_W { CYCLES_W::new(self) } #[doc = "Bit 9 - start / stop tick generation"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<9> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Controls the tick generator -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [tick](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`tick::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tick::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TICK_SPEC; impl crate::RegisterSpec for TICK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tick::R](R) reader structure"] -impl crate::Readable for TICK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tick::W](W) writer structure"] +#[doc = "`read()` method returns [`tick::R`](R) reader structure"] +impl crate::Readable for TICK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tick::W`](W) writer structure"] impl crate::Writable for TICK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl.rs b/src/xip_ctrl.rs index 6a33d95b2..86294c9fe 100644 --- a/src/xip_ctrl.rs +++ b/src/xip_ctrl.rs @@ -27,41 +27,90 @@ pub struct RegisterBlock { the DMA to bus stalls caused by other XIP traffic."] pub stream_fifo: STREAM_FIFO, } -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: Cache control + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "Cache control"] pub mod ctrl; -#[doc = "FLUSH (rw) register accessor: an alias for `Reg`"] +#[doc = "FLUSH (rw) register accessor: Cache Flush control + +You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flush`] +module"] pub type FLUSH = crate::Reg; #[doc = "Cache Flush control"] pub mod flush; -#[doc = "STAT (r) register accessor: an alias for `Reg`"] +#[doc = "STAT (r) register accessor: Cache Status + +You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Cache Status"] pub mod stat; -#[doc = "CTR_HIT (rw) register accessor: an alias for `Reg`"] +#[doc = "CTR_HIT (rw) register accessor: Cache Hit counter + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + +You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr_hit`] +module"] pub type CTR_HIT = crate::Reg; #[doc = "Cache Hit counter A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] pub mod ctr_hit; -#[doc = "CTR_ACC (rw) register accessor: an alias for `Reg`"] +#[doc = "CTR_ACC (rw) register accessor: Cache Access counter + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + +You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr_acc`] +module"] pub type CTR_ACC = crate::Reg; #[doc = "Cache Access counter A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] pub mod ctr_acc; -#[doc = "STREAM_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "STREAM_ADDR (rw) register accessor: FIFO stream address + +You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_addr`] +module"] pub type STREAM_ADDR = crate::Reg; #[doc = "FIFO stream address"] pub mod stream_addr; -#[doc = "STREAM_CTR (rw) register accessor: an alias for `Reg`"] +#[doc = "STREAM_CTR (rw) register accessor: FIFO stream control + +You can [`read`](crate::generic::Reg::read) this register and get [`stream_ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_ctr`] +module"] pub type STREAM_CTR = crate::Reg; #[doc = "FIFO stream control"] pub mod stream_ctr; -#[doc = "STREAM_FIFO (r) register accessor: an alias for `Reg`"] +#[doc = "STREAM_FIFO (r) register accessor: FIFO stream data + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + +You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_fifo`] +module"] pub type STREAM_FIFO = crate::Reg; #[doc = "FIFO stream data Streamed data is buffered here, for retrieval by the system DMA. diff --git a/src/xip_ctrl/ctr_acc.rs b/src/xip_ctrl/ctr_acc.rs index 4e7fe67b8..6681d1d4c 100644 --- a/src/xip_ctrl/ctr_acc.rs +++ b/src/xip_ctrl/ctr_acc.rs @@ -1,39 +1,7 @@ #[doc = "Register `CTR_ACC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTR_ACC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctr_acc](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTR_ACC_SPEC; impl crate::RegisterSpec for CTR_ACC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctr_acc::R](R) reader structure"] -impl crate::Readable for CTR_ACC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctr_acc::W](W) writer structure"] +#[doc = "`read()` method returns [`ctr_acc::R`](R) reader structure"] +impl crate::Readable for CTR_ACC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr_acc::W`](W) writer structure"] impl crate::Writable for CTR_ACC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/ctr_hit.rs b/src/xip_ctrl/ctr_hit.rs index 5d78a4914..bb6ca27f0 100644 --- a/src/xip_ctrl/ctr_hit.rs +++ b/src/xip_ctrl/ctr_hit.rs @@ -1,39 +1,7 @@ #[doc = "Register `CTR_HIT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTR_HIT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -57,20 +29,15 @@ impl W { i.e. when an XIP access is serviced directly from cached data. Write any value to clear. -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctr_hit](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTR_HIT_SPEC; impl crate::RegisterSpec for CTR_HIT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctr_hit::R](R) reader structure"] -impl crate::Readable for CTR_HIT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctr_hit::W](W) writer structure"] +#[doc = "`read()` method returns [`ctr_hit::R`](R) reader structure"] +impl crate::Readable for CTR_HIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr_hit::W`](W) writer structure"] impl crate::Writable for CTR_HIT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs index 3213cb2c4..aa2f66d42 100644 --- a/src/xip_ctrl/ctrl.rs +++ b/src/xip_ctrl/ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN` reader - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will @@ -49,7 +17,7 @@ pub type EN_R = crate::BitReader; If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERR_BADWRITE` reader - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, @@ -59,7 +27,7 @@ pub type ERR_BADWRITE_R = crate::BitReader; will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] -pub type ERR_BADWRITE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type ERR_BADWRITE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POWER_DOWN` reader - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot @@ -73,7 +41,7 @@ pub type POWER_DOWN_R = crate::BitReader; be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] -pub type POWER_DOWN_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type POWER_DOWN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, @@ -115,7 +83,7 @@ impl W { cache data RAM, and will produce a bus error response."] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<0> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) @@ -124,7 +92,7 @@ impl W { as usual."] #[inline(always)] #[must_use] - pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W<1> { + pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W { ERR_BADWRITE_W::new(self) } #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, @@ -135,32 +103,31 @@ impl W { the cache is powered down."] #[inline(always)] #[must_use] - pub fn power_down(&mut self) -> POWER_DOWN_W<3> { + pub fn power_down(&mut self) -> POWER_DOWN_W { POWER_DOWN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Cache control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/flush.rs b/src/xip_ctrl/flush.rs index ae33941d1..7d668d8fa 100644 --- a/src/xip_ctrl/flush.rs +++ b/src/xip_ctrl/flush.rs @@ -1,39 +1,7 @@ #[doc = "Register `FLUSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FLUSH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FLUSH` reader - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) @@ -45,7 +13,7 @@ pub type FLUSH_R = crate::BitReader; contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion."] -pub type FLUSH_W<'a, const O: u8> = crate::BitWriter<'a, FLUSH_SPEC, O>; +pub type FLUSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM @@ -65,32 +33,31 @@ impl W { completes. Alternatively STAT can be polled until completion."] #[inline(always)] #[must_use] - pub fn flush(&mut self) -> FLUSH_W<0> { + pub fn flush(&mut self) -> FLUSH_W { FLUSH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Cache Flush control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [flush](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FLUSH_SPEC; impl crate::RegisterSpec for FLUSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [flush::R](R) reader structure"] -impl crate::Readable for FLUSH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [flush::W](W) writer structure"] +#[doc = "`read()` method returns [`flush::R`](R) reader structure"] +impl crate::Readable for FLUSH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flush::W`](W) writer structure"] impl crate::Writable for FLUSH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/stat.rs b/src/xip_ctrl/stat.rs index 8fc9bfea1..3eceb6547 100644 --- a/src/xip_ctrl/stat.rs +++ b/src/xip_ctrl/stat.rs @@ -1,18 +1,5 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FLUSH_READY` reader - Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register."] @@ -46,17 +33,13 @@ impl R { } #[doc = "Cache Status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [stat](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} #[doc = "`reset()` method sets STAT to value 0x02"] impl crate::Resettable for STAT_SPEC { const RESET_VALUE: Self::Ux = 0x02; diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs index 2a9733cc4..4eac37698 100644 --- a/src/xip_ctrl/stream_addr.rs +++ b/src/xip_ctrl/stream_addr.rs @@ -1,39 +1,7 @@ #[doc = "Register `STREAM_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STREAM_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STREAM_ADDR` reader - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] @@ -41,7 +9,7 @@ pub type STREAM_ADDR_R = crate::FieldReader; #[doc = "Field `STREAM_ADDR` writer - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] -pub type STREAM_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, STREAM_ADDR_SPEC, 30, O, u32>; +pub type STREAM_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. @@ -57,32 +25,31 @@ impl W { Write the initial access address here before starting a streaming read."] #[inline(always)] #[must_use] - pub fn stream_addr(&mut self) -> STREAM_ADDR_W<2> { + pub fn stream_addr(&mut self) -> STREAM_ADDR_W { STREAM_ADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "FIFO stream address -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [stream_addr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STREAM_ADDR_SPEC; impl crate::RegisterSpec for STREAM_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stream_addr::R](R) reader structure"] -impl crate::Readable for STREAM_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stream_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`stream_addr::R`](R) reader structure"] +impl crate::Readable for STREAM_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_addr::W`](W) writer structure"] impl crate::Writable for STREAM_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs index 17c3b1b99..03c928323 100644 --- a/src/xip_ctrl/stream_ctr.rs +++ b/src/xip_ctrl/stream_ctr.rs @@ -1,39 +1,7 @@ #[doc = "Register `STREAM_CTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STREAM_CTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STREAM_CTR` reader - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. @@ -51,7 +19,7 @@ pub type STREAM_CTR_R = crate::FieldReader; Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] -pub type STREAM_CTR_W<'a, const O: u8> = crate::FieldWriter<'a, STREAM_CTR_SPEC, 22, O, u32>; +pub type STREAM_CTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 22, O, u32>; impl R { #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer @@ -77,32 +45,31 @@ impl W { draining the FIFO and reinitialising STREAM_ADDR)"] #[inline(always)] #[must_use] - pub fn stream_ctr(&mut self) -> STREAM_CTR_W<0> { + pub fn stream_ctr(&mut self) -> STREAM_CTR_W { STREAM_CTR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "FIFO stream control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [stream_ctr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`stream_ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STREAM_CTR_SPEC; impl crate::RegisterSpec for STREAM_CTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stream_ctr::R](R) reader structure"] -impl crate::Readable for STREAM_CTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stream_ctr::W](W) writer structure"] +#[doc = "`read()` method returns [`stream_ctr::R`](R) reader structure"] +impl crate::Readable for STREAM_CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_ctr::W`](W) writer structure"] impl crate::Writable for STREAM_CTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ctrl/stream_fifo.rs b/src/xip_ctrl/stream_fifo.rs index 71d9e09a6..7bc8c9e29 100644 --- a/src/xip_ctrl/stream_fifo.rs +++ b/src/xip_ctrl/stream_fifo.rs @@ -1,18 +1,5 @@ #[doc = "Register `STREAM_FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -28,17 +15,13 @@ impl core::fmt::Debug for crate::generic::Reg { This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic. -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [stream_fifo](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STREAM_FIFO_SPEC; impl crate::RegisterSpec for STREAM_FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stream_fifo::R](R) reader structure"] -impl crate::Readable for STREAM_FIFO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`stream_fifo::R`](R) reader structure"] +impl crate::Readable for STREAM_FIFO_SPEC {} #[doc = "`reset()` method sets STREAM_FIFO to value 0"] impl crate::Resettable for STREAM_FIFO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi.rs b/src/xip_ssi.rs index 4fcb95cc1..2648a274c 100644 --- a/src/xip_ssi.rs +++ b/src/xip_ssi.rs @@ -59,115 +59,255 @@ pub struct RegisterBlock { #[doc = "0xf8 - TX drive edge"] pub txd_drive_edge: TXD_DRIVE_EDGE, } -#[doc = "CTRLR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRLR0 (rw) register accessor: Control register 0 + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrlr0`] +module"] pub type CTRLR0 = crate::Reg; #[doc = "Control register 0"] pub mod ctrlr0; -#[doc = "CTRLR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRLR1 (rw) register accessor: Master Control register 1 + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrlr1`] +module"] pub type CTRLR1 = crate::Reg; #[doc = "Master Control register 1"] pub mod ctrlr1; -#[doc = "SSIENR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSIENR (rw) register accessor: SSI Enable + +You can [`read`](crate::generic::Reg::read) this register and get [`ssienr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssienr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssienr`] +module"] pub type SSIENR = crate::Reg; #[doc = "SSI Enable"] pub mod ssienr; -#[doc = "MWCR (rw) register accessor: an alias for `Reg`"] +#[doc = "MWCR (rw) register accessor: Microwire Control + +You can [`read`](crate::generic::Reg::read) this register and get [`mwcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mwcr`] +module"] pub type MWCR = crate::Reg; #[doc = "Microwire Control"] pub mod mwcr; -#[doc = "SER (rw) register accessor: an alias for `Reg`"] +#[doc = "SER (rw) register accessor: Slave enable + +You can [`read`](crate::generic::Reg::read) this register and get [`ser::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ser`] +module"] pub type SER = crate::Reg; #[doc = "Slave enable"] pub mod ser; -#[doc = "BAUDR (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDR (rw) register accessor: Baud rate + +You can [`read`](crate::generic::Reg::read) this register and get [`baudr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@baudr`] +module"] pub type BAUDR = crate::Reg; #[doc = "Baud rate"] pub mod baudr; -#[doc = "TXFTLR (rw) register accessor: an alias for `Reg`"] +#[doc = "TXFTLR (rw) register accessor: TX FIFO threshold level + +You can [`read`](crate::generic::Reg::read) this register and get [`txftlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txftlr`] +module"] pub type TXFTLR = crate::Reg; #[doc = "TX FIFO threshold level"] pub mod txftlr; -#[doc = "RXFTLR (rw) register accessor: an alias for `Reg`"] +#[doc = "RXFTLR (rw) register accessor: RX FIFO threshold level + +You can [`read`](crate::generic::Reg::read) this register and get [`rxftlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxftlr`] +module"] pub type RXFTLR = crate::Reg; #[doc = "RX FIFO threshold level"] pub mod rxftlr; -#[doc = "TXFLR (r) register accessor: an alias for `Reg`"] +#[doc = "TXFLR (r) register accessor: TX FIFO level + +You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txflr`] +module"] pub type TXFLR = crate::Reg; #[doc = "TX FIFO level"] pub mod txflr; -#[doc = "RXFLR (r) register accessor: an alias for `Reg`"] +#[doc = "RXFLR (r) register accessor: RX FIFO level + +You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxflr`] +module"] pub type RXFLR = crate::Reg; #[doc = "RX FIFO level"] pub mod rxflr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status register + +You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sr`] +module"] pub type SR = crate::Reg; #[doc = "Status register"] pub mod sr; -#[doc = "IMR (rw) register accessor: an alias for `Reg`"] +#[doc = "IMR (rw) register accessor: Interrupt mask + +You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt mask"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt status + +You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt status"] pub mod isr; -#[doc = "RISR (r) register accessor: an alias for `Reg`"] +#[doc = "RISR (r) register accessor: Raw interrupt status + +You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@risr`] +module"] pub type RISR = crate::Reg; #[doc = "Raw interrupt status"] pub mod risr; -#[doc = "TXOICR (r) register accessor: an alias for `Reg`"] +#[doc = "TXOICR (r) register accessor: TX FIFO overflow interrupt clear + +You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txoicr`] +module"] pub type TXOICR = crate::Reg; #[doc = "TX FIFO overflow interrupt clear"] pub mod txoicr; -#[doc = "RXOICR (r) register accessor: an alias for `Reg`"] +#[doc = "RXOICR (r) register accessor: RX FIFO overflow interrupt clear + +You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxoicr`] +module"] pub type RXOICR = crate::Reg; #[doc = "RX FIFO overflow interrupt clear"] pub mod rxoicr; -#[doc = "RXUICR (r) register accessor: an alias for `Reg`"] +#[doc = "RXUICR (r) register accessor: RX FIFO underflow interrupt clear + +You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxuicr`] +module"] pub type RXUICR = crate::Reg; #[doc = "RX FIFO underflow interrupt clear"] pub mod rxuicr; -#[doc = "MSTICR (r) register accessor: an alias for `Reg`"] +#[doc = "MSTICR (r) register accessor: Multi-master interrupt clear + +You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@msticr`] +module"] pub type MSTICR = crate::Reg; #[doc = "Multi-master interrupt clear"] pub mod msticr; -#[doc = "ICR (r) register accessor: an alias for `Reg`"] +#[doc = "ICR (r) register accessor: Interrupt clear + +You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@icr`] +module"] pub type ICR = crate::Reg; #[doc = "Interrupt clear"] pub mod icr; -#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMACR (rw) register accessor: DMA control + +You can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dmacr`] +module"] pub type DMACR = crate::Reg; #[doc = "DMA control"] pub mod dmacr; -#[doc = "DMATDLR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMATDLR (rw) register accessor: DMA TX data level + +You can [`read`](crate::generic::Reg::read) this register and get [`dmatdlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dmatdlr`] +module"] pub type DMATDLR = crate::Reg; #[doc = "DMA TX data level"] pub mod dmatdlr; -#[doc = "DMARDLR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMARDLR (rw) register accessor: DMA RX data level + +You can [`read`](crate::generic::Reg::read) this register and get [`dmardlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmardlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dmardlr`] +module"] pub type DMARDLR = crate::Reg; #[doc = "DMA RX data level"] pub mod dmardlr; -#[doc = "IDR (r) register accessor: an alias for `Reg`"] +#[doc = "IDR (r) register accessor: Identification register + +You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@idr`] +module"] pub type IDR = crate::Reg; #[doc = "Identification register"] pub mod idr; -#[doc = "SSI_VERSION_ID (r) register accessor: an alias for `Reg`"] +#[doc = "SSI_VERSION_ID (r) register accessor: Version ID + +You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssi_version_id`] +module"] pub type SSI_VERSION_ID = crate::Reg; #[doc = "Version ID"] pub mod ssi_version_id; -#[doc = "DR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "DR0 (rw) register accessor: Data Register 0 (of 36) + +You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dr0`] +module"] pub type DR0 = crate::Reg; #[doc = "Data Register 0 (of 36)"] pub mod dr0; -#[doc = "RX_SAMPLE_DLY (rw) register accessor: an alias for `Reg`"] +#[doc = "RX_SAMPLE_DLY (rw) register accessor: RX sample delay + +You can [`read`](crate::generic::Reg::read) this register and get [`rx_sample_dly::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_sample_dly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rx_sample_dly`] +module"] pub type RX_SAMPLE_DLY = crate::Reg; #[doc = "RX sample delay"] pub mod rx_sample_dly; -#[doc = "SPI_CTRLR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SPI_CTRLR0 (rw) register accessor: SPI control + +You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spi_ctrlr0`] +module"] pub type SPI_CTRLR0 = crate::Reg; #[doc = "SPI control"] pub mod spi_ctrlr0; -#[doc = "TXD_DRIVE_EDGE (rw) register accessor: an alias for `Reg`"] +#[doc = "TXD_DRIVE_EDGE (rw) register accessor: TX drive edge + +You can [`read`](crate::generic::Reg::read) this register and get [`txd_drive_edge::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txd_drive_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txd_drive_edge`] +module"] pub type TXD_DRIVE_EDGE = crate::Reg; #[doc = "TX drive edge"] pub mod txd_drive_edge; diff --git a/src/xip_ssi/baudr.rs b/src/xip_ssi/baudr.rs index 0bb89448a..df07db9bd 100644 --- a/src/xip_ssi/baudr.rs +++ b/src/xip_ssi/baudr.rs @@ -1,43 +1,11 @@ #[doc = "Register `BAUDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SCKDV` reader - SSI clock divider"] pub type SCKDV_R = crate::FieldReader; #[doc = "Field `SCKDV` writer - SSI clock divider"] -pub type SCKDV_W<'a, const O: u8> = crate::FieldWriter<'a, BAUDR_SPEC, 16, O, u16>; +pub type SCKDV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - SSI clock divider"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - SSI clock divider"] #[inline(always)] #[must_use] - pub fn sckdv(&mut self) -> SCKDV_W<0> { + pub fn sckdv(&mut self) -> SCKDV_W { SCKDV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Baud rate -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [baudr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`baudr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDR_SPEC; impl crate::RegisterSpec for BAUDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [baudr::R](R) reader structure"] -impl crate::Readable for BAUDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudr::W](W) writer structure"] +#[doc = "`read()` method returns [`baudr::R`](R) reader structure"] +impl crate::Readable for BAUDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudr::W`](W) writer structure"] impl crate::Writable for BAUDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/ctrlr0.rs b/src/xip_ssi/ctrlr0.rs index e2b4a7186..e3d4e4fab 100644 --- a/src/xip_ssi/ctrlr0.rs +++ b/src/xip_ssi/ctrlr0.rs @@ -1,55 +1,23 @@ #[doc = "Register `CTRLR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRLR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DFS` reader - Data frame size"] pub type DFS_R = crate::FieldReader; #[doc = "Field `DFS` writer - Data frame size"] -pub type DFS_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR0_SPEC, 4, O>; +pub type DFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FRF` reader - Frame format"] pub type FRF_R = crate::FieldReader; #[doc = "Field `FRF` writer - Frame format"] -pub type FRF_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR0_SPEC, 2, O>; +pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `SCPH` reader - Serial clock phase"] pub type SCPH_R = crate::BitReader; #[doc = "Field `SCPH` writer - Serial clock phase"] -pub type SCPH_W<'a, const O: u8> = crate::BitWriter<'a, CTRLR0_SPEC, O>; +pub type SCPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCPOL` reader - Serial clock polarity"] pub type SCPOL_R = crate::BitReader; #[doc = "Field `SCPOL` writer - Serial clock polarity"] -pub type SCPOL_W<'a, const O: u8> = crate::BitWriter<'a, CTRLR0_SPEC, O>; +pub type SCPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TMOD` reader - Transfer mode"] pub type TMOD_R = crate::FieldReader; #[doc = "Transfer mode @@ -79,7 +47,7 @@ impl crate::FieldSpec for TMOD_A { impl TMOD_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TMOD_A { + pub const fn variant(&self) -> TMOD_A { match self.bits { 0 => TMOD_A::TX_AND_RX, 1 => TMOD_A::TX_ONLY, @@ -88,71 +56,75 @@ impl TMOD_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TX_AND_RX`"] + #[doc = "Both transmit and receive"] #[inline(always)] pub fn is_tx_and_rx(&self) -> bool { *self == TMOD_A::TX_AND_RX } - #[doc = "Checks if the value of the field is `TX_ONLY`"] + #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"] #[inline(always)] pub fn is_tx_only(&self) -> bool { *self == TMOD_A::TX_ONLY } - #[doc = "Checks if the value of the field is `RX_ONLY`"] + #[doc = "Receive only (not for FRF == 0, standard SPI mode)"] #[inline(always)] pub fn is_rx_only(&self) -> bool { *self == TMOD_A::RX_ONLY } - #[doc = "Checks if the value of the field is `EEPROM_READ`"] + #[doc = "EEPROM read mode (TX then RX; RX starts after control data TX'd)"] #[inline(always)] pub fn is_eeprom_read(&self) -> bool { *self == TMOD_A::EEPROM_READ } } #[doc = "Field `TMOD` writer - Transfer mode"] -pub type TMOD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CTRLR0_SPEC, 2, O, TMOD_A>; -impl<'a, const O: u8> TMOD_W<'a, O> { +pub type TMOD_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TMOD_A>; +impl<'a, REG, const O: u8> TMOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Both transmit and receive"] #[inline(always)] - pub fn tx_and_rx(self) -> &'a mut W { + pub fn tx_and_rx(self) -> &'a mut crate::W { self.variant(TMOD_A::TX_AND_RX) } #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"] #[inline(always)] - pub fn tx_only(self) -> &'a mut W { + pub fn tx_only(self) -> &'a mut crate::W { self.variant(TMOD_A::TX_ONLY) } #[doc = "Receive only (not for FRF == 0, standard SPI mode)"] #[inline(always)] - pub fn rx_only(self) -> &'a mut W { + pub fn rx_only(self) -> &'a mut crate::W { self.variant(TMOD_A::RX_ONLY) } #[doc = "EEPROM read mode (TX then RX; RX starts after control data TX'd)"] #[inline(always)] - pub fn eeprom_read(self) -> &'a mut W { + pub fn eeprom_read(self) -> &'a mut crate::W { self.variant(TMOD_A::EEPROM_READ) } } #[doc = "Field `SLV_OE` reader - Slave output enable"] pub type SLV_OE_R = crate::BitReader; #[doc = "Field `SLV_OE` writer - Slave output enable"] -pub type SLV_OE_W<'a, const O: u8> = crate::BitWriter<'a, CTRLR0_SPEC, O>; +pub type SLV_OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRL` reader - Shift register loop (test mode)"] pub type SRL_R = crate::BitReader; #[doc = "Field `SRL` writer - Shift register loop (test mode)"] -pub type SRL_W<'a, const O: u8> = crate::BitWriter<'a, CTRLR0_SPEC, O>; +pub type SRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFS` reader - Control frame size Value of n -> n+1 clocks per frame."] pub type CFS_R = crate::FieldReader; #[doc = "Field `CFS` writer - Control frame size Value of n -> n+1 clocks per frame."] -pub type CFS_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR0_SPEC, 4, O>; +pub type CFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `DFS_32` reader - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] pub type DFS_32_R = crate::FieldReader; #[doc = "Field `DFS_32` writer - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] -pub type DFS_32_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR0_SPEC, 5, O>; +pub type DFS_32_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SPI_FRF` reader - SPI frame format"] pub type SPI_FRF_R = crate::FieldReader; #[doc = "SPI frame format @@ -180,7 +152,7 @@ impl crate::FieldSpec for SPI_FRF_A { impl SPI_FRF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(SPI_FRF_A::STD), 1 => Some(SPI_FRF_A::DUAL), @@ -188,45 +160,49 @@ impl SPI_FRF_R { _ => None, } } - #[doc = "Checks if the value of the field is `STD`"] + #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"] #[inline(always)] pub fn is_std(&self) -> bool { *self == SPI_FRF_A::STD } - #[doc = "Checks if the value of the field is `DUAL`"] + #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"] #[inline(always)] pub fn is_dual(&self) -> bool { *self == SPI_FRF_A::DUAL } - #[doc = "Checks if the value of the field is `QUAD`"] + #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"] #[inline(always)] pub fn is_quad(&self) -> bool { *self == SPI_FRF_A::QUAD } } #[doc = "Field `SPI_FRF` writer - SPI frame format"] -pub type SPI_FRF_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR0_SPEC, 2, O, SPI_FRF_A>; -impl<'a, const O: u8> SPI_FRF_W<'a, O> { +pub type SPI_FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SPI_FRF_A>; +impl<'a, REG, const O: u8> SPI_FRF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"] #[inline(always)] - pub fn std(self) -> &'a mut W { + pub fn std(self) -> &'a mut crate::W { self.variant(SPI_FRF_A::STD) } #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"] #[inline(always)] - pub fn dual(self) -> &'a mut W { + pub fn dual(self) -> &'a mut crate::W { self.variant(SPI_FRF_A::DUAL) } #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"] #[inline(always)] - pub fn quad(self) -> &'a mut W { + pub fn quad(self) -> &'a mut crate::W { self.variant(SPI_FRF_A::QUAD) } } #[doc = "Field `SSTE` reader - Slave select toggle enable"] pub type SSTE_R = crate::BitReader; #[doc = "Field `SSTE` writer - Slave select toggle enable"] -pub type SSTE_W<'a, const O: u8> = crate::BitWriter<'a, CTRLR0_SPEC, O>; +pub type SSTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:3 - Data frame size"] #[inline(always)] @@ -290,94 +266,93 @@ impl W { #[doc = "Bits 0:3 - Data frame size"] #[inline(always)] #[must_use] - pub fn dfs(&mut self) -> DFS_W<0> { + pub fn dfs(&mut self) -> DFS_W { DFS_W::new(self) } #[doc = "Bits 4:5 - Frame format"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W<4> { + pub fn frf(&mut self) -> FRF_W { FRF_W::new(self) } #[doc = "Bit 6 - Serial clock phase"] #[inline(always)] #[must_use] - pub fn scph(&mut self) -> SCPH_W<6> { + pub fn scph(&mut self) -> SCPH_W { SCPH_W::new(self) } #[doc = "Bit 7 - Serial clock polarity"] #[inline(always)] #[must_use] - pub fn scpol(&mut self) -> SCPOL_W<7> { + pub fn scpol(&mut self) -> SCPOL_W { SCPOL_W::new(self) } #[doc = "Bits 8:9 - Transfer mode"] #[inline(always)] #[must_use] - pub fn tmod(&mut self) -> TMOD_W<8> { + pub fn tmod(&mut self) -> TMOD_W { TMOD_W::new(self) } #[doc = "Bit 10 - Slave output enable"] #[inline(always)] #[must_use] - pub fn slv_oe(&mut self) -> SLV_OE_W<10> { + pub fn slv_oe(&mut self) -> SLV_OE_W { SLV_OE_W::new(self) } #[doc = "Bit 11 - Shift register loop (test mode)"] #[inline(always)] #[must_use] - pub fn srl(&mut self) -> SRL_W<11> { + pub fn srl(&mut self) -> SRL_W { SRL_W::new(self) } #[doc = "Bits 12:15 - Control frame size Value of n -> n+1 clocks per frame."] #[inline(always)] #[must_use] - pub fn cfs(&mut self) -> CFS_W<12> { + pub fn cfs(&mut self) -> CFS_W { CFS_W::new(self) } #[doc = "Bits 16:20 - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] #[inline(always)] #[must_use] - pub fn dfs_32(&mut self) -> DFS_32_W<16> { + pub fn dfs_32(&mut self) -> DFS_32_W { DFS_32_W::new(self) } #[doc = "Bits 21:22 - SPI frame format"] #[inline(always)] #[must_use] - pub fn spi_frf(&mut self) -> SPI_FRF_W<21> { + pub fn spi_frf(&mut self) -> SPI_FRF_W { SPI_FRF_W::new(self) } #[doc = "Bit 24 - Slave select toggle enable"] #[inline(always)] #[must_use] - pub fn sste(&mut self) -> SSTE_W<24> { + pub fn sste(&mut self) -> SSTE_W { SSTE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Control register 0 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrlr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRLR0_SPEC; impl crate::RegisterSpec for CTRLR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrlr0::R](R) reader structure"] -impl crate::Readable for CTRLR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrlr0::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrlr0::R`](R) reader structure"] +impl crate::Readable for CTRLR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrlr0::W`](W) writer structure"] impl crate::Writable for CTRLR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/ctrlr1.rs b/src/xip_ssi/ctrlr1.rs index 52afad014..0d2381761 100644 --- a/src/xip_ssi/ctrlr1.rs +++ b/src/xip_ssi/ctrlr1.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTRLR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRLR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NDF` reader - Number of data frames"] pub type NDF_R = crate::FieldReader; #[doc = "Field `NDF` writer - Number of data frames"] -pub type NDF_W<'a, const O: u8> = crate::FieldWriter<'a, CTRLR1_SPEC, 16, O, u16>; +pub type NDF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of data frames"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:15 - Number of data frames"] #[inline(always)] #[must_use] - pub fn ndf(&mut self) -> NDF_W<0> { + pub fn ndf(&mut self) -> NDF_W { NDF_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Master Control register 1 -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrlr1](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRLR1_SPEC; impl crate::RegisterSpec for CTRLR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrlr1::R](R) reader structure"] -impl crate::Readable for CTRLR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrlr1::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrlr1::R`](R) reader structure"] +impl crate::Readable for CTRLR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrlr1::W`](W) writer structure"] impl crate::Writable for CTRLR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/dmacr.rs b/src/xip_ssi/dmacr.rs index fa2fd845e..653e72035 100644 --- a/src/xip_ssi/dmacr.rs +++ b/src/xip_ssi/dmacr.rs @@ -1,47 +1,15 @@ #[doc = "Register `DMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDMAE` reader - Receive DMA enable"] pub type RDMAE_R = crate::BitReader; #[doc = "Field `RDMAE` writer - Receive DMA enable"] -pub type RDMAE_W<'a, const O: u8> = crate::BitWriter<'a, DMACR_SPEC, O>; +pub type RDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDMAE` reader - Transmit DMA enable"] pub type TDMAE_R = crate::BitReader; #[doc = "Field `TDMAE` writer - Transmit DMA enable"] -pub type TDMAE_W<'a, const O: u8> = crate::BitWriter<'a, DMACR_SPEC, O>; +pub type TDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive DMA enable"] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bit 0 - Receive DMA enable"] #[inline(always)] #[must_use] - pub fn rdmae(&mut self) -> RDMAE_W<0> { + pub fn rdmae(&mut self) -> RDMAE_W { RDMAE_W::new(self) } #[doc = "Bit 1 - Transmit DMA enable"] #[inline(always)] #[must_use] - pub fn tdmae(&mut self) -> TDMAE_W<1> { + pub fn tdmae(&mut self) -> TDMAE_W { TDMAE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dmacr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMACR_SPEC; impl crate::RegisterSpec for DMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmacr::R](R) reader structure"] -impl crate::Readable for DMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmacr::R`](R) reader structure"] +impl crate::Readable for DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"] impl crate::Writable for DMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/dmardlr.rs b/src/xip_ssi/dmardlr.rs index 60f9e856e..67a984851 100644 --- a/src/xip_ssi/dmardlr.rs +++ b/src/xip_ssi/dmardlr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMARDLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMARDLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMARDL` reader - Receive data watermark level (DMARDLR+1)"] pub type DMARDL_R = crate::FieldReader; #[doc = "Field `DMARDL` writer - Receive data watermark level (DMARDLR+1)"] -pub type DMARDL_W<'a, const O: u8> = crate::FieldWriter<'a, DMARDLR_SPEC, 8, O>; +pub type DMARDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Receive data watermark level (DMARDLR+1)"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - Receive data watermark level (DMARDLR+1)"] #[inline(always)] #[must_use] - pub fn dmardl(&mut self) -> DMARDL_W<0> { + pub fn dmardl(&mut self) -> DMARDL_W { DMARDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA RX data level -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dmardlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dmardlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmardlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMARDLR_SPEC; impl crate::RegisterSpec for DMARDLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmardlr::R](R) reader structure"] -impl crate::Readable for DMARDLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmardlr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmardlr::R`](R) reader structure"] +impl crate::Readable for DMARDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmardlr::W`](W) writer structure"] impl crate::Writable for DMARDLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/dmatdlr.rs b/src/xip_ssi/dmatdlr.rs index 022f1d9f0..afee924b4 100644 --- a/src/xip_ssi/dmatdlr.rs +++ b/src/xip_ssi/dmatdlr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMATDLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMATDLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMATDL` reader - Transmit data watermark level"] pub type DMATDL_R = crate::FieldReader; #[doc = "Field `DMATDL` writer - Transmit data watermark level"] -pub type DMATDL_W<'a, const O: u8> = crate::FieldWriter<'a, DMATDLR_SPEC, 8, O>; +pub type DMATDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Transmit data watermark level"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - Transmit data watermark level"] #[inline(always)] #[must_use] - pub fn dmatdl(&mut self) -> DMATDL_W<0> { + pub fn dmatdl(&mut self) -> DMATDL_W { DMATDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "DMA TX data level -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dmatdlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dmatdlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMATDLR_SPEC; impl crate::RegisterSpec for DMATDLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmatdlr::R](R) reader structure"] -impl crate::Readable for DMATDLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmatdlr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmatdlr::R`](R) reader structure"] +impl crate::Readable for DMATDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmatdlr::W`](W) writer structure"] impl crate::Writable for DMATDLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/dr0.rs b/src/xip_ssi/dr0.rs index bb86b1160..6fd432599 100644 --- a/src/xip_ssi/dr0.rs +++ b/src/xip_ssi/dr0.rs @@ -1,43 +1,11 @@ #[doc = "Register `DR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DR` reader - First data register of 36"] pub type DR_R = crate::FieldReader; #[doc = "Field `DR` writer - First data register of 36"] -pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, DR0_SPEC, 32, O, u32>; +pub type DR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - First data register of 36"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:31 - First data register of 36"] #[inline(always)] #[must_use] - pub fn dr(&mut self) -> DR_W<0> { + pub fn dr(&mut self) -> DR_W { DR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Data Register 0 (of 36) -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DR0_SPEC; impl crate::RegisterSpec for DR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dr0::R](R) reader structure"] -impl crate::Readable for DR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dr0::W](W) writer structure"] +#[doc = "`read()` method returns [`dr0::R`](R) reader structure"] +impl crate::Readable for DR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dr0::W`](W) writer structure"] impl crate::Writable for DR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/icr.rs b/src/xip_ssi/icr.rs index e9a457fa1..53df8a9d5 100644 --- a/src/xip_ssi/icr.rs +++ b/src/xip_ssi/icr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ICR` reader - Clear-on-read all active interrupts"] pub type ICR_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Interrupt clear -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [icr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [icr::R](R) reader structure"] -impl crate::Readable for ICR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`icr::R`](R) reader structure"] +impl crate::Readable for ICR_SPEC {} #[doc = "`reset()` method sets ICR to value 0"] impl crate::Resettable for ICR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/idr.rs b/src/xip_ssi/idr.rs index 3b2dca107..88eeabdc2 100644 --- a/src/xip_ssi/idr.rs +++ b/src/xip_ssi/idr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IDCODE` reader - Peripheral dentification code"] pub type IDCODE_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Identification register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [idr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [idr::R](R) reader structure"] -impl crate::Readable for IDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`idr::R`](R) reader structure"] +impl crate::Readable for IDR_SPEC {} #[doc = "`reset()` method sets IDR to value 0x5153_5049"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: Self::Ux = 0x5153_5049; diff --git a/src/xip_ssi/imr.rs b/src/xip_ssi/imr.rs index 41270bf75..5f27ce5ae 100644 --- a/src/xip_ssi/imr.rs +++ b/src/xip_ssi/imr.rs @@ -1,63 +1,31 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXEIM` reader - Transmit FIFO empty interrupt mask"] pub type TXEIM_R = crate::BitReader; #[doc = "Field `TXEIM` writer - Transmit FIFO empty interrupt mask"] -pub type TXEIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TXEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOIM` reader - Transmit FIFO overflow interrupt mask"] pub type TXOIM_R = crate::BitReader; #[doc = "Field `TXOIM` writer - Transmit FIFO overflow interrupt mask"] -pub type TXOIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TXOIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUIM` reader - Receive FIFO underflow interrupt mask"] pub type RXUIM_R = crate::BitReader; #[doc = "Field `RXUIM` writer - Receive FIFO underflow interrupt mask"] -pub type RXUIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RXUIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOIM` reader - Receive FIFO overflow interrupt mask"] pub type RXOIM_R = crate::BitReader; #[doc = "Field `RXOIM` writer - Receive FIFO overflow interrupt mask"] -pub type RXOIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RXOIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFIM` reader - Receive FIFO full interrupt mask"] pub type RXFIM_R = crate::BitReader; #[doc = "Field `RXFIM` writer - Receive FIFO full interrupt mask"] -pub type RXFIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RXFIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSTIM` reader - Multi-master contention interrupt mask"] pub type MSTIM_R = crate::BitReader; #[doc = "Field `MSTIM` writer - Multi-master contention interrupt mask"] -pub type MSTIM_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type MSTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transmit FIFO empty interrupt mask"] #[inline(always)] @@ -94,62 +62,61 @@ impl W { #[doc = "Bit 0 - Transmit FIFO empty interrupt mask"] #[inline(always)] #[must_use] - pub fn txeim(&mut self) -> TXEIM_W<0> { + pub fn txeim(&mut self) -> TXEIM_W { TXEIM_W::new(self) } #[doc = "Bit 1 - Transmit FIFO overflow interrupt mask"] #[inline(always)] #[must_use] - pub fn txoim(&mut self) -> TXOIM_W<1> { + pub fn txoim(&mut self) -> TXOIM_W { TXOIM_W::new(self) } #[doc = "Bit 2 - Receive FIFO underflow interrupt mask"] #[inline(always)] #[must_use] - pub fn rxuim(&mut self) -> RXUIM_W<2> { + pub fn rxuim(&mut self) -> RXUIM_W { RXUIM_W::new(self) } #[doc = "Bit 3 - Receive FIFO overflow interrupt mask"] #[inline(always)] #[must_use] - pub fn rxoim(&mut self) -> RXOIM_W<3> { + pub fn rxoim(&mut self) -> RXOIM_W { RXOIM_W::new(self) } #[doc = "Bit 4 - Receive FIFO full interrupt mask"] #[inline(always)] #[must_use] - pub fn rxfim(&mut self) -> RXFIM_W<4> { + pub fn rxfim(&mut self) -> RXFIM_W { RXFIM_W::new(self) } #[doc = "Bit 5 - Multi-master contention interrupt mask"] #[inline(always)] #[must_use] - pub fn mstim(&mut self) -> MSTIM_W<5> { + pub fn mstim(&mut self) -> MSTIM_W { MSTIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Interrupt mask -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [imr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"] +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] impl crate::Writable for IMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/isr.rs b/src/xip_ssi/isr.rs index 8b27169b7..631bb9462 100644 --- a/src/xip_ssi/isr.rs +++ b/src/xip_ssi/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXEIS` reader - Transmit FIFO empty interrupt status"] pub type TXEIS_R = crate::BitReader; #[doc = "Field `TXOIS` reader - Transmit FIFO overflow interrupt status"] @@ -59,17 +46,13 @@ impl R { } #[doc = "Interrupt status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [isr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/msticr.rs b/src/xip_ssi/msticr.rs index a16cabad7..fe2388043 100644 --- a/src/xip_ssi/msticr.rs +++ b/src/xip_ssi/msticr.rs @@ -1,18 +1,5 @@ #[doc = "Register `MSTICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MSTICR` reader - Clear-on-read multi-master contention interrupt"] pub type MSTICR_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Multi-master interrupt clear -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [msticr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSTICR_SPEC; impl crate::RegisterSpec for MSTICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [msticr::R](R) reader structure"] -impl crate::Readable for MSTICR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`msticr::R`](R) reader structure"] +impl crate::Readable for MSTICR_SPEC {} #[doc = "`reset()` method sets MSTICR to value 0"] impl crate::Resettable for MSTICR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/mwcr.rs b/src/xip_ssi/mwcr.rs index 9851ac783..773d364fc 100644 --- a/src/xip_ssi/mwcr.rs +++ b/src/xip_ssi/mwcr.rs @@ -1,51 +1,19 @@ #[doc = "Register `MWCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MWCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MWMOD` reader - Microwire transfer mode"] pub type MWMOD_R = crate::BitReader; #[doc = "Field `MWMOD` writer - Microwire transfer mode"] -pub type MWMOD_W<'a, const O: u8> = crate::BitWriter<'a, MWCR_SPEC, O>; +pub type MWMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MDD` reader - Microwire control"] pub type MDD_R = crate::BitReader; #[doc = "Field `MDD` writer - Microwire control"] -pub type MDD_W<'a, const O: u8> = crate::BitWriter<'a, MWCR_SPEC, O>; +pub type MDD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MHS` reader - Microwire handshaking"] pub type MHS_R = crate::BitReader; #[doc = "Field `MHS` writer - Microwire handshaking"] -pub type MHS_W<'a, const O: u8> = crate::BitWriter<'a, MWCR_SPEC, O>; +pub type MHS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Microwire transfer mode"] #[inline(always)] @@ -67,44 +35,43 @@ impl W { #[doc = "Bit 0 - Microwire transfer mode"] #[inline(always)] #[must_use] - pub fn mwmod(&mut self) -> MWMOD_W<0> { + pub fn mwmod(&mut self) -> MWMOD_W { MWMOD_W::new(self) } #[doc = "Bit 1 - Microwire control"] #[inline(always)] #[must_use] - pub fn mdd(&mut self) -> MDD_W<1> { + pub fn mdd(&mut self) -> MDD_W { MDD_W::new(self) } #[doc = "Bit 2 - Microwire handshaking"] #[inline(always)] #[must_use] - pub fn mhs(&mut self) -> MHS_W<2> { + pub fn mhs(&mut self) -> MHS_W { MHS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Microwire Control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [mwcr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`mwcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MWCR_SPEC; impl crate::RegisterSpec for MWCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mwcr::R](R) reader structure"] -impl crate::Readable for MWCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mwcr::W](W) writer structure"] +#[doc = "`read()` method returns [`mwcr::R`](R) reader structure"] +impl crate::Readable for MWCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mwcr::W`](W) writer structure"] impl crate::Writable for MWCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/risr.rs b/src/xip_ssi/risr.rs index 1e4649b15..76dc75c04 100644 --- a/src/xip_ssi/risr.rs +++ b/src/xip_ssi/risr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXEIR` reader - Transmit FIFO empty raw interrupt status"] pub type TXEIR_R = crate::BitReader; #[doc = "Field `TXOIR` reader - Transmit FIFO overflow raw interrupt status"] @@ -59,17 +46,13 @@ impl R { } #[doc = "Raw interrupt status -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [risr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RISR_SPEC; impl crate::RegisterSpec for RISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [risr::R](R) reader structure"] -impl crate::Readable for RISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`risr::R`](R) reader structure"] +impl crate::Readable for RISR_SPEC {} #[doc = "`reset()` method sets RISR to value 0"] impl crate::Resettable for RISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/rx_sample_dly.rs b/src/xip_ssi/rx_sample_dly.rs index f987df2f7..317740b2d 100644 --- a/src/xip_ssi/rx_sample_dly.rs +++ b/src/xip_ssi/rx_sample_dly.rs @@ -1,43 +1,11 @@ #[doc = "Register `RX_SAMPLE_DLY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RX_SAMPLE_DLY` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSD` reader - RXD sample delay (in SCLK cycles)"] pub type RSD_R = crate::FieldReader; #[doc = "Field `RSD` writer - RXD sample delay (in SCLK cycles)"] -pub type RSD_W<'a, const O: u8> = crate::FieldWriter<'a, RX_SAMPLE_DLY_SPEC, 8, O>; +pub type RSD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - RXD sample delay (in SCLK cycles)"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - RXD sample delay (in SCLK cycles)"] #[inline(always)] #[must_use] - pub fn rsd(&mut self) -> RSD_W<0> { + pub fn rsd(&mut self) -> RSD_W { RSD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "RX sample delay -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rx_sample_dly](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rx_sample_dly::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_sample_dly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RX_SAMPLE_DLY_SPEC; impl crate::RegisterSpec for RX_SAMPLE_DLY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rx_sample_dly::R](R) reader structure"] -impl crate::Readable for RX_SAMPLE_DLY_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rx_sample_dly::W](W) writer structure"] +#[doc = "`read()` method returns [`rx_sample_dly::R`](R) reader structure"] +impl crate::Readable for RX_SAMPLE_DLY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_sample_dly::W`](W) writer structure"] impl crate::Writable for RX_SAMPLE_DLY_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/rxflr.rs b/src/xip_ssi/rxflr.rs index 049e03a87..5793c2491 100644 --- a/src/xip_ssi/rxflr.rs +++ b/src/xip_ssi/rxflr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXFLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXTFL` reader - Receive FIFO level"] pub type RXTFL_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "RX FIFO level -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rxflr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXFLR_SPEC; impl crate::RegisterSpec for RXFLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxflr::R](R) reader structure"] -impl crate::Readable for RXFLR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxflr::R`](R) reader structure"] +impl crate::Readable for RXFLR_SPEC {} #[doc = "`reset()` method sets RXFLR to value 0"] impl crate::Resettable for RXFLR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/rxftlr.rs b/src/xip_ssi/rxftlr.rs index 12b0e175c..d1b814a67 100644 --- a/src/xip_ssi/rxftlr.rs +++ b/src/xip_ssi/rxftlr.rs @@ -1,43 +1,11 @@ #[doc = "Register `RXFTLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXFTLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RFT` reader - Receive FIFO threshold"] pub type RFT_R = crate::FieldReader; #[doc = "Field `RFT` writer - Receive FIFO threshold"] -pub type RFT_W<'a, const O: u8> = crate::FieldWriter<'a, RXFTLR_SPEC, 8, O>; +pub type RFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Receive FIFO threshold"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - Receive FIFO threshold"] #[inline(always)] #[must_use] - pub fn rft(&mut self) -> RFT_W<0> { + pub fn rft(&mut self) -> RFT_W { RFT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "RX FIFO threshold level -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rxftlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rxftlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxftlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXFTLR_SPEC; impl crate::RegisterSpec for RXFTLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxftlr::R](R) reader structure"] -impl crate::Readable for RXFTLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxftlr::W](W) writer structure"] +#[doc = "`read()` method returns [`rxftlr::R`](R) reader structure"] +impl crate::Readable for RXFTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxftlr::W`](W) writer structure"] impl crate::Writable for RXFTLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/rxoicr.rs b/src/xip_ssi/rxoicr.rs index 876ec5903..b05a2c875 100644 --- a/src/xip_ssi/rxoicr.rs +++ b/src/xip_ssi/rxoicr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXOICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXOICR` reader - Clear-on-read receive FIFO overflow interrupt"] pub type RXOICR_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "RX FIFO overflow interrupt clear -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rxoicr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXOICR_SPEC; impl crate::RegisterSpec for RXOICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxoicr::R](R) reader structure"] -impl crate::Readable for RXOICR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxoicr::R`](R) reader structure"] +impl crate::Readable for RXOICR_SPEC {} #[doc = "`reset()` method sets RXOICR to value 0"] impl crate::Resettable for RXOICR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/rxuicr.rs b/src/xip_ssi/rxuicr.rs index 0aca86e9f..8b6386da5 100644 --- a/src/xip_ssi/rxuicr.rs +++ b/src/xip_ssi/rxuicr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXUICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXUICR` reader - Clear-on-read receive FIFO underflow interrupt"] pub type RXUICR_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "RX FIFO underflow interrupt clear -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [rxuicr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXUICR_SPEC; impl crate::RegisterSpec for RXUICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxuicr::R](R) reader structure"] -impl crate::Readable for RXUICR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxuicr::R`](R) reader structure"] +impl crate::Readable for RXUICR_SPEC {} #[doc = "`reset()` method sets RXUICR to value 0"] impl crate::Resettable for RXUICR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/ser.rs b/src/xip_ssi/ser.rs index 2a7452f4d..20947d667 100644 --- a/src/xip_ssi/ser.rs +++ b/src/xip_ssi/ser.rs @@ -1,39 +1,7 @@ #[doc = "Register `SER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SER` reader - For each bit: 0 -> slave not selected 1 -> slave selected"] @@ -41,7 +9,7 @@ pub type SER_R = crate::BitReader; #[doc = "Field `SER` writer - For each bit: 0 -> slave not selected 1 -> slave selected"] -pub type SER_W<'a, const O: u8> = crate::BitWriter<'a, SER_SPEC, O>; +pub type SER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - For each bit: 0 -> slave not selected @@ -57,32 +25,31 @@ impl W { 1 -> slave selected"] #[inline(always)] #[must_use] - pub fn ser(&mut self) -> SER_W<0> { + pub fn ser(&mut self) -> SER_W { SER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Slave enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ser](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ser::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SER_SPEC; impl crate::RegisterSpec for SER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ser::R](R) reader structure"] -impl crate::Readable for SER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ser::W](W) writer structure"] +#[doc = "`read()` method returns [`ser::R`](R) reader structure"] +impl crate::Readable for SER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ser::W`](W) writer structure"] impl crate::Writable for SER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/xip_ssi/spi_ctrlr0.rs index 83ed277e1..6482d3a37 100644 --- a/src/xip_ssi/spi_ctrlr0.rs +++ b/src/xip_ssi/spi_ctrlr0.rs @@ -1,39 +1,7 @@ #[doc = "Register `SPI_CTRLR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SPI_CTRLR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"] pub type TRANS_TYPE_R = crate::FieldReader; #[doc = "Address and instruction transfer format @@ -61,7 +29,7 @@ impl crate::FieldSpec for TRANS_TYPE_A { impl TRANS_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TRANS_TYPE_A::_1C1A), 1 => Some(TRANS_TYPE_A::_1C2A), @@ -69,46 +37,49 @@ impl TRANS_TYPE_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1C1A`"] + #[doc = "Command and address both in standard SPI frame format"] #[inline(always)] pub fn is_1c1a(&self) -> bool { *self == TRANS_TYPE_A::_1C1A } - #[doc = "Checks if the value of the field is `_1C2A`"] + #[doc = "Command in standard SPI format, address in format specified by FRF"] #[inline(always)] pub fn is_1c2a(&self) -> bool { *self == TRANS_TYPE_A::_1C2A } - #[doc = "Checks if the value of the field is `_2C2A`"] + #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"] #[inline(always)] pub fn is_2c2a(&self) -> bool { *self == TRANS_TYPE_A::_2C2A } } #[doc = "Field `TRANS_TYPE` writer - Address and instruction transfer format"] -pub type TRANS_TYPE_W<'a, const O: u8> = - crate::FieldWriter<'a, SPI_CTRLR0_SPEC, 2, O, TRANS_TYPE_A>; -impl<'a, const O: u8> TRANS_TYPE_W<'a, O> { +pub type TRANS_TYPE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TRANS_TYPE_A>; +impl<'a, REG, const O: u8> TRANS_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Command and address both in standard SPI frame format"] #[inline(always)] - pub fn _1c1a(self) -> &'a mut W { + pub fn _1c1a(self) -> &'a mut crate::W { self.variant(TRANS_TYPE_A::_1C1A) } #[doc = "Command in standard SPI format, address in format specified by FRF"] #[inline(always)] - pub fn _1c2a(self) -> &'a mut W { + pub fn _1c2a(self) -> &'a mut crate::W { self.variant(TRANS_TYPE_A::_1C2A) } #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"] #[inline(always)] - pub fn _2c2a(self) -> &'a mut W { + pub fn _2c2a(self) -> &'a mut crate::W { self.variant(TRANS_TYPE_A::_2C2A) } } #[doc = "Field `ADDR_L` reader - Address length (0b-60b in 4b increments)"] pub type ADDR_L_R = crate::FieldReader; #[doc = "Field `ADDR_L` writer - Address length (0b-60b in 4b increments)"] -pub type ADDR_L_W<'a, const O: u8> = crate::FieldWriter<'a, SPI_CTRLR0_SPEC, 4, O>; +pub type ADDR_L_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"] pub type INST_L_R = crate::FieldReader; #[doc = "Instruction length (0/4/8/16b) @@ -138,7 +109,7 @@ impl crate::FieldSpec for INST_L_A { impl INST_L_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INST_L_A { + pub const fn variant(&self) -> INST_L_A { match self.bits { 0 => INST_L_A::NONE, 1 => INST_L_A::_4B, @@ -147,71 +118,75 @@ impl INST_L_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No instruction"] #[inline(always)] pub fn is_none(&self) -> bool { *self == INST_L_A::NONE } - #[doc = "Checks if the value of the field is `_4B`"] + #[doc = "4-bit instruction"] #[inline(always)] pub fn is_4b(&self) -> bool { *self == INST_L_A::_4B } - #[doc = "Checks if the value of the field is `_8B`"] + #[doc = "8-bit instruction"] #[inline(always)] pub fn is_8b(&self) -> bool { *self == INST_L_A::_8B } - #[doc = "Checks if the value of the field is `_16B`"] + #[doc = "16-bit instruction"] #[inline(always)] pub fn is_16b(&self) -> bool { *self == INST_L_A::_16B } } #[doc = "Field `INST_L` writer - Instruction length (0/4/8/16b)"] -pub type INST_L_W<'a, const O: u8> = crate::FieldWriterSafe<'a, SPI_CTRLR0_SPEC, 2, O, INST_L_A>; -impl<'a, const O: u8> INST_L_W<'a, O> { +pub type INST_L_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, INST_L_A>; +impl<'a, REG, const O: u8> INST_L_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No instruction"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(INST_L_A::NONE) } #[doc = "4-bit instruction"] #[inline(always)] - pub fn _4b(self) -> &'a mut W { + pub fn _4b(self) -> &'a mut crate::W { self.variant(INST_L_A::_4B) } #[doc = "8-bit instruction"] #[inline(always)] - pub fn _8b(self) -> &'a mut W { + pub fn _8b(self) -> &'a mut crate::W { self.variant(INST_L_A::_8B) } #[doc = "16-bit instruction"] #[inline(always)] - pub fn _16b(self) -> &'a mut W { + pub fn _16b(self) -> &'a mut crate::W { self.variant(INST_L_A::_16B) } } #[doc = "Field `WAIT_CYCLES` reader - Wait cycles between control frame transmit and data reception (in SCLK cycles)"] pub type WAIT_CYCLES_R = crate::FieldReader; #[doc = "Field `WAIT_CYCLES` writer - Wait cycles between control frame transmit and data reception (in SCLK cycles)"] -pub type WAIT_CYCLES_W<'a, const O: u8> = crate::FieldWriter<'a, SPI_CTRLR0_SPEC, 5, O>; +pub type WAIT_CYCLES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `SPI_DDR_EN` reader - SPI DDR transfer enable"] pub type SPI_DDR_EN_R = crate::BitReader; #[doc = "Field `SPI_DDR_EN` writer - SPI DDR transfer enable"] -pub type SPI_DDR_EN_W<'a, const O: u8> = crate::BitWriter<'a, SPI_CTRLR0_SPEC, O>; +pub type SPI_DDR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INST_DDR_EN` reader - Instruction DDR transfer enable"] pub type INST_DDR_EN_R = crate::BitReader; #[doc = "Field `INST_DDR_EN` writer - Instruction DDR transfer enable"] -pub type INST_DDR_EN_W<'a, const O: u8> = crate::BitWriter<'a, SPI_CTRLR0_SPEC, O>; +pub type INST_DDR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_RXDS_EN` reader - Read data strobe enable"] pub type SPI_RXDS_EN_R = crate::BitReader; #[doc = "Field `SPI_RXDS_EN` writer - Read data strobe enable"] -pub type SPI_RXDS_EN_W<'a, const O: u8> = crate::BitWriter<'a, SPI_CTRLR0_SPEC, O>; +pub type SPI_RXDS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XIP_CMD` reader - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"] pub type XIP_CMD_R = crate::FieldReader; #[doc = "Field `XIP_CMD` writer - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"] -pub type XIP_CMD_W<'a, const O: u8> = crate::FieldWriter<'a, SPI_CTRLR0_SPEC, 8, O>; +pub type XIP_CMD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:1 - Address and instruction transfer format"] #[inline(always)] @@ -258,74 +233,73 @@ impl W { #[doc = "Bits 0:1 - Address and instruction transfer format"] #[inline(always)] #[must_use] - pub fn trans_type(&mut self) -> TRANS_TYPE_W<0> { + pub fn trans_type(&mut self) -> TRANS_TYPE_W { TRANS_TYPE_W::new(self) } #[doc = "Bits 2:5 - Address length (0b-60b in 4b increments)"] #[inline(always)] #[must_use] - pub fn addr_l(&mut self) -> ADDR_L_W<2> { + pub fn addr_l(&mut self) -> ADDR_L_W { ADDR_L_W::new(self) } #[doc = "Bits 8:9 - Instruction length (0/4/8/16b)"] #[inline(always)] #[must_use] - pub fn inst_l(&mut self) -> INST_L_W<8> { + pub fn inst_l(&mut self) -> INST_L_W { INST_L_W::new(self) } #[doc = "Bits 11:15 - Wait cycles between control frame transmit and data reception (in SCLK cycles)"] #[inline(always)] #[must_use] - pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W<11> { + pub fn wait_cycles(&mut self) -> WAIT_CYCLES_W { WAIT_CYCLES_W::new(self) } #[doc = "Bit 16 - SPI DDR transfer enable"] #[inline(always)] #[must_use] - pub fn spi_ddr_en(&mut self) -> SPI_DDR_EN_W<16> { + pub fn spi_ddr_en(&mut self) -> SPI_DDR_EN_W { SPI_DDR_EN_W::new(self) } #[doc = "Bit 17 - Instruction DDR transfer enable"] #[inline(always)] #[must_use] - pub fn inst_ddr_en(&mut self) -> INST_DDR_EN_W<17> { + pub fn inst_ddr_en(&mut self) -> INST_DDR_EN_W { INST_DDR_EN_W::new(self) } #[doc = "Bit 18 - Read data strobe enable"] #[inline(always)] #[must_use] - pub fn spi_rxds_en(&mut self) -> SPI_RXDS_EN_W<18> { + pub fn spi_rxds_en(&mut self) -> SPI_RXDS_EN_W { SPI_RXDS_EN_W::new(self) } #[doc = "Bits 24:31 - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"] #[inline(always)] #[must_use] - pub fn xip_cmd(&mut self) -> XIP_CMD_W<24> { + pub fn xip_cmd(&mut self) -> XIP_CMD_W { XIP_CMD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "SPI control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [spi_ctrlr0](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPI_CTRLR0_SPEC; impl crate::RegisterSpec for SPI_CTRLR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spi_ctrlr0::R](R) reader structure"] -impl crate::Readable for SPI_CTRLR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [spi_ctrlr0::W](W) writer structure"] +#[doc = "`read()` method returns [`spi_ctrlr0::R`](R) reader structure"] +impl crate::Readable for SPI_CTRLR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_ctrlr0::W`](W) writer structure"] impl crate::Writable for SPI_CTRLR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/sr.rs b/src/xip_ssi/sr.rs index cda45cc7d..207f68b7b 100644 --- a/src/xip_ssi/sr.rs +++ b/src/xip_ssi/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BUSY` reader - SSI busy flag"] pub type BUSY_R = crate::BitReader; #[doc = "Field `TFNF` reader - Transmit FIFO not full"] @@ -66,17 +53,13 @@ impl R { } #[doc = "Status register -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [sr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/ssi_version_id.rs b/src/xip_ssi/ssi_version_id.rs index 4ae4b2aae..fd0c42371 100644 --- a/src/xip_ssi/ssi_version_id.rs +++ b/src/xip_ssi/ssi_version_id.rs @@ -1,18 +1,5 @@ #[doc = "Register `SSI_VERSION_ID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SSI_COMP_VERSION` reader - SNPS component version (format X.YY)"] pub type SSI_COMP_VERSION_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "Version ID -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssi_version_id](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSI_VERSION_ID_SPEC; impl crate::RegisterSpec for SSI_VERSION_ID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssi_version_id::R](R) reader structure"] -impl crate::Readable for SSI_VERSION_ID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ssi_version_id::R`](R) reader structure"] +impl crate::Readable for SSI_VERSION_ID_SPEC {} #[doc = "`reset()` method sets SSI_VERSION_ID to value 0x3430_312a"] impl crate::Resettable for SSI_VERSION_ID_SPEC { const RESET_VALUE: Self::Ux = 0x3430_312a; diff --git a/src/xip_ssi/ssienr.rs b/src/xip_ssi/ssienr.rs index 20e2b00fe..8aab72c4b 100644 --- a/src/xip_ssi/ssienr.rs +++ b/src/xip_ssi/ssienr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SSIENR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSIENR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SSI_EN` reader - SSI enable"] pub type SSI_EN_R = crate::BitReader; #[doc = "Field `SSI_EN` writer - SSI enable"] -pub type SSI_EN_W<'a, const O: u8> = crate::BitWriter<'a, SSIENR_SPEC, O>; +pub type SSI_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - SSI enable"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bit 0 - SSI enable"] #[inline(always)] #[must_use] - pub fn ssi_en(&mut self) -> SSI_EN_W<0> { + pub fn ssi_en(&mut self) -> SSI_EN_W { SSI_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "SSI Enable -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ssienr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ssienr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssienr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSIENR_SPEC; impl crate::RegisterSpec for SSIENR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ssienr::R](R) reader structure"] -impl crate::Readable for SSIENR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ssienr::W](W) writer structure"] +#[doc = "`read()` method returns [`ssienr::R`](R) reader structure"] +impl crate::Readable for SSIENR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssienr::W`](W) writer structure"] impl crate::Writable for SSIENR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/txd_drive_edge.rs b/src/xip_ssi/txd_drive_edge.rs index 247f80eec..b23e5b0c4 100644 --- a/src/xip_ssi/txd_drive_edge.rs +++ b/src/xip_ssi/txd_drive_edge.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXD_DRIVE_EDGE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXD_DRIVE_EDGE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDE` reader - TXD drive edge"] pub type TDE_R = crate::FieldReader; #[doc = "Field `TDE` writer - TXD drive edge"] -pub type TDE_W<'a, const O: u8> = crate::FieldWriter<'a, TXD_DRIVE_EDGE_SPEC, 8, O>; +pub type TDE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - TXD drive edge"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - TXD drive edge"] #[inline(always)] #[must_use] - pub fn tde(&mut self) -> TDE_W<0> { + pub fn tde(&mut self) -> TDE_W { TDE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "TX drive edge -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [txd_drive_edge](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`txd_drive_edge::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txd_drive_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXD_DRIVE_EDGE_SPEC; impl crate::RegisterSpec for TXD_DRIVE_EDGE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txd_drive_edge::R](R) reader structure"] -impl crate::Readable for TXD_DRIVE_EDGE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txd_drive_edge::W](W) writer structure"] +#[doc = "`read()` method returns [`txd_drive_edge::R`](R) reader structure"] +impl crate::Readable for TXD_DRIVE_EDGE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txd_drive_edge::W`](W) writer structure"] impl crate::Writable for TXD_DRIVE_EDGE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/txflr.rs b/src/xip_ssi/txflr.rs index f937248e4..6fe835c65 100644 --- a/src/xip_ssi/txflr.rs +++ b/src/xip_ssi/txflr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXFLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TFTFL` reader - Transmit FIFO level"] pub type TFTFL_R = crate::FieldReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "TX FIFO level -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [txflr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXFLR_SPEC; impl crate::RegisterSpec for TXFLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txflr::R](R) reader structure"] -impl crate::Readable for TXFLR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txflr::R`](R) reader structure"] +impl crate::Readable for TXFLR_SPEC {} #[doc = "`reset()` method sets TXFLR to value 0"] impl crate::Resettable for TXFLR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xip_ssi/txftlr.rs b/src/xip_ssi/txftlr.rs index b9cd2b0b2..ecd41e215 100644 --- a/src/xip_ssi/txftlr.rs +++ b/src/xip_ssi/txftlr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXFTLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXFTLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TFT` reader - Transmit FIFO threshold"] pub type TFT_R = crate::FieldReader; #[doc = "Field `TFT` writer - Transmit FIFO threshold"] -pub type TFT_W<'a, const O: u8> = crate::FieldWriter<'a, TXFTLR_SPEC, 8, O>; +pub type TFT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Transmit FIFO threshold"] #[inline(always)] @@ -49,32 +17,31 @@ impl W { #[doc = "Bits 0:7 - Transmit FIFO threshold"] #[inline(always)] #[must_use] - pub fn tft(&mut self) -> TFT_W<0> { + pub fn tft(&mut self) -> TFT_W { TFT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "TX FIFO threshold level -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [txftlr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`txftlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txftlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXFTLR_SPEC; impl crate::RegisterSpec for TXFTLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txftlr::R](R) reader structure"] -impl crate::Readable for TXFTLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txftlr::W](W) writer structure"] +#[doc = "`read()` method returns [`txftlr::R`](R) reader structure"] +impl crate::Readable for TXFTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txftlr::W`](W) writer structure"] impl crate::Writable for TXFTLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xip_ssi/txoicr.rs b/src/xip_ssi/txoicr.rs index 4caf99307..64e49e2c8 100644 --- a/src/xip_ssi/txoicr.rs +++ b/src/xip_ssi/txoicr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXOICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXOICR` reader - Clear-on-read transmit FIFO overflow interrupt"] pub type TXOICR_R = crate::BitReader; impl R { @@ -24,17 +11,13 @@ impl R { } #[doc = "TX FIFO overflow interrupt clear -This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [txoicr](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXOICR_SPEC; impl crate::RegisterSpec for TXOICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txoicr::R](R) reader structure"] -impl crate::Readable for TXOICR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txoicr::R`](R) reader structure"] +impl crate::Readable for TXOICR_SPEC {} #[doc = "`reset()` method sets TXOICR to value 0"] impl crate::Resettable for TXOICR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/src/xosc.rs b/src/xosc.rs index 0e99d6024..51cd6be11 100644 --- a/src/xosc.rs +++ b/src/xosc.rs @@ -15,15 +15,35 @@ pub struct RegisterBlock { #[doc = "0x0c - Controls the startup delay"] pub startup: STARTUP, } -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: Crystal Oscillator Control + +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "Crystal Oscillator Control"] pub mod ctrl; -#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS (rw) register accessor: Crystal Oscillator Status + +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@status`] +module"] pub type STATUS = crate::Reg; #[doc = "Crystal Oscillator Status"] pub mod status; -#[doc = "DORMANT (rw) register accessor: an alias for `Reg`"] +#[doc = "DORMANT (rw) register accessor: Crystal Oscillator pause control + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + WARNING: stop the PLLs before selecting dormant mode + WARNING: setup the irq before selecting dormant mode + +You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant`] +module"] pub type DORMANT = crate::Reg; #[doc = "Crystal Oscillator pause control This is used to save power by pausing the XOSC @@ -32,7 +52,12 @@ pub type DORMANT = crate::Reg; WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode"] pub mod dormant; -#[doc = "STARTUP (rw) register accessor: an alias for `Reg`"] +#[doc = "STARTUP (rw) register accessor: Controls the startup delay + +You can [`read`](crate::generic::Reg::read) this register and get [`startup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@startup`] +module"] pub type STARTUP = crate::Reg; #[doc = "Controls the startup delay"] pub mod startup; diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs index 631dac08c..1950c67b1 100644 --- a/src/xosc/ctrl.rs +++ b/src/xosc/ctrl.rs @@ -1,39 +1,7 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."] pub type FREQ_RANGE_R = crate::FieldReader; #[doc = "Frequency range. This resets to 0xAA0 and cannot be changed. @@ -63,7 +31,7 @@ impl crate::FieldSpec for FREQ_RANGE_A { impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 2720 => Some(FREQ_RANGE_A::_1_15MHZ), 2721 => Some(FREQ_RANGE_A::RESERVED_1), @@ -72,48 +40,52 @@ impl FREQ_RANGE_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_15MHZ`"] + #[doc = "`101010100000`"] #[inline(always)] pub fn is_1_15mhz(&self) -> bool { *self == FREQ_RANGE_A::_1_15MHZ } - #[doc = "Checks if the value of the field is `RESERVED_1`"] + #[doc = "`101010100001`"] #[inline(always)] pub fn is_reserved_1(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_1 } - #[doc = "Checks if the value of the field is `RESERVED_2`"] + #[doc = "`101010100010`"] #[inline(always)] pub fn is_reserved_2(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_2 } - #[doc = "Checks if the value of the field is `RESERVED_3`"] + #[doc = "`101010100011`"] #[inline(always)] pub fn is_reserved_3(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_3 } } #[doc = "Field `FREQ_RANGE` writer - Frequency range. This resets to 0xAA0 and cannot be changed."] -pub type FREQ_RANGE_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 12, O, FREQ_RANGE_A>; -impl<'a, const O: u8> FREQ_RANGE_W<'a, O> { +pub type FREQ_RANGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, FREQ_RANGE_A>; +impl<'a, REG, const O: u8> FREQ_RANGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`101010100000`"] #[inline(always)] - pub fn _1_15mhz(self) -> &'a mut W { + pub fn _1_15mhz(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::_1_15MHZ) } #[doc = "`101010100001`"] #[inline(always)] - pub fn reserved_1(self) -> &'a mut W { + pub fn reserved_1(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::RESERVED_1) } #[doc = "`101010100010`"] #[inline(always)] - pub fn reserved_2(self) -> &'a mut W { + pub fn reserved_2(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::RESERVED_2) } #[doc = "`101010100011`"] #[inline(always)] - pub fn reserved_3(self) -> &'a mut W { + pub fn reserved_3(self) -> &'a mut crate::W { self.variant(FREQ_RANGE_A::RESERVED_3) } } @@ -146,19 +118,19 @@ impl crate::FieldSpec for ENABLE_A { impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 3358 => Some(ENABLE_A::DISABLE), 4011 => Some(ENABLE_A::ENABLE), _ => None, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "`110100011110`"] #[inline(always)] pub fn is_disable(&self) -> bool { *self == ENABLE_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "`111110101011`"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == ENABLE_A::ENABLE @@ -167,16 +139,20 @@ impl ENABLE_R { #[doc = "Field `ENABLE` writer - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] -pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 12, O, ENABLE_A>; -impl<'a, const O: u8> ENABLE_W<'a, O> { +pub type ENABLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, ENABLE_A>; +impl<'a, REG, const O: u8> ENABLE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`110100011110`"] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(ENABLE_A::DISABLE) } #[doc = "`111110101011`"] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(ENABLE_A::ENABLE) } } @@ -198,7 +174,7 @@ impl W { #[doc = "Bits 0:11 - Frequency range. This resets to 0xAA0 and cannot be changed."] #[inline(always)] #[must_use] - pub fn freq_range(&mut self) -> FREQ_RANGE_W<0> { + pub fn freq_range(&mut self) -> FREQ_RANGE_W { FREQ_RANGE_W::new(self) } #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. @@ -206,32 +182,31 @@ impl W { The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<12> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Crystal Oscillator Control -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [ctrl](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xosc/dormant.rs b/src/xosc/dormant.rs index 825ac577f..385c770e5 100644 --- a/src/xosc/dormant.rs +++ b/src/xosc/dormant.rs @@ -1,39 +1,7 @@ #[doc = "Register `DORMANT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DORMANT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -45,10 +13,14 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } @@ -59,20 +31,15 @@ impl W { WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [dormant](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_SPEC; impl crate::RegisterSpec for DORMANT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dormant::R](R) reader structure"] -impl crate::Readable for DORMANT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dormant::W](W) writer structure"] +#[doc = "`read()` method returns [`dormant::R`](R) reader structure"] +impl crate::Readable for DORMANT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] impl crate::Writable for DORMANT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs index 68036063a..8f8e5d243 100644 --- a/src/xosc/startup.rs +++ b/src/xosc/startup.rs @@ -1,47 +1,15 @@ #[doc = "Register `STARTUP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STARTUP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DELAY` reader - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] pub type DELAY_R = crate::FieldReader; #[doc = "Field `DELAY` writer - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] -pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, STARTUP_SPEC, 14, O, u16>; +pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `X4` reader - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly."] pub type X4_R = crate::BitReader; #[doc = "Field `X4` writer - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly."] -pub type X4_W<'a, const O: u8> = crate::BitWriter<'a, STARTUP_SPEC, O>; +pub type X4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:13 - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] #[inline(always)] @@ -58,38 +26,37 @@ impl W { #[doc = "Bits 0:13 - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W<0> { + pub fn delay(&mut self) -> DELAY_W { DELAY_W::new(self) } #[doc = "Bit 20 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly."] #[inline(always)] #[must_use] - pub fn x4(&mut self) -> X4_W<20> { + pub fn x4(&mut self) -> X4_W { X4_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Controls the startup delay -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [startup](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`startup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STARTUP_SPEC; impl crate::RegisterSpec for STARTUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [startup::R](R) reader structure"] -impl crate::Readable for STARTUP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [startup::W](W) writer structure"] +#[doc = "`read()` method returns [`startup::R`](R) reader structure"] +impl crate::Readable for STARTUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`startup::W`](W) writer structure"] impl crate::Writable for STARTUP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/src/xosc/status.rs b/src/xosc/status.rs index b2355671e..8446a24b3 100644 --- a/src/xosc/status.rs +++ b/src/xosc/status.rs @@ -1,39 +1,7 @@ #[doc = "Register `STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"] pub type FREQ_RANGE_R = crate::FieldReader; #[doc = "The current frequency range setting, always reads 0 @@ -63,7 +31,7 @@ impl crate::FieldSpec for FREQ_RANGE_A { impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FREQ_RANGE_A { + pub const fn variant(&self) -> FREQ_RANGE_A { match self.bits { 0 => FREQ_RANGE_A::_1_15MHZ, 1 => FREQ_RANGE_A::RESERVED_1, @@ -72,22 +40,22 @@ impl FREQ_RANGE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_1_15MHZ`"] + #[doc = "`0`"] #[inline(always)] pub fn is_1_15mhz(&self) -> bool { *self == FREQ_RANGE_A::_1_15MHZ } - #[doc = "Checks if the value of the field is `RESERVED_1`"] + #[doc = "`1`"] #[inline(always)] pub fn is_reserved_1(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_1 } - #[doc = "Checks if the value of the field is `RESERVED_2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_reserved_2(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_2 } - #[doc = "Checks if the value of the field is `RESERVED_3`"] + #[doc = "`11`"] #[inline(always)] pub fn is_reserved_3(&self) -> bool { *self == FREQ_RANGE_A::RESERVED_3 @@ -98,7 +66,7 @@ pub type ENABLED_R = crate::BitReader; #[doc = "Field `BADWRITE` reader - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] pub type BADWRITE_R = crate::BitReader; #[doc = "Field `BADWRITE` writer - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] -pub type BADWRITE_W<'a, const O: u8> = crate::BitWriter1C<'a, STATUS_SPEC, O>; +pub type BADWRITE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `STABLE` reader - Oscillator is running and stable"] pub type STABLE_R = crate::BitReader; impl R { @@ -127,32 +95,31 @@ impl W { #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] #[inline(always)] #[must_use] - pub fn badwrite(&mut self) -> BADWRITE_W<24> { + pub fn badwrite(&mut self) -> BADWRITE_W { BADWRITE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } #[doc = "Crystal Oscillator Status -This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). - -For information about available fields see [status](index.html) module"] +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status::R](R) reader structure"] -impl crate::Readable for STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] impl crate::Writable for STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0100_0000; } diff --git a/update.sh b/update.sh index 63c80e7ff..00dd11d30 100755 --- a/update.sh +++ b/update.sh @@ -5,7 +5,7 @@ SVDTOOLS="${SVDTOOLS:-svdtools}" set -ex -cargo install --version 0.29.0 svd2rust +cargo install --version 0.30.2 svd2rust cargo install --version 0.10.0 form rustup component add rustfmt if [ "$SVDTOOLS" == "svdtools" ]; then