diff --git a/rp2040-hal/Cargo.toml b/rp2040-hal/Cargo.toml index 3c8df516a..205a5cc95 100644 --- a/rp2040-hal/Cargo.toml +++ b/rp2040-hal/Cargo.toml @@ -30,7 +30,7 @@ embedded-io = "0.6.1" fugit = "0.3.6" itertools = { version = "0.10.1", default-features = false } nb = "1.0" -rp2040-pac = { version = "0.5.0", features = ["critical-section"] } +rp2040-pac = { version = "0.6.0", features = ["critical-section"] } paste = "1.0" pio = "0.2.0" rp2040-hal-macros = { version = "0.1.0", path = "../rp2040-hal-macros" } diff --git a/rp2040-hal/examples/rosc_as_system_clock.rs b/rp2040-hal/examples/rosc_as_system_clock.rs index d55d2e661..d4c8428e7 100644 --- a/rp2040-hal/examples/rosc_as_system_clock.rs +++ b/rp2040-hal/examples/rosc_as_system_clock.rs @@ -142,37 +142,39 @@ fn main() -> ! { /// Measure the actual speed of the ROSC at the current freq_range and drive strength config fn rosc_frequency_count_hz(clocks: &CLOCKS) -> HertzU32 { // Wait for the frequency counter to be ready - while clocks.fc0_status.read().running().bit_is_set() { + while clocks.fc0_status().read().running().bit_is_set() { cortex_m::asm::nop(); } // Set the speed of the reference clock in kHz. clocks - .fc0_ref_khz + .fc0_ref_khz() .write(|w| unsafe { w.fc0_ref_khz().bits(XTAL_FREQ_HZ / 1000) }); // Corresponds to a 1ms test time, which seems to give good enough accuracy clocks - .fc0_interval + .fc0_interval() .write(|w| unsafe { w.fc0_interval().bits(10) }); // We don't really care about the min/max, so these are just set to min/max values. clocks - .fc0_min_khz + .fc0_min_khz() .write(|w| unsafe { w.fc0_min_khz().bits(0) }); clocks - .fc0_max_khz + .fc0_max_khz() .write(|w| unsafe { w.fc0_max_khz().bits(0xffffffff) }); // To measure rosc directly we use the value 0x03. - clocks.fc0_src.write(|w| unsafe { w.fc0_src().bits(0x03) }); + clocks + .fc0_src() + .write(|w| unsafe { w.fc0_src().bits(0x03) }); // Wait until the measurement is ready - while clocks.fc0_status.read().done().bit_is_clear() { + while clocks.fc0_status().read().done().bit_is_clear() { cortex_m::asm::nop(); } - let speed_hz = clocks.fc0_result.read().khz().bits() * 1000; + let speed_hz = clocks.fc0_result().read().khz().bits() * 1000; speed_hz.Hz() } @@ -217,26 +219,26 @@ fn find_target_rosc_frequency( fn set_rosc_div(rosc: &ROSC, div: u32) { assert!(div <= 32); let div = if div == 32 { 0 } else { div }; - rosc.div.write(|w| unsafe { w.bits(0xaa0 + div) }); + rosc.div().write(|w| unsafe { w.bits(0xaa0 + div) }); } fn reset_rosc_operating_frequency(rosc: &ROSC) { // Set divider to 1 set_rosc_div(rosc, 1); - rosc.ctrl.write(|w| w.freq_range().low()); + rosc.ctrl().write(|w| w.freq_range().low()); write_freq_stages(rosc, &[0, 0, 0, 0, 0, 0, 0, 0]); } fn read_freq_stage(rosc: &ROSC, stage: u8) -> u8 { match stage { - 0 => rosc.freqa.read().ds0().bits(), - 1 => rosc.freqa.read().ds1().bits(), - 2 => rosc.freqa.read().ds2().bits(), - 3 => rosc.freqa.read().ds3().bits(), - 4 => rosc.freqb.read().ds4().bits(), - 5 => rosc.freqb.read().ds5().bits(), - 6 => rosc.freqb.read().ds6().bits(), - 7 => rosc.freqb.read().ds7().bits(), + 0 => rosc.freqa().read().ds0().bits(), + 1 => rosc.freqa().read().ds1().bits(), + 2 => rosc.freqa().read().ds2().bits(), + 3 => rosc.freqa().read().ds3().bits(), + 4 => rosc.freqb().read().ds4().bits(), + 5 => rosc.freqb().read().ds5().bits(), + 6 => rosc.freqb().read().ds6().bits(), + 7 => rosc.freqb().read().ds7().bits(), _ => panic!("invalid frequency drive strength stage"), } } @@ -249,7 +251,7 @@ fn increase_drive_strength(rosc: &ROSC) -> bool { for (stage_index, stage) in stages.iter_mut().enumerate() { *stage = read_freq_stage(rosc, stage_index as u8) } - let num_stages_at_drive_level = match rosc.ctrl.read().freq_range().variant() { + let num_stages_at_drive_level = match rosc.ctrl().read().freq_range().variant() { Some(FREQ_RANGE_A::LOW) => 8, Some(FREQ_RANGE_A::MEDIUM) => 6, Some(FREQ_RANGE_A::HIGH) => 4, @@ -293,31 +295,31 @@ fn write_freq_stages(rosc: &ROSC, stages: &[u8; 8]) { for (stage_index, stage) in stages.iter().enumerate().skip(4) { freq_b |= ((*stage & 0x07) as u32) << ((stage_index - 4) * 4); } - rosc.freqa.write(|w| unsafe { w.bits(freq_a) }); - rosc.freqb.write(|w| unsafe { w.bits(freq_b) }); + rosc.freqa().write(|w| unsafe { w.bits(freq_a) }); + rosc.freqb().write(|w| unsafe { w.bits(freq_b) }); } /// Increase the rosc frequency range up to the next step. /// Returns a boolean to indicate whether the frequency was increased. fn increase_freq_range(rosc: &ROSC) -> bool { - match rosc.ctrl.read().freq_range().variant() { + match rosc.ctrl().read().freq_range().variant() { None => { // Initial unset frequency range, move to LOW frequency range - rosc.ctrl.write(|w| w.freq_range().low()); + rosc.ctrl().write(|w| w.freq_range().low()); // Reset all the drive strength bits. write_freq_stages(rosc, &[0, 0, 0, 0, 0, 0, 0, 0]); true } Some(FREQ_RANGE_A::LOW) => { // Transition from LOW to MEDIUM frequency range - rosc.ctrl.write(|w| w.freq_range().medium()); + rosc.ctrl().write(|w| w.freq_range().medium()); // Reset all the drive strength bits. write_freq_stages(rosc, &[0, 0, 0, 0, 0, 0, 0, 0]); true } Some(FREQ_RANGE_A::MEDIUM) => { // Transition from MEDIUM to HIGH frequency range - rosc.ctrl.write(|w| w.freq_range().high()); + rosc.ctrl().write(|w| w.freq_range().high()); // Reset all the drive strength bits. write_freq_stages(rosc, &[0, 0, 0, 0, 0, 0, 0, 0]); true diff --git a/rp2040-hal/src/adc.rs b/rp2040-hal/src/adc.rs index a875ae881..3894bcc41 100644 --- a/rp2040-hal/src/adc.rs +++ b/rp2040-hal/src/adc.rs @@ -240,10 +240,10 @@ impl Adc { device.reset_bring_up(resets); // Enable adc - device.cs.write(|w| w.en().set_bit()); + device.cs().write(|w| w.en().set_bit()); // Wait for adc ready - while !device.cs.read().ready().bit_is_set() {} + while !device.cs().read().ready().bit_is_set() {} Self { device } } @@ -255,7 +255,7 @@ impl Adc { /// Read single pub fn read_single(&self) -> u16 { - self.device.result.read().result().bits() + self.device.result().read().result().bits() } /// Enable temperature sensor, returns a channel to use. @@ -276,7 +276,7 @@ impl Adc { /// If the sensor has already been enabled, this method returns `None`. pub fn take_temp_sensor(&mut self) -> Option { let mut disabled = false; - self.device.cs.modify(|r, w| { + self.device.cs().modify(|r, w| { disabled = r.ts_en().bit_is_clear(); // if bit was already set, this is a nop w.ts_en().set_bit() @@ -286,7 +286,7 @@ impl Adc { /// Disable temperature sensor, consumes channel pub fn disable_temp_sensor(&mut self, _: TempSense) { - self.device.cs.modify(|_, w| w.ts_en().clear_bit()); + self.device.cs().modify(|_, w| w.ts_en().clear_bit()); } /// Start configuring free-running mode, and set up the FIFO @@ -305,19 +305,19 @@ impl Adc { } fn inner_read(&mut self, chan: u8) -> u16 { - while !self.device.cs.read().ready().bit_is_set() { + while !self.device.cs().read().ready().bit_is_set() { cortex_m::asm::nop(); } self.device - .cs + .cs() .modify(|_, w| unsafe { w.ainsel().bits(chan).start_once().set_bit() }); - while !self.device.cs.read().ready().bit_is_set() { + while !self.device.cs().read().ready().bit_is_set() { cortex_m::asm::nop(); } - self.device.result.read().result().bits() + self.device.result().read().result().bits() } } @@ -409,7 +409,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { pub fn clock_divider(self, int: u16, frac: u8) -> Self { self.adc .device - .div + .div() .modify(|_, w| unsafe { w.int().bits(int).frac().bits(frac) }); self } @@ -423,7 +423,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { pub fn set_channel>(self, _pin: &mut PIN) -> Self { self.adc .device - .cs + .cs() .modify(|_, w| unsafe { w.ainsel().bits(PIN::channel()) }); self } @@ -438,7 +438,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { let RoundRobin(bits) = selected_channels.into(); self.adc .device - .cs + .cs() .modify(|_, w| unsafe { w.rrobin().bits(bits) }); self } @@ -447,10 +447,10 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { /// /// It will be triggered whenever there are at least `threshold` samples waiting in the FIFO. pub fn enable_interrupt(self, threshold: u8) -> Self { - self.adc.device.inte.modify(|_, w| w.fifo().set_bit()); + self.adc.device.inte().modify(|_, w| w.fifo().set_bit()); self.adc .device - .fcs + .fcs() .modify(|_, w| unsafe { w.thresh().bits(threshold) }); self } @@ -462,7 +462,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { /// /// When this method has been called, the resulting fifo's `read` method returns u8. pub fn shift_8bit(self) -> AdcFifoBuilder<'a, u8> { - self.adc.device.fcs.modify(|_, w| w.shift().set_bit()); + self.adc.device.fcs().modify(|_, w| w.shift().set_bit()); AdcFifoBuilder { adc: self.adc, marker: PhantomData, @@ -479,7 +479,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { pub fn enable_dma(self) -> Self { self.adc .device - .fcs + .fcs() .modify(|_, w| unsafe { w.dreq_en().set_bit().thresh().bits(1) }); self } @@ -492,8 +492,8 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { /// /// Note: if you plan to use the FIFO for DMA transfers, [`AdcFifoBuilder::prepare`] instead. pub fn start(self) -> AdcFifo<'a, Word> { - self.adc.device.fcs.modify(|_, w| w.en().set_bit()); - self.adc.device.cs.modify(|_, w| w.start_many().set_bit()); + self.adc.device.fcs().modify(|_, w| w.en().set_bit()); + self.adc.device.cs().modify(|_, w| w.start_many().set_bit()); AdcFifo { adc: self.adc, marker: PhantomData, @@ -506,7 +506,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { /// /// Use [`AdcFifo::resume`] to start conversion. pub fn prepare(self) -> AdcFifo<'a, Word> { - self.adc.device.fcs.modify(|_, w| w.en().set_bit()); + self.adc.device.fcs().modify(|_, w| w.en().set_bit()); AdcFifo { adc: self.adc, marker: PhantomData, @@ -527,7 +527,7 @@ impl<'a, Word> AdcFifo<'a, Word> { #[allow(clippy::len_without_is_empty)] /// Returns the number of elements currently in the fifo pub fn len(&mut self) -> u8 { - self.adc.device.fcs.read().level().bits() + self.adc.device.fcs().read().level().bits() } /// Check if there was a fifo overrun @@ -536,11 +536,11 @@ impl<'a, Word> AdcFifo<'a, Word> { /// /// This function also clears the `over` bit if it was set. pub fn is_over(&mut self) -> bool { - let over = self.adc.device.fcs.read().over().bit(); + let over = self.adc.device.fcs().read().over().bit(); if over { self.adc .device - .fcs + .fcs() .modify(|_, w| w.over().clear_bit_by_one()); } over @@ -552,11 +552,11 @@ impl<'a, Word> AdcFifo<'a, Word> { /// /// This function also clears the `under` bit if it was set. pub fn is_under(&mut self) -> bool { - let under = self.adc.device.fcs.read().under().bit(); + let under = self.adc.device.fcs().read().under().bit(); if under { self.adc .device - .fcs + .fcs() .modify(|_, w| w.under().clear_bit_by_one()); } under @@ -601,7 +601,7 @@ impl<'a, Word> AdcFifo<'a, Word> { /// /// There may be existing samples in the FIFO though, or a conversion may still be in progress. pub fn is_paused(&mut self) -> bool { - self.adc.device.cs.read().start_many().bit_is_clear() + self.adc.device.cs().read().start_many().bit_is_clear() } /// Temporarily pause conversion @@ -613,7 +613,10 @@ impl<'a, Word> AdcFifo<'a, Word> { /// Note that existing samples can still be read from the FIFO, and can possibly /// cause interrupts and DMA transfer progress until the FIFO is emptied. pub fn pause(&mut self) { - self.adc.device.cs.modify(|_, w| w.start_many().clear_bit()); + self.adc + .device + .cs() + .modify(|_, w| w.start_many().clear_bit()); } /// Resume conversion after it was paused @@ -624,7 +627,7 @@ impl<'a, Word> AdcFifo<'a, Word> { /// /// Calling this method when conversion is already running has no effect. pub fn resume(&mut self) { - self.adc.device.cs.modify(|_, w| w.start_many().set_bit()); + self.adc.device.cs().modify(|_, w| w.start_many().set_bit()); } /// Clears the FIFO, removing all values @@ -648,29 +651,29 @@ impl<'a, Word> AdcFifo<'a, Word> { // stop capture and clear channel selection self.adc .device - .cs + .cs() .modify(|_, w| unsafe { w.start_many().clear_bit().rrobin().bits(0).ainsel().bits(0) }); // disable fifo interrupt - self.adc.device.inte.modify(|_, w| w.fifo().clear_bit()); + self.adc.device.inte().modify(|_, w| w.fifo().clear_bit()); // Wait for one more conversion, then drain remaining values from fifo. // This MUST happen *after* the interrupt is disabled, but // *before* `thresh` is modified. Otherwise if `INTS.FIFO = 1`, // the interrupt will be fired one more time. // The only way to clear `INTS.FIFO` is for `FCS.LEVEL` to go // below `FCS.THRESH`, which requires `FCS.THRESH` not to be 0. - while self.adc.device.cs.read().ready().bit_is_clear() {} + while self.adc.device.cs().read().ready().bit_is_clear() {} while self.len() > 0 { self.read_from_fifo(); } // disable fifo, reset threshold to 0 and disable DMA self.adc .device - .fcs + .fcs() .modify(|_, w| unsafe { w.en().clear_bit().thresh().bits(0).dreq_en().clear_bit() }); // reset clock divider self.adc .device - .div + .div() .modify(|_, w| unsafe { w.int().bits(0).frac().bits(0) }); self.adc } @@ -679,11 +682,11 @@ impl<'a, Word> AdcFifo<'a, Word> { /// /// Interrupts must be enabled ([`AdcFifoBuilder::enable_interrupt`]), or else this methods blocks forever. pub fn wait_for_interrupt(&mut self) { - while self.adc.device.intr.read().fifo().bit_is_clear() {} + while self.adc.device.intr().read().fifo().bit_is_clear() {} } fn read_from_fifo(&mut self) -> u16 { - self.adc.device.fifo.read().val().bits() + self.adc.device.fifo().read().val().bits() } /// Returns a read-target for initiating DMA transfers @@ -691,7 +694,7 @@ impl<'a, Word> AdcFifo<'a, Word> { /// The [`DmaReadTarget`] returned by this function can be used to initiate DMA transfers /// reading from the ADC. pub fn dma_read_target(&self) -> DmaReadTarget { - DmaReadTarget(&self.adc.device.fifo as *const _ as u32, PhantomData) + DmaReadTarget(self.adc.device.fifo() as *const _ as u32, PhantomData) } } diff --git a/rp2040-hal/src/clocks/macros.rs b/rp2040-hal/src/clocks/macros.rs index e387a5258..12bb499f4 100644 --- a/rp2040-hal/src/clocks/macros.rs +++ b/rp2040-hal/src/clocks/macros.rs @@ -28,7 +28,7 @@ macro_rules! clocks { pub fn new(mut clocks_block: CLOCKS) -> Self { // Disable resus that may be enabled from previous software unsafe { - clocks_block.clk_sys_resus_ctrl.write_with_zero(|w| w); + clocks_block.clk_sys_resus_ctrl().write_with_zero(|w| w); } let shared_clocks = ShareableClocks::new(&mut clocks_block); @@ -91,7 +91,7 @@ macro_rules! clock { fn await_select(&self, clock_token: &ChangingClockToken) -> nb::Result<(), Infallible> { let shared_dev = unsafe { self.shared_dev.get() }; - let selected = shared_dev.[<$reg _selected>].read().bits(); + let selected = shared_dev.[<$reg _selected>]().read().bits(); if selected != 1 << clock_token.clock_nr { return Err(nb::Error::WouldBlock); } @@ -136,7 +136,7 @@ macro_rules! clock { pub fn reset_source_await(&mut self) -> nb::Result<(), Infallible> { let shared_dev = unsafe { self.shared_dev.get() }; - shared_dev.[<$reg _ctrl>].modify(|_, w| { + shared_dev.[<$reg _ctrl>]().modify(|_, w| { w.src().variant(self.get_default_clock_source()) }); @@ -149,7 +149,7 @@ macro_rules! clock { fn set_src>(&mut self, src: &S)-> ChangingClockToken<$name> { let shared_dev = unsafe { self.shared_dev.get() }; - shared_dev.[<$reg _ctrl>].modify(|_,w| { + shared_dev.[<$reg _ctrl>]().modify(|_,w| { w.src().variant(src.variant().unwrap_src()) }); @@ -160,7 +160,7 @@ macro_rules! clock { } fn set_self_aux_src(&mut self) -> ChangingClockToken<$name> { - unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| { + unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| { w.src().variant(self.get_aux_source()) }); @@ -269,13 +269,13 @@ macro_rules! divisable_clock { $crate::paste::paste! { impl ClockDivision for $name { fn set_div(&mut self, div: u32) { - unsafe { self.shared_dev.get() }.[<$reg _div>].modify(|_, w| unsafe { + unsafe { self.shared_dev.get() }.[<$reg _div>]().modify(|_, w| unsafe { w.bits(div); w }); } fn get_div(&self) -> u32 { - unsafe { self.shared_dev.get() }.[<$reg _div>].read().bits() + unsafe { self.shared_dev.get() }.[<$reg _div>]().read().bits() } } } @@ -302,21 +302,21 @@ macro_rules! stoppable_clock { impl StoppableClock for $name { /// Enable the clock fn enable(&mut self) { - unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| { + unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| { w.enable().set_bit() }); } /// Disable the clock cleanly fn disable(&mut self) { - unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| { + unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| { w.enable().clear_bit() }); } /// Disable the clock asynchronously fn kill(&mut self) { - unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| { + unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| { w.kill().set_bit() }); } @@ -412,7 +412,7 @@ macro_rules! base_clock { fn set_aux>(&mut self, src: &S) { let shared_dev = unsafe { self.shared_dev.get() }; - shared_dev.[<$reg _ctrl>].modify(|_,w| { + shared_dev.[<$reg _ctrl>]().modify(|_,w| { w.auxsrc().variant(src.variant().unwrap_aux()) }); } diff --git a/rp2040-hal/src/clocks/mod.rs b/rp2040-hal/src/clocks/mod.rs index 2fdd7353d..00e4fd0e0 100644 --- a/rp2040-hal/src/clocks/mod.rs +++ b/rp2040-hal/src/clocks/mod.rs @@ -459,26 +459,26 @@ impl ClocksManager { /// Configure the clocks staying ON during deep-sleep. pub fn configure_sleep_enable(&mut self, clock_gate: ClockGate) { self.clocks - .sleep_en0 + .sleep_en0() .write(|w| unsafe { w.bits(clock_gate.0 as u32) }); self.clocks - .sleep_en1 + .sleep_en1() .write(|w| unsafe { w.bits((clock_gate.0 >> 32) as u32) }); } /// Read the clock gate configuration while the device is in its (deep) sleep state. pub fn sleep_enable(&self) -> ClockGate { ClockGate( - (u64::from(self.clocks.sleep_en1.read().bits()) << 32) - | u64::from(self.clocks.sleep_en0.read().bits()), + (u64::from(self.clocks.sleep_en1().read().bits()) << 32) + | u64::from(self.clocks.sleep_en0().read().bits()), ) } /// Read the clock gate configuration while the device is in its wake state. pub fn wake_enable(&self) -> ClockGate { ClockGate( - (u64::from(self.clocks.wake_en1.read().bits()) << 32) - | u64::from(self.clocks.wake_en0.read().bits()), + (u64::from(self.clocks.wake_en1().read().bits()) << 32) + | u64::from(self.clocks.wake_en0().read().bits()), ) } diff --git a/rp2040-hal/src/dma/bidirectional.rs b/rp2040-hal/src/dma/bidirectional.rs index 53fd58a30..c54c44fbe 100644 --- a/rp2040-hal/src/dma/bidirectional.rs +++ b/rp2040-hal/src/dma/bidirectional.rs @@ -141,8 +141,8 @@ where /// Check if the transfer is completed pub fn is_done(&self) -> bool { - let a = self.ch.1.ch().ch_ctrl_trig.read().busy().bit_is_set(); - let b = self.ch.0.ch().ch_ctrl_trig.read().busy().bit_is_set(); + let a = self.ch.1.ch().ch_ctrl_trig().read().busy().bit_is_set(); + let b = self.ch.0.ch().ch_ctrl_trig().read().busy().bit_is_set(); !(a | b) } diff --git a/rp2040-hal/src/dma/double_buffer.rs b/rp2040-hal/src/dma/double_buffer.rs index 2b8885ae0..075140f21 100644 --- a/rp2040-hal/src/dma/double_buffer.rs +++ b/rp2040-hal/src/dma/double_buffer.rs @@ -130,9 +130,9 @@ where /// Check if the transfer is completed pub fn is_done(&self) -> bool { if self.second_ch { - !self.ch.1.ch().ch_ctrl_trig.read().busy().bit_is_set() + !self.ch.1.ch().ch_ctrl_trig().read().busy().bit_is_set() } else { - !self.ch.0.ch().ch_ctrl_trig.read().busy().bit_is_set() + !self.ch.0.ch().ch_ctrl_trig().read().busy().bit_is_set() } } } diff --git a/rp2040-hal/src/dma/mod.rs b/rp2040-hal/src/dma/mod.rs index b941f0c18..2047012cf 100644 --- a/rp2040-hal/src/dma/mod.rs +++ b/rp2040-hal/src/dma/mod.rs @@ -143,7 +143,7 @@ trait ChannelRegs { impl ChannelRegs for Channel { unsafe fn ptr() -> *const pac::dma::CH { - &(*pac::DMA::ptr()).ch[CH::id() as usize] as *const _ + (*pac::DMA::ptr()).ch(CH::id() as usize) } fn regs(&self) -> &pac::dma::CH { diff --git a/rp2040-hal/src/dma/single_buffer.rs b/rp2040-hal/src/dma/single_buffer.rs index d7f5c4310..161260e8f 100644 --- a/rp2040-hal/src/dma/single_buffer.rs +++ b/rp2040-hal/src/dma/single_buffer.rs @@ -99,7 +99,7 @@ where /// Check if the transfer has completed. pub fn is_done(&self) -> bool { - !self.ch.ch().ch_ctrl_trig.read().busy().bit_is_set() + !self.ch.ch().ch_ctrl_trig().read().busy().bit_is_set() } /// Block until the transfer is complete, returning the channel and targets diff --git a/rp2040-hal/src/dma/single_channel.rs b/rp2040-hal/src/dma/single_channel.rs index 35cec3f21..1b016eb71 100644 --- a/rp2040-hal/src/dma/single_channel.rs +++ b/rp2040-hal/src/dma/single_channel.rs @@ -27,7 +27,7 @@ pub trait SingleChannel: Sealed { fn enable_irq0(&mut self) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_set((*DMA::ptr()).inte0.as_ptr(), 1 << self.id()); + write_bitmask_set((*DMA::ptr()).inte0().as_ptr(), 1 << self.id()); } } @@ -41,7 +41,7 @@ pub trait SingleChannel: Sealed { fn disable_irq0(&mut self) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_clear((*DMA::ptr()).inte0.as_ptr(), 1 << self.id()); + write_bitmask_clear((*DMA::ptr()).inte0().as_ptr(), 1 << self.id()); } } @@ -50,10 +50,10 @@ pub trait SingleChannel: Sealed { // Safety: The following is race-free as we only ever clear the bit for this channel. // Nobody else modifies that bit. unsafe { - let status = (*DMA::ptr()).ints0.read().bits(); + let status = (*DMA::ptr()).ints0().read().bits(); if (status & (1 << self.id())) != 0 { // Clear the interrupt. - (*DMA::ptr()).ints0.write(|w| w.bits(1 << self.id())); + (*DMA::ptr()).ints0().write(|w| w.bits(1 << self.id())); true } else { false @@ -71,7 +71,7 @@ pub trait SingleChannel: Sealed { fn enable_irq1(&mut self) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_set((*DMA::ptr()).inte1.as_ptr(), 1 << self.id()); + write_bitmask_set((*DMA::ptr()).inte1().as_ptr(), 1 << self.id()); } } @@ -85,7 +85,7 @@ pub trait SingleChannel: Sealed { fn disable_irq1(&mut self) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_clear((*DMA::ptr()).inte1.as_ptr(), 1 << self.id()); + write_bitmask_clear((*DMA::ptr()).inte1().as_ptr(), 1 << self.id()); } } @@ -94,10 +94,10 @@ pub trait SingleChannel: Sealed { // Safety: The following is race-free as we only ever clear the bit for this channel. // Nobody else modifies that bit. unsafe { - let status = (*DMA::ptr()).ints1.read().bits(); + let status = (*DMA::ptr()).ints1().read().bits(); if (status & (1 << self.id())) != 0 { // Clear the interrupt. - (*DMA::ptr()).ints1.write(|w| w.bits(1 << self.id())); + (*DMA::ptr()).ints1().write(|w| w.bits(1 << self.id())); true } else { false @@ -199,7 +199,7 @@ impl ChannelConfig for CH { Pace::PreferSink => TO::tx_treq().or_else(FROM::rx_treq).unwrap_or(TREQ_UNPACED), }; let len = u32::min(src_count, dest_count); - self.ch().ch_al1_ctrl.write(|w| unsafe { + self.ch().ch_al1_ctrl().write(|w| unsafe { w.data_size().bits(mem::size_of::() as u8 >> 1); w.incr_read().bit(src_incr); w.incr_write().bit(dest_incr); @@ -209,14 +209,14 @@ impl ChannelConfig for CH { w.en().bit(true); w }); - self.ch().ch_read_addr.write(|w| unsafe { w.bits(src) }); - self.ch().ch_trans_count.write(|w| unsafe { w.bits(len) }); + self.ch().ch_read_addr().write(|w| unsafe { w.bits(src) }); + self.ch().ch_trans_count().write(|w| unsafe { w.bits(len) }); if start { self.ch() - .ch_al2_write_addr_trig + .ch_al2_write_addr_trig() .write(|w| unsafe { w.bits(dest) }); } else { - self.ch().ch_write_addr.write(|w| unsafe { w.bits(dest) }); + self.ch().ch_write_addr().write(|w| unsafe { w.bits(dest) }); } } @@ -228,14 +228,14 @@ impl ChannelConfig for CH { // succession, yet we did not notice, as the situation is not distinguishable from one // where the second channel was not started at all. - self.ch().ch_al1_ctrl.modify(|_, w| unsafe { + self.ch().ch_al1_ctrl().modify(|_, w| unsafe { w.chain_to().bits(other.id()); w.en().clear_bit(); w }); - if self.ch().ch_al1_ctrl.read().busy().bit_is_set() { + if self.ch().ch_al1_ctrl().read().busy().bit_is_set() { // This channel is still active, so just continue. - self.ch().ch_al1_ctrl.modify(|_, w| w.en().set_bit()); + self.ch().ch_al1_ctrl().modify(|_, w| w.en().set_bit()); } else { // This channel has already finished, so just start the other channel directly. other.start(); @@ -246,7 +246,7 @@ impl ChannelConfig for CH { // Safety: The write does not interfere with any other writes, it only affects this // channel. unsafe { &*crate::pac::DMA::ptr() } - .multi_chan_trigger + .multi_chan_trigger() .write(|w| unsafe { w.bits(1 << self.id()) }); } @@ -255,7 +255,7 @@ impl ChannelConfig for CH { // channel and other (which we have an exclusive borrow of). let channel_flags = 1 << self.id() | 1 << other.id(); unsafe { &*crate::pac::DMA::ptr() } - .multi_chan_trigger + .multi_chan_trigger() .write(|w| unsafe { w.bits(channel_flags) }); } } diff --git a/rp2040-hal/src/float/div.rs b/rp2040-hal/src/float/div.rs index 42a8cefd3..af74545d3 100644 --- a/rp2040-hal/src/float/div.rs +++ b/rp2040-hal/src/float/div.rs @@ -19,13 +19,13 @@ where // The Pico SDK ensures this by using a 6 cycle push and two 1 cycle reads. // Since we can't be sure the Rust implementation will optimize to the same, // just use an explicit wait. - while !sio.div_csr.read().ready().bit() {} + while !sio.div_csr().read().ready().bit() {} // Read the quotient last, since that's what clears the dirty flag - let dividend = sio.div_udividend.read().bits(); - let divisor = sio.div_udivisor.read().bits(); - let remainder = sio.div_remainder.read().bits(); - let quotient = sio.div_quotient.read().bits(); + let dividend = sio.div_udividend().read().bits(); + let divisor = sio.div_udivisor().read().bits(); + let remainder = sio.div_remainder().read().bits(); + let quotient = sio.div_quotient().read().bits(); // If we get interrupted here (before a write sets the DIRTY flag) its fine, since // we have the full state, so the interruptor doesn't have to restore it. Once the @@ -36,19 +36,19 @@ where // If we are interrupted here, then the interruptor will start an incorrect calculation // using a wrong divisor, but we'll restore the divisor and result ourselves correctly. // This sets DIRTY, so any interruptor will save the state. - sio.div_udividend.write(|w| unsafe { w.bits(dividend) }); + sio.div_udividend().write(|w| unsafe { w.bits(dividend) }); // If we are interrupted here, the the interruptor may start the calculation using // incorrectly signed inputs, but we'll restore the result ourselves. // This sets DIRTY, so any interruptor will save the state. - sio.div_udivisor.write(|w| unsafe { w.bits(divisor) }); + sio.div_udivisor().write(|w| unsafe { w.bits(divisor) }); // If we are interrupted here, the interruptor will have restored everything but the // quotient may be wrongly signed. If the calculation started by the above writes is // still ongoing it is stopped, so it won't replace the result we're restoring. // DIRTY and READY set, but only DIRTY matters to make the interruptor save the state. - sio.div_remainder.write(|w| unsafe { w.bits(remainder) }); + sio.div_remainder().write(|w| unsafe { w.bits(remainder) }); // State fully restored after the quotient write. This sets both DIRTY and READY, so // whatever we may have interrupted can read the result. - sio.div_quotient.write(|w| unsafe { w.bits(quotient) }); + sio.div_quotient().write(|w| unsafe { w.bits(quotient) }); result } @@ -58,7 +58,7 @@ where F: FnOnce() -> R, { let sio = unsafe { &(*pac::SIO::ptr()) }; - if !sio.div_csr.read().dirty().bit() { + if !sio.div_csr().read().dirty().bit() { // Not dirty, so nothing is waiting for the calculation. So we can just // issue it directly without a save/restore. f() diff --git a/rp2040-hal/src/gpio/mod.rs b/rp2040-hal/src/gpio/mod.rs index cbf46839d..8364a35ca 100644 --- a/rp2040-hal/src/gpio/mod.rs +++ b/rp2040-hal/src/gpio/mod.rs @@ -1045,11 +1045,11 @@ macro_rules! gpio { // SAFETY: this function owns the whole bank that will be affected. let sio = unsafe { &*$crate::pac::SIO::PTR }; if DynBankId::$bank == DynBankId::Bank0 { - sio.gpio_oe.reset(); - sio.gpio_out.reset(); + sio.gpio_oe().reset(); + sio.gpio_out().reset(); } else { - sio.gpio_hi_oe.reset(); - sio.gpio_hi_out.reset(); + sio.gpio_hi_oe().reset(); + sio.gpio_hi_out().reset(); } } diff --git a/rp2040-hal/src/gpio/pin/pin_sealed.rs b/rp2040-hal/src/gpio/pin/pin_sealed.rs index 44a6078d0..951931f7c 100644 --- a/rp2040-hal/src/gpio/pin/pin_sealed.rs +++ b/rp2040-hal/src/gpio/pin/pin_sealed.rs @@ -43,8 +43,8 @@ macro_rules! accessor_fns { unsafe { let sio = &*$crate::pac::SIO::PTR; match pin.bank { - DynBankId::Bank0 => &sio.[], - DynBankId::Qspi => core::mem::transmute(&sio.[]), + DynBankId::Bank0 => &sio.[](), + DynBankId::Qspi => core::mem::transmute(&sio.[]()), } } } @@ -57,17 +57,17 @@ macro_rules! accessor_fns { match pin.bank { DynBankId::Bank0 => { let gpio = unsafe { &*$crate::pac::IO_BANK0::PTR }; - &gpio.gpio[usize::from(pin.num)].[] + &gpio.gpio(usize::from(pin.num)).[]() } DynBankId::Qspi => unsafe { let qspi = &*$crate::pac::IO_QSPI::PTR; match pin.num { - 0 => core::mem::transmute(&qspi.gpio_qspisclk().[]), - 1 => core::mem::transmute(&qspi.gpio_qspiss().[]), - 2 => core::mem::transmute(&qspi.gpio_qspisd0().[]), - 3 => core::mem::transmute(&qspi.gpio_qspisd1().[]), - 4 => core::mem::transmute(&qspi.gpio_qspisd2().[]), - 5 => core::mem::transmute(&qspi.gpio_qspisd3().[]), + 0 => core::mem::transmute(&qspi.gpio_qspisclk().[]()), + 1 => core::mem::transmute(&qspi.gpio_qspiss().[]()), + 2 => core::mem::transmute(&qspi.gpio_qspisd0().[]()), + 3 => core::mem::transmute(&qspi.gpio_qspisd1().[]()), + 4 => core::mem::transmute(&qspi.gpio_qspisd2().[]()), + 5 => core::mem::transmute(&qspi.gpio_qspisd3().[]()), _ => unreachable!("Invalid QSPI bank pin number."), } }, @@ -85,15 +85,15 @@ macro_rules! accessor_fns { DynBankId::Bank0 => { let bank = &*$crate::pac::IO_BANK0::PTR; match proc { - CoreId::Core0 => &bank.[][usize::from(index)], - CoreId::Core1 => core::mem::transmute(&bank.[][usize::from(index)]), + CoreId::Core0 => bank.[](usize::from(index)), + CoreId::Core1 => core::mem::transmute(&bank.[](usize::from(index))), } } DynBankId::Qspi => { let bank = &*$crate::pac::IO_QSPI::PTR; match proc { - CoreId::Core0 => core::mem::transmute(&bank.[]), - CoreId::Core1 => core::mem::transmute(&bank.[]), + CoreId::Core0 => core::mem::transmute(&bank.[]()), + CoreId::Core1 => core::mem::transmute(&bank.[]()), } } }; @@ -111,11 +111,11 @@ macro_rules! accessor_fns { let reg = match pin.bank { DynBankId::Bank0 => { let bank = &*$crate::pac::IO_BANK0::PTR; - &bank.[< dormant_wake_ $reg:lower>][usize::from(index)] + bank.[< dormant_wake_ $reg:lower>](usize::from(index)) } DynBankId::Qspi => { let bank = &*$crate::pac::IO_QSPI::PTR; - core::mem::transmute(&bank.[< dormant_wake_ $reg:lower>]) + core::mem::transmute(&bank.[< dormant_wake_ $reg:lower>]()) } }; (reg, usize::from(offset)) @@ -136,17 +136,17 @@ where match pin.bank { DynBankId::Bank0 => { let gpio = unsafe { &*pac::PADS_BANK0::PTR }; - &gpio.gpio[usize::from(pin.num)] + gpio.gpio(usize::from(pin.num)) } DynBankId::Qspi => unsafe { let qspi = &*pac::PADS_QSPI::PTR; match pin.num { - 0 => core::mem::transmute(&qspi.gpio_qspi_sclk), - 1 => core::mem::transmute(&qspi.gpio_qspi_ss), - 2 => core::mem::transmute(&qspi.gpio_qspi_sd0), - 3 => core::mem::transmute(&qspi.gpio_qspi_sd1), - 4 => core::mem::transmute(&qspi.gpio_qspi_sd2), - 5 => core::mem::transmute(&qspi.gpio_qspi_sd3), + 0 => core::mem::transmute(&qspi.gpio_qspi_sclk()), + 1 => core::mem::transmute(&qspi.gpio_qspi_ss()), + 2 => core::mem::transmute(&qspi.gpio_qspi_sd0()), + 3 => core::mem::transmute(&qspi.gpio_qspi_sd1()), + 4 => core::mem::transmute(&qspi.gpio_qspi_sd2()), + 5 => core::mem::transmute(&qspi.gpio_qspi_sd3()), _ => unreachable!("Invalid QSPI bank pin number."), } }, @@ -170,8 +170,8 @@ where unsafe { let syscfg = &*pac::SYSCFG::PTR; match pin.bank { - DynBankId::Bank0 => &syscfg.proc_in_sync_bypass, - DynBankId::Qspi => core::mem::transmute(&syscfg.proc_in_sync_bypass_hi), + DynBankId::Bank0 => syscfg.proc_in_sync_bypass(), + DynBankId::Qspi => core::mem::transmute(&syscfg.proc_in_sync_bypass_hi()), } } } @@ -183,11 +183,11 @@ where let reg = match pin.bank { DynBankId::Bank0 => { let bank = &*pac::IO_BANK0::PTR; - &bank.intr[usize::from(index)] + bank.intr(usize::from(index)) } DynBankId::Qspi => { let bank = &*pac::IO_QSPI::PTR; - core::mem::transmute(&bank.intr) + core::mem::transmute(&bank.intr()) } }; diff --git a/rp2040-hal/src/i2c.rs b/rp2040-hal/src/i2c.rs index a68c44dd6..18d91287f 100644 --- a/rp2040-hal/src/i2c.rs +++ b/rp2040-hal/src/i2c.rs @@ -316,7 +316,7 @@ impl, PINS, Mode> I2C { /// Number of bytes currently in the RX FIFO #[inline] pub fn rx_fifo_used(&self) -> u8 { - self.i2c.ic_rxflr.read().rxflr().bits() + self.i2c.ic_rxflr().read().rxflr().bits() } /// Remaining capacity in the RX FIFO @@ -328,13 +328,13 @@ impl, PINS, Mode> I2C { /// RX FIFO is empty #[inline] pub fn rx_fifo_empty(&self) -> bool { - self.i2c.ic_status.read().rfne().bit_is_clear() + self.i2c.ic_status().read().rfne().bit_is_clear() } /// Number of bytes currently in the TX FIFO #[inline] pub fn tx_fifo_used(&self) -> u8 { - self.i2c.ic_txflr.read().txflr().bits() + self.i2c.ic_txflr().read().txflr().bits() } /// Remaining capacity in the TX FIFO @@ -346,7 +346,7 @@ impl, PINS, Mode> I2C { /// TX FIFO is at capacity #[inline] pub fn tx_fifo_full(&self) -> bool { - self.i2c.ic_status.read().tfnf().bit_is_clear() + self.i2c.ic_status().read().tfnf().bit_is_clear() } } diff --git a/rp2040-hal/src/i2c/controller.rs b/rp2040-hal/src/i2c/controller.rs index fd9bb4b8f..8c1c4d2e9 100644 --- a/rp2040-hal/src/i2c/controller.rs +++ b/rp2040-hal/src/i2c/controller.rs @@ -34,10 +34,10 @@ where i2c.reset_bring_down(resets); i2c.reset_bring_up(resets); - i2c.ic_enable.write(|w| w.enable().disabled()); + i2c.ic_enable().write(|w| w.enable().disabled()); // select controller mode & speed - i2c.ic_con.modify(|_, w| { + i2c.ic_con().modify(|_, w| { w.speed().fast(); w.master_mode().enabled(); w.ic_slave_disable().slave_disabled(); @@ -46,8 +46,8 @@ where }); // Clear FIFO threshold - i2c.ic_tx_tl.write(|w| unsafe { w.tx_tl().bits(0) }); - i2c.ic_rx_tl.write(|w| unsafe { w.rx_tl().bits(0) }); + i2c.ic_tx_tl().write(|w| unsafe { w.tx_tl().bits(0) }); + i2c.ic_rx_tl().write(|w| unsafe { w.rx_tl().bits(0) }); let freq_in = system_clock.to_Hz(); @@ -84,33 +84,34 @@ where assert!(sda_tx_hold_count <= lcnt - 2); unsafe { - i2c.ic_fs_scl_hcnt + i2c.ic_fs_scl_hcnt() .write(|w| w.ic_fs_scl_hcnt().bits(hcnt as u16)); - i2c.ic_fs_scl_lcnt + i2c.ic_fs_scl_lcnt() .write(|w| w.ic_fs_scl_lcnt().bits(lcnt as u16)); // spike filter duration - i2c.ic_fs_spklen.write(|w| { + i2c.ic_fs_spklen().write(|w| { let ticks = if lcnt < 16 { 1 } else { (lcnt / 16) as u8 }; w.ic_fs_spklen().bits(ticks) }); // sda hold time - i2c.ic_sda_hold + i2c.ic_sda_hold() .modify(|_r, w| w.ic_sda_tx_hold().bits(sda_tx_hold_count as u16)); // make TX_EMPTY raise when the tx fifo is not full - i2c.ic_tx_tl.write(|w| w.tx_tl().bits(Self::TX_FIFO_DEPTH)); + i2c.ic_tx_tl() + .write(|w| w.tx_tl().bits(Self::TX_FIFO_DEPTH)); // make RX_FULL raise when the rx fifo contains at least 1 byte - i2c.ic_rx_tl.write(|w| w.rx_tl().bits(0)); + i2c.ic_rx_tl().write(|w| w.rx_tl().bits(0)); // Enable clock stretching. // Will hold clock when: // - receiving and rx fifo is full // - writting and tx fifo is empty - i2c.ic_con + i2c.ic_con() .modify(|_, w| w.rx_fifo_full_hld_ctrl().enabled()); } // Enable I2C block - i2c.ic_enable.write(|w| w.enable().enabled()); + i2c.ic_enable().write(|w| w.enable().enabled()); Self { i2c, @@ -143,25 +144,27 @@ impl, PINS> I2C { fn setup(&mut self, addr: A) -> Result<(), Error> { addr.is_valid()?; - self.i2c.ic_enable.write(|w| w.enable().disabled()); + self.i2c.ic_enable().write(|w| w.enable().disabled()); self.i2c - .ic_con + .ic_con() .modify(|_, w| w.ic_10bitaddr_master().variant(A::BIT_ADDR_M)); let addr = addr.into(); - self.i2c.ic_tar.write(|w| unsafe { w.ic_tar().bits(addr) }); - self.i2c.ic_enable.write(|w| w.enable().enabled()); + self.i2c + .ic_tar() + .write(|w| unsafe { w.ic_tar().bits(addr) }); + self.i2c.ic_enable().write(|w| w.enable().enabled()); Ok(()) } #[inline] fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> { - let abort_reason = self.i2c.ic_tx_abrt_source.read().bits(); + let abort_reason = self.i2c.ic_tx_abrt_source().read().bits(); if abort_reason != 0 { // Note clearing the abort flag also clears the reason, and // this instance of flag is clear-on-read! Note also the // IC_CLR_TX_ABRT register always reads as 0. - self.i2c.ic_clr_tx_abrt.read(); + self.i2c.ic_clr_tx_abrt().read(); Err(Error::Abort(abort_reason)) } else { Ok(()) @@ -180,7 +183,7 @@ impl, PINS> I2C { #[inline] fn poll_tx_empty(&mut self) -> Poll<()> { - if self.i2c.ic_raw_intr_stat.read().tx_empty().is_inactive() { + if self.i2c.ic_raw_intr_stat().read().tx_empty().is_inactive() { Poll::Pending } else { Poll::Ready(()) @@ -189,7 +192,7 @@ impl, PINS> I2C { #[inline] fn poll_stop_deteced(&mut self) -> Poll<()> { - if self.i2c.ic_raw_intr_stat.read().stop_det().is_inactive() { + if self.i2c.ic_raw_intr_stat().read().stop_det().is_inactive() { Poll::Pending } else { Poll::Ready(()) @@ -198,17 +201,17 @@ impl, PINS> I2C { #[inline] fn abort(&mut self) { - self.i2c.ic_enable.modify(|_, w| w.abort().set_bit()); - while self.i2c.ic_enable.read().abort().bit_is_set() { + self.i2c.ic_enable().modify(|_, w| w.abort().set_bit()); + while self.i2c.ic_enable().read().abort().bit_is_set() { cortex_m::asm::nop() } - while self.i2c.ic_raw_intr_stat.read().tx_abrt().bit_is_clear() { + while self.i2c.ic_raw_intr_stat().read().tx_abrt().bit_is_clear() { cortex_m::asm::nop() } // clear tx_abort interrupt flags (might have already been clear by irq) - self.i2c.ic_clr_tx_abrt.read(); + self.i2c.ic_clr_tx_abrt().read(); // clear tx_abrt_source by reading it - self.i2c.ic_tx_abrt_source.read(); + self.i2c.ic_tx_abrt_source().read(); } fn read_internal( @@ -229,9 +232,9 @@ impl, PINS> I2C { let last_byte = i == lastindex; // wait until there is space in the FIFO to write the next byte - while self.i2c.ic_status.read().tfnf().bit_is_clear() {} + while self.i2c.ic_status().read().tfnf().bit_is_clear() {} - self.i2c.ic_data_cmd.write(|w| { + self.i2c.ic_data_cmd().write(|w| { if first_byte { if !first_transaction { w.restart().enable(); @@ -243,11 +246,11 @@ impl, PINS> I2C { w.cmd().read() }); - while self.i2c.ic_rxflr.read().bits() == 0 { + while self.i2c.ic_rxflr().read().bits() == 0 { self.read_and_clear_abort_reason()?; } - *byte = self.i2c.ic_data_cmd.read().dat().bits(); + *byte = self.i2c.ic_data_cmd().read().dat().bits(); } Ok(()) @@ -285,7 +288,7 @@ impl, PINS> I2C { // else enqueue let last = peekable.peek().is_none(); - self.i2c.ic_data_cmd.write(|w| { + self.i2c.ic_data_cmd().write(|w| { if first_byte { if !first_transaction { w.restart().enable(); @@ -308,7 +311,7 @@ impl, PINS> I2C { // If the transaction was aborted or if it completed // successfully wait until the STOP condition has occured. while self.poll_stop_deteced().is_pending() {} - self.i2c.ic_clr_stop_det.read().clr_stop_det(); + self.i2c.ic_clr_stop_det().read().clr_stop_det(); } // Note: the hardware issues a STOP automatically on an abort condition. // Note: the hardware also clears RX FIFO as well as TX on abort diff --git a/rp2040-hal/src/i2c/controller/non_blocking.rs b/rp2040-hal/src/i2c/controller/non_blocking.rs index aa5fcb7b5..ca2006341 100644 --- a/rp2040-hal/src/i2c/controller/non_blocking.rs +++ b/rp2040-hal/src/i2c/controller/non_blocking.rs @@ -20,7 +20,7 @@ macro_rules! impl_async_traits { // Mask all interrupt flags. This does not clear the flags. // Clearing is done by the driver after it wakes up. - i2c.ic_intr_mask.write_with_zero(|w| w); + i2c.ic_intr_mask().write_with_zero(|w| w); } // interrupts are now masked, we can wake the task and return from this handler. Self::waker().wake(); @@ -46,7 +46,7 @@ where #[inline] fn unmask_intr(&mut self, tx_empty: bool) { unsafe { - self.i2c.ic_intr_mask.write_with_zero(|w| { + self.i2c.ic_intr_mask().write_with_zero(|w| { w.m_tx_empty() .bit(tx_empty) .m_rx_full() @@ -61,7 +61,7 @@ where #[inline] fn configure_tx_empty(&mut self, cfg: TxEmptyConfig) { self.i2c - .ic_tx_tl + .ic_tx_tl() // SAFETY: we are within [0; TX_FIFO_DEPTH) .write(|w| unsafe { w.tx_tl().bits(match cfg { @@ -91,7 +91,7 @@ where #[inline] fn poll_rx_not_empty_or_abrt(&mut self) -> Poll> { self.read_and_clear_abort_reason()?; - if self.i2c.ic_raw_intr_stat.read().rx_full().bit_is_set() { + if self.i2c.ic_raw_intr_stat().read().rx_full().bit_is_set() { Poll::Ready(Ok(())) } else { Poll::Pending @@ -101,7 +101,7 @@ where #[inline] fn cancel(&mut self) { unsafe { - self.i2c.ic_intr_mask.write_with_zero(|w| w); + self.i2c.ic_intr_mask().write_with_zero(|w| w); } self.abort(); @@ -134,7 +134,7 @@ where ) .await; - self.i2c.ic_data_cmd.write(|w| { + self.i2c.ic_data_cmd().write(|w| { if first_byte { if !first_transaction { w.restart().enable(); @@ -154,7 +154,7 @@ where ) .await?; - *byte = self.i2c.ic_data_cmd.read().dat().bits(); + *byte = self.i2c.ic_data_cmd().read().dat().bits(); } Ok(()) @@ -192,7 +192,7 @@ where // else enqueue let last = peekable.peek().is_none(); - self.i2c.ic_data_cmd.write(|w| { + self.i2c.ic_data_cmd().write(|w| { if first_byte { if !first_transaction { w.restart().enable(); @@ -227,7 +227,7 @@ where Self::cancel, ) .await; - self.i2c.ic_clr_stop_det.read().clr_stop_det(); + self.i2c.ic_clr_stop_det().read().clr_stop_det(); } // Note: the hardware issues a STOP automatically on an abort condition. // Note: the hardware also clears RX FIFO as well as TX on abort diff --git a/rp2040-hal/src/i2c/peripheral.rs b/rp2040-hal/src/i2c/peripheral.rs index 2b978e267..e67acb91c 100644 --- a/rp2040-hal/src/i2c/peripheral.rs +++ b/rp2040-hal/src/i2c/peripheral.rs @@ -95,15 +95,15 @@ where i2c.reset_bring_down(resets); i2c.reset_bring_up(resets); - i2c.ic_enable.write(|w| w.enable().disabled()); + i2c.ic_enable().write(|w| w.enable().disabled()); // TODO: Validate address? let addr = addr.into(); // SAFETY: Only address by this function. IC_SAR spec filters out bits 15:10. // Any value is valid for the controller. They may not be for the bus itself though. - i2c.ic_sar.write(|w| unsafe { w.ic_sar().bits(addr) }); + i2c.ic_sar().write(|w| unsafe { w.ic_sar().bits(addr) }); // select peripheral mode & speed - i2c.ic_con.modify(|_, w| { + i2c.ic_con().modify(|_, w| { // run in fast mode w.speed().fast(); // setup slave mode @@ -118,10 +118,10 @@ where // Clear FIFO threshold // SAFETY: Only address by this function. The field is 8bit long. 0 is a valid value. - i2c.ic_tx_tl.write(|w| unsafe { w.tx_tl().bits(0) }); - i2c.ic_rx_tl.write(|w| unsafe { w.rx_tl().bits(0) }); + i2c.ic_tx_tl().write(|w| unsafe { w.tx_tl().bits(0) }); + i2c.ic_rx_tl().write(|w| unsafe { w.rx_tl().bits(0) }); - i2c.ic_clr_intr.read(); + i2c.ic_clr_intr().read(); let mut me = Self { i2c, @@ -130,7 +130,7 @@ where }; me.unmask_intr(); // Enable I2C block - me.i2c.ic_enable.write(|w| w.enable().enabled()); + me.i2c.ic_enable().write(|w| w.enable().enabled()); me } @@ -140,7 +140,7 @@ fn unmask_intr(i2c: &RegisterBlock) { // SAFETY: 0 is a valid value meaning all irq masked. // This operation is atomic, `write_with_zero` only writes to the register. unsafe { - i2c.ic_intr_mask.write_with_zero(|w| { + i2c.ic_intr_mask().write_with_zero(|w| { // Only keep these IRQ enabled. w.m_start_det() .disabled() @@ -157,7 +157,7 @@ fn unmask_intr(i2c: &RegisterBlock) { /// SAFETY: Takes a non-mutable reference to RegisterBlock but mutates its `ic_intr_mask` register. unsafe fn mask_intr(i2c: &RegisterBlock) { // 0 is a valid value and means all flag masked. - unsafe { i2c.ic_intr_mask.write_with_zero(|w| w) } + unsafe { i2c.ic_intr_mask().write_with_zero(|w| w) } } impl, PINS> I2C { @@ -174,7 +174,7 @@ impl, PINS> I2C { /// are effectively received by the controller. pub fn write(&mut self, buf: &[u8]) -> usize { // just in case, clears previous tx abort. - self.i2c.ic_clr_tx_abrt.read(); + self.i2c.ic_clr_tx_abrt().read(); let mut sent = 0; for &b in buf.iter() { @@ -183,11 +183,11 @@ impl, PINS> I2C { } // SAFETY: dat field is 8bits long. All values are valid. - self.i2c.ic_data_cmd.write(|w| unsafe { w.dat().bits(b) }); + self.i2c.ic_data_cmd().write(|w| unsafe { w.dat().bits(b) }); sent += 1; } // serve a pending read request - self.i2c.ic_clr_rd_req.read(); + self.i2c.ic_clr_rd_req().read(); sent } @@ -205,18 +205,18 @@ impl, PINS> Iterator for I2C, PINS> I2C { /// Returns the next i2c event if any. pub fn next_event(&mut self) -> Option { - let stat = self.i2c.ic_raw_intr_stat.read(); + let stat = self.i2c.ic_raw_intr_stat().read(); match self.mode.state { State::Idle if stat.start_det().bit_is_set() => { - self.i2c.ic_clr_start_det.read(); + self.i2c.ic_clr_start_det().read(); self.mode.state = State::Active; Some(Event::Start) } @@ -229,7 +229,7 @@ impl, PINS> I2C { // It cannot be due the end of the current request as SCL is held low while waiting // for user input. if stat.stop_det().bit_is_set() { - self.i2c.ic_clr_stop_det.read(); + self.i2c.ic_clr_stop_det().read(); } Some(Event::TransferRead) } @@ -242,15 +242,15 @@ impl, PINS> I2C { State::Write if !self.rx_fifo_empty() => Some(Event::TransferWrite), State::Read | State::Write if stat.restart_det().bit_is_set() => { - self.i2c.ic_clr_restart_det.read(); - self.i2c.ic_clr_start_det.read(); + self.i2c.ic_clr_restart_det().read(); + self.i2c.ic_clr_start_det().read(); self.mode.state = State::Active; Some(Event::Restart) } _ if stat.stop_det().bit_is_set() => { - self.i2c.ic_clr_stop_det.read(); - self.i2c.ic_clr_tx_abrt.read(); + self.i2c.ic_clr_stop_det().read(); + self.i2c.ic_clr_tx_abrt().read(); self.mode.state = State::Idle; Some(Event::Stop) } @@ -299,7 +299,7 @@ where CancellablePollFn::new( self, |me| { - let stat = me.i2c.ic_raw_intr_stat.read(); + let stat = me.i2c.ic_raw_intr_stat().read(); if stat.start_det().bit_is_set() || stat.restart_det().bit_is_set() || stat.stop_det().bit_is_set() diff --git a/rp2040-hal/src/lib.rs b/rp2040-hal/src/lib.rs index bb4b8e26b..5820ada5f 100644 --- a/rp2040-hal/src/lib.rs +++ b/rp2040-hal/src/lib.rs @@ -106,8 +106,10 @@ pub extern crate fugit; pub fn reset() -> ! { unsafe { cortex_m::interrupt::disable(); - (*pac::PSM::PTR).wdsel.write(|w| w.bits(0x0001ffff)); - (*pac::WATCHDOG::PTR).ctrl.write(|w| w.trigger().set_bit()); + (*pac::PSM::PTR).wdsel().write(|w| w.bits(0x0001ffff)); + (*pac::WATCHDOG::PTR) + .ctrl() + .write(|w| w.trigger().set_bit()); #[allow(clippy::empty_loop)] loop {} } @@ -124,8 +126,8 @@ pub fn halt() -> ! { cortex_m::interrupt::disable(); // Stop other core match crate::Sio::core() { - CoreId::Core0 => (*pac::PSM::PTR).frce_off.write(|w| w.proc1().set_bit()), - CoreId::Core1 => (*pac::PSM::PTR).frce_off.write(|w| w.proc0().set_bit()), + CoreId::Core0 => (*pac::PSM::PTR).frce_off().write(|w| w.proc1().set_bit()), + CoreId::Core1 => (*pac::PSM::PTR).frce_off().write(|w| w.proc0().set_bit()), } // Keep current core running, so debugging stays possible loop { diff --git a/rp2040-hal/src/multicore.rs b/rp2040-hal/src/multicore.rs index 30d1fd5fe..a4f1a048e 100644 --- a/rp2040-hal/src/multicore.rs +++ b/rp2040-hal/src/multicore.rs @@ -195,11 +195,11 @@ impl<'p> Core<'p> { // But there does not seem to be any obvious way to check that. A marker flag could be // set from this method and cleared for the wrapper after `entry` returned. But doing // so wouldn't be zero cost. - psm.frce_off.modify(|_, w| w.proc1().set_bit()); - while !psm.frce_off.read().proc1().bit_is_set() { + psm.frce_off().modify(|_, w| w.proc1().set_bit()); + while !psm.frce_off().read().proc1().bit_is_set() { cortex_m::asm::nop(); } - psm.frce_off.modify(|_, w| w.proc1().clear_bit()); + psm.frce_off().modify(|_, w| w.proc1().clear_bit()); // Set up the stack // AAPCS requires in 6.2.1.2 that the stack is 8bytes aligned., we may need to trim the @@ -235,7 +235,7 @@ impl<'p> Core<'p> { // memory caches, and writes happen in-order. compiler_fence(Ordering::Release); - let vector_table = ppb.vtor.read().bits(); + let vector_table = ppb.vtor().read().bits(); // After reset, core 1 is waiting to receive commands over FIFO. // This is the sequence to have it jump to some code. diff --git a/rp2040-hal/src/pio.rs b/rp2040-hal/src/pio.rs index dd9f9da1c..c38e7ddf0 100644 --- a/rp2040-hal/src/pio.rs +++ b/rp2040-hal/src/pio.rs @@ -39,22 +39,22 @@ pub trait PIOExt: Deref + SubsystemReset + Sized + Send let sm0 = UninitStateMachine { block: self.deref(), - sm: &self.deref().sm[0], + sm: self.sm(0), _phantom: core::marker::PhantomData, }; let sm1 = UninitStateMachine { block: self.deref(), - sm: &self.deref().sm[1], + sm: self.sm(1), _phantom: core::marker::PhantomData, }; let sm2 = UninitStateMachine { block: self.deref(), - sm: &self.deref().sm[2], + sm: self.sm(2), _phantom: core::marker::PhantomData, }; let sm3 = UninitStateMachine { block: self.deref(), - sm: &self.deref().sm[3], + sm: self.sm(3), _phantom: core::marker::PhantomData, }; ( @@ -153,7 +153,7 @@ impl PIO

{ /// The PIO has 8 IRQ flags, of which 4 are visible to the host processor. Each bit of `flags` corresponds to one of /// the IRQ flags. pub fn get_irq_raw(&self) -> u8 { - self.pio.irq.read().irq().bits() + self.pio.irq().read().irq().bits() } /// Clear PIO's IRQ flags indicated by the bits. @@ -163,7 +163,7 @@ impl PIO

{ // Safety: PIOExt provides exclusive access to the pio.irq register, this must be preserved to // satisfy Send trait. pub fn clear_irq(&self, flags: u8) { - self.pio.irq.write(|w| unsafe { w.irq().bits(flags) }); + self.pio.irq().write(|w| unsafe { w.irq().bits(flags) }); } /// Force PIO's IRQ flags indicated by the bits. @@ -174,7 +174,7 @@ impl PIO

{ // satisfy Send trait. pub fn force_irq(&self, flags: u8) { self.pio - .irq_force + .irq_force() .write(|w| unsafe { w.irq_force().bits(flags) }); } @@ -243,7 +243,8 @@ impl PIO

{ }) .enumerate() .for_each(|(i, instr)| { - self.pio.instr_mem[i + offset as usize] + self.pio + .instr_mem(i + offset as usize) .write(|w| unsafe { w.instr_mem0().bits(instr) }) }); self.used_instruction_space |= Self::instruction_mask(p.code.len()) << offset; @@ -525,7 +526,7 @@ impl UninitStateMachine { fn set_ctrl_bits(&mut self, bits: u32) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_set((*self.block).ctrl.as_ptr(), bits); + write_bitmask_set((*self.block).ctrl().as_ptr(), bits); } } @@ -533,7 +534,7 @@ impl UninitStateMachine { fn clear_ctrl_bits(&mut self, bits: u32) { // Safety: We only use the atomic alias of the register. unsafe { - write_bitmask_clear((*self.block).ctrl.as_ptr(), bits); + write_bitmask_clear((*self.block).ctrl().as_ptr(), bits); } } @@ -542,7 +543,7 @@ impl UninitStateMachine { // Safety: This is the only write to this register unsafe { self.sm() - .sm_clkdiv + .sm_clkdiv() .write(|w| w.int().bits(int).frac().bits(frac)); } } @@ -603,7 +604,7 @@ impl StateMachine { /// The address of the instruction currently being executed. pub fn instruction_address(&self) -> u32 { // Safety: Read only access without side effect - unsafe { self.sm.sm().sm_addr.read().bits() } + unsafe { self.sm.sm().sm_addr().read().bits() } } #[deprecated(note = "Renamed to exec_instruction")] @@ -626,7 +627,7 @@ impl StateMachine { unsafe { self.sm .sm() - .sm_instr + .sm_instr() .write(|w| w.sm0_instr().bits(instruction)) } } @@ -634,7 +635,7 @@ impl StateMachine { /// Check if the current instruction is stalled. pub fn stalled(&self) -> bool { // Safety: read only access without side effect - unsafe { self.sm.sm().sm_execctrl.read().exec_stalled().bit() } + unsafe { self.sm.sm().sm_execctrl().read().exec_stalled().bit() } } /// Clear both TX and RX FIFOs @@ -642,7 +643,7 @@ impl StateMachine { // Safety: all accesses to these registers are controlled by this instance unsafe { let sm = &self.sm.sm(); - let sm_shiftctrl = &sm.sm_shiftctrl; + let sm_shiftctrl = &sm.sm_shiftctrl(); let mut current = false; // Toggling the FIFO join state clears the fifo sm_shiftctrl.modify(|r, w| { @@ -676,11 +677,11 @@ impl StateMachine { // Safety: all accesses to these registers are controlled by this instance unsafe { let sm = &self.sm.sm(); - let sm_pinctrl = &sm.sm_pinctrl; - let sm_instr = &sm.sm_instr; - let fstat = &self.sm.pio().fstat; + let sm_pinctrl = &sm.sm_pinctrl(); + let sm_instr = &sm.sm_instr(); + let fstat = &self.sm.pio().fstat(); - let operands = if sm.sm_shiftctrl.read().autopull().bit_is_set() { + let operands = if sm.sm_shiftctrl().read().autopull().bit_is_set() { OUT } else { PULL @@ -769,9 +770,9 @@ impl StateMachine { // Safety: all accesses to these registers are controlled by this instance unsafe { let sm = self.sm.sm(); - let sm_pinctrl = &sm.sm_pinctrl; - let sm_execctrl = &sm.sm_execctrl; - let sm_instr = &sm.sm_instr; + let sm_pinctrl = &sm.sm_pinctrl(); + let sm_execctrl = &sm.sm_execctrl(); + let sm_instr = &sm.sm_instr(); // sideset_count is implicitly set to 0 when the set_base/set_count are written (rather // than modified) @@ -821,9 +822,9 @@ impl StateMachine { // Safety: all accesses to these registers are controlled by this instance unsafe { let sm = self.sm.sm(); - let sm_pinctrl = &sm.sm_pinctrl; - let sm_execctrl = &sm.sm_execctrl; - let sm_instr = &sm.sm_instr; + let sm_pinctrl = &sm.sm_pinctrl(); + let sm_execctrl = &sm.sm_execctrl(); + let sm_instr = &sm.sm_instr(); // sideset_count is implicitly set to 0 when the set_base/set_count are written (rather // than modified) @@ -1270,8 +1271,8 @@ impl StateMachine { // Safety: all accesses to these registers are controlled by this instance unsafe { let sm = self.sm.sm(); - let sm_pinctrl = &sm.sm_pinctrl; - let sm_instr = &sm.sm_instr; + let sm_pinctrl = &sm.sm_pinctrl(); + let sm_instr = &sm.sm_instr(); // save exec_ctrl & make side_set optional let mut saved_sideset_count = 0; @@ -1327,7 +1328,7 @@ impl Rx { pub fn fifo_address(&self) -> *const u32 { // Safety: returning the address is safe as such. The user is responsible for any // dereference ops at that address. - unsafe { self.block().rxf[SM::id()].as_ptr() } + unsafe { self.block().rxf(SM::id()).as_ptr() } } /// Gets the FIFO's `DREQ` value. @@ -1360,8 +1361,9 @@ impl Rx { // Safety: only instance reading/writing to autopush bit and no other write to this // register unsafe { - self.block().sm[SM::id()] - .sm_shiftctrl + self.block() + .sm(SM::id()) + .sm_shiftctrl() .modify(|_, w| w.autopush().bit(enable)) } } @@ -1369,13 +1371,13 @@ impl Rx { /// Indicate if the rx FIFO is empty pub fn is_empty(&self) -> bool { // Safety: Read only access without side effect - unsafe { self.block().fstat.read().rxempty().bits() & (1 << SM::id()) != 0 } + unsafe { self.block().fstat().read().rxempty().bits() & (1 << SM::id()) != 0 } } /// Indicate if the rx FIFO is full pub fn is_full(&self) -> bool { // Safety: Read only access without side effect - unsafe { self.block().fstat.read().rxfull().bits() & (1 << SM::id()) != 0 } + unsafe { self.block().fstat().read().rxfull().bits() & (1 << SM::id()) != 0 } } /// Enable RX FIFO not empty interrupt. @@ -1385,7 +1387,7 @@ impl Rx { // Safety: Atomic write to a single bit owned by this instance unsafe { write_bitmask_set( - self.block().sm_irq[id.to_index()].irq_inte.as_ptr(), + self.block().sm_irq(id.to_index()).irq_inte().as_ptr(), 1 << SM::id(), ); } @@ -1396,7 +1398,7 @@ impl Rx { // Safety: Atomic write to a single bit owned by this instance unsafe { write_bitmask_clear( - self.block().sm_irq[id.to_index()].irq_inte.as_ptr(), + self.block().sm_irq(id.to_index()).irq_inte().as_ptr(), 1 << SM::id(), ); } @@ -1412,7 +1414,7 @@ impl Rx { // Safety: Atomic write to a single bit owned by this instance unsafe { action( - self.block().sm_irq[id.to_index()].irq_intf.as_ptr(), + self.block().sm_irq(id.to_index()).irq_intf().as_ptr(), 1 << SM::id(), ); } @@ -1430,7 +1432,7 @@ unsafe impl ReadTarget for Rx { fn rx_address_count(&self) -> (u32, u32) { ( - &unsafe { &*self.block }.rxf[SM::id()] as *const _ as u32, + unsafe { &*self.block }.rxf(SM::id()) as *const _ as u32, u32::MAX, ) } @@ -1479,7 +1481,7 @@ impl Tx { /// overflowing the buffer. pub fn fifo_address(&self) -> *const u32 { // Safety: The only access to this register - unsafe { self.block().txf[SM::id()].as_ptr() } + unsafe { self.block().txf(SM::id()).as_ptr() } } /// Gets the FIFO's `DREQ` value. @@ -1552,7 +1554,7 @@ impl Tx { pub fn has_stalled(&self) -> bool { let mask = 1 << SM::id(); // Safety: read-only access without side-effect - unsafe { self.block().fdebug.read().txstall().bits() & mask == mask } + unsafe { self.block().fdebug().read().txstall().bits() & mask == mask } } /// Clears the `tx_stalled` flag. @@ -1561,20 +1563,20 @@ impl Tx { // Safety: These bits are WC, only the one corresponding to this SM is set. unsafe { - self.block().fdebug.write(|w| w.txstall().bits(mask)); + self.block().fdebug().write(|w| w.txstall().bits(mask)); } } /// Indicate if the tx FIFO is empty pub fn is_empty(&self) -> bool { // Safety: read-only access without side-effect - unsafe { self.block().fstat.read().txempty().bits() & (1 << SM::id()) != 0 } + unsafe { self.block().fstat().read().txempty().bits() & (1 << SM::id()) != 0 } } /// Indicate if the tx FIFO is full pub fn is_full(&self) -> bool { // Safety: read-only access without side-effect - unsafe { self.block().fstat.read().txfull().bits() & (1 << SM::id()) != 0 } + unsafe { self.block().fstat().read().txfull().bits() & (1 << SM::id()) != 0 } } /// Enable TX FIFO not full interrupt. @@ -1584,7 +1586,7 @@ impl Tx { // Safety: Atomic access to the register. Bit only modified by this Tx unsafe { write_bitmask_set( - self.block().sm_irq[id.to_index()].irq_inte.as_ptr(), + self.block().sm_irq(id.to_index()).irq_inte().as_ptr(), 1 << (SM::id() + 4), ); } @@ -1595,7 +1597,7 @@ impl Tx { // Safety: Atomic access to the register. Bit only modified by this Tx unsafe { write_bitmask_clear( - self.block().sm_irq[id.to_index()].irq_inte.as_ptr(), + self.block().sm_irq(id.to_index()).irq_inte().as_ptr(), 1 << (SM::id() + 4), ); } @@ -1606,7 +1608,7 @@ impl Tx { // Safety: Atomic access to the register. Bit only modified by this Tx unsafe { write_bitmask_set( - self.block().sm_irq[id.to_index()].irq_intf.as_ptr(), + self.block().sm_irq(id.to_index()).irq_intf().as_ptr(), 1 << (SM::id() + 4), ); } @@ -1624,7 +1626,7 @@ unsafe impl WriteTarget for Tx { fn tx_address_count(&mut self) -> (u32, u32) { ( - &unsafe { &*self.block }.txf[SM::id()] as *const _ as u32, + unsafe { &*self.block }.txf(SM::id()) as *const _ as u32, u32::MAX, ) } @@ -1659,7 +1661,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_set(self.irq().irq_inte.as_ptr(), 1 << (id + 8)); + write_bitmask_set(self.irq().irq_inte().as_ptr(), 1 << (id + 8)); } } @@ -1670,7 +1672,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_clear(self.irq().irq_inte.as_ptr(), 1 << (id + 8)); + write_bitmask_clear(self.irq().irq_inte().as_ptr(), 1 << (id + 8)); } } @@ -1686,9 +1688,9 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { // Safety: Atomic write to a single bit owned by this instance unsafe { if set { - write_bitmask_set(self.irq().irq_intf.as_ptr(), 1 << (id + 8)); + write_bitmask_set(self.irq().irq_intf().as_ptr(), 1 << (id + 8)); } else { - write_bitmask_clear(self.irq().irq_intf.as_ptr(), 1 << (id + 8)); + write_bitmask_clear(self.irq().irq_intf().as_ptr(), 1 << (id + 8)); } } } @@ -1705,7 +1707,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_set(self.irq().irq_inte.as_ptr(), 1 << (id + 4)); + write_bitmask_set(self.irq().irq_inte().as_ptr(), 1 << (id + 4)); } } @@ -1720,7 +1722,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_clear(self.irq().irq_inte.as_ptr(), 1 << (id + 4)); + write_bitmask_clear(self.irq().irq_inte().as_ptr(), 1 << (id + 4)); } } @@ -1735,7 +1737,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_set(self.irq().irq_intf.as_ptr(), 1 << (id + 4)); + write_bitmask_set(self.irq().irq_intf().as_ptr(), 1 << (id + 4)); } } @@ -1751,7 +1753,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_set(self.irq().irq_inte.as_ptr(), 1 << id); + write_bitmask_set(self.irq().irq_inte().as_ptr(), 1 << id); } } @@ -1766,7 +1768,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_clear(self.irq().irq_inte.as_ptr(), 1 << id); + write_bitmask_clear(self.irq().irq_inte().as_ptr(), 1 << id); } } @@ -1781,7 +1783,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { assert!(id < 4, "invalid state machine interrupt number"); // Safety: Atomic write to a single bit owned by this instance unsafe { - write_bitmask_set(self.irq().irq_intf.as_ptr(), 1 << id); + write_bitmask_set(self.irq().irq_intf().as_ptr(), 1 << id); } } @@ -1791,7 +1793,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { pub fn raw(&self) -> InterruptState { InterruptState( // Safety: Read only access without side effect - unsafe { self.block().intr.read().bits() }, + unsafe { self.block().intr().read().bits() }, ) } @@ -1801,7 +1803,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { pub fn state(&self) -> InterruptState { InterruptState( // Safety: Read only access without side effect - unsafe { self.irq().irq_ints.read().bits() }, + unsafe { self.irq().irq_ints().read().bits() }, ) } @@ -1810,7 +1812,7 @@ impl<'a, P: PIOExt, const IRQ: usize> Interrupt<'a, P, IRQ> { } unsafe fn irq(&self) -> &crate::pac::pio0::SM_IRQ { - &self.block().sm_irq[IRQ] + self.block().sm_irq(IRQ) } } @@ -2174,7 +2176,7 @@ impl PIOBuilder

{ // Safety: Only instance owning the SM unsafe { - sm.sm().sm_execctrl.write(|w| { + sm.sm().sm_execctrl().write(|w| { w.side_en().bit(self.program.side_set.optional()); w.side_pindir().bit(self.program.side_set.pindirs()); @@ -2205,7 +2207,7 @@ impl PIOBuilder

{ w.status_n().bits(n) }); - sm.sm().sm_shiftctrl.write(|w| { + sm.sm().sm_shiftctrl().write(|w| { let (fjoin_rx, fjoin_tx) = match self.fifo_join { Buffers::RxTx => (false, false), Buffers::OnlyTx => (false, true), @@ -2225,7 +2227,7 @@ impl PIOBuilder

{ w.autopush().bit(self.autopush) }); - sm.sm().sm_pinctrl.write(|w| { + sm.sm().sm_pinctrl().write(|w| { w.sideset_count().bits(self.program.side_set.bits()); w.set_count().bits(self.set_count); w.out_count().bits(self.out_count); @@ -2250,7 +2252,7 @@ impl PIOBuilder

{ .encode(); // Safety: Only instance owning the SM unsafe { - sm.sm().sm_instr.write(|w| w.sm0_instr().bits(instr)); + sm.sm().sm_instr().write(|w| w.sm0_instr().bits(instr)); } let rx = Rx { diff --git a/rp2040-hal/src/pll.rs b/rp2040-hal/src/pll.rs index 85e882c5f..56b14e7f5 100644 --- a/rp2040-hal/src/pll.rs +++ b/rp2040-hal/src/pll.rs @@ -203,21 +203,21 @@ impl PhaseLockedLoop { self.device.reset_bring_up(resets); // Turn off PLL in case it is already running - self.device.pwr.reset(); - self.device.fbdiv_int.reset(); + self.device.pwr().reset(); + self.device.fbdiv_int().reset(); - self.device.cs.write(|w| unsafe { + self.device.cs().write(|w| unsafe { w.refdiv().bits(self.state.refdiv); w }); - self.device.fbdiv_int.write(|w| unsafe { + self.device.fbdiv_int().write(|w| unsafe { w.fbdiv_int().bits(self.state.fbdiv); w }); // Turn on PLL - self.device.pwr.modify(|_, w| { + self.device.pwr().modify(|_, w| { w.pd().clear_bit(); w.vcopd().clear_bit(); w @@ -243,7 +243,7 @@ pub struct LockedPLLToken { impl PhaseLockedLoop { /// Awaits locking of the PLL. pub fn await_lock(&self) -> nb::Result, Infallible> { - if self.device.cs.read().lock().bit_is_clear() { + if self.device.cs().read().lock().bit_is_clear() { return Err(WouldBlock); } @@ -255,14 +255,14 @@ impl PhaseLockedLoop { /// Exchanges a token for a Locked PLL. pub fn get_locked(self, _token: LockedPLLToken) -> PhaseLockedLoop { // Set up post dividers - self.device.prim.write(|w| unsafe { + self.device.prim().write(|w| unsafe { w.postdiv1().bits(self.state.post_div1); w.postdiv2().bits(self.state.post_div2); w }); // Turn on post divider - self.device.pwr.modify(|_, w| { + self.device.pwr().modify(|_, w| { w.postdivpd().clear_bit(); w }); diff --git a/rp2040-hal/src/pwm/mod.rs b/rp2040-hal/src/pwm/mod.rs index 9675809a9..22fc36a35 100644 --- a/rp2040-hal/src/pwm/mod.rs +++ b/rp2040-hal/src/pwm/mod.rs @@ -445,7 +445,7 @@ where pub fn enable_interrupt(&mut self) { unsafe { let pwm = &(*pac::PWM::ptr()); - let reg = pwm.inte.as_ptr(); + let reg = pwm.inte().as_ptr(); write_bitmask_set(reg, self.bitmask()); } } @@ -455,7 +455,7 @@ where pub fn disable_interrupt(&mut self) { unsafe { let pwm = &(*pac::PWM::ptr()); - let reg = pwm.inte.as_ptr(); + let reg = pwm.inte().as_ptr(); write_bitmask_clear(reg, self.bitmask()); }; } @@ -468,13 +468,13 @@ where #[inline] pub fn has_overflown(&self) -> bool { let mask = self.bitmask(); - unsafe { (*pac::PWM::ptr()).intr.read().bits() & mask == mask } + unsafe { (*pac::PWM::ptr()).intr().read().bits() & mask == mask } } /// Mark the interrupt handled for this slice. #[inline] pub fn clear_interrupt(&mut self) { - unsafe { (*pac::PWM::ptr()).intr.write(|w| w.bits(self.bitmask())) }; + unsafe { (*pac::PWM::ptr()).intr().write(|w| w.bits(self.bitmask())) }; } /// Force the interrupt. This bit is not cleared by hardware and must be manually cleared to @@ -483,7 +483,7 @@ where pub fn force_interrupt(&mut self) { unsafe { let pwm = &(*pac::PWM::ptr()); - let reg = pwm.intf.as_ptr(); + let reg = pwm.intf().as_ptr(); write_bitmask_set(reg, self.bitmask()); } } @@ -494,7 +494,7 @@ where pub fn clear_force_interrupt(&mut self) { unsafe { let pwm = &(*pac::PWM::ptr()); - let reg = pwm.intf.as_ptr(); + let reg = pwm.intf().as_ptr(); write_bitmask_clear(reg, self.bitmask()); } } @@ -573,7 +573,7 @@ impl Slices { pub fn enable_simultaneous(&mut self, bits: u8) { // Enable multiple slices at the same time unsafe { - let reg = self._pwm.en.as_ptr(); + let reg = self._pwm.en().as_ptr(); write_bitmask_set(reg, bits as u32); } } @@ -1005,7 +1005,7 @@ unsafe impl> WriteTarget for SliceDmaWriteCc {}, }; - (regs.ch().cc.as_ptr() as u32, u32::MAX) + (regs.ch().cc().as_ptr() as u32, u32::MAX) } fn tx_increment(&self) -> bool { @@ -1026,7 +1026,7 @@ unsafe impl> WriteTarget for SliceDmaWriteTop {}, }; - (regs.ch().top.as_ptr() as u32, u32::MAX) + (regs.ch().top().as_ptr() as u32, u32::MAX) } fn tx_increment(&self) -> bool { diff --git a/rp2040-hal/src/pwm/reg.rs b/rp2040-hal/src/pwm/reg.rs index 149fe9edf..20c27009a 100644 --- a/rp2040-hal/src/pwm/reg.rs +++ b/rp2040-hal/src/pwm/reg.rs @@ -17,22 +17,22 @@ pub(super) unsafe trait RegisterInterface { #[inline] fn ch(&self) -> &CH { let num = self.id().num as usize; - unsafe { &(*pac::PWM::ptr()).ch[num] } + unsafe { (*pac::PWM::ptr()).ch(num) } } #[inline] fn advance_phase(&mut self) { - self.ch().csr.modify(|_, w| w.ph_adv().set_bit()) + self.ch().csr().modify(|_, w| w.ph_adv().set_bit()) } #[inline] fn retard_phase(&mut self) { - self.ch().csr.modify(|_, w| w.ph_ret().set_bit()) + self.ch().csr().modify(|_, w| w.ph_ret().set_bit()) } #[inline] fn do_change_mode(&mut self, mode: DynSliceMode) { - self.ch().csr.modify(|_, w| match mode { + self.ch().csr().modify(|_, w| match mode { DynSliceMode::FreeRunning => w.divmode().div(), DynSliceMode::InputHighRunning => w.divmode().level(), DynSliceMode::CountRisingEdge => w.divmode().rise(), @@ -42,66 +42,70 @@ pub(super) unsafe trait RegisterInterface { #[inline] fn write_inv_a(&mut self, value: bool) { - self.ch().csr.modify(|_, w| w.a_inv().bit(value)); + self.ch().csr().modify(|_, w| w.a_inv().bit(value)); } #[inline] fn write_inv_b(&mut self, value: bool) { - self.ch().csr.modify(|_, w| w.b_inv().bit(value)); + self.ch().csr().modify(|_, w| w.b_inv().bit(value)); } #[inline] fn write_ph_correct(&mut self, value: bool) { - self.ch().csr.modify(|_, w| w.ph_correct().bit(value)); + self.ch().csr().modify(|_, w| w.ph_correct().bit(value)); } #[inline] fn write_enable(&mut self, value: bool) { - self.ch().csr.modify(|_, w| w.en().bit(value)); + self.ch().csr().modify(|_, w| w.en().bit(value)); } #[inline] fn write_div_int(&mut self, value: u8) { - self.ch().div.modify(|_, w| unsafe { w.int().bits(value) }); + self.ch() + .div() + .modify(|_, w| unsafe { w.int().bits(value) }); } #[inline] fn write_div_frac(&mut self, value: u8) { - self.ch().div.modify(|_, w| unsafe { w.frac().bits(value) }); + self.ch() + .div() + .modify(|_, w| unsafe { w.frac().bits(value) }); } #[inline] fn write_ctr(&mut self, value: u16) { - self.ch().ctr.write(|w| unsafe { w.ctr().bits(value) }); + self.ch().ctr().write(|w| unsafe { w.ctr().bits(value) }); } #[inline] fn read_ctr(&self) -> u16 { - self.ch().ctr.read().ctr().bits() + self.ch().ctr().read().ctr().bits() } #[inline] fn write_cc_a(&mut self, value: u16) { - self.ch().cc.modify(|_, w| unsafe { w.a().bits(value) }); + self.ch().cc().modify(|_, w| unsafe { w.a().bits(value) }); } #[inline] fn read_cc_a(&self) -> u16 { - self.ch().cc.read().a().bits() + self.ch().cc().read().a().bits() } #[inline] fn write_cc_b(&mut self, value: u16) { - self.ch().cc.modify(|_, w| unsafe { w.b().bits(value) }); + self.ch().cc().modify(|_, w| unsafe { w.b().bits(value) }); } #[inline] fn read_cc_b(&self) -> u16 { - self.ch().cc.read().b().bits() + self.ch().cc().read().b().bits() } #[inline] fn write_top(&mut self, value: u16) { - self.ch().top.write(|w| unsafe { w.top().bits(value) }); + self.ch().top().write(|w| unsafe { w.top().bits(value) }); } #[inline] fn read_top(&self) -> u16 { - self.ch().top.read().top().bits() + self.ch().top().read().top().bits() } } diff --git a/rp2040-hal/src/resets.rs b/rp2040-hal/src/resets.rs index 07f2081ad..0c34a0e7b 100644 --- a/rp2040-hal/src/resets.rs +++ b/rp2040-hal/src/resets.rs @@ -13,11 +13,11 @@ macro_rules! generate_reset { ($MODULE:ident, $module:ident) => { impl SubsystemReset for $crate::pac::$MODULE { fn reset_bring_up(&self, resets: &mut $crate::pac::RESETS) { - resets.reset.modify(|_, w| w.$module().clear_bit()); - while resets.reset_done.read().$module().bit_is_clear() {} + resets.reset().modify(|_, w| w.$module().clear_bit()); + while resets.reset_done().read().$module().bit_is_clear() {} } fn reset_bring_down(&self, resets: &mut $crate::pac::RESETS) { - resets.reset.modify(|_, w| w.$module().set_bit()); + resets.reset().modify(|_, w| w.$module().set_bit()); } } }; diff --git a/rp2040-hal/src/rosc.rs b/rp2040-hal/src/rosc.rs index 93a0ab17b..efdcfc483 100644 --- a/rp2040-hal/src/rosc.rs +++ b/rp2040-hal/src/rosc.rs @@ -70,7 +70,7 @@ impl RingOscillator { /// Initializes the ROSC : frequency range is set, startup delay is calculated and set. pub fn initialize(self) -> RingOscillator { - self.device.ctrl.write(|w| w.enable().enable()); + self.device.ctrl().write(|w| w.enable().enable()); use fugit::RateExtU32; self.transition(Enabled { @@ -83,7 +83,7 @@ impl RingOscillator { /// in the rp2040 datasheet for guidance on how to do this before initialising the ROSC. /// Also see `rosc_as_system_clock` example for usage. pub fn initialize_with_freq(self, known_freq: HertzU32) -> RingOscillator { - self.device.ctrl.write(|w| w.enable().enable()); + self.device.ctrl().write(|w| w.enable().enable()); self.transition(Enabled { freq_hz: known_freq, }) @@ -98,7 +98,7 @@ impl RingOscillator { /// Disables the ROSC pub fn disable(self) -> RingOscillator { - self.device.ctrl.modify(|_r, w| w.enable().disable()); + self.device.ctrl().modify(|_r, w| w.enable().disable()); self.transition(Disabled) } @@ -106,7 +106,7 @@ impl RingOscillator { /// Generate random bit based on the Ring oscillator /// This is not suited for security purposes pub fn get_random_bit(&self) -> bool { - self.device.randombit.read().randombit().bit() + self.device.randombit().read().randombit().bit() } /// Put the ROSC in DORMANT state. @@ -120,7 +120,7 @@ impl RingOscillator { //taken from the C SDK const ROSC_DORMANT_VALUE: u32 = 0x636f6d61; - self.device.dormant.write(|w| w.bits(ROSC_DORMANT_VALUE)); + self.device.dormant().write(|w| w.bits(ROSC_DORMANT_VALUE)); self.transition(Dormant) } diff --git a/rp2040-hal/src/rtc/mod.rs b/rp2040-hal/src/rtc/mod.rs index adb11c4cc..c905c55c9 100644 --- a/rp2040-hal/src/rtc/mod.rs +++ b/rp2040-hal/src/rtc/mod.rs @@ -59,15 +59,15 @@ impl RealTimeClock { initial_date: DateTime, ) -> Result { // Toggle the RTC reset - resets.reset.modify(|_, w| w.rtc().set_bit()); - resets.reset.modify(|_, w| w.rtc().clear_bit()); - while resets.reset_done.read().rtc().bit_is_clear() { + resets.reset().modify(|_, w| w.rtc().set_bit()); + resets.reset().modify(|_, w| w.rtc().clear_bit()); + while resets.reset_done().read().rtc().bit_is_clear() { core::hint::spin_loop(); } // Set the RTC divider let freq = clock.freq().to_Hz() - 1; - rtc.clkdiv_m1.write(|w| unsafe { w.bits(freq) }); + rtc.clkdiv_m1().write(|w| unsafe { w.bits(freq) }); let mut result = Self { rtc, clock }; result.set_leap_year_check(true); // should be on by default, make sure this is the case. @@ -80,13 +80,13 @@ impl RealTimeClock { /// Leap year checking is enabled by default. pub fn set_leap_year_check(&mut self, leap_year_check_enabled: bool) { self.rtc - .ctrl + .ctrl() .modify(|_, w| w.force_notleapyear().bit(!leap_year_check_enabled)); } /// Checks to see if this RealTimeClock is running pub fn is_running(&self) -> bool { - self.rtc.ctrl.read().rtc_active().bit_is_set() + self.rtc.ctrl().read().rtc_active().bit_is_set() } /// Set the datetime to a new value. @@ -98,24 +98,24 @@ impl RealTimeClock { self::datetime::validate_datetime(&t).map_err(RtcError::InvalidDateTime)?; // disable RTC while we configure it - self.rtc.ctrl.modify(|_, w| w.rtc_enable().clear_bit()); - while self.rtc.ctrl.read().rtc_active().bit_is_set() { + self.rtc.ctrl().modify(|_, w| w.rtc_enable().clear_bit()); + while self.rtc.ctrl().read().rtc_active().bit_is_set() { core::hint::spin_loop(); } - self.rtc.setup_0.write(|w| { + self.rtc.setup_0().write(|w| { self::datetime::write_setup_0(&t, w); w }); - self.rtc.setup_1.write(|w| { + self.rtc.setup_1().write(|w| { self::datetime::write_setup_1(&t, w); w }); // Load the new datetime and re-enable RTC - self.rtc.ctrl.write(|w| w.load().set_bit()); - self.rtc.ctrl.write(|w| w.rtc_enable().set_bit()); - while self.rtc.ctrl.read().rtc_active().bit_is_clear() { + self.rtc.ctrl().write(|w| w.load().set_bit()); + self.rtc.ctrl().write(|w| w.rtc_enable().set_bit()); + while self.rtc.ctrl().read().rtc_active().bit_is_clear() { core::hint::spin_loop(); } @@ -132,16 +132,16 @@ impl RealTimeClock { return Err(RtcError::NotRunning); } - let rtc_0 = self.rtc.rtc_0.read(); - let rtc_1 = self.rtc.rtc_1.read(); + let rtc_0 = self.rtc.rtc_0().read(); + let rtc_1 = self.rtc.rtc_1().read(); self::datetime::datetime_from_registers(rtc_0, rtc_1).map_err(RtcError::InvalidDateTime) } fn set_match_ena(&mut self, ena: bool) { // Set the enable bit and check if it is set - self.rtc.irq_setup_0.modify(|_, w| w.match_ena().bit(ena)); - while self.rtc.irq_setup_0.read().match_active().bit() != ena { + self.rtc.irq_setup_0().modify(|_, w| w.match_ena().bit(ena)); + while self.rtc.irq_setup_0().read().match_active().bit() != ena { core::hint::spin_loop(); } } @@ -167,11 +167,11 @@ impl RealTimeClock { pub fn schedule_alarm(&mut self, filter: DateTimeFilter) { self.set_match_ena(false); - self.rtc.irq_setup_0.write(|w| { + self.rtc.irq_setup_0().write(|w| { filter.write_setup_0(w); w }); - self.rtc.irq_setup_1.write(|w| { + self.rtc.irq_setup_1().write(|w| { filter.write_setup_1(w); w }); @@ -181,12 +181,12 @@ impl RealTimeClock { /// Enable the propagation of alarm to the NVIC. pub fn enable_interrupt(&mut self) { - self.rtc.inte.modify(|_, w| w.rtc().set_bit()); + self.rtc.inte().modify(|_, w| w.rtc().set_bit()); } /// Disable the propagation of the alarm to the NVIC. pub fn disable_interrupt(&mut self) { - self.rtc.inte.modify(|_, w| w.rtc().clear_bit()); + self.rtc.inte().modify(|_, w| w.rtc().clear_bit()); } /// Clear the interrupt. @@ -200,7 +200,7 @@ impl RealTimeClock { /// Free the RTC peripheral and RTC clock pub fn free(self, resets: &mut RESETS) -> (RTC, RtcClock) { - resets.reset.modify(|_, w| w.rtc().set_bit()); + resets.reset().modify(|_, w| w.rtc().set_bit()); (self.rtc, self.clock) } } diff --git a/rp2040-hal/src/sio.rs b/rp2040-hal/src/sio.rs index 694bf0cc3..0ff0a6719 100644 --- a/rp2040-hal/src/sio.rs +++ b/rp2040-hal/src/sio.rs @@ -101,13 +101,13 @@ impl Sio { /// Reads the whole bank0 at once. pub fn read_bank0() -> u32 { - unsafe { (*pac::SIO::PTR).gpio_in.read().bits() } + unsafe { (*pac::SIO::PTR).gpio_in().read().bits() } } /// Returns whether we are running on Core 0 (`0`) or Core 1 (`1`). pub fn core() -> CoreId { // Safety: it is always safe to read this read-only register - match unsafe { (*pac::SIO::ptr()).cpuid.read().bits() as u8 } { + match unsafe { (*pac::SIO::ptr()).cpuid().read().bits() as u8 } { 0 => CoreId::Core0, 1 => CoreId::Core1, _ => unreachable!("This MCU only has 2 cores."), @@ -122,7 +122,7 @@ impl SioFifo { /// and you must not read from it. pub fn is_read_ready(&mut self) -> bool { let sio = unsafe { &(*pac::SIO::ptr()) }; - sio.fifo_st.read().vld().bit_is_set() + sio.fifo_st().read().vld().bit_is_set() } /// Check if the inter-core FIFO is ready to receive data. @@ -131,13 +131,13 @@ impl SioFifo { /// must not write to it. pub fn is_write_ready(&mut self) -> bool { let sio = unsafe { &(*pac::SIO::ptr()) }; - sio.fifo_st.read().rdy().bit_is_set() + sio.fifo_st().read().rdy().bit_is_set() } /// Return the FIFO status, as an integer. pub fn status(&self) -> u32 { let sio = unsafe { &(*pac::SIO::ptr()) }; - sio.fifo_st.read().bits() + sio.fifo_st().read().bits() } /// Write to the inter-core FIFO. @@ -145,7 +145,7 @@ impl SioFifo { /// You must ensure the FIFO has space by calling `is_write_ready` pub fn write(&mut self, value: u32) { let sio = unsafe { &(*pac::SIO::ptr()) }; - sio.fifo_wr.write(|w| unsafe { w.bits(value) }); + sio.fifo_wr().write(|w| unsafe { w.bits(value) }); // Fire off an event to the other core. // This is required as the other core may be `wfe` (waiting for event) cortex_m::asm::sev(); @@ -157,7 +157,7 @@ impl SioFifo { pub fn read(&mut self) -> Option { if self.is_read_ready() { let sio = unsafe { &(*pac::SIO::ptr()) }; - Some(sio.fifo_rd.read().bits()) + Some(sio.fifo_rd().read().bits()) } else { None } @@ -476,7 +476,7 @@ where pub fn try_claim() -> Option { // Safety: We're only reading from this register let sio = unsafe { &*pac::SIO::ptr() }; - let lock = sio.spinlock[N].read().bits(); + let lock = sio.spinlock(N).read().bits(); if lock > 0 { Some(Self(core::marker::PhantomData)) } else { @@ -508,7 +508,7 @@ where pub unsafe fn release() { let sio = &*pac::SIO::ptr(); // Write (any value): release the lock - sio.spinlock[N].write_with_zero(|b| b.bits(1)); + sio.spinlock(N).write_with_zero(|b| b.bits(1)); } } @@ -559,7 +559,7 @@ pub fn spinlock_state() -> [bool; 32] { // Safety: we're only reading from a register let sio = unsafe { &*pac::SIO::ptr() }; // A bitmap containing the state of all 32 spinlocks (1=locked). - let register = sio.spinlock_st.read().bits(); + let register = sio.spinlock_st().read().bits(); let mut result = [false; 32]; #[allow(clippy::needless_range_loop)] for i in 0..32 { @@ -741,43 +741,43 @@ macro_rules! interpolators { impl Lane for [<$interp $lane>]{ fn pop(&mut self) ->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _pop_ $lane:lower>].read().bits() + sio.[<$interp:lower _pop_ $lane:lower>]().read().bits() } fn peek(&self) ->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _peek_ $lane:lower>].read().bits() + sio.[<$interp:lower _peek_ $lane:lower>]().read().bits() } fn set_accum(&mut self,v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _accum $lane_id>].write(|w| unsafe { w.bits(v) }); + sio.[<$interp:lower _accum $lane_id>]().write(|w| unsafe { w.bits(v) }); } fn get_accum(&self)->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _accum $lane_id>].read().bits() + sio.[<$interp:lower _accum $lane_id>]().read().bits() } fn set_base(&mut self, v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _base $lane_id>].write(|w| unsafe { w.bits(v) }); + sio.[<$interp:lower _base $lane_id>]().write(|w| unsafe { w.bits(v) }); } fn get_base(&self)->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _base $lane_id>].read().bits() + sio.[<$interp:lower _base $lane_id>]().read().bits() } fn set_ctrl(&mut self, v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _ctrl_lane $lane_id>].write(|w| unsafe { w.bits(v) }); + sio.[<$interp:lower _ctrl_lane $lane_id>]().write(|w| unsafe { w.bits(v) }); } fn get_ctrl(&self)->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _ctrl_lane $lane_id>].read().bits() + sio.[<$interp:lower _ctrl_lane $lane_id>]().read().bits() } fn add_accum(&mut self, v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _accum $lane_id _add>].write(|w| unsafe { w.bits(v) }); + sio.[<$interp:lower _accum $lane_id _add>]().write(|w| unsafe { w.bits(v) }); } fn read_raw(&self)->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _accum $lane_id _add>].read().bits() + sio.[<$interp:lower _accum $lane_id _add>]().read().bits() } } impl Sealed for [<$interp $lane>] {} @@ -799,23 +799,23 @@ macro_rules! interpolators { impl Interp for $interp{ fn pop(&mut self) ->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _pop_full>].read().bits() + sio.[<$interp:lower _pop_full>]().read().bits() } fn peek(&self) ->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _peek_full>].read().bits() + sio.[<$interp:lower _peek_full>]().read().bits() } fn set_base(&mut self, v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _base2>].write(|w| unsafe { w.bits(v)}); + sio.[<$interp:lower _base2>]().write(|w| unsafe { w.bits(v)}); } fn get_base(&self)->u32{ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _base2>].read().bits() + sio.[<$interp:lower _base2>]().read().bits() } fn set_base_1and0(&mut self, v:u32){ let sio = unsafe { &*pac::SIO::ptr() }; - sio.[<$interp:lower _base_1and0>].write(|w| unsafe { w.bits(v)}); + sio.[<$interp:lower _base_1and0>]().write(|w| unsafe { w.bits(v)}); } } impl Sealed for $interp {} diff --git a/rp2040-hal/src/spi.rs b/rp2040-hal/src/spi.rs index 73103a233..4da1abc90 100644 --- a/rp2040-hal/src/spi.rs +++ b/rp2040-hal/src/spi.rs @@ -237,10 +237,10 @@ impl, const DS: u8> Spi, const DS: u8> Spi { /// Set format and datasize fn set_format(&mut self, data_bits: u8, frame_format: FrameFormat) { - self.device.sspcr0.modify(|_, w| unsafe { + self.device.sspcr0().modify(|_, w| unsafe { w.dss().bits(data_bits - 1).frf().bits(match &frame_format { FrameFormat::MotorolaSpi(_) => 0x00, FrameFormat::TexasInstrumentsSynchronousSerial => 0x01, @@ -290,9 +290,9 @@ impl, const DS: u8> Spi { /// Set master/slave fn set_slave(&mut self, slave: bool) { if slave { - self.device.sspcr1.modify(|_, w| w.ms().set_bit()); + self.device.sspcr1().modify(|_, w| w.ms().set_bit()); } else { - self.device.sspcr1.modify(|_, w| w.ms().clear_bit()); + self.device.sspcr1().modify(|_, w| w.ms().clear_bit()); } } @@ -312,11 +312,11 @@ impl, const DS: u8> Spi { self.set_slave(slave); // Always enable DREQ signals -- harmless if DMA is not listening self.device - .sspdmacr + .sspdmacr() .modify(|_, w| w.txdmae().set_bit().rxdmae().set_bit()); // Finally enable the SPI - self.device.sspcr1.modify(|_, w| w.sse().set_bit()); + self.device.sspcr1().modify(|_, w| w.sse().set_bit()); self.transition(Enabled { __private: () }) } @@ -353,21 +353,21 @@ impl, const DS: u8> Spi { impl, const DS: u8> Spi { fn is_writable(&self) -> bool { - self.device.sspsr.read().tnf().bit_is_set() + self.device.sspsr().read().tnf().bit_is_set() } fn is_readable(&self) -> bool { - self.device.sspsr.read().rne().bit_is_set() + self.device.sspsr().read().rne().bit_is_set() } /// Check if spi is busy transmitting and/or receiving pub fn is_busy(&self) -> bool { - self.device.sspsr.read().bsy().bit_is_set() + self.device.sspsr().read().bsy().bit_is_set() } /// Disable the spi to reset its configuration. You'll then need to initialize it again to use /// it. pub fn disable(self) -> Spi { - self.device.sspcr1.modify(|_, w| w.sse().clear_bit()); + self.device.sspcr1().modify(|_, w| w.sse().clear_bit()); self.transition(Disabled { __private: () }) } @@ -385,7 +385,7 @@ macro_rules! impl_write { return Err(nb::Error::WouldBlock); } - Ok(self.device.sspdr.read().data().bits() as $type) + Ok(self.device.sspdr().read().data().bits() as $type) } fn send(&mut self, word: $type) -> Result<(), nb::Error> { // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX @@ -396,7 +396,7 @@ macro_rules! impl_write { } self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(word as u16) }); Ok(()) } @@ -416,12 +416,12 @@ macro_rules! impl_write { // write empty word while !self.is_writable() {} self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(0) }); // read one word while !self.is_readable() {} - *word = self.device.sspdr.read().data().bits() as $type; + *word = self.device.sspdr().read().data().bits() as $type; } Ok(()) } @@ -431,12 +431,12 @@ macro_rules! impl_write { // write one word while !self.is_writable() {} self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(*word as u16) }); // drop read wordd while !self.is_readable() {} - let _ = self.device.sspdr.read().data().bits(); + let _ = self.device.sspdr().read().data().bits(); } Ok(()) } @@ -448,12 +448,12 @@ macro_rules! impl_write { let wb = write.get(i).copied().unwrap_or(0); while !self.is_writable() {} self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(wb as u16) }); // read one word. Drop extra words if buffer is full. while !self.is_readable() {} - let rb = self.device.sspdr.read().data().bits() as $type; + let rb = self.device.sspdr().read().data().bits() as $type; if let Some(r) = read.get_mut(i) { *r = rb; } @@ -467,12 +467,12 @@ macro_rules! impl_write { // write one word while !self.is_writable() {} self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(*word as u16) }); // read one word while !self.is_readable() {} - *word = self.device.sspdr.read().data().bits() as $type; + *word = self.device.sspdr().read().data().bits() as $type; } Ok(()) @@ -490,7 +490,7 @@ macro_rules! impl_write { return Err(nb::Error::WouldBlock); } - Ok(self.device.sspdr.read().data().bits() as $type) + Ok(self.device.sspdr().read().data().bits() as $type) } fn write(&mut self, word: $type) -> Result<(), nb::Error> { // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX @@ -501,7 +501,7 @@ macro_rules! impl_write { } self.device - .sspdr + .sspdr() .write(|w| unsafe { w.data().bits(word as u16) }); Ok(()) } @@ -518,7 +518,7 @@ macro_rules! impl_write { fn rx_address_count(&self) -> (u32, u32) { ( - &self.device.sspdr as *const _ as u32, + self.device.sspdr() as *const _ as u32, u32::MAX, ) } @@ -541,7 +541,7 @@ macro_rules! impl_write { fn tx_address_count(&mut self) -> (u32, u32) { ( - &self.device.sspdr as *const _ as u32, + self.device.sspdr() as *const _ as u32, u32::MAX, ) } diff --git a/rp2040-hal/src/timer.rs b/rp2040-hal/src/timer.rs index 444ce985a..4810a78c6 100644 --- a/rp2040-hal/src/timer.rs +++ b/rp2040-hal/src/timer.rs @@ -69,10 +69,10 @@ impl Timer { pub fn get_counter(&self) -> Instant { // Safety: Only used for reading current timer value let timer = unsafe { &*pac::TIMER::PTR }; - let mut hi0 = timer.timerawh.read().bits(); + let mut hi0 = timer.timerawh().read().bits(); let timestamp = loop { - let low = timer.timerawl.read().bits(); - let hi1 = timer.timerawh.read().bits(); + let low = timer.timerawl().read().bits(); + let hi1 = timer.timerawh().read().bits(); if hi0 == hi1 { break (u64::from(hi0) << 32) | u64::from(low); } @@ -84,7 +84,7 @@ impl Timer { /// Get the value of the least significant word of the counter. pub fn get_counter_low(&self) -> u32 { // Safety: Only used for reading current timer value - unsafe { &*pac::TIMER::PTR }.timerawl.read().bits() + unsafe { &*pac::TIMER::PTR }.timerawl().read().bits() } /// Initialized a Count Down instance without starting it. @@ -319,22 +319,22 @@ macro_rules! impl_alarm { // This lock is for time-criticality cortex_m::interrupt::free(|_| { - let alarm = &timer.$timer_alarm; + let alarm = &timer.$timer_alarm(); // safety: This is the only code in the codebase that accesses memory address $timer_alarm alarm.write(|w| unsafe { w.bits(timestamp_low) }); // If it is not set, it has already triggered. let now = self.0.get_counter(); - if now > timestamp && (timer.armed.read().bits() & $armed_bit_mask) != 0 { + if now > timestamp && (timer.armed().read().bits() & $armed_bit_mask) != 0 { // timestamp was set to a value in the past // safety: TIMER.armed is a write-clear register, and there can only be // 1 instance of AlarmN so we can safely atomically clear this bit. unsafe { - timer.armed.write_with_zero(|w| w.bits($armed_bit_mask)); + timer.armed().write_with_zero(|w| w.bits($armed_bit_mask)); crate::atomic_register_access::write_bitmask_set( - timer.intf.as_ptr(), + timer.intf().as_ptr(), $armed_bit_mask, ); } @@ -358,11 +358,11 @@ macro_rules! impl_alarm { unsafe { let timer = &(*pac::TIMER::ptr()); crate::atomic_register_access::write_bitmask_clear( - timer.intf.as_ptr(), + timer.intf().as_ptr(), $armed_bit_mask, ); timer - .intr + .intr() .write_with_zero(|w| w.$int_alarm().clear_bit_by_one()); } } @@ -380,7 +380,7 @@ macro_rules! impl_alarm { // of the TIMER.inte register unsafe { let timer = &(*pac::TIMER::ptr()); - let reg = (&timer.inte).as_ptr(); + let reg = (&timer.inte()).as_ptr(); write_bitmask_set(reg, $armed_bit_mask); } } @@ -392,7 +392,7 @@ macro_rules! impl_alarm { // of the TIMER.inte register unsafe { let timer = &(*pac::TIMER::ptr()); - let reg = (&timer.inte).as_ptr(); + let reg = (&timer.inte()).as_ptr(); write_bitmask_clear(reg, $armed_bit_mask); } } @@ -431,7 +431,7 @@ macro_rules! impl_alarm { /// has not been scheduled yet. fn finished(&self) -> bool { // safety: This is a read action and should not have any UB - let bits: u32 = unsafe { &*TIMER::ptr() }.armed.read().bits(); + let bits: u32 = unsafe { &*TIMER::ptr() }.armed().read().bits(); (bits & $armed_bit_mask) == 0 } @@ -441,9 +441,9 @@ macro_rules! impl_alarm { fn cancel(&mut self) -> Result<(), ScheduleAlarmError> { unsafe { let timer = &*TIMER::ptr(); - timer.armed.write_with_zero(|w| w.bits($armed_bit_mask)); + timer.armed().write_with_zero(|w| w.bits($armed_bit_mask)); crate::atomic_register_access::write_bitmask_clear( - timer.intf.as_ptr(), + timer.intf().as_ptr(), $armed_bit_mask, ); } diff --git a/rp2040-hal/src/uart/peripheral.rs b/rp2040-hal/src/uart/peripheral.rs index 1d5f65291..70fffbccb 100644 --- a/rp2040-hal/src/uart/peripheral.rs +++ b/rp2040-hal/src/uart/peripheral.rs @@ -60,7 +60,7 @@ impl> UartPeripheral { let (mut device, pins) = self.free(); configure_baudrate(&mut device, config.baudrate, frequency)?; - device.uartlcr_h.write(|w| { + device.uartlcr_h().write(|w| { // FIFOs are enabled w.fen().set_bit(); // Leaved here for backward compatibility set_format(w, &config.data_bits, &config.stop_bits, &config.parity); @@ -68,7 +68,7 @@ impl> UartPeripheral { }); // Enable the UART, and the TX,RC,CTS and RTS based on the pins - device.uartcr.write(|w| { + device.uartcr().write(|w| { w.uarten().set_bit(); w.txe().bit(P::Tx::IS_SOME); w.rxe().bit(P::Rx::IS_SOME); @@ -78,7 +78,7 @@ impl> UartPeripheral { w }); - device.uartdmacr.write(|w| { + device.uartdmacr().write(|w| { w.txdmae().set_bit(); w.rxdmae().set_bit(); w @@ -96,7 +96,7 @@ impl> UartPeripheral { /// Disable this UART Peripheral, falling back to the Disabled state. pub fn disable(self) -> UartPeripheral { // Disable the UART, both TX and RX - self.device.uartcr.write(|w| { + self.device.uartcr().write(|w| { w.uarten().clear_bit(); w.txe().clear_bit(); w.rxe().clear_bit(); @@ -286,20 +286,20 @@ fn configure_baudrate( let (baud_div_int, baud_div_frac) = calculate_baudrate_dividers(wanted_baudrate, frequency)?; // First we load the integer part of the divider. - device.uartibrd.write(|w| unsafe { + device.uartibrd().write(|w| unsafe { w.baud_divint().bits(baud_div_int); w }); // Then we load the fractional part of the divider. - device.uartfbrd.write(|w| unsafe { + device.uartfbrd().write(|w| unsafe { w.baud_divfrac().bits(baud_div_frac as u8); w }); // PL011 needs a (dummy) line control register write to latch in the // divisors. We don't want to actually change LCR contents here. - device.uartlcr_h.modify(|_, w| w); + device.uartlcr_h().modify(|_, w| w); Ok(HertzU32::from_raw( (4 * frequency.to_Hz()) / (64 * baud_div_int as u32 + baud_div_frac as u32), diff --git a/rp2040-hal/src/uart/reader.rs b/rp2040-hal/src/uart/reader.rs index 18fbb36f6..0a86431b9 100644 --- a/rp2040-hal/src/uart/reader.rs +++ b/rp2040-hal/src/uart/reader.rs @@ -50,7 +50,7 @@ impl Error for ReadErrorType { } pub(crate) fn is_readable(device: &D) -> bool { - device.uartfr.read().rxfe().bit_is_clear() + device.uartfr().read().rxfe().bit_is_clear() } /// Enable/disable the rx/tx FIFO @@ -60,9 +60,9 @@ pub(crate) fn is_readable(device: &D) -> bool { /// Default is false pub fn set_fifos(rb: &RegisterBlock, enable: bool) { if enable { - rb.uartlcr_h.modify(|_r, w| w.fen().set_bit()) + rb.uartlcr_h().modify(|_r, w| w.fen().set_bit()) } else { - rb.uartlcr_h.modify(|_r, w| w.fen().clear_bit()) + rb.uartlcr_h().modify(|_r, w| w.fen().clear_bit()) } } @@ -77,7 +77,8 @@ pub fn set_rx_watermark(rb: &RegisterBlock, watermark: FifoWatermark) { FifoWatermark::Bytes24 => 3, FifoWatermark::Bytes28 => 4, }; - rb.uartifls.modify(|_r, w| unsafe { w.rxiflsel().bits(wm) }); + rb.uartifls() + .modify(|_r, w| unsafe { w.rxiflsel().bits(wm) }); } /// Enables the Receive Interrupt. @@ -92,7 +93,7 @@ pub(crate) fn enable_rx_interrupt(rb: &RegisterBlock) { // when the RX FIFO is non-empty, but 32-bit periods have passed with // no further data. This means we don't have to interrupt on every // single byte, but can make use of the hardware FIFO. - rb.uartimsc.modify(|_r, w| { + rb.uartimsc().modify(|_r, w| { w.rxim().set_bit(); w.rtim().set_bit(); w @@ -104,7 +105,7 @@ pub(crate) fn disable_rx_interrupt(rb: &RegisterBlock) { // Access the UART Interrupt Mask Set/Clear register. Setting a bit // low disables the interrupt. - rb.uartimsc.modify(|_r, w| { + rb.uartimsc().modify(|_r, w| { w.rxim().clear_bit(); w.rtim().clear_bit(); w @@ -129,7 +130,7 @@ pub(crate) fn read_raw<'b, D: UartDevice>( if bytes_read < buffer.len() { let mut error: Option = None; - let read = device.uartdr.read(); + let read = device.uartdr().read(); // If multiple status bits are set, report // the most serious or most specific condition, @@ -243,7 +244,7 @@ unsafe impl> ReadTarget for Reader { } fn rx_address_count(&self) -> (u32, u32) { - (&self.device.uartdr as *const _ as u32, u32::MAX) + (self.device.uartdr() as *const _ as u32, u32::MAX) } fn rx_increment(&self) -> bool { diff --git a/rp2040-hal/src/uart/writer.rs b/rp2040-hal/src/uart/writer.rs index 326c2f610..505468474 100644 --- a/rp2040-hal/src/uart/writer.rs +++ b/rp2040-hal/src/uart/writer.rs @@ -22,14 +22,15 @@ pub fn set_tx_watermark(rb: &RegisterBlock, watermark: FifoWatermark) { FifoWatermark::Bytes24 => 1, FifoWatermark::Bytes28 => 0, }; - rb.uartifls.modify(|_r, w| unsafe { w.txiflsel().bits(wm) }); + rb.uartifls() + .modify(|_r, w| unsafe { w.txiflsel().bits(wm) }); } /// Returns `Err(WouldBlock)` if the UART is still busy transmitting data. /// It returns Ok(()) when the TX fifo and the transmit shift register are empty /// and the last stop bit is sent. pub(crate) fn transmit_flushed(rb: &RegisterBlock) -> nb::Result<(), Infallible> { - if rb.uartfr.read().busy().bit_is_set() { + if rb.uartfr().read().busy().bit_is_set() { Err(WouldBlock) } else { Ok(()) @@ -38,13 +39,13 @@ pub(crate) fn transmit_flushed(rb: &RegisterBlock) -> nb::Result<(), Infallible> /// Returns `true` if the TX FIFO has space, or false if it is full pub(crate) fn uart_is_writable(rb: &RegisterBlock) -> bool { - rb.uartfr.read().txff().bit_is_clear() + rb.uartfr().read().txff().bit_is_clear() } /// Returns `true` if the UART is busy transmitting data, `false` after all /// bits (including stop bits) have been transmitted. pub(crate) fn uart_is_busy(rb: &RegisterBlock) -> bool { - rb.uartfr.read().busy().bit_is_set() + rb.uartfr().read().busy().bit_is_set() } /// Writes bytes to the UART. @@ -70,7 +71,7 @@ pub(crate) fn write_raw<'d>( } } - rb.uartdr.write(|w| unsafe { + rb.uartdr().write(|w| unsafe { w.data().bits(*c); w }); @@ -103,7 +104,8 @@ pub(crate) fn enable_tx_interrupt(rb: &RegisterBlock) { // to be when it's half-empty.. // 2 means '<= 1/2 full'. - rb.uartifls.modify(|_r, w| unsafe { w.txiflsel().bits(2) }); + rb.uartifls() + .modify(|_r, w| unsafe { w.txiflsel().bits(2) }); // Access the UART Interrupt Mask Set/Clear register. Setting a bit // high enables the interrupt. @@ -112,7 +114,7 @@ pub(crate) fn enable_tx_interrupt(rb: &RegisterBlock) { // the TX FIFO level is triggered. This means we don't have to // interrupt on every single byte, but can make use of the hardware // FIFO. - rb.uartimsc.modify(|_r, w| { + rb.uartimsc().modify(|_r, w| { w.txim().set_bit(); w }); @@ -123,7 +125,7 @@ pub(crate) fn disable_tx_interrupt(rb: &RegisterBlock) { // Access the UART Interrupt Mask Set/Clear register. Setting a bit // low disables the interrupt. - rb.uartimsc.modify(|_r, w| { + rb.uartimsc().modify(|_r, w| { w.txim().clear_bit(); w }); @@ -198,7 +200,7 @@ unsafe impl> WriteTarget for Writer { } fn tx_address_count(&mut self) -> (u32, u32) { - (&self.device.uartdr as *const _ as u32, u32::MAX) + (self.device.uartdr() as *const _ as u32, u32::MAX) } fn tx_increment(&self) -> bool { diff --git a/rp2040-hal/src/usb.rs b/rp2040-hal/src/usb.rs index d0dcbb8fa..4d6afd75f 100644 --- a/rp2040-hal/src/usb.rs +++ b/rp2040-hal/src/usb.rs @@ -273,13 +273,19 @@ impl Inner { fn ep_reset_all(&mut self) { self.ctrl_reg - .sie_ctrl + .sie_ctrl() .modify(|_, w| w.ep0_int_1buf().set_bit()); // expect ctrl ep to receive on DATA first - self.ctrl_dpram.ep_buffer_control[0].write(|w| w.pid_0().set_bit()); - self.ctrl_dpram.ep_buffer_control[1].write(|w| w.pid_0().set_bit()); + self.ctrl_dpram + .ep_buffer_control(0) + .write(|w| w.pid_0().set_bit()); + self.ctrl_dpram + .ep_buffer_control(1) + .write(|w| w.pid_0().set_bit()); cortex_m::asm::delay(12); - self.ctrl_dpram.ep_buffer_control[1].write(|w| w.available_0().set_bit()); + self.ctrl_dpram + .ep_buffer_control(1) + .write(|w| w.available_0().set_bit()); for (index, ep) in itertools::interleave( self.in_endpoints.iter().skip(1), // skip control endpoint @@ -297,14 +303,14 @@ impl Inner { }; // configure // ep 0 in&out are not part of index (skipped before enumeration) - self.ctrl_dpram.ep_control[index].modify(|_, w| unsafe { + self.ctrl_dpram.ep_control(index).modify(|_, w| unsafe { w.endpoint_type().variant(ep_type); w.interrupt_per_buff().set_bit(); w.enable().set_bit(); w.buffer_address().bits(0x180 + (ep.buffer_offset << 6)) }); // reset OUT ep and prepare IN ep to accept data - let buf_control = &self.ctrl_dpram.ep_buffer_control[index + 2]; + let buf_control = &self.ctrl_dpram.ep_buffer_control(index + 2); if (index & 1) == 0 { // first write occur on DATA0 so prepare the pid bit to be flipped buf_control.write(|w| w.pid_0().set_bit()); @@ -327,7 +333,7 @@ impl Inner { .and_then(Option::as_mut) .ok_or(UsbError::InvalidEndpoint)?; - let buf_control = &self.ctrl_dpram.ep_buffer_control[index * 2]; + let buf_control = &self.ctrl_dpram.ep_buffer_control(index * 2); if buf_control.read().available_0().bit_is_set() { return Err(UsbError::WouldBlock); } @@ -357,7 +363,7 @@ impl Inner { .and_then(Option::as_mut) .ok_or(UsbError::InvalidEndpoint)?; - let buf_control = &self.ctrl_dpram.ep_buffer_control[index * 2 + 1]; + let buf_control = &self.ctrl_dpram.ep_buffer_control(index * 2 + 1); let buf_control_val = buf_control.read(); let process_setup = index == 0 && self.read_setup; @@ -375,14 +381,16 @@ impl Inner { buf[..len].copy_from_slice(&ep_buf[..len]); // Next packet will be on DATA1 so clear pid_0 so it gets flipped by next buf config - self.ctrl_dpram.ep_buffer_control[0].modify(|_, w| w.pid_0().clear_bit()); + self.ctrl_dpram + .ep_buffer_control(0) + .modify(|_, w| w.pid_0().clear_bit()); // clear setup request flag self.ctrl_reg - .sie_status + .sie_status() .write(|w| w.setup_rec().clear_bit_by_one()); // clear any out standing out flag e.g. in case a zlp got discarded - self.ctrl_reg.buff_status.write(|w| unsafe { w.bits(2) }); + self.ctrl_reg.buff_status().write(|w| unsafe { w.bits(2) }); let is_in_request = (buf[0] & 0x80) == 0x80; let data_length = u16::from(buf[6]) | (u16::from(buf[7]) << 8); @@ -411,7 +419,7 @@ impl Inner { buf[..len].copy_from_slice(&ep.get_buf()[..len]); // Clear OUT flag once it is read. self.ctrl_reg - .buff_status + .buff_status() .write(|w| unsafe { w.bits(1 << (index * 2 + 1)) }); buf_control.modify(|r, w| unsafe { @@ -460,18 +468,18 @@ impl UsbBus { raw_ctrl_pdram.fill(0); } - ctrl_reg.usb_muxing.modify(|_, w| { + ctrl_reg.usb_muxing().modify(|_, w| { w.to_phy().set_bit(); w.softcon().set_bit() }); if force_vbus_detect_bit { - ctrl_reg.usb_pwr.modify(|_, w| { + ctrl_reg.usb_pwr().modify(|_, w| { w.vbus_detect().set_bit(); w.vbus_detect_override_en().set_bit() }); } - ctrl_reg.main_ctrl.modify(|_, w| { + ctrl_reg.main_ctrl().modify(|_, w| { w.sim_timing().clear_bit(); w.host_ndevice().clear_bit(); w.controller_en().set_bit() @@ -486,7 +494,10 @@ impl UsbBus { pub fn remote_wakeup(&self) { critical_section::with(|cs| { let inner = self.inner.borrow(cs).borrow_mut(); - inner.ctrl_reg.sie_ctrl.modify(|_, w| w.resume().set_bit()); + inner + .ctrl_reg + .sie_ctrl() + .modify(|_, w| w.resume().set_bit()); }); } @@ -527,7 +538,7 @@ impl UsbBusTrait for UsbBus { // Enable interrupt generation when a buffer is done, when the bus is reset, // and when a setup packet is received // this should be sufficient for device mode, will need more for host. - inner.ctrl_reg.inte.modify(|_, w| { + inner.ctrl_reg.inte().modify(|_, w| { w.buff_status() .set_bit() .bus_reset() @@ -543,7 +554,7 @@ impl UsbBusTrait for UsbBus { // enable pull up to let the host know we exist. inner .ctrl_reg - .sie_ctrl + .sie_ctrl() .modify(|_, w| w.pullup_en().set_bit()); }) } @@ -554,18 +565,18 @@ impl UsbBusTrait for UsbBus { // clear reset flag inner .ctrl_reg - .sie_status + .sie_status() .write(|w| w.bus_reset().clear_bit_by_one()); inner .ctrl_reg - .buff_status + .buff_status() .write(|w| unsafe { w.bits(0xFFFF_FFFF) }); // reset all endpoints inner.ep_reset_all(); // Reset address register - inner.ctrl_reg.addr_endp.reset(); + inner.ctrl_reg.addr_endp().reset(); // TODO: RP2040-E5: work around implementation // TODO: reset all endpoints & buffer statuses }) @@ -575,11 +586,17 @@ impl UsbBusTrait for UsbBus { let inner = self.inner.borrow(cs).borrow_mut(); inner .ctrl_reg - .addr_endp + .addr_endp() .modify(|_, w| unsafe { w.address().bits(addr & 0x7F) }); // reset ep0 - inner.ctrl_dpram.ep_buffer_control[0].modify(|_, w| w.pid_0().set_bit()); - inner.ctrl_dpram.ep_buffer_control[1].modify(|_, w| w.pid_0().set_bit()); + inner + .ctrl_dpram + .ep_buffer_control(0) + .modify(|_, w| w.pid_0().set_bit()); + inner + .ctrl_dpram + .ep_buffer_control(1) + .modify(|_, w| w.pid_0().set_bit()); }) } fn write(&self, ep_addr: EndpointAddress, buf: &[u8]) -> UsbResult { @@ -599,7 +616,7 @@ impl UsbBusTrait for UsbBus { let inner = self.inner.borrow(cs).borrow_mut(); if ep_addr.index() == 0 { - inner.ctrl_reg.ep_stall_arm.modify(|_, w| { + inner.ctrl_reg.ep_stall_arm().modify(|_, w| { if ep_addr.is_in() { w.ep0_in().bit(stalled) } else { @@ -609,14 +626,19 @@ impl UsbBusTrait for UsbBus { } let index = ep_addr_to_ep_buf_ctrl_idx(ep_addr); - inner.ctrl_dpram.ep_buffer_control[index].modify(|_, w| w.stall().bit(stalled)); + inner + .ctrl_dpram + .ep_buffer_control(index) + .modify(|_, w| w.stall().bit(stalled)); }) } fn is_stalled(&self, ep_addr: EndpointAddress) -> bool { critical_section::with(|cs| { let inner = self.inner.borrow(cs).borrow_mut(); let index = ep_addr_to_ep_buf_ctrl_idx(ep_addr); - inner.ctrl_dpram.ep_buffer_control[index] + inner + .ctrl_dpram + .ep_buffer_control(index) .read() .stall() .bit_is_set() @@ -641,12 +663,18 @@ impl UsbBusTrait for UsbBus { } // check for bus reset and/or suspended states. - let ints = inner.ctrl_reg.ints.read(); - let mut buff_status = inner.ctrl_reg.buff_status.read().bits(); + let ints = inner.ctrl_reg.ints().read(); + let mut buff_status = inner.ctrl_reg.buff_status().read().bits(); if ints.bus_reset().bit_is_set() { #[cfg(feature = "rp2040-e5")] - if inner.ctrl_reg.sie_status.read().connected().bit_is_clear() { + if inner + .ctrl_reg + .sie_status() + .read() + .connected() + .bit_is_clear() + { inner.errata5_state = Some(errata5::Errata5State::start()); return PollResult::None; } else { @@ -659,13 +687,13 @@ impl UsbBusTrait for UsbBus { if ints.dev_suspend().bit_is_set() { inner .ctrl_reg - .sie_status + .sie_status() .write(|w| w.suspended().clear_bit_by_one()); return PollResult::Suspend; } else if ints.dev_resume_from_host().bit_is_set() { inner .ctrl_reg - .sie_status + .sie_status() .write(|w| w.resume().clear_bit_by_one()); return PollResult::Resume; } @@ -677,7 +705,7 @@ impl UsbBusTrait for UsbBus { // IN Complete shall only be reported once. inner .ctrl_reg - .buff_status + .buff_status() .write(|w| unsafe { w.bits(0x5555_5555) }); for i in 0..32u32 { @@ -698,7 +726,10 @@ impl UsbBusTrait for UsbBus { // check for setup request if ints.setup_req().bit_is_set() { // Small max_packet_size_ep0 Work-Around - inner.ctrl_dpram.ep_buffer_control[0].modify(|_, w| w.available_0().clear_bit()); + inner + .ctrl_dpram + .ep_buffer_control(0) + .modify(|_, w| w.available_0().clear_bit()); ep_setup |= 1; inner.read_setup = true; diff --git a/rp2040-hal/src/usb/errata5.rs b/rp2040-hal/src/usb/errata5.rs index 5c22a7623..5ba9b084c 100644 --- a/rp2040-hal/src/usb/errata5.rs +++ b/rp2040-hal/src/usb/errata5.rs @@ -29,9 +29,9 @@ impl Errata5State { let pac = crate::pac::Peripherals::steal(); match self { Self::WaitEndOfReset => { - if pac.SYSINFO.chip_id.read().revision().bits() >= 2 { + if pac.SYSINFO.chip_id().read().revision().bits() >= 2 { None - } else if pac.USBCTRL_REGS.sie_status.read().line_state().is_se0() { + } else if pac.USBCTRL_REGS.sie_status().read().line_state().is_se0() { Some(self) } else { Some(Self::ForceLineStateJ(start_force_j(&pac))) @@ -40,7 +40,7 @@ impl Errata5State { Self::ForceLineStateJ(ref state) => { if pac .USBCTRL_REGS - .sie_status + .sie_status() .read() .connected() .bit_is_clear() @@ -59,7 +59,7 @@ impl Errata5State { pub fn check_bank0_reset() { // SAFETY: Only used for reading the reset state. let pac = unsafe { crate::pac::Peripherals::steal() }; - let reset_state = pac.RESETS.reset.read(); + let reset_state = pac.RESETS.reset().read(); assert!( reset_state.io_bank0().bit_is_clear() && reset_state.pads_bank0().bit_is_clear(), "IO Bank 0 must be out of reset for this work around to function properly." @@ -71,37 +71,37 @@ const DP_PULLUP_EN_FLAG: u32 = 0x0000_0002; const DP_PULLUP_EN_OVERRIDE_FLAG: u32 = 0x0000_0004; fn start_force_j(pac: &Peripherals) -> ForceLineStateJ { - let pads = &pac.PADS_BANK0.gpio[15]; - let io = &pac.IO_BANK0.gpio[15]; + let pads = &pac.PADS_BANK0.gpio(15); + let io = &pac.IO_BANK0.gpio(15); let usb_ctrl = &pac.USBCTRL_REGS; - assert!(!usb_ctrl.sie_status.read().line_state().is_se0()); + assert!(!usb_ctrl.sie_status().read().line_state().is_se0()); assert!( - pac.IO_BANK0.gpio[16].gpio_ctrl.read().funcsel().bits() != 8, + pac.IO_BANK0.gpio(16).gpio_ctrl().read().funcsel().bits() != 8, "Not expecting DM to be function 8" ); // backup io ctrl & pad ctrl let prev_pads = pads.read().bits(); - let prev_io_ctrls = io.gpio_ctrl.read().bits(); + let prev_io_ctrls = io.gpio_ctrl().read().bits(); // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect // pin state pads.modify(|_, w| w.pue().set_bit().pde().set_bit()); - io.gpio_ctrl.modify(|_, w| w.oeover().disable()); + io.gpio_ctrl().modify(|_, w| w.oeover().disable()); // Select function 8 (USB debug muxing) without disturbing other controls - io.gpio_ctrl.modify(|_, w| unsafe { w.funcsel().bits(8) }); + io.gpio_ctrl().modify(|_, w| unsafe { w.funcsel().bits(8) }); // J state is a differential 1 for a full speed device so // DP = 1 and DM = 0. Don't actually need to set DM low as it // is already gated assuming it isn't funcseld. - io.gpio_ctrl.modify(|_, w| w.inover().high()); + io.gpio_ctrl().modify(|_, w| w.inover().high()); // Force PHY pull up to stay before switching away from the phy unsafe { - let usbphy_direct = usb_ctrl.usbphy_direct.as_ptr(); - let usbphy_direct_override = usb_ctrl.usbphy_direct_override.as_ptr(); + let usbphy_direct = usb_ctrl.usbphy_direct().as_ptr(); + let usbphy_direct_override = usb_ctrl.usbphy_direct_override().as_ptr(); write_bitmask_set(usbphy_direct, DP_PULLUP_EN_FLAG); write_bitmask_set(usbphy_direct_override, DP_PULLUP_EN_OVERRIDE_FLAG); } @@ -109,13 +109,13 @@ fn start_force_j(pac: &Peripherals) -> ForceLineStateJ { // Switch to GPIO phy with LS_J forced unsafe { usb_ctrl - .usb_muxing + .usb_muxing() .write_with_zero(|w| w.to_digital_pad().set_bit().softcon().set_bit()); } // LS_J is now forced, wait until the signal propagates through the usb logic. loop { - let status = usb_ctrl.sie_status.read(); + let status = usb_ctrl.sie_status().read(); if status.line_state().is_j() { break; } @@ -127,21 +127,21 @@ fn start_force_j(pac: &Peripherals) -> ForceLineStateJ { } } fn finish(pac: &Peripherals, prev_pads: u32, prev_io_ctrls: u32) { - let pads = &pac.PADS_BANK0.gpio[15]; - let io = &pac.IO_BANK0.gpio[15]; + let pads = &pac.PADS_BANK0.gpio(15); + let io = &pac.IO_BANK0.gpio(15); // Switch back to USB phy pac.USBCTRL_REGS - .usb_muxing + .usb_muxing() .write(|w| w.to_phy().set_bit().softcon().set_bit()); // Get rid of DP pullup override unsafe { - let usbphy_direct_override = pac.USBCTRL_REGS.usbphy_direct_override.as_ptr(); + let usbphy_direct_override = pac.USBCTRL_REGS.usbphy_direct_override().as_ptr(); write_bitmask_clear(usbphy_direct_override, DP_PULLUP_EN_OVERRIDE_FLAG); // Finally, restore the gpio ctrl value back to GPIO15 - io.gpio_ctrl.write(|w| w.bits(prev_io_ctrls)); + io.gpio_ctrl().write(|w| w.bits(prev_io_ctrls)); // Restore the pad ctrl value pads.write(|w| w.bits(prev_pads)); } diff --git a/rp2040-hal/src/vector_table.rs b/rp2040-hal/src/vector_table.rs index c39827b2e..8bc33a78e 100644 --- a/rp2040-hal/src/vector_table.rs +++ b/rp2040-hal/src/vector_table.rs @@ -43,7 +43,7 @@ impl VectorTable { #[allow(unknown_lints)] #[allow(clippy::needless_pass_by_ref_mut)] pub fn init(&mut self, ppb: &mut crate::pac::PPB) { - let vector_table = ppb.vtor.read().bits(); + let vector_table = ppb.vtor().read().bits(); unsafe { crate::rom_data::memcpy44( &mut self.table as *mut _ as *mut u32, @@ -82,7 +82,7 @@ impl VectorTable { #[allow(unknown_lints)] #[allow(clippy::needless_pass_by_ref_mut)] pub unsafe fn activate(&mut self, ppb: &mut crate::pac::PPB) { - ppb.vtor + ppb.vtor() .write(|w| w.bits(&mut self.table as *mut _ as *mut u32 as u32)); } } diff --git a/rp2040-hal/src/watchdog.rs b/rp2040-hal/src/watchdog.rs index 6969c3551..31e35d550 100644 --- a/rp2040-hal/src/watchdog.rs +++ b/rp2040-hal/src/watchdog.rs @@ -79,7 +79,7 @@ impl Watchdog { const WATCHDOG_TICK_ENABLE_BITS: u32 = 0x200; self.watchdog - .tick + .tick() .write(|w| unsafe { w.bits(WATCHDOG_TICK_ENABLE_BITS | cycles as u32) }) } @@ -90,7 +90,7 @@ impl Watchdog { /// /// * `pause` - If true, watchdog timer will be paused pub fn pause_on_debug(&mut self, pause: bool) { - self.watchdog.ctrl.write(|w| { + self.watchdog.ctrl().write(|w| { w.pause_dbg0() .bit(pause) .pause_dbg1() @@ -101,38 +101,54 @@ impl Watchdog { } fn load_counter(&self, counter: u32) { - self.watchdog.load.write(|w| unsafe { w.bits(counter) }); + self.watchdog.load().write(|w| unsafe { w.bits(counter) }); } fn enable(&self, bit: bool) { - self.watchdog.ctrl.write(|w| w.enable().bit(bit)) + self.watchdog.ctrl().write(|w| w.enable().bit(bit)) } /// Read a scratch register pub fn read_scratch(&self, reg: ScratchRegister) -> u32 { match reg { - ScratchRegister::Scratch0 => self.watchdog.scratch0.read().bits(), - ScratchRegister::Scratch1 => self.watchdog.scratch1.read().bits(), - ScratchRegister::Scratch2 => self.watchdog.scratch2.read().bits(), - ScratchRegister::Scratch3 => self.watchdog.scratch3.read().bits(), - ScratchRegister::Scratch4 => self.watchdog.scratch4.read().bits(), - ScratchRegister::Scratch5 => self.watchdog.scratch5.read().bits(), - ScratchRegister::Scratch6 => self.watchdog.scratch6.read().bits(), - ScratchRegister::Scratch7 => self.watchdog.scratch7.read().bits(), + ScratchRegister::Scratch0 => self.watchdog.scratch0().read().bits(), + ScratchRegister::Scratch1 => self.watchdog.scratch1().read().bits(), + ScratchRegister::Scratch2 => self.watchdog.scratch2().read().bits(), + ScratchRegister::Scratch3 => self.watchdog.scratch3().read().bits(), + ScratchRegister::Scratch4 => self.watchdog.scratch4().read().bits(), + ScratchRegister::Scratch5 => self.watchdog.scratch5().read().bits(), + ScratchRegister::Scratch6 => self.watchdog.scratch6().read().bits(), + ScratchRegister::Scratch7 => self.watchdog.scratch7().read().bits(), } } /// Write a scratch register pub fn write_scratch(&mut self, reg: ScratchRegister, value: u32) { match reg { - ScratchRegister::Scratch0 => self.watchdog.scratch0.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch1 => self.watchdog.scratch1.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch2 => self.watchdog.scratch2.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch3 => self.watchdog.scratch3.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch4 => self.watchdog.scratch4.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch5 => self.watchdog.scratch5.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch6 => self.watchdog.scratch6.write(|w| unsafe { w.bits(value) }), - ScratchRegister::Scratch7 => self.watchdog.scratch7.write(|w| unsafe { w.bits(value) }), + ScratchRegister::Scratch0 => { + self.watchdog.scratch0().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch1 => { + self.watchdog.scratch1().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch2 => { + self.watchdog.scratch2().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch3 => { + self.watchdog.scratch3().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch4 => { + self.watchdog.scratch4().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch5 => { + self.watchdog.scratch5().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch6 => { + self.watchdog.scratch6().write(|w| unsafe { w.bits(value) }) + } + ScratchRegister::Scratch7 => { + self.watchdog.scratch7().write(|w| unsafe { w.bits(value) }) + } } } @@ -143,7 +159,7 @@ impl Watchdog { /// This is easy at the moment, since nothing else uses PSM unsafe fn configure_wdog_reset_triggers(&self) { let psm = &*pac::PSM::ptr(); - psm.wdsel.write_with_zero(|w| { + psm.wdsel().write_with_zero(|w| { w.bits(0x0001ffff); w.xosc().clear_bit(); w.rosc().clear_bit(); diff --git a/rp2040-hal/src/xosc.rs b/rp2040-hal/src/xosc.rs index 5ee008535..3a52f8bbe 100644 --- a/rp2040-hal/src/xosc.rs +++ b/rp2040-hal/src/xosc.rs @@ -136,7 +136,7 @@ impl CrystalOscillator { return Err(Error::BadArgument); } - self.device.ctrl.write(|w| { + self.device.ctrl().write(|w| { w.freq_range()._1_15mhz(); w }); @@ -151,12 +151,12 @@ impl CrystalOscillator { //Then we check if it fits into an u16. let startup_delay: u16 = startup_delay.try_into().map_err(|_| Error::BadArgument)?; - self.device.startup.write(|w| unsafe { + self.device.startup().write(|w| unsafe { w.delay().bits(startup_delay); w }); - self.device.ctrl.write(|w| { + self.device.ctrl().write(|w| { w.enable().enable(); w }); @@ -173,7 +173,7 @@ pub struct StableOscillatorToken { impl CrystalOscillator { /// One has to wait for the startup delay before using the oscillator, ie awaiting stablilzation of the XOSC pub fn await_stabilization(&self) -> nb::Result { - if self.device.status.read().stable().bit_is_clear() { + if self.device.status().read().stable().bit_is_clear() { return Err(WouldBlock); } @@ -195,7 +195,7 @@ impl CrystalOscillator { /// Disables the XOSC pub fn disable(self) -> CrystalOscillator { - self.device.ctrl.modify(|_r, w| { + self.device.ctrl().modify(|_r, w| { w.enable().disable(); w }); @@ -214,7 +214,7 @@ impl CrystalOscillator { //taken from the C SDK const XOSC_DORMANT_VALUE: u32 = 0x636f6d61; - self.device.dormant.write(|w| { + self.device.dormant().write(|w| { w.bits(XOSC_DORMANT_VALUE); w });