Populate mtval with instruction bytes on illegal instruction traps

[michaeljclark]

Populating mtval/stval with instruction bytes on illegal instruction traps is an optional feature.

We should add RISCV_FEATURE_MTVAL_INST to target/riscv/cpu.h and let cpus set this in their init functions so that we can model CPUs that don't support setting mtval/stval on illegal instructions.

Currently, mtval/stval is set to zero on all synchronous exceptions that don't have address info (load/store/amo/fetch access faults and page faults). This is for privileged isa v1.10 compliance. In privileged isa v1.9.1 mbadaddr/sbadaddr was only populated on exceptions with address info.