v3.1.1: Cluster reset

Fixed

• Fix cdc reset signal for cluster

v3.1.0: Simulation stdout

Changed

• Added simulation stdout (replacing the hierarchical access in the tb hack)

Removed

• Removed apb_timer (duplicate)

v3.0.1: Dependency fixes

Fixed

• ips_list.yml has missing domain tags causing trouble with the FPGA flow
• Bumped fpnew for common_cells deps

v3.0.0: Major overhaul

Added

• Added support for Hyperbus. pulp_soc now supports booting from HyperFlash memory

Changed

• Increase size of boot_mode signal to 2-bit to accomodate the new Hyperbus bootmode
• Bumped riscv_dbg IP Version to 0.4.1
• Switched to new AXI CDC IPs between SoC and Cluster
• Switched to common cells CDC for cluster event exchange
• Bumped axi IP Version to 0.29.1
• Reduced latency of APB and AXI transactions
• Bumped register interface IP Version to 0.3.1
• Bumped cv32e40p IP Version to pulpissimo-v3.4.0-rev3
• Bumped udma_core IP version to 1.1.0
• Switched to new I2C peripheral version with command stream interface

Removed

• Removed APB Bus interface from repository. The identical version defined in the APB depedency is now used
• Removed dependency to archived legacy axi_slice_dc
• Removed ifdef for separate FPGA RAM instantiation. This is now supposed to be handled by tc_sram wrapping a Xilinx XPM.

Fixed

• Fixed Genus SystemVerilog incompatibility in soc_interconnect

v2.1.0: Bender and Ibex support

Added

• Added Bender.yml file for bender compatibility
• Added obi_pulp_adapter

Changed

• updated ibex
• change from deprecated generic_memory to tc_sram tech cell, bump tech_cells_generic accordingly
• Expose L2 Bank sizes to improve consistency
• updated apb_fll_if, removed local interface definition to use the one defined externally
• updated hwpe-mac-engine

v2.0.1: Fix Interconnect Addressing Issues

Changed

• Changed address aliasing rules to be identical to the behavior of the legacy
  interconnect.

Fixed

• Fix wrong address part select in SRAM wrappers that caused part of the
  memories to be inaccessible and alias into lower address ranges.

v2.0.0: Major interconnect changes

Added

• Completely replaced soc_interconnect with a new parametric version
• Added AXI Crossbar to soc_interconnect to attach custom IPs
• Added new pulp_soc parameter to isolate the axi plug CDC fifo in case it is not needed
• Add register_interface as dependency to simplify integration of custom ip using reggen
• Properly assert r_opc signal in new interconnect to indicate bus errors
• Add error checking for illegal access on HWPE ports which only have access to L2 interleaved memory

Changed

• AXI ID width of cluster plugs are now set to actually required width instead of a hardcoded one
• TCDM protocol to SRAM specific protocol is moved from interconnect to memory bank module

Removed

• obsolete axi_node dependency
• obsolete header files

v1.4.2: Zfinx patch on latest SoC version (#34)

* Zfinx patch on latest SoC version

* indentation errors fix

* indentation misalignemts solved