diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index 7db655b5..31c316bb 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -27,6 +27,8 @@ jobs: # Exclude generated headers (no license checker support for optional lines) exclude_paths: | sw/include/regs/*.h + sw/include/tasi.h + sw/tests/bare-metal/hostd/tasi_* .dir-locals.el utils/* scripts/* diff --git a/Bender.local b/Bender.local index 56685400..9e2c1825 100644 --- a/Bender.local +++ b/Bender.local @@ -19,5 +19,4 @@ overrides: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git" , version: =0.0.0-alpha.8 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git" , version: 0.4.4 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git" , version: 1.37.0 } # branch: master - + common_cells: { git: "https://github.com/pulp-platform/common_cells.git" , version: 1.37.0 } \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index a36bf3b2..a5494d51 100644 --- a/Bender.lock +++ b/Bender.lock @@ -22,8 +22,8 @@ packages: - apb - register_interface axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 + version: 0.39.4 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -544,6 +544,12 @@ packages: - hwpe-ctrl - hwpe-stream - ibex + spacewire: + revision: 4e8ad9fc08c25e6d8db60d6abdcc1310a4c0b289 + version: null + source: + Git: git@gitlab.thalesdigital.io:musa/spacewire.git + dependencies: [] spatz: revision: 98de97f24fe42675c9b4a8cc08354a03af57400a version: null @@ -558,6 +564,12 @@ packages: - register_interface - riscv-dbg - tech_cells_generic + streamer: + revision: f5594d3cf7325ed941a88a796a47484e1f8ebacd + version: null + source: + Git: git@gitlab.thalesdigital.io:musa/streamer.git + dependencies: [] tagger: revision: b288376b65b6bbd5feea196bb3c220f783d96e29 version: null diff --git a/Bender.yml b/Bender.yml index 45f1bf75..bec11ff7 100644 --- a/Bender.yml +++ b/Bender.yml @@ -28,6 +28,8 @@ dependencies: common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 1f8f1776ec494773f8e6c48e16685eb35d5f445e } # branch: handshake riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 } + streamer: { git: git@gitlab.thalesdigital.io:musa/streamer.git, rev: f5594d3cf7325ed941a88a796a47484e1f8ebacd } # branch: yt/synth-1 + spacewire: { git: git@gitlab.thalesdigital.io:musa/spacewire.git, rev: 4e8ad9fc08c25e6d8db60d6abdcc1310a4c0b289 } # branch: yt/synth workspace: package_links: @@ -44,6 +46,10 @@ sources: files: - hw/configs/carfield_l2dual_secure_pulp_periph_can.sv + - target: carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw + files: + - hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv + - target: carfield_l2dual_safe_secure_pulp_spatz_periph_can files: - hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv @@ -115,6 +121,7 @@ sources: files: - tech/sourcecode/tc_clk.sv - tech/sourcecode/tc_sram.sv + - tech/sourcecode/ptme_ram.sv - tech/sourcecode/configurable_delay.sv - target/synth/src/carfield_synth_wrap.sv @@ -132,8 +139,10 @@ sources: - tech/sourcecode/macros/sram_dp_hse_rvt_mvt_16384x8m16b8w1.v - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_2560x76m4b4w0.v - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_4096x76m4b4w0.v + - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_16384x39m8b8w0.v - tech/sourcecode/tc_clk.sv - tech/sourcecode/tc_sram.sv + - tech/sourcecode/ptme_ram.sv - target: all(xilinx, fpga, xilinx_vanilla) files: diff --git a/bender-common.mk b/bender-common.mk index 0f12d785..7c61b849 100644 --- a/bender-common.mk +++ b/bender-common.mk @@ -6,7 +6,7 @@ # Author: Matteo Perotti # Runtime-selectable Carfield configuration -CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can +CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw # bender targets common_targs += -t cva6 diff --git a/carfield.mk b/carfield.mk index 9969e6d0..d4be82d3 100644 --- a/carfield.mk +++ b/carfield.mk @@ -20,7 +20,7 @@ CAR_ROOT ?= $(shell $(BENDER) path carfield) CAR_HW_DIR := $(CAR_ROOT)/hw CAR_SW_DIR := $(CAR_ROOT)/sw -CAR_TGT_DIR := $(CAR_ROOT)/target/ +CAR_TGT_DIR := $(CAR_ROOT)/target CAR_XIL_DIR := $(CAR_TGT_DIR)/xilinx CAR_SIM_DIR := $(CAR_TGT_DIR)/sim SECD_ROOT ?= $(shell $(BENDER) path opentitan) @@ -100,6 +100,12 @@ SPATZD_MAKEDIR := $(SPATZD_ROOT)/hw/system/spatz_cluster SPATZD_BINARY ?= SPATZD_BOOTMODE ?= 0 # default jtag bootmode +# Streamer, implementing telecommand and telemetry protocols +STREAMER_ROOT ?= $(shell $(BENDER) path streamer) + +# SpaceWire IP +SPACEWIRE_ROOT ?= $(shell $(BENDER) path spacewire) + ########################### # System HW configuration # ########################### @@ -167,7 +173,7 @@ SAFED_SW_BUILD := safed-sw-build SAFED_SW_INIT := safed-sw-init endif -ifeq ($(shell echo $(SAFED_PRESENT)), 1) +ifeq ($(shell echo $(SPATZD_PRESENT)), 1) SPATZD_HW_INIT := spatzd-hw-init endif @@ -387,7 +393,7 @@ car-check-litmus-tests: $(LITMUS_WORK_DIR)/litmus.log ############## tech-repo := git@iis-git.ee.ethz.ch:Astral/gf12.git # no commit by default, change during development -tech-commit := fdb28aed61aa113a897c6840674ec9033eb1f2ed # branch: zx/ecc_llc_256x39 +tech-commit := a8c12632a9c395aed8e014d36dd88e760d8e5ddf # branch: thales tech-clone: git clone $(tech-repo) tech diff --git a/hw/carfield.sv b/hw/carfield.sv index f6aba4f8..9f3e1f13 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -142,6 +142,26 @@ module carfield output logic [HypNumPhys-1:0][7:0] hyper_dq_o, output logic [HypNumPhys-1:0] hyper_dq_oe_o, output logic [HypNumPhys-1:0] hyper_reset_no, + // TCTM Interface + input logic tc_active_i, + input logic tc_clock_i, + input logic tc_data_i, + output logic ptme_clk_o, + output logic ptme_enc_o, + output logic ptme_sync_o, + input logic ptme_ext_clk_i, + output logic [2:0] hpc_addr_o, + output logic hpc_cmd_en_o, + output logic hpc_sample_o, + output logic [1:0] llc_line_o, + input logic obt_ext_clk_i, + input logic obt_pps_in_i, + output logic obt_sync_out_o, + // SpW Interface + input logic spw_data_i, + input logic spw_strb_i, + output logic spw_data_o, + output logic spw_strb_o, `ifdef GEN_NO_HYPERBUS // LLC interface output logic [LlcArWidth-1:0] llc_ar_data, @@ -1939,11 +1959,11 @@ mailbox_unit #( ); // Carfield peripherals +logic eth_clk; if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet localparam int unsigned EthAsyncIdx = CarfieldRegBusSlvIdx.ethernet-NumSyncRegSlv; localparam int unsigned EthDivWidth = 20; localparam int unsigned DefaultEthClkDivValue = 1; - logic eth_clk; logic eth_clk_decoupled_valid, eth_clk_decoupled_ready; assign ethernet_isolate_req = car_regs_reg2hw.periph_isolate.q; @@ -2050,6 +2070,7 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet .eth_rx_irq_o ( car_eth_rx_intr ) ); end else begin : gen_no_ethernet + assign eth_clk = '0; assign ethernet_isolate_req = '0; assign car_eth_rx_intr = '0; assign eth_md_o = '0; @@ -2455,6 +2476,308 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... assign can_tx_o = '0; assign apb_mst_rsp[CanIdx] = '0; end + + // Telemetry and Telecomand IP (Streamer) + if (carfield_configuration::StreamerEnable) begin: gen_streamer + localparam int unsigned ZeroBits = Cfg.AddrWidth - AxiNarrowAddrWidth; + localparam int unsigned StreamerDivisionValueWidth = 6; // Divide up to 63 + localparam int unsigned NrStreamerApbSlaves = 2; // 0: APB2Reg; 1: APB + logic [Cfg.AddrWidth-1:0] mask_address; + logic streamer_clk; + logic streamer_clk_decoupled_valid, streamer_clk_decoupled_ready; + logic streamer_apb_demux_sel; + logic [StreamerDivisionValueWidth-1:0] streamer_clk_div_value; + + carfield_apb_req_t apb_async_req; + carfield_apb_rsp_t apb_async_rsp; + + carfield_apb_req_t [NrStreamerApbSlaves-1:0] apb_streamer_req; + carfield_apb_rsp_t [NrStreamerApbSlaves-1:0] apb_streamer_rsp; + + lossy_valid_to_stream #( + .T ( logic[StreamerDivisionValueWidth-1:0] ) + ) i_streamer_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .valid_i ( car_regs_reg2hw.streamer_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.streamer_clk_div_value.q ), + .valid_o ( streamer_clk_decoupled_valid ), + .ready_i ( streamer_clk_decoupled_ready ), + .data_o ( streamer_clk_div_value ), + .busy_o ( ) + ); + + clk_int_div #( + .DIV_VALUE_WIDTH(StreamerDivisionValueWidth), + .DEFAULT_DIV_VALUE(1), + .ENABLE_CLOCK_IN_RESET(1) + ) i_streamer_clk_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .en_i ( car_regs_reg2hw.streamer_clk_div_enable.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( streamer_clk_div_value ), + .div_valid_i ( streamer_clk_decoupled_valid ), + .div_ready_o ( streamer_clk_decoupled_ready ), + .clk_o ( streamer_clk ), + .cycl_count_o ( ) + ); + + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_streamer ( streamer_clk ); + + (* no_ungroup *) + (* no_boundary_optimization *) + apb_cdc #( + .LogDepth ( LogDepth ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ), + .addr_t ( car_nar_addrw_t ), + .data_t ( car_nar_dataw_t ), + .strb_t ( car_nar_strb_t ) + ) i_streamer_apb_cdc ( + .src_pclk_i ( periph_clk ), + .src_preset_ni ( periph_pwr_on_rst_n ), + .src_req_i ( apb_mst_req[StreamerIdx] ), + .src_resp_o ( apb_mst_rsp[StreamerIdx] ), + .dst_pclk_i ( streamer_clk ), + .dst_preset_ni ( periph_pwr_on_rst_n ), + .dst_req_o ( apb_async_req ), + .dst_resp_i ( apb_async_rsp ) + ); + + assign streamer_apb_demux_sel = + (apb_async_req.paddr < carfield_configuration::StreamerApbBase) ? 'h0 : 'h1; + + apb_demux #( + .NoMstPorts ( NrStreamerApbSlaves ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ) + ) i_streamer_apb_demux ( + .slv_req_i ( apb_async_req ), + .slv_resp_o ( apb_async_rsp ), + .mst_req_o ( apb_streamer_req ), + .mst_resp_i ( apb_streamer_rsp ), + .select_i ( streamer_apb_demux_sel ) + ); + + apb_to_reg i_streamer_apb_to_reg ( + .clk_i ( streamer_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .penable_i ( apb_streamer_req[0].penable ), + .pwrite_i ( apb_streamer_req[0].pwrite ), + .paddr_i ( apb_streamer_req[0].paddr ), + .psel_i ( apb_streamer_req[0].psel ), + .pwdata_i ( apb_streamer_req[0].pwdata ), + .prdata_o ( apb_streamer_rsp[0].prdata ), + .pready_o ( apb_streamer_rsp[0].pready ), + .pslverr_o ( apb_streamer_rsp[0].pslverr ), + .reg_o ( reg_bus_streamer ) + ); + + assign reg_bus_streamer.error = '0; + assign mask_address = {{ZeroBits{1'b0}}, reg_bus_streamer.addr}; + + TASI_top i_tctm_streamer ( + .SYS_CLK (streamer_clk), + .ASYNC_RST_N (periph_rst_n), + .APB_PADD (apb_streamer_req[1].paddr), // : in + .APB_PENABLE (apb_streamer_req[1].penable), // : in + .APB_PPROT (3'b0), // : in + .APB_PSEL (apb_streamer_req[1].psel), // : in + .APB_PSTROBE (4'b1111), // : in + .APB_PWDATA (apb_streamer_req[1].pwdata), // : in + .APB_PWRITE (apb_streamer_req[1].pwrite), // : in + .APB_PRDATA (apb_streamer_rsp[1].prdata), // : out + .APB_PREADY (apb_streamer_rsp[1].pready), // : out + .APB_PSLVERR (apb_streamer_rsp[1].pslverr), // : out + .REG_ADDR (mask_address), // : in + .REG_M_ID (3'b001), // : in + .REG_VALID (reg_bus_streamer.valid), // : in + .REG_WDATA (reg_bus_streamer.wdata), // : in + .REG_WRITE (reg_bus_streamer.write), // : in + .REG_RDATA (reg_bus_streamer.rdata), // : out + .REG_READY (reg_bus_streamer.ready), // : out + .AUEND_SDU (1'b0), // : in + .AUR_SDU (1'b0), // : in + .BIT_LOCKn (3'b0), // : in + .CLCW_C_B (1'b0), // : in + .CLCW_S_B (1'b0), // : in + .CONF_REG_ACC_ACK (1'b1), // : in + .CPDU_INPROGRESS (1'b0), // : in + .EXT_OBT_CLK (obt_ext_clk_i), // : in + .INT_PPS_IN (obt_pps_in_i), // : in + .RFAVN (1'b0), // : in + .SDU_WRONG_LENGTH (1'b0), // : in + .SYNC_RST_N (1'b1), // : in + .TC_ACTIVE (tc_active_i), // : in + .TC_CLOCK (tc_clock_i), // : in + .TC_DATA (tc_data_i), // : in + .TME_CLCW_FSR_DAT_FROM_REM_PDEC_SEC (1'b0), // : in + .TME_ENCR_UNENC_CLK (1'b0), // : in + .TME_ENCR_UNENC_OUT (1'b0), // : in + .TME_ENCR_UNENC_SYNC (1'b0), // : in + .TME_EXT_CLK (ptme_ext_clk_i), // : in + .TME_FSR_DAT_FROM_LOC_SEC (1'b0), // : in + .ANACOND_LLC_RESET (/* Not Connected */), // : out + .AUTH_SEL (/* Not Connected */), // : out + .BUSY (/* Not Connected */), // : out + + .CADUFrameMark (/* Not Connected */), // : out + .CLCWD_B (/* Not Connected */), // : out + .CONF_REG_ACC_REQ (/* Not Connected */), // : out + + .CONF_REG_ADDR_OFFSET (/* Not Connected */), // : out + + .CONF_REG_GROUP_ADDR (/* Not Connected */), // : out + + .CONF_REG_WDATA (/* Not Connected */), // : out + + .CROSSED_LCL_RESET (/* Not Connected */), // : out + .CROSSED_POWER_REARM_OUT (llc_line_o[1]), // : out + .CROSSED_RESET_OUT (/* Not Connected */), // : out + .FPEMO (/* Not Connected */), // : out + .FPRELM (/* Not Connected */), // : out + .GENERAL_INTERRUPT (car_regs_hw2reg.streamer_general_irq.d), // : out + .HPC_ADDR (hpc_addr_o), // : out + .HPC_CMD_EN (hpc_cmd_en_o), // : out + .HPC_INTERRUPT_SOURCES (/* Not Connected */), // : out + .HPC_PROTECTIONn (/* Not Connected */), // : out + .HPC_SMP (hpc_sample_o), // : out + .INH_MMA (/* Not Connected */), // : out + .LLC_INTERRUPT_SOURCES (/* Not Connected */), // : out + .LLC_IRQ_FORCE_REGISTER (/* Not Connected */), // : out + .LOC_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out + .LOC_AOCS_ON_OFFn (/* Not Connected */), // : out + .LOC_HK_ON_OFFn (/* Not Connected */), // : out + .LOC_IO_ON_OFFn (/* Not Connected */), // : out + .LOC_MCPM_ON_OFFn (/* Not Connected */), // : out + .LOC_MCPM_RESET (llc_line_o[0]), // : out + .LVDS_IF_TME_ENC_IOUT (/* Not Connected */), // : out + .LVDS_IF_TME_ENC_IQCLK (/* Not Connected */), // : out + .LVDS_IF_TME_ENC_QOUT (/* Not Connected */), // : out + .PP0Busy_N (/* Not Connected */), // : out + //.PP1Busy_N (/* Not Connected */), // : out + .PP2Busy_N (/* Not Connected */), // : out + .PP3Busy_N (/* Not Connected */), // : out + .PP4Busy_N (/* Not Connected */), // : out + .PP5Busy_N (/* Not Connected */), // : out + .PP6Busy_N (/* Not Connected */), // : out + .PPS_OUT (/* Not Connected */), // : out + .REM_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out + .REM_AOCS_ON_OFFn (/* Not Connected */), // : out + .REM_HK_ON_OFFn (/* Not Connected */), // : out + .REM_IO_ON_OFFn (/* Not Connected */), // : out + .REM_MCPM_ON_OFFn (/* Not Connected */), // : out + .RM_RECOVERY_RESET (/* Not Connected */), // : out + .RM_RESET (/* Not Connected */), // : out + .RS422_IF_TME_ENC_CLK (ptme_clk_o), // : out + .RS422_IF_TME_ENC_OUT (ptme_enc_o), // : out + .RS422_IF_TME_ENC_SYNC (ptme_sync_o), // : out + .SYNC_TO_EXT_IF (obt_sync_out_o), // : out + .TC_ONDOING (/* Not Connected */), // : out + .TC_STANDARD (/* Not Connected */), // : out + .TME_CLR_UNENC_CLK (/* Not Connected */), // : out + .TME_CLR_UNENC_EODF_TO_ADAM (/* Not Connected */), // : out + .TME_CLR_UNENC_EODF_TO_EXT (/* Not Connected */), // : out + .TME_CLR_UNENC_OUT (/* Not Connected */), // : out + .TME_CLR_UNENC_SYNC (/* Not Connected */), // : out + .TME_Cn_S (/* Not Connected */), // : out + .TME_REM_CLCWn_FSR_SEL (/* Not Connected */), // : out + .TME_TIME_STROBE_TO_REM_OBT (/* Not Connected */), // : out + .TME_UNENC_SYNC (/* Not Connected */) // : out + ); + + assign car_regs_hw2reg.streamer_general_irq.de = '1; + end else begin: gen_no_streamer + assign car_regs_hw2reg.streamer_general_irq.de = '0; + assign car_regs_hw2reg.streamer_general_irq.d = '0; + end + + // SpaceWire IP + if (carfield_configuration::SpaceWireEnable) begin: gen_spw + + localparam int unsigned SpWZeroBits = Cfg.AddrWidth - AxiNarrowAddrWidth; + localparam int unsigned NrSpaceWireApbSlaves = 2; // 0: APB2Reg; 1: APB + logic spw_apb_demux_sel; + logic [Cfg.AddrWidth-1:0] spw_address; + + carfield_apb_req_t [NrSpaceWireApbSlaves-1:0] apb_spw_req; + carfield_apb_rsp_t [NrSpaceWireApbSlaves-1:0] apb_spw_rsp; + + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_spw ( periph_clk ); + + assign spw_apb_demux_sel = + (apb_mst_req[SpaceWireIdx].paddr < carfield_configuration::SpaceWireApbBase) ? 'h0 : 'h1; + + apb_demux #( + .NoMstPorts ( NrSpaceWireApbSlaves ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ) + ) i_spw_apb_demux ( + .slv_req_i ( apb_mst_req[SpaceWireIdx] ), + .slv_resp_o ( apb_mst_rsp[SpaceWireIdx] ), + .mst_req_o ( apb_spw_req ), + .mst_resp_i ( apb_spw_rsp ), + .select_i ( spw_apb_demux_sel ) + ); + + apb_to_reg i_spw_apb_to_reg ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .penable_i ( apb_spw_req[0].penable ), + .pwrite_i ( apb_spw_req[0].pwrite ), + .paddr_i ( apb_spw_req[0].paddr ), + .psel_i ( apb_spw_req[0].psel ), + .pwdata_i ( apb_spw_req[0].pwdata ), + .prdata_o ( apb_spw_rsp[0].prdata ), + .pready_o ( apb_spw_rsp[0].pready ), + .pslverr_o ( apb_spw_rsp[0].pslverr ), + .reg_o ( reg_bus_spw ) + ); + + assign reg_bus_spw.error = '0; + + assign spw_address = {{SpWZeroBits{1'b0}}, reg_bus_spw.addr}; + + spw_astr_top i_spacewire ( + .ASYNC_RSTN (periph_rst_n), + .SYNC_RSTN (periph_rst_n), + .SYS_CLK (periph_clk), + .SPW_DATA_IN (spw_data_i), + .SPW_STROBE_IN (spw_strb_i), + .SPW_DATA_OUT (spw_data_o), + .SPW_STROBE_OUT (spw_strb_o), + .REG_ADDR_i (spw_address), + .REG_VALID_i (reg_bus_spw.valid), + .REG_WDATA_i (reg_bus_spw.wdata), + .REG_WRITE_i (reg_bus_spw.write), + .REG_RDATA_o (reg_bus_spw.rdata), + .REG_READY_o (reg_bus_spw.ready), + .APB_PADD (apb_spw_req[1].paddr), + .APB_PSEL (apb_spw_req[1].psel), + .APB_PENABLE (apb_spw_req[1].penable), + .APB_PWDATA (apb_spw_req[1].pwdata), + .APB_PWRITE (apb_spw_req[1].pwrite), + .APB_PRDATA (apb_spw_rsp[1].prdata), + .APB_PREADY (apb_spw_rsp[1].pready), + .APB_PSLVERR (apb_spw_rsp[1].pslverr), + .GENERAL_INTERRUPT_o (car_regs_hw2reg.spw_general_irq.d) + ); + assign car_regs_hw2reg.spw_general_irq.de = '1; + + end else begin: gen_no_spw + assign spw_data_o = '0; + assign spw_strb_o = '0; + assign car_regs_hw2reg.spw_general_irq.d = '0; + assign car_regs_hw2reg.spw_general_irq.de = '0; + end + end else begin: gen_no_periph assign car_regs_hw2reg.periph_isolate_status.d = '0; assign car_regs_hw2reg.periph_isolate_status.de = '0; diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index c9f792dc..9633a043 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -754,14 +754,16 @@ typedef logic [ AxiNarrowDataWidth-1:0] car_nar_dataw_t; typedef logic [ AxiNarrowStrobe-1:0] car_nar_strb_t; // APB Mapping -localparam int unsigned NumApbMst = 5; +localparam int unsigned NumApbMst = 7; typedef enum int { SystemTimerIdx = 'd0, AdvancedTimerIdx = 'd1, SystemWdtIdx = 'd2, CanIdx = 'd3, - HyperBusIdx = 'd4 + HyperBusIdx = 'd4, + StreamerIdx = 'd5, + SpaceWireIdx = 'd6 } carfield_peripherals_e; // Address map of peripheral system @@ -772,7 +774,7 @@ typedef struct packed { } carfield_addr_map_rule_t; localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ - // 0: System Timer + // 0: System Timer '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, end_addr: SystemTimerBase + SystemTimerSize }, // 1: Advanced Timer @@ -786,7 +788,13 @@ localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ end_addr: CanBase + CanSize }, // 4: Hyperbus '{ idx: HyperBusIdx, start_addr: HyperBusBase, - end_addr: HyperBusBase + HyperBusSize } + end_addr: HyperBusBase + HyperBusSize }, + // 5: Streamer + '{ idx: StreamerIdx, start_addr: StreamerCfgBase, + end_addr: StreamerApbBase + StreamerApbSize }, + // 6: SpW + '{ idx: SpaceWireIdx, start_addr: SpaceWireRegBase, + end_addr: SpaceWireApbBase + SpaceWireApbSize } }; // Narrow reg types diff --git a/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv b/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv new file mode 100644 index 00000000..146cc644 --- /dev/null +++ b/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv @@ -0,0 +1,104 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00080000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 1; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h01000000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00003000; +/********************* + * APB Configuration * + ********************/ +// Can +localparam bit CanEnable = 1; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20008000; +localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 1; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 1; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; +/************************ + * RegBus Configuration * + ***********************/ +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h21000000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h21001000; +localparam doub_bt L2EccCfgSize = 'h00001000; +// Platform control registers +localparam doub_bt PcrsBase = 'h21002000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h21003000; +localparam doub_bt PllCfgSize = 'h00001000; +/************************** + * HyperBus Configuration * + **************************/ +localparam doub_bt NumHypPhys = 1; +localparam doub_bt NumHypChips = 2; + +endpackage diff --git a/hw/regs/carfield_reg_pkg.sv b/hw/regs/carfield_reg_pkg.sv index 6f9836e8..6ac16530 100644 --- a/hw/regs/carfield_reg_pkg.sv +++ b/hw/regs/carfield_reg_pkg.sv @@ -7,7 +7,7 @@ package carfield_reg_pkg; // Address widths within the block - parameter int BlockAw = 8; + parameter int BlockAw = 9; //////////////////////////// // Typedefs for registers // @@ -227,6 +227,16 @@ package carfield_reg_pkg; logic qe; } carfield_reg2hw_hyperbus_clk_div_value_reg_t; + typedef struct packed { + logic q; + logic qe; + } carfield_reg2hw_streamer_clk_div_enable_reg_t; + + typedef struct packed { + logic [5:0] q; + logic qe; + } carfield_reg2hw_streamer_clk_div_value_reg_t; + typedef struct packed { logic [31:0] d; logic de; @@ -282,140 +292,158 @@ package carfield_reg_pkg; logic de; } carfield_hw2reg_pulp_cluster_eoc_reg_t; + typedef struct packed { + logic d; + logic de; + } carfield_hw2reg_streamer_general_irq_reg_t; + + typedef struct packed { + logic d; + logic de; + } carfield_hw2reg_spw_general_irq_reg_t; + // Register -> HW type typedef struct packed { - carfield_reg2hw_generic_scratch0_reg_t generic_scratch0; // [460:429] - carfield_reg2hw_generic_scratch1_reg_t generic_scratch1; // [428:397] - carfield_reg2hw_host_rst_reg_t host_rst; // [396:396] - carfield_reg2hw_periph_rst_reg_t periph_rst; // [395:395] - carfield_reg2hw_safety_island_rst_reg_t safety_island_rst; // [394:394] - carfield_reg2hw_security_island_rst_reg_t security_island_rst; // [393:393] - carfield_reg2hw_pulp_cluster_rst_reg_t pulp_cluster_rst; // [392:392] - carfield_reg2hw_spatz_cluster_rst_reg_t spatz_cluster_rst; // [391:391] - carfield_reg2hw_l2_rst_reg_t l2_rst; // [390:390] - carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [389:389] - carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [388:388] - carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [387:387] - carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [386:386] - carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [385:385] - carfield_reg2hw_l2_isolate_reg_t l2_isolate; // [384:384] - carfield_reg2hw_periph_clk_en_reg_t periph_clk_en; // [383:383] - carfield_reg2hw_safety_island_clk_en_reg_t safety_island_clk_en; // [382:382] - carfield_reg2hw_security_island_clk_en_reg_t security_island_clk_en; // [381:381] - carfield_reg2hw_pulp_cluster_clk_en_reg_t pulp_cluster_clk_en; // [380:380] - carfield_reg2hw_spatz_cluster_clk_en_reg_t spatz_cluster_clk_en; // [379:379] - carfield_reg2hw_l2_clk_en_reg_t l2_clk_en; // [378:378] - carfield_reg2hw_periph_clk_sel_reg_t periph_clk_sel; // [377:376] - carfield_reg2hw_safety_island_clk_sel_reg_t safety_island_clk_sel; // [375:374] - carfield_reg2hw_security_island_clk_sel_reg_t security_island_clk_sel; // [373:372] - carfield_reg2hw_pulp_cluster_clk_sel_reg_t pulp_cluster_clk_sel; // [371:370] - carfield_reg2hw_spatz_cluster_clk_sel_reg_t spatz_cluster_clk_sel; // [369:368] - carfield_reg2hw_l2_clk_sel_reg_t l2_clk_sel; // [367:366] - carfield_reg2hw_periph_clk_div_value_reg_t periph_clk_div_value; // [365:341] - carfield_reg2hw_safety_island_clk_div_value_reg_t safety_island_clk_div_value; // [340:316] - carfield_reg2hw_security_island_clk_div_value_reg_t security_island_clk_div_value; // [315:291] - carfield_reg2hw_pulp_cluster_clk_div_value_reg_t pulp_cluster_clk_div_value; // [290:266] - carfield_reg2hw_spatz_cluster_clk_div_value_reg_t spatz_cluster_clk_div_value; // [265:241] - carfield_reg2hw_l2_clk_div_value_reg_t l2_clk_div_value; // [240:216] - carfield_reg2hw_host_fetch_enable_reg_t host_fetch_enable; // [215:215] - carfield_reg2hw_safety_island_fetch_enable_reg_t safety_island_fetch_enable; // [214:214] - carfield_reg2hw_security_island_fetch_enable_reg_t security_island_fetch_enable; // [213:213] - carfield_reg2hw_pulp_cluster_fetch_enable_reg_t pulp_cluster_fetch_enable; // [212:212] - carfield_reg2hw_spatz_cluster_debug_req_reg_t spatz_cluster_debug_req; // [211:210] - carfield_reg2hw_host_boot_addr_reg_t host_boot_addr; // [209:178] - carfield_reg2hw_safety_island_boot_addr_reg_t safety_island_boot_addr; // [177:146] - carfield_reg2hw_security_island_boot_addr_reg_t security_island_boot_addr; // [145:114] - carfield_reg2hw_pulp_cluster_boot_addr_reg_t pulp_cluster_boot_addr; // [113:82] - carfield_reg2hw_spatz_cluster_boot_addr_reg_t spatz_cluster_boot_addr; // [81:50] - carfield_reg2hw_pulp_cluster_boot_enable_reg_t pulp_cluster_boot_enable; // [49:49] - carfield_reg2hw_spatz_cluster_busy_reg_t spatz_cluster_busy; // [48:48] - carfield_reg2hw_pulp_cluster_busy_reg_t pulp_cluster_busy; // [47:47] - carfield_reg2hw_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [46:46] - carfield_reg2hw_eth_clk_div_en_reg_t eth_clk_div_en; // [45:44] - carfield_reg2hw_eth_clk_div_value_reg_t eth_clk_div_value; // [43:23] - carfield_reg2hw_hyperbus_clk_div_en_reg_t hyperbus_clk_div_en; // [22:21] - carfield_reg2hw_hyperbus_clk_div_value_reg_t hyperbus_clk_div_value; // [20:0] + carfield_reg2hw_generic_scratch0_reg_t generic_scratch0; // [469:438] + carfield_reg2hw_generic_scratch1_reg_t generic_scratch1; // [437:406] + carfield_reg2hw_host_rst_reg_t host_rst; // [405:405] + carfield_reg2hw_periph_rst_reg_t periph_rst; // [404:404] + carfield_reg2hw_safety_island_rst_reg_t safety_island_rst; // [403:403] + carfield_reg2hw_security_island_rst_reg_t security_island_rst; // [402:402] + carfield_reg2hw_pulp_cluster_rst_reg_t pulp_cluster_rst; // [401:401] + carfield_reg2hw_spatz_cluster_rst_reg_t spatz_cluster_rst; // [400:400] + carfield_reg2hw_l2_rst_reg_t l2_rst; // [399:399] + carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [398:398] + carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [397:397] + carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [396:396] + carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [395:395] + carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [394:394] + carfield_reg2hw_l2_isolate_reg_t l2_isolate; // [393:393] + carfield_reg2hw_periph_clk_en_reg_t periph_clk_en; // [392:392] + carfield_reg2hw_safety_island_clk_en_reg_t safety_island_clk_en; // [391:391] + carfield_reg2hw_security_island_clk_en_reg_t security_island_clk_en; // [390:390] + carfield_reg2hw_pulp_cluster_clk_en_reg_t pulp_cluster_clk_en; // [389:389] + carfield_reg2hw_spatz_cluster_clk_en_reg_t spatz_cluster_clk_en; // [388:388] + carfield_reg2hw_l2_clk_en_reg_t l2_clk_en; // [387:387] + carfield_reg2hw_periph_clk_sel_reg_t periph_clk_sel; // [386:385] + carfield_reg2hw_safety_island_clk_sel_reg_t safety_island_clk_sel; // [384:383] + carfield_reg2hw_security_island_clk_sel_reg_t security_island_clk_sel; // [382:381] + carfield_reg2hw_pulp_cluster_clk_sel_reg_t pulp_cluster_clk_sel; // [380:379] + carfield_reg2hw_spatz_cluster_clk_sel_reg_t spatz_cluster_clk_sel; // [378:377] + carfield_reg2hw_l2_clk_sel_reg_t l2_clk_sel; // [376:375] + carfield_reg2hw_periph_clk_div_value_reg_t periph_clk_div_value; // [374:350] + carfield_reg2hw_safety_island_clk_div_value_reg_t safety_island_clk_div_value; // [349:325] + carfield_reg2hw_security_island_clk_div_value_reg_t security_island_clk_div_value; // [324:300] + carfield_reg2hw_pulp_cluster_clk_div_value_reg_t pulp_cluster_clk_div_value; // [299:275] + carfield_reg2hw_spatz_cluster_clk_div_value_reg_t spatz_cluster_clk_div_value; // [274:250] + carfield_reg2hw_l2_clk_div_value_reg_t l2_clk_div_value; // [249:225] + carfield_reg2hw_host_fetch_enable_reg_t host_fetch_enable; // [224:224] + carfield_reg2hw_safety_island_fetch_enable_reg_t safety_island_fetch_enable; // [223:223] + carfield_reg2hw_security_island_fetch_enable_reg_t security_island_fetch_enable; // [222:222] + carfield_reg2hw_pulp_cluster_fetch_enable_reg_t pulp_cluster_fetch_enable; // [221:221] + carfield_reg2hw_spatz_cluster_debug_req_reg_t spatz_cluster_debug_req; // [220:219] + carfield_reg2hw_host_boot_addr_reg_t host_boot_addr; // [218:187] + carfield_reg2hw_safety_island_boot_addr_reg_t safety_island_boot_addr; // [186:155] + carfield_reg2hw_security_island_boot_addr_reg_t security_island_boot_addr; // [154:123] + carfield_reg2hw_pulp_cluster_boot_addr_reg_t pulp_cluster_boot_addr; // [122:91] + carfield_reg2hw_spatz_cluster_boot_addr_reg_t spatz_cluster_boot_addr; // [90:59] + carfield_reg2hw_pulp_cluster_boot_enable_reg_t pulp_cluster_boot_enable; // [58:58] + carfield_reg2hw_spatz_cluster_busy_reg_t spatz_cluster_busy; // [57:57] + carfield_reg2hw_pulp_cluster_busy_reg_t pulp_cluster_busy; // [56:56] + carfield_reg2hw_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [55:55] + carfield_reg2hw_eth_clk_div_en_reg_t eth_clk_div_en; // [54:53] + carfield_reg2hw_eth_clk_div_value_reg_t eth_clk_div_value; // [52:32] + carfield_reg2hw_hyperbus_clk_div_en_reg_t hyperbus_clk_div_en; // [31:30] + carfield_reg2hw_hyperbus_clk_div_value_reg_t hyperbus_clk_div_value; // [29:9] + carfield_reg2hw_streamer_clk_div_enable_reg_t streamer_clk_div_enable; // [8:7] + carfield_reg2hw_streamer_clk_div_value_reg_t streamer_clk_div_value; // [6:0] } carfield_reg2hw_t; // HW -> register type typedef struct packed { - carfield_hw2reg_generic_scratch0_reg_t generic_scratch0; // [83:51] - carfield_hw2reg_generic_scratch1_reg_t generic_scratch1; // [50:18] - carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [17:16] - carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [15:14] - carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [13:12] - carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [11:10] - carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [9:8] - carfield_hw2reg_l2_isolate_status_reg_t l2_isolate_status; // [7:6] - carfield_hw2reg_spatz_cluster_busy_reg_t spatz_cluster_busy; // [5:4] - carfield_hw2reg_pulp_cluster_busy_reg_t pulp_cluster_busy; // [3:2] - carfield_hw2reg_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [1:0] + carfield_hw2reg_generic_scratch0_reg_t generic_scratch0; // [87:55] + carfield_hw2reg_generic_scratch1_reg_t generic_scratch1; // [54:22] + carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [21:20] + carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [19:18] + carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [17:16] + carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [15:14] + carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [13:12] + carfield_hw2reg_l2_isolate_status_reg_t l2_isolate_status; // [11:10] + carfield_hw2reg_spatz_cluster_busy_reg_t spatz_cluster_busy; // [9:8] + carfield_hw2reg_pulp_cluster_busy_reg_t pulp_cluster_busy; // [7:6] + carfield_hw2reg_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [5:4] + carfield_hw2reg_streamer_general_irq_reg_t streamer_general_irq; // [3:2] + carfield_hw2reg_spw_general_irq_reg_t spw_general_irq; // [1:0] } carfield_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CARFIELD_VERSION0_OFFSET = 8'h 0; - parameter logic [BlockAw-1:0] CARFIELD_VERSION1_OFFSET = 8'h 4; - parameter logic [BlockAw-1:0] CARFIELD_VERSION2_OFFSET = 8'h 8; - parameter logic [BlockAw-1:0] CARFIELD_VERSION3_OFFSET = 8'h c; - parameter logic [BlockAw-1:0] CARFIELD_VERSION4_OFFSET = 8'h 10; - parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 8'h 14; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 8'h 18; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 8'h 1c; - parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 8'h 20; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 8'h 24; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 8'h 28; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 8'h 2c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 8'h 30; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 8'h 34; - parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 8'h 38; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 8'h 3c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 8'h 40; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 8'h 44; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 8'h 48; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 8'h 4c; - parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_OFFSET = 8'h 50; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 8'h 54; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 58; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 5c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 60; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 64; - parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_STATUS_OFFSET = 8'h 68; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 8'h 6c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 8'h 70; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 8'h 74; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 8'h 78; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 8'h 7c; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 8'h 80; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 8'h 84; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 8'h 88; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 8'h 8c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 8'h 90; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 8'h 94; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 8'h 98; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 8'h 9c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a0; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h a8; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h ac; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 8'h b0; - parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 8'h b4; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 8'h b8; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 8'h bc; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c0; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_DEBUG_REQ_OFFSET = 8'h c4; - parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 8'h c8; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 8'h cc; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 8'h d0; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 8'h d4; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 8'h d8; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 8'h dc; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 8'h e0; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 8'h e4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 8'h e8; - parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_EN_OFFSET = 8'h ec; - parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_VALUE_OFFSET = 8'h f0; - parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET = 8'h f4; - parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET = 8'h f8; + parameter logic [BlockAw-1:0] CARFIELD_VERSION0_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] CARFIELD_VERSION1_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] CARFIELD_VERSION2_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] CARFIELD_VERSION3_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] CARFIELD_VERSION4_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_STATUS_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_DEBUG_REQ_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_EN_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_VALUE_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_CLK_DIV_ENABLE_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_CLK_DIV_VALUE_OFFSET = 9'h 100; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_GENERAL_IRQ_OFFSET = 9'h 104; + parameter logic [BlockAw-1:0] CARFIELD_SPW_GENERAL_IRQ_OFFSET = 9'h 108; // Register index typedef enum int { @@ -481,11 +509,15 @@ package carfield_reg_pkg; CARFIELD_ETH_CLK_DIV_EN, CARFIELD_ETH_CLK_DIV_VALUE, CARFIELD_HYPERBUS_CLK_DIV_EN, - CARFIELD_HYPERBUS_CLK_DIV_VALUE + CARFIELD_HYPERBUS_CLK_DIV_VALUE, + CARFIELD_STREAMER_CLK_DIV_ENABLE, + CARFIELD_STREAMER_CLK_DIV_VALUE, + CARFIELD_STREAMER_GENERAL_IRQ, + CARFIELD_SPW_GENERAL_IRQ } carfield_id_e; // Register width information to check illegal writes - parameter logic [3:0] CARFIELD_PERMIT [63] = '{ + parameter logic [3:0] CARFIELD_PERMIT [67] = '{ 4'b 1111, // index[ 0] CARFIELD_VERSION0 4'b 1111, // index[ 1] CARFIELD_VERSION1 4'b 1111, // index[ 2] CARFIELD_VERSION2 @@ -548,7 +580,11 @@ package carfield_reg_pkg; 4'b 0001, // index[59] CARFIELD_ETH_CLK_DIV_EN 4'b 0111, // index[60] CARFIELD_ETH_CLK_DIV_VALUE 4'b 0001, // index[61] CARFIELD_HYPERBUS_CLK_DIV_EN - 4'b 0111 // index[62] CARFIELD_HYPERBUS_CLK_DIV_VALUE + 4'b 0111, // index[62] CARFIELD_HYPERBUS_CLK_DIV_VALUE + 4'b 0001, // index[63] CARFIELD_STREAMER_CLK_DIV_ENABLE + 4'b 0001, // index[64] CARFIELD_STREAMER_CLK_DIV_VALUE + 4'b 0001, // index[65] CARFIELD_STREAMER_GENERAL_IRQ + 4'b 0001 // index[66] CARFIELD_SPW_GENERAL_IRQ }; endpackage diff --git a/hw/regs/carfield_reg_top.sv b/hw/regs/carfield_reg_top.sv index 801f53ed..54bdf898 100644 --- a/hw/regs/carfield_reg_top.sv +++ b/hw/regs/carfield_reg_top.sv @@ -10,7 +10,7 @@ module carfield_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 8 + parameter int AW = 9 ) ( input logic clk_i, input logic rst_ni, @@ -237,6 +237,18 @@ module carfield_reg_top #( logic [19:0] hyperbus_clk_div_value_qs; logic [19:0] hyperbus_clk_div_value_wd; logic hyperbus_clk_div_value_we; + logic streamer_clk_div_enable_qs; + logic streamer_clk_div_enable_wd; + logic streamer_clk_div_enable_we; + logic [5:0] streamer_clk_div_value_qs; + logic [5:0] streamer_clk_div_value_wd; + logic streamer_clk_div_value_we; + logic streamer_general_irq_qs; + logic streamer_general_irq_wd; + logic streamer_general_irq_we; + logic spw_general_irq_qs; + logic spw_general_irq_wd; + logic spw_general_irq_we; // Register instances // R[version0]: V(False) @@ -1830,9 +1842,117 @@ module carfield_reg_top #( ); + // R[streamer_clk_div_enable]: V(False) + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_streamer_clk_div_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (streamer_clk_div_enable_we), + .wd (streamer_clk_div_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.streamer_clk_div_enable.qe), + .q (reg2hw.streamer_clk_div_enable.q ), + + // to register interface (read) + .qs (streamer_clk_div_enable_qs) + ); + + + // R[streamer_clk_div_value]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h1) + ) u_streamer_clk_div_value ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (streamer_clk_div_value_we), + .wd (streamer_clk_div_value_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.streamer_clk_div_value.qe), + .q (reg2hw.streamer_clk_div_value.q ), + + // to register interface (read) + .qs (streamer_clk_div_value_qs) + ); + + + // R[streamer_general_irq]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_streamer_general_irq ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (streamer_general_irq_we), + .wd (streamer_general_irq_wd), + + // from internal hardware + .de (hw2reg.streamer_general_irq.de), + .d (hw2reg.streamer_general_irq.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (streamer_general_irq_qs) + ); + + + // R[spw_general_irq]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_spw_general_irq ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (spw_general_irq_we), + .wd (spw_general_irq_wd), + + // from internal hardware + .de (hw2reg.spw_general_irq.de), + .d (hw2reg.spw_general_irq.d ), - logic [62:0] addr_hit; + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (spw_general_irq_qs) + ); + + + + + logic [66:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CARFIELD_VERSION0_OFFSET); @@ -1898,6 +2018,10 @@ module carfield_reg_top #( addr_hit[60] = (reg_addr == CARFIELD_ETH_CLK_DIV_VALUE_OFFSET); addr_hit[61] = (reg_addr == CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET); addr_hit[62] = (reg_addr == CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET); + addr_hit[63] = (reg_addr == CARFIELD_STREAMER_CLK_DIV_ENABLE_OFFSET); + addr_hit[64] = (reg_addr == CARFIELD_STREAMER_CLK_DIV_VALUE_OFFSET); + addr_hit[65] = (reg_addr == CARFIELD_STREAMER_GENERAL_IRQ_OFFSET); + addr_hit[66] = (reg_addr == CARFIELD_SPW_GENERAL_IRQ_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1967,7 +2091,11 @@ module carfield_reg_top #( (addr_hit[59] & (|(CARFIELD_PERMIT[59] & ~reg_be))) | (addr_hit[60] & (|(CARFIELD_PERMIT[60] & ~reg_be))) | (addr_hit[61] & (|(CARFIELD_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))))); + (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(CARFIELD_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(CARFIELD_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(CARFIELD_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(CARFIELD_PERMIT[66] & ~reg_be))))); end assign jedec_idcode_we = addr_hit[5] & reg_we & !reg_error; @@ -2129,6 +2257,18 @@ module carfield_reg_top #( assign hyperbus_clk_div_value_we = addr_hit[62] & reg_we & !reg_error; assign hyperbus_clk_div_value_wd = reg_wdata[19:0]; + assign streamer_clk_div_enable_we = addr_hit[63] & reg_we & !reg_error; + assign streamer_clk_div_enable_wd = reg_wdata[0]; + + assign streamer_clk_div_value_we = addr_hit[64] & reg_we & !reg_error; + assign streamer_clk_div_value_wd = reg_wdata[5:0]; + + assign streamer_general_irq_we = addr_hit[65] & reg_we & !reg_error; + assign streamer_general_irq_wd = reg_wdata[0]; + + assign spw_general_irq_we = addr_hit[66] & reg_we & !reg_error; + assign spw_general_irq_wd = reg_wdata[0]; + // Read data return always_comb begin reg_rdata_next = '0; @@ -2385,6 +2525,22 @@ module carfield_reg_top #( reg_rdata_next[19:0] = hyperbus_clk_div_value_qs; end + addr_hit[63]: begin + reg_rdata_next[0] = streamer_clk_div_enable_qs; + end + + addr_hit[64]: begin + reg_rdata_next[5:0] = streamer_clk_div_value_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = streamer_general_irq_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = spw_general_irq_qs; + end + default: begin reg_rdata_next = '1; end @@ -2407,7 +2563,7 @@ endmodule module carfield_reg_top_intf #( - parameter int AW = 8, + parameter int AW = 9, localparam int DW = 32 ) ( input logic clk_i, diff --git a/hw/regs/carfield_regs.csv b/hw/regs/carfield_regs.csv index b7bb2e5e..6b279e52 100644 --- a/hw/regs/carfield_regs.csv +++ b/hw/regs/carfield_regs.csv @@ -62,3 +62,7 @@ ETH_CLK_DIV_EN,1,rw,hro,1,1,Ethernet clock divider enable bit ETH_CLK_DIV_VALUE,20,rw,hro,1,10,Ethernet clock divider value HYPERBUS_CLK_DIV_EN,1,rw,hro,1,1,Hyperbus clock divider enable bit HYPERBUS_CLK_DIV_VALUE,20,rw,hro,1,1,Hyperbus clock divider value +STREAMER_CLK_DIV_ENABLE,1,rw,hro,1,0,Streamer clock divider enable +STREAMER_CLK_DIV_VALUE,6,rw,hro,1,1,Streamer clock divider value +STREAMER_GENERAL_IRQ,1,rw,hwo,1,0,Streamer general interrupt +SPW_GENERAL_IRQ,1,rw,hwo,1,0,SpaceWire general interrupt \ No newline at end of file diff --git a/hw/regs/carfield_regs.hjson b/hw/regs/carfield_regs.hjson index a5f131ea..81ee3703 100644 --- a/hw/regs/carfield_regs.hjson +++ b/hw/regs/carfield_regs.hjson @@ -704,5 +704,49 @@ { bits: "19:0" } ], } + + { name: "STREAMER_CLK_DIV_ENABLE", + desc: "Streamer clock divider enable", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } + + { name: "STREAMER_CLK_DIV_VALUE", + desc: "Streamer clock divider value", + swaccess: "rw", + hwaccess: "hro", + resval: "1", + hwqe: "1", + fields: [ + { bits: "5:0" } + ], + } + + { name: "STREAMER_GENERAL_IRQ", + desc: "Streamer general interrupt", + swaccess: "rw", + hwaccess: "hwo", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } + + { name: "SPW_GENERAL_IRQ", + desc: "SpaceWire general interrupt", + swaccess: "rw", + hwaccess: "hwo", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } ], } diff --git a/hw/regs/pcr.md b/hw/regs/pcr.md index babed51e..387caeb7 100644 --- a/hw/regs/pcr.md +++ b/hw/regs/pcr.md @@ -65,6 +65,10 @@ | carfield.[`ETH_CLK_DIV_VALUE`](#eth_clk_div_value) | 0xf0 | 4 | Ethernet clock divider value | | carfield.[`HYPERBUS_CLK_DIV_EN`](#hyperbus_clk_div_en) | 0xf4 | 4 | Hyperbus clock divider enable bit | | carfield.[`HYPERBUS_CLK_DIV_VALUE`](#hyperbus_clk_div_value) | 0xf8 | 4 | Hyperbus clock divider value | +| carfield.[`STREAMER_CLK_DIV_ENABLE`](#streamer_clk_div_enable) | 0xfc | 4 | Streamer clock divider enable | +| carfield.[`STREAMER_CLK_DIV_VALUE`](#streamer_clk_div_value) | 0x100 | 4 | Streamer clock divider value | +| carfield.[`STREAMER_GENERAL_IRQ`](#streamer_general_irq) | 0x104 | 4 | Streamer general interrupt | +| carfield.[`SPW_GENERAL_IRQ`](#spw_general_irq) | 0x108 | 4 | SpaceWire general interrupt | ## VERSION0 Cheshire sha256 commit @@ -1124,3 +1128,71 @@ Hyperbus clock divider value | 31:20 | | | | Reserved | | 19:0 | rw | 0x1 | HYPERBUS_CLK_DIV_VALUE | | +## STREAMER_CLK_DIV_ENABLE +Streamer clock divider enable +- Offset: `0xfc` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_CLK_DIV_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | STREAMER_CLK_DIV_ENABLE | | + +## STREAMER_CLK_DIV_VALUE +Streamer clock divider value +- Offset: `0x100` +- Reset default: `0x1` +- Reset mask: `0x3f` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_CLK_DIV_VALUE", "bits": 6, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------|:--------------| +| 31:6 | | | | Reserved | +| 5:0 | rw | 0x1 | STREAMER_CLK_DIV_VALUE | | + +## STREAMER_GENERAL_IRQ +Streamer general interrupt +- Offset: `0x104` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_GENERAL_IRQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | STREAMER_GENERAL_IRQ | | + +## SPW_GENERAL_IRQ +SpaceWire general interrupt +- Offset: `0x108` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "SPW_GENERAL_IRQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | SPW_GENERAL_IRQ | | + diff --git a/sw/include/car_memory_map.h b/sw/include/car_memory_map.h index 9729716b..add225e6 100644 --- a/sw/include/car_memory_map.h +++ b/sw/include/car_memory_map.h @@ -121,6 +121,8 @@ extern void *__base_l2; #define CAR_ADVANCED_TIMER_OFFSET 0x0005000 #define CAR_WATCHDOG_TIMER_OFFSET 0x0007000 #define CAR_HYPERBUS_CFG_OFFSET 0x0008000 +#define CAR_STREAMER_CFG_OFFSET 0x0009000 +#define CAR_STREAMER_APB_OFFSET 0x0011000 #define CAR_PAD_CFG_OFFSET 0x1000000 #define CAR_ETHERNET_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ETHERNET_OFFSET) @@ -129,6 +131,8 @@ extern void *__base_l2; #define CAR_ADVANCED_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ADVANCED_TIMER_OFFSET) #define CAR_WATCHDOG_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_WATCHDOG_TIMER_OFFSET) #define CAR_HYPERBUS_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_HYPERBUS_CFG_OFFSET) +#define CAR_STREAMER_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_STREAMER_CFG_OFFSET) +#define CAR_STREAMER_APB_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_STREAMER_APB_OFFSET) #define CAR_PAD_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_PAD_CFG_OFFSET) #define CAR_SOC_CTRL_BASE_ADDR(BASE) BASE @@ -158,6 +162,32 @@ extern void *__base_l2; #define MBOX_CAR_LETTER0(id) (CAR_MBOX_BASE_ADDR + MBOX_LETTER0_OFFSET + (id*0x100)) #define MBOX_CAR_LETTER1(id) (CAR_MBOX_BASE_ADDR + MBOX_LETTER1_OFFSET + (id*0x100)) +//TCTM Streamer +#define TCTM_STREAMER_CFG_OFFS 0x0 +#define TCTM_STREAMER_MAP_ROUTER_OFFS 0x0 +#define TCTM_STREAMER_HPC_OFFS 0x80 +#define TCTM_STREAMER_OBT_OFFS 0x100 +#define TCTM_STREAMER_PTME_OFFS 0x180 +#define TCTM_STREAMER_PTD_OFFS 0x200 +#define TCTM_STREAMER_LLC_OFFS 0x280 + +#define TCTM_STREAMER_PTME_CFG_OFFS 0x000 +#define TCTM_STREAMER_TM_PACKETS_OFFS 0x400 +#define TCTM_STREAMER_TC_BUFFER_OFFS 0x800 +#define TCTM_STREAMER_TX_BUFFER_OFFS 0xC00 + +#define TCTM_STREAMER_CFG_MAP_ROUTER_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_MAP_ROUTER_OFFS +#define TCTM_STREAMER_CFG_HPC_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_HPC_OFFS +#define TCTM_STREAMER_CFG_OBT_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_OBT_OFFS +#define TCTM_STREAMER_CFG_PTME_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_PTME_OFFS +#define TCTM_STREAMER_CFG_PTD_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_PTD_OFFS +#define TCTM_STREAMER_CFG_LLC_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_LLC_OFFS + +#define TCTM_STREAMER_APB_PTME_CFG CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_PTME_CFG_OFFS +#define TCTM_STREAMER_APB_TM_PACKET_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TM_PACKETS_OFFS +#define TCTM_STREAMER_APB_TC_BUFFER_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TC_BUFFER_OFFS +#define TCTM_STREAMER_APB_TX_BUFFER_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TX_BUFFER_OFFS + // PLL #define CAR_PLL_BASE_ADDRESS 0x21003000 #define PLL_ADDR_SPACE 0x200 diff --git a/sw/include/regs/soc_ctrl.h b/sw/include/regs/soc_ctrl.h index 5f127b21..4de1e831 100644 --- a/sw/include/regs/soc_ctrl.h +++ b/sw/include/regs/soc_ctrl.h @@ -308,6 +308,25 @@ extern "C" { #define CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_MASK, .index = CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_OFFSET }) +// Streamer clock divider enable +#define CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET 0xfc +#define CARFIELD_STREAMER_CLK_DIV_ENABLE_STREAMER_CLK_DIV_ENABLE_BIT 0 + +// Streamer clock divider value +#define CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET 0x100 +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_MASK 0x3f +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_OFFSET 0 +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_FIELD \ + ((bitfield_field32_t) { .mask = CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_MASK, .index = CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_OFFSET }) + +// Streamer general interrupt +#define CARFIELD_STREAMER_GENERAL_IRQ_REG_OFFSET 0x104 +#define CARFIELD_STREAMER_GENERAL_IRQ_STREAMER_GENERAL_IRQ_BIT 0 + +// SpaceWire general interrupt +#define CARFIELD_SPW_GENERAL_IRQ_REG_OFFSET 0x108 +#define CARFIELD_SPW_GENERAL_IRQ_SPW_GENERAL_IRQ_BIT 0 + #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/include/tasi.h b/sw/include/tasi.h new file mode 100644 index 00000000..8f0ba3fa --- /dev/null +++ b/sw/include/tasi.h @@ -0,0 +1,325 @@ + +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Robert Balas +// + +/* Description: Memory mapped register I/O access + */ + +#ifndef __TASI_H +#define __TASI_H + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "params.h" +#include "util.h" +#include "car_util.h" +#include "printf.h" +#include "regs/system_timer.h" +#include "csr.h" + + +#define MHZ 100 + +#define BIT0 0 +#define BIT1 1 +#define BIT2 2 +#define BIT3 3 +#define BIT4 4 +#define BIT5 5 +#define BIT6 6 +#define BIT7 7 +#define BIT8 8 +#define BIT9 9 +#define BIT10 10 +#define BIT11 11 +#define BIT12 12 +#define BIT13 13 +#define BIT14 14 +#define BIT15 15 +#define BIT16 16 +#define BIT17 17 +#define BIT18 18 +#define BIT19 19 +#define BIT20 20 +#define BIT21 21 +#define BIT22 22 +#define BIT23 23 +#define BIT24 24 +#define BIT25 25 +#define BIT26 26 +#define BIT27 27 +#define BIT28 28 +#define BIT29 29 +#define BIT30 30 +#define BIT31 31 + +#define STREAMER_REG_BUS 0x20009000 +#define STREAMER_APB 0x20011000 +#define SPW_REG_BUS 0x20019000 +#define SPW_APB 0x20019100 + +//Streamer + +#define STREAMER_PTME_CONFIG (STREAMER_APB | 0x000) +#define STREAMER_PTME_DATA (STREAMER_APB | 0x400) +#define STREAMER_PTD_DATA (STREAMER_APB | 0x800) +#define STREAMER_HPC_LLC_DATA (STREAMER_APB | 0xC00) + + +#define STREAMER_OBT_ATSS (STREAMER_REG_BUS | 0x120) +#define STREAMER_OBT_ATSSS (STREAMER_REG_BUS | 0x124) + +#define STREAMER_TC_BUFFER_STATUS (STREAMER_REG_BUS | 0x280) +#define STREAMER_TC_BUFFER_RELEASE (STREAMER_REG_BUS | 0x284) +#define STREAMER_HPC_LLC_BUFFER_BUSY_SET (STREAMER_REG_BUS | 0x288) +#define STREAMER_HPC_LLC_BUFFER_STATUS (STREAMER_REG_BUS | 0x28C) +#define STREAMER_HPTM_PACKET_HEADER (STREAMER_REG_BUS | 0x290) + +#define STREAMER_INTERRUPT_MASK (STREAMER_REG_BUS | 0x294) +#define STREAMER_INTERRUPT_CLEAR (STREAMER_REG_BUS | 0x298) +#define STREAMER_INTERRUPT_FORCE (STREAMER_REG_BUS | 0x29C) +#define STREAMER_INTERRUPT_PENDING (STREAMER_REG_BUS | 0x2A0) + +//#define STREAMER_INTERUPT_TC 0x1 +//#define STREAMER_INTERUPT_PPS 0x2 +//#define STREAMER_INTERUPT_TS 0x4 +//#define STREAMER_INTERUPT_RTC 0x8 + +#define STREAMER_PTME_CONFIG_READY BIT6 + +#define STREAMER_INTERRUPT_TC BIT0 +#define STREAMER_INTERRUPT_PPS BIT1 +#define STREAMER_INTERRUPT_TS BIT2 +#define STREAMER_INTERRUPT_RTC BIT3 + + + +#define STREAMER_INTERRUPT_TC_ABS_VALUE (1< return 1; + // If hart_id() == 1 -> return 0; + // Hart 0 enters first + if (hart_id() != 0) wfi(); + // Update clock divider value and re-enable streamer clock divider + writew(1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET); + writew(0x1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET); +} + + + +void wait_us(unsigned int us); + +void wait_us(unsigned int us) +{ + unsigned long start_time = 0; + unsigned long end_time = 0; + + get_time_us (&start_time); + + do{ + get_time_us (&end_time); + } + while(end_time> j) & 1) * pow(2,24-j)); //due to lack of pow in math.h + time_s += (((atsss_internal >> j) & 1) * pow); + pow*=2; + } + + //printf("time_s = %f \n",time_s); + + //set us to s + time_us_internal = time_s*1000000; + //add seconds part + time_us_internal += atss_internal*1000000; + //printf("time_us %lu \n",time_us); + //assign return value to parameters + *time_us = time_us_internal; + *atss = atss_internal; + *atsss = atsss_internal; + +} + +void start_time (unsigned long * time_us) +{ + get_time_us(time_us); +} + +void end_time (unsigned long time_us,unsigned long * duration) +{ + unsigned long tmp; + + get_time_us(&tmp); + + *duration = tmp - time_us; +} + +void start_time_streamer (unsigned long * time_us) +{ + unsigned int atss,atsss; + + get_time_streamer_us(&atss,&atsss,time_us); +} + +void end_time_streamer (unsigned long time_us,unsigned long * duration) +{ + unsigned long tmp; + unsigned int atss,atsss; + + get_time_streamer_us(&atss,&atsss,&tmp); + + //calculate duration + *duration = tmp - time_us; +} + + +#endif + + + diff --git a/sw/tests/bare-metal/hostd/streamer.c b/sw/tests/bare-metal/hostd/streamer.c new file mode 100644 index 00000000..a625139a --- /dev/null +++ b/sw/tests/bare-metal/hostd/streamer.c @@ -0,0 +1,108 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Yvan Tortorella +// +// Streamer access test. + +#include "car_util.h" +#include "car_params.h" +#include "regs/soc_ctrl.h" +#include "printf.h" + +#define PTME_ENABLE_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x04) +#define PTME_VIRT_CHANNELA_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x10) +#define PTME_VIRT_CHANNELB_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x14) +#define TM_FRAME_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x48) +#define PTME_ENCODING_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x60) +#define PTME_CLK_PRESCALER_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x68) +#define BIT_CLK_DIVISOR_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x6C) +#define TME_INIT_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x00) +#define STREAMER_PENDING_IRQ_ADDR (TCTM_STREAMER_CFG_MAP_ROUTER_BASE + 0x20) + +#define PTME_ENABLE_VALUE 0x00010000 +#define TM_FRAME_CFG_VALUE 0x3FFE0020 +#define PTME_CLK_PRESCALE_VALUE 0x00000000 +#define BIT_CLK_DIVISOR_VALUE 0x00000000 +#define TME_INIT_VALUE 0x0000AAAA +#define PTME_ACTIVATE_VALUE 0x00000008 +#define PTME_DEACTIVATE_VALUE 0x00000000 +#define PTME_ENCODING_CFG_VALUE 0x2 + +#define PTME_ENABLE_RETURN_VALUE 0x00010001 +#define PTME_VIRT_CHANNELA_CFG_VALUE 0x21 +#define PTME_VIRT_CHANNELB_CFG_VALUE 0x31 + +int main(void) { + + if (hart_id() != 0) wfi(); + + // Update clock divider value and re-enable streamer clock divider + writew(10, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET); + writew(0x1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET); + + uint32_t error = 0; + + const char packet[] = { 0x09, 0x4C, 0xD2, 0x35, + 0x00, 0x1F, 0xAF, 0x01, + 0x00, 0x00, 0xAF, 0x02, + 0x00, 0x01, 0xAF, 0x03, + 0x00, 0x02, 0xAF, 0x04, + 0x00, 0x03, 0xAF, 0x05, + 0x00, 0x04, 0xAF, 0x06, + 0x00, 0x05, 0xAF, 0x07, + 0x00, 0x06, 0xAF, 0x08, + 0x00, 0x07 }; + + while ( readw(STREAMER_PENDING_IRQ_ADDR) == 0 ); + + // Start reading TC buffer + for (int i = 0; i < 4; i++) + readb(TCTM_STREAMER_APB_TC_BUFFER_BASE + i); + + // Write HPC LLC + for (int i = 0; i < 4; i++) + writeb(i, TCTM_STREAMER_APB_TX_BUFFER_BASE + i); + + // Configure telemetry frame + writew(TM_FRAME_CFG_VALUE, TM_FRAME_ADDR); + + writew(PTME_ENCODING_CFG_VALUE, PTME_ENCODING_CFG_ADDR); + + writew(PTME_VIRT_CHANNELA_CFG_VALUE, PTME_VIRT_CHANNELA_CFG_ADDR); + + writew(PTME_VIRT_CHANNELB_CFG_VALUE, PTME_VIRT_CHANNELB_CFG_ADDR); + + // Set PTME clock pre-scaler + writew(PTME_CLK_PRESCALE_VALUE, PTME_CLK_PRESCALER_ADDR); + // Set bit clock divisor + writew(BIT_CLK_DIVISOR_VALUE, BIT_CLK_DIVISOR_ADDR); + // TME_INIT (?) + writew(TME_INIT_VALUE, TME_INIT_ADDR); + // Enable PTME + writew(PTME_ENABLE_VALUE, PTME_ENABLE_ADDR); + + // Check the written registers for errors + error += (readw(PTME_ENABLE_ADDR) != PTME_ENABLE_RETURN_VALUE); + error += (readw(TM_FRAME_ADDR) != TM_FRAME_CFG_VALUE); + error += (readw(PTME_CLK_PRESCALER_ADDR) != PTME_CLK_PRESCALE_VALUE); + error += (readw(BIT_CLK_DIVISOR_ADDR) != BIT_CLK_DIVISOR_VALUE); + error += (readw(TME_INIT_ADDR) != TME_INIT_VALUE); + + // Manifest interest in sending data (specifying only LSB is meaningful) + writew(PTME_ACTIVATE_VALUE, TCTM_STREAMER_APB_PTME_CFG + 0x00); + + // Push data into the TM buffer + for (int i = 0; i < sizeof(packet); i++) + writew(packet[i], TCTM_STREAMER_APB_TM_PACKET_BASE + 0x04*i); + + // Disable ACTIVE signal to start the transmission + writew(PTME_DEACTIVATE_VALUE, TCTM_STREAMER_APB_PTME_CFG); + + // TODO: Should we wait for an event or something here? + if (error == 0) printf("Success!\n"); + else printf("Failed!\n"); + + return error; +} diff --git a/sw/tests/bare-metal/hostd/tasi_apb_test.c b/sw/tests/bare-metal/hostd/tasi_apb_test.c new file mode 100644 index 00000000..557bc78f --- /dev/null +++ b/sw/tests/bare-metal/hostd/tasi_apb_test.c @@ -0,0 +1,56 @@ + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "params.h" +#include "util.h" +#include "car_util.h" +#include "printf.h" +#include "tasi.h" + + +int main(void) { + + + + unsigned int i; + unsigned int len; + unsigned int offset; + unsigned char tmp; + //printf("TEST - Apb module \n\n"); + + //STREAMER_PTME_DATA + len=1024; + offset = STREAMER_PTME_DATA ; + for(i=0;i enable TME + //W_REG(STREAMER_TME_ENACONF) = 0xFFFFF001; //0x00010000; --> CBA=b1111 + + + + //check interface Ready + //wait bit Idle is set + WAIT_BIT_SET(R_REG(STREAMER_PTME_CONFIG),STREAMER_PTME_CONFIG_READY); + + + //enable packet + //W_REG(STREAMER_PTME_CONFIG) = 8 ;//0xB; //bit 3 Valid to 1 and Size to 32bit + SET_BIT(W_REG(STREAMER_PTME_CONFIG),BIT3); + + //write packet with 8bit access + for(i=0;i end of packet + + //wait bit Idle is set + WAIT_BIT_SET(R_REG(STREAMER_PTME_CONFIG),STREAMER_PTME_CONFIG_READY); + + //enable new packet with 32bit mode + W_REG(STREAMER_PTME_CONFIG) = 0xB; //bit 3 Valid to 1 and Size to 32bit + + //write packet with 32bit access + for(i=0;i end of packet + + //printf("\n end TEST TM module \n\n"); + if (error == 0) + printf("Success!\n"); + else + printf("Failed!\n"); + + while(1); + return error; +} + diff --git a/target/sim/sim.mk b/target/sim/sim.mk index eaf56985..019b590d 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -35,6 +35,9 @@ RUNTIME_DEFINES := +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)" RUNTIME_DEFINES += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\" RUNTIME_DEFINES += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\" +TASI_LIB += vlib $ROOT/working_dir/streamer/TASI_generic_Lib +TASI_LIB += vmap TASI_generic_Lib $ROOT/working_dir/streamer/TASI_generic_Lib + ############# # Questasim # ############# @@ -59,6 +62,12 @@ endif .PHONY: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl $(CAR_VSIM_DIR)/compile.carfield_soc.tcl: $(BENDER) script vsim $(common_targs) $(sim_targs) $(sim_defs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@ + sed -i '2a\ + set VsimDir "$(CAR_VSIM_DIR)"\ + set TCTMPATH "$(STREAMER_ROOT)"\ + set SPWPATH "$(SPACEWIRE_ROOT)"\ + source $(STREAMER_ROOT)/astral.compile.tcl \ + source $(SPACEWIRE_ROOT)/astr_compile.tcl' $@ echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@ @@ -78,7 +87,7 @@ car-vsim-sim-build: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl .PHONY: car-vsim-sim-clean ## Remove all Questasim simulation build artifacts car-vsim-sim-clean: - rm -rf $(CAR_VSIM_DIR)/uart $(CAR_VSIM_DIR)/FETCH* $(CAR_VSIM_DIR)/logs $(CAR_VSIM_DIR)/*.ini $(CAR_VSIM_DIR)/trace* $(CAR_VSIM_DIR)/*.wlf $(CAR_VSIM_DIR)/transcript $(CAR_VSIM_DIR)/work + rm -rf $(CAR_VSIM_DIR)/uart $(CAR_VSIM_DIR)/FETCH* $(CAR_VSIM_DIR)/logs $(CAR_VSIM_DIR)/*.ini $(CAR_VSIM_DIR)/trace* $(CAR_VSIM_DIR)/*.wlf $(CAR_VSIM_DIR)/transcript $(CAR_VSIM_DIR)/work $(CAR_VSIM_DIR)/*lib $(CAR_VSIM_DIR)/*Lib $(CAR_VSIM_DIR)/*.vstf $(CAR_VSIM_DIR)/*.log $(CAR_VSIM_DIR)/*.txt .PHONY: car-vsim-sim-run ## Run simulation of the carfield RTL. diff --git a/target/sim/src/carfield_fix.sv b/target/sim/src/carfield_fix.sv index 1f2fc951..6fd02b8f 100644 --- a/target/sim/src/carfield_fix.sv +++ b/target/sim/src/carfield_fix.sv @@ -135,6 +135,12 @@ module carfield_soc_fixture; logic [NumPhys-1:0] hyper_dq_oe_o; logic [NumPhys-1:0] hyper_reset_no; + logic ptme_clk, ptme_enc; + logic tc_active, tc_clock, tc_data; + logic [2:0] hpc_addr; + logic hpc_cmd_en, hpc_smp; + logic [1:0] llc_line; + wire [NumPhys-1:0][NumChips-1:0] pad_hyper_csn; wire [NumPhys-1:0] pad_hyper_ck; wire [NumPhys-1:0] pad_hyper_ckn; @@ -142,6 +148,11 @@ module carfield_soc_fixture; wire [NumPhys-1:0] pad_hyper_resetn; wire [NumPhys-1:0][7:0] pad_hyper_dq; + wire spw_data_in, spw_strobe_in; + wire spw_data_out, spw_strobe_out; + + logic eth_clk; + clk_rst_gen #( .ClkPeriod ( ClkPeriodPeriph ), .RstClkCycles ( RstCycles ) @@ -238,6 +249,24 @@ module carfield_soc_fixture; .hyper_dq_o ( hyper_dq_o ), .hyper_dq_oe_o ( hyper_dq_oe_o ), .hyper_reset_no ( hyper_reset_no ), + .tc_active_i ( tc_active ), + .tc_clock_i ( tc_clock ), + .tc_data_i ( tc_data ), + .ptme_clk_o ( ptme_clk ), + .ptme_enc_o ( ptme_enc ), + .ptme_sync_o ( ), + .ptme_ext_clk_i ( '0 ), + .hpc_addr_o ( hpc_addr ), + .hpc_cmd_en_o ( hpc_cmd_en ), + .hpc_sample_o ( hpc_smp ), + .llc_line_o ( llc_line ), + .obt_ext_clk_i ( '0 ), + .obt_pps_in_i ( '0 ), + .obt_sync_out_o ( ), + .spw_data_i ( spw_data_in ), + .spw_strb_i ( spw_strobe_in ), + .spw_data_o ( spw_data_out ), + .spw_strb_o ( spw_strobe_out ), .ext_reg_async_slv_req_i ( '0 ), .ext_reg_async_slv_ack_o ( ), .ext_reg_async_slv_data_i ( '0 ), @@ -247,9 +276,7 @@ module carfield_soc_fixture; .debug_signals_o ( ) ); - logic eth_clk; - - assign eth_clk = i_dut.gen_ethernet.eth_clk; + assign eth_clk = i_dut.eth_clk; ////////////////// // Carfield VIP // @@ -298,6 +325,19 @@ module carfield_soc_fixture; .axi_slvs_rsp ( ext_to_vip_rsp ), .axi_muxed_req ( axi_muxed_req ), .axi_muxed_rsp ( axi_muxed_rsp ), + .ptme_clk_i ( ptme_clk ), + .ptme_enc_i ( ptme_enc ), + .hpc_addr_i ( hpc_addr ), + .hpc_cmd_en_i ( hpc_cmd_en ), + .hpc_smp_i ( hpc_smp ), + .llc_line_i ( llc_line ), + .tc_active ( tc_active ), + .tc_clk ( tc_clock ), + .tc_data ( tc_data ), + .spw_din ( spw_data_out ), + .spw_sin ( spw_strobe_out), + .spw_dout ( spw_data_in ), + .spw_sout ( spw_strobe_in ), .* ); diff --git a/target/sim/src/vip_carfield_soc.sv b/target/sim/src/vip_carfield_soc.sv index df8aaee8..4dd127f5 100644 --- a/target/sim/src/vip_carfield_soc.sv +++ b/target/sim/src/vip_carfield_soc.sv @@ -64,7 +64,20 @@ module vip_carfield_soc output axi_slv_ext_rsp_t [NumAxiExtSlvPorts-1:0] axi_slvs_rsp, // Multiplexed virtual AXI ports output axi_slv_ext_req_t axi_muxed_req, - input axi_slv_ext_rsp_t axi_muxed_rsp + input axi_slv_ext_rsp_t axi_muxed_rsp, + input logic ptme_clk_i, + input logic ptme_enc_i, + input logic [2:0] hpc_addr_i, + input logic hpc_cmd_en_i, + input logic hpc_smp_i, + input logic [1:0] llc_line_i, + output logic tc_active, + output logic tc_clk, + output logic tc_data, + input logic spw_din, + input logic spw_sin, + output logic spw_dout, + output logic spw_sout ); `include "cheshire/typedef.svh" @@ -367,6 +380,35 @@ end .mst_resp_i ( axi_muxed_rsp ) ); + /* + PTME_EMULATOR i_ptme_emulator ( + .Reset_N ( rst_n ), + .CADUClk ( ptme_clk_i ), + .CADUOut ( ptme_enc_i ) + ); + */ + + tb_MuSA_compact i_tb_MuSA_compact ( + .CADUClk ( ptme_clk_i), + .CADUOut ( ptme_enc_i), + .HPC_ADDR ( hpc_addr_i), + .HPC_CMD_EN ( hpc_cmd_en_i), + .HPC_SMP ( hpc_smp_i), + .LLC_LINE ( llc_line_i), + .RST_BOARD ( rst_n), + .TCA ( tc_active), + .TCC ( tc_clk), + .TCS ( tc_data) + ); + + spw_codec_tb i_spw_codec_tb ( + .DATA_IN (spw_din), + .STROBE_IN (spw_sin), + .DATA_OUT (spw_dout), + .STROBE_OUT(spw_sout) + ); + + endmodule module vip_carfield_soc_tristate import carfield_pkg::*; # (