From f39371538f31dcedc978a24178987c787ad65d62 Mon Sep 17 00:00:00 2001 From: Theo Hill Date: Wed, 10 Jul 2024 02:22:08 -0700 Subject: [PATCH] Prune legacy code -150k loc. Moving from OreSat0 to OreSat0.5 saw significant hardware changes that until this point hadn't been reflected in this repo. This commit removes support for the no longer used hardware, including old boards, drivers for no longer used devices, and STM32F4/L4 microcontrollers entirely. Of note: - The archive is gone. Its contents, like the rest of the removals here can be accessed in git history. - The C3 is now Linux based. Removing the old project means we can drop our custom ChibiOS patches, and also external dependencies on littlefs and OpenCCSDS. - I tried to keep modified files to a minimum but do note sensors.h, can_hw.h, and the app_adcs Makefile. --- .github/workflows/tests.yaml | 18 - .gitmodules | 6 - CONTRIBUTING.md | 3 - Makefile | 2 - README.md | 4 - boards/BATTERY_V1/board.c | 267 - boards/BATTERY_V1/board.h | 973 --- boards/BATTERY_V1/board.mk | 9 - boards/BATTERY_V1/gdboocd.cmd | 2 - boards/BATTERY_V1/oocd.cfg | 9 - boards/BATTERY_V2/board.c | 266 - boards/BATTERY_V2/board.h | 973 --- boards/BATTERY_V2/board.mk | 9 - boards/BATTERY_V2/gdboocd.cmd | 2 - boards/BATTERY_V2/oocd.cfg | 9 - boards/BOARD_TEMPLATE_F4/board.c | 267 - boards/BOARD_TEMPLATE_F4/board.h | 1197 --- boards/BOARD_TEMPLATE_F4/board.mk | 9 - boards/BOARD_TEMPLATE_F4/gdboocd.cmd | 2 - boards/BOARD_TEMPLATE_F4/oocd.cfg | 9 - boards/BOARD_TEMPLATE_L4/board.c | 282 - boards/BOARD_TEMPLATE_L4/board.h | 1452 ---- boards/BOARD_TEMPLATE_L4/board.mk | 9 - boards/BOARD_TEMPLATE_L4/gdboocd.cmd | 2 - boards/BOARD_TEMPLATE_L4/oocd.cfg | 9 - boards/ORESAT_ACS_V4/board.c | 267 - boards/ORESAT_ACS_V4/board.h | 967 --- boards/ORESAT_ACS_V4/board.mk | 9 - boards/ORESAT_ACS_V4/gdboocd.cmd | 2 - boards/ORESAT_ACS_V4/oocd.cfg | 9 - boards/ORESAT_C3_V1/board.c | 267 - boards/ORESAT_C3_V1/board.h | 1346 ---- boards/ORESAT_C3_V1/board.mk | 9 - boards/ORESAT_C3_V1/gdboocd.cmd | 2 - boards/ORESAT_C3_V1/oocd.cfg | 9 - boards/ORESAT_C3_V3/board.c | 267 - boards/ORESAT_C3_V3/board.h | 1217 --- boards/ORESAT_C3_V3/board.mk | 9 - boards/ORESAT_C3_V3/gdboocd.cmd | 2 - boards/ORESAT_C3_V3/oocd.cfg | 9 - boards/ORESAT_C3_V4/board.c | 267 - boards/ORESAT_C3_V4/board.h | 1355 ---- boards/ORESAT_C3_V4/board.mk | 9 - boards/ORESAT_C3_V4/gdboocd.cmd | 2 - boards/ORESAT_C3_V4/oocd.cfg | 9 - boards/ORESAT_C3_V5/board.c | 267 - boards/ORESAT_C3_V5/board.h | 1355 ---- boards/ORESAT_C3_V5/board.mk | 9 - boards/ORESAT_C3_V5/gdboocd.cmd | 2 - boards/ORESAT_C3_V5/oocd.cfg | 9 - boards/ORESAT_RWB_V1_1/board.c | 267 - boards/ORESAT_RWB_V1_1/board.h | 927 --- boards/ORESAT_RWB_V1_1/board.mk | 9 - boards/ORESAT_RWB_V1_1/gdboocd.cmd | 2 - boards/ORESAT_RWB_V1_1/oocd.cfg | 9 - boards/ORESAT_RWB_V3/board.c | 267 - boards/ORESAT_RWB_V3/board.h | 925 --- boards/ORESAT_RWB_V3/board.mk | 9 - boards/ORESAT_RWB_V3/gdboocd.cmd | 2 - boards/ORESAT_RWB_V3/oocd.cfg | 9 - boards/ORESAT_RWB_V4/board.c | 282 - boards/ORESAT_RWB_V4/board.h | 1466 ---- boards/ORESAT_RWB_V4/board.mk | 9 - boards/ORESAT_RWB_V4/gdboocd.cmd | 2 - boards/ORESAT_RWB_V4/oocd.cfg | 9 - boards/PROTOCARD_V1_1/board.c | 267 - boards/PROTOCARD_V1_1/board.h | 934 --- boards/PROTOCARD_V1_1/board.mk | 9 - boards/PROTOCARD_V1_1/gdboocd.cmd | 2 - boards/PROTOCARD_V1_1/oocd.cfg | 9 - boards/PROTOCARD_V2/board.c | 267 - boards/PROTOCARD_V2/board.h | 934 --- boards/PROTOCARD_V2/board.mk | 9 - boards/PROTOCARD_V2/gdboocd.cmd | 2 - boards/PROTOCARD_V2/oocd.cfg | 9 - boards/PROTOCARD_V3/board.c | 267 - boards/PROTOCARD_V3/board.h | 958 --- boards/PROTOCARD_V3/board.mk | 9 - boards/PROTOCARD_V3/gdboocd.cmd | 2 - boards/PROTOCARD_V3/oocd.cfg | 9 - boards/README.md | 0 boards/SOLAR_V1/board.c | 267 - boards/SOLAR_V1/board.h | 926 --- boards/SOLAR_V1/board.mk | 9 - boards/SOLAR_V1/gdboocd.cmd | 2 - boards/SOLAR_V1/oocd.cfg | 9 - boards/SOLAR_V2/board.c | 267 - boards/SOLAR_V2/board.h | 961 --- boards/SOLAR_V2/board.mk | 9 - boards/SOLAR_V2/gdboocd.cmd | 2 - boards/SOLAR_V2/oocd.cfg | 9 - boards/SOLAR_V3/board.c | 267 - boards/SOLAR_V3/board.h | 962 --- boards/SOLAR_V3/board.mk | 9 - boards/SOLAR_V3/gdboocd.cmd | 2 - boards/SOLAR_V3/oocd.cfg | 9 - boards/SOLAR_V4/board.c | 267 - boards/SOLAR_V4/board.h | 961 --- boards/SOLAR_V4/board.mk | 9 - boards/SOLAR_V4/gdboocd.cmd | 2 - boards/SOLAR_V4/oocd.cfg | 9 - boards/ST_NUCLEO144_F439ZI/board.c | 267 - boards/ST_NUCLEO144_F439ZI/board.h | 1201 --- boards/ST_NUCLEO144_F439ZI/board.mk | 9 - boards/ST_NUCLEO144_F439ZI/gdboocd.cmd | 2 - boards/ST_NUCLEO144_F439ZI/oocd.cfg | 9 - boards/ST_NUCLEO32_F042K6/board.c | 267 - boards/ST_NUCLEO32_F042K6/board.h | 966 --- boards/ST_NUCLEO32_F042K6/board.mk | 9 - boards/ST_NUCLEO32_F042K6/gdboocd.cmd | 2 - boards/ST_NUCLEO32_F042K6/oocd.cfg | 9 - boards/ST_NUCLEO64_F446RE/board.c | 267 - boards/ST_NUCLEO64_F446RE/board.h | 1344 ---- boards/ST_NUCLEO64_F446RE/board.mk | 9 - boards/ST_NUCLEO64_F446RE/gdboocd.cmd | 2 - boards/ST_NUCLEO64_F446RE/oocd.cfg | 9 - boards/ST_NUCLEO64_L452RE_P/board.c | 282 - boards/ST_NUCLEO64_L452RE_P/board.h | 1555 ---- boards/ST_NUCLEO64_L452RE_P/board.mk | 9 - boards/ST_NUCLEO64_L452RE_P/gdboocd.cmd | 2 - boards/ST_NUCLEO64_L452RE_P/oocd.cfg | 9 - common/README.md | 1 - common/aprs.c | 35 - common/aprs.mk | 10 - common/ax25.c | 56 - common/ax5043.c | 1365 ---- common/ax5043.mk | 9 - common/bootloader.mk | 7 - common/can_bootloader.c | 942 --- common/can_hw.c | 3 - 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src/l4/app_devboard_cpp/cfg/CO_driver_custom.h delete mode 100644 src/l4/app_devboard_cpp/cfg/chconf.h delete mode 100644 src/l4/app_devboard_cpp/cfg/halconf.h delete mode 100644 src/l4/app_devboard_cpp/cfg/mcuconf.h delete mode 100644 src/l4/app_devboard_cpp/main.cpp delete mode 100644 src/l4/app_devboard_cpp/od/app.eds delete mode 100644 src/l4/app_devboard_cpp/source/README.md delete mode 100644 src/l4/app_devboard_cpp/source/blink.cpp delete mode 100644 src/l4/app_devboard_cpp/source/blink.h diff --git a/.github/workflows/tests.yaml b/.github/workflows/tests.yaml index 8b4a95b4..de67d3dd 100644 --- a/.github/workflows/tests.yaml +++ b/.github/workflows/tests.yaml @@ -34,13 +34,6 @@ jobs: sudo apt update sudo apt install -y gcc-arm-none-eabi srecord xxd - - name: Apply C3 patches - working-directory: - ext/ChibiOS - run: | - patch -p0 < ../../src/f4/app_control/stm32f42x_43x_efl.patch - patch -p1 < ../../src/f4/app_control/stm32f439_hmacsha256.patch - - name: Compile f0 apps run: | make -C src/f0/app_battery @@ -49,14 +42,3 @@ jobs: make -C src/f0/app_devboard make -C src/f0/app_adcs make -C src/f0/app_solar - - - name: Compile f4 apps - run: | - make -C src/f4/app_blinky - make -C src/f4/app_cantest - - - name: Compile l4 apps - run: | - make -C src/l4/app_blinky - make -C src/l4/app_devboard - make -C src/l4/app_devboard_cpp diff --git a/.gitmodules b/.gitmodules index e4692aa3..71c14e5e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,9 +4,3 @@ [submodule "ext/CANopenNode"] path = ext/CANopenNode url = https://github.com/CANopenNode/CANopenNode.git -[submodule "ext/littlefs"] - path = ext/littlefs - url = https://github.com/littlefs-project/littlefs -[submodule "ext/OpenCCSDS"] - path = ext/OpenCCSDS - url = https://github.com/oresat/OpenCCSDS.git diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 4f281455..a6cca803 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -30,9 +30,6 @@ Join one of our meetings. Meetings can be found in [Our Calendar](https://calend Here are links to some of our supported development boards. * [NUCLEO-F091RC](https://www.mouser.com/ProductDetail/STMicroelectronics/NUCLEO-F091RC?qs=CE9ecZDhCK0jcTHFYd%2Fi5g%3D%3D#.YoAe6h4MCag.link) - * [NUCLEO-F446RE](https://www.mouser.com/ProductDetail/STMicroelectronics/NUCLEO-F446RE?qs=PRtH0mD6DWYnuBoPSlbRCA%3D%3D) - * [NUCLEO-L452RE](https://www.mouser.com/ProductDetail/STMicroelectronics/NUCLEO-L452RE?qs=zwwtnr6GuIyXyX5dw%2FgKaw%3D%3D) - * [NUCLEO-F439ZI](https://www.mouser.com/ProductDetail/STMicroelectronics/NUCLEO-F439ZI?qs=w%2Fv1CP2dgqohyY3gLxBfCw%3D%3D) Be sure to test with [app_blinky](https://github.com/oresat/oresat-firmware#test-your-toolchain)! diff --git a/Makefile b/Makefile index 9ce68802..e3b14219 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,6 @@ TOPTARGETS := all clean SUBDIRS := $(wildcard src/f0/*/.) -SUBDIRS += $(wildcard src/l4/*/.) -SUBDIRS += $(wildcard src/f4/*/.) $(TOPTARGETS): $(SUBDIRS) $(SUBDIRS): diff --git a/README.md b/README.md index c741ebcc..8a18d3ce 100644 --- a/README.md +++ b/README.md @@ -97,8 +97,6 @@ for details on how to do this on a per-system basis. #### Test your toolchain To test that your build system works correctly, it's recommended that you build one of the `app_blinky` applications and write it to a dev board successfully. Here are the links for the various versions of the app with further documentation: * [NUCLEO64_STM32F091RC](src/f0/app_blinky) -* [NUCLEO144 STM32F439ZI](src/f4/app_blinky) -* [NUCLEO64 STM32L452RE](src/l4/app_blinky) ### Creating an app Once you have a working toolchain in place, the next step is to copy an existing @@ -107,8 +105,6 @@ supported MCUs for OreSat are listed below, and link to the relevant folders and #### Supported MCUs * [STM32F091xC](src/f0) -* [STM32F439Zx](src/f4) -* [STM32L452RE](src/l4) ## Subsystems ### ACS (Attitude Control System) diff --git a/boards/BATTERY_V1/board.c b/boards/BATTERY_V1/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/BATTERY_V1/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/BATTERY_V1/board.h b/boards/BATTERY_V1/board.h deleted file mode 100644 index ed06e434..00000000 --- a/boards/BATTERY_V1/board.h +++ /dev/null @@ -1,973 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Battery V1 Board Configuration - * PART: STM32F091CC - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_BATTERY_V1 -#define BOARD_NAME "Battery v1.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F091xC - -/* - * IO pins assignments. - */ -#define GPIOA_LED 0U -#define GPIOA_DCHG_STAT_PK1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_CHG_DIS_PK1 4U -#define GPIOA_DCHG_DIS_PK1 5U -#define GPIOA_FASTCHG_PK1 6U -#define GPIOA_CHG_STAT_PK1 7U -#define GPIOA_POUTPROT 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_CHG_DIS_PK2 0U -#define GPIOB_DCHG_DIS_PK2 1U -#define GPIOB_FASTCHG_PK2 2U -#define GPIOB_PIN3 3U -#define GPIOB_ALERT_PK2 4U -#define GPIOB_ALERT_PK1 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_CHG_STAT_PK2 10U -#define GPIOB_DCHG_STAT_PK2 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_MOARPWR 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_BOOT0 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) -#define LINE_DCHG_STAT_PK1 PAL_LINE(GPIOA, 1U) -#define LINE_CHG_DIS_PK1 PAL_LINE(GPIOA, 4U) -#define LINE_DCHG_DIS_PK1 PAL_LINE(GPIOA, 5U) -#define LINE_FASTCHG_PK1 PAL_LINE(GPIOA, 6U) -#define LINE_CHG_STAT_PK1 PAL_LINE(GPIOA, 7U) -#define LINE_CAN_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_CHG_DIS_PK2 PAL_LINE(GPIOB, 0U) -#define LINE_DCHG_DIS_PK2 PAL_LINE(GPIOB, 1U) -#define LINE_FASTCHG_PK2 PAL_LINE(GPIOB, 2U) -#define LINE_ALERT_PK2 PAL_LINE(GPIOB, 4U) -#define LINE_ALERT_PK1 PAL_LINE(GPIOB, 5U) -#define LINE_CHG_STAT_PK2 PAL_LINE(GPIOB, 10U) -#define LINE_DCHG_STAT_PK2 PAL_LINE(GPIOB, 11U) -#define LINE_MOARPWR PAL_LINE(GPIOB, 14U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - DCHG_STAT_PK1 (input). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - CHG_DIS_PK1 (output pushpull maximum). - * PA5 - DCHG_DIS_PK1 (output pushpull maximum). - * PA6 - FASTCHG_PK1 (output pushpull maximum). - * PA7 - CHG_STAT_PK1 (input). - * PA8 - POUTPROT (analog). - * PA9 - CAN_SILENT (output pushpull maximum). - * PA10 - CAN_SHDN (output pushpull maximum). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_INPUT(GPIOA_DCHG_STAT_PK1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_OUTPUT(GPIOA_CHG_DIS_PK1) | \ - PIN_MODE_OUTPUT(GPIOA_DCHG_DIS_PK1) | \ - PIN_MODE_OUTPUT(GPIOA_FASTCHG_PK1) | \ - PIN_MODE_INPUT(GPIOA_CHG_STAT_PK1) | \ - PIN_MODE_ANALOG(GPIOA_POUTPROT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_DCHG_STAT_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CHG_DIS_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_DCHG_DIS_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_FASTCHG_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CHG_STAT_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_POUTPROT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_DCHG_STAT_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CHG_DIS_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_DCHG_DIS_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_FASTCHG_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_CHG_STAT_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_POUTPROT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_LED) | \ - PIN_PUPDR_PULLDOWN(GPIOA_DCHG_STAT_PK1) |\ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CHG_DIS_PK1) |\ - PIN_PUPDR_PULLDOWN(GPIOA_DCHG_DIS_PK1) |\ - PIN_PUPDR_PULLDOWN(GPIOA_FASTCHG_PK1) |\ - PIN_PUPDR_PULLDOWN(GPIOA_CHG_STAT_PK1) |\ - PIN_PUPDR_FLOATING(GPIOA_POUTPROT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_LOW(GPIOA_DCHG_STAT_PK1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_LOW(GPIOA_CHG_DIS_PK1) | \ - PIN_ODR_LOW(GPIOA_DCHG_DIS_PK1) | \ - PIN_ODR_LOW(GPIOA_FASTCHG_PK1) | \ - PIN_ODR_HIGH(GPIOA_CHG_STAT_PK1) | \ - PIN_ODR_HIGH(GPIOA_POUTPROT) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_DCHG_STAT_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_CHG_DIS_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_DCHG_DIS_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_FASTCHG_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_CHG_STAT_PK1, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_POUTPROT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - CHG_DIS_PK2 (output pushpull maximum). - * PB1 - DCHG_DIS_PK2 (output pushpull maximum). - * PB2 - FASTCHG_PK2 (output pushpull maximum). - * PB3 - PIN3 (analog). - * PB4 - ALERT_PK2 (input). - * PB5 - ALERT_PK1 (input). - * PB6 - I2C1_SCL (alternate 1). - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - CHG_STAT_PK2 (input). - * PB11 - DCHG_STAT_PK2 (input). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - MOARPWR (output pushpull maximum). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_CHG_DIS_PK2) | \ - PIN_MODE_OUTPUT(GPIOB_DCHG_DIS_PK2) | \ - PIN_MODE_OUTPUT(GPIOB_FASTCHG_PK2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_ALERT_PK2) | \ - PIN_MODE_INPUT(GPIOB_ALERT_PK1) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_CHG_STAT_PK2) | \ - PIN_MODE_INPUT(GPIOB_DCHG_STAT_PK2) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_OUTPUT(GPIOB_MOARPWR) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_CHG_DIS_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_DCHG_DIS_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_FASTCHG_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ALERT_PK2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ALERT_PK1) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CHG_STAT_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_DCHG_STAT_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MOARPWR) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_CHG_DIS_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_DCHG_DIS_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_FASTCHG_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_ALERT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_ALERT_PK1) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_CHG_STAT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_DCHG_STAT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_MOARPWR) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(GPIOB_CHG_DIS_PK2) |\ - PIN_PUPDR_PULLDOWN(GPIOB_DCHG_DIS_PK2) |\ - PIN_PUPDR_PULLDOWN(GPIOB_FASTCHG_PK2) |\ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_ALERT_PK2) | \ - PIN_PUPDR_FLOATING(GPIOB_ALERT_PK1) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_CHG_STAT_PK2) |\ - PIN_PUPDR_FLOATING(GPIOB_DCHG_STAT_PK2) |\ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_PULLDOWN(GPIOB_MOARPWR) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_CHG_DIS_PK2) | \ - PIN_ODR_LOW(GPIOB_DCHG_DIS_PK2) | \ - PIN_ODR_LOW(GPIOB_FASTCHG_PK2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_ALERT_PK2) | \ - PIN_ODR_HIGH(GPIOB_ALERT_PK1) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_CHG_STAT_PK2) | \ - PIN_ODR_HIGH(GPIOB_DCHG_STAT_PK2) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_MOARPWR) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_CHG_DIS_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_DCHG_DIS_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_FASTCHG_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_ALERT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_ALERT_PK1, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_CHG_STAT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_DCHG_STAT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_MOARPWR, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - BOOT0 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_BOOT0) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_BOOT0) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/BATTERY_V1/board.mk b/boards/BATTERY_V1/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/BATTERY_V1/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/BATTERY_V1/gdboocd.cmd b/boards/BATTERY_V1/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/BATTERY_V1/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/BATTERY_V1/oocd.cfg b/boards/BATTERY_V1/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/BATTERY_V1/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/BATTERY_V2/board.c b/boards/BATTERY_V2/board.c deleted file mode 100644 index 9427402d..00000000 --- a/boards/BATTERY_V2/board.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/BATTERY_V2/board.h b/boards/BATTERY_V2/board.h deleted file mode 100644 index 8dd7af61..00000000 --- a/boards/BATTERY_V2/board.h +++ /dev/null @@ -1,973 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Battery V1 Board Configuration - * PART: STM32F091CC - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_BATTERY_V2 -#define BOARD_NAME "Battery v2.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F091xC - -/* - * IO pins assignments. - */ -#define GPIOA_LED 0U -#define GPIOA_DCHG_STAT_PK1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_CHG_DIS_PK1 4U -#define GPIOA_DCHG_DIS_PK1 5U -#define GPIOA_PIN6 6U -#define GPIOA_CHG_STAT_PK1 7U -#define GPIOA_POUTPROT 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_CHG_DIS_PK2 0U -#define GPIOB_DCHG_DIS_PK2 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_ALERT_PK2 4U -#define GPIOB_ALERT_PK1 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_CHG_STAT_PK2 10U -#define GPIOB_DCHG_STAT_PK2 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_MOARPWR 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_HEATER_ON_1 14U -#define GPIOC_HEATER_ON_2 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_BOOT0 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) -#define LINE_DCHG_STAT_PK1 PAL_LINE(GPIOA, 1U) -#define LINE_CHG_DIS_PK1 PAL_LINE(GPIOA, 4U) -#define LINE_DCHG_DIS_PK1 PAL_LINE(GPIOA, 5U) -#define LINE_CHG_STAT_PK1 PAL_LINE(GPIOA, 7U) -#define LINE_CAN_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_CHG_DIS_PK2 PAL_LINE(GPIOB, 0U) -#define LINE_DCHG_DIS_PK2 PAL_LINE(GPIOB, 1U) -#define LINE_ALERT_PK2 PAL_LINE(GPIOB, 4U) -#define LINE_ALERT_PK1 PAL_LINE(GPIOB, 5U) -#define LINE_CHG_STAT_PK2 PAL_LINE(GPIOB, 10U) -#define LINE_DCHG_STAT_PK2 PAL_LINE(GPIOB, 11U) -#define LINE_MOARPWR PAL_LINE(GPIOB, 14U) -#define LINE_HEATER_ON_1 PAL_LINE(GPIOC, 14U) -#define LINE_HEATER_ON_2 PAL_LINE(GPIOC, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - DCHG_STAT_PK1 (input). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - CHG_DIS_PK1 (output pushpull maximum). - * PA5 - DCHG_DIS_PK1 (output pushpull maximum). - * PA6 - PIN6 (output pushpull maximum). - * PA7 - CHG_STAT_PK1 (input). - * PA8 - POUTPROT (analog). - * PA9 - CAN_SILENT (output pushpull maximum). - * PA10 - CAN_SHDN (output pushpull maximum). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_INPUT(GPIOA_DCHG_STAT_PK1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_OUTPUT(GPIOA_CHG_DIS_PK1) | \ - PIN_MODE_OUTPUT(GPIOA_DCHG_DIS_PK1) | \ - PIN_MODE_OUTPUT(GPIOA_PIN6) | \ - PIN_MODE_INPUT(GPIOA_CHG_STAT_PK1) | \ - PIN_MODE_ANALOG(GPIOA_POUTPROT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_DCHG_STAT_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CHG_DIS_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_DCHG_DIS_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CHG_STAT_PK1) |\ - PIN_OTYPE_PUSHPULL(GPIOA_POUTPROT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_DCHG_STAT_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CHG_DIS_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_DCHG_DIS_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_CHG_STAT_PK1) | \ - PIN_OSPEED_HIGH(GPIOA_POUTPROT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_LED) | \ - PIN_PUPDR_PULLDOWN(GPIOA_DCHG_STAT_PK1) |\ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CHG_DIS_PK1) |\ - PIN_PUPDR_PULLDOWN(GPIOA_DCHG_DIS_PK1) |\ - PIN_PUPDR_PULLDOWN(GPIOA_PIN6) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CHG_STAT_PK1) |\ - PIN_PUPDR_FLOATING(GPIOA_POUTPROT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_LOW(GPIOA_DCHG_STAT_PK1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_LOW(GPIOA_CHG_DIS_PK1) | \ - PIN_ODR_LOW(GPIOA_DCHG_DIS_PK1) | \ - PIN_ODR_LOW(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_CHG_STAT_PK1) | \ - PIN_ODR_HIGH(GPIOA_POUTPROT) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_DCHG_STAT_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_CHG_DIS_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_DCHG_DIS_PK1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_CHG_STAT_PK1, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_POUTPROT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - CHG_DIS_PK2 (output pushpull maximum). - * PB1 - DCHG_DIS_PK2 (output pushpull maximum). - * PB2 - PIN2 (output pushpull maximum). - * PB3 - PIN3 (analog). - * PB4 - ALERT_PK2 (input). - * PB5 - ALERT_PK1 (input). - * PB6 - I2C1_SCL (alternate 1). - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - CHG_STAT_PK2 (input). - * PB11 - DCHG_STAT_PK2 (input). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - MOARPWR (output pushpull maximum). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_CHG_DIS_PK2) | \ - PIN_MODE_OUTPUT(GPIOB_DCHG_DIS_PK2) | \ - PIN_MODE_OUTPUT(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_ALERT_PK2) | \ - PIN_MODE_INPUT(GPIOB_ALERT_PK1) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_CHG_STAT_PK2) | \ - PIN_MODE_INPUT(GPIOB_DCHG_STAT_PK2) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_OUTPUT(GPIOB_MOARPWR) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_CHG_DIS_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_DCHG_DIS_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ALERT_PK2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ALERT_PK1) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CHG_STAT_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_DCHG_STAT_PK2) |\ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MOARPWR) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_CHG_DIS_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_DCHG_DIS_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_ALERT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_ALERT_PK1) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_CHG_STAT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_DCHG_STAT_PK2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_MOARPWR) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(GPIOB_CHG_DIS_PK2) |\ - PIN_PUPDR_PULLDOWN(GPIOB_DCHG_DIS_PK2) |\ - PIN_PUPDR_PULLDOWN(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_ALERT_PK2) | \ - PIN_PUPDR_FLOATING(GPIOB_ALERT_PK1) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_CHG_STAT_PK2) |\ - PIN_PUPDR_FLOATING(GPIOB_DCHG_STAT_PK2) |\ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_PULLDOWN(GPIOB_MOARPWR) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_CHG_DIS_PK2) | \ - PIN_ODR_LOW(GPIOB_DCHG_DIS_PK2) | \ - PIN_ODR_LOW(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_ALERT_PK2) | \ - PIN_ODR_HIGH(GPIOB_ALERT_PK1) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_CHG_STAT_PK2) | \ - PIN_ODR_HIGH(GPIOB_DCHG_STAT_PK2) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_MOARPWR) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_CHG_DIS_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_DCHG_DIS_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_ALERT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_ALERT_PK1, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_CHG_STAT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_DCHG_STAT_PK2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_MOARPWR, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - HEATER_ON_1 (output pushpull maximum). - * PC15 - HEATER_ON_2 (output pushpull maximum). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_OUTPUT(GPIOC_HEATER_ON_1) | \ - PIN_MODE_OUTPUT(GPIOC_HEATER_ON_2)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_HEATER_ON_1) |\ - PIN_OTYPE_PUSHPULL(GPIOC_HEATER_ON_2)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_HEATER_ON_1) | \ - PIN_OSPEED_HIGH(GPIOC_HEATER_ON_2)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_HEATER_ON_1) |\ - PIN_PUPDR_FLOATING(GPIOC_HEATER_ON_2)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_LOW(GPIOC_HEATER_ON_1) | \ - PIN_ODR_LOW(GPIOC_HEATER_ON_2)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_HEATER_ON_1, 0U) | \ - PIN_AFIO_AF(GPIOC_HEATER_ON_2, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - BOOT0 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_BOOT0) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_BOOT0) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/BATTERY_V2/board.mk b/boards/BATTERY_V2/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/BATTERY_V2/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/BATTERY_V2/gdboocd.cmd b/boards/BATTERY_V2/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/BATTERY_V2/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/BATTERY_V2/oocd.cfg b/boards/BATTERY_V2/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/BATTERY_V2/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/BOARD_TEMPLATE_F4/board.c b/boards/BOARD_TEMPLATE_F4/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/BOARD_TEMPLATE_F4/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/BOARD_TEMPLATE_F4/board.h b/boards/BOARD_TEMPLATE_F4/board.h deleted file mode 100644 index ab66e6aa..00000000 --- a/boards/BOARD_TEMPLATE_F4/board.h +++ /dev/null @@ -1,1197 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Board description - * PART: PART_NUM - * PACKAGE: PACKAGE - */ - -/* - * Board identifier. - */ -#define BOARD_TEMPLATE_F4 -#define BOARD_NAME "Board name" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* #define STM32_HSE_BYPASS */ - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F446xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_PIN7 7U -#define GPIOA_PIN8 8U -#define GPIOA_PIN9 9U -#define GPIOA_PIN10 10U -#define GPIOA_PIN11 11U -#define GPIOA_PIN12 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_PIN7 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -//#define LINE_PIN0 PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 (analog). - * PA3 - PIN3 (analog). - * PA4 - PIN4 (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - PIN7 (analog). - * PA8 - PIN8 (analog). - * PA9 - PIN9 (analog). - * PA10 - PIN10 (analog). - * PA11 - PIN11 (analog). - * PA12 - PIN12 (analog). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ANALOG(GPIOA_PIN2) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_ANALOG(GPIOA_PIN9) | \ - PIN_MODE_ANALOG(GPIOA_PIN10) | \ - PIN_MODE_ANALOG(GPIOA_PIN11) | \ - PIN_MODE_ANALOG(GPIOA_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_PIN9) | \ - PIN_OSPEED_HIGH(GPIOA_PIN10) | \ - PIN_OSPEED_HIGH(GPIOA_PIN11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN12) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_PIN11) | \ - PIN_ODR_HIGH(GPIOA_PIN12) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN2 (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - PIN6 (analog). - * PB7 - PIN7 (analog). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ANALOG(GPIOB_PIN6) | \ - PIN_MODE_ANALOG(GPIOB_PIN7) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_PIN6) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 5U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 5U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 5U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 5U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - OSC32_IN (analog). - * PC15 - OSC32_OUT (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/BOARD_TEMPLATE_F4/board.mk b/boards/BOARD_TEMPLATE_F4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/BOARD_TEMPLATE_F4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/BOARD_TEMPLATE_F4/gdboocd.cmd b/boards/BOARD_TEMPLATE_F4/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/BOARD_TEMPLATE_F4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/BOARD_TEMPLATE_F4/oocd.cfg b/boards/BOARD_TEMPLATE_F4/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/BOARD_TEMPLATE_F4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/BOARD_TEMPLATE_L4/board.c b/boards/BOARD_TEMPLATE_L4/board.c deleted file mode 100644 index 274c5b8c..00000000 --- a/boards/BOARD_TEMPLATE_L4/board.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; - uint32_t ascr; - uint32_t lockr; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, - VAL_GPIOA_LOCKR}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, - VAL_GPIOB_LOCKR}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, - VAL_GPIOC_LOCKR}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, - VAL_GPIOD_LOCKR}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, - VAL_GPIOE_LOCKR}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, - VAL_GPIOF_LOCKR}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, - VAL_GPIOG_LOCKR}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, - VAL_GPIOH_LOCKR}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, - VAL_GPIOI_LOCKR}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, - VAL_GPIOJ_LOCKR}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, - VAL_GPIOK_LOCKR} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB2(STM32_GPIO_EN_MASK); - rccEnableAHB2(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/BOARD_TEMPLATE_L4/board.h b/boards/BOARD_TEMPLATE_L4/board.h deleted file mode 100644 index 9790b81b..00000000 --- a/boards/BOARD_TEMPLATE_L4/board.h +++ /dev/null @@ -1,1452 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Board description - * PART: PART_NUM - * PACKAGE: PACKAGE - */ - -/* - * Board identifier. - */ -#define BOARD_TEMPLATE_L4 -#define BOARD_NAME "Board name" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32L452xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_PIN7 7U -#define GPIOA_PIN8 8U -#define GPIOA_PIN9 9U -#define GPIOA_PIN10 10U -#define GPIOA_PIN11 11U -#define GPIOA_PIN12 12U -#define GPIOA_PIN13 13U -#define GPIOA_PIN14 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_PIN7 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -//#define LINE_PIN0 PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) -#define PIN_ASCR_DISABLED(n) (0U << (n)) -#define PIN_ASCR_ENABLED(n) (1U << (n)) -#define PIN_LOCKR_DISABLED(n) (0U << (n)) -#define PIN_LOCKR_ENABLED(n) (1U << (n)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 (analog). - * PA3 - PIN3 (analog). - * PA4 - PIN4 (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - PIN7 (analog). - * PA8 - PIN8 (analog). - * PA9 - PIN9 (analog). - * PA10 - PIN10 (analog). - * PA11 - PIN11 (analog). - * PA12 - PIN12 (analog). - * PA13 - PIN13 (analog). - * PA14 - PIN14 (analog). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ANALOG(GPIOA_PIN2) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_ANALOG(GPIOA_PIN9) | \ - PIN_MODE_ANALOG(GPIOA_PIN10) | \ - PIN_MODE_ANALOG(GPIOA_PIN11) | \ - PIN_MODE_ANALOG(GPIOA_PIN12) | \ - PIN_MODE_ANALOG(GPIOA_PIN13) | \ - PIN_MODE_ANALOG(GPIOA_PIN14) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_PIN9) | \ - PIN_OSPEED_HIGH(GPIOA_PIN10) | \ - PIN_OSPEED_HIGH(GPIOA_PIN11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN12) | \ - PIN_OSPEED_HIGH(GPIOA_PIN13) | \ - PIN_OSPEED_HIGH(GPIOA_PIN14) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_PIN11) | \ - PIN_ODR_HIGH(GPIOA_PIN12) | \ - PIN_ODR_HIGH(GPIOA_PIN13) | \ - PIN_ODR_HIGH(GPIOA_PIN14) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) -#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_PIN0) | \ - PIN_ASCR_DISABLED(GPIOA_PIN1) | \ - PIN_ASCR_DISABLED(GPIOA_PIN2) | \ - PIN_ASCR_DISABLED(GPIOA_PIN3) | \ - PIN_ASCR_DISABLED(GPIOA_PIN4) | \ - PIN_ASCR_DISABLED(GPIOA_PIN5) | \ - PIN_ASCR_DISABLED(GPIOA_PIN6) | \ - PIN_ASCR_DISABLED(GPIOA_PIN7) | \ - PIN_ASCR_DISABLED(GPIOA_PIN8) | \ - PIN_ASCR_DISABLED(GPIOA_PIN9) | \ - PIN_ASCR_DISABLED(GPIOA_PIN10) | \ - PIN_ASCR_DISABLED(GPIOA_PIN11) | \ - PIN_ASCR_DISABLED(GPIOA_PIN12) | \ - PIN_ASCR_DISABLED(GPIOA_PIN13) | \ - PIN_ASCR_DISABLED(GPIOA_PIN14) | \ - PIN_ASCR_DISABLED(GPIOA_PIN15)) -#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN15)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN2 (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - PIN6 (analog). - * PB7 - PIN7 (analog). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ANALOG(GPIOB_PIN6) | \ - PIN_MODE_ANALOG(GPIOB_PIN7) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_PIN6) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) -#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \ - PIN_ASCR_DISABLED(GPIOB_PIN1) | \ - PIN_ASCR_DISABLED(GPIOB_PIN2) | \ - PIN_ASCR_DISABLED(GPIOB_PIN3) | \ - PIN_ASCR_DISABLED(GPIOB_PIN4) | \ - PIN_ASCR_DISABLED(GPIOB_PIN5) | \ - PIN_ASCR_DISABLED(GPIOB_PIN6) | \ - PIN_ASCR_DISABLED(GPIOB_PIN7) | \ - PIN_ASCR_DISABLED(GPIOB_PIN8) | \ - PIN_ASCR_DISABLED(GPIOB_PIN9) | \ - PIN_ASCR_DISABLED(GPIOB_PIN10) | \ - PIN_ASCR_DISABLED(GPIOB_PIN11) | \ - PIN_ASCR_DISABLED(GPIOB_PIN12) | \ - PIN_ASCR_DISABLED(GPIOB_PIN13) | \ - PIN_ASCR_DISABLED(GPIOB_PIN14) | \ - PIN_ASCR_DISABLED(GPIOB_PIN15)) -#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN15)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) -#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \ - PIN_ASCR_DISABLED(GPIOC_PIN1) | \ - PIN_ASCR_DISABLED(GPIOC_PIN2) | \ - PIN_ASCR_DISABLED(GPIOC_PIN3) | \ - PIN_ASCR_DISABLED(GPIOC_PIN4) | \ - PIN_ASCR_DISABLED(GPIOC_PIN5) | \ - PIN_ASCR_DISABLED(GPIOC_PIN6) | \ - PIN_ASCR_DISABLED(GPIOC_PIN7) | \ - PIN_ASCR_DISABLED(GPIOC_PIN8) | \ - PIN_ASCR_DISABLED(GPIOC_PIN9) | \ - PIN_ASCR_DISABLED(GPIOC_PIN10) | \ - PIN_ASCR_DISABLED(GPIOC_PIN11) | \ - PIN_ASCR_DISABLED(GPIOC_PIN12) | \ - PIN_ASCR_DISABLED(GPIOC_PIN13) | \ - PIN_ASCR_DISABLED(GPIOC_PIN14) | \ - PIN_ASCR_DISABLED(GPIOC_PIN15)) -#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN15)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) -#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ - PIN_ASCR_DISABLED(GPIOD_PIN1) | \ - PIN_ASCR_DISABLED(GPIOD_PIN2) | \ - PIN_ASCR_DISABLED(GPIOD_PIN3) | \ - PIN_ASCR_DISABLED(GPIOD_PIN4) | \ - PIN_ASCR_DISABLED(GPIOD_PIN5) | \ - PIN_ASCR_DISABLED(GPIOD_PIN6) | \ - PIN_ASCR_DISABLED(GPIOD_PIN7) | \ - PIN_ASCR_DISABLED(GPIOD_PIN8) | \ - PIN_ASCR_DISABLED(GPIOD_PIN9) | \ - PIN_ASCR_DISABLED(GPIOD_PIN10) | \ - PIN_ASCR_DISABLED(GPIOD_PIN11) | \ - PIN_ASCR_DISABLED(GPIOD_PIN12) | \ - PIN_ASCR_DISABLED(GPIOD_PIN13) | \ - PIN_ASCR_DISABLED(GPIOD_PIN14) | \ - PIN_ASCR_DISABLED(GPIOD_PIN15)) -#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN15)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) -#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ - PIN_ASCR_DISABLED(GPIOE_PIN1) | \ - PIN_ASCR_DISABLED(GPIOE_PIN2) | \ - PIN_ASCR_DISABLED(GPIOE_PIN3) | \ - PIN_ASCR_DISABLED(GPIOE_PIN4) | \ - PIN_ASCR_DISABLED(GPIOE_PIN5) | \ - PIN_ASCR_DISABLED(GPIOE_PIN6) | \ - PIN_ASCR_DISABLED(GPIOE_PIN7) | \ - PIN_ASCR_DISABLED(GPIOE_PIN8) | \ - PIN_ASCR_DISABLED(GPIOE_PIN9) | \ - PIN_ASCR_DISABLED(GPIOE_PIN10) | \ - PIN_ASCR_DISABLED(GPIOE_PIN11) | \ - PIN_ASCR_DISABLED(GPIOE_PIN12) | \ - PIN_ASCR_DISABLED(GPIOE_PIN13) | \ - PIN_ASCR_DISABLED(GPIOE_PIN14) | \ - PIN_ASCR_DISABLED(GPIOE_PIN15)) -#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN15)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) -#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ - PIN_ASCR_DISABLED(GPIOF_PIN1) | \ - PIN_ASCR_DISABLED(GPIOF_PIN2) | \ - PIN_ASCR_DISABLED(GPIOF_PIN3) | \ - PIN_ASCR_DISABLED(GPIOF_PIN4) | \ - PIN_ASCR_DISABLED(GPIOF_PIN5) | \ - PIN_ASCR_DISABLED(GPIOF_PIN6) | \ - PIN_ASCR_DISABLED(GPIOF_PIN7) | \ - PIN_ASCR_DISABLED(GPIOF_PIN8) | \ - PIN_ASCR_DISABLED(GPIOF_PIN9) | \ - PIN_ASCR_DISABLED(GPIOF_PIN10) | \ - PIN_ASCR_DISABLED(GPIOF_PIN11) | \ - PIN_ASCR_DISABLED(GPIOF_PIN12) | \ - PIN_ASCR_DISABLED(GPIOF_PIN13) | \ - PIN_ASCR_DISABLED(GPIOF_PIN14) | \ - PIN_ASCR_DISABLED(GPIOF_PIN15)) -#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN15)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) -#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ - PIN_ASCR_DISABLED(GPIOG_PIN1) | \ - PIN_ASCR_DISABLED(GPIOG_PIN2) | \ - PIN_ASCR_DISABLED(GPIOG_PIN3) | \ - PIN_ASCR_DISABLED(GPIOG_PIN4) | \ - PIN_ASCR_DISABLED(GPIOG_PIN5) | \ - PIN_ASCR_DISABLED(GPIOG_PIN6) | \ - PIN_ASCR_DISABLED(GPIOG_PIN7) | \ - PIN_ASCR_DISABLED(GPIOG_PIN8) | \ - PIN_ASCR_DISABLED(GPIOG_PIN9) | \ - PIN_ASCR_DISABLED(GPIOG_PIN10) | \ - PIN_ASCR_DISABLED(GPIOG_PIN11) | \ - PIN_ASCR_DISABLED(GPIOG_PIN12) | \ - PIN_ASCR_DISABLED(GPIOG_PIN13) | \ - PIN_ASCR_DISABLED(GPIOG_PIN14) | \ - PIN_ASCR_DISABLED(GPIOG_PIN15)) -#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN15)) - -/* - * GPIOH setup: - * - * PH0 - PIN0 (analog). - * PH1 - PIN1 (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_PIN0) | \ - PIN_MODE_ANALOG(GPIOH_PIN1) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_PIN0) | \ - PIN_OSPEED_HIGH(GPIOH_PIN1) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | \ - PIN_ODR_HIGH(GPIOH_PIN1) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) -#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \ - PIN_ASCR_DISABLED(GPIOH_PIN1) | \ - PIN_ASCR_DISABLED(GPIOH_PIN2) | \ - PIN_ASCR_DISABLED(GPIOH_PIN3) | \ - PIN_ASCR_DISABLED(GPIOH_PIN4) | \ - PIN_ASCR_DISABLED(GPIOH_PIN5) | \ - PIN_ASCR_DISABLED(GPIOH_PIN6) | \ - PIN_ASCR_DISABLED(GPIOH_PIN7) | \ - PIN_ASCR_DISABLED(GPIOH_PIN8) | \ - PIN_ASCR_DISABLED(GPIOH_PIN9) | \ - PIN_ASCR_DISABLED(GPIOH_PIN10) | \ - PIN_ASCR_DISABLED(GPIOH_PIN11) | \ - PIN_ASCR_DISABLED(GPIOH_PIN12) | \ - PIN_ASCR_DISABLED(GPIOH_PIN13) | \ - PIN_ASCR_DISABLED(GPIOH_PIN14) | \ - PIN_ASCR_DISABLED(GPIOH_PIN15)) -#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN15)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/BOARD_TEMPLATE_L4/board.mk b/boards/BOARD_TEMPLATE_L4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/BOARD_TEMPLATE_L4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/BOARD_TEMPLATE_L4/gdboocd.cmd b/boards/BOARD_TEMPLATE_L4/gdboocd.cmd deleted file mode 100644 index d386b739..00000000 --- a/boards/BOARD_TEMPLATE_L4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32l4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/BOARD_TEMPLATE_L4/oocd.cfg b/boards/BOARD_TEMPLATE_L4/oocd.cfg deleted file mode 100644 index 7f81f2b4..00000000 --- a/boards/BOARD_TEMPLATE_L4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32l4x.cfg] - diff --git a/boards/ORESAT_ACS_V4/board.c b/boards/ORESAT_ACS_V4/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/ORESAT_ACS_V4/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_ACS_V4/board.h b/boards/ORESAT_ACS_V4/board.h deleted file mode 100644 index cb918c1e..00000000 --- a/boards/ORESAT_ACS_V4/board.h +++ /dev/null @@ -1,967 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * OreSat ACS V4 Board Configuration - * PART: STM32F091CC - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORESAT_ACS_V4 -#define BOARD_NAME "OreSat ACS v4.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F091xC - -/* - * IO pins assignments. - */ -#define GPIOA_LED 0U -#define GPIOA_PIN1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_PIN7 7U -#define GPIOA_POUTPROT 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_MAG_FAULT 3U -#define GPIOB_MAG_EN 4U -#define GPIOB_MAG_READY 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_IMU_INT1 12U -#define GPIOB_IMU_INT2 13U -#define GPIOB_IMU_INT4 14U -#define GPIOB_IMU_INT3 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_BOOT0 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) -#define LINE_CAN_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_MAG_FAULT PAL_LINE(GPIOB, 3U) -#define LINE_MAG_EN PAL_LINE(GPIOB, 4U) -#define LINE_MAG_READY PAL_LINE(GPIOB, 5U) -#define LINE_IMU_INT1 PAL_LINE(GPIOB, 12U) -#define LINE_IMU_INT2 PAL_LINE(GPIOB, 13U) -#define LINE_IMU_INT4 PAL_LINE(GPIOB, 14U) -#define LINE_IMU_INT3 PAL_LINE(GPIOB, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - PIN1 (analog). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - PIN4 (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - PIN7 (analog). - * PA8 - POUTPROT (analog). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ANALOG(GPIOA_POUTPROT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_POUTPROT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_POUTPROT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_LED) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_POUTPROT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_POUTPROT) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_POUTPROT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN2 (analog). - * PB3 - MAG_FAULT (input). - * PB4 - MAG_EN (output). - * PB5 - MAG_READY (input). - * PB6 - I2C1_SCL (alternate 1). - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - IMU_INT1 (input). - * PB13 - IMU_INT2 (input). - * PB14 - IMU_INT4 (input). - * PB15 - IMU_INT3 (input). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_INPUT(GPIOB_MAG_FAULT) | \ - PIN_MODE_OUTPUT(GPIOB_MAG_EN) | \ - PIN_MODE_INPUT(GPIOB_MAG_READY) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_IMU_INT1) | \ - PIN_MODE_INPUT(GPIOB_IMU_INT2) | \ - PIN_MODE_INPUT(GPIOB_IMU_INT4) | \ - PIN_MODE_INPUT(GPIOB_IMU_INT3)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_READY) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_IMU_INT1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_IMU_INT2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_IMU_INT4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_IMU_INT3)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_FAULT) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_EN) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_READY) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_IMU_INT1) | \ - PIN_OSPEED_HIGH(GPIOB_IMU_INT2) | \ - PIN_OSPEED_HIGH(GPIOB_IMU_INT4) | \ - PIN_OSPEED_HIGH(GPIOB_IMU_INT3)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_EN) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_READY) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_IMU_INT1) | \ - PIN_PUPDR_FLOATING(GPIOB_IMU_INT2) | \ - PIN_PUPDR_FLOATING(GPIOB_IMU_INT4) | \ - PIN_PUPDR_FLOATING(GPIOB_IMU_INT3)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_MAG_FAULT) | \ - PIN_ODR_HIGH(GPIOB_MAG_EN) | \ - PIN_ODR_HIGH(GPIOB_MAG_READY) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_IMU_INT1) | \ - PIN_ODR_HIGH(GPIOB_IMU_INT2) | \ - PIN_ODR_HIGH(GPIOB_IMU_INT4) | \ - PIN_ODR_HIGH(GPIOB_IMU_INT3)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_EN, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_READY, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_IMU_INT1, 0U) | \ - PIN_AFIO_AF(GPIOB_IMU_INT2, 0U) | \ - PIN_AFIO_AF(GPIOB_IMU_INT4, 0U) | \ - PIN_AFIO_AF(GPIOB_IMU_INT3, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - BOOT0 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_BOOT0) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_BOOT0) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_ACS_V4/board.mk b/boards/ORESAT_ACS_V4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_ACS_V4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_ACS_V4/gdboocd.cmd b/boards/ORESAT_ACS_V4/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/ORESAT_ACS_V4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_ACS_V4/oocd.cfg b/boards/ORESAT_ACS_V4/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/ORESAT_ACS_V4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/ORESAT_C3_V1/board.c b/boards/ORESAT_C3_V1/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/ORESAT_C3_V1/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_C3_V1/board.h b/boards/ORESAT_C3_V1/board.h deleted file mode 100644 index 0062bd99..00000000 --- a/boards/ORESAT_C3_V1/board.h +++ /dev/null @@ -1,1346 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * OreSat C3 Prototype Board - * PART: STM32F446RE - * PACKAGE: QFP64 - */ - -/* - * Board identifier. - */ -#define ORESAT_C3_V1 -#define BOARD_NAME "OreSat C3 v1" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* #define STM32_HSE_BYPASS */ - -/* - * Board voltages. - * Required for performance limits calculation. - */ -/* #define STM32_VDD 300U */ - -/* - * MCU type as defined in the ST header. - */ -#define STM32F446xx - -/* - * IO pins assignments. - */ -#define GPIOA_WDT 0U -#define GPIOA_PIN1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_RADIO1_IRQ 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_RADIO2_IRQ 8U -#define GPIOA_CAN1_SILENT 9U -#define GPIOA_CAN1_SHDN 10U -#define GPIOA_CAN1_RX 11U -#define GPIOA_CAN1_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_CB_IOUT 0U -#define GPIOB_OPD_ISET 1U -#define GPIOB_OPD_ENABLE 2U -#define GPIOB_OPD_FAULT 3U -#define GPIOB_CAN2_SHDN 4U -#define GPIOB_CAN2_RX 5U -#define GPIOB_CAN2_TX 6U -#define GPIOB_CAN2_SILENT 7U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_I2C1_SDA 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_SPI2_SCK 13U -#define GPIOB_SPI2_MISO 14U -#define GPIOB_SPI2_MOSI 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_RADIO1_CS 6U -#define GPIOC_RADIO2_CS 7U -#define GPIOC_SDIO_D0 8U -#define GPIOC_SDIO_D1 9U -#define GPIOC_SDIO_D2 10U -#define GPIOC_SDIO_D3 11U -#define GPIOC_SDIO_CK 12U -#define GPIOC_MMC_PWR 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_SDIO_CMD 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_WDT PAL_LINE(GPIOA, 0U) -#define LINE_CAN1_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN1_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_OPD_ENABLE PAL_LINE(GPIOB, 2U) -#define LINE_CAN2_SHDN PAL_LINE(GPIOB, 4U) -#define LINE_CAN2_SILENT PAL_LINE(GPIOB, 7U) -#define LINE_RADIO1_CS PAL_LINE(GPIOC, 6U) -#define LINE_RADIO2_CS PAL_LINE(GPIOC, 7U) -#define LINE_MMC_PWR PAL_LINE(GPIOC, 13U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - WDT (output pushpull maximum). - * PA1 - PIN1 (input pullup). - * PA2 - USART2_TX (alternate 7). - * PA3 - USART2_RX (alternate 7). - * PA4 - RADIO1_IRQ (input pullup). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - SPI1_MOSI (alternate 5). - * PA8 - RADIO2_IRQ (input pullup). - * PA9 - CAN1_SILENT (output pushpull maximum). - * PA10 - CAN1_SHDN (output pushpull maximum). - * PA11 - CAN1_RX (alternate 9). - * PA12 - CAN1_TX (alternate 9). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_WDT) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_RADIO1_IRQ) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_INPUT(GPIOA_RADIO2_IRQ) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_WDT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RADIO1_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RADIO2_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SILENT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_WDT) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_RADIO1_IRQ) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_RADIO2_IRQ) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_WDT) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_RADIO1_IRQ) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOA_RADIO2_IRQ) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN1_SILENT) |\ - PIN_PUPDR_PULLDOWN(GPIOA_CAN1_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN1_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN1_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_WDT) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_RADIO1_IRQ) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_RADIO2_IRQ) | \ - PIN_ODR_LOW(GPIOA_CAN1_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN1_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN1_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_WDT, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 7U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 7U) | \ - PIN_AFIO_AF(GPIOA_RADIO1_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_RADIO2_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_RX, 9U) | \ - PIN_AFIO_AF(GPIOA_CAN1_TX, 9U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - CB_IOUT (analog). - * PB1 - OPD_ISET (analog). - * PB2 - OPD_ENABLE (output pushpull maximum). - * PB3 - OPD_FAULT (input pullup). - * PB4 - CAN2_SHDN (output pushpull maximum). - * PB5 - CAN2_RX (alternate 9). - * PB6 - CAN2_TX (alternate 9). - * PB7 - CAN2_SILENT (output pushpull maximum). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - SPI2_SCK (alternate 5). - * PB14 - SPI2_MISO (alternate 5). - * PB15 - SPI2_MOSI (alternate 5). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_CB_IOUT) | \ - PIN_MODE_ANALOG(GPIOB_OPD_ISET) | \ - PIN_MODE_OUTPUT(GPIOB_OPD_ENABLE) | \ - PIN_MODE_INPUT(GPIOB_OPD_FAULT) | \ - PIN_MODE_OUTPUT(GPIOB_CAN2_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) | \ - PIN_MODE_OUTPUT(GPIOB_CAN2_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_CB_IOUT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OPD_ISET) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_OPD_ENABLE) |\ - PIN_OTYPE_PUSHPULL(GPIOB_OPD_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SILENT) |\ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_CB_IOUT) | \ - PIN_OSPEED_HIGH(GPIOB_OPD_ISET) | \ - PIN_OSPEED_HIGH(GPIOB_OPD_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOB_OPD_FAULT) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SHDN) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_TX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SILENT) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_CB_IOUT) | \ - PIN_PUPDR_FLOATING(GPIOB_OPD_ISET) | \ - PIN_PUPDR_PULLUP(GPIOB_OPD_ENABLE) | \ - PIN_PUPDR_PULLUP(GPIOB_OPD_FAULT) | \ - PIN_PUPDR_PULLDOWN(GPIOB_CAN2_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOB_CAN2_RX) | \ - PIN_PUPDR_PULLUP(GPIOB_CAN2_TX) | \ - PIN_PUPDR_PULLDOWN(GPIOB_CAN2_SILENT) |\ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_SCK) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_CB_IOUT) | \ - PIN_ODR_HIGH(GPIOB_OPD_ISET) | \ - PIN_ODR_HIGH(GPIOB_OPD_ENABLE) | \ - PIN_ODR_HIGH(GPIOB_OPD_FAULT) | \ - PIN_ODR_LOW(GPIOB_CAN2_SHDN) | \ - PIN_ODR_HIGH(GPIOB_CAN2_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN2_TX) | \ - PIN_ODR_LOW(GPIOB_CAN2_SILENT) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ - PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \ - PIN_ODR_HIGH(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_CB_IOUT, 0U) | \ - PIN_AFIO_AF(GPIOB_OPD_ISET, 0U) | \ - PIN_AFIO_AF(GPIOB_OPD_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOB_OPD_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_RX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_TX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SILENT, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \ - PIN_AFIO_AF(GPIOB_SPI2_MISO, 5U) | \ - PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - RADIO1_CS (output pushpull maximum). - * PC7 - RADIO2_CS (output pushpull maximum). - * PC8 - SDIO_D0 (alternate 12). - * PC9 - SDIO_D1 (alternate 12). - * PC10 - SDIO_D2 (alternate 12). - * PC11 - SDIO_D3 (alternate 12). - * PC12 - SDIO_CK (alternate 12). - * PC13 - MMC_PWR (output pushpull maximum). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_OUTPUT(GPIOC_RADIO1_CS) | \ - PIN_MODE_OUTPUT(GPIOC_RADIO2_CS) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \ - PIN_MODE_OUTPUT(GPIOC_MMC_PWR) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RADIO1_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RADIO2_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_CK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_MMC_PWR) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_RADIO1_CS) | \ - PIN_OSPEED_HIGH(GPIOC_RADIO2_CS) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D0) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D1) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D2) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D3) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_CK) | \ - PIN_OSPEED_HIGH(GPIOC_MMC_PWR) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_RADIO1_CS) | \ - PIN_PUPDR_PULLUP(GPIOC_RADIO2_CS) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D0) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D1) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D2) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D3) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_CK) | \ - PIN_PUPDR_PULLUP(GPIOC_MMC_PWR) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_RADIO1_CS) | \ - PIN_ODR_HIGH(GPIOC_RADIO2_CS) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D0) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D1) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D2) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D3) | \ - PIN_ODR_HIGH(GPIOC_SDIO_CK) | \ - PIN_ODR_HIGH(GPIOC_MMC_PWR) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_RADIO1_CS, 0U) | \ - PIN_AFIO_AF(GPIOC_RADIO2_CS, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D1, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D2, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D3, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_CK, 12U) | \ - PIN_AFIO_AF(GPIOC_MMC_PWR, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - SDIO_CMD (alternate 12). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_SDIO_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_SDIO_CMD) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_SDIO_CMD) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_SDIO_CMD, 12U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (input pullup). - * PF1 - PIN1 (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (input pullup). - * PG1 - PIN1 (input pullup). - * PG2 - PIN2 (input pullup). - * PG3 - PIN3 (input pullup). - * PG4 - PIN4 (input pullup). - * PG5 - PIN5 (input pullup). - * PG6 - PIN6 (input pullup). - * PG7 - PIN7 (input pullup). - * PG8 - PIN8 (input pullup). - * PG9 - PIN9 (input pullup). - * PG10 - PIN10 (input pullup). - * PG11 - PIN11 (input pullup). - * PG12 - PIN12 (input pullup). - * PG13 - PIN13 (input pullup). - * PG14 - PIN14 (input pullup). - * PG15 - PIN15 (input pullup). - */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_INPUT(GPIOG_PIN6) | \ - PIN_MODE_INPUT(GPIOG_PIN7) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_INPUT(GPIOG_PIN10) | \ - PIN_MODE_INPUT(GPIOG_PIN11) | \ - PIN_MODE_INPUT(GPIOG_PIN12) | \ - PIN_MODE_INPUT(GPIOG_PIN13) | \ - PIN_MODE_INPUT(GPIOG_PIN14) | \ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input pullup). - * PH3 - PIN3 (input pullup). - * PH4 - PIN4 (input pullup). - * PH5 - PIN5 (input pullup). - * PH6 - PIN6 (input pullup). - * PH7 - PIN7 (input pullup). - * PH8 - PIN8 (input pullup). - * PH9 - PIN9 (input pullup). - * PH10 - PIN10 (input pullup). - * PH11 - PIN11 (input pullup). - * PH12 - PIN12 (input pullup). - * PH13 - PIN13 (input pullup). - * PH14 - PIN14 (input pullup). - * PH15 - PIN15 (input pullup). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_INPUT(GPIOH_PIN7) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input pullup). - * PI1 - PIN1 (input pullup). - * PI2 - PIN2 (input pullup). - * PI3 - PIN3 (input pullup). - * PI4 - PIN4 (input pullup). - * PI5 - PIN5 (input pullup). - * PI6 - PIN6 (input pullup). - * PI7 - PIN7 (input pullup). - * PI8 - PIN8 (input pullup). - * PI9 - PIN9 (input pullup). - * PI10 - PIN10 (input pullup). - * PI11 - PIN11 (input pullup). - * PI12 - PIN12 (input pullup). - * PI13 - PIN13 (input pullup). - * PI14 - PIN14 (input pullup). - * PI15 - PIN15 (input pullup). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ - PIN_OSPEED_HIGH(GPIOI_PIN1) | \ - PIN_OSPEED_HIGH(GPIOI_PIN2) | \ - PIN_OSPEED_HIGH(GPIOI_PIN3) | \ - PIN_OSPEED_HIGH(GPIOI_PIN4) | \ - PIN_OSPEED_HIGH(GPIOI_PIN5) | \ - PIN_OSPEED_HIGH(GPIOI_PIN6) | \ - PIN_OSPEED_HIGH(GPIOI_PIN7) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_PIN9) | \ - PIN_OSPEED_HIGH(GPIOI_PIN10) | \ - PIN_OSPEED_HIGH(GPIOI_PIN11) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_PIN13) | \ - PIN_OSPEED_HIGH(GPIOI_PIN14) | \ - PIN_OSPEED_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_C3_V1/board.mk b/boards/ORESAT_C3_V1/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_C3_V1/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_C3_V1/gdboocd.cmd b/boards/ORESAT_C3_V1/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ORESAT_C3_V1/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_C3_V1/oocd.cfg b/boards/ORESAT_C3_V1/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ORESAT_C3_V1/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ORESAT_C3_V3/board.c b/boards/ORESAT_C3_V3/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/ORESAT_C3_V3/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_C3_V3/board.h b/boards/ORESAT_C3_V3/board.h deleted file mode 100644 index b107e0a8..00000000 --- a/boards/ORESAT_C3_V3/board.h +++ /dev/null @@ -1,1217 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * OreSat C3 Prototype Board - * PART: STM32F446VE - * PACKAGE: LQFP100 - */ - -/* - * Board identifier. - */ -#define ORESAT_C3_V3 -#define BOARD_NAME "OreSat C3 v3" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* #define STM32_HSE_BYPASS */ - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F446xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN1_SILENT 9U -#define GPIOA_CAN1_SHDN 10U -#define GPIOA_CAN1_RX 11U -#define GPIOA_CAN1_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_SDIO_D1 0U -#define GPIOB_SDIO_D2 1U -#define GPIOB_SDIO_CK 2U -#define GPIOB_SWO 3U -#define GPIOB_CAN2_SHDN 4U -#define GPIOB_CAN2_RX 5U -#define GPIOB_CAN2_TX 6U -#define GPIOB_CAN2_SILENT 7U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_I2C1_SDA 9U -#define GPIOB_USART3_TX 10U -#define GPIOB_PIN11 11U -#define GPIOB_LO_SEN 12U -#define GPIOB_LO_SCLK 13U -#define GPIOB_LO_SDATA 14U -#define GPIOB_LO_PLL 15U - -#define GPIOC_VERIFY_TURN 0U -#define GPIOC_VERIFY_HELI 1U -#define GPIOC_CB_IOUT 2U -#define GPIOC_OPD_ISET 3U -#define GPIOC_PA_FWD 4U -#define GPIOC_PA_REV 5U -#define GPIOC_LBAND_CS 6U -#define GPIOC_UHF_CS 7U -#define GPIOC_SDIO_D0 8U -#define GPIOC_UHF_IRQ 9U -#define GPIOC_OPD_FAULT 10U -#define GPIOC_SDIO_D3 11U -#define GPIOC_TEST_TURN 12U -#define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_FIRE_HELI_1 0U -#define GPIOD_FIRE_TURN_1 1U -#define GPIOD_SDIO_CMD 2U -#define GPIOD_TEST_HELI 3U -#define GPIOD_UHF_ENABLE 4U -#define GPIOD_OPD_ENABLE 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_LBAND_IRQ 8U -#define GPIOD_USART3_RX 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_WDT 1U -#define GPIOE_FIRE_TURN_2 2U -#define GPIOE_FIRE_HELI_2 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_MMC_PWR 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) -#define LINE_CAN1_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN1_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_CAN2_SHDN PAL_LINE(GPIOB, 4U) -#define LINE_CAN2_SILENT PAL_LINE(GPIOB, 7U) -#define LINE_LO_SEN PAL_LINE(GPIOB, 12U) -#define LINE_LO_SCLK PAL_LINE(GPIOB, 13U) -#define LINE_LO_SDATA PAL_LINE(GPIOB, 14U) -#define LINE_LO_PLL PAL_LINE(GPIOB, 15U) -#define LINE_LBAND_CS PAL_LINE(GPIOC, 6U) -#define LINE_UHF_CS PAL_LINE(GPIOC, 7U) -#define LINE_UHF_IRQ PAL_LINE(GPIOC, 9U) -#define LINE_FIRE_HELI_1 PAL_LINE(GPIOD, 0U) -#define LINE_FIRE_TURN_1 PAL_LINE(GPIOD, 1U) -#define LINE_UHF_ENABLE PAL_LINE(GPIOD, 4U) -#define LINE_OPD_ENABLE PAL_LINE(GPIOD, 5U) -#define LINE_LBAND_IRQ PAL_LINE(GPIOD, 8U) -#define LINE_WDT PAL_LINE(GPIOE, 1U) -#define LINE_FIRE_TURN_2 PAL_LINE(GPIOE, 2U) -#define LINE_FIRE_HELI_2 PAL_LINE(GPIOE, 3U) -#define LINE_MMC_PWR PAL_LINE(GPIOE, 7U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 (analog). - * PA3 - PIN3 (analog). - * PA4 - PIN4 (analog). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - SPI1_MOSI (alternate 5). - * PA8 - PIN8 (analog). - * PA9 - CAN1_SILENT (output pushpull). - * PA10 - CAN1_SHDN (output pushpull). - * PA11 - CAN1_RX (alternate 9). - * PA12 - CAN1_TX (alternate 9). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ANALOG(GPIOA_PIN2) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SILENT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN1_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN1_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN1_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_RX, 9U) | \ - PIN_AFIO_AF(GPIOA_CAN1_TX, 9U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - SDIO_D1 (alternate 12). - * PB1 - SDIO_D2 (alternate 12). - * PB2 - SDIO_CK (alternate 12). - * PB3 - SWO (alternate 0). - * PB4 - CAN2_SHDN (output pushpull). - * PB5 - CAN2_RX (alternate 9). - * PB6 - CAN2_TX (alternate 9). - * PB7 - CAN2_SILENT (output pushpull). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - USART3_TX (alternate 7). - * PB11 - PIN11 (NC) (analog). - * PB12 - LO_SEN (output pushpull). - * PB13 - LO_SCLK (output pushpull). - * PB14 - LO_SDATA (output pushpull). - * PB15 - LO_PLL (input). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_SDIO_D1) | \ - PIN_MODE_ALTERNATE(GPIOB_SDIO_D2) | \ - PIN_MODE_ALTERNATE(GPIOB_SDIO_CK) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_USART3_TX) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SEN) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SCLK) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SDATA) | \ - PIN_MODE_INPUT(GPIOB_LO_PLL)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_SDIO_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SDIO_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SDIO_CK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SILENT) |\ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_USART3_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SEN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SDATA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_PLL)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_SDIO_D1) | \ - PIN_OSPEED_HIGH(GPIOB_SDIO_D2) | \ - PIN_OSPEED_HIGH(GPIOB_SDIO_CK) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SHDN) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_TX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SILENT) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_USART3_TX) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SEN) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SCLK) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SDATA) | \ - PIN_OSPEED_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_SDIO_D1) | \ - PIN_PUPDR_FLOATING(GPIOB_SDIO_D2) | \ - PIN_PUPDR_FLOATING(GPIOB_SDIO_CK) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_RX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_TX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_USART3_TX) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SEN) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SCLK) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SDATA) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_PLL)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_SDIO_D1) | \ - PIN_ODR_HIGH(GPIOB_SDIO_D2) | \ - PIN_ODR_HIGH(GPIOB_SDIO_CK) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_LOW(GPIOB_CAN2_SHDN) | \ - PIN_ODR_HIGH(GPIOB_CAN2_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN2_TX) | \ - PIN_ODR_LOW(GPIOB_CAN2_SILENT) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_USART3_TX) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_LO_SEN) | \ - PIN_ODR_HIGH(GPIOB_LO_SCLK) | \ - PIN_ODR_HIGH(GPIOB_LO_SDATA) | \ - PIN_ODR_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_SDIO_D1, 12U) | \ - PIN_AFIO_AF(GPIOB_SDIO_D2, 12U) | \ - PIN_AFIO_AF(GPIOB_SDIO_CK, 12U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_RX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_TX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SILENT, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_USART3_TX, 7U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_LO_SEN, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SCLK, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SDATA, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_PLL, 5U)) - -/* - * GPIOC setup: - * - * PC0 - VERIFY_TURN (analog). - * PC1 - VERIFY_HELI (analog). - * PC2 - CB_IOUT (analog). - * PC3 - OPD_ISET (analog). - * PC4 - PA_FWD (analog). - * PC5 - PA_REV (analog). - * PC6 - LBAND_CS (output pushpull). - * PC7 - UHF_CS (output pushpull). - * PC8 - SDIO_D0 (alternate 12). - * PC9 - UHF_IRQ (input). - * PC10 - OPD_FAULT (input). - * PC11 - SDIO_D3 (alternate 12). - * PC12 - TEST_TURN (analog). - * PC13 - PIN13 (analog). - * PC14 - OSC32_IN (analog). - * PC15 - OSC32_OUT (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_VERIFY_TURN) | \ - PIN_MODE_ANALOG(GPIOC_VERIFY_HELI) | \ - PIN_MODE_ANALOG(GPIOC_CB_IOUT) | \ - PIN_MODE_ANALOG(GPIOC_OPD_ISET) | \ - PIN_MODE_ANALOG(GPIOC_PA_FWD) | \ - PIN_MODE_ANALOG(GPIOC_PA_REV) | \ - PIN_MODE_OUTPUT(GPIOC_LBAND_CS) | \ - PIN_MODE_OUTPUT(GPIOC_UHF_CS) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ - PIN_MODE_INPUT(GPIOC_UHF_IRQ) | \ - PIN_MODE_INPUT(GPIOC_OPD_FAULT) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ - PIN_MODE_ANALOG(GPIOC_TEST_TURN) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_TURN) |\ - PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_HELI) |\ - PIN_OTYPE_PUSHPULL(GPIOC_CB_IOUT) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OPD_ISET) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PA_FWD) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PA_REV) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LBAND_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOC_UHF_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_UHF_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OPD_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_TEST_TURN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_OSPEED_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_OSPEED_HIGH(GPIOC_CB_IOUT) | \ - PIN_OSPEED_HIGH(GPIOC_OPD_ISET) | \ - PIN_OSPEED_HIGH(GPIOC_PA_FWD) | \ - PIN_OSPEED_HIGH(GPIOC_PA_REV) | \ - PIN_OSPEED_HIGH(GPIOC_LBAND_CS) | \ - PIN_OSPEED_HIGH(GPIOC_UHF_CS) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D0) | \ - PIN_OSPEED_HIGH(GPIOC_UHF_IRQ) | \ - PIN_OSPEED_HIGH(GPIOC_OPD_FAULT) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D3) | \ - PIN_OSPEED_HIGH(GPIOC_TEST_TURN) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_VERIFY_TURN) |\ - PIN_PUPDR_FLOATING(GPIOC_VERIFY_HELI) |\ - PIN_PUPDR_FLOATING(GPIOC_CB_IOUT) | \ - PIN_PUPDR_FLOATING(GPIOC_OPD_ISET) | \ - PIN_PUPDR_FLOATING(GPIOC_PA_FWD) | \ - PIN_PUPDR_FLOATING(GPIOC_PA_REV) | \ - PIN_PUPDR_FLOATING(GPIOC_LBAND_CS) | \ - PIN_PUPDR_FLOATING(GPIOC_UHF_CS) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_UHF_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOC_OPD_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D3) | \ - PIN_PUPDR_FLOATING(GPIOC_TEST_TURN) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_ODR_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_ODR_HIGH(GPIOC_CB_IOUT) | \ - PIN_ODR_HIGH(GPIOC_OPD_ISET) | \ - PIN_ODR_HIGH(GPIOC_PA_FWD) | \ - PIN_ODR_HIGH(GPIOC_PA_REV) | \ - PIN_ODR_HIGH(GPIOC_LBAND_CS) | \ - PIN_ODR_HIGH(GPIOC_UHF_CS) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D0) | \ - PIN_ODR_HIGH(GPIOC_UHF_IRQ) | \ - PIN_ODR_HIGH(GPIOC_OPD_FAULT) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D3) | \ - PIN_ODR_HIGH(GPIOC_TEST_TURN) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_VERIFY_TURN, 0U) | \ - PIN_AFIO_AF(GPIOC_VERIFY_HELI, 0U) | \ - PIN_AFIO_AF(GPIOC_CB_IOUT, 0U) | \ - PIN_AFIO_AF(GPIOC_OPD_ISET, 0U) | \ - PIN_AFIO_AF(GPIOC_PA_FWD, 0U) | \ - PIN_AFIO_AF(GPIOC_PA_REV, 0U) | \ - PIN_AFIO_AF(GPIOC_LBAND_CS, 0U) | \ - PIN_AFIO_AF(GPIOC_UHF_CS, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12U) | \ - PIN_AFIO_AF(GPIOC_UHF_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOC_OPD_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D3, 12U) | \ - PIN_AFIO_AF(GPIOC_TEST_TURN, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - FIRE_HELI_1 (output pushpull). - * PD1 - FIRE_TURN_1 (output pushpull). - * PD2 - SDIO_CMD (alternate 12). - * PD3 - TEST_HELI (analog). - * PD4 - UHF_ENABLE (output pushpull). - * PD5 - OPD_ENABLE (output pushpull). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - LBAND_IRQ (input). - * PD9 - USART3_RX (alternate 7). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_OUTPUT(GPIOD_FIRE_HELI_1) | \ - PIN_MODE_OUTPUT(GPIOD_FIRE_TURN_1) | \ - PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ - PIN_MODE_ANALOG(GPIOD_TEST_HELI) | \ - PIN_MODE_OUTPUT(GPIOD_UHF_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOD_OPD_ENABLE) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_LBAND_IRQ) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FIRE_HELI_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_FIRE_TURN_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_TEST_HELI) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_OPD_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LBAND_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FIRE_HELI_1) | \ - PIN_OSPEED_HIGH(GPIOD_FIRE_TURN_1) | \ - PIN_OSPEED_HIGH(GPIOD_SDIO_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_TEST_HELI) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FIRE_HELI_1) |\ - PIN_PUPDR_FLOATING(GPIOD_FIRE_TURN_1) |\ - PIN_PUPDR_FLOATING(GPIOD_SDIO_CMD) | \ - PIN_PUPDR_FLOATING(GPIOD_TEST_HELI) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_OPD_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_LBAND_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_FIRE_HELI_1) | \ - PIN_ODR_LOW(GPIOD_FIRE_TURN_1) | \ - PIN_ODR_HIGH(GPIOD_SDIO_CMD) | \ - PIN_ODR_HIGH(GPIOD_TEST_HELI) | \ - PIN_ODR_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_ODR_HIGH(GPIOD_USART3_RX) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FIRE_HELI_1, 0U) | \ - PIN_AFIO_AF(GPIOD_FIRE_TURN_1, 0U) | \ - PIN_AFIO_AF(GPIOD_SDIO_CMD, 12U) | \ - PIN_AFIO_AF(GPIOD_TEST_HELI, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_OPD_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_LBAND_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - WDT (output pushpull). - * PE2 - FIRE_TURN_2 (output pushpull). - * PE3 - FIRE_HELI_2 (output pushpull). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - MMC_PWR (output pushpull). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_OUTPUT(GPIOE_WDT) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_TURN_2) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_HELI_2) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_OUTPUT(GPIOE_MMC_PWR) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_WDT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_TURN_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_HELI_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MMC_PWR) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_WDT) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_TURN_2) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_HELI_2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_MMC_PWR) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_WDT) | \ - PIN_PUPDR_FLOATING(GPIOE_FIRE_TURN_2) |\ - PIN_PUPDR_FLOATING(GPIOE_FIRE_HELI_2) |\ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_MMC_PWR) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_LOW(GPIOE_WDT) | \ - PIN_ODR_LOW(GPIOE_FIRE_TURN_2) | \ - PIN_ODR_LOW(GPIOE_FIRE_HELI_2) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_MMC_PWR) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_WDT, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_TURN_2, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_HELI_2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_MMC_PWR, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_C3_V3/board.mk b/boards/ORESAT_C3_V3/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_C3_V3/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_C3_V3/gdboocd.cmd b/boards/ORESAT_C3_V3/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ORESAT_C3_V3/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_C3_V3/oocd.cfg b/boards/ORESAT_C3_V3/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ORESAT_C3_V3/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ORESAT_C3_V4/board.c b/boards/ORESAT_C3_V4/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/ORESAT_C3_V4/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_C3_V4/board.h b/boards/ORESAT_C3_V4/board.h deleted file mode 100644 index 41da5a8b..00000000 --- a/boards/ORESAT_C3_V4/board.h +++ /dev/null @@ -1,1355 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * OreSat C3 Prototype Board - * PART: STM32F439VI - * PACKAGE: LQFP100 - */ - -/* - * Board identifier. - */ -#define ORESAT_C3_V4 -#define BOARD_NAME "OreSat C3 v4" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F439xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PA_THERM 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_I2C_PWROFF 8U -#define GPIOA_CAN1_SILENT 9U -#define GPIOA_CAN1_SHDN 10U -#define GPIOA_CAN1_RX 11U -#define GPIOA_CAN1_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN3 2U -#define GPIOB_SWO 3U -#define GPIOB_CAN2_SHDN 4U -#define GPIOB_CAN2_RX 5U -#define GPIOB_CAN2_TX 6U -#define GPIOB_CAN2_SILENT 7U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_I2C1_SDA 9U -#define GPIOB_I2C2_SCL 10U -#define GPIOB_I2C2_SDA 11U -#define GPIOB_LO_SEN 12U -#define GPIOB_LO_SCLK 13U -#define GPIOB_LO_SDATA 14U -#define GPIOB_LO_PLL 15U - -#define GPIOC_VERIFY_TURN 0U -#define GPIOC_VERIFY_HELI 1U -#define GPIOC_CB_IOUT 2U -#define GPIOC_OPD_ISET 3U -#define GPIOC_PA_FWD 4U -#define GPIOC_PA_REV 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_SDIO_D0 8U -#define GPIOC_SDIO_D1 9U -#define GPIOC_SDIO_D2 10U -#define GPIOC_SDIO_D3 11U -#define GPIOC_SDIO_CK 12U -#define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_FIRE_HELI_1 0U -#define GPIOD_FIRE_TURN_1 1U -#define GPIOD_SDIO_CMD 2U -#define GPIOD_TEST_HELI 3U -#define GPIOD_UHF_ENABLE 4U -#define GPIOD_OPD_ENABLE 5U -#define GPIOD_TEST_TURN 6U -#define GPIOD_UHF_FLT 7U -#define GPIOD_USART3_TX 8U -#define GPIOD_USART3_RX 9U -#define GPIOD_UHF_IRQ 10U -#define GPIOD_UHF_CS 11U -#define GPIOD_LBAND_IRQ 12U -#define GPIOD_LBAND_CS 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_OPD_FAULT 0U -#define GPIOE_WDT 1U -#define GPIOE_FIRE_TURN_2 2U -#define GPIOE_FIRE_HELI_2 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_MMC_PWR 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_TOT_OUT 11U -#define GPIOE_PIN12 12U -#define GPIOE_LNA_ENABLE 13U -#define GPIOE_PA_ENABLE 14U -#define GPIOE_TOT_CLEAR 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) -#define LINE_I2C_PWROFF PAL_LINE(GPIOA, 8U) -#define LINE_CAN1_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN1_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_CAN2_SHDN PAL_LINE(GPIOB, 4U) -#define LINE_CAN2_SILENT PAL_LINE(GPIOB, 7U) -#define LINE_LO_SEN PAL_LINE(GPIOB, 12U) -#define LINE_LO_SCLK PAL_LINE(GPIOB, 13U) -#define LINE_LO_SDATA PAL_LINE(GPIOB, 14U) -#define LINE_LO_PLL PAL_LINE(GPIOB, 15U) -#define LINE_FIRE_HELI_1 PAL_LINE(GPIOD, 0U) -#define LINE_FIRE_TURN_1 PAL_LINE(GPIOD, 1U) -#define LINE_UHF_ENABLE PAL_LINE(GPIOD, 4U) -#define LINE_OPD_ENABLE PAL_LINE(GPIOD, 5U) -#define LINE_UHF_IRQ PAL_LINE(GPIOD, 10U) -#define LINE_UHF_CS PAL_LINE(GPIOD, 11U) -#define LINE_LBAND_IRQ PAL_LINE(GPIOD, 12U) -#define LINE_LBAND_CS PAL_LINE(GPIOD, 13U) -#define LINE_OPD_FAULT PAL_LINE(GPIOE, 0U) -#define LINE_WDT PAL_LINE(GPIOE, 1U) -#define LINE_FIRE_TURN_2 PAL_LINE(GPIOE, 2U) -#define LINE_FIRE_HELI_2 PAL_LINE(GPIOE, 3U) -#define LINE_MMC_PWR PAL_LINE(GPIOE, 7U) -#define LINE_TOT_OUT PAL_LINE(GPIOE, 11U) -#define LINE_LNA_ENABLE PAL_LINE(GPIOE, 13U) -#define LINE_PA_ENABLE PAL_LINE(GPIOE, 14U) -#define LINE_TOT_CLEAR PAL_LINE(GPIOE, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 (analog). - * PA3 - PIN3 (analog). - * PA4 - PA_THERM (analog). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - SPI1_MOSI (alternate 5). - * PA8 - I2C_PWROFF (output pushpull). - * PA9 - CAN1_SILENT (output pushpull). - * PA10 - CAN1_SHDN (output pushpull). - * PA11 - CAN1_RX (alternate 9). - * PA12 - CAN1_TX (alternate 9). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ANALOG(GPIOA_PIN2) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PA_THERM) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_OUTPUT(GPIOA_I2C_PWROFF) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PA_THERM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_I2C_PWROFF) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SILENT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PA_THERM) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_I2C_PWROFF) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PA_THERM) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOA_I2C_PWROFF) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PA_THERM) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_LOW(GPIOA_I2C_PWROFF) | \ - PIN_ODR_LOW(GPIOA_CAN1_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN1_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN1_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PA_THERM, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C_PWROFF, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_RX, 9U) | \ - PIN_AFIO_AF(GPIOA_CAN1_TX, 9U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN3 (analog). - * PB3 - SWO (alternate 0). - * PB4 - CAN2_SHDN (output pushpull). - * PB5 - CAN2_RX (alternate 9). - * PB6 - CAN2_TX (alternate 9). - * PB7 - CAN2_SILENT (output pushpull). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - I2C2_SCL (alternate 4). - * PB11 - I2C2_SDA (alternate 4). - * PB12 - LO_SEN (output pushpull). - * PB13 - LO_SCLK (output pushpull). - * PB14 - LO_SDATA (output pushpull). - * PB15 - LO_PLL (input). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SEN) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SCLK) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SDATA) | \ - PIN_MODE_INPUT(GPIOB_LO_PLL)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SILENT) |\ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SEN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SDATA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_PLL)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SHDN) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_TX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SILENT) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SEN) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SCLK) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SDATA) | \ - PIN_OSPEED_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_RX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_TX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SEN) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SCLK) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SDATA) | \ - PIN_PUPDR_PULLUP(GPIOB_LO_PLL)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_LOW(GPIOB_CAN2_SHDN) | \ - PIN_ODR_HIGH(GPIOB_CAN2_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN2_TX) | \ - PIN_ODR_LOW(GPIOB_CAN2_SILENT) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SDA) | \ - PIN_ODR_HIGH(GPIOB_LO_SEN) | \ - PIN_ODR_HIGH(GPIOB_LO_SCLK) | \ - PIN_ODR_HIGH(GPIOB_LO_SDATA) | \ - PIN_ODR_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_RX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_TX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SILENT, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_LO_SEN, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SCLK, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SDATA, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_PLL, 5U)) - -/* - * GPIOC setup: - * - * PC0 - VERIFY_TURN (analog). - * PC1 - VERIFY_HELI (analog). - * PC2 - CB_IOUT (analog). - * PC3 - OPD_ISET (analog). - * PC4 - PA_FWD (analog). - * PC5 - PA_REV (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - SDIO_D0 (alternate 12). - * PC9 - SDIO_D1 (alternate 12). - * PC10 - SDIO_D2 (alternate 12). - * PC11 - SDIO_D3 (alternate 12). - * PC12 - SDIO_CK (alternate 12). - * PC13 - PIN13 (analog). - * PC14 - OSC32_IN (analog). - * PC15 - OSC32_OUT (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_VERIFY_TURN) | \ - PIN_MODE_ANALOG(GPIOC_VERIFY_HELI) | \ - PIN_MODE_ANALOG(GPIOC_CB_IOUT) | \ - PIN_MODE_ANALOG(GPIOC_OPD_ISET) | \ - PIN_MODE_ANALOG(GPIOC_PA_FWD) | \ - PIN_MODE_ANALOG(GPIOC_PA_REV) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_TURN) |\ - PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_HELI) |\ - PIN_OTYPE_PUSHPULL(GPIOC_CB_IOUT) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OPD_ISET) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PA_FWD) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PA_REV) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_CK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_OSPEED_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_OSPEED_HIGH(GPIOC_CB_IOUT) | \ - PIN_OSPEED_HIGH(GPIOC_OPD_ISET) | \ - PIN_OSPEED_HIGH(GPIOC_PA_FWD) | \ - PIN_OSPEED_HIGH(GPIOC_PA_REV) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D0) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D1) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D2) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D3) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_CK) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_VERIFY_TURN) |\ - PIN_PUPDR_FLOATING(GPIOC_VERIFY_HELI) |\ - PIN_PUPDR_FLOATING(GPIOC_CB_IOUT) | \ - PIN_PUPDR_FLOATING(GPIOC_OPD_ISET) | \ - PIN_PUPDR_FLOATING(GPIOC_PA_FWD) | \ - PIN_PUPDR_FLOATING(GPIOC_PA_REV) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D1) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D2) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D3) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_CK) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_ODR_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_ODR_HIGH(GPIOC_CB_IOUT) | \ - PIN_ODR_HIGH(GPIOC_OPD_ISET) | \ - PIN_ODR_HIGH(GPIOC_PA_FWD) | \ - PIN_ODR_HIGH(GPIOC_PA_REV) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D0) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D1) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D2) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D3) | \ - PIN_ODR_HIGH(GPIOC_SDIO_CK) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_VERIFY_TURN, 0U) | \ - PIN_AFIO_AF(GPIOC_VERIFY_HELI, 0U) | \ - PIN_AFIO_AF(GPIOC_CB_IOUT, 0U) | \ - PIN_AFIO_AF(GPIOC_OPD_ISET, 0U) | \ - PIN_AFIO_AF(GPIOC_PA_FWD, 0U) | \ - PIN_AFIO_AF(GPIOC_PA_REV, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D1, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D2, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D3, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_CK, 12U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - FIRE_HELI_1 (output pushpull). - * PD1 - FIRE_TURN_1 (output pushpull). - * PD2 - SDIO_CMD (alternate 12). - * PD3 - TEST_HELI (analog). - * PD4 - UHF_ENABLE (output pushpull). - * PD5 - OPD_ENABLE (output pushpull). - * PD6 - TEST_TURN (analog). - * PD7 - UHF_FLT (analog). - * PD8 - USART3_TX (alternate 7). - * PD9 - USART3_RX (alternate 7). - * PD10 - UHF_IRQ (input). - * PD11 - UHF_CS (output). - * PD12 - LBAND_IRQ (input). - * PD13 - LBAND_CS (output). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_OUTPUT(GPIOD_FIRE_HELI_1) | \ - PIN_MODE_OUTPUT(GPIOD_FIRE_TURN_1) | \ - PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ - PIN_MODE_ANALOG(GPIOD_TEST_HELI) | \ - PIN_MODE_OUTPUT(GPIOD_UHF_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOD_OPD_ENABLE) | \ - PIN_MODE_ANALOG(GPIOD_TEST_TURN) | \ - PIN_MODE_ANALOG(GPIOD_UHF_FLT) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ - PIN_MODE_INPUT(GPIOD_UHF_IRQ) | \ - PIN_MODE_OUTPUT(GPIOD_UHF_CS) | \ - PIN_MODE_INPUT(GPIOD_LBAND_IRQ) | \ - PIN_MODE_OUTPUT(GPIOD_LBAND_CS) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FIRE_HELI_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_FIRE_TURN_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_TEST_HELI) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_OPD_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_TEST_TURN) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_FLT) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LBAND_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LBAND_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FIRE_HELI_1) | \ - PIN_OSPEED_HIGH(GPIOD_FIRE_TURN_1) | \ - PIN_OSPEED_HIGH(GPIOD_SDIO_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_TEST_HELI) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_TEST_TURN) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_FLT) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_IRQ) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_CS) | \ - PIN_OSPEED_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_OSPEED_HIGH(GPIOD_LBAND_CS) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FIRE_HELI_1) |\ - PIN_PUPDR_FLOATING(GPIOD_FIRE_TURN_1) |\ - PIN_PUPDR_FLOATING(GPIOD_SDIO_CMD) | \ - PIN_PUPDR_FLOATING(GPIOD_TEST_HELI) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_OPD_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_TEST_TURN) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_FLT) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_CS) | \ - PIN_PUPDR_FLOATING(GPIOD_LBAND_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOD_LBAND_CS) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_FIRE_HELI_1) | \ - PIN_ODR_LOW(GPIOD_FIRE_TURN_1) | \ - PIN_ODR_HIGH(GPIOD_SDIO_CMD) | \ - PIN_ODR_HIGH(GPIOD_TEST_HELI) | \ - PIN_ODR_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_TEST_TURN) | \ - PIN_ODR_HIGH(GPIOD_UHF_FLT) | \ - PIN_ODR_HIGH(GPIOD_USART3_TX) | \ - PIN_ODR_HIGH(GPIOD_USART3_RX) | \ - PIN_ODR_HIGH(GPIOD_UHF_IRQ) | \ - PIN_ODR_HIGH(GPIOD_UHF_CS) | \ - PIN_ODR_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_ODR_HIGH(GPIOD_LBAND_CS) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FIRE_HELI_1, 0U) | \ - PIN_AFIO_AF(GPIOD_FIRE_TURN_1, 0U) | \ - PIN_AFIO_AF(GPIOD_SDIO_CMD, 12U) | \ - PIN_AFIO_AF(GPIOD_TEST_HELI, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_OPD_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_TEST_TURN, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_FLT, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ - PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ - PIN_AFIO_AF(GPIOD_UHF_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_CS, 0U) | \ - PIN_AFIO_AF(GPIOD_LBAND_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOD_LBAND_CS, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - OPD_FAULT (input). - * PE1 - WDT (output pushpull). - * PE2 - FIRE_TURN_2 (output pushpull). - * PE3 - FIRE_HELI_2 (output pushpull). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - MMC_PWR (output pushpull). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - TOT_OUT (input). - * PE12 - PIN12 (analog). - * PE13 - LNA_ENABLE (output pushpull). - * PE14 - PA_ENABLE (output pushpull). - * PE15 - TOT_CLEAR (output pushpull). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_OPD_FAULT) | \ - PIN_MODE_OUTPUT(GPIOE_WDT) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_TURN_2) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_HELI_2) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_OUTPUT(GPIOE_MMC_PWR) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_TOT_OUT) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_OUTPUT(GPIOE_LNA_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOE_PA_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOE_TOT_CLEAR)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_OPD_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_WDT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_TURN_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_HELI_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MMC_PWR) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_TOT_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LNA_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PA_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOE_TOT_CLEAR)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_OPD_FAULT) | \ - PIN_OSPEED_HIGH(GPIOE_WDT) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_TURN_2) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_HELI_2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_MMC_PWR) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_TOT_OUT) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_LNA_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOE_PA_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOE_TOT_CLEAR)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_OPD_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOE_WDT) | \ - PIN_PUPDR_FLOATING(GPIOE_FIRE_TURN_2) |\ - PIN_PUPDR_FLOATING(GPIOE_FIRE_HELI_2) |\ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_MMC_PWR) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_TOT_OUT) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_LNA_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOE_PA_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOE_TOT_CLEAR)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_OPD_FAULT) | \ - PIN_ODR_LOW(GPIOE_WDT) | \ - PIN_ODR_LOW(GPIOE_FIRE_TURN_2) | \ - PIN_ODR_LOW(GPIOE_FIRE_HELI_2) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_MMC_PWR) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_TOT_OUT) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_LNA_ENABLE) | \ - PIN_ODR_LOW(GPIOE_PA_ENABLE) | \ - PIN_ODR_LOW(GPIOE_TOT_CLEAR)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_OPD_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOE_WDT, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_TURN_2, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_HELI_2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_MMC_PWR, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_TOT_OUT, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_LNA_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOE_PA_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOE_TOT_CLEAR, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOI_MODER (PIN_MODE_ANALOG(GPIOI_PIN0) | \ - PIN_MODE_ANALOG(GPIOI_PIN1) | \ - PIN_MODE_ANALOG(GPIOI_PIN2) | \ - PIN_MODE_ANALOG(GPIOI_PIN3) | \ - PIN_MODE_ANALOG(GPIOI_PIN4) | \ - PIN_MODE_ANALOG(GPIOI_PIN5) | \ - PIN_MODE_ANALOG(GPIOI_PIN6) | \ - PIN_MODE_ANALOG(GPIOI_PIN7) | \ - PIN_MODE_ANALOG(GPIOI_PIN8) | \ - PIN_MODE_ANALOG(GPIOI_PIN9) | \ - PIN_MODE_ANALOG(GPIOI_PIN10) | \ - PIN_MODE_ANALOG(GPIOI_PIN11) | \ - PIN_MODE_ANALOG(GPIOI_PIN12) | \ - PIN_MODE_ANALOG(GPIOI_PIN13) | \ - PIN_MODE_ANALOG(GPIOI_PIN14) | \ - PIN_MODE_ANALOG(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ - PIN_OSPEED_HIGH(GPIOI_PIN1) | \ - PIN_OSPEED_HIGH(GPIOI_PIN2) | \ - PIN_OSPEED_HIGH(GPIOI_PIN3) | \ - PIN_OSPEED_HIGH(GPIOI_PIN4) | \ - PIN_OSPEED_HIGH(GPIOI_PIN5) | \ - PIN_OSPEED_HIGH(GPIOI_PIN6) | \ - PIN_OSPEED_HIGH(GPIOI_PIN7) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_PIN9) | \ - PIN_OSPEED_HIGH(GPIOI_PIN10) | \ - PIN_OSPEED_HIGH(GPIOI_PIN11) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_PIN13) | \ - PIN_OSPEED_HIGH(GPIOI_PIN14) | \ - PIN_OSPEED_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_C3_V4/board.mk b/boards/ORESAT_C3_V4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_C3_V4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_C3_V4/gdboocd.cmd b/boards/ORESAT_C3_V4/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ORESAT_C3_V4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_C3_V4/oocd.cfg b/boards/ORESAT_C3_V4/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ORESAT_C3_V4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ORESAT_C3_V5/board.c b/boards/ORESAT_C3_V5/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/ORESAT_C3_V5/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_C3_V5/board.h b/boards/ORESAT_C3_V5/board.h deleted file mode 100644 index c2d476e3..00000000 --- a/boards/ORESAT_C3_V5/board.h +++ /dev/null @@ -1,1355 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * OreSat C3 Prototype Board - * PART: STM32F439VI - * PACKAGE: LQFP100 - */ - -/* - * Board identifier. - */ -#define ORESAT_C3_V5 -#define BOARD_NAME "OreSat C3 v5" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F439xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PA_THERM 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_I2C_PWROFF 8U -#define GPIOA_CAN1_SILENT 9U -#define GPIOA_CAN1_SHDN 10U -#define GPIOA_CAN1_RX 11U -#define GPIOA_CAN1_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN3 2U -#define GPIOB_SWO 3U -#define GPIOB_CAN2_SHDN 4U -#define GPIOB_CAN2_RX 5U -#define GPIOB_CAN2_TX 6U -#define GPIOB_CAN2_SILENT 7U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_I2C1_SDA 9U -#define GPIOB_I2C2_SCL 10U -#define GPIOB_I2C2_SDA 11U -#define GPIOB_LO_SEN 12U -#define GPIOB_LO_SCLK 13U -#define GPIOB_LO_SDATA 14U -#define GPIOB_LO_PLL 15U - -#define GPIOC_VERIFY_TURN 0U -#define GPIOC_VERIFY_HELI 1U -#define GPIOC_CB_IOUT 2U -#define GPIOC_OPD_ISET 3U -#define GPIOC_RF_FWD 4U -#define GPIOC_RF_REV 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_SDIO_D0 8U -#define GPIOC_SDIO_D1 9U -#define GPIOC_SDIO_D2 10U -#define GPIOC_SDIO_D3 11U -#define GPIOC_SDIO_CK 12U -#define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_FIRE_HELI_1 0U -#define GPIOD_FIRE_TURN_1 1U -#define GPIOD_SDIO_CMD 2U -#define GPIOD_TEST_HELI 3U -#define GPIOD_UHF_ENABLE 4U -#define GPIOD_OPD_ENABLE 5U -#define GPIOD_TEST_TURN 6U -#define GPIOD_UHF_FLT 7U -#define GPIOD_USART3_TX 8U -#define GPIOD_USART3_RX 9U -#define GPIOD_UHF_IRQ 10U -#define GPIOD_UHF_CS 11U -#define GPIOD_LBAND_IRQ 12U -#define GPIOD_LBAND_CS 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_OPD_FAULT 0U -#define GPIOE_WDT 1U -#define GPIOE_FIRE_TURN_2 2U -#define GPIOE_FIRE_HELI_2 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_MMC_PWR 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_TOT_STATE 11U -#define GPIOE_PIN12 12U -#define GPIOE_LNA_ENABLE 13U -#define GPIOE_PA_ENABLE 14U -#define GPIOE_TOT_RESET 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) -#define LINE_I2C_PWROFF PAL_LINE(GPIOA, 8U) -#define LINE_CAN1_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN1_SHDN PAL_LINE(GPIOA, 10U) -#define LINE_CAN2_SHDN PAL_LINE(GPIOB, 4U) -#define LINE_CAN2_SILENT PAL_LINE(GPIOB, 7U) -#define LINE_LO_SEN PAL_LINE(GPIOB, 12U) -#define LINE_LO_SCLK PAL_LINE(GPIOB, 13U) -#define LINE_LO_SDATA PAL_LINE(GPIOB, 14U) -#define LINE_LO_PLL PAL_LINE(GPIOB, 15U) -#define LINE_FIRE_HELI_1 PAL_LINE(GPIOD, 0U) -#define LINE_FIRE_TURN_1 PAL_LINE(GPIOD, 1U) -#define LINE_UHF_ENABLE PAL_LINE(GPIOD, 4U) -#define LINE_OPD_ENABLE PAL_LINE(GPIOD, 5U) -#define LINE_UHF_IRQ PAL_LINE(GPIOD, 10U) -#define LINE_UHF_CS PAL_LINE(GPIOD, 11U) -#define LINE_LBAND_IRQ PAL_LINE(GPIOD, 12U) -#define LINE_LBAND_CS PAL_LINE(GPIOD, 13U) -#define LINE_OPD_FAULT PAL_LINE(GPIOE, 0U) -#define LINE_WDT PAL_LINE(GPIOE, 1U) -#define LINE_FIRE_TURN_2 PAL_LINE(GPIOE, 2U) -#define LINE_FIRE_HELI_2 PAL_LINE(GPIOE, 3U) -#define LINE_MMC_PWR PAL_LINE(GPIOE, 7U) -#define LINE_TOT_STATE PAL_LINE(GPIOE, 11U) -#define LINE_LNA_ENABLE PAL_LINE(GPIOE, 13U) -#define LINE_PA_ENABLE PAL_LINE(GPIOE, 14U) -#define LINE_TOT_RESET PAL_LINE(GPIOE, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 (analog). - * PA3 - PIN3 (analog). - * PA4 - PA_THERM (analog). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - SPI1_MOSI (alternate 5). - * PA8 - I2C_PWROFF (output pushpull). - * PA9 - CAN1_SILENT (output pushpull). - * PA10 - CAN1_SHDN (output pushpull). - * PA11 - CAN1_RX (alternate 9). - * PA12 - CAN1_TX (alternate 9). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ANALOG(GPIOA_PIN2) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PA_THERM) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_OUTPUT(GPIOA_I2C_PWROFF) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN1_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PA_THERM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_I2C_PWROFF) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SILENT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_PIN2) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PA_THERM) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_I2C_PWROFF) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PA_THERM) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOA_I2C_PWROFF) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOA_CAN1_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_CAN1_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PA_THERM) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_LOW(GPIOA_I2C_PWROFF) | \ - PIN_ODR_LOW(GPIOA_CAN1_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN1_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN1_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PA_THERM, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C_PWROFF, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_RX, 9U) | \ - PIN_AFIO_AF(GPIOA_CAN1_TX, 9U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN3 (analog). - * PB3 - SWO (alternate 0). - * PB4 - CAN2_SHDN (output pushpull). - * PB5 - CAN2_RX (alternate 9). - * PB6 - CAN2_TX (alternate 9). - * PB7 - CAN2_SILENT (output pushpull). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - I2C2_SCL (alternate 4). - * PB11 - I2C2_SDA (alternate 4). - * PB12 - LO_SEN (output pushpull). - * PB13 - LO_SCLK (output pushpull). - * PB14 - LO_SDATA (output pushpull). - * PB15 - LO_PLL (input). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) | \ - PIN_MODE_ANALOG(GPIOB_CAN2_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SEN) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SCLK) | \ - PIN_MODE_OUTPUT(GPIOB_LO_SDATA) | \ - PIN_MODE_INPUT(GPIOB_LO_PLL)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_SILENT) |\ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SEN) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_SDATA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LO_PLL)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SHDN) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_TX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_SILENT) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SEN) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SCLK) | \ - PIN_OSPEED_HIGH(GPIOB_LO_SDATA) | \ - PIN_OSPEED_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SHDN) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_RX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_TX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN2_SILENT) |\ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SEN) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SCLK) | \ - PIN_PUPDR_FLOATING(GPIOB_LO_SDATA) | \ - PIN_PUPDR_PULLUP(GPIOB_LO_PLL)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_LOW(GPIOB_CAN2_SHDN) | \ - PIN_ODR_HIGH(GPIOB_CAN2_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN2_TX) | \ - PIN_ODR_LOW(GPIOB_CAN2_SILENT) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SDA) | \ - PIN_ODR_HIGH(GPIOB_LO_SEN) | \ - PIN_ODR_HIGH(GPIOB_LO_SCLK) | \ - PIN_ODR_HIGH(GPIOB_LO_SDATA) | \ - PIN_ODR_HIGH(GPIOB_LO_PLL)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_RX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_TX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_SILENT, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_LO_SEN, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SCLK, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_SDATA, 5U) | \ - PIN_AFIO_AF(GPIOB_LO_PLL, 5U)) - -/* - * GPIOC setup: - * - * PC0 - VERIFY_TURN (analog). - * PC1 - VERIFY_HELI (analog). - * PC2 - CB_IOUT (analog). - * PC3 - OPD_ISET (analog). - * PC4 - RF_FWD (analog). - * PC5 - RF_REV (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - SDIO_D0 (alternate 12). - * PC9 - SDIO_D1 (alternate 12). - * PC10 - SDIO_D2 (alternate 12). - * PC11 - SDIO_D3 (alternate 12). - * PC12 - SDIO_CK (alternate 12). - * PC13 - PIN13 (analog). - * PC14 - OSC32_IN (analog). - * PC15 - OSC32_OUT (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_VERIFY_TURN) | \ - PIN_MODE_ANALOG(GPIOC_VERIFY_HELI) | \ - PIN_MODE_ANALOG(GPIOC_CB_IOUT) | \ - PIN_MODE_ANALOG(GPIOC_OPD_ISET) | \ - PIN_MODE_ANALOG(GPIOC_RF_FWD) | \ - PIN_MODE_ANALOG(GPIOC_RF_REV) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_TURN) |\ - PIN_OTYPE_PUSHPULL(GPIOC_VERIFY_HELI) |\ - PIN_OTYPE_PUSHPULL(GPIOC_CB_IOUT) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OPD_ISET) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RF_FWD) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RF_REV) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_CK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_OSPEED_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_OSPEED_HIGH(GPIOC_CB_IOUT) | \ - PIN_OSPEED_HIGH(GPIOC_OPD_ISET) | \ - PIN_OSPEED_HIGH(GPIOC_RF_FWD) | \ - PIN_OSPEED_HIGH(GPIOC_RF_REV) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D0) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D1) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D2) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D3) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_CK) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_VERIFY_TURN) |\ - PIN_PUPDR_FLOATING(GPIOC_VERIFY_HELI) |\ - PIN_PUPDR_FLOATING(GPIOC_CB_IOUT) | \ - PIN_PUPDR_FLOATING(GPIOC_OPD_ISET) | \ - PIN_PUPDR_FLOATING(GPIOC_RF_FWD) | \ - PIN_PUPDR_FLOATING(GPIOC_RF_REV) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D1) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D2) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_D3) | \ - PIN_PUPDR_FLOATING(GPIOC_SDIO_CK) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_VERIFY_TURN) | \ - PIN_ODR_HIGH(GPIOC_VERIFY_HELI) | \ - PIN_ODR_HIGH(GPIOC_CB_IOUT) | \ - PIN_ODR_HIGH(GPIOC_OPD_ISET) | \ - PIN_ODR_HIGH(GPIOC_RF_FWD) | \ - PIN_ODR_HIGH(GPIOC_RF_REV) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D0) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D1) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D2) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D3) | \ - PIN_ODR_HIGH(GPIOC_SDIO_CK) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_VERIFY_TURN, 0U) | \ - PIN_AFIO_AF(GPIOC_VERIFY_HELI, 0U) | \ - PIN_AFIO_AF(GPIOC_CB_IOUT, 0U) | \ - PIN_AFIO_AF(GPIOC_OPD_ISET, 0U) | \ - PIN_AFIO_AF(GPIOC_RF_FWD, 0U) | \ - PIN_AFIO_AF(GPIOC_RF_REV, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D1, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D2, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D3, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_CK, 12U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - FIRE_HELI_1 (output pushpull). - * PD1 - FIRE_TURN_1 (output pushpull). - * PD2 - SDIO_CMD (alternate 12). - * PD3 - TEST_HELI (analog). - * PD4 - UHF_ENABLE (output pushpull). - * PD5 - OPD_ENABLE (output pushpull). - * PD6 - TEST_TURN (analog). - * PD7 - UHF_FLT (analog). - * PD8 - USART3_TX (alternate 7). - * PD9 - USART3_RX (alternate 7). - * PD10 - UHF_IRQ (input). - * PD11 - UHF_CS (output). - * PD12 - LBAND_IRQ (input). - * PD13 - LBAND_CS (output). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_OUTPUT(GPIOD_FIRE_HELI_1) | \ - PIN_MODE_OUTPUT(GPIOD_FIRE_TURN_1) | \ - PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ - PIN_MODE_ANALOG(GPIOD_TEST_HELI) | \ - PIN_MODE_OUTPUT(GPIOD_UHF_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOD_OPD_ENABLE) | \ - PIN_MODE_ANALOG(GPIOD_TEST_TURN) | \ - PIN_MODE_ANALOG(GPIOD_UHF_FLT) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ - PIN_MODE_INPUT(GPIOD_UHF_IRQ) | \ - PIN_MODE_OUTPUT(GPIOD_UHF_CS) | \ - PIN_MODE_INPUT(GPIOD_LBAND_IRQ) | \ - PIN_MODE_OUTPUT(GPIOD_LBAND_CS) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FIRE_HELI_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_FIRE_TURN_1) |\ - PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_TEST_HELI) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_OPD_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_TEST_TURN) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_FLT) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOD_UHF_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LBAND_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LBAND_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FIRE_HELI_1) | \ - PIN_OSPEED_HIGH(GPIOD_FIRE_TURN_1) | \ - PIN_OSPEED_HIGH(GPIOD_SDIO_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_TEST_HELI) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOD_TEST_TURN) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_FLT) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_IRQ) | \ - PIN_OSPEED_HIGH(GPIOD_UHF_CS) | \ - PIN_OSPEED_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_OSPEED_HIGH(GPIOD_LBAND_CS) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FIRE_HELI_1) |\ - PIN_PUPDR_FLOATING(GPIOD_FIRE_TURN_1) |\ - PIN_PUPDR_FLOATING(GPIOD_SDIO_CMD) | \ - PIN_PUPDR_FLOATING(GPIOD_TEST_HELI) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_OPD_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOD_TEST_TURN) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_FLT) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOD_UHF_CS) | \ - PIN_PUPDR_FLOATING(GPIOD_LBAND_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOD_LBAND_CS) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_FIRE_HELI_1) | \ - PIN_ODR_LOW(GPIOD_FIRE_TURN_1) | \ - PIN_ODR_HIGH(GPIOD_SDIO_CMD) | \ - PIN_ODR_HIGH(GPIOD_TEST_HELI) | \ - PIN_ODR_HIGH(GPIOD_UHF_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_OPD_ENABLE) | \ - PIN_ODR_HIGH(GPIOD_TEST_TURN) | \ - PIN_ODR_HIGH(GPIOD_UHF_FLT) | \ - PIN_ODR_HIGH(GPIOD_USART3_TX) | \ - PIN_ODR_HIGH(GPIOD_USART3_RX) | \ - PIN_ODR_HIGH(GPIOD_UHF_IRQ) | \ - PIN_ODR_HIGH(GPIOD_UHF_CS) | \ - PIN_ODR_HIGH(GPIOD_LBAND_IRQ) | \ - PIN_ODR_HIGH(GPIOD_LBAND_CS) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FIRE_HELI_1, 0U) | \ - PIN_AFIO_AF(GPIOD_FIRE_TURN_1, 0U) | \ - PIN_AFIO_AF(GPIOD_SDIO_CMD, 12U) | \ - PIN_AFIO_AF(GPIOD_TEST_HELI, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_OPD_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOD_TEST_TURN, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_FLT, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ - PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ - PIN_AFIO_AF(GPIOD_UHF_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOD_UHF_CS, 0U) | \ - PIN_AFIO_AF(GPIOD_LBAND_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOD_LBAND_CS, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - OPD_FAULT (input). - * PE1 - WDT (output pushpull). - * PE2 - FIRE_TURN_2 (output pushpull). - * PE3 - FIRE_HELI_2 (output pushpull). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - MMC_PWR (output pushpull). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - TOT_STATE (input). - * PE12 - PIN12 (analog). - * PE13 - LNA_ENABLE (output pushpull). - * PE14 - PA_ENABLE (output pushpull). - * PE15 - TOT_RESET (output pushpull). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_OPD_FAULT) | \ - PIN_MODE_OUTPUT(GPIOE_WDT) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_TURN_2) | \ - PIN_MODE_OUTPUT(GPIOE_FIRE_HELI_2) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_OUTPUT(GPIOE_MMC_PWR) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_TOT_STATE) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_OUTPUT(GPIOE_LNA_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOE_PA_ENABLE) | \ - PIN_MODE_OUTPUT(GPIOE_TOT_RESET)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_OPD_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_WDT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_TURN_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_FIRE_HELI_2) |\ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MMC_PWR) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_TOT_STATE) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LNA_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PA_ENABLE) | \ - PIN_OTYPE_PUSHPULL(GPIOE_TOT_RESET)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_OPD_FAULT) | \ - PIN_OSPEED_HIGH(GPIOE_WDT) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_TURN_2) | \ - PIN_OSPEED_HIGH(GPIOE_FIRE_HELI_2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_MMC_PWR) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_TOT_STATE) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_LNA_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOE_PA_ENABLE) | \ - PIN_OSPEED_HIGH(GPIOE_TOT_RESET)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_OPD_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOE_WDT) | \ - PIN_PUPDR_FLOATING(GPIOE_FIRE_TURN_2) |\ - PIN_PUPDR_FLOATING(GPIOE_FIRE_HELI_2) |\ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_MMC_PWR) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_TOT_STATE) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_LNA_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOE_PA_ENABLE) | \ - PIN_PUPDR_FLOATING(GPIOE_TOT_RESET)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_OPD_FAULT) | \ - PIN_ODR_LOW(GPIOE_WDT) | \ - PIN_ODR_LOW(GPIOE_FIRE_TURN_2) | \ - PIN_ODR_LOW(GPIOE_FIRE_HELI_2) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_MMC_PWR) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_TOT_STATE) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_LOW(GPIOE_LNA_ENABLE) | \ - PIN_ODR_HIGH(GPIOE_PA_ENABLE) | \ - PIN_ODR_LOW(GPIOE_TOT_RESET)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_OPD_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOE_WDT, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_TURN_2, 0U) | \ - PIN_AFIO_AF(GPIOE_FIRE_HELI_2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_MMC_PWR, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_TOT_STATE, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_LNA_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOE_PA_ENABLE, 0U) | \ - PIN_AFIO_AF(GPIOE_TOT_RESET, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOI_MODER (PIN_MODE_ANALOG(GPIOI_PIN0) | \ - PIN_MODE_ANALOG(GPIOI_PIN1) | \ - PIN_MODE_ANALOG(GPIOI_PIN2) | \ - PIN_MODE_ANALOG(GPIOI_PIN3) | \ - PIN_MODE_ANALOG(GPIOI_PIN4) | \ - PIN_MODE_ANALOG(GPIOI_PIN5) | \ - PIN_MODE_ANALOG(GPIOI_PIN6) | \ - PIN_MODE_ANALOG(GPIOI_PIN7) | \ - PIN_MODE_ANALOG(GPIOI_PIN8) | \ - PIN_MODE_ANALOG(GPIOI_PIN9) | \ - PIN_MODE_ANALOG(GPIOI_PIN10) | \ - PIN_MODE_ANALOG(GPIOI_PIN11) | \ - PIN_MODE_ANALOG(GPIOI_PIN12) | \ - PIN_MODE_ANALOG(GPIOI_PIN13) | \ - PIN_MODE_ANALOG(GPIOI_PIN14) | \ - PIN_MODE_ANALOG(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ - PIN_OSPEED_HIGH(GPIOI_PIN1) | \ - PIN_OSPEED_HIGH(GPIOI_PIN2) | \ - PIN_OSPEED_HIGH(GPIOI_PIN3) | \ - PIN_OSPEED_HIGH(GPIOI_PIN4) | \ - PIN_OSPEED_HIGH(GPIOI_PIN5) | \ - PIN_OSPEED_HIGH(GPIOI_PIN6) | \ - PIN_OSPEED_HIGH(GPIOI_PIN7) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_PIN9) | \ - PIN_OSPEED_HIGH(GPIOI_PIN10) | \ - PIN_OSPEED_HIGH(GPIOI_PIN11) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_PIN13) | \ - PIN_OSPEED_HIGH(GPIOI_PIN14) | \ - PIN_OSPEED_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_C3_V5/board.mk b/boards/ORESAT_C3_V5/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_C3_V5/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_C3_V5/gdboocd.cmd b/boards/ORESAT_C3_V5/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ORESAT_C3_V5/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_C3_V5/oocd.cfg b/boards/ORESAT_C3_V5/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ORESAT_C3_V5/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ORESAT_RWB_V1_1/board.c b/boards/ORESAT_RWB_V1_1/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/ORESAT_RWB_V1_1/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_RWB_V1_1/board.h b/boards/ORESAT_RWB_V1_1/board.h deleted file mode 100644 index ada36699..00000000 --- a/boards/ORESAT_RWB_V1_1/board.h +++ /dev/null @@ -1,927 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * ACS V1.1 STM32F042K6 Board Configuration - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORESAT_RWB_V1_1 -#define BOARD_NAME "Oresat RWB V1.1" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#define STM32_HSECLK 16000000U - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_CURR_FDB_MAG 0U -#define GPIOA_CURR_FDB_BLDC 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_FAULT_BLDC 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_CAN_SILENT 6U -#define GPIOA_TIM1_CH1N 7U -#define GPIOA_TIM1_CH1 8U -#define GPIOA_TIM1_CH2 9U -#define GPIOA_TIM1_CH3 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U -#define GPIOA_SPI1_NSS 15U - -#define GPIOB_TIM1_CH2N 0U -#define GPIOB_TIM1_CH3N 1U -#define GPIOB_PIN2 2U -#define GPIOB_EN_MAG 3U -#define GPIOB_SPI1_MISO 4U -#define GPIOB_PIN5 5U -#define GPIOB_EN_BLDC 6U -#define GPIOB_FAULT_MAG 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_NSS PAL_LINE(GPIOA, 15U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - CURR_FDB_MAG (analog). - * PA1 - CURR_FDB_BLDC (analog). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - FAULT_BLDC (input pullup). - * PA5 - SPI1_SCK (alternate 0). - * PA6 - CAN_SILENT (output pulldown). - * PA7 - TIM1_CH1N (alternate 2). - * PA8 - TIM1_CH1 (alternate 2). - * PA9 - TIM1_CH2 (alternate 2). - * PA10 - TIM1_CH3 (alternate 2). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - SPI1_NSS (output pushpull maximum). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_CURR_FDB_MAG) | \ - PIN_MODE_ANALOG(GPIOA_CURR_FDB_BLDC) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_FAULT_BLDC) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1N) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH2) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH3) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_OUTPUT(GPIOA_SPI1_NSS)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_CURR_FDB_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CURR_FDB_BLDC) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_FAULT_BLDC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1N) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_CURR_FDB_MAG) | \ - PIN_OSPEED_HIGH(GPIOA_CURR_FDB_BLDC) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_FAULT_BLDC) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH2) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH3) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_NSS)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_CURR_FDB_MAG) | \ - PIN_PUPDR_FLOATING(GPIOA_CURR_FDB_BLDC) |\ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_FAULT_BLDC) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1N) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH2) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH3) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_NSS)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_CURR_FDB_MAG) | \ - PIN_ODR_HIGH(GPIOA_CURR_FDB_BLDC) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_FAULT_BLDC) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH2) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH3) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_NSS)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_CURR_FDB_MAG, 0U) | \ - PIN_AFIO_AF(GPIOA_CURR_FDB_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_FAULT_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH1N, 2U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_TIM1_CH1, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH2, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH3, 2U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_NSS, 0U)) - -/* - * GPIOB setup: - * - * PB0 - TIM1_CH2N (alternate 2). - * PB1 - TIM1_CH3N (alternate 2). - * PB2 - NA (input pullup). - * PB3 - EN_MAG (output pushpull maximum). - * PB4 - SPI1_MISO (alternate 0). - * PB5 - PIN5 (input pullup). - * PB6 - EN_BLDC (output pushpull maximum) - * PB7 - FAULT_MAG (input pullup). - * PB8 - PIN8_BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_TIM1_CH2N) | \ - PIN_MODE_ALTERNATE(GPIOB_TIM1_CH3N) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_OUTPUT(GPIOB_EN_MAG) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_OUTPUT(GPIOB_EN_BLDC) | \ - PIN_MODE_INPUT(GPIOB_FAULT_MAG) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH2N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH3N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_EN_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_EN_BLDC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_FAULT_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_OSPEED_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_EN_MAG) | \ - PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_EN_BLDC) | \ - PIN_OSPEED_HIGH(GPIOB_FAULT_MAG) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_TIM1_CH2N) | \ - PIN_PUPDR_PULLUP(GPIOB_TIM1_CH3N) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_EN_MAG) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_EN_BLDC) | \ - PIN_PUPDR_PULLUP(GPIOB_FAULT_MAG) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_ODR_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_EN_MAG) | \ - PIN_ODR_HIGH(GPIOB_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_EN_BLDC) | \ - PIN_ODR_HIGH(GPIOB_FAULT_MAG) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_TIM1_CH2N, 2U) | \ - PIN_AFIO_AF(GPIOB_TIM1_CH3N, 2U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_EN_MAG, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_EN_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOB_FAULT_MAG, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_RWB_V1_1/board.mk b/boards/ORESAT_RWB_V1_1/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_RWB_V1_1/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_RWB_V1_1/gdboocd.cmd b/boards/ORESAT_RWB_V1_1/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/ORESAT_RWB_V1_1/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_RWB_V1_1/oocd.cfg b/boards/ORESAT_RWB_V1_1/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/ORESAT_RWB_V1_1/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/ORESAT_RWB_V3/board.c b/boards/ORESAT_RWB_V3/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/ORESAT_RWB_V3/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_RWB_V3/board.h b/boards/ORESAT_RWB_V3/board.h deleted file mode 100644 index a3d7c88f..00000000 --- a/boards/ORESAT_RWB_V3/board.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * ACS V3 STM32F042K6 Board Configuration - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORESAT_RWB_V3 -#define BOARD_NAME "Oresat RWB V3" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_CURR_FDB_MAG 0U -#define GPIOA_CURR_FDB_BLDC 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_FAULT_BLDC 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_PA6 6U -#define GPIOA_SPI1_NSS 6U -#define GPIOA_TIM1_CH1N 7U -#define GPIOA_TIM1_CH1 8U -#define GPIOA_TIM1_CH2 9U -#define GPIOA_TIM1_CH3 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_CAN_SILENT 15U - -#define GPIOB_TIM1_CH2N 0U -#define GPIOB_TIM1_CH3N 1U -#define GPIOB_PIN2 2U -#define GPIOB_EN_MAG 3U -#define GPIOB_SPI1_MISO 4U -#define GPIOB_PIN5 5U -#define GPIOB_EN_BLDC 6U -#define GPIOB_FAULT_MAG 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_NSS PAL_LINE(GPIOA, 6U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - CURR_FDB_MAG (analog). - * PA1 - CURR_FDB_BLDC (analog). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - FAULT_BLDC (input pullup). - * PA5 - SPI1_SCK (alternate 0). - * PA6 - SPI1_NSS (output pushpull maximum). - * PA7 - TIM1_CH1N (alternate 2). - * PA8 - TIM1_CH1 (alternate 2). - * PA9 - TIM1_CH2 (alternate 2). - * PA10 - TIM1_CH3 (alternate 2). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - CAN_SILENT (output pulldown). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_CURR_FDB_MAG) | \ - PIN_MODE_ANALOG(GPIOA_CURR_FDB_BLDC) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_FAULT_BLDC) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_OUTPUT(GPIOA_SPI1_NSS) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1N) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH2) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH3) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_CURR_FDB_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CURR_FDB_BLDC) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_FAULT_BLDC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1N) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_CURR_FDB_MAG) | \ - PIN_OSPEED_HIGH(GPIOA_CURR_FDB_BLDC) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_FAULT_BLDC) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_NSS) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH2) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH3) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_CURR_FDB_MAG) | \ - PIN_PUPDR_FLOATING(GPIOA_CURR_FDB_BLDC) |\ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_FAULT_BLDC) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_NSS) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1N) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH2) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH3) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_CURR_FDB_MAG) | \ - PIN_ODR_HIGH(GPIOA_CURR_FDB_BLDC) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_FAULT_BLDC) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH2) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH3) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_CURR_FDB_MAG, 0U) | \ - PIN_AFIO_AF(GPIOA_CURR_FDB_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_FAULT_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_NSS, 0U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH1N, 2U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_TIM1_CH1, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH2, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH3, 2U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U)) - -/* - * GPIOB setup: - * - * PB0 - TIM1_CH2N (alternate 2). - * PB1 - TIM1_CH3N (alternate 2). - * PB2 - NA (input pullup). - * PB3 - EN_MAG (output pushpull maximum). - * PB4 - SPI1_MISO (alternate 0). - * PB5 - PIN5 (input pullup). - * PB6 - EN_BLDC (output pushpull maximum) - * PB7 - FAULT_MAG (input pullup). - * PB8 - PIN8_BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_TIM1_CH2N) | \ - PIN_MODE_ALTERNATE(GPIOB_TIM1_CH3N) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_OUTPUT(GPIOB_EN_MAG) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_OUTPUT(GPIOB_EN_BLDC) | \ - PIN_MODE_INPUT(GPIOB_FAULT_MAG) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH2N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH3N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_EN_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_EN_BLDC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_FAULT_MAG) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_OSPEED_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_EN_MAG) | \ - PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_EN_BLDC) | \ - PIN_OSPEED_HIGH(GPIOB_FAULT_MAG) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_TIM1_CH2N) | \ - PIN_PUPDR_PULLUP(GPIOB_TIM1_CH3N) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_EN_MAG) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_EN_BLDC) | \ - PIN_PUPDR_PULLUP(GPIOB_FAULT_MAG) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_ODR_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_EN_MAG) | \ - PIN_ODR_HIGH(GPIOB_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_EN_BLDC) | \ - PIN_ODR_HIGH(GPIOB_FAULT_MAG) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_TIM1_CH2N, 2U) | \ - PIN_AFIO_AF(GPIOB_TIM1_CH3N, 2U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_EN_MAG, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_EN_BLDC, 0U) | \ - PIN_AFIO_AF(GPIOB_FAULT_MAG, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_RWB_V3/board.mk b/boards/ORESAT_RWB_V3/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_RWB_V3/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_RWB_V3/gdboocd.cmd b/boards/ORESAT_RWB_V3/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/ORESAT_RWB_V3/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_RWB_V3/oocd.cfg b/boards/ORESAT_RWB_V3/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/ORESAT_RWB_V3/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/ORESAT_RWB_V4/board.c b/boards/ORESAT_RWB_V4/board.c deleted file mode 100644 index 274c5b8c..00000000 --- a/boards/ORESAT_RWB_V4/board.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; - uint32_t ascr; - uint32_t lockr; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, - VAL_GPIOA_LOCKR}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, - VAL_GPIOB_LOCKR}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, - VAL_GPIOC_LOCKR}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, - VAL_GPIOD_LOCKR}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, - VAL_GPIOE_LOCKR}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, - VAL_GPIOF_LOCKR}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, - VAL_GPIOG_LOCKR}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, - VAL_GPIOH_LOCKR}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, - VAL_GPIOI_LOCKR}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, - VAL_GPIOJ_LOCKR}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, - VAL_GPIOK_LOCKR} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB2(STM32_GPIO_EN_MASK); - rccEnableAHB2(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ORESAT_RWB_V4/board.h b/boards/ORESAT_RWB_V4/board.h deleted file mode 100644 index fc1f0fb1..00000000 --- a/boards/ORESAT_RWB_V4/board.h +++ /dev/null @@ -1,1466 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * ACS V4.x STM32L452CE Board Configuration - * PART: STM32L452CEU3 - * PACKAGE: UFQFPN48 - */ - -/* - * Board identifier. - */ -#define BOARD_ORESAT_RWB_V4 -#define BOARD_NAME "OreSat RWB V4.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32L452xx - -/* - * IO pins assignments. - */ -#define GPIOA_MAG_CURR_FDB 0U -#define GPIOA_BLDC_CURR_FDB 1U -#define GPIOA_LPUART1_TX 2U -#define GPIOA_LPUART1_RX 3U -#define GPIOA_SPI1_CS 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_PIN7 7U -#define GPIOA_BLDC_INUL 8U -#define GPIOA_TIM1_CH1 8U -#define GPIOA_BLDC_INVL 9U -#define GPIOA_TIM1_CH2 9U -#define GPIOA_BLDC_INWL 10U -#define GPIOA_TIM1_CH3 10U -#define GPIOA_BLDC_FAULT 11U -#define GPIOA_BLDC_EN 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_MAG_PWM 15U - -#define GPIOB_PIN0 0U -#define GPIOB_DEBUG_2 1U -#define GPIOB_DEBUG_1 2U -#define GPIOB_MAG_DIR 3U -#define GPIOB_CAN_SILENT 4U -#define GPIOB_CAN1_RX 5U -#define GPIOB_CAN1_TX 6U -#define GPIOB_MAG_STBY 7U -#define GPIOB_MAG_FAULT 8U -#define GPIOB_MAG_EN 9U -#define GPIOB_I2C2_SCL 10U -#define GPIOB_I2C2_SDA 11U -#define GPIOB_BLDC_STBY 12U -#define GPIOB_BLDC_INUH 13U -#define GPIOB_TIM1_CH1N 13U -#define GPIOB_BLDC_INVH 14U -#define GPIOB_TIM1_CH2N 14U -#define GPIOB_BLDC_INWH 15U -#define GPIOB_TIM1_CH3N 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_BOOT0 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_SPI1_CS PAL_LINE(GPIOA, 4U) -#define LINE_BLDC_EN PAL_LINE(GPIOA, 12U) -#define LINE_DEBUG_2 PAL_LINE(GPIOB, 1U) -#define LINE_DEBUG_1 PAL_LINE(GPIOB, 2U) -#define LINE_MAG_DIR PAL_LINE(GPIOB, 3U) -#define LINE_CAN_SILENT PAL_LINE(GPIOB, 4U) -#define LINE_MAG_STBY PAL_LINE(GPIOB, 7U) -#define LINE_MAG_EN PAL_LINE(GPIOB, 9U) -#define LINE_BLDC_STBY PAL_LINE(GPIOB, 12U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) -#define PIN_ASCR_DISABLED(n) (0U << (n)) -#define PIN_ASCR_ENABLED(n) (1U << (n)) -#define PIN_LOCKR_DISABLED(n) (0U << (n)) -#define PIN_LOCKR_ENABLED(n) (1U << (n)) - -/* - * GPIOA setup: - * - * PA0 - MAG_CURR_FDB (analog). - * PA1 - BLDC_CURR_FDB (analog). - * PA2 - LPUART1_TX (alternate 8). - * PA3 - LPUART1_RX (alternate 8). - * PA4 - SPI1_CS (output pushpull maximum). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - PIN7 (analog). - * PA8 - BLDC_INUL TIM1_CH1 (alternate 1). - * PA9 - BLDC_INVL TIM1_CH2 (alternate 1). - * PA10 - BLDC_INWL TIM1_CH3 (alternate 1). - * PA11 - BLDC_FAULT (analog). - * PA12 - BLDC_EN (output pushpull maximum). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - MAG_PWM (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_MAG_CURR_FDB) | \ - PIN_MODE_ANALOG(GPIOA_BLDC_CURR_FDB) | \ - PIN_MODE_ALTERNATE(GPIOA_LPUART1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_LPUART1_RX) | \ - PIN_MODE_OUTPUT(GPIOA_SPI1_CS) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOA_BLDC_INUL) | \ - PIN_MODE_ALTERNATE(GPIOA_BLDC_INVL) | \ - PIN_MODE_ALTERNATE(GPIOA_BLDC_INWL) | \ - PIN_MODE_ANALOG(GPIOA_BLDC_FAULT) | \ - PIN_MODE_OUTPUT(GPIOA_BLDC_EN) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_MAG_PWM)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_MAG_CURR_FDB) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_CURR_FDB) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LPUART1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LPUART1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_INUL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_INVL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_INWL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_BLDC_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_MAG_PWM)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_MAG_CURR_FDB) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_CURR_FDB) | \ - PIN_OSPEED_HIGH(GPIOA_LPUART1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_LPUART1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_CS) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_INUL) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_INVL) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_INWL) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_FAULT) | \ - PIN_OSPEED_HIGH(GPIOA_BLDC_EN) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_MAG_PWM)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_MAG_CURR_FDB) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_CURR_FDB) | \ - PIN_PUPDR_FLOATING(GPIOA_LPUART1_TX) | \ - PIN_PUPDR_FLOATING(GPIOA_LPUART1_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_CS) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_INUL) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_INVL) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_INWL) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOA_BLDC_EN) | \ - PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_MAG_PWM)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_MAG_CURR_FDB) | \ - PIN_ODR_HIGH(GPIOA_BLDC_CURR_FDB) | \ - PIN_ODR_HIGH(GPIOA_LPUART1_TX) | \ - PIN_ODR_HIGH(GPIOA_LPUART1_RX) | \ - PIN_ODR_LOW(GPIOA_SPI1_CS) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_BLDC_INUL) | \ - PIN_ODR_HIGH(GPIOA_BLDC_INVL) | \ - PIN_ODR_HIGH(GPIOA_BLDC_INWL) | \ - PIN_ODR_HIGH(GPIOA_BLDC_FAULT) | \ - PIN_ODR_LOW(GPIOA_BLDC_EN) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_MAG_PWM)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_MAG_CURR_FDB, 0U) | \ - PIN_AFIO_AF(GPIOA_BLDC_CURR_FDB, 0U) | \ - PIN_AFIO_AF(GPIOA_LPUART1_TX, 8U) | \ - PIN_AFIO_AF(GPIOA_LPUART1_RX, 8U) | \ - PIN_AFIO_AF(GPIOA_SPI1_CS, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_BLDC_INUL, 1U) | \ - PIN_AFIO_AF(GPIOA_BLDC_INVL, 1U) | \ - PIN_AFIO_AF(GPIOA_BLDC_INWL, 1U) | \ - PIN_AFIO_AF(GPIOA_BLDC_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOA_BLDC_EN, 0U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_MAG_PWM, 0U)) -#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_MAG_CURR_FDB) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_CURR_FDB) | \ - PIN_ASCR_DISABLED(GPIOA_LPUART1_TX) | \ - PIN_ASCR_DISABLED(GPIOA_LPUART1_RX) | \ - PIN_ASCR_DISABLED(GPIOA_SPI1_CS) | \ - PIN_ASCR_DISABLED(GPIOA_SPI1_SCK) | \ - PIN_ASCR_DISABLED(GPIOA_SPI1_MISO) | \ - PIN_ASCR_DISABLED(GPIOA_PIN7) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_INUL) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_INVL) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_INWL) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_FAULT) | \ - PIN_ASCR_DISABLED(GPIOA_BLDC_EN) | \ - PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ - PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ - PIN_ASCR_DISABLED(GPIOA_MAG_PWM)) -#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_MAG_CURR_FDB) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_CURR_FDB) | \ - PIN_LOCKR_DISABLED(GPIOA_LPUART1_TX) | \ - PIN_LOCKR_DISABLED(GPIOA_LPUART1_RX) | \ - PIN_LOCKR_DISABLED(GPIOA_SPI1_CS) | \ - PIN_LOCKR_DISABLED(GPIOA_SPI1_SCK) | \ - PIN_LOCKR_DISABLED(GPIOA_SPI1_MISO) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_INUL) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_INVL) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_INWL) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_FAULT) | \ - PIN_LOCKR_DISABLED(GPIOA_BLDC_EN) | \ - PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ - PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ - PIN_LOCKR_DISABLED(GPIOA_MAG_PWM)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - DEBUG_2 (output pushpull maximum). - * PB2 - DEBUG_1 (output pushpull maximum). - * PB3 - MAG_DIR (output pushpull maximum). - * PB4 - CAN_SILENT (output pushpull maximum). - * PB5 - CAN1_RX (alternate 3). - * PB6 - CAN1_TX (alternate 8). - * PB7 - MAG_STBY (output pushpull maximum). - * PB8 - MAG_FAULT (analog). - * PB9 - MAG_EN (output pushpull maximum). - * PB10 - I2C2_SCL (altenrate 4). - * PB11 - I2C2_SDA (altenrate 4). - * PB12 - BLDC_STBY (output pushpull maximum). - * PB13 - BLDC_INUH TIM1_CH1N (alternate 1). - * PB14 - BLDC_INVH TIM1_CH2N (alternate 1). - * PB15 - BLDC_INWH TIM1_CH3N (alternate 1). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_OUTPUT(GPIOB_DEBUG_2) | \ - PIN_MODE_OUTPUT(GPIOB_DEBUG_1) | \ - PIN_MODE_OUTPUT(GPIOB_MAG_DIR) | \ - PIN_MODE_OUTPUT(GPIOB_CAN_SILENT) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) | \ - PIN_MODE_OUTPUT(GPIOB_MAG_STBY) | \ - PIN_MODE_ANALOG(GPIOB_MAG_FAULT) | \ - PIN_MODE_OUTPUT(GPIOB_MAG_EN) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ - PIN_MODE_OUTPUT(GPIOB_BLDC_STBY) | \ - PIN_MODE_ALTERNATE(GPIOB_BLDC_INUH) | \ - PIN_MODE_ALTERNATE(GPIOB_BLDC_INVH) | \ - PIN_MODE_ALTERNATE(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_DEBUG_2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_DEBUG_1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_DIR) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_STBY) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_FAULT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MAG_EN) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BLDC_INUH) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BLDC_STBY) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BLDC_INVH) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_DEBUG_2) | \ - PIN_OSPEED_HIGH(GPIOB_DEBUG_1) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_DIR) | \ - PIN_OSPEED_HIGH(GPIOB_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOB_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_STBY) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_FAULT) | \ - PIN_OSPEED_HIGH(GPIOB_MAG_EN) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_BLDC_STBY) | \ - PIN_OSPEED_HIGH(GPIOB_BLDC_INUH) | \ - PIN_OSPEED_HIGH(GPIOB_BLDC_INVH) | \ - PIN_OSPEED_HIGH(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_DEBUG_2) | \ - PIN_PUPDR_FLOATING(GPIOB_DEBUG_1) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_DIR) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN_SILENT) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN1_RX) | \ - PIN_PUPDR_FLOATING(GPIOB_CAN1_TX) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_STBY) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_FAULT) | \ - PIN_PUPDR_FLOATING(GPIOB_MAG_EN) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C2_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C2_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_BLDC_STBY) | \ - PIN_PUPDR_FLOATING(GPIOB_BLDC_INUH) | \ - PIN_PUPDR_FLOATING(GPIOB_BLDC_INVH) | \ - PIN_PUPDR_FLOATING(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_LOW(GPIOB_DEBUG_2) | \ - PIN_ODR_LOW(GPIOB_DEBUG_1) | \ - PIN_ODR_LOW(GPIOB_MAG_DIR) | \ - PIN_ODR_LOW(GPIOB_CAN_SILENT) | \ - PIN_ODR_HIGH(GPIOB_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN1_TX) | \ - PIN_ODR_LOW(GPIOB_MAG_STBY) | \ - PIN_ODR_HIGH(GPIOB_MAG_FAULT) | \ - PIN_ODR_LOW(GPIOB_MAG_EN) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SDA) | \ - PIN_ODR_LOW(GPIOB_BLDC_STBY) | \ - PIN_ODR_HIGH(GPIOB_BLDC_INUH) | \ - PIN_ODR_HIGH(GPIOB_BLDC_INVH) | \ - PIN_ODR_HIGH(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_DEBUG_2, 0U) | \ - PIN_AFIO_AF(GPIOB_DEBUG_2, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_DIR, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN1_RX, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN1_TX, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_STBY, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_MAG_FAULT, 0U) | \ - PIN_AFIO_AF(GPIOB_MAG_EN, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_BLDC_STBY, 0U) | \ - PIN_AFIO_AF(GPIOB_BLDC_INUH, 1U) | \ - PIN_AFIO_AF(GPIOB_BLDC_INVH, 1U) | \ - PIN_AFIO_AF(GPIOB_BLDC_INWH, 1U)) -#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \ - PIN_ASCR_DISABLED(GPIOB_DEBUG_2) | \ - PIN_ASCR_DISABLED(GPIOB_DEBUG_1) | \ - PIN_ASCR_DISABLED(GPIOB_MAG_DIR) | \ - PIN_ASCR_DISABLED(GPIOB_CAN_SILENT) | \ - PIN_ASCR_DISABLED(GPIOB_CAN1_RX) | \ - PIN_ASCR_DISABLED(GPIOB_CAN1_TX) | \ - PIN_ASCR_DISABLED(GPIOB_MAG_STBY) | \ - PIN_ASCR_DISABLED(GPIOB_MAG_FAULT) | \ - PIN_ASCR_DISABLED(GPIOB_MAG_EN) | \ - PIN_ASCR_DISABLED(GPIOB_I2C2_SCL) | \ - PIN_ASCR_DISABLED(GPIOB_I2C2_SDA) | \ - PIN_ASCR_DISABLED(GPIOB_BLDC_STBY) | \ - PIN_ASCR_DISABLED(GPIOB_BLDC_INUH) | \ - PIN_ASCR_DISABLED(GPIOB_BLDC_INVH) | \ - PIN_ASCR_DISABLED(GPIOB_BLDC_INWH)) -#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOB_DEBUG_2) | \ - PIN_LOCKR_DISABLED(GPIOB_DEBUG_1) | \ - PIN_LOCKR_DISABLED(GPIOB_MAG_DIR) | \ - PIN_LOCKR_DISABLED(GPIOB_CAN_SILENT) | \ - PIN_LOCKR_DISABLED(GPIOB_CAN1_RX) | \ - PIN_LOCKR_DISABLED(GPIOB_CAN1_TX) | \ - PIN_LOCKR_DISABLED(GPIOB_MAG_STBY) | \ - PIN_LOCKR_DISABLED(GPIOB_MAG_FAULT) | \ - PIN_LOCKR_DISABLED(GPIOB_MAG_EN) | \ - PIN_LOCKR_DISABLED(GPIOB_I2C2_SCL) | \ - PIN_LOCKR_DISABLED(GPIOB_I2C2_SDA) | \ - PIN_LOCKR_DISABLED(GPIOB_BLDC_STBY) | \ - PIN_LOCKR_DISABLED(GPIOB_BLDC_INUH) | \ - PIN_LOCKR_DISABLED(GPIOB_BLDC_INVH) | \ - PIN_LOCKR_DISABLED(GPIOB_BLDC_INWH)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) -#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \ - PIN_ASCR_DISABLED(GPIOC_PIN1) | \ - PIN_ASCR_DISABLED(GPIOC_PIN2) | \ - PIN_ASCR_DISABLED(GPIOC_PIN3) | \ - PIN_ASCR_DISABLED(GPIOC_PIN4) | \ - PIN_ASCR_DISABLED(GPIOC_PIN5) | \ - PIN_ASCR_DISABLED(GPIOC_PIN6) | \ - PIN_ASCR_DISABLED(GPIOC_PIN7) | \ - PIN_ASCR_DISABLED(GPIOC_PIN8) | \ - PIN_ASCR_DISABLED(GPIOC_PIN9) | \ - PIN_ASCR_DISABLED(GPIOC_PIN10) | \ - PIN_ASCR_DISABLED(GPIOC_PIN11) | \ - PIN_ASCR_DISABLED(GPIOC_PIN12) | \ - PIN_ASCR_DISABLED(GPIOC_PIN13) | \ - PIN_ASCR_DISABLED(GPIOC_PIN14) | \ - PIN_ASCR_DISABLED(GPIOC_PIN15)) -#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN15)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) -#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ - PIN_ASCR_DISABLED(GPIOD_PIN1) | \ - PIN_ASCR_DISABLED(GPIOD_PIN2) | \ - PIN_ASCR_DISABLED(GPIOD_PIN3) | \ - PIN_ASCR_DISABLED(GPIOD_PIN4) | \ - PIN_ASCR_DISABLED(GPIOD_PIN5) | \ - PIN_ASCR_DISABLED(GPIOD_PIN6) | \ - PIN_ASCR_DISABLED(GPIOD_PIN7) | \ - PIN_ASCR_DISABLED(GPIOD_PIN8) | \ - PIN_ASCR_DISABLED(GPIOD_PIN9) | \ - PIN_ASCR_DISABLED(GPIOD_PIN10) | \ - PIN_ASCR_DISABLED(GPIOD_PIN11) | \ - PIN_ASCR_DISABLED(GPIOD_PIN12) | \ - PIN_ASCR_DISABLED(GPIOD_PIN13) | \ - PIN_ASCR_DISABLED(GPIOD_PIN14) | \ - PIN_ASCR_DISABLED(GPIOD_PIN15)) -#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN15)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) -#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ - PIN_ASCR_DISABLED(GPIOE_PIN1) | \ - PIN_ASCR_DISABLED(GPIOE_PIN2) | \ - PIN_ASCR_DISABLED(GPIOE_PIN3) | \ - PIN_ASCR_DISABLED(GPIOE_PIN4) | \ - PIN_ASCR_DISABLED(GPIOE_PIN5) | \ - PIN_ASCR_DISABLED(GPIOE_PIN6) | \ - PIN_ASCR_DISABLED(GPIOE_PIN7) | \ - PIN_ASCR_DISABLED(GPIOE_PIN8) | \ - PIN_ASCR_DISABLED(GPIOE_PIN9) | \ - PIN_ASCR_DISABLED(GPIOE_PIN10) | \ - PIN_ASCR_DISABLED(GPIOE_PIN11) | \ - PIN_ASCR_DISABLED(GPIOE_PIN12) | \ - PIN_ASCR_DISABLED(GPIOE_PIN13) | \ - PIN_ASCR_DISABLED(GPIOE_PIN14) | \ - PIN_ASCR_DISABLED(GPIOE_PIN15)) -#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN15)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) -#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ - PIN_ASCR_DISABLED(GPIOF_PIN1) | \ - PIN_ASCR_DISABLED(GPIOF_PIN2) | \ - PIN_ASCR_DISABLED(GPIOF_PIN3) | \ - PIN_ASCR_DISABLED(GPIOF_PIN4) | \ - PIN_ASCR_DISABLED(GPIOF_PIN5) | \ - PIN_ASCR_DISABLED(GPIOF_PIN6) | \ - PIN_ASCR_DISABLED(GPIOF_PIN7) | \ - PIN_ASCR_DISABLED(GPIOF_PIN8) | \ - PIN_ASCR_DISABLED(GPIOF_PIN9) | \ - PIN_ASCR_DISABLED(GPIOF_PIN10) | \ - PIN_ASCR_DISABLED(GPIOF_PIN11) | \ - PIN_ASCR_DISABLED(GPIOF_PIN12) | \ - PIN_ASCR_DISABLED(GPIOF_PIN13) | \ - PIN_ASCR_DISABLED(GPIOF_PIN14) | \ - PIN_ASCR_DISABLED(GPIOF_PIN15)) -#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN15)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) -#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ - PIN_ASCR_DISABLED(GPIOG_PIN1) | \ - PIN_ASCR_DISABLED(GPIOG_PIN2) | \ - PIN_ASCR_DISABLED(GPIOG_PIN3) | \ - PIN_ASCR_DISABLED(GPIOG_PIN4) | \ - PIN_ASCR_DISABLED(GPIOG_PIN5) | \ - PIN_ASCR_DISABLED(GPIOG_PIN6) | \ - PIN_ASCR_DISABLED(GPIOG_PIN7) | \ - PIN_ASCR_DISABLED(GPIOG_PIN8) | \ - PIN_ASCR_DISABLED(GPIOG_PIN9) | \ - PIN_ASCR_DISABLED(GPIOG_PIN10) | \ - PIN_ASCR_DISABLED(GPIOG_PIN11) | \ - PIN_ASCR_DISABLED(GPIOG_PIN12) | \ - PIN_ASCR_DISABLED(GPIOG_PIN13) | \ - PIN_ASCR_DISABLED(GPIOG_PIN14) | \ - PIN_ASCR_DISABLED(GPIOG_PIN15)) -#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN15)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - BOOT0 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_BOOT0) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_BOOT0) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) -#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \ - PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \ - PIN_ASCR_DISABLED(GPIOH_PIN2) | \ - PIN_ASCR_DISABLED(GPIOH_BOOT0) | \ - PIN_ASCR_DISABLED(GPIOH_PIN4) | \ - PIN_ASCR_DISABLED(GPIOH_PIN5) | \ - PIN_ASCR_DISABLED(GPIOH_PIN6) | \ - PIN_ASCR_DISABLED(GPIOH_PIN7) | \ - PIN_ASCR_DISABLED(GPIOH_PIN8) | \ - PIN_ASCR_DISABLED(GPIOH_PIN9) | \ - PIN_ASCR_DISABLED(GPIOH_PIN10) | \ - PIN_ASCR_DISABLED(GPIOH_PIN11) | \ - PIN_ASCR_DISABLED(GPIOH_PIN12) | \ - PIN_ASCR_DISABLED(GPIOH_PIN13) | \ - PIN_ASCR_DISABLED(GPIOH_PIN14) | \ - PIN_ASCR_DISABLED(GPIOH_PIN15)) -#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \ - PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOH_BOOT0) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN15)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ORESAT_RWB_V4/board.mk b/boards/ORESAT_RWB_V4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ORESAT_RWB_V4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ORESAT_RWB_V4/gdboocd.cmd b/boards/ORESAT_RWB_V4/gdboocd.cmd deleted file mode 100644 index d386b739..00000000 --- a/boards/ORESAT_RWB_V4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32l4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ORESAT_RWB_V4/oocd.cfg b/boards/ORESAT_RWB_V4/oocd.cfg deleted file mode 100644 index 7f81f2b4..00000000 --- a/boards/ORESAT_RWB_V4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32l4x.cfg] - diff --git a/boards/PROTOCARD_V1_1/board.c b/boards/PROTOCARD_V1_1/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/PROTOCARD_V1_1/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/PROTOCARD_V1_1/board.h b/boards/PROTOCARD_V1_1/board.h deleted file mode 100644 index cffc2809..00000000 --- a/boards/PROTOCARD_V1_1/board.h +++ /dev/null @@ -1,934 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Protocard V1.1 Board Configuration - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_PROTOCARD_V1_1 -#define BOARD_NAME "Protocard V1.1" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#define STM32_HSECLK 16000000U - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_LED 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_USART2_TX 2U -#define GPIOA_PIN3 3U -#define GPIOA_USART2_RX 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_PIN6 6U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_PIN7 7U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_PIN7 7U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - PIN1 (input pullup). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - PIN4 (input pullup). - * PA5 - SPI1_SCK (alternate 0). - * PA6 - SPI1_MISO (alternate 0). - * PA7 - SPI1_MOSI (alternate 0). - * PA8 - PIN8 (input pullup). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_LED) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLUP(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (input pullup). - * PB1 - PIN1 (input pullup). - * PB2 - NC (input pullup). - * PB3 - PIN3 (input pullup). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8_BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_INPUT(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/PROTOCARD_V1_1/board.mk b/boards/PROTOCARD_V1_1/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/PROTOCARD_V1_1/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/PROTOCARD_V1_1/gdboocd.cmd b/boards/PROTOCARD_V1_1/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/PROTOCARD_V1_1/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/PROTOCARD_V1_1/oocd.cfg b/boards/PROTOCARD_V1_1/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/PROTOCARD_V1_1/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/PROTOCARD_V2/board.c b/boards/PROTOCARD_V2/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/PROTOCARD_V2/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/PROTOCARD_V2/board.h b/boards/PROTOCARD_V2/board.h deleted file mode 100644 index ec954e88..00000000 --- a/boards/PROTOCARD_V2/board.h +++ /dev/null @@ -1,934 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Protocard V2 Board Configuration - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_PROTOCARD_V2 -#define BOARD_NAME "Protocard V2" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#define STM32_HSECLK 16000000U - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_LED 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_USART2_TX 2U -#define GPIOA_PIN3 3U -#define GPIOA_USART2_RX 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_PIN6 6U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_PIN7 7U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_PIN7 7U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - PIN1 (input pullup). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - PIN4 (input pullup). - * PA5 - SPI1_SCK (alternate 0). - * PA6 - SPI1_MISO (alternate 0). - * PA7 - SPI1_MOSI (alternate 0). - * PA8 - PIN8 (input pullup). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_LED) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLUP(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (input pullup). - * PB1 - PIN1 (input pullup). - * PB2 - NC (input pullup). - * PB3 - PIN3 (input pullup). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8_BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_INPUT(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/PROTOCARD_V2/board.mk b/boards/PROTOCARD_V2/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/PROTOCARD_V2/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/PROTOCARD_V2/gdboocd.cmd b/boards/PROTOCARD_V2/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/PROTOCARD_V2/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/PROTOCARD_V2/oocd.cfg b/boards/PROTOCARD_V2/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/PROTOCARD_V2/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/PROTOCARD_V3/board.c b/boards/PROTOCARD_V3/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/PROTOCARD_V3/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/PROTOCARD_V3/board.h b/boards/PROTOCARD_V3/board.h deleted file mode 100644 index 107015f0..00000000 --- a/boards/PROTOCARD_V3/board.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Protocard V3 Board Configuration - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_PROTOCARD_V3 -#define BOARD_NAME "Protocard v3.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_LED 0U -#define GPIOA_PIN1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_PIN4 4U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_BOOT0 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - PIN1 (analog). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - PIN4 (analog). - * PA5 - SPI1_SCK (alternate 0). - * PA6 - SPI1_MISO (alternate 0). - * PA7 - SPI1_MOSI (alternate 0). - * PA8 - PIN8 (analog). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_LED) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - NC (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - BOOT0 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ANALOG(GPIOB_BOOT0) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_BOOT0) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/PROTOCARD_V3/board.mk b/boards/PROTOCARD_V3/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/PROTOCARD_V3/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/PROTOCARD_V3/gdboocd.cmd b/boards/PROTOCARD_V3/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/PROTOCARD_V3/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/PROTOCARD_V3/oocd.cfg b/boards/PROTOCARD_V3/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/PROTOCARD_V3/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/README.md b/boards/README.md deleted file mode 100644 index e69de29b..00000000 diff --git a/boards/SOLAR_V1/board.c b/boards/SOLAR_V1/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/SOLAR_V1/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/SOLAR_V1/board.h b/boards/SOLAR_V1/board.h deleted file mode 100644 index bd2a8603..00000000 --- a/boards/SOLAR_V1/board.h +++ /dev/null @@ -1,926 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for Oresat Solar V1 STM32F042K6 board. - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORSAT_SOLAR_V1 -#define BOARD_NAME "Oresat solar v1" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#define STM32_HSECLK 16000000U - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0_NC 0U -#define GPIOA_PIN1_NC 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_DEBUG 4U -#define GPIOA_TP9 5U -#define GPIOA_TP10 6U -#define GPIOA_TP11 7U -#define GPIOA_PIN8_NC 8U -#define GPIOA_CAN_LSTN 9U -#define GPIOA_CAN_EN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15_NC 15U - -#define GPIOB_PIN0_NC 0U -#define GPIOB_PIN1_NC 1U -#define GPIOB_PIN2_NA 2U -#define GPIOB_TP12 3U -#define GPIOB_TP13 4U -#define GPIOB_PIN5_NC 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8_BOOT0 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -//#define LINE_PIN0 PAL_LINE(GPIOA, 0U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - NC (output pulldown). - * PA1 - NC (output pulldown). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - DEBUG (output pullup). - * PA5 - TP9 (output pullup). - * PA6 - TP10 (output pullup). - * PA7 - TP11 (output pullup). - * PA8 - NC (output pulldown). - * PA9 - CAN_LSTN (output pulldown). - * PA10 - CAN_EN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - NC (output pulldown). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_PIN0_NC) | \ - PIN_MODE_OUTPUT(GPIOA_PIN1_NC) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_OUTPUT(GPIOA_DEBUG) | \ - PIN_MODE_OUTPUT(GPIOA_TP9) | \ - PIN_MODE_OUTPUT(GPIOA_TP10) | \ - PIN_MODE_OUTPUT(GPIOA_TP11) | \ - PIN_MODE_OUTPUT(GPIOA_PIN8_NC) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_LSTN) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_EN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_OUTPUT(GPIOA_PIN15_NC)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOA_PIN0_NC) | \ - PIN_OTYPE_OPENDRAIN(GPIOA_PIN1_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_DEBUG) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP11) | \ - PIN_OTYPE_OPENDRAIN(GPIOA_PIN8_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_LSTN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_OPENDRAIN(GPIOA_PIN15_NC)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0_NC) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1_NC) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_DEBUG) | \ - PIN_OSPEED_HIGH(GPIOA_TP9) | \ - PIN_OSPEED_HIGH(GPIOA_TP10) | \ - PIN_OSPEED_HIGH(GPIOA_TP11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8_NC) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_LSTN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_EN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15_NC)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_PIN0_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOA_PIN1_NC) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLDOWN(GPIOA_DEBUG) | \ - PIN_PUPDR_PULLUP(GPIOA_TP9) | \ - PIN_PUPDR_PULLUP(GPIOA_TP10) | \ - PIN_PUPDR_PULLUP(GPIOA_TP11) | \ - PIN_PUPDR_PULLDOWN(GPIOA_PIN8_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_LSTN) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_EN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLDOWN(GPIOA_PIN15_NC)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0_NC) | \ - PIN_ODR_HIGH(GPIOA_PIN1_NC) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_DEBUG) | \ - PIN_ODR_HIGH(GPIOA_TP9) | \ - PIN_ODR_HIGH(GPIOA_TP10) | \ - PIN_ODR_HIGH(GPIOA_TP11) | \ - PIN_ODR_HIGH(GPIOA_PIN8_NC) | \ - PIN_ODR_LOW(GPIOA_CAN_LSTN) | \ - PIN_ODR_LOW(GPIOA_CAN_EN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15_NC)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0_NC, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1_NC, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_DEBUG, 0U) | \ - PIN_AFIO_AF(GPIOA_TP9, 0U) | \ - PIN_AFIO_AF(GPIOA_TP10, 0U) | \ - PIN_AFIO_AF(GPIOA_TP11, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8_NC, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_LSTN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_EN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15_NC, 0U)) - -/* - * GPIOB setup: - * - * PB0 - NC (output pulldown). - * PB1 - NC (output pulldown). - * PB2 - NA (input pullup). - * PB3 - TP12 (output pullup) - * PB4 - TP13 (output pullup). - * PB5 - NC (output pulldown). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - NC BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_PIN0_NC) | \ - PIN_MODE_OUTPUT(GPIOB_PIN1_NC) | \ - PIN_MODE_INPUT(GPIOB_PIN2_NA) | \ - PIN_MODE_OUTPUT(GPIOB_TP12) | \ - PIN_MODE_OUTPUT(GPIOB_TP13) | \ - PIN_MODE_OUTPUT(GPIOB_PIN5_NC) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN8_BOOT0) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_PIN0_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2_NA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5_NC) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0_NC) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1_NC) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2_NA) | \ - PIN_OSPEED_HIGH(GPIOB_TP12) | \ - PIN_OSPEED_HIGH(GPIOB_TP13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5_NC) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(GPIOB_PIN0_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN1_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN2_NA) | \ - PIN_PUPDR_PULLUP(GPIOB_TP12) | \ - PIN_PUPDR_PULLUP(GPIOB_TP13) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN5_NC) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN8_BOOT0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0_NC) | \ - PIN_ODR_HIGH(GPIOB_PIN1_NC) | \ - PIN_ODR_HIGH(GPIOB_PIN2_NA) | \ - PIN_ODR_HIGH(GPIOB_TP12) | \ - PIN_ODR_HIGH(GPIOB_TP13) | \ - PIN_ODR_HIGH(GPIOB_PIN5_NC) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8_BOOT0) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2_NA, 0U) | \ - PIN_AFIO_AF(GPIOB_TP12, 0U) | \ - PIN_AFIO_AF(GPIOB_TP13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/SOLAR_V1/board.mk b/boards/SOLAR_V1/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/SOLAR_V1/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/SOLAR_V1/gdboocd.cmd b/boards/SOLAR_V1/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/SOLAR_V1/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/SOLAR_V1/oocd.cfg b/boards/SOLAR_V1/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/SOLAR_V1/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/SOLAR_V2/board.c b/boards/SOLAR_V2/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/SOLAR_V2/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/SOLAR_V2/board.h b/boards/SOLAR_V2/board.h deleted file mode 100644 index c1893830..00000000 --- a/boards/SOLAR_V2/board.h +++ /dev/null @@ -1,961 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for Oresat Solar V2 STM32F042K6 board. - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORSAT_SOLAR_V2 -#define BOARD_NAME "Oresat Solar v2" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#define STM32_HSECLK 16000000U - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_SHDN_STM 0U -#define GPIOA_ZSPM-NFLT 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_DEBUG 4U -#define GPIOA_TP9 5U -#define GPIOA_TP10 6U -#define GPIOA_TP11 7U -#define GPIOA_PIN8_NC 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15_NC 15U - -#define GPIOB_PIN0_NC 0U -#define GPIOB_PIN1_NC 1U -#define GPIOB_PIN2_NA 2U -#define GPIOB_TP12 3U -#define GPIOB_TP13 4U -#define GPIOB_PIN5_NC 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8_BOOT0 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 4U) -#define LINE_DEBUG PAL_LINE(GPIOA, 4U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - SHDN_STM (output floating). - * PA1 - ZSPM-NFLT (input pullup). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - DEBUG (output pulldown). - * PA5 - TP9 (output pullup). - * PA6 - TP10 (output pullup). - * PA7 - TP11 (output pullup). - * PA8 - NC (output pulldown). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - NC (output pulldown). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_SHDN_STM) | \ - PIN_MODE_INPUT(GPIOA_ZSPM-NFLT) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_OUTPUT(GPIOA_DEBUG) | \ - PIN_MODE_OUTPUT(GPIOA_TP9) | \ - PIN_MODE_OUTPUT(GPIOA_TP10) | \ - PIN_MODE_OUTPUT(GPIOA_TP11) | \ - PIN_MODE_OUTPUT(GPIOA_PIN8_NC) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_OUTPUT(GPIOA_PIN15_NC)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOA_SHDN_STM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ZSPM-NFLT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_DEBUG) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15_NC)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_SHDN_STM) | \ - PIN_OSPEED_HIGH(GPIOA_ZSPM-NFLT) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_DEBUG) | \ - PIN_OSPEED_HIGH(GPIOA_TP9) | \ - PIN_OSPEED_HIGH(GPIOA_TP10) | \ - PIN_OSPEED_HIGH(GPIOA_TP11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8_NC) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15_NC)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_SHDN_STM) | \ - PIN_PUPDR_PULLUP(GPIOA_ZSPM-NFLT) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLDOWN(GPIOA_DEBUG) | \ - PIN_PUPDR_PULLUP(GPIOA_TP9) | \ - PIN_PUPDR_PULLUP(GPIOA_TP10) | \ - PIN_PUPDR_PULLUP(GPIOA_TP11) | \ - PIN_PUPDR_PULLDOWN(GPIOA_PIN8_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLDOWN(GPIOA_PIN15_NC)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_SHDN_STM) | \ - PIN_ODR_HIGH(GPIOA_ZSPM-NFLT) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_LOW(GPIOA_DEBUG) | \ - PIN_ODR_HIGH(GPIOA_TP9) | \ - PIN_ODR_HIGH(GPIOA_TP10) | \ - PIN_ODR_HIGH(GPIOA_TP11) | \ - PIN_ODR_HIGH(GPIOA_PIN8_NC) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15_NC)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_SHDN_STM, 0U) | \ - PIN_AFIO_AF(GPIOA_ZSPM-NFLT, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_DEBUG, 0U) | \ - PIN_AFIO_AF(GPIOA_TP9, 0U) | \ - PIN_AFIO_AF(GPIOA_TP10, 0U) | \ - PIN_AFIO_AF(GPIOA_TP11, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8_NC, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15_NC, 0U)) - -/* - * GPIOB setup: - * - * PB0 - NC (output pulldown). - * PB1 - NC (output pulldown). - * PB2 - NA (input pullup). - * PB3 - TP12 (output pullup) - * PB4 - TP13 (output pullup). - * PB5 - NC (output pulldown). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - NC BOOT0 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_PIN0_NC) | \ - PIN_MODE_OUTPUT(GPIOB_PIN1_NC) | \ - PIN_MODE_INPUT(GPIOB_PIN2_NA) | \ - PIN_MODE_OUTPUT(GPIOB_TP12) | \ - PIN_MODE_OUTPUT(GPIOB_TP13) | \ - PIN_MODE_OUTPUT(GPIOB_PIN5_NC) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN8_BOOT0) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_PIN0_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1_NC) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2_NA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5_NC) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0_NC) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1_NC) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2_NA) | \ - PIN_OSPEED_HIGH(GPIOB_TP12) | \ - PIN_OSPEED_HIGH(GPIOB_TP13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5_NC) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(GPIOB_PIN0_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN1_NC) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN2_NA) | \ - PIN_PUPDR_PULLUP(GPIOB_TP12) | \ - PIN_PUPDR_PULLUP(GPIOB_TP13) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN5_NC) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLDOWN(GPIOB_PIN8_BOOT0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0_NC) | \ - PIN_ODR_HIGH(GPIOB_PIN1_NC) | \ - PIN_ODR_HIGH(GPIOB_PIN2_NA) | \ - PIN_ODR_HIGH(GPIOB_TP12) | \ - PIN_ODR_HIGH(GPIOB_TP13) | \ - PIN_ODR_HIGH(GPIOB_PIN5_NC) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8_BOOT0) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2_NA, 0U) | \ - PIN_AFIO_AF(GPIOB_TP12, 0U) | \ - PIN_AFIO_AF(GPIOB_TP13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5_NC, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (input pullup). - * PF1 - OSC_OUT (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \ - PIN_MODE_INPUT(GPIOF_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_OSC_IN) | \ - PIN_PUPDR_PULLUP(GPIOF_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/SOLAR_V2/board.mk b/boards/SOLAR_V2/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/SOLAR_V2/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/SOLAR_V2/gdboocd.cmd b/boards/SOLAR_V2/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/SOLAR_V2/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/SOLAR_V2/oocd.cfg b/boards/SOLAR_V2/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/SOLAR_V2/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/SOLAR_V3/board.c b/boards/SOLAR_V3/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/SOLAR_V3/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/SOLAR_V3/board.h b/boards/SOLAR_V3/board.h deleted file mode 100644 index bd45c36a..00000000 --- a/boards/SOLAR_V3/board.h +++ /dev/null @@ -1,962 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for Oresat Solar V3 STM32F042K6 board. - * PART: STM32F042K6T6 - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORSAT_SOLAR_V3 -#define BOARD_NAME "Oresat Solar v3.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_SHDN_STM 0U -#define GPIOA_PIN1 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_DEBUG 4U -#define GPIOA_OUTPUT_EN 5U -#define GPIOA_ALERT 6U -#define GPIOA_TP11 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_TP12 3U -#define GPIOB_TP13 4U -#define GPIOB_PIN5 5U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_BOOT0 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 4U) -#define LINE_DEBUG PAL_LINE(GPIOA, 4U) -#define LINE_OUTPUT_EN PAL_LINE(GPIOA, 5U) -#define LINE_CAN_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN_SHDN PAL_LINE(GPIOA, 10U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - SHDN_STM (analog). - * PA1 - PIN1 NOT CONNECTED (analog). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - DEBUG (output pulldown). - * PA5 - OUTPUT_EN (output pushpull). - * PA6 - ALERT (input). - * PA7 - TP11 (analog). - * PA8 - PIN8 NOT CONNECTED (analog). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 NOT CONNECTED (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_SHDN_STM) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_OUTPUT(GPIOA_DEBUG) | \ - PIN_MODE_OUTPUT(GPIOA_OUTPUT_EN) | \ - PIN_MODE_INPUT(GPIOA_ALERT) | \ - PIN_MODE_ANALOG(GPIOA_TP11) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_SHDN_STM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_DEBUG) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OUTPUT_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ALERT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_SHDN_STM) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_DEBUG) | \ - PIN_OSPEED_HIGH(GPIOA_OUTPUT_EN) | \ - PIN_OSPEED_HIGH(GPIOA_ALERT) | \ - PIN_OSPEED_HIGH(GPIOA_TP11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_SHDN_STM) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLDOWN(GPIOA_DEBUG) | \ - PIN_PUPDR_FLOATING(GPIOA_OUTPUT_EN) | \ - PIN_PUPDR_FLOATING(GPIOA_ALERT) | \ - PIN_PUPDR_FLOATING(GPIOA_TP11) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_SHDN_STM) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_LOW(GPIOA_DEBUG) | \ - PIN_ODR_LOW(GPIOA_OUTPUT_EN) | \ - PIN_ODR_HIGH(GPIOA_ALERT) | \ - PIN_ODR_HIGH(GPIOA_TP11) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_SHDN_STM, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_DEBUG, 0U) | \ - PIN_AFIO_AF(GPIOA_OUTPUT_EN, 0U) | \ - PIN_AFIO_AF(GPIOA_ALERT, 0U) | \ - PIN_AFIO_AF(GPIOA_TP11, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 NOT CONNECTED (analog). - * PB1 - PIN1 NOT CONNECTED (analog). - * PB2 - PIN2 NOT APPLICABLE (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 NOT CONNECTED (analog). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - BOOT0 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_TP12) | \ - PIN_MODE_ANALOG(GPIOB_TP13) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ANALOG(GPIOB_BOOT0) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TP13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_TP12) | \ - PIN_OSPEED_HIGH(GPIOB_TP13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_TP12) | \ - PIN_PUPDR_FLOATING(GPIOB_TP13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_TP12) | \ - PIN_ODR_HIGH(GPIOB_TP13) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_BOOT0) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_TP12, 0U) | \ - PIN_AFIO_AF(GPIOB_TP13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/SOLAR_V3/board.mk b/boards/SOLAR_V3/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/SOLAR_V3/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/SOLAR_V3/gdboocd.cmd b/boards/SOLAR_V3/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/SOLAR_V3/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/SOLAR_V3/oocd.cfg b/boards/SOLAR_V3/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/SOLAR_V3/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/SOLAR_V4/board.c b/boards/SOLAR_V4/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/SOLAR_V4/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/SOLAR_V4/board.h b/boards/SOLAR_V4/board.h deleted file mode 100644 index 714974d4..00000000 --- a/boards/SOLAR_V4/board.h +++ /dev/null @@ -1,961 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Oresat Solar V4 STM32F091CC board. - * PART: STM32F091CC - * PACKAGE: LQFP32 - */ - -/* - * Board identifier. - */ -#define BOARD_ORSAT_SOLAR_V4 -#define BOARD_NAME "Oresat Solar v4.x" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 16000000U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F091xC - -/* - * IO pins assignments. - */ -#define GPIOA_LED 0U -#define GPIOA_LT1618_EN 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_IADJ 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_PIN7 7U -#define GPIOA_PIN8 8U -#define GPIOA_CAN_SILENT 9U -#define GPIOA_CAN_SHDN 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_PIN7 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_I2C2_SCL 10U -#define GPIOB_I2C2_SDA 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_OSC_IN 0U -#define GPIOF_OSC_OUT 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_BOOT0 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_PIN1 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LED PAL_LINE(GPIOA, 0U) -#define LINE_LT1618_EN PAL_LINE(GPIOA, 1U) -#define LINE_CAN_SILENT PAL_LINE(GPIOA, 9U) -#define LINE_CAN_SHDN PAL_LINE(GPIOA, 10U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - LED (output pushpull). - * PA1 - LT1618_EN (output pushpull). - * PA2 - USART2_TX (alternate 1). - * PA3 - USART2_RX (alternate 1). - * PA4 - IADJ (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - PIN7 (analog). - * PA8 - PIN8 (analog). - * PA9 - CAN_SILENT (output pulldown). - * PA10 - CAN_SHDN (output pulldown). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_LED) | \ - PIN_MODE_OUTPUT(GPIOA_LT1618_EN) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_ANALOG(GPIOA_IADJ) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SILENT) | \ - PIN_MODE_OUTPUT(GPIOA_CAN_SHDN) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_LED) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LT1618_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_IADJ) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SILENT) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_SHDN) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_LED) | \ - PIN_OSPEED_HIGH(GPIOA_LT1618_EN) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_IADJ) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SILENT) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_SHDN) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_LED) | \ - PIN_PUPDR_PULLDOWN(GPIOA_LT1618_EN) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_USART2_RX) | \ - PIN_PUPDR_FLOATING(GPIOA_IADJ) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SILENT) | \ - PIN_PUPDR_PULLDOWN(GPIOA_CAN_SHDN) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_LED) | \ - PIN_ODR_LOW(GPIOA_LT1618_EN) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_IADJ) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_LOW(GPIOA_CAN_SILENT) | \ - PIN_ODR_LOW(GPIOA_CAN_SHDN) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LED, 0U) | \ - PIN_AFIO_AF(GPIOA_LT1618_EN, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 1U) | \ - PIN_AFIO_AF(GPIOA_IADJ, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SILENT, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_SHDN, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN2 (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - PIN6 (analog). - * PB7 - PIN7 (analog). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - I2C2_SCL (alternate 1). - * PB11 - I2C2_SDA (alternate 1). - * PB12 - PIN12 (analog). - * PB13 - PIN13 (analog). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ANALOG(GPIOB_PIN6) | \ - PIN_MODE_ANALOG(GPIOB_PIN7) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ANALOG(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_PIN6) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C2_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C2_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C2_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C2_SDA, 1U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 (analog). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_ANALOG(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - OSC_IN (analog). - * PF1 - OSC_OUT (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - BOOT0 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_BOOT0) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_BOOT0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_BOOT0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_BOOT0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \ - PIN_ODR_HIGH(GPIOF_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_BOOT0) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_BOOT0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/SOLAR_V4/board.mk b/boards/SOLAR_V4/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/SOLAR_V4/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/SOLAR_V4/gdboocd.cmd b/boards/SOLAR_V4/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/SOLAR_V4/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/SOLAR_V4/oocd.cfg b/boards/SOLAR_V4/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/SOLAR_V4/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/ST_NUCLEO144_F439ZI/board.c b/boards/ST_NUCLEO144_F439ZI/board.c deleted file mode 100644 index 47713668..00000000 --- a/boards/ST_NUCLEO144_F439ZI/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -// #if STM32_HAS_GPIOI || defined(__DOXYGEN__) -// gpio_setup_t PIData; -// #endif -// #if STM32_HAS_GPIOJ || defined(__DOXYGEN__) -// gpio_setup_t PJData; -// #endif -// #if STM32_HAS_GPIOK || defined(__DOXYGEN__) -// gpio_setup_t PKData; -// #endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -// #if STM32_HAS_GPIOI -// {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, -// VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -// #endif -// #if STM32_HAS_GPIOJ -// {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, -// VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -// #endif -// #if STM32_HAS_GPIOK -// {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, -// VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -// #endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -// #if STM32_HAS_GPIOI -// gpio_init(GPIOI, &gpio_default_config.PIData); -// #endif -// #if STM32_HAS_GPIOJ -// gpio_init(GPIOJ, &gpio_default_config.PJData); -// #endif -// #if STM32_HAS_GPIOK -// gpio_init(GPIOK, &gpio_default_config.PKData); -// #endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ST_NUCLEO144_F439ZI/board.h b/boards/ST_NUCLEO144_F439ZI/board.h deleted file mode 100644 index cb9a4818..00000000 --- a/boards/ST_NUCLEO144_F439ZI/board.h +++ /dev/null @@ -1,1201 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Board description - * PART: PART_NUM - * PACKAGE: PACKAGE - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO144_F439ZI -#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F439ZI" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000U -#endif - -#define STM32_HSE_BYPASS - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F439xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_RMII_REF_CLK 1U -#define GPIOA_RMII_MDIO 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_RMII_CRS_DV 7U -#define GPIOA_PIN8 8U -#define GPIOA_USB_VBUS 9U -#define GPIOA_USB_ID 10U -#define GPIOA_USB_DM 11U -#define GPIOA_USB_DP 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_LD1 0U -#define GPIOB_PIN1 1U -#define GPIOB_BOOT1 2U -#define GPIOB_SWO 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_LD2 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_RMII_TXD1 13U -#define GPIOB_LD3 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_RMII_MDC 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_RMII_RXD0 4U -#define GPIOC_RMII_RXD1 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_USR_BUT 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_USART3_TX 8U -#define GPIOD_USART3_RX 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_USB_GPIO_OUT 6U -#define GPIOG_USB_GPIO_IN 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_RMII_TX_EN 11U -#define GPIOG_PIN12 12U -#define GPIOG_RMII_TXD0 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_LD1 PAL_LINE(GPIOB, 0U) -#define LINE_LD2 PAL_LINE(GPIOB, 7U) -#define LINE_LED PAL_LINE(GPIOB, 14U) -#define LINE_BUTTON PAL_LINE(GPIOC, 13U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - RMII_REF_CLK (alternate 11). - * PA2 - RMII_MDIO (alternate 11). - * PA3 - PIN3 (analog). - * PA4 - PIN4 (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - RMII_CRS_DV (alternate 11). - * PA8 - PIN8 (analog). - * PA9 - USB_VBUS (analog). - * PA10 - USB_ID (alternate 10). - * PA11 - USB_DM (alternate 10). - * PA12 - USB_DP (alternate 10). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ - PIN_MODE_ANALOG(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ - PIN_OSPEED_HIGH(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ - PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ - PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ - PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) | \ - PIN_PUPDR_FLOATING(GPIOA_RMII_MDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ - PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ - PIN_ODR_HIGH(GPIOA_USB_ID) | \ - PIN_ODR_HIGH(GPIOA_USB_DM) | \ - PIN_ODR_HIGH(GPIOA_USB_DP) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ - PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ - PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ - PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ - PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - LD1 (output). - * PB1 - PIN1 (analog). - * PB2 - BOOT1 (alternate 0). - * PB3 - SWO (alternate 0). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - PIN6 (analog). - * PB7 - LD2 (output). - * PB8 - PIN8 (analog). - * PB9 - PIN9 (analog). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - RMII_TXD1 (alternate 11). - * PB14 - LD3 (output). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LD1) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOB_BOOT1) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ANALOG(GPIOB_PIN6) | \ - PIN_MODE_OUTPUT(GPIOB_LD2) | \ - PIN_MODE_ANALOG(GPIOB_PIN8) | \ - PIN_MODE_ANALOG(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \ - PIN_MODE_OUTPUT(GPIOB_LD3) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LD1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LD2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LD3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LD1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_PIN6) | \ - PIN_OSPEED_HIGH(GPIOB_LD2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \ - PIN_OSPEED_HIGH(GPIOB_LD3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LD1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_LD2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_RMII_TXD1) | \ - PIN_PUPDR_FLOATING(GPIOB_LD3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LD1) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_BOOT1) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_LOW(GPIOB_LD2) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \ - PIN_ODR_LOW(GPIOB_LD3) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LD1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_LD2, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \ - PIN_AFIO_AF(GPIOB_LD3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - RMII_MDC (alternate 11). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - RMII_RXD0 (alternate 11). - * PC5 - RMII_RXD1 (alternate 11). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - USR_BUT (input). - * PC14 - OSC32_IN (analog). - * PC15 - OSC32_OUT (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_USR_BUT) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \ - PIN_MODE_ANALOG(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_USR_BUT) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_USR_BUT) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_USR_BUT) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ - PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_LOW(GPIOC_USR_BUT) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ - PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_USR_BUT, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - USART3_TX (alternate 7). - * PD9 - USART3_RX (alternate 7). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_USART3_TX) | \ - PIN_ODR_HIGH(GPIOD_USART3_RX) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ - PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - GPIO_OUT (output). - * PG7 - GPIO_IN (input). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - RMII_TX_EN (alternate 11). - * PG12 - PIN12 (analog). - * PG13 - RMII_TXD0 (alternate 11). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_OUTPUT(GPIOG_USB_GPIO_OUT) | \ - PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ - PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_USB_GPIO_OUT) | \ - PIN_PUPDR_FLOATING(GPIOG_USB_GPIO_IN) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_LOW(GPIOG_USB_GPIO_OUT) | \ - PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ - PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (analog). - * PH1 - OSC_OUT (analog). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_OSC_IN) | \ - PIN_MODE_ANALOG(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ST_NUCLEO144_F439ZI/board.mk b/boards/ST_NUCLEO144_F439ZI/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ST_NUCLEO144_F439ZI/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ST_NUCLEO144_F439ZI/gdboocd.cmd b/boards/ST_NUCLEO144_F439ZI/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ST_NUCLEO144_F439ZI/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ST_NUCLEO144_F439ZI/oocd.cfg b/boards/ST_NUCLEO144_F439ZI/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ST_NUCLEO144_F439ZI/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ST_NUCLEO32_F042K6/board.c b/boards/ST_NUCLEO32_F042K6/board.c deleted file mode 100644 index e9075159..00000000 --- a/boards/ST_NUCLEO32_F042K6/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB(STM32_GPIO_EN_MASK); - rccEnableAHB(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ST_NUCLEO32_F042K6/board.h b/boards/ST_NUCLEO32_F042K6/board.h deleted file mode 100644 index ddffebf2..00000000 --- a/boards/ST_NUCLEO32_F042K6/board.h +++ /dev/null @@ -1,966 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for STMicroelectronics STM32 Nucleo32-F042K6 board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO32_F042K6 -#define BOARD_NAME "STMicroelectronics STM32 Nucleo32-F042K6" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - * NOTE: HSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 0U -#endif - -/* - * MCU type as defined in the ST header. - */ -#define STM32F042x6 - -/* - * IO pins assignments. - */ -#define GPIOA_ARD_A0 0U -#define GPIOA_ARD_A1 1U -#define GPIOA_VCP_TX 2U -#define GPIOA_ARD_A2 3U -#define GPIOA_ARD_A3 4U -#define GPIOA_SPI1_NSS 4U -#define GPIOA_ARD_A4 5U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_ARD_A5 6U -#define GPIOA_ARD_A6 7U -#define GPIOA_TIM1_CH1N 7U -#define GPIOA_ARD_D9 8U -#define GPIOA_TIM1_CH1 8U -#define GPIOA_ARD_D1 9U -#define GPIOA_TIM1_CH2 9U -#define GPIOA_ARD_D0 10U -#define GPIOA_TIM1_CH3 10U -#define GPIOA_CAN_RX 11U -#define GPIOA_CAN_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_VCP_RX 15U - -#define GPIOB_ARD_D3 0U -#define GPIOB_TIM1_CH2N 0U -#define GPIOB_ARD_D6 1U -#define GPIOB_TIM1_CH3N 1U -#define GPIOB_PIN2 2U -#define GPIOB_ARD_D13 3U -#define GPIOB_LED 3U -#define GPIOB_ARD_D12 4U -#define GPIOB_SPI1_MISO 4U -#define GPIOB_ARD_D11 5U -#define GPIOB_SPI1_MOSI 5U -#define GPIOB_ARD_D5 6U -#define GPIOB_ARD_A5_ALT 6U -#define GPIOB_I2C1_SCL 6U -#define GPIOB_ARD_D4 7U -#define GPIOB_ARD_A4_ALT 7U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_ARD_D7 0U -#define GPIOF_ARD_D8 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) -#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) -#define LINE_VCP_TX PAL_LINE(GPIOA, 2U) -#define LINE_ARD_A2 PAL_LINE(GPIOA, 3U) -#define LINE_ARD_A3 PAL_LINE(GPIOA, 4U) -#define LINE_SPI1_NSS PAL_LINE(GPIOA, 4U) -#define LINE_ARD_A4 PAL_LINE(GPIOA, 5U) -#define LINE_ARD_A5 PAL_LINE(GPIOA, 6U) -#define LINE_ARD_A6 PAL_LINE(GPIOA, 7U) -#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U) -#define LINE_ARD_D1 PAL_LINE(GPIOA, 9U) -#define LINE_ARD_D0 PAL_LINE(GPIOA, 10U) -#define LINE_CAN_RX PAL_LINE(GPIOA, 11U) -#define LINE_CAN_TX PAL_LINE(GPIOA, 12U) -#define LINE_SWDIO PAL_LINE(GPIOA, 13U) -#define LINE_SWCLK PAL_LINE(GPIOA, 14U) -#define LINE_VCP_RX PAL_LINE(GPIOA, 15U) -#define LINE_ARD_D3 PAL_LINE(GPIOB, 0U) -#define LINE_ARD_D6 PAL_LINE(GPIOB, 1U) -#define LINE_ARD_D13 PAL_LINE(GPIOB, 3U) -#define LINE_LED PAL_LINE(GPIOB, 3U) -#define LINE_ARD_D12 PAL_LINE(GPIOB, 4U) -#define LINE_ARD_D11 PAL_LINE(GPIOB, 5U) -#define LINE_ARD_D5 PAL_LINE(GPIOB, 6U) -#define LINE_ARD_A5_ALT PAL_LINE(GPIOB, 6U) -#define LINE_ARD_D4 PAL_LINE(GPIOB, 7U) -#define LINE_ARD_A4_ALT PAL_LINE(GPIOB, 7U) -#define LINE_ARD_D7 PAL_LINE(GPIOF, 0U) -#define LINE_ARD_D8 PAL_LINE(GPIOF, 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - ARD_A0 (input pullup). - * PA1 - ARD_A1 (input pullup). - * PA2 - VCP_TX (alternate 1). - * PA3 - ARD_A2 (input pullup). - * PA4 - SPI1_NSS (output pushpull maximum). - * PA5 - SPI1_SCK (input floating). - * PA6 - ARD_A5 (input pullup). - * PA7 - TIM1_CH1N (alternate 2). - * PA8 - TIM1_CH1 (alternate 2). - * PA9 - TIM1_CH2 (alternate 2). - * PA10 - TIM1_CH3 (alternate 2). - * PA11 - CAN_RX (alternate 4). - * PA12 - CAN_TX (alternate 4). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - VCP_RX (alternate 1). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \ - PIN_MODE_INPUT(GPIOA_ARD_A1) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ - PIN_MODE_INPUT(GPIOA_ARD_A2) | \ - PIN_MODE_OUTPUT(GPIOA_SPI1_NSS) | \ - PIN_MODE_INPUT(GPIOA_SPI1_SCK) | \ - PIN_MODE_INPUT(GPIOA_ARD_A5) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH1N) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH2) | \ - PIN_MODE_ALTERNATE(GPIOA_TIM1_CH3) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_RX)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1N) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TIM1_CH3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ - PIN_OSPEED_LOW(GPIOA_VCP_TX) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_NSS) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A5) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH1) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH2) | \ - PIN_OSPEED_HIGH(GPIOA_TIM1_CH3) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_VCP_RX)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_NSS) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_A5) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1N) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH1) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH2) | \ - PIN_PUPDR_PULLUP(GPIOA_TIM1_CH3) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_RX)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ - PIN_ODR_HIGH(GPIOA_ARD_A1) | \ - PIN_ODR_HIGH(GPIOA_VCP_TX) | \ - PIN_ODR_HIGH(GPIOA_ARD_A2) | \ - PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_ARD_A5) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1N) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH1) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH2) | \ - PIN_ODR_HIGH(GPIOA_TIM1_CH3) | \ - PIN_ODR_HIGH(GPIOA_CAN_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_VCP_RX)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ - PIN_AFIO_AF(GPIOA_VCP_TX, 1U) | \ - PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_NSS, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH1N, 2U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_TIM1_CH1, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH2, 2U) | \ - PIN_AFIO_AF(GPIOA_TIM1_CH3, 2U) | \ - PIN_AFIO_AF(GPIOA_CAN_RX, 4U) | \ - PIN_AFIO_AF(GPIOA_CAN_TX, 4U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_VCP_RX, 1U)) - -/* - * GPIOB setup: - * - * PB0 - TIM1_CH2N (alternate 2). - * PB1 - TIM1_CH3N (alternate 2). - * PB2 - PIN2 (input pullup). - * PB3 - ARD_D13 LED (output pushpull maximum). - * PB4 - SPI1_MISO (alternate 0). - * PB5 - SPI1_MOSI (alternate 0). - * PB6 - I2C1_SCL (alternate 1) - * PB7 - I2C1_SDA (alternate 1). - * PB8 - PIN8 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - PIN13 (input pullup). - * PB14 - PIN14 (input pullup). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_TIM1_CH2N) | \ - PIN_MODE_ALTERNATE(GPIOB_TIM1_CH3N) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_OUTPUT(GPIOB_ARD_D13) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI1_MOSI) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH2N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_TIM1_CH3N) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MOSI) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_OSPEED_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D13) | \ - PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOB_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_TIM1_CH2N) | \ - PIN_PUPDR_PULLUP(GPIOB_TIM1_CH3N) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_ARD_D13) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_TIM1_CH2N) | \ - PIN_ODR_HIGH(GPIOB_TIM1_CH3N) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_LOW(GPIOB_ARD_D13) | \ - PIN_ODR_HIGH(GPIOB_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOB_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_TIM1_CH2N, 2U) | \ - PIN_AFIO_AF(GPIOB_TIM1_CH3N, 2U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI1_MISO, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI1_MOSI, 0U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 1U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 1U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - PIN1 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - PIN5 (input pullup). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - PIN14 (input pullup). - * PC15 - PIN15 (input pullup). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - ARD_D7 (input pullup). - * PF1 - ARD_D8 (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ARD_D7) | \ - PIN_MODE_INPUT(GPIOF_ARD_D8) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ARD_D7) | \ - PIN_OSPEED_HIGH(GPIOF_ARD_D8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ - PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ARD_D7) | \ - PIN_ODR_HIGH(GPIOF_ARD_D8) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ - PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ST_NUCLEO32_F042K6/board.mk b/boards/ST_NUCLEO32_F042K6/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ST_NUCLEO32_F042K6/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ST_NUCLEO32_F042K6/gdboocd.cmd b/boards/ST_NUCLEO32_F042K6/gdboocd.cmd deleted file mode 100644 index 2fea8ebd..00000000 --- a/boards/ST_NUCLEO32_F042K6/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f0x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ST_NUCLEO32_F042K6/oocd.cfg b/boards/ST_NUCLEO32_F042K6/oocd.cfg deleted file mode 100644 index 46967e82..00000000 --- a/boards/ST_NUCLEO32_F042K6/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f0x.cfg] - diff --git a/boards/ST_NUCLEO64_F446RE/board.c b/boards/ST_NUCLEO64_F446RE/board.c deleted file mode 100644 index 5f49a349..00000000 --- a/boards/ST_NUCLEO64_F446RE/board.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ST_NUCLEO64_F446RE/board.h b/boards/ST_NUCLEO64_F446RE/board.h deleted file mode 100644 index 6e3dfecf..00000000 --- a/boards/ST_NUCLEO64_F446RE/board.h +++ /dev/null @@ -1,1344 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for STMicroelectronics STM32 Nucleo64-F446RE board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO64_F446RE -#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-F446RE" - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000U -#endif - -#define STM32_HSE_BYPASS - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32F446xx - -/* - * IO pins assignments. - */ -#define GPIOA_AX1_IRQ 0U -#define GPIOA_AX2_IRQ 1U -#define GPIOA_USART2_TX 2U -#define GPIOA_USART2_RX 3U -#define GPIOA_ARD_A2 4U -#define GPIOA_LED 5U -#define GPIOA_SPI1_SCK 5U -#define GPIOA_SPI1_MISO 6U -#define GPIOA_SPI1_MOSI 7U -#define GPIOA_AX1_CS 8U -#define GPIOA_AX2_CS 9U -#define GPIOA_ARD_D2 10U -#define GPIOA_CAN1_RX 11U -#define GPIOA_CAN1_TX 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U - -#define GPIOB_ARD_A3 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_SWO 3U -#define GPIOB_ARD_D5 4U -#define GPIOB_CAN2_RX 5U -#define GPIOB_CAN2_TX 6U -#define GPIOB_PIN7 7U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_I2C1_SDA 9U -#define GPIOB_MMC_CS 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_SPI2_SCK 13U -#define GPIOB_SPI2_MISO 14U -#define GPIOB_SPI2_MOSI 15U - -#define GPIOC_ARD_A5 0U -#define GPIOC_ARD_A4 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U -#define GPIOC_SDIO_CD 5U -#define GPIOC_SDIO_WP 6U -#define GPIOC_ARD_D9 7U -#define GPIOC_SDIO_D0 8U -#define GPIOC_SDIO_D1 9U -#define GPIOC_SDIO_D2 10U -#define GPIOC_SDIO_D3 11U -#define GPIOC_SDIO_CK 12U -#define GPIOC_BUTTON 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_SDIO_CMD 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_AX1_IRQ PAL_LINE(GPIOA, 0U) -#define LINE_AX2_IRQ PAL_LINE(GPIOA, 1U) -#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) -#define LINE_LED PAL_LINE(GPIOA, 5U) -#define LINE_AX1_CS PAL_LINE(GPIOA, 8U) -#define LINE_AX2_CS PAL_LINE(GPIOA, 9U) -#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) -#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) -#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) -#define LINE_MMC_CS PAL_LINE(GPIOB, 10U) -#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) -#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) -#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) -#define LINE_BUTTON PAL_LINE(GPIOC, 13U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - AX1_IRQ (input pullup). - * PA1 - AX2_IRQ (input pullup). - * PA2 - USART2_TX (alternate 7). - * PA3 - USART2_RX (alternate 7). - * PA4 - ARD_A2 (input pullup). - * PA5 - SPI1_SCK (alternate 5). - * PA6 - SPI1_MISO (alternate 5). - * PA7 - SPI1_MOSI (alternate 5). - * PA8 - AX1_CS (output pushpull maximum). - * PA9 - AX2_CS (output pushpull maximum). - * PA10 - ARD_D2 (input pullup). - * PA11 - CAN1_RX (alternate 9). - * PA12 - CAN1_TX (alternate 9). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (input pullup). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_AX1_IRQ) | \ - PIN_MODE_INPUT(GPIOA_AX2_IRQ) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ - PIN_MODE_INPUT(GPIOA_ARD_A2) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_OUTPUT(GPIOA_AX1_CS) | \ - PIN_MODE_OUTPUT(GPIOA_AX2_CS) | \ - PIN_MODE_INPUT(GPIOA_ARD_D2) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_RX) | \ - PIN_MODE_ALTERNATE(GPIOA_CAN1_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_AX1_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOA_AX2_IRQ) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_AX1_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_AX2_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CAN1_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_AX1_IRQ) | \ - PIN_OSPEED_HIGH(GPIOA_AX2_IRQ) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ - PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_HIGH(GPIOA_AX1_CS) | \ - PIN_OSPEED_HIGH(GPIOA_AX2_CS) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_RX) | \ - PIN_OSPEED_HIGH(GPIOA_CAN1_TX) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_AX1_IRQ) | \ - PIN_PUPDR_PULLUP(GPIOA_AX2_IRQ) | \ - PIN_PUPDR_FLOATING(GPIOA_USART2_TX) | \ - PIN_PUPDR_FLOATING(GPIOA_USART2_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOA_AX1_CS) | \ - PIN_PUPDR_PULLUP(GPIOA_AX2_CS) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN1_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_CAN1_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_AX1_IRQ) | \ - PIN_ODR_HIGH(GPIOA_AX2_IRQ) | \ - PIN_ODR_HIGH(GPIOA_USART2_TX) | \ - PIN_ODR_HIGH(GPIOA_USART2_RX) | \ - PIN_ODR_HIGH(GPIOA_ARD_A2) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_AX1_CS) | \ - PIN_ODR_HIGH(GPIOA_AX2_CS) | \ - PIN_ODR_HIGH(GPIOA_ARD_D2) | \ - PIN_ODR_HIGH(GPIOA_CAN1_RX) | \ - PIN_ODR_HIGH(GPIOA_CAN1_TX) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_AX1_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOA_AX2_IRQ, 0U) | \ - PIN_AFIO_AF(GPIOA_USART2_TX, 7U) | \ - PIN_AFIO_AF(GPIOA_USART2_RX, 7U) | \ - PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_AX1_CS, 0U) | \ - PIN_AFIO_AF(GPIOA_AX2_CS, 0U) | \ - PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ - PIN_AFIO_AF(GPIOA_CAN1_RX, 9U) | \ - PIN_AFIO_AF(GPIOA_CAN1_TX, 9U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) - -/* - * GPIOB setup: - * - * PB0 - ARD_A3 (input pullup). - * PB1 - PIN1 (input pullup). - * PB2 - PIN2 (input pullup). - * PB3 - SWO (alternate 0). - * PB4 - ARD_D5 (input pullup). - * PB5 - CAN2_RX (alternate 9). - * PB6 - CAN2_TX (alternate 9). - * PB7 - PIN7 (input pullup). - * PB8 - I2C1_SCL (alternate 4). - * PB9 - I2C1_SDA (alternate 4). - * PB10 - MMC_CS (output pushpull maximum). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - SPI2_SCK (alternate 5). - * PB14 - SPI2_MISO (alternate 5). - * PB15 - SPI2_MOSI (alternate 5). - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_INPUT(GPIOB_ARD_D5) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) | \ - PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_OUTPUT(GPIOB_MMC_CS) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_MMC_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_RX) | \ - PIN_OSPEED_HIGH(GPIOB_CAN2_TX) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_MMC_CS) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) | \ - PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_SWO) | \ - PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \ - PIN_PUPDR_PULLUP(GPIOB_CAN2_RX) | \ - PIN_PUPDR_PULLUP(GPIOB_CAN2_TX) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_MMC_CS) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_SCK) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_HIGH(GPIOB_ARD_D5) | \ - PIN_ODR_HIGH(GPIOB_CAN2_RX) | \ - PIN_ODR_HIGH(GPIOB_CAN2_TX) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ - PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_MMC_CS) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ - PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \ - PIN_ODR_HIGH(GPIOB_SPI2_MOSI)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ - PIN_AFIO_AF(GPIOB_CAN2_RX, 9U) | \ - PIN_AFIO_AF(GPIOB_CAN2_TX, 9U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_MMC_CS, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \ - PIN_AFIO_AF(GPIOB_SPI2_MISO, 5U) | \ - PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U)) - -/* - * GPIOC setup: - * - * PC0 - ARD_A5 (input pullup). - * PC1 - ARD_A4 (input pullup). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - PIN4 (input pullup). - * PC5 - SDIO_CD (input pullup). - * PC6 - SDIO_WP (input pullup). - * PC7 - ARD_D9 (input pullup). - * PC8 - SDIO_D0 (alternate 12). - * PC9 - SDIO_D1 (alternate 12). - * PC10 - SDIO_D2 (alternate 12). - * PC11 - SDIO_D3 (alternate 12). - * PC12 - SDIO_CK (alternate 12). - * PC13 - BUTTON (input floating). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | \ - PIN_MODE_INPUT(GPIOC_ARD_A4) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_SDIO_CD) | \ - PIN_MODE_INPUT(GPIOC_SDIO_WP) | \ - PIN_MODE_INPUT(GPIOC_ARD_D9) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \ - PIN_MODE_INPUT(GPIOC_BUTTON) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_CD) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_WP) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SDIO_CK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_CD) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_WP) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D0) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D1) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D2) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_D3) | \ - PIN_OSPEED_HIGH(GPIOC_SDIO_CK) | \ - PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \ - PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_CD) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_WP) | \ - PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D0) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D1) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D2) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_D3) | \ - PIN_PUPDR_PULLUP(GPIOC_SDIO_CK) | \ - PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \ - PIN_ODR_HIGH(GPIOC_ARD_A4) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_SDIO_CD) | \ - PIN_ODR_HIGH(GPIOC_SDIO_WP) | \ - PIN_ODR_HIGH(GPIOC_ARD_D9) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D0) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D1) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D2) | \ - PIN_ODR_HIGH(GPIOC_SDIO_D3) | \ - PIN_ODR_HIGH(GPIOC_SDIO_CK) | \ - PIN_ODR_HIGH(GPIOC_BUTTON) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ - PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_SDIO_CD, 0U) | \ - PIN_AFIO_AF(GPIOC_SDIO_WP, 0U) | \ - PIN_AFIO_AF(GPIOC_ARD_D9, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D1, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D2, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_D3, 12U) | \ - PIN_AFIO_AF(GPIOC_SDIO_CK, 12U) | \ - PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - SDIO_CMD (alternate 12). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - PIN8 (input pullup). - * PD9 - PIN9 (input pullup). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_SDIO_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_SDIO_CMD) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_SDIO_CMD) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_SDIO_CMD, 12U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_INPUT(GPIOE_PIN1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (input pullup). - * PF1 - PIN1 (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (input pullup). - * PG1 - PIN1 (input pullup). - * PG2 - PIN2 (input pullup). - * PG3 - PIN3 (input pullup). - * PG4 - PIN4 (input pullup). - * PG5 - PIN5 (input pullup). - * PG6 - PIN6 (input pullup). - * PG7 - PIN7 (input pullup). - * PG8 - PIN8 (input pullup). - * PG9 - PIN9 (input pullup). - * PG10 - PIN10 (input pullup). - * PG11 - PIN11 (input pullup). - * PG12 - PIN12 (input pullup). - * PG13 - PIN13 (input pullup). - * PG14 - PIN14 (input pullup). - * PG15 - PIN15 (input pullup). - */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_INPUT(GPIOG_PIN6) | \ - PIN_MODE_INPUT(GPIOG_PIN7) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_INPUT(GPIOG_PIN10) | \ - PIN_MODE_INPUT(GPIOG_PIN11) | \ - PIN_MODE_INPUT(GPIOG_PIN12) | \ - PIN_MODE_INPUT(GPIOG_PIN13) | \ - PIN_MODE_INPUT(GPIOG_PIN14) | \ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input pullup). - * PH3 - PIN3 (input pullup). - * PH4 - PIN4 (input pullup). - * PH5 - PIN5 (input pullup). - * PH6 - PIN6 (input pullup). - * PH7 - PIN7 (input pullup). - * PH8 - PIN8 (input pullup). - * PH9 - PIN9 (input pullup). - * PH10 - PIN10 (input pullup). - * PH11 - PIN11 (input pullup). - * PH12 - PIN12 (input pullup). - * PH13 - PIN13 (input pullup). - * PH14 - PIN14 (input pullup). - * PH15 - PIN15 (input pullup). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_INPUT(GPIOH_PIN7) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input pullup). - * PI1 - PIN1 (input pullup). - * PI2 - PIN2 (input pullup). - * PI3 - PIN3 (input pullup). - * PI4 - PIN4 (input pullup). - * PI5 - PIN5 (input pullup). - * PI6 - PIN6 (input pullup). - * PI7 - PIN7 (input pullup). - * PI8 - PIN8 (input pullup). - * PI9 - PIN9 (input pullup). - * PI10 - PIN10 (input pullup). - * PI11 - PIN11 (input pullup). - * PI12 - PIN12 (input pullup). - * PI13 - PIN13 (input pullup). - * PI14 - PIN14 (input pullup). - * PI15 - PIN15 (input pullup). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ - PIN_OSPEED_HIGH(GPIOI_PIN1) | \ - PIN_OSPEED_HIGH(GPIOI_PIN2) | \ - PIN_OSPEED_HIGH(GPIOI_PIN3) | \ - PIN_OSPEED_HIGH(GPIOI_PIN4) | \ - PIN_OSPEED_HIGH(GPIOI_PIN5) | \ - PIN_OSPEED_HIGH(GPIOI_PIN6) | \ - PIN_OSPEED_HIGH(GPIOI_PIN7) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_PIN9) | \ - PIN_OSPEED_HIGH(GPIOI_PIN10) | \ - PIN_OSPEED_HIGH(GPIOI_PIN11) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_PIN13) | \ - PIN_OSPEED_HIGH(GPIOI_PIN14) | \ - PIN_OSPEED_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ST_NUCLEO64_F446RE/board.mk b/boards/ST_NUCLEO64_F446RE/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ST_NUCLEO64_F446RE/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ST_NUCLEO64_F446RE/gdboocd.cmd b/boards/ST_NUCLEO64_F446RE/gdboocd.cmd deleted file mode 100644 index ac017d4e..00000000 --- a/boards/ST_NUCLEO64_F446RE/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32f4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ST_NUCLEO64_F446RE/oocd.cfg b/boards/ST_NUCLEO64_F446RE/oocd.cfg deleted file mode 100644 index d44f8d8f..00000000 --- a/boards/ST_NUCLEO64_F446RE/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32f4x.cfg] - diff --git a/boards/ST_NUCLEO64_L452RE_P/board.c b/boards/ST_NUCLEO64_L452RE_P/board.c deleted file mode 100644 index 274c5b8c..00000000 --- a/boards/ST_NUCLEO64_L452RE_P/board.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; - uint32_t ascr; - uint32_t lockr; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, - VAL_GPIOA_LOCKR}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, - VAL_GPIOB_LOCKR}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, - VAL_GPIOC_LOCKR}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, - VAL_GPIOD_LOCKR}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, - VAL_GPIOE_LOCKR}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, - VAL_GPIOF_LOCKR}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, - VAL_GPIOG_LOCKR}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, - VAL_GPIOH_LOCKR}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, - VAL_GPIOI_LOCKR}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, - VAL_GPIOJ_LOCKR}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, - VAL_GPIOK_LOCKR} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->ASCR = config->ascr; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; - gpiop->LOCKR = config->lockr; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB2(STM32_GPIO_EN_MASK); - rccEnableAHB2(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - rccEnableCRC(true); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { - -} diff --git a/boards/ST_NUCLEO64_L452RE_P/board.h b/boards/ST_NUCLEO64_L452RE_P/board.h deleted file mode 100644 index 088bd258..00000000 --- a/boards/ST_NUCLEO64_L452RE_P/board.h +++ /dev/null @@ -1,1555 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for STMicroelectronics STM32 Nucleo64-L452RE-P board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO64_L452RE_P -#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L452RE-P" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000U -#endif - -#define STM32_HSE_BYPASS - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#define STM32L452xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_ARD_A0 0U -#define GPIOA_ADC1_IN5 0U -#define GPIOA_PIN1 1U -#define GPIOA_ARD_A1 1U -#define GPIOA_ADC1_IN6 1U -#define GPIOA_PIN2 2U -#define GPIOA_STLINK_TX 2U -#define GPIOA_LPUART1_TX 2U -#define GPIOA_PIN3 3U -#define GPIOA_STLINK_RX 3U -#define GPIOA_LPUART1_RX 3U -#define GPIOA_PIN4 4U -#define GPIOA_SMPS_EN 4U -#define GPIOA_PIN5 5U -#define GPIOA_SMPS_V1 5U -#define GPIOA_PIN6 6U -#define GPIOA_SMPS_PG 6U -#define GPIOA_PIN7 7U -#define GPIOA_SMPS_SW 7U -#define GPIOA_PIN8 8U -#define GPIOA_ARD_D9 8U -#define GPIOA_TIM1_CH1 8U -#define GPIOA_PIN9 9U -#define GPIOA_ARD_D1_TX 9U -#define GPIOA_UART1_TX 9U -#define GPIOA_PIN10 10U -#define GPIOA_ARD_D0_RX 10U -#define GPIOA_UART1_RX 10U -#define GPIOA_PIN11 11U -#define GPIOA_ARD_D10 11U -#define GPIOA_TIM1_CH4 11U -#define GPIOA_PIN12 12U -#define GPIOA_ARD_D2 12U -#define GPIOA_PIN13 13U -#define GPIOA_SWDIO 13U -#define GPIOA_PIN14 14U -#define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U -#define GPIOA_ARD_D5 15U -#define GPIOA_TIM2_CH1 15U - -#define GPIOB_PIN0 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_ARD_D3 3U -#define GPIOB_TIM2_CH2 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_ARD_D4 5U -#define GPIOB_PIN6 6U -#define GPIOB_ARD_D8 6U -#define GPIOB_PIN7 7U -#define GPIOB_ARD_D14 7U -#define GPIOB_I2C1_SDA 7U -#define GPIOB_PIN8 8U -#define GPIOB_ARD_D15 8U -#define GPIOB_I2C1_SCL 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_ARD_D6 10U -#define GPIOB_TIM2_CH3 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_ARD_D13 13U -#define GPIOB_SPI2_SCK 13U -#define GPIOB_LED 13U -#define GPIOB_PIN14 14U -#define GPIOB_ARD_D12 14U -#define GPIOB_SPI2_MISO 14U -#define GPIOB_PIN15 15U -#define GPIOB_ARD_D11 15U -#define GPIOB_SPI2_MOSI 15U -#define GPIOB_TIM15_CH2 15U - -#define GPIOC_PIN0 0U -#define GPIOC_ARD_A5 0U -#define GPIOC_ADC1_IN1 0U -#define GPIOC_I2C3_SCL 0U -#define GPIOC_PIN1 1U -#define GPIOC_ARD_A4 1U -#define GPIOC_ADC1_IN2 1U -#define GPIOC_I2C3_SDA 1U -#define GPIOC_PIN2 2U -#define GPIOC_ARD_A3 2U -#define GPIOC_ADC1_IN3 2U -#define GPIOC_PIN3 3U -#define GPIOC_ARD_A2 3U -#define GPIOC_ADC1_IN4 3U -#define GPIOC_PIN4 4U -#define GPIOC_PIN5 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_ARD_D7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_BUTTON 13U -#define GPIOC_PIN14 14U -#define GPIOC_OSC32_IN 14U -#define GPIOC_PIN15 15U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_PIN1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_PIN6 6U -#define GPIOG_PIN7 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_PIN11 11U -#define GPIOG_PIN12 12U -#define GPIOG_PIN13 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_PIN0 0U -#define GPIOH_OSC_IN 0U -#define GPIOH_PIN1 1U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) -#define LINE_ADC1_IN5 PAL_LINE(GPIOA, 0U) -#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) -#define LINE_ADC1_IN6 PAL_LINE(GPIOA, 1U) -#define LINE_STLINK_TX PAL_LINE(GPIOA, 2U) -#define LINE_STLINK_RX PAL_LINE(GPIOA, 3U) -#define LINE_SMPS_EN PAL_LINE(GPIOA, 4U) -#define LINE_SMPS_V1 PAL_LINE(GPIOA, 5U) -#define LINE_SMPS_PG PAL_LINE(GPIOA, 6U) -#define LINE_SMPS_SW PAL_LINE(GPIOA, 7U) -#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U) -#define LINE_ARD_D1_TX PAL_LINE(GPIOA, 9U) -#define LINE_ARD_D0_RX PAL_LINE(GPIOA, 10U) -#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) -#define LINE_ARD_D2 PAL_LINE(GPIOA, 12U) -#define LINE_ARD_D5 PAL_LINE(GPIOA, 15U) -#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) -#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) -#define LINE_ARD_D8 PAL_LINE(GPIOB, 6U) -#define LINE_ARD_D14 PAL_LINE(GPIOB, 7U) -#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) -#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) -#define LINE_ARD_D13 PAL_LINE(GPIOB, 13U) -#define LINE_LED PAL_LINE(GPIOB, 13U) -#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) -#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) -#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) -#define LINE_ADC1_IN1 PAL_LINE(GPIOC, 0U) -#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) -#define LINE_ADC1_IN2 PAL_LINE(GPIOC, 1U) -#define LINE_ARD_A3 PAL_LINE(GPIOC, 2U) -#define LINE_ADC1_IN3 PAL_LINE(GPIOC, 2U) -#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) -#define LINE_ADC1_IN4 PAL_LINE(GPIOC, 3U) -#define LINE_ARD_D7 PAL_LINE(GPIOC, 7U) -#define LINE_BUTTON PAL_LINE(GPIOC, 13U) -#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) -#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) -#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) -#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) -#define PIN_ASCR_DISABLED(n) (0U << (n)) -#define PIN_ASCR_ENABLED(n) (1U << (n)) -#define PIN_LOCKR_DISABLED(n) (0U << (n)) -#define PIN_LOCKR_ENABLED(n) (1U << (n)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (analog). - * PA1 - PIN1 (analog). - * PA2 - PIN2 STLINK_TX (alternate 8). - * PA3 - PIN3 STLINK_RX (alternate 8). - * PA4 - PIN4 (analog). - * PA5 - PIN5 (analog). - * PA6 - PIN6 (analog). - * PA7 - PIN7 (analog). - * PA8 - PIN8 (analog). - * PA9 - PIN9 (analog). - * PA10 - PIN10 (analog). - * PA11 - PIN11 (analog). - * PA12 - PIN12 (analog). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - PIN15 (analog). - */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \ - PIN_MODE_ANALOG(GPIOA_PIN1) | \ - PIN_MODE_ALTERNATE(GPIOA_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOA_PIN3) | \ - PIN_MODE_ANALOG(GPIOA_PIN4) | \ - PIN_MODE_ANALOG(GPIOA_PIN5) | \ - PIN_MODE_ANALOG(GPIOA_PIN6) | \ - PIN_MODE_ANALOG(GPIOA_PIN7) | \ - PIN_MODE_ANALOG(GPIOA_PIN8) | \ - PIN_MODE_ANALOG(GPIOA_PIN9) | \ - PIN_MODE_ANALOG(GPIOA_PIN10) | \ - PIN_MODE_ANALOG(GPIOA_PIN11) | \ - PIN_MODE_ANALOG(GPIOA_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ANALOG(GPIOA_PIN15)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_PIN1) | \ - PIN_OSPEED_MEDIUM(GPIOA_PIN2) | \ - PIN_OSPEED_MEDIUM(GPIOA_PIN3) | \ - PIN_OSPEED_HIGH(GPIOA_PIN4) | \ - PIN_OSPEED_HIGH(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_PIN7) | \ - PIN_OSPEED_HIGH(GPIOA_PIN8) | \ - PIN_OSPEED_HIGH(GPIOA_PIN9) | \ - PIN_OSPEED_HIGH(GPIOA_PIN10) | \ - PIN_OSPEED_HIGH(GPIOA_PIN11) | \ - PIN_OSPEED_HIGH(GPIOA_PIN12) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN15)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_PIN9) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_PIN11) | \ - PIN_ODR_HIGH(GPIOA_PIN12) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_PIN15)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN2, 8U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 8U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN15, 0U)) -#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_PIN0) | \ - PIN_ASCR_DISABLED(GPIOA_PIN1) | \ - PIN_ASCR_DISABLED(GPIOA_PIN2) | \ - PIN_ASCR_DISABLED(GPIOA_PIN3) | \ - PIN_ASCR_DISABLED(GPIOA_PIN4) | \ - PIN_ASCR_DISABLED(GPIOA_PIN5) | \ - PIN_ASCR_DISABLED(GPIOA_PIN6) | \ - PIN_ASCR_DISABLED(GPIOA_PIN7) | \ - PIN_ASCR_DISABLED(GPIOA_PIN8) | \ - PIN_ASCR_DISABLED(GPIOA_PIN9) | \ - PIN_ASCR_DISABLED(GPIOA_PIN10) | \ - PIN_ASCR_DISABLED(GPIOA_PIN11) | \ - PIN_ASCR_DISABLED(GPIOA_PIN12) | \ - PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ - PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ - PIN_ASCR_DISABLED(GPIOA_PIN15)) -#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ - PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ - PIN_LOCKR_DISABLED(GPIOA_PIN15)) - -/* - * GPIOB setup: - * - * PB0 - PIN0 (analog). - * PB1 - PIN1 (analog). - * PB2 - PIN2 (analog). - * PB3 - PIN3 (analog). - * PB4 - PIN4 (analog). - * PB5 - PIN5 (analog). - * PB6 - PIN6 (analog). - * PB7 - PIN7 (analog). - * PB8 - PIN8 (alternate 9). - * PB9 - PIN9 (alternate 9). - * PB10 - PIN10 (analog). - * PB11 - PIN11 (analog). - * PB12 - PIN12 (analog). - * PB13 - PIN13 LED (output pushpull maximum). - * PB14 - PIN14 (analog). - * PB15 - PIN15 (analog). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \ - PIN_MODE_ANALOG(GPIOB_PIN1) | \ - PIN_MODE_ANALOG(GPIOB_PIN2) | \ - PIN_MODE_ANALOG(GPIOB_PIN3) | \ - PIN_MODE_ANALOG(GPIOB_PIN4) | \ - PIN_MODE_ANALOG(GPIOB_PIN5) | \ - PIN_MODE_ANALOG(GPIOB_PIN6) | \ - PIN_MODE_ANALOG(GPIOB_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOB_PIN8) | \ - PIN_MODE_ALTERNATE(GPIOB_PIN9) | \ - PIN_MODE_ANALOG(GPIOB_PIN10) | \ - PIN_MODE_ANALOG(GPIOB_PIN11) | \ - PIN_MODE_ANALOG(GPIOB_PIN12) | \ - PIN_MODE_OUTPUT(GPIOB_PIN13) | \ - PIN_MODE_ANALOG(GPIOB_PIN14) | \ - PIN_MODE_ANALOG(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ - PIN_OSPEED_HIGH(GPIOB_PIN1) | \ - PIN_OSPEED_HIGH(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_PIN3) | \ - PIN_OSPEED_HIGH(GPIOB_PIN4) | \ - PIN_OSPEED_HIGH(GPIOB_PIN5) | \ - PIN_OSPEED_HIGH(GPIOB_PIN6) | \ - PIN_OSPEED_HIGH(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_PIN8) | \ - PIN_OSPEED_HIGH(GPIOB_PIN9) | \ - PIN_OSPEED_HIGH(GPIOB_PIN10) | \ - PIN_OSPEED_HIGH(GPIOB_PIN11) | \ - PIN_OSPEED_HIGH(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_PIN13) | \ - PIN_OSPEED_HIGH(GPIOB_PIN14) | \ - PIN_OSPEED_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_PIN3) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_LOW(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 9U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 9U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) -#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \ - PIN_ASCR_DISABLED(GPIOB_PIN1) | \ - PIN_ASCR_DISABLED(GPIOB_PIN2) | \ - PIN_ASCR_DISABLED(GPIOB_PIN3) | \ - PIN_ASCR_DISABLED(GPIOB_PIN4) | \ - PIN_ASCR_DISABLED(GPIOB_PIN5) | \ - PIN_ASCR_DISABLED(GPIOB_PIN6) | \ - PIN_ASCR_DISABLED(GPIOB_PIN7) | \ - PIN_ASCR_DISABLED(GPIOB_PIN8) | \ - PIN_ASCR_DISABLED(GPIOB_PIN9) | \ - PIN_ASCR_DISABLED(GPIOB_PIN10) | \ - PIN_ASCR_DISABLED(GPIOB_PIN11) | \ - PIN_ASCR_DISABLED(GPIOB_PIN12) | \ - PIN_ASCR_DISABLED(GPIOB_PIN13) | \ - PIN_ASCR_DISABLED(GPIOB_PIN14) | \ - PIN_ASCR_DISABLED(GPIOB_PIN15)) -#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOB_PIN15)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (analog). - * PC1 - PIN1 (analog). - * PC2 - PIN2 (analog). - * PC3 - PIN3 (analog). - * PC4 - PIN4 (analog). - * PC5 - PIN5 (analog). - * PC6 - PIN6 (analog). - * PC7 - PIN7 (analog). - * PC8 - PIN8 (analog). - * PC9 - PIN9 (analog). - * PC10 - PIN10 (analog). - * PC11 - PIN11 (analog). - * PC12 - PIN12 (analog). - * PC13 - PIN13 BUTTON (input floating). - * PC14 - PIN14 (analog). - * PC15 - PIN15 (analog). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \ - PIN_MODE_ANALOG(GPIOC_PIN1) | \ - PIN_MODE_ANALOG(GPIOC_PIN2) | \ - PIN_MODE_ANALOG(GPIOC_PIN3) | \ - PIN_MODE_ANALOG(GPIOC_PIN4) | \ - PIN_MODE_ANALOG(GPIOC_PIN5) | \ - PIN_MODE_ANALOG(GPIOC_PIN6) | \ - PIN_MODE_ANALOG(GPIOC_PIN7) | \ - PIN_MODE_ANALOG(GPIOC_PIN8) | \ - PIN_MODE_ANALOG(GPIOC_PIN9) | \ - PIN_MODE_ANALOG(GPIOC_PIN10) | \ - PIN_MODE_ANALOG(GPIOC_PIN11) | \ - PIN_MODE_ANALOG(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_ANALOG(GPIOC_PIN14) | \ - PIN_MODE_ANALOG(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_PIN1) | \ - PIN_OSPEED_HIGH(GPIOC_PIN2) | \ - PIN_OSPEED_HIGH(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_PIN4) | \ - PIN_OSPEED_HIGH(GPIOC_PIN5) | \ - PIN_OSPEED_HIGH(GPIOC_PIN6) | \ - PIN_OSPEED_HIGH(GPIOC_PIN7) | \ - PIN_OSPEED_HIGH(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_PIN9) | \ - PIN_OSPEED_HIGH(GPIOC_PIN10) | \ - PIN_OSPEED_HIGH(GPIOC_PIN11) | \ - PIN_OSPEED_HIGH(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_PIN14) | \ - PIN_OSPEED_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0U)) -#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \ - PIN_ASCR_DISABLED(GPIOC_PIN1) | \ - PIN_ASCR_DISABLED(GPIOC_PIN2) | \ - PIN_ASCR_DISABLED(GPIOC_PIN3) | \ - PIN_ASCR_DISABLED(GPIOC_PIN4) | \ - PIN_ASCR_DISABLED(GPIOC_PIN5) | \ - PIN_ASCR_DISABLED(GPIOC_PIN6) | \ - PIN_ASCR_DISABLED(GPIOC_PIN7) | \ - PIN_ASCR_DISABLED(GPIOC_PIN8) | \ - PIN_ASCR_DISABLED(GPIOC_PIN9) | \ - PIN_ASCR_DISABLED(GPIOC_PIN10) | \ - PIN_ASCR_DISABLED(GPIOC_PIN11) | \ - PIN_ASCR_DISABLED(GPIOC_PIN12) | \ - PIN_ASCR_DISABLED(GPIOC_PIN13) | \ - PIN_ASCR_DISABLED(GPIOC_PIN14) | \ - PIN_ASCR_DISABLED(GPIOC_PIN15)) -#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOC_PIN15)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (analog). - * PD1 - PIN1 (analog). - * PD2 - PIN2 (analog). - * PD3 - PIN3 (analog). - * PD4 - PIN4 (analog). - * PD5 - PIN5 (analog). - * PD6 - PIN6 (analog). - * PD7 - PIN7 (analog). - * PD8 - PIN8 (analog). - * PD9 - PIN9 (analog). - * PD10 - PIN10 (analog). - * PD11 - PIN11 (analog). - * PD12 - PIN12 (analog). - * PD13 - PIN13 (analog). - * PD14 - PIN14 (analog). - * PD15 - PIN15 (analog). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ - PIN_MODE_ANALOG(GPIOD_PIN1) | \ - PIN_MODE_ANALOG(GPIOD_PIN2) | \ - PIN_MODE_ANALOG(GPIOD_PIN3) | \ - PIN_MODE_ANALOG(GPIOD_PIN4) | \ - PIN_MODE_ANALOG(GPIOD_PIN5) | \ - PIN_MODE_ANALOG(GPIOD_PIN6) | \ - PIN_MODE_ANALOG(GPIOD_PIN7) | \ - PIN_MODE_ANALOG(GPIOD_PIN8) | \ - PIN_MODE_ANALOG(GPIOD_PIN9) | \ - PIN_MODE_ANALOG(GPIOD_PIN10) | \ - PIN_MODE_ANALOG(GPIOD_PIN11) | \ - PIN_MODE_ANALOG(GPIOD_PIN12) | \ - PIN_MODE_ANALOG(GPIOD_PIN13) | \ - PIN_MODE_ANALOG(GPIOD_PIN14) | \ - PIN_MODE_ANALOG(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ - PIN_OSPEED_HIGH(GPIOD_PIN1) | \ - PIN_OSPEED_HIGH(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_PIN3) | \ - PIN_OSPEED_HIGH(GPIOD_PIN4) | \ - PIN_OSPEED_HIGH(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_PIN6) | \ - PIN_OSPEED_HIGH(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_PIN8) | \ - PIN_OSPEED_HIGH(GPIOD_PIN9) | \ - PIN_OSPEED_HIGH(GPIOD_PIN10) | \ - PIN_OSPEED_HIGH(GPIOD_PIN11) | \ - PIN_OSPEED_HIGH(GPIOD_PIN12) | \ - PIN_OSPEED_HIGH(GPIOD_PIN13) | \ - PIN_OSPEED_HIGH(GPIOD_PIN14) | \ - PIN_OSPEED_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) -#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ - PIN_ASCR_DISABLED(GPIOD_PIN1) | \ - PIN_ASCR_DISABLED(GPIOD_PIN2) | \ - PIN_ASCR_DISABLED(GPIOD_PIN3) | \ - PIN_ASCR_DISABLED(GPIOD_PIN4) | \ - PIN_ASCR_DISABLED(GPIOD_PIN5) | \ - PIN_ASCR_DISABLED(GPIOD_PIN6) | \ - PIN_ASCR_DISABLED(GPIOD_PIN7) | \ - PIN_ASCR_DISABLED(GPIOD_PIN8) | \ - PIN_ASCR_DISABLED(GPIOD_PIN9) | \ - PIN_ASCR_DISABLED(GPIOD_PIN10) | \ - PIN_ASCR_DISABLED(GPIOD_PIN11) | \ - PIN_ASCR_DISABLED(GPIOD_PIN12) | \ - PIN_ASCR_DISABLED(GPIOD_PIN13) | \ - PIN_ASCR_DISABLED(GPIOD_PIN14) | \ - PIN_ASCR_DISABLED(GPIOD_PIN15)) -#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOD_PIN15)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (analog). - * PE1 - PIN1 (analog). - * PE2 - PIN2 (analog). - * PE3 - PIN3 (analog). - * PE4 - PIN4 (analog). - * PE5 - PIN5 (analog). - * PE6 - PIN6 (analog). - * PE7 - PIN7 (analog). - * PE8 - PIN8 (analog). - * PE9 - PIN9 (analog). - * PE10 - PIN10 (analog). - * PE11 - PIN11 (analog). - * PE12 - PIN12 (analog). - * PE13 - PIN13 (analog). - * PE14 - PIN14 (analog). - * PE15 - PIN15 (analog). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ - PIN_MODE_ANALOG(GPIOE_PIN1) | \ - PIN_MODE_ANALOG(GPIOE_PIN2) | \ - PIN_MODE_ANALOG(GPIOE_PIN3) | \ - PIN_MODE_ANALOG(GPIOE_PIN4) | \ - PIN_MODE_ANALOG(GPIOE_PIN5) | \ - PIN_MODE_ANALOG(GPIOE_PIN6) | \ - PIN_MODE_ANALOG(GPIOE_PIN7) | \ - PIN_MODE_ANALOG(GPIOE_PIN8) | \ - PIN_MODE_ANALOG(GPIOE_PIN9) | \ - PIN_MODE_ANALOG(GPIOE_PIN10) | \ - PIN_MODE_ANALOG(GPIOE_PIN11) | \ - PIN_MODE_ANALOG(GPIOE_PIN12) | \ - PIN_MODE_ANALOG(GPIOE_PIN13) | \ - PIN_MODE_ANALOG(GPIOE_PIN14) | \ - PIN_MODE_ANALOG(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_PIN1) | \ - PIN_OSPEED_HIGH(GPIOE_PIN2) | \ - PIN_OSPEED_HIGH(GPIOE_PIN3) | \ - PIN_OSPEED_HIGH(GPIOE_PIN4) | \ - PIN_OSPEED_HIGH(GPIOE_PIN5) | \ - PIN_OSPEED_HIGH(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_PIN7) | \ - PIN_OSPEED_HIGH(GPIOE_PIN8) | \ - PIN_OSPEED_HIGH(GPIOE_PIN9) | \ - PIN_OSPEED_HIGH(GPIOE_PIN10) | \ - PIN_OSPEED_HIGH(GPIOE_PIN11) | \ - PIN_OSPEED_HIGH(GPIOE_PIN12) | \ - PIN_OSPEED_HIGH(GPIOE_PIN13) | \ - PIN_OSPEED_HIGH(GPIOE_PIN14) | \ - PIN_OSPEED_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_HIGH(GPIOE_PIN1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) -#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ - PIN_ASCR_DISABLED(GPIOE_PIN1) | \ - PIN_ASCR_DISABLED(GPIOE_PIN2) | \ - PIN_ASCR_DISABLED(GPIOE_PIN3) | \ - PIN_ASCR_DISABLED(GPIOE_PIN4) | \ - PIN_ASCR_DISABLED(GPIOE_PIN5) | \ - PIN_ASCR_DISABLED(GPIOE_PIN6) | \ - PIN_ASCR_DISABLED(GPIOE_PIN7) | \ - PIN_ASCR_DISABLED(GPIOE_PIN8) | \ - PIN_ASCR_DISABLED(GPIOE_PIN9) | \ - PIN_ASCR_DISABLED(GPIOE_PIN10) | \ - PIN_ASCR_DISABLED(GPIOE_PIN11) | \ - PIN_ASCR_DISABLED(GPIOE_PIN12) | \ - PIN_ASCR_DISABLED(GPIOE_PIN13) | \ - PIN_ASCR_DISABLED(GPIOE_PIN14) | \ - PIN_ASCR_DISABLED(GPIOE_PIN15)) -#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOE_PIN15)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (analog). - * PF1 - PIN1 (analog). - * PF2 - PIN2 (analog). - * PF3 - PIN3 (analog). - * PF4 - PIN4 (analog). - * PF5 - PIN5 (analog). - * PF6 - PIN6 (analog). - * PF7 - PIN7 (analog). - * PF8 - PIN8 (analog). - * PF9 - PIN9 (analog). - * PF10 - PIN10 (analog). - * PF11 - PIN11 (analog). - * PF12 - PIN12 (analog). - * PF13 - PIN13 (analog). - * PF14 - PIN14 (analog). - * PF15 - PIN15 (analog). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ - PIN_MODE_ANALOG(GPIOF_PIN1) | \ - PIN_MODE_ANALOG(GPIOF_PIN2) | \ - PIN_MODE_ANALOG(GPIOF_PIN3) | \ - PIN_MODE_ANALOG(GPIOF_PIN4) | \ - PIN_MODE_ANALOG(GPIOF_PIN5) | \ - PIN_MODE_ANALOG(GPIOF_PIN6) | \ - PIN_MODE_ANALOG(GPIOF_PIN7) | \ - PIN_MODE_ANALOG(GPIOF_PIN8) | \ - PIN_MODE_ANALOG(GPIOF_PIN9) | \ - PIN_MODE_ANALOG(GPIOF_PIN10) | \ - PIN_MODE_ANALOG(GPIOF_PIN11) | \ - PIN_MODE_ANALOG(GPIOF_PIN12) | \ - PIN_MODE_ANALOG(GPIOF_PIN13) | \ - PIN_MODE_ANALOG(GPIOF_PIN14) | \ - PIN_MODE_ANALOG(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ - PIN_OSPEED_HIGH(GPIOF_PIN1) | \ - PIN_OSPEED_HIGH(GPIOF_PIN2) | \ - PIN_OSPEED_HIGH(GPIOF_PIN3) | \ - PIN_OSPEED_HIGH(GPIOF_PIN4) | \ - PIN_OSPEED_HIGH(GPIOF_PIN5) | \ - PIN_OSPEED_HIGH(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_PIN7) | \ - PIN_OSPEED_HIGH(GPIOF_PIN8) | \ - PIN_OSPEED_HIGH(GPIOF_PIN9) | \ - PIN_OSPEED_HIGH(GPIOF_PIN10) | \ - PIN_OSPEED_HIGH(GPIOF_PIN11) | \ - PIN_OSPEED_HIGH(GPIOF_PIN12) | \ - PIN_OSPEED_HIGH(GPIOF_PIN13) | \ - PIN_OSPEED_HIGH(GPIOF_PIN14) | \ - PIN_OSPEED_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) -#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ - PIN_ASCR_DISABLED(GPIOF_PIN1) | \ - PIN_ASCR_DISABLED(GPIOF_PIN2) | \ - PIN_ASCR_DISABLED(GPIOF_PIN3) | \ - PIN_ASCR_DISABLED(GPIOF_PIN4) | \ - PIN_ASCR_DISABLED(GPIOF_PIN5) | \ - PIN_ASCR_DISABLED(GPIOF_PIN6) | \ - PIN_ASCR_DISABLED(GPIOF_PIN7) | \ - PIN_ASCR_DISABLED(GPIOF_PIN8) | \ - PIN_ASCR_DISABLED(GPIOF_PIN9) | \ - PIN_ASCR_DISABLED(GPIOF_PIN10) | \ - PIN_ASCR_DISABLED(GPIOF_PIN11) | \ - PIN_ASCR_DISABLED(GPIOF_PIN12) | \ - PIN_ASCR_DISABLED(GPIOF_PIN13) | \ - PIN_ASCR_DISABLED(GPIOF_PIN14) | \ - PIN_ASCR_DISABLED(GPIOF_PIN15)) -#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOF_PIN15)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (analog). - * PG1 - PIN1 (analog). - * PG2 - PIN2 (analog). - * PG3 - PIN3 (analog). - * PG4 - PIN4 (analog). - * PG5 - PIN5 (analog). - * PG6 - PIN6 (analog). - * PG7 - PIN7 (analog). - * PG8 - PIN8 (analog). - * PG9 - PIN9 (analog). - * PG10 - PIN10 (analog). - * PG11 - PIN11 (analog). - * PG12 - PIN12 (analog). - * PG13 - PIN13 (analog). - * PG14 - PIN14 (analog). - * PG15 - PIN15 (analog). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ - PIN_MODE_ANALOG(GPIOG_PIN1) | \ - PIN_MODE_ANALOG(GPIOG_PIN2) | \ - PIN_MODE_ANALOG(GPIOG_PIN3) | \ - PIN_MODE_ANALOG(GPIOG_PIN4) | \ - PIN_MODE_ANALOG(GPIOG_PIN5) | \ - PIN_MODE_ANALOG(GPIOG_PIN6) | \ - PIN_MODE_ANALOG(GPIOG_PIN7) | \ - PIN_MODE_ANALOG(GPIOG_PIN8) | \ - PIN_MODE_ANALOG(GPIOG_PIN9) | \ - PIN_MODE_ANALOG(GPIOG_PIN10) | \ - PIN_MODE_ANALOG(GPIOG_PIN11) | \ - PIN_MODE_ANALOG(GPIOG_PIN12) | \ - PIN_MODE_ANALOG(GPIOG_PIN13) | \ - PIN_MODE_ANALOG(GPIOG_PIN14) | \ - PIN_MODE_ANALOG(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ - PIN_OSPEED_HIGH(GPIOG_PIN1) | \ - PIN_OSPEED_HIGH(GPIOG_PIN2) | \ - PIN_OSPEED_HIGH(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_PIN4) | \ - PIN_OSPEED_HIGH(GPIOG_PIN5) | \ - PIN_OSPEED_HIGH(GPIOG_PIN6) | \ - PIN_OSPEED_HIGH(GPIOG_PIN7) | \ - PIN_OSPEED_HIGH(GPIOG_PIN8) | \ - PIN_OSPEED_HIGH(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_PIN11) | \ - PIN_OSPEED_HIGH(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_PIN13) | \ - PIN_OSPEED_HIGH(GPIOG_PIN14) | \ - PIN_OSPEED_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) -#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ - PIN_ASCR_DISABLED(GPIOG_PIN1) | \ - PIN_ASCR_DISABLED(GPIOG_PIN2) | \ - PIN_ASCR_DISABLED(GPIOG_PIN3) | \ - PIN_ASCR_DISABLED(GPIOG_PIN4) | \ - PIN_ASCR_DISABLED(GPIOG_PIN5) | \ - PIN_ASCR_DISABLED(GPIOG_PIN6) | \ - PIN_ASCR_DISABLED(GPIOG_PIN7) | \ - PIN_ASCR_DISABLED(GPIOG_PIN8) | \ - PIN_ASCR_DISABLED(GPIOG_PIN9) | \ - PIN_ASCR_DISABLED(GPIOG_PIN10) | \ - PIN_ASCR_DISABLED(GPIOG_PIN11) | \ - PIN_ASCR_DISABLED(GPIOG_PIN12) | \ - PIN_ASCR_DISABLED(GPIOG_PIN13) | \ - PIN_ASCR_DISABLED(GPIOG_PIN14) | \ - PIN_ASCR_DISABLED(GPIOG_PIN15)) -#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOG_PIN15)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (analog). - * PH3 - PIN3 (analog). - * PH4 - PIN4 (analog). - * PH5 - PIN5 (analog). - * PH6 - PIN6 (analog). - * PH7 - PIN7 (analog). - * PH8 - PIN8 (analog). - * PH9 - PIN9 (analog). - * PH10 - PIN10 (analog). - * PH11 - PIN11 (analog). - * PH12 - PIN12 (analog). - * PH13 - PIN13 (analog). - * PH14 - PIN14 (analog). - * PH15 - PIN15 (analog). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_ANALOG(GPIOH_PIN2) | \ - PIN_MODE_ANALOG(GPIOH_PIN3) | \ - PIN_MODE_ANALOG(GPIOH_PIN4) | \ - PIN_MODE_ANALOG(GPIOH_PIN5) | \ - PIN_MODE_ANALOG(GPIOH_PIN6) | \ - PIN_MODE_ANALOG(GPIOH_PIN7) | \ - PIN_MODE_ANALOG(GPIOH_PIN8) | \ - PIN_MODE_ANALOG(GPIOH_PIN9) | \ - PIN_MODE_ANALOG(GPIOH_PIN10) | \ - PIN_MODE_ANALOG(GPIOH_PIN11) | \ - PIN_MODE_ANALOG(GPIOH_PIN12) | \ - PIN_MODE_ANALOG(GPIOH_PIN13) | \ - PIN_MODE_ANALOG(GPIOH_PIN14) | \ - PIN_MODE_ANALOG(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_PIN2) | \ - PIN_OSPEED_HIGH(GPIOH_PIN3) | \ - PIN_OSPEED_HIGH(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_PIN5) | \ - PIN_OSPEED_HIGH(GPIOH_PIN6) | \ - PIN_OSPEED_HIGH(GPIOH_PIN7) | \ - PIN_OSPEED_HIGH(GPIOH_PIN8) | \ - PIN_OSPEED_HIGH(GPIOH_PIN9) | \ - PIN_OSPEED_HIGH(GPIOH_PIN10) | \ - PIN_OSPEED_HIGH(GPIOH_PIN11) | \ - PIN_OSPEED_HIGH(GPIOH_PIN12) | \ - PIN_OSPEED_HIGH(GPIOH_PIN13) | \ - PIN_OSPEED_HIGH(GPIOH_PIN14) | \ - PIN_OSPEED_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) -#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \ - PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \ - PIN_ASCR_DISABLED(GPIOH_PIN2) | \ - PIN_ASCR_DISABLED(GPIOH_PIN3) | \ - PIN_ASCR_DISABLED(GPIOH_PIN4) | \ - PIN_ASCR_DISABLED(GPIOH_PIN5) | \ - PIN_ASCR_DISABLED(GPIOH_PIN6) | \ - PIN_ASCR_DISABLED(GPIOH_PIN7) | \ - PIN_ASCR_DISABLED(GPIOH_PIN8) | \ - PIN_ASCR_DISABLED(GPIOH_PIN9) | \ - PIN_ASCR_DISABLED(GPIOH_PIN10) | \ - PIN_ASCR_DISABLED(GPIOH_PIN11) | \ - PIN_ASCR_DISABLED(GPIOH_PIN12) | \ - PIN_ASCR_DISABLED(GPIOH_PIN13) | \ - PIN_ASCR_DISABLED(GPIOH_PIN14) | \ - PIN_ASCR_DISABLED(GPIOH_PIN15)) -#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \ - PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ - PIN_LOCKR_DISABLED(GPIOH_PIN15)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/boards/ST_NUCLEO64_L452RE_P/board.mk b/boards/ST_NUCLEO64_L452RE_P/board.mk deleted file mode 100644 index 60673b37..00000000 --- a/boards/ST_NUCLEO64_L452RE_P/board.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c - -# Required include directories -BOARDINC = $(BOARDDIR) - -# Shared variables -ALLCSRC += $(BOARDSRC) -ALLINC += $(BOARDINC) diff --git a/boards/ST_NUCLEO64_L452RE_P/gdboocd.cmd b/boards/ST_NUCLEO64_L452RE_P/gdboocd.cmd deleted file mode 100644 index d386b739..00000000 --- a/boards/ST_NUCLEO64_L452RE_P/gdboocd.cmd +++ /dev/null @@ -1,2 +0,0 @@ -monitor stm32l4x.cpu configure -rtos chibios -monitor reset halt diff --git a/boards/ST_NUCLEO64_L452RE_P/oocd.cfg b/boards/ST_NUCLEO64_L452RE_P/oocd.cfg deleted file mode 100644 index 7f81f2b4..00000000 --- a/boards/ST_NUCLEO64_L452RE_P/oocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# -# for use with STLINK V2 SWD programmer -# - -source [find interface/stlink.cfg] -transport select hla_swd -source [find target/stm32l4x.cfg] - diff --git a/common/README.md b/common/README.md deleted file mode 100644 index d710707b..00000000 --- a/common/README.md +++ /dev/null @@ -1 +0,0 @@ -# Common Source Files and Libraries diff --git a/common/aprs.c b/common/aprs.c deleted file mode 100644 index a2044e17..00000000 --- a/common/aprs.c +++ /dev/null @@ -1,35 +0,0 @@ -/** - * @file aprs.c - * @brief Automatic Packet Reporting System (APRS) support library. - * - * @addtogroup APRS - * @{ - */ -#include -#include "aprs.h" - -/*===========================================================================*/ -/* Local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Interface implementation. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/common/aprs.mk b/common/aprs.mk deleted file mode 100644 index a40ba389..00000000 --- a/common/aprs.mk +++ /dev/null @@ -1,10 +0,0 @@ -# List of all the APRS protocol files. -APRSSRC := $(PROJ_SRC)/ax25.c \ - $(PROJ_SRC)/aprs.c - -# Required include directories -APRSINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(APRSSRC) -ALLINC += $(APRSINC) diff --git a/common/ax25.c b/common/ax25.c deleted file mode 100644 index 063cb0f5..00000000 --- a/common/ax25.c +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file ax25.c - * @brief AX.25 protocol support library. - * - * @addtogroup AX25 - * @{ - */ -#include -#include "ax25.h" - -/*===========================================================================*/ -/* Local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Interface implementation. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Exported functions. */ -/*===========================================================================*/ - -void *ax25_sdu(fb_t *fb, const void *arg) -{ - const ax25_link_t *link = arg; - ax25_hdr_t *mac_hdr; - - mac_hdr = fb_push(fb, sizeof(ax25_hdr_t)); - if (mac_hdr != NULL) { - for (int i = 0; i < 6; i++) { - /* Shift characters and convert NULL's to spaces */ - mac_hdr->dest[i] = (link->dest[i] != 0 ? link->dest[i] << 1 : 0x20 << 1); - mac_hdr->src[i] = (link->src[i] != 0 ? link->src[i] << 1 : 0x20 << 1); - } - mac_hdr->dest_ssid = AX25_SSID(link->dest_ssid); - mac_hdr->src_ssid = AX25_SSID(link->src_ssid) | AX25_SSID_EXT; - mac_hdr->control = link->control; - mac_hdr->sid = link->sid; - } - - return mac_hdr; -} - -/** @} */ diff --git a/common/ax5043.c b/common/ax5043.c deleted file mode 100644 index bafadb3e..00000000 --- a/common/ax5043.c +++ /dev/null @@ -1,1365 +0,0 @@ -/** - * @file ax5043.c - * @brief AX5043 Radio. - * - * @addtogroup AX5043 - * @{ - */ -#include -#include "ch.h" -#include "hal.h" -#include "ax5043.h" -#include "radio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief ChibiOS Event masks for AX5043. - */ -#define AX5043_EVENT_IRQ EVENT_MASK(0) -#define AX5043_EVENT_TERMINATE EVENT_MASK(1) - -/** - * @brief ChibiOS Event masks for AX5043. - */ -#define AX5043_FIFO_SIZE 256U - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -typedef union __attribute__((packed)) { - struct { - union { - uint16_t reg; - uint16_t status; - }; - uint8_t data[AX5043_FIFO_SIZE]; - }; - uint8_t buf[AX5043_FIFO_SIZE + sizeof(uint16_t)]; -} spibuf_t; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (AX5043_USE_SPI) || defined(__DOXYGEN__) -/** - * @brief Perform a long (16-bit address) exchange with AX5043 using SPI. - * @note Can be called with NULL values for txbuf and/or rxbuf. - * @note A maximum of 256 bytes can be transferred at a time using this function. - * @pre The SPI interface must be initialized, the driver started, and the device selected. - * - * @param[in] spip SPI Configuration - * @param[in] reg Register address - * @param[in] write Indicates Read/Write bit - * @param[in] txbuf Buffer to send data from - * @param[out] rxbuf Buffer to return data in - * @param[in] n Number of bytes to exchange - * - * @return AX5043 status bits - * @notapi - */ -ax5043_status_t ax5043SPIExchange(SPIDriver *spip, uint16_t reg, bool write, const void *txbuf, void *rxbuf, size_t n) { - spibuf_t sendbuf; - spibuf_t recvbuf; - - /* Ensure we don't exceed 256 bytes of data */ - n = (n < AX5043_FIFO_SIZE ? n : AX5043_FIFO_SIZE); - - /* Set the register address to perform the transaction with */ - sendbuf.reg = __REVSH((reg & 0x0FFFU) | 0x7000U | (write << 15)); - - /* Copy the TX data to the sending buffer */ - if (txbuf != NULL) { - memcpy(sendbuf.data, txbuf, n); - } else { - memset(sendbuf.data, 0, n); - } - - /* Perform the exchange */ - /* We always receive because we need the status bits */ - spiExchange(spip, n + sizeof(uint16_t), sendbuf.buf, recvbuf.buf); - - /* Copy the RX data to provided buffer */ - if (rxbuf != NULL) { - memcpy(rxbuf, recvbuf.data, n); - } - - return __REVSH(recvbuf.status); -} -#endif /* AX5043_USE_SPI */ - -/** - * @brief Interrupt handler for AX5043 IRQ signals. - * - * @param[in] arg Pointer to the @p AX5043Driver object - * - * @notapi - */ -void ax5043IRQHandler(void *arg) { - AX5043Driver *devp = arg; - - osalDbgCheck(devp != NULL && devp->irq_worker != NULL); - - chSysLockFromISR(); - chEvtSignalI(devp->irq_worker, AX5043_EVENT_IRQ); - chSysUnlockFromISR(); -} - -/** - * @brief Interrupt worker thread for AX5043 IRQ signals. - * @details Broadcasts IRQ signals and handles error conditions. - * - * @param[in] arg Pointer to the @p AX5043Driver object - * - * @notapi - */ -THD_FUNCTION(irq_worker, arg) { - AX5043Driver *devp = arg; - eventmask_t irq = 0; - - osalDbgCheck(devp != NULL); - - ax5043WriteU16(devp, AX5043_REG_IRQMASK, 0x0000U); - - while (!chThdShouldTerminateX()) { - chEvtWaitAny(AX5043_EVENT_IRQ | AX5043_EVENT_TERMINATE); - - /* Retrieve the pending interrupt requests */ - irq = ax5043ReadU16(devp, AX5043_REG_IRQREQUEST); - - /* Signal waiting thread with pending interrupts */ - chEvtBroadcastFlags(&devp->irq_event, irq); - } - chThdExit(MSG_OK); -} - -/** - * @brief Waits for the specified interrupts to occur - * - * @return Event mask - * @notapi - */ -eventmask_t ax5043WaitIRQ(AX5043Driver *devp, uint16_t irq, sysinterval_t timeout) { - event_listener_t el; - eventmask_t event; - uint16_t regval; - - osalDbgCheck(devp != NULL && devp->config != NULL); - - /* Register on the interrupt with the specified IRQ signals */ - chEvtRegisterMaskWithFlags(&devp->irq_event, &el, AX5043_EVENT_IRQ, irq); - - /* Enable the interrupt source */ - regval = ax5043ReadU16(devp, AX5043_REG_IRQMASK); - regval |= irq; - ax5043WriteU16(devp, AX5043_REG_IRQMASK, regval); - - /* Wait for the interrupt to occur */ - event = chEvtWaitAnyTimeout(AX5043_EVENT_IRQ | AX5043_EVENT_TERMINATE, timeout); - - /* Retrieve interrupt request value and unregister from interrupt */ - regval = chEvtGetAndClearFlags(&el); - chEvtUnregister(&devp->irq_event, &el); - - /* Disable the interrupt */ - regval &= ~irq; - ax5043WriteU16(devp, AX5043_REG_IRQMASK, regval); - return event; -} - -/** - * @brief RX worker thread for handling AX5043 receive data. - * - * @param[in] arg Pointer to the @p AX5043Driver object - * - * @notapi - */ -THD_FUNCTION(rx_worker, arg) { - AX5043Driver *devp = arg; - objects_fifo_t *fifo = devp->config->fifo; - fb_t *fb = NULL; - uint8_t buf[AX5043_FIFO_SIZE]; - ax5043_rx_chunk_t *chunkp = (ax5043_rx_chunk_t*)buf; - uint8_t header; - size_t length, data_len; - uint8_t *pos; - - osalDbgCheck(devp != NULL); - - while (!chThdShouldTerminateX()) { - - /* Wait for FIFO data */ - if (ax5043WaitIRQ(devp, AX5043_IRQ_FIFONOTEMPTY, TIME_INFINITE) & AX5043_EVENT_TERMINATE) { - continue; - } - - /* Get chunk header from FIFO */ - ax5043Exchange(devp, AX5043_REG_FIFODATA, false, NULL, &header, 1); - - /* Determine chunk length */ - length = _FLD2VAL(AX5043_FIFOCHUNK_SIZE, header); - if (length == AX5043_CHUNKSIZE_VAR) { - ax5043Exchange(devp, AX5043_REG_FIFODATA, false, NULL, &length, 1); - } - - /* Get chunk */ - ax5043Exchange(devp, AX5043_REG_FIFODATA, false, NULL, buf, length); - - /* Process chunk */ - switch (_FLD2VAL(AX5043_FIFOCHUNK_CMD, header)) { - case AX5043_CHUNKCMD_DATA: - data_len = length - sizeof(ax5043_chunk_data_t); - /* TODO: Handle error flags */ - /* Start of new packet */ - if (chunkp->data.flags & AX5043_CHUNK_DATARX_PKTSTART) { - /* Acquire frame buffer object if needed */ - if (fb != NULL) { - fb_free(fb, fifo); - fb = NULL; - } - while (fb == NULL) { - fb = fb_alloc(FB_MAX_LEN, fifo); - } - fb->phy_rx = devp; - fb->phy_arg = (void*)devp->config->phy_arg; - } - - osalDbgAssert(fb != NULL, "rx_worker(), NULL frame buffer object"); - pos = fb_put(fb, data_len); - if (pos != NULL) { - /* Copy packet data */ - memcpy(pos, chunkp->data.data, data_len); - } else { - /* Length exceeds maximum frame buffer length, abort receive */ - uint8_t reg = ax5043ReadU8(devp, AX5043_REG_FRAMING); - reg |= AX5043_FRAMING_FABORT; - ax5043WriteU8(devp, AX5043_REG_FRAMING, reg); - fb_free(fb, fifo); - fb = NULL; - } - - /* End of packet */ - if (chunkp->data.flags & AX5043_CHUNK_DATARX_PKTEND) { - if (fb != NULL) { - pdu_send(fb, fifo); - fb = NULL; - } - } - break; - case AX5043_CHUNKCMD_TIMER: - devp->timer = __REV(chunkp->timer.timer << 8); - break; - case AX5043_CHUNKCMD_RSSI: - devp->rssi = chunkp->rssi.rssi; - break; - case AX5043_CHUNKCMD_FREQOFFS: - devp->freq_off = __REV(chunkp->freqoffs.freqoffs << 8); - break; - case AX5043_CHUNKCMD_RFFREQOFFS: - devp->rf_freq_off = __REV(chunkp->rffreqoffs.rffreqoffs << 8); - break; - case AX5043_CHUNKCMD_DATARATE: - devp->datarate = __REV(chunkp->datarate.datarate << 8); - break; - case AX5043_CHUNKCMD_ANTRSSI: - if (length == 2) { - devp->ant0rssi = chunkp->antrssi2.rssi; - devp->bgndnoise = chunkp->antrssi2.bgndnoise; - } else if (length == 3) { - devp->ant0rssi = chunkp->antrssi3.ant0rssi; - devp->ant1rssi = chunkp->antrssi3.ant1rssi; - devp->bgndnoise = chunkp->antrssi3.bgndnoise; - } - break; - default: - break; - } - } - - if (fb != NULL) { - fb_free(fb, fifo); - fb = NULL; - } - chThdExit(MSG_OK); -} - -/** - * @brief Sets powermode register of AX5043. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] pwrmode Power mode register value. - * - * @return Most significant status bits (S14...S8) - * @notapi - */ -ax5043_status_t ax5043SetPWRMode(AX5043Driver *devp, uint8_t pwrmode) { - uint8_t regval = 0; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043SetPWRMode(), invalid state"); - - ax5043Exchange(devp, AX5043_REG_PWRMODE, false, NULL, ®val, 1); - regval &= ~AX5043_PWRMODE; - regval |= _VAL2FLD(AX5043_PWRMODE, pwrmode); - return ax5043Exchange(devp, AX5043_REG_PWRMODE, true, ®val, NULL, 1); -} - -/** - * @brief Resets the AX5043 device into POWERDOWN state. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return AX5043 status bits - * @notapi - */ -ax5043_status_t ax5043Reset(AX5043Driver *devp) { - ax5043_status_t status = 0; - uint8_t regval = 0; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043Reset(), invalid state"); - - devp->error = AX5043_ERR_NOERROR; - - /* Reset the chip through powermode register */ - regval = AX5043_PWRMODE_RESET; - ax5043WriteU8(devp, AX5043_REG_PWRMODE, regval); - - /* Write to PWRMODE: XOEN, REFEN and POWERDOWN mode. Clear RST bit. - Page 33 in programming manual */ - regval = AX5043_PWRMODE_REFEN | AX5043_PWRMODE_XOEN | AX5043_PWRMODE_POWERDOWN; - ax5043WriteU8(devp, AX5043_REG_PWRMODE, regval); - - /* Verify functionality with SCRATCH register */ - regval = 0xAA; - ax5043Exchange(devp, AX5043_REG_SCRATCH, true, ®val, NULL, 1); - regval = 0x55; - status = ax5043Exchange(devp, AX5043_REG_SCRATCH, true, ®val, ®val, 1); - if (regval != 0xAA) { - devp->error = AX5043_ERR_NOT_CONNECTED; - devp->state = AX5043_STOP; - return status; - } - status = ax5043Exchange(devp, AX5043_REG_SCRATCH, true, NULL, ®val, 1); - if (regval != 0x55) { - devp->error = AX5043_ERR_NOT_CONNECTED; - devp->state = AX5043_STOP; - return status; - } - - devp->state = AX5043_RESET; - return status; -} - -/** - * @brief Sets RFDIV related registers. - * - * @param[in] freq Frequency - * - * @notapi - */ -void ax5043SetRFDIV(AX5043Driver *devp, uint32_t freq) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043SetRFDIV(), invalid state"); - osalDbgAssert((freq >= AX5043_RFDIV_DIV1_MIN && freq <= AX5043_RFDIV_DIV1_MAX) || - (freq >= AX5043_RFDIV_DIV2_MIN && freq <= AX5043_RFDIV_DIV2_MAX), - "ax5043SetRFDIV(), frequency out of bounds"); - - uint8_t pllvcodiv = ax5043ReadU8(devp, AX5043_REG_PLLVCODIV); - if (freq >= AX5043_RFDIV_DIV1_MIN && freq <= AX5043_RFDIV_DIV1_MAX) { - pllvcodiv &= ~AX5043_PLLVCODIV_RFDIV; - } else { - pllvcodiv |= AX5043_PLLVCODIV_RFDIV; - } - ax5043WriteU8(devp, AX5043_REG_PLLVCODIV, pllvcodiv); - ax5043WriteU8(devp, AX5043_REG_0xF34, (pllvcodiv & AX5043_PLLVCODIV_RFDIV ? AX5043_0xF34_RFDIV : AX5043_0xF34_NORFDIV)); -} - -/*===========================================================================*/ -/* Interface implementation. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance of AX5043Driver object. - * - * @param[out] devp Pointer to the @p AX5043Driver object - * - * @init - */ -void ax5043ObjectInit(AX5043Driver *devp) { - devp->config = NULL; - - chMtxObjectInit(&devp->tx_lock); - - devp->irq_worker = NULL; - chEvtObjectInit(&devp->irq_event); - - devp->rx_worker = NULL; - - devp->preamble = NULL; - devp->postamble = NULL; - - devp->state = AX5043_STOP; -} - -/** - * @brief Configures and activates the AX5043 Radio Driver. - * - * @param[in] devp Pointer to the @p AX5043Driver object - * @param[in] config Pointer to the @p AX5043Config object - * - * @api - */ -void ax5043Start(AX5043Driver *devp, const AX5043Config *config) { - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state != AX5043_UNINIT), - "ax5043Start(), invalid state"); - - devp->config = config; - devp->error = AX5043_ERR_NOERROR; - devp->profile = config->profile; - devp->preamble = config->preamble; - devp->preamble_len = config->preamble_len; - devp->postamble = config->postamble; - devp->postamble_len = config->postamble_len; - - devp->vcora = 0; - devp->vcorb = 0; - devp->timer = 0; - devp->datarate = 0; - devp->freq_off = 0; - devp->rf_freq_off = 0; - devp->rssi = 0; - devp->ant0rssi = 0; - devp->ant1rssi = 0; - devp->bgndnoise = 0; - -#if AX5043_USE_SPI -#if AX5043_SHARED_SPI - spiAcquireBus(config->spip); -#endif /* AX5043_SHARED_SPI */ - - /* Start the SPI interface for the device */ - spiStart(config->spip, config->spicfg); - -#if AX5043_SHARED_SPI - spiReleaseBus(config->spip); -#endif /* AX5043_SHARED_SPI */ -#endif /* AX5043_USE_SPI */ - - /* Reset device into POWERDOWN state */ - devp->status = ax5043Reset(devp); - if (devp->error != AX5043_ERR_NOERROR) { - return; - } - - /* Register interrupt handler for device and start worker */ - if (devp->irq_worker == NULL) { - devp->irq_worker = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(0x400), "ax5043_irq_worker", HIGHPRIO, irq_worker, devp); - palSetLineCallback(config->irq, ax5043IRQHandler, devp); - palEnableLineEvent(config->irq, PAL_EVENT_MODE_RISING_EDGE); - } - - /* Transition to ready state */ - devp->state = AX5043_READY; - - /* Apply initial profile provided by user */ - if (config->profile) { - ax5043SetProfile(devp, config->profile); - } - -} - -/** - * @brief Deactivates the AX5043 Radio Driver. - * - * @param[in] devp Pointer to the @p AX5043Driver object - * - * @api - */ -void ax5043Stop(AX5043Driver *devp) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), - "ax5043Stop(), invalid state"); - - if (devp->state != AX5043_STOP) { - /* Power down device */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_POWERDOWN); - - /* Disable the interrupt handler and worker thread */ - palDisableLineEvent(devp->config->irq); - palSetLineCallback(devp->config->irq, NULL, NULL); - chThdTerminate(devp->irq_worker); - chEvtSignal(devp->irq_worker, AX5043_EVENT_TERMINATE); - chThdWait(devp->irq_worker); - devp->irq_worker = NULL; - -#if AX5043_USE_SPI -#if AX5043_SHARED_SPI - spiAcquireBus(devp->config->spip); - spiStart(devp->config->spip, devp->config->spicfg); -#endif /* AX5043_SHARED_SPI */ - - /* Stop the SPI interface for the device */ - spiStop(devp->config->spip); - -#if AX5043_SHARED_SPI - spiReleaseBus(devp->config->spip); -#endif /* AX5043_SHARED_SPI */ -#endif /* AX5043_USE_SPI */ - } - - /* Transition to stop state */ - devp->state = AX5043_STOP; -} - -/** - * @brief Puts AX5043 into idle mode. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @api - */ -void ax5043Idle(AX5043Driver *devp) { - osalDbgCheck(devp != NULL); - osalDbgAssert(((devp->state == AX5043_READY) || - (devp->state == AX5043_RX) || - (devp->state == AX5043_WOR) || - (devp->state == AX5043_TX)), "ax5043Idle(), invalid state"); - - if (devp->state != AX5043_READY) { - devp->error = AX5043_ERR_NOERROR; - - if (devp->rx_worker) { - chThdTerminate(devp->rx_worker); - chEvtSignal(devp->rx_worker, AX5043_EVENT_TERMINATE); - chThdWait(devp->rx_worker); - devp->rx_worker = NULL; - } - - ax5043SetPWRMode(devp, AX5043_PWRMODE_POWERDOWN); - - devp->state = AX5043_READY; - } -} - -/** - * @brief Puts AX5043 into receive or wake-on-radio mode. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] chan_b Use channel B if true. - * @param[in] wor Enable Wake-On-Radio mode. - * - * @api - */ -void ax5043RX(AX5043Driver *devp, bool chan_b, bool wor) { - osalDbgCheck(devp != NULL); - osalDbgAssert(((devp->state == AX5043_READY) || - (devp->state == AX5043_RX) || - (devp->state == AX5043_WOR) || - (devp->state == AX5043_TX)), "ax5043RX(), invalid state"); - - bool cur_chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - - if ((!wor && devp->state != AX5043_RX) || (wor && devp->state != AX5043_WOR) || chan_b != cur_chan) { - devp->error = AX5043_ERR_NOERROR; - - /* Enter idle state first */ - ax5043Idle(devp); - - /* Set the channel */ - uint32_t freq; - uint8_t pllloop = ax5043ReadU8(devp, AX5043_REG_PLLLOOP); - if (chan_b) { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQB), devp->config->xtal_freq); - pllloop |= AX5043_PLLLOOP_FREQSEL; - } else { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQA), devp->config->xtal_freq); - pllloop &= ~AX5043_PLLLOOP_FREQSEL; - } - ax5043WriteU8(devp, AX5043_REG_PLLLOOP, pllloop); - ax5043SetRFDIV(devp, freq); - - /* Activate synthesizer to lock PLL */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_RX_SYNTH); - chThdSleepMicroseconds(1); - if (!(ax5043GetStatus(devp) & AX5043_STATUS_PLL_LOCK)) { - ax5043SetPWRMode(devp, AX5043_PWRMODE_POWERDOWN); - devp->error = AX5043_ERR_LOCKLOST; - return; - } - /* Clear FIFO and set threshold */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_CLEAR_FIFODAT); - ax5043WriteU16(devp, AX5043_REG_FIFOTHRESH, 0); - - /* Activate RX or WOR */ - if (wor) { - ax5043SetPWRMode(devp, AX5043_PWRMODE_RX_WOR); - devp->state = AX5043_WOR; - } else { - ax5043SetPWRMode(devp, AX5043_PWRMODE_RX_FULL); - devp->state = AX5043_RX; - } - - /* Start the FIFO worker */ - devp->rx_worker = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(0x400), "ax5043_rx_worker", HIGHPRIO-1, rx_worker, devp); - } -} - -/** - * @brief Puts AX5043 into transmit mode and transmits a packet. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] buf Transmit buffer. - * @param[in] len Initial length provided in the buffer. - * @param[in] total_len Total length of data to be transmitted. - * @param[in] tx_cb Optional transmit buffer fill callback. - * @param[in] tx_cb_arg Optional transmit buffer fill callback argument. - * @param[in] chan_b Use channel B if true. - * - * @api - */ -void ax5043TX(AX5043Driver *devp, const ax5043_profile_t *profile, const void *buf, size_t len, size_t total_len, ax5043_tx_cb_t tx_cb, void *tx_cb_arg, bool chan_b) { - const ax5043_profile_t *prev_profile; - ax5043_state_t prev_state; - bool prev_chan; - - osalDbgCheck(devp != NULL && buf != NULL); - osalDbgAssert(((devp->state == AX5043_READY) || - (devp->state == AX5043_RX) || - (devp->state == AX5043_WOR) || - (devp->state == AX5043_TX)), "ax5043TX(), invalid state"); - osalDbgAssert(total_len != 0, "ax5043TX(), invalid total length"); - osalDbgAssert(tx_cb != NULL || len == total_len, - "ax5043TX(), no callback when len != total_len"); - - chMtxLock(&devp->tx_lock); - devp->error = AX5043_ERR_NOERROR; - - /* Record previous state and enter idle state */ - prev_state = devp->state; - prev_chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - ax5043Idle(devp); - - /* Set TX profile */ - if (profile != NULL) { - prev_profile = ax5043GetProfile(devp); - ax5043SetProfile(devp, profile); - } - - /* Set Frequency Selection */ - uint32_t freq; - uint8_t pllloop = ax5043ReadU8(devp, AX5043_REG_PLLLOOP); - if (chan_b) { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQB), devp->config->xtal_freq); - pllloop |= AX5043_PLLLOOP_FREQSEL; - } else { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQA), devp->config->xtal_freq); - pllloop &= ~AX5043_PLLLOOP_FREQSEL; - } - ax5043WriteU8(devp, AX5043_REG_PLLLOOP, pllloop); - ax5043SetRFDIV(devp, freq); - - /* Activate synthesizer to lock PLL */ - /* TODO: Can we base this on an interrupt instead of a delay? */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_SYNTH); - chThdSleepMicroseconds(1); - if (!(ax5043GetStatus(devp) & AX5043_STATUS_PLL_LOCK)) { - ax5043SetPWRMode(devp, AX5043_PWRMODE_POWERDOWN); - devp->error = AX5043_ERR_LOCKLOST; - return; - } - /* Clear FIFO */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_CLEAR_FIFODAT); - - /* Activate TX */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_FULL); - devp->state = AX5043_TX; - - /* Write preamble if provided */ - if (devp->preamble) { - ax5043WriteU16(devp, AX5043_REG_FIFOTHRESH, devp->preamble_len); - ax5043WaitIRQ(devp, AX5043_IRQ_FIFOTHRFREE, TIME_INFINITE); - - /* Write preamble to FIFO */ - ax5043Exchange(devp, AX5043_REG_FIFODATA, true, devp->preamble, NULL, devp->preamble_len); - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_COMMIT); - } - - size_t transferred = 0; - size_t offset = 0; - ax5043WriteU16(devp, AX5043_REG_FIFOTHRESH, AX5043_FIFO_WRITE_LEN); - while (transferred < total_len) { - ax5043_chunk_data_tx_t data; - size_t write_len; - - /* Refill buffer if needed */ - if (len == 0 && tx_cb) { - len = tx_cb(tx_cb_arg); - offset = 0; - osalDbgAssert(len != 0, - "ax5043TX(), callback returned zero length"); - osalDbgAssert(transferred + len <= total_len, - "ax5043TX(), callback returned length exceeding total length"); - } - - /* Determine length of data chunk write */ - write_len = AX5043_FIFO_WRITE_LEN - sizeof(data); - if (len < write_len) { - write_len = len; - } - - /* Prepare chunk */ - data.header = AX5043_CHUNKCMD_DATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, AX5043_CHUNKSIZE_VAR); - data.length = write_len + 1; - data.flags = 0; - if (transferred == 0) { - data.flags |= AX5043_CHUNK_DATATX_PKTSTART; - } - if (transferred + write_len == total_len) { - data.flags |= AX5043_CHUNK_DATATX_PKTEND; - } - - /* Once there's enough free space, write the data chunk and commit */ - ax5043WaitIRQ(devp, AX5043_IRQ_FIFOTHRFREE, TIME_INFINITE); - ax5043Exchange(devp, AX5043_REG_FIFODATA, true, (uint8_t*)(&data), NULL, sizeof(data)); - ax5043Exchange(devp, AX5043_REG_FIFODATA, true, &((uint8_t*)buf)[offset], NULL, write_len); - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_COMMIT); - - len -= write_len; - offset += write_len; - transferred += write_len; - } - - /* Write postamble if provided */ - if (devp->postamble) { - ax5043WriteU16(devp, AX5043_REG_FIFOTHRESH, devp->postamble_len); - ax5043WaitIRQ(devp, AX5043_IRQ_FIFOTHRFREE, TIME_INFINITE); - - /* Write postamble to FIFO */ - ax5043Exchange(devp, AX5043_REG_FIFODATA, true, devp->postamble, NULL, devp->postamble_len); - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_COMMIT); - } - - ax5043WriteU16(devp, AX5043_REG_RADIOEVENTMASK, AX5043_RADIOEVENT_DONE); - ax5043WaitIRQ(devp, AX5043_IRQ_RADIOCTRL, TIME_INFINITE); - ax5043WriteU16(devp, AX5043_REG_RADIOEVENTMASK, 0x0000U); - ax5043ReadU16(devp, AX5043_REG_RADIOEVENTREQ); - - /* Return to original state */ - if (profile != NULL) { - ax5043SetProfile(devp, prev_profile); - } - switch (prev_state) { - case AX5043_RX: - ax5043RX(devp, prev_chan, false); - break; - case AX5043_WOR: - ax5043RX(devp, prev_chan, true); - break; - case AX5043_READY: - default: - ax5043Idle(devp); - } - chMtxUnlock(&devp->tx_lock); -} - -/** - * @brief Puts AX5043 into raw transmit mode. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] buf Transmit FIFO buffer. - * @param[in] len Initial length provided in the buffer. - * @param[in] total_len Total length of data to be transmitted. - * @param[in] tx_cb Optional transmit buffer fill callback. - * @param[in] tx_cb_arg Optional transmit buffer fill callback argument. - * @param[in] chan_b Use channel B if true. - * - * @api - */ -void ax5043TXRaw(AX5043Driver *devp, const ax5043_profile_t *profile, const void *buf, size_t len, size_t total_len, ax5043_tx_cb_t tx_cb, void *tx_cb_arg, bool chan_b) { - const ax5043_profile_t *prev_profile; - ax5043_state_t prev_state; - bool prev_chan; - - osalDbgCheck(devp != NULL && buf != NULL); - osalDbgAssert(((devp->state == AX5043_READY) || - (devp->state == AX5043_RX) || - (devp->state == AX5043_WOR) || - (devp->state == AX5043_TX)), "ax5043TXRaw(), invalid state"); - osalDbgAssert(total_len != 0, "ax5043TXRaw(), invalid total length"); - osalDbgAssert(tx_cb != NULL || len == total_len, - "ax5043TXRaw(), no callback when len != total_len"); - - chMtxLock(&devp->tx_lock); - devp->error = AX5043_ERR_NOERROR; - - /* Record previous state and enter idle state */ - prev_state = devp->state; - prev_chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - ax5043Idle(devp); - - /* Set TX profile */ - if (profile != NULL) { - prev_profile = ax5043GetProfile(devp); - ax5043SetProfile(devp, profile); - } - - /* Set Frequency Selection */ - uint32_t freq; - uint8_t pllloop = ax5043ReadU8(devp, AX5043_REG_PLLLOOP); - if (chan_b) { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQB), devp->config->xtal_freq); - pllloop |= AX5043_PLLLOOP_FREQSEL; - } else { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, AX5043_REG_FREQA), devp->config->xtal_freq); - pllloop &= ~AX5043_PLLLOOP_FREQSEL; - } - ax5043WriteU8(devp, AX5043_REG_PLLLOOP, pllloop); - ax5043SetRFDIV(devp, freq); - - /* Activate synthesizer to lock PLL */ - /* TODO: Can we base this on an interrupt instead of a delay? */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_SYNTH); - chThdSleepMicroseconds(1); - if (!(ax5043GetStatus(devp) & AX5043_STATUS_PLL_LOCK)) { - ax5043SetPWRMode(devp, AX5043_PWRMODE_POWERDOWN); - devp->error = AX5043_ERR_LOCKLOST; - return; - } - /* Clear FIFO */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_CLEAR_FIFODAT); - - /* Activate TX */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_FULL); - devp->state = AX5043_TX; - - size_t transferred = 0; - size_t offset = 0; - ax5043WriteU16(devp, AX5043_REG_FIFOTHRESH, AX5043_FIFO_WRITE_LEN); - while (transferred < total_len) { - size_t write_len; - - /* Refill buffer if needed */ - if (len == 0 && tx_cb) { - len = tx_cb(tx_cb_arg); - offset = 0; - osalDbgAssert(len != 0, - "ax5043TX(), callback returned zero length"); - osalDbgAssert(transferred + len <= total_len, - "ax5043TX(), callback returned length exceeding total length"); - } - - /* Determine length of data chunk write */ - write_len = (len < AX5043_FIFO_WRITE_LEN ? len : AX5043_FIFO_WRITE_LEN); - - /* Once there's enough free space, write the data chunk and commit */ - ax5043WaitIRQ(devp, AX5043_IRQ_FIFOTHRFREE, TIME_INFINITE); - ax5043Exchange(devp, AX5043_REG_FIFODATA, true, &((uint8_t*)buf)[offset], NULL, write_len); - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_COMMIT); - - len -= write_len; - offset += write_len; - transferred += write_len; - } - - ax5043WriteU16(devp, AX5043_REG_RADIOEVENTMASK, AX5043_RADIOEVENT_DONE); - ax5043WaitIRQ(devp, AX5043_IRQ_RADIOCTRL, TIME_INFINITE); - ax5043WriteU16(devp, AX5043_REG_RADIOEVENTMASK, 0x0000U); - ax5043ReadU16(devp, AX5043_REG_RADIOEVENTREQ); - - /* Return to original state */ - if (profile != NULL) { - ax5043SetProfile(devp, prev_profile); - } - switch (prev_state) { - case AX5043_RX: - ax5043RX(devp, prev_chan, false); - break; - case AX5043_WOR: - ax5043RX(devp, prev_chan, true); - break; - case AX5043_READY: - default: - ax5043Idle(devp); - } - chMtxUnlock(&devp->tx_lock); -} - -/** - * @brief Sets register values from a profile. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] profile Pointer to the @p ax5043_profile_t list of register values. - * - * @api - */ -void ax5043SetProfile(AX5043Driver *devp, const ax5043_profile_t *profile) { - ax5043_state_t prev_state; - bool prev_chan; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043SetProfile(), invalid state"); - - devp->profile = profile; - - /* Record previous state and enter idle state */ - prev_state = devp->state; - prev_chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - ax5043Idle(devp); - - /* Set all profile values */ - for (const ax5043_profile_t *entry = profile; entry->reg; entry++) { - switch (entry->len) { - case 1: - ax5043WriteU8(devp, entry->reg, entry->val); - break; - case 2: - ax5043WriteU16(devp, entry->reg, entry->val); - break; - case 3: - ax5043WriteU24(devp, entry->reg, entry->val); - break; - case 4: - ax5043WriteU32(devp, entry->reg, entry->val); - break; - default: - break; - } - } - - /* Re-range frequencies in case they changed */ - ax5043SetFreq(devp, 0, devp->vcorb, true); - ax5043SetFreq(devp, 0, devp->vcora, false); - - /* Return to original state */ - switch (prev_state) { - case AX5043_RX: - ax5043RX(devp, prev_chan, false); - break; - case AX5043_WOR: - ax5043RX(devp, prev_chan, true); - break; - case AX5043_READY: - default: - ax5043Idle(devp); - } -} - -/** - * @brief Gets the currently active profile. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return Pointer to the current profile. - * @api - */ -const ax5043_profile_t *ax5043GetProfile(AX5043Driver *devp) { - return devp->profile; -} - -/** - * @brief Sets Carrier Frequency on an AX5043 device. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] freq Carrier frequency in Hz. If 0, ranges existing reg value. - * @param[in] vcor VCO Range value. Set to 0 if unknown. - * @param[in] chan_b Set channel B frequency if true, channel A otherwise. - * - * @return Corrected VCOR for given frequency. - * @api - */ -uint8_t ax5043SetFreq(AX5043Driver *devp, uint32_t freq, uint8_t vcor, bool chan_b) { - ax5043_state_t prev_state; - bool prev_chan; - - uint16_t freq_reg = (chan_b ? AX5043_REG_FREQB : AX5043_REG_FREQA); - uint16_t rng_reg = (chan_b ? AX5043_REG_PLLRANGINGB : AX5043_REG_PLLRANGINGA); - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043SetFreq(), invalid state"); - osalDbgAssert((freq >= AX5043_RFDIV_DIV1_MIN && freq <= AX5043_RFDIV_DIV1_MAX) || - (freq >= AX5043_RFDIV_DIV2_MIN && freq <= AX5043_RFDIV_DIV2_MAX) || - freq == 0, "ax5043SetFreq(), frequency out of bounds"); - - devp->error = AX5043_ERR_NOERROR; - - /* Record previous state and enter idle state */ - prev_state = devp->state; - prev_chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - ax5043Idle(devp); - - /* If no VCOR specified, default to 8 */ - if (vcor == 0) { - vcor = 8; - } - - /* Enter Standby mode */ - ax5043SetPWRMode(devp, AX5043_PWRMODE_STANDBY); - - /* Wait for XTAL */ - ax5043WaitIRQ(devp, AX5043_IRQ_XTALREADY, TIME_INFINITE); - - /* Set frequencies - * We first find the GCD of the two frequencies in order to reduce them - * as much as possible before doing the calculations. - * NOTE: The programming manual recommends always setting bit 0 - * - * REG = f_carrier * 2^24 / f_xtal + 1/2 - * = (f_carrier * 2^25 + f_xtal) / (f_xtal * 2) - */ - - /* Set Frequency Selection */ - uint8_t pllloop = ax5043ReadU8(devp, AX5043_REG_PLLLOOP); - if (chan_b) { - pllloop |= AX5043_PLLLOOP_FREQSEL; - } else { - pllloop &= ~AX5043_PLLLOOP_FREQSEL; - } - ax5043WriteU8(devp, AX5043_REG_PLLLOOP, pllloop); - - /* Set the frequency and RFDIV if needed, and initiate ranging */ - if (freq) { - ax5043WriteU32(devp, freq_reg, AX5043_FREQ_TO_REG(freq, devp->config->xtal_freq)); - } else { - freq = AX5043_REG_TO_FREQ(ax5043ReadU32(devp, freq_reg), devp->config->xtal_freq); - } - ax5043SetRFDIV(devp, freq); - ax5043WriteU8(devp, rng_reg, _VAL2FLD(AX5043_PLLRANGING_VCOR, vcor) | AX5043_PLLRANGING_RNGSTART); - ax5043WaitIRQ(devp, AX5043_IRQ_PLLRNGDONE, TIME_INFINITE); - vcor = ax5043ReadU8(devp, rng_reg); - if (vcor & AX5043_PLLRANGING_RNGERR) { - devp->error = AX5043_ERR_RANGING; - } - vcor = _FLD2VAL(AX5043_PLLRANGING_VCOR, vcor); - if (chan_b) { - devp->vcorb = vcor; - } else { - devp->vcora = vcor; - } - - /* Return to original state */ - switch (prev_state) { - case AX5043_RX: - ax5043RX(devp, prev_chan, false); - break; - case AX5043_WOR: - ax5043RX(devp, prev_chan, true); - break; - case AX5043_READY: - default: - ax5043Idle(devp); - } - - return vcor; -} - -/** - * @brief Gets the current frequency. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return The frequency in Hz. - * @api - */ -uint32_t ax5043GetFreq(AX5043Driver *devp) { - bool chan = ax5043ReadU8(devp, AX5043_REG_PLLLOOP) & AX5043_PLLLOOP_FREQSEL; - uint16_t freq_reg = (chan ? AX5043_REG_FREQB : AX5043_REG_FREQA); - - return AX5043_REG_TO_FREQ(ax5043ReadU32(devp, freq_reg), devp->config->xtal_freq); -} - -/** - * @brief Sets Preamble pointer and length for AX5043 transmission operations. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] preamble Pointer to the preamble buffer. - * @param[in] len Length of the buffer. - * - * @api - */ -void ax5043SetPreamble(AX5043Driver *devp, const void *preamble, size_t len) { - osalDbgCheck(devp != NULL); - osalDbgAssert(len <= AX5043_FIFO_SIZE, "ax5043SetPreamble(), Preamble length exceeds max FIFO size"); - - devp->preamble = preamble; - devp->preamble_len = len; -} - -/** - * @brief Gets the currently active preamble. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return Pointer to the current preamble. - * @api - */ -const void *ax5043GetPreamble(AX5043Driver *devp) { - return devp->preamble; -} - -/** - * @brief Sets Postamble pointer and length for AX5043 transmission operations. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] postamble Pointer to the postamble buffer. - * @param[in] len Length of the buffer. - * - * @api - */ -void ax5043SetPostamble(AX5043Driver *devp, const void *postamble, size_t len) { - osalDbgCheck(devp != NULL); - osalDbgAssert(len <= AX5043_FIFO_SIZE, "ax5043SetPostamble(), Postamble length exceeds max FIFO size"); - - devp->postamble = postamble; - devp->postamble_len = len; -} - -/** - * @brief Gets the currently active postamble. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return Pointer to the current postamble. - * @api - */ -const void *ax5043GetPostamble(AX5043Driver *devp) { - return devp->postamble; -} - -/** - * @brief Perform a long (16-bit address) exchange with an AX5043 device. - * @note Can be called with NULL values for txbuf and/or rxbuf. - * @note A maximum of 256 bytes can be transferred at a time using this function. - * - * @param[in] devp Pointer to the @p AX5043Driver object - * @param[in] reg Register address - * @param[in] write Indicates Read/Write bit - * @param[in] txbuf Buffer to send data from - * @param[out] rxbuf Buffer to return data in - * @param[in] n Number of bytes to exchange - * - * @return AX5043 status bits - * @api - */ -ax5043_status_t ax5043Exchange(AX5043Driver *devp, uint16_t reg, bool write, const void *txbuf, void *rxbuf, size_t n) { - SPIDriver *spip = NULL; - ax5043_status_t status = 0; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043Exchange(), invalid state"); - -#if AX5043_USE_SPI - spip = devp->config->spip; -#if AX5043_SHARED_SPI - spiAcquireBus(spip); - spiStart(spip, devp->config->spicfg); -#endif /* AX5043_SHARED_SPI */ - - spiSelect(spip); - while (!palReadLine(devp->config->miso)); - status = ax5043SPIExchange(spip, reg, write, txbuf, rxbuf, n); - spiUnselect(spip); - -#if AX5043_SHARED_SPI - spiReleaseBus(spip); -#endif /* AX5043_SHARED_SPI */ -#endif /* AX5043_USE_SPI */ - - return status; -} - -/** - * @brief Gets the status of the AX5043 device. - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * - * @return AX5043 status bits - * @api - */ -ax5043_status_t ax5043GetStatus(AX5043Driver *devp) { - SPIDriver *spip = NULL; - ax5043_status_t status = 0; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043GetStatus(), invalid state"); - -#if AX5043_USE_SPI - spip = devp->config->spip; -#if AX5043_SHARED_SPI - spiAcquireBus(spip); - spiStart(spip, devp->config->spicfg); -#endif /* AX5043_SHARED_SPI */ - - spiSelect(spip); - while (!palReadLine(devp->config->miso)); - spiReceive(spip, 2, &status); - spiUnselect(spip); - -#if AX5043_SHARED_SPI - spiReleaseBus(spip); -#endif /* AX5043_SHARED_SPI */ -#endif /* AX5043_USE_SPI */ - - return __REVSH(status); -} - -/** - * @brief Read a uint8_t value from a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * - * @return The value in the register - * @api - */ -uint8_t ax5043ReadU8(AX5043Driver *devp, uint16_t reg) { - uint8_t value; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043ReadU8(), invalid state"); - - ax5043Exchange(devp, reg, false, NULL, &value, 1); - - return value; -} - -/** - * @brief Read a uint16_t value from a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * - * @return The value in the register - * @api - */ -uint16_t ax5043ReadU16(AX5043Driver *devp, uint16_t reg) { - uint16_t value; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043ReadU16(), invalid state"); - - ax5043Exchange(devp, reg, false, NULL, (uint8_t*)&value, 2); - - return __REVSH(value); -} - -/** - * @brief Read a uint32_t value from a 24-bit register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * - * @return The value in the register - * @api - */ -uint32_t ax5043ReadU24(AX5043Driver *devp, uint16_t reg) { - uint32_t value; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043ReadU32(), invalid state"); - - ax5043Exchange(devp, reg, false, NULL, (uint8_t*)&value, 3); - - return __REV(value << 8); -} - -/** - * @brief Read a uint32_t value from a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * - * @return The value in the register - * @api - */ -uint32_t ax5043ReadU32(AX5043Driver *devp, uint16_t reg) { - uint32_t value; - - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043ReadU32(), invalid state"); - - ax5043Exchange(devp, reg, false, NULL, (uint8_t*)&value, 4); - - return __REV(value); -} - -/** - * @brief Write a uint8_t value to a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * @param[in] value Register value - * - * @api - */ -void ax5043WriteU8(AX5043Driver *devp, uint16_t reg, uint8_t value) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043WriteU8(), invalid state"); - - ax5043Exchange(devp, reg, true, &value, NULL, 1); -} - -/** - * @brief Write a uint16_t value to a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * @param[in] value Register value - * - * @api - */ -void ax5043WriteU16(AX5043Driver *devp, uint16_t reg, uint16_t value) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043WriteU8(), invalid state"); - - value = __REVSH(value); - ax5043Exchange(devp, reg, true, (uint8_t*)&value, NULL, 2); -} - -/** - * @brief Write a uint32_t value to a 24-bit register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * @param[in] value Register value - * - * @api - */ -void ax5043WriteU24(AX5043Driver *devp, uint16_t reg, uint32_t value) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043WriteU8(), invalid state"); - - value = __REV(value) >> 8; - ax5043Exchange(devp, reg, true, (uint8_t*)&value, NULL, 3); -} - -/** - * @brief Write a uint32_t value to a register - * - * @param[in] devp Pointer to the @p AX5043Driver object. - * @param[in] reg Register address - * @param[in] value Register value - * - * @api - */ -void ax5043WriteU32(AX5043Driver *devp, uint16_t reg, uint32_t value) { - osalDbgCheck(devp != NULL && devp->config != NULL); - osalDbgAssert((devp->state != AX5043_UNINIT), "ax5043WriteU32(), invalid state"); - - value = __REV(value); - ax5043Exchange(devp, reg, true, (uint8_t*)&value, NULL, 4); -} - -/** @} */ diff --git a/common/ax5043.mk b/common/ax5043.mk deleted file mode 100644 index ee385817..00000000 --- a/common/ax5043.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the AX5043 device files. -AX5043SRC := $(PROJ_SRC)/ax5043.c - -# Required include directories -AX5043INC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(AX5043SRC) -ALLINC += $(AX5043INC) diff --git a/common/bootloader.mk b/common/bootloader.mk deleted file mode 100644 index 17ca5faa..00000000 --- a/common/bootloader.mk +++ /dev/null @@ -1,7 +0,0 @@ -BOOTLOADERINC = $(PROJ_SRC)/include - -BOOTLOADERSRC = $(PROJ_SRC)/can_bootloader.c - -# Shared variables. -ALLCSRC += $(BOOTLOADERSRC) -ALLINC += $(BOOTLOADERINC) diff --git a/common/can_bootloader.c b/common/can_bootloader.c deleted file mode 100644 index 9561a802..00000000 --- a/common/can_bootloader.c +++ /dev/null @@ -1,942 +0,0 @@ -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "can_bootloader.h" -#include "string.h" -#include "oresat_f0.h" - -#define CAN_MAILBOX_TO_USE 2 - -#define DEFAULT_RETRY_LIMIT 3 - - -#define M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE 64 -uint8_t m0_firmware_temp_buffer[M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE]; - -#define STM32_BOOTLOADER_TEST_CODE 0 - -#if CAN_BOOTLOADER_ENABLE_SERIAL_DEBUG -#define can_bl_api_print_rx_frame(a, b, c, d) can_api_print_rx_frame(a, b, c, d) -#define can_bl_api_print_tx_frame(a, b, c, d) can_api_print_tx_frame(a, b, c, d) -#else -#define can_bl_api_print_rx_frame(a, b, c, d) -#define can_bl_api_print_tx_frame(a, b, c, d) -#endif - - -#define ORESAT_F0_FLASH_START_ADDRESS 0x08000000 -#define ORESAT_F0_FIRMWARE_CRC_ADDRESS 0x0800A7F4 -#define ORESAT_F0_FIRMWARE_CODE_ADDRESS 0x0800A804 - -/** - * Used to fully initialize a can_bootloader_config_t structure. - * - * @param *canp Pointer to can driver object - * @param *chp Pointer to debug output serial stream - * @param low_cpu_id Use for matching to the lower order 32 bits of the unique CPU id of a given M0 node. - * @param stm32_bootloader_mode Flag to indicate if the target is at stm32 CAN bootloader rather then an ORESAT bootloader (stm32 bootloader not currently supported) - * - * @return true on success, false otherwise. - */ -bool can_api_init_can_bootloader_config_t(can_bootloader_config_t *can_bl_config, CANDriver *canp, BaseSequentialStream *chp, const uint32_t low_cpu_id, const bool stm32_bootloader_mode, void *read_function_arg0) { - if (can_bl_config == NULL) { - return (false); - } - memset(can_bl_config, 0, sizeof(*can_bl_config)); - - can_bl_config->canp = canp; - can_bl_config->chp = chp; - can_bl_config->low_cpu_id = low_cpu_id; - can_bl_config->stm32_bootloader_mode = stm32_bootloader_mode; - can_bl_config->read_function_arg0 = read_function_arg0; - - return (true); -} - -/** - * Helper functino to - */ -void print_can_bootloader_config_t(BaseSequentialStream *chp, can_bootloader_config_t *can_bl_config) { - chprintf(chp, "can_bootloader_config_t:\r\n"); - chprintf(chp, " low_cpu_id: 0x%X\r\n", can_bl_config->low_cpu_id); - chprintf(chp, " stm32_bootloader_mode: %u\r\n", can_bl_config->stm32_bootloader_mode); - chprintf(chp, " read_fail_count: %u\r\n", can_bl_config->read_fail_count); - chprintf(chp, " write_fail_count: %u\r\n", can_bl_config->write_fail_count); - chprintf(chp, " erase_fail_count: %u\r\n", can_bl_config->erase_fail_count); - chprintf(chp, " verify_fail_count: %u\r\n", can_bl_config->verify_fail_count); - chprintf(chp, " ack_count: %u\r\n", can_bl_config->ack_count); - chprintf(chp, " nack_count: %u\r\n", can_bl_config->nack_count); - chprintf(chp, " unknown_count: %u\r\n", can_bl_config->unknown_count); - chprintf(chp, " can_tx_fail_count: %u\r\n", can_bl_config->can_tx_fail_count); - chprintf(chp, " initiate_connection_count: %u\r\n", can_bl_config->initiate_connection_count); - chprintf(chp, " connection_verify_fail: %u\r\n", can_bl_config->connection_verify_fail); - chprintf(chp, " update_duration_ms: %u\r\n", can_bl_config->update_duration_ms); -} - -void can_api_print_rx_frame(BaseSequentialStream *chp, CANRxFrame *msg, const char *pre_msg, const char *post_msg) { - chprintf(chp, "RX Frame: %s ", pre_msg); - - chprintf(chp, "SID = 0x%X ", msg->SID); - chprintf(chp, "DLC = %u ", msg->DLC); - chprintf(chp, "RTR = %u ", msg->RTR); - chprintf(chp, "IDE = %u ", msg->IDE); - - chprintf(chp, "[ "); - for(int i = 0; i < msg->DLC; i++ ) { - chprintf(chp, "0x%X ", msg->data8[i]); - } - chprintf(chp, "] "); - - chprintf(chp, "%s", post_msg); - chprintf(chp, "\r\n"); -} - - - - -void can_api_print_tx_frame(BaseSequentialStream *chp, CANTxFrame *msg, const char *pre_msg, const char *post_msg) { - chprintf(chp, "TX Frame: %s ", pre_msg); - - chprintf(chp, "SID = 0x%X ", msg->SID); - chprintf(chp, "DLC = %u ", msg->DLC); - chprintf(chp, "RTR = %u ", msg->RTR); - chprintf(chp, "IDE = %u ", msg->IDE); - - chprintf(chp, "[ "); - for(int i = 0; i < msg->DLC; i++ ) { - chprintf(chp, "0x%X ", msg->data8[i]); - } - chprintf(chp, "] "); - - chprintf(chp, "%s", post_msg); - chprintf(chp, "\r\n"); -} - - -msg_t can_api_receive2(can_bootloader_config_t *can_bl_config, CANRxFrame *msg, const uint32_t timeout_ms, const char *pre_msg, const char *post_msg) { - CANDriver *canp = can_bl_config->canp; - - msg_t r = canReceive(canp, CAN_MAILBOX_TO_USE, msg, TIME_MS2I(timeout_ms)); - if( r == MSG_OK ) { - can_bl_api_print_rx_frame(can_bl_config->chp, msg, pre_msg, post_msg); - } - return(r); -} - -msg_t can_api_receive(can_bootloader_config_t *can_bl_config, CANRxFrame *msg, const uint32_t timeout_ms) { - return(can_api_receive2(can_bl_config, msg, timeout_ms, "", "")); -} - -void can_api_purge_rx_buffer(can_bootloader_config_t *can_bl_config) { - CANRxFrame msg; - uint32_t timeout = 5; - if( can_bl_config->stm32_bootloader_mode ) { - timeout = 50; - } - - for(int i = 0; i < 3; i++ ) { - if( can_api_receive2(can_bl_config, &msg, timeout, "", "PURGED") != MSG_OK ) { - //break; - } - } -} - -msg_t can_api_transmit(can_bootloader_config_t *can_bl_config, CANTxFrame *msg, const uint32_t timeout_ms) { - CANDriver *canp = can_bl_config->canp; - - const msg_t r = canTransmit(canp, CAN_MAILBOX_TO_USE, msg, TIME_MS2I(timeout_ms)); - if( r == MSG_OK ) { - can_bl_api_print_tx_frame(can_bl_config->chp, msg, "", " - SUCCESS"); - } else { - can_bl_api_print_tx_frame(can_bl_config->chp, msg, "", " - FAIL"); - can_bl_config->can_tx_fail_count++; - } - return(r); -} - -#if STM32_BOOTLOADER_TEST_CODE -bool can_bootloader_tx_garbage_frame(can_bootloader_config_t *can_bl_config) { - if( ! can_bl_config->stm32_bootloader_mode ) { - return(true); - } - - CANTxFrame msg; - memset(&msg, 0, sizeof(msg)); - msg.SID = 0x99; - if( can_api_transmit(can_bl_config, &msg, 100) == MSG_OK ) { - return(true); - } - - return(false); -} -#endif - -/** - * Used to put the M0 bootloader or STM32 bootloader into actual bootloader mode such that the device can be flashed. - * - * @return true if the remote device was put into bootloader mode, false otherwise. - */ -bool can_bootloader_initiate(can_bootloader_config_t *can_bl_config, const uint32_t timeout_ms) { - BaseSequentialStream *chp = can_bl_config->chp; - - if( can_bl_config->stm32_bootloader_mode ) { - //Note: The STM32 bootloader expects the CAN peripheral bitrate to be configured to 125kbit. - const uint32_t rx_read_timeout_ms = 50; - const uint32_t max_retrys = timeout_ms / rx_read_timeout_ms; - - for(uint32_t retry_count = 0; retry_count < max_retrys; retry_count++ ) { - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = STM32_BOOTLOADER_CAN_ACK; - tx_msg.DLC = 8; - memset(&tx_msg.data8[0], 0x55, sizeof(tx_msg.data8)); - - msg_t r = can_api_transmit(can_bl_config, &tx_msg, 50); - - if( r == MSG_OK ) { - chprintf(chp, "Sent STM32 CAN bootloader initialization frame...\r\n"); - CANRxFrame msg; - memset(&msg, 0, sizeof(msg)); - r = can_api_receive(can_bl_config, &msg, rx_read_timeout_ms); - - if( r == MSG_OK ) { - chprintf(chp, "Got response from STM32 CAN bootloader...\r\n"); - can_bl_api_print_rx_frame(chp, &msg, "", ""); - if( msg.SID == STM32_BOOTLOADER_CAN_ACK ) { - chprintf(chp, "Successfully put remote STM32 devices into CAN bootloader mode!\r\n"); - //chThdSleepMilliseconds(5000); - return(true); - } - break; - - } else { - chprintf(chp, "No response from STM32 CAN bootloader...\r\n"); - } - - } else { - chprintf(chp, "Failed to send STM32 CAN bootloader initialization frame...\r\n"); - } - } - - } else { - CANRxFrame msg; - memset(&msg, 0, sizeof(msg)); - msg_t r = can_api_receive(can_bl_config, &msg, timeout_ms); - if( r == MSG_OK ) { - if( msg.SID == STM32_BOOTLOADER_CAN_ANNOUNCE && msg.DLC == 8 ) { - - if( msg.data8[0] == 0x01 && msg.data8[1] == 0x02 && msg.data8[2] == 0x03 && msg.data8[3] == 0x04 ) { - const uint32_t remote_low_cpu_id = (msg.data8[4] << 24) | (msg.data8[5] << 16) | (msg.data8[6] << 8) | (msg.data8[7] << 0); - chprintf(chp, "Remote CPU ID Low = 0x%X\r\n", remote_low_cpu_id); - - if( can_bl_config->low_cpu_id == 0 || remote_low_cpu_id == can_bl_config->low_cpu_id ) { - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = BOOTLOADER_EXPECTED_FIRST_FRAME_ID; - tx_msg.DLC = 8; - tx_msg.data8[0] = msg.data8[4]; - tx_msg.data8[1] = msg.data8[5]; - tx_msg.data8[2] = msg.data8[6]; - tx_msg.data8[3] = msg.data8[7]; - tx_msg.data8[4] = 0x01; - tx_msg.data8[5] = 0x02; - tx_msg.data8[6] = 0x03; - tx_msg.data8[7] = 0x04; - - r = can_api_transmit(can_bl_config, &tx_msg, 100); - if( r == MSG_OK ) { - chprintf(chp, "Successfully put remote node into bootloader mode...\r\n"); - can_bl_config->initiate_connection_count++; - return(true); - } - } else { - chprintf(chp, "Remote CPU ID did not match target CPU ID: 0x%X != 0x%X\r\n", can_bl_config->low_cpu_id, remote_low_cpu_id); - } - - } - } - } else { - chprintf(chp, "Failed to receive CAN frame to initiate CAN bootloader on a device...\r\n"); - } - } - return(false); -} - -/** - * Used to wait for an ACK or NACK from the remote bootloader. - * - * @param sid_match The command SID to for which we are expecting to read an ACK for. - * - * @return true if ACK for the given SID was received, false if a NACK or unknown frame was received. - */ -bool can_bootloader_wait_for_ack(can_bootloader_config_t *can_bl_config, const uint32_t sid_match) { - BaseSequentialStream *chp = can_bl_config->chp; - - CANRxFrame rx_msg; - memset(&rx_msg, 0, sizeof(rx_msg)); - - for(uint32_t retry_count = 0; retry_count < 3; retry_count++) { - msg_t r = can_api_receive2(can_bl_config, &rx_msg, 1000, "", "expecting ACK/NACK"); - if( r == MSG_OK ) { - if( rx_msg.SID == sid_match && rx_msg.data8[0] == STM32_BOOTLOADER_CAN_ACK ) { - can_bl_api_print_rx_frame(chp, &rx_msg, "", " - got ACK"); - can_bl_config->ack_count++; - return(true); - } else if( rx_msg.SID == sid_match && rx_msg.data8[0] == STM32_BOOTLOADER_CAN_NACK ) { - can_bl_api_print_rx_frame(chp, &rx_msg, "", " - got NACK"); - can_bl_config->nack_count++; - return(false); - } else { - can_bl_api_print_rx_frame(chp, &rx_msg, "", " - UNKNOWN"); - can_bl_config->unknown_count++; - } - - } else { - chprintf(chp, "Failed to get CAN frame while waiting for ACK/NACK for 0x%X\r\n", sid_match); - } - } - return(false); -} - -#if STM32_BOOTLOADER_TEST_CODE -bool can_bootloader_wait_for_ack_with_garbage(can_bootloader_config_t *can_bl_config, const uint32_t sid_match) { - if( can_bl_config->stm32_bootloader_mode ) { - for(int i = 0; i < 5; i++ ) { - if( can_bootloader_wait_for_ack(can_bl_config, sid_match) ) { - return(true); - } - can_bootloader_tx_garbage_frame(can_bl_config); - } - } else { - return(can_bootloader_wait_for_ack_with_garbage(can_bl_config, sid_match)); - } - - return(false); -} -#endif - -/** - * Reads data from a given address from the remote device that is in bootloader mode. - * - * @param memory_addres The base memory address to start reading data from - * @param num_bytes_to_read The number of bytes to read. - * @param *dest_buffer The destination buffer into which to store the data. - * @param dest_buffer_length The maximum length of the destination buffer. - * - * @return true If data was successfully read, false otherwise. - */ -bool can_bootloader_read_data(can_bootloader_config_t *can_bl_config, const uint32_t memory_address, const uint32_t num_bytes_to_read, uint8_t *dest_buffer, const uint32_t dest_buffer_length) { - BaseSequentialStream *chp = can_bl_config->chp; - - //can_api_purge_rx_buffer(canp, chp); - chprintf(chp, "can_bootloader_read_data(0x%X, %u)\r\n", memory_address, num_bytes_to_read); - - msg_t r = 0; - - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY; - tx_msg.DLC = 5; - tx_msg.data8[0] = (memory_address >> 24) & 0xFF; - tx_msg.data8[1] = (memory_address >> 16) & 0xFF; - tx_msg.data8[2] = (memory_address >> 8) & 0xFF; - tx_msg.data8[3] = (memory_address >> 0) & 0xFF; - tx_msg.data8[4] = num_bytes_to_read - 1; - - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY) ) { - return(false); - } - - uint32_t expected_frame_count = num_bytes_to_read / 8; - if( num_bytes_to_read % 8 > 0 ) { - expected_frame_count++; - } - - //chprintf(chp, "expected_frame_count = %u\r\n", expected_frame_count); - - uint32_t dest_buffer_index = 0; - for(uint32_t i = 0; i < expected_frame_count; i++) { - CANRxFrame rx_msg; - memset(&rx_msg, 0, sizeof(rx_msg)); - msg_t r = can_api_receive(can_bl_config, &rx_msg, 1000); - if( r == MSG_OK ) { - for(uint32_t j = 0; j < rx_msg.DLC && dest_buffer_index < dest_buffer_length && j < sizeof(rx_msg.data8); j++ ) { - dest_buffer[dest_buffer_index] = rx_msg.data8[j]; - dest_buffer_index++; - } - } - } - - //chprintf(chp, "final dest_buffer_index = %u\r\n", dest_buffer_index); - - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY) ) { - return(false); - } - -#if CAN_BOOTLOADER_ENABLE_SERIAL_DEBUG - chprintf(chp, "Successfully read memory from remote device...\r\n"); - for(uint32_t i = 0; i < dest_buffer_index; i++ ) { - chprintf(chp, " 0x%X", dest_buffer[i]); - } - chprintf(chp, "\r\n\r\n"); -#endif - - return(true); -} - -/** - * Erases a given page (sometimes also refered to as sector, depending on the device type) of flash on the remote device. - * - * @page_number The page number of flash to be erased. - * - * @return true on success, false otherwise. - */ -bool can_bootloader_erase_page(can_bootloader_config_t *can_bl_config, const uint32_t page_number) { - BaseSequentialStream *chp = can_bl_config->chp; - -#if CAN_BOOTLOADER_ENABLE_SERIAL_DEBUG - chprintf(chp, "\r\ncan_bootloader_erase_page(%u)\r\n", page_number); -#endif - msg_t r = 0; - - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = ORESAT_BOOTLOADER_CAN_COMMAND_ERASE; - tx_msg.DLC = 2; - tx_msg.data8[0] = 0; - tx_msg.data8[1] = page_number; - - - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_ERASE) ) { - return(false); - } - - - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_ERASE) ) { - return(false); - } - - chprintf(chp, "Successfully erased page %u on remote device\r\n", page_number); - return(true); -} - -/** - * TODO document this - * - * @return true on success, false otherwise. - */ -bool can_bootloader_set_opt_data(can_bootloader_config_t *can_bl_config, const uint8_t data_0_value, const uint8_t data_1_value) { -#if CAN_BOOTLOADER_ENABLE_SERIAL_DEBUG - chprintf(can_bl_config->chp, "can_bootloader_set_opt_data(0x%X, 0x%X)\r\n", data_0_value, data_1_value); -#endif - msg_t r = 0; - - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA; - tx_msg.DLC = 2; - tx_msg.data8[0] = data_0_value; - tx_msg.data8[1] = data_1_value; - - - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA) ) { - return(false); - } - - - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA) ) { - return(false); - } - - chprintf(can_bl_config->chp, "Successfully set data 0 and data 1 on remote node to 0x%X and 0x%X\r\n", data_0_value, data_1_value); - return(true); -} - - - -/** - * Writes to flash memory on the remote device. - * - * @param memory_address Base memory address to start writing to. - * @param *src_buffer The data to be written to flash on the remote device. - * @param num_bytes The number of bytes to write - * - * @return true on success, false otherwise. - */ -bool can_bootloader_write_memory(can_bootloader_config_t *can_bl_config, const uint32_t memory_address, const uint8_t *src_buffer, const uint32_t num_bytes) { - BaseSequentialStream *chp = can_bl_config->chp; - - chprintf(chp, "can_bootloader_write_memory(., 0x%X, ., %u)\r\n", memory_address, num_bytes); - - msg_t r = 0; - - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY; - tx_msg.DLC = 5; - tx_msg.data8[0] = (memory_address >> 24) & 0xFF; - tx_msg.data8[1] = (memory_address >> 16) & 0xFF; - tx_msg.data8[2] = (memory_address >> 8) & 0xFF; - tx_msg.data8[3] = (memory_address >> 0) & 0xFF; - tx_msg.data8[4] = num_bytes; - - - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY) ) { - chprintf(chp, "Failed waiting for ACK in can_bootloader_write_memory()\r\n"); - return(false); - } - - - uint32_t idx = 0; - while(1) { - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = CAN_BOOTLOADER_WRITE_MEMORY_RESPONSE_SID; - - while( idx < num_bytes && tx_msg.DLC < 8 ) { - tx_msg.data8[tx_msg.DLC] = src_buffer[idx]; - tx_msg.DLC++; - idx++; - } - - if( tx_msg.DLC > 0 ) { - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY) ) { - chprintf(chp, "Failed waiting for ACK in can_bootloader_write_memory() - 2\r\n"); - return(false); - } - } else { - break; - } - } - - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY) ) { - chprintf(chp, "Failed waiting for ACK in can_bootloader_write_memory() - 3\r\n"); - return(false); - } - - //chprintf(chp, "Successfully wrote memory on remote device...\r\n"); - - return(true); -} - -/** - * Causes the remote device to start executing code from the given address. For M0 based bootloaders, this just causes a reset. - * - * @return true on success, false otherwise. - */ -bool can_bootloader_go(can_bootloader_config_t *can_bl_config, const uint32_t memory_address) { - msg_t r = 0; - - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = ORESAT_BOOTLOADER_CAN_COMMAND_GO; - tx_msg.DLC = 4; - tx_msg.data8[0] = (memory_address >> 24) & 0xFF; - tx_msg.data8[1] = (memory_address >> 16) & 0xFF; - tx_msg.data8[2] = (memory_address >> 8) & 0xFF; - tx_msg.data8[3] = (memory_address >> 0) & 0xFF; - - - if( (r = can_api_transmit(can_bl_config, &tx_msg, 100)) != MSG_OK ) { - return(false); - } - if( ! can_bootloader_wait_for_ack(can_bl_config, ORESAT_BOOTLOADER_CAN_COMMAND_GO) ) { - return(false); - } - - return(true); -} - -/** - * Function for development and testing of this API. - */ -#if 0 -bool can_bootloader_test(can_bootloader_config_t *can_bl_config) { - BaseSequentialStream *chp = can_bl_config->chp; - - if( ! can_bootloader_initiate(can_bl_config, 4000) ) { - chprintf(chp, "Failed to put node into bootloader mode...\r\n"); - return(false); - } - uint32_t test_memory_address = 0x800A000; - if( can_bl_config->stm32_bootloader_mode ) { - test_memory_address = 0x8000000; - } - - //bool can_bootloader_read_data(CANDriver *canp, const uint32_t memory_address, const uint32_t num_bytes_to_read, uint8_t *dest_buffer, const uint32_t dest_buffer_length, BaseSequentialStream *chp) { - static uint8_t temp_buffer[128]; - if( ! can_bootloader_read_data(can_bl_config, 0x8000000, 4, temp_buffer, sizeof(temp_buffer)) ) { - return(false); - } - - if( can_bl_config->stm32_bootloader_mode ) { - if( ! can_bootloader_erase_page(can_bl_config, 0) ) { - return(false); - } - } else { - if( ! can_bootloader_erase_page(can_bl_config, 20) ) { - return(false); - } - } - - if( ! can_bootloader_read_data(can_bl_config, 0x8000000, 4, temp_buffer, sizeof(temp_buffer)) ) { - return(false); - } - - temp_buffer[0] = 0x0D; - temp_buffer[1] = 0x0E; - temp_buffer[2] = 0x0A; - temp_buffer[3] = 0x0D; - temp_buffer[4] = 0x0B; - temp_buffer[5] = 0x0E; - temp_buffer[6] = 0x0E; - temp_buffer[7] = 0x0F; - if( ! can_bootloader_write_memory(can_bl_config, test_memory_address, temp_buffer, 4) ) { - return(false); - } - - if( ! can_bootloader_read_data(can_bl_config, 0x8000000, 4, temp_buffer, sizeof(temp_buffer)) ) { - return(false); - } - -#if 0 - if( ! can_bootloader_read_data(can_bl_config, test_memory_address, 16, temp_buffer, sizeof(temp_buffer)) ) { - return(false); - } - - if( ! can_bootloader_go(can_bl_config, test_memory_address) ) { - return(false); - } -#endif - - return(true); -} -#endif - -/** - * Used to validate communication to a remote bootloader device. - * - * @return true if the remote device is responding in bootloader mode, false otherwise. - */ -bool can_bootloader_check_communication(can_bootloader_config_t *can_bl_config) { - can_api_purge_rx_buffer(can_bl_config); - - uint8_t trash_buffer[8]; - - if( ! can_bootloader_read_data(can_bl_config, ORESAT_F0_FIRMWARE_CRC_ADDRESS, sizeof(trash_buffer), trash_buffer, sizeof(trash_buffer))) { - return(false); - } - - return(true); -} - -/** - * Verify and re-initiate the connection to the M0 cpu if it powered off mid process - */ -bool can_bootloader_verify_retry_connection(can_bootloader_config_t *can_bl_config) { - for(int i = 0; i < 5; i++ ) { - if( can_bootloader_check_communication(can_bl_config) ) { - return(true); - } else { - if( can_bootloader_initiate(can_bl_config, 15000) ) { - return(true); - } - } - } - - can_bl_config->connection_verify_fail++; - - return(false); -} - -/** - * Wrapped to deal with solar cards that power on and off at variable times. - */ -bool can_bootloader_erase_page_reliable(can_bootloader_config_t *can_bl_config, const uint32_t page_number) { - for (int i = 0; i < DEFAULT_RETRY_LIMIT; i++) { - if(can_bootloader_erase_page(can_bl_config, page_number)) { - return (true); - } - can_bl_config->erase_fail_count++; - - if( ! can_bootloader_verify_retry_connection(can_bl_config) ) { - return(false); - } - } - - return (false); -} - -/** - * Wrapped to deal with solar cards that power on and off at variable times. - */ -bool can_bootloader_write_memory_reliable(can_bootloader_config_t *can_bl_config, const uint32_t memory_address, const uint8_t *src_buffer, const uint32_t num_bytes) { - for (int i = 0; i < DEFAULT_RETRY_LIMIT; i++) { - if (can_bootloader_write_memory(can_bl_config, memory_address, src_buffer, num_bytes)) { - return (true); - } - can_bl_config->write_fail_count++; - if( ! can_bootloader_verify_retry_connection(can_bl_config) ) { - return(false); - } - } - - return (false); -} - -/** - * Wrapped to deal with solar cards that power on and off at variable times. - */ -bool can_bootloader_read_data_reliable(can_bootloader_config_t *can_bl_config, const uint32_t memory_address, const uint32_t num_bytes_to_read, uint8_t *dest_buffer, const uint32_t dest_buffer_length) { - for (int i = 0; i < DEFAULT_RETRY_LIMIT; i++) { - if(can_bootloader_read_data(can_bl_config, memory_address, num_bytes_to_read, dest_buffer, dest_buffer_length)) { - return(true); - } - can_bl_config->read_fail_count++; - - if( ! can_bootloader_verify_retry_connection(can_bl_config) ) { - return(false); - } - } - - return(false); -} - -/** - * Wrapped to deal with solar cards that power on and off at variable times. - */ -bool can_bootloader_verify_memory_reliable(can_bootloader_config_t *can_bl_config, const uint32_t base_memory_address, const uint8_t *src_buffer, const uint32_t num_bytes) -{ - BaseSequentialStream *chp = can_bl_config->chp; - - chprintf(chp, "Verifying %u bytes at address 0x%X\r\n", num_bytes, base_memory_address); - - uint8_t temp_buff[16]; - - uint32_t current_offset = 0; - //uint32_t current_offset2 = 0; - while(current_offset < num_bytes) { - if( ! can_bootloader_read_data_reliable(can_bl_config, base_memory_address + current_offset, sizeof(temp_buff), temp_buff, sizeof(temp_buff))) { - return(false); - } -#if 0 - for(uint32_t i = 0; i < sizeof(temp_buff) && current_offset2 < num_bytes; i++ ) { - chprintf(chp, "0x%X 0x%X\r\n", src_buffer[current_offset2], temp_buff[i]); - current_offset2++; - } -#endif - - for( uint32_t i = 0; i < sizeof(temp_buff) && current_offset < num_bytes; i++ ) { - if( src_buffer[current_offset] != temp_buff[i] ) { - chprintf(chp, "ERROR: Failed verification! 0x%X != 0x%X, %u, %u\r\n", src_buffer[current_offset], temp_buff[i], current_offset, i); - return(false); - } - - current_offset++; - } - } - - return(true); -} - -/** - * Writes a subsection of a firmware image to a remote node. - * - * @param *can_bl_config Configuration structure pointer for the bootloader update process. - * @param base_address Address from which to start the firmware update - * @param start_byte_offset Offset from which to start writing. - * @param total_firmware_length_bytes Number of bytes to write - * @param read_function_pointer Function pointer that will return chucks of data from a given offset and length to be written to the remote device. - * - * @return true upon success, false otherwise. - */ -bool oresat_firmware_update_m0_write_subsection(can_bootloader_config_t *can_bl_config, const uint32_t base_address, const uint32_t start_byte_offset, const uint32_t total_firmware_length_bytes, firmware_read_function_ptr_t read_function_pointer) { - - uint32_t current_file_offset = start_byte_offset;//0; - - while (current_file_offset < total_firmware_length_bytes) { - uint32_t bytes_to_write_to_flash = M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE; - if( (current_file_offset + bytes_to_write_to_flash) > total_firmware_length_bytes ) { - bytes_to_write_to_flash = total_firmware_length_bytes - current_file_offset; - if( bytes_to_write_to_flash > M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE ) { - bytes_to_write_to_flash = M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE; - } - } - - if( ! read_function_pointer(current_file_offset, m0_firmware_temp_buffer, bytes_to_write_to_flash, can_bl_config->read_function_arg0) ) { - chprintf(can_bl_config->chp, "failed oresat_firmware_update_m0_write_subsection()\r\n"); - return(false); - } - - if( ! can_bootloader_write_memory_reliable(can_bl_config, (base_address + current_file_offset), m0_firmware_temp_buffer, bytes_to_write_to_flash) ) { - chprintf(can_bl_config->chp, "failed can_bootloader_write_memory_reliable()\r\n"); - return(false); - } - - current_file_offset += bytes_to_write_to_flash; - } - - return(true); -} - - -/** - * Verifies a sub-section of the firmware image on the remote node. - * - * @param *can_bl_config Configuration structure pointer for the bootloader update process. - * @param base_address Address from which to start the firmware update - * @param start_byte_offset Offset from which to start writing. - * @param total_firmware_length_bytes Number of bytes to write - * @param read_function_pointer Function pointer that will return chucks of data from a given offset and length to be written to the remote device. - * - * @return true upon success, false otherwise. - */ -bool oresat_firmware_update_m0_verify_subsection(can_bootloader_config_t *can_bl_config, const uint32_t base_address, const uint32_t start_byte_offset, const uint32_t total_firmware_length_bytes, firmware_read_function_ptr_t read_function_pointer) { - uint32_t current_file_offset = start_byte_offset;//0; - - while (current_file_offset < total_firmware_length_bytes) { - uint32_t bytes_to_write_to_flash = M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE; - if( (current_file_offset + bytes_to_write_to_flash) > total_firmware_length_bytes ) { - bytes_to_write_to_flash = total_firmware_length_bytes - current_file_offset; - if( bytes_to_write_to_flash > M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE ) { - bytes_to_write_to_flash = M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE; - } - } - - if( ! read_function_pointer(current_file_offset, m0_firmware_temp_buffer, bytes_to_write_to_flash, can_bl_config->read_function_arg0) ) { - chprintf(can_bl_config->chp, "failed oresat_firmware_update_m0_write_subsection()\r\n"); - return(false); - } - - if( ! can_bootloader_verify_memory_reliable(can_bl_config, (base_address + current_file_offset), m0_firmware_temp_buffer, bytes_to_write_to_flash) ) { - chprintf(can_bl_config->chp, "failed can_bootloader_verify_memory_reliable()\r\n"); - return(false); - } - - current_file_offset += bytes_to_write_to_flash; - } - - return(true); -} - - - -/** - * Updates firmware on an M0 node - * - * @param *can_bl_config Configuration structure pointer for the bootloader update process. - * @param base_address Address from which to start the firmware update - * @param start_byte_offset Offset from which to start writing. - * @param total_firmware_length_bytes Number of bytes to write - * @param read_function_pointer Function pointer that will return chucks of data from a given offset and length to be written to the remote device. - * - * @return true upon success, false otherwise. - */ -bool oresat_firmware_update_m0(can_bootloader_config_t *can_bl_config, const uint32_t base_address, const uint32_t total_firmware_length_bytes, firmware_read_function_ptr_t read_function_pointer) { - const systime_t start_time = TIME_I2MS(chVTGetSystemTime()); - - BaseSequentialStream *chp = can_bl_config->chp; - - chprintf(chp, "Trying to put node into bootloader mode...\r\n"); - chThdSleepMilliseconds(10); - - // CAN FIFO 1 on the C3 Node will almost certainly have some cruft bootloader related can messages in it that need to be discarded - can_api_purge_rx_buffer(can_bl_config); - - if( ! can_bootloader_initiate(can_bl_config, 5000) ) { - chprintf(chp, "Failed to put node into bootloader mode...\r\n"); - return(false); - } else { - chprintf(chp, "Successfully put node into bootloader mode...\r\n"); - } - - - uint32_t temp_address = base_address; - while(temp_address <= (base_address + total_firmware_length_bytes) ) { - uint32_t page_number = (temp_address - ORESAT_F0_FLASH_START_ADDRESS) / ORESAT_F0_FLASH_PAGE_SIZE; - if( can_bl_config->stm32_bootloader_mode ) { - //proxy for STM32F407 CPU - page_number = 0; - } - - - if( ! can_bootloader_erase_page_reliable(can_bl_config, page_number) ) { - return(false); - } - - temp_address += ORESAT_F0_FLASH_PAGE_SIZE; - } - - - //Initially skip the meta-data portion so that if the node power cycle mid update, the bootloader will not try to CRC check the whole image - if( ! oresat_firmware_update_m0_write_subsection(can_bl_config, base_address, M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE, total_firmware_length_bytes, read_function_pointer) ) { - return(false); - } - - if( ! oresat_firmware_update_m0_verify_subsection(can_bl_config, base_address, M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE, total_firmware_length_bytes, read_function_pointer) ) { - return(false); - } - - //Write the CRC portion last - if( ! oresat_firmware_update_m0_write_subsection(can_bl_config, base_address, 0, M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE, read_function_pointer) ) { - return(false); - } - - if( ! oresat_firmware_update_m0_verify_subsection(can_bl_config, base_address, 0, M0_FIRMWARE_UPDATE_WRITE_CHUNK_SIZE, read_function_pointer) ) { - return(false); - } - - - can_bootloader_go(can_bl_config, ORESAT_F0_FIRMWARE_CODE_ADDRESS); - - can_bl_config->update_duration_ms = TIME_I2MS(chVTGetSystemTime()) - start_time; - - chprintf(chp, "\r\nSuccessfully wrote and verified firmware image to remote MCU device...\r\n\r\n"); - - return(true); -} - -/** - * Helper function for enum to string mapping - */ -const char* oresat_bootloader_can_command_t_to_str(const oresat_bootloader_can_command_t v) { - switch (v) { - case ORESAT_BOOTLOADER_CAN_COMMAND_GET: - return ("ORESAT_BOOTLOADER_CAN_COMMAND_GET"); - case ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY: - return ("ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY"); - case ORESAT_BOOTLOADER_CAN_COMMAND_GO: - return ("ORESAT_BOOTLOADER_CAN_COMMAND_GO"); - case ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY: - return ("ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY"); - case ORESAT_BOOTLOADER_CAN_COMMAND_ERASE: - return ("ORESAT_BOOTLOADER_CAN_COMMAND_ERASE"); - case ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA: - return("ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA"); - } - - if( v == STM32_BOOTLOADER_CAN_ACK ) { - return("ACK"); - } - if( v == STM32_BOOTLOADER_CAN_NACK ) { - return("NACK"); - } - - return ("???"); -} - - diff --git a/common/can_hw.c b/common/can_hw.c deleted file mode 100644 index a4c88e64..00000000 --- a/common/can_hw.c +++ /dev/null @@ -1,3 +0,0 @@ -#include "can_hw.h" - - diff --git a/common/fram.c b/common/fram.c deleted file mode 100644 index 08d71663..00000000 --- a/common/fram.c +++ /dev/null @@ -1,297 +0,0 @@ -/** - * @file fram.c - * @brief FRAM Driver Implementation. - * - * @addtogroup FRAM - * @ingrup ORESAT - * @{ - */ - -#include -#include "hal.h" -#include "fram.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define BLOCK_SIZE 512U - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -FRAMDriver FRAMD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -typedef union { - struct __attribute__((packed)) { - uint16_t addr; - uint8_t data[BLOCK_SIZE]; - }; - uint8_t buf[sizeof(uint16_t) + BLOCK_SIZE]; -} i2cbuf_t; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (FRAM_USE_I2C) || defined(__DOXYGEN__) -/** - * @brief Reads F-RAM memory using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] saddr slave address without R bit - * @param[in] addr address - * @param[out] rxbuf pointer to an output buffer - * @param[in] n number of consecutive bytes to read - * @return the operation status. - * @notapi - */ -msg_t framI2CReadAddr(I2CDriver *i2cp, i2caddr_t saddr, uint16_t addr, uint8_t* rxbuf, size_t n) -{ - addr = __REVSH(addr); - return i2cMasterTransmitTimeout(i2cp, saddr, (uint8_t*)(&addr), sizeof(addr), rxbuf, n, TIME_INFINITE); -} - -/** - * @brief Writes F-RAM memory using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] saddr slave address without R bit - * @param[in] addr address - * @param[in] txbuf buffer containing data - * @param[in] n number of consecutive bytes to write - * @return the operation status. - * @notapi - */ -msg_t framI2CWriteAddr(I2CDriver *i2cp, i2caddr_t saddr, uint16_t addr, uint8_t *txbuf, size_t n) -{ - i2cbuf_t i2cbuf; - size_t size, offset = 0; - msg_t ret; - - while (n) { - size = (n < BLOCK_SIZE ? n : BLOCK_SIZE); - i2cbuf.addr = __REVSH(addr + offset); - memcpy(i2cbuf.data, &txbuf[offset], size); - ret = i2cMasterTransmitTimeout(i2cp, saddr, i2cbuf.buf, sizeof(addr) + n, NULL, 0, TIME_INFINITE); - offset += size; - n -= size; - } - - return ret; -} -#endif /* FRAM_USE_I2C */ - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct FRAMVMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. - * - * @param[out] devp pointer to the @p FRAMDriver object - * - * @init - */ -void framObjectInit(FRAMDriver *devp) -{ - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = FRAM_STOP; -} - -/** - * @brief Configures and activates FRAM Complex Driver peripheral. - * - * @param[in] devp pointer to the @p FRAMDriver object - * @param[in] config pointer to the @p FRAMConfig object - * - * @api - */ -void framStart(FRAMDriver *devp, const FRAMConfig *config) -{ - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == FRAM_STOP) || - (devp->state == FRAM_READY), - "framStart(), invalid state"); - - devp->config = config; - - /* Configuring common registers.*/ -#if FRAM_USE_I2C -#if FRAM_SHARED_I2C - i2cAcquireBus(config->i2cp); -#endif /* FRAM_SHARED_I2C */ - - i2cStart(config->i2cp, config->i2ccfg); - -#if FRAM_SHARED_I2C - i2cReleaseBus(config->i2cp); -#endif /* FRAM_SHARED_I2C */ -#endif /* FRAM_USE_I2C */ - devp->state = FRAM_READY; -} - -/** - * @brief Deactivates the FRAM Complex Driver peripheral. - * - * @param[in] devp pointer to the @p FRAMDriver object - * - * @api - */ -void framStop(FRAMDriver *devp) -{ - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == FRAM_STOP) || (devp->state == FRAM_READY), - "framStop(), invalid state"); - - if (devp->state == FRAM_READY) { -#if FRAM_USE_I2C -#if FRAM_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* FRAM_SHARED_I2C */ - - i2cStop(devp->config->i2cp); - -#if FRAM_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* FRAM_SHARED_I2C */ -#endif /* FRAM_USE_I2C */ - } - devp->state = FRAM_STOP; -} - -/** - * @brief Reads FRAM memory. - * - * @param[in] devp pointer to the @p FRAMDriver object - * @param[in] addr the address to start reading from - * @param[out] buf the buffer to read data into - * @param[in] n number of bytes to read - * - * @api - */ -void framRead(FRAMDriver *devp, uint16_t addr, void *buf, size_t n) -{ - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == FRAM_READY, - "framRead(), invalid state"); - -#if FRAM_USE_I2C -#if FRAM_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* FRAM_SHARED_I2C */ - - framI2CReadAddr(devp->config->i2cp, devp->config->saddr, addr, buf, n); - -#if FRAM_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* FRAM_SHARED_I2C */ -#endif /* FRAM_USE_I2C */ - return; -} - -/** - * @brief Writes FRAM memory. - * - * @param[in] devp pointer to the @p FRAMDriver object - * @param[in] addr the address to start writing to - * @param[out] buf the buffer to read data from - * @param[in] n number of bytes to write - * - * @api - */ -void framWrite(FRAMDriver *devp, uint16_t addr, void *buf, size_t n) -{ - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == FRAM_READY, - "framWrite(), invalid state"); - -#if FRAM_USE_I2C -#if FRAM_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* FRAM_SHARED_I2C */ - - framI2CWriteAddr(devp->config->i2cp, devp->config->saddr, addr, buf, n); - -#if FRAM_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* FRAM_SHARED_I2C */ -#endif /* FRAM_USE_I2C */ - return; -} - -/** - * @brief Erase FRAM memory. - * - * @param[in] devp pointer to the @p FRAMDriver object - * @param[in] addr the address to start erasing from - * @param[in] n number of bytes to erase - * - * @api - */ -void framErase(FRAMDriver *devp, uint16_t addr, size_t n) -{ - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == FRAM_READY, - "framErase(), invalid state"); - - uint8_t buf[BLOCK_SIZE] = {0}; - size_t len, offset = addr; - - while (n) { - len = (n < BLOCK_SIZE ? n : BLOCK_SIZE); - framWrite(devp, offset, buf, len); - offset += len; - n -= len; - } - - return; -} - -/** - * @brief Erase ALL FRAM memory. - * - * @param[in] devp pointer to the @p FRAMDriver object - * - * @api - */ -void framEraseAll(FRAMDriver *devp) -{ - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == FRAM_READY, - "framErase(), invalid state"); - - uint8_t buf[BLOCK_SIZE] = {0}; - size_t len, offset = 0, n = FRAM_SIZE; - - while (n) { - len = (n < BLOCK_SIZE ? n : BLOCK_SIZE); - framWrite(devp, offset, buf, len); - offset += len; - n -= len; - } - - return; -} - -/** @} */ - diff --git a/common/fram.mk b/common/fram.mk deleted file mode 100644 index 66985545..00000000 --- a/common/fram.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the FRAM device files. -FRAMSRC := $(PROJ_SRC)/fram.c - -# Required include directories -FRAMINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(FRAMSRC) -ALLINC += $(FRAMINC) diff --git a/common/fs.c b/common/fs.c deleted file mode 100644 index c8f49796..00000000 --- a/common/fs.c +++ /dev/null @@ -1,1333 +0,0 @@ -/** - * @file fs.c - * @brief Filesystem driver. - * - * @addtogroup Filesystem - * @ingrup ORESAT - * @{ - */ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "fs.h" -#include "crc.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -FSDriver FSD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Locks a block device. - * - * @param[in] cfg Pointer to the LFS configuration - * - * @return Negative error code on failure - * @notapi - */ -int mmc_lock(const struct lfs_config *cfg) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL); - - FSDriver *fsp = cfg->context; - - chMtxLock(&fsp->mutex); - - return LFS_ERR_OK; -} - -/** - * @brief Unlocks a block device. - * - * @param[in] cfg Pointer to the LFS configuration - * - * @return Negative error code on failure - * @notapi - */ -int mmc_unlock(const struct lfs_config *cfg) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL); - - FSDriver *fsp = cfg->context; - - chMtxUnlock(&fsp->mutex); - - return LFS_ERR_OK; -} - -/** - * @brief Reads a block from SDC device. - * @pre The SDC interface must be initialized and the driver started. - * - * @param[in] cfg Pointer to the LFS configuration - * @param[in] block The block to read from - * @param[in] off The offset within the block - * @param[out] buffer Pointer to an output buffer - * @param[in] size Number of consecutive bytes to read - * - * @return Negative error code on failure - * @notapi - */ -int mmc_read(const struct lfs_config *cfg, lfs_block_t block, lfs_off_t off, void *buffer, lfs_size_t size) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL && buffer != NULL); - - FSDriver *fsp = cfg->context; - SDCDriver *sdcp = fsp->config->sdcp; - uint8_t buf[cfg->block_size]; - - /* Sanity checks */ - chDbgCheck(off % cfg->read_size == 0); - chDbgCheck(size % cfg->read_size == 0); - chDbgCheck(off + size <= cfg->block_size); - chDbgCheck(block < cfg->block_count); - - /* Read data from block */ - if (blkRead(sdcp, block, buf, 1) != HAL_SUCCESS) { - return LFS_ERR_IO; - } - - /* Copy the requested data to the buffer */ - memcpy(buffer, &buf[off], size); - - return LFS_ERR_OK; -} - -/** - * @brief Programs a block of an SDC device. - * @pre The SDC interface must be initialized and the driver started. - * - * @param[in] cfg Pointer to the LFS configuration - * @param[in] block The block to program - * @param[in] off The offset within the block - * @param[in] buffer Pointer to an input buffer - * @param[in] size Number of consecutive bytes to program - * - * @return Negative error code on failure - * @notapi - */ -int mmc_prog(const struct lfs_config *cfg, lfs_block_t block, lfs_off_t off, const void *buffer, lfs_size_t size) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL && buffer != NULL); - - FSDriver *fsp = cfg->context; - SDCDriver *sdcp = fsp->config->sdcp; - uint8_t buf[cfg->block_size]; - - /* Sanity checks */ - chDbgCheck(off % cfg->read_size == 0); - chDbgCheck(size % cfg->read_size == 0); - chDbgCheck(off + size <= cfg->block_size); - chDbgCheck(block < cfg->block_count); - - /* Read the current data from the block */ - if (blkRead(sdcp, block, buf, 1) != HAL_SUCCESS) { - return LFS_ERR_IO; - } - - /* Check if existing block already has the data */ - size_t i; - for (i = 0; i < size; i++) { - if (buf[off + i] != ((uint8_t*)buffer)[i]) { - break; - } - } - if (i == size) { - return LFS_ERR_OK; - } - - /* Copy new data */ - memcpy(&buf[off], buffer, size); - - /* Write data to block */ - if (blkWrite(sdcp, block, buf, 1) != HAL_SUCCESS) { - return LFS_ERR_IO; - } - - return LFS_ERR_OK; -} - -/** - * @brief Erase a block of an SDC device. - * @pre The SDC interface must be initialized and the driver started. - * - * @param[in] cfg Pointer to the LFS configuration - * @param[in] block The block to read from - * - * @return Negative error code on failure - * @notapi - */ -int mmc_erase(const struct lfs_config *cfg, lfs_block_t block) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL); - - FSDriver *fsp = cfg->context; - SDCDriver *sdcp = fsp->config->sdcp; - uint8_t buf[cfg->block_size]; - - /* Sanity checks */ - chDbgCheck(block < cfg->block_count); - - memset(buf, 0xFF, cfg->block_size); - - /* Write data to block */ - if (blkWrite(sdcp, block, buf, 1) != HAL_SUCCESS) { - return LFS_ERR_IO; - } - - return LFS_ERR_OK; -} - -/** - * @brief Sync an SDC device. - * @pre The SDC interface must be initialized and the driver started. - * - * @param[in] cfg Pointer to the LFS configuration - * - * @return Negative error code on failure - * @notapi - */ -int mmc_sync(const struct lfs_config *cfg) -{ - /* Sanity checks */ - osalDbgCheck(cfg != NULL); - - FSDriver *fsp = cfg->context; - SDCDriver *sdcp = fsp->config->sdcp; - - if (blkSync(sdcp) != HAL_SUCCESS) { - return LFS_ERR_IO; - } - - return LFS_ERR_OK; -} - -/** - * @brief Enable eMMC and connect. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @notapi - */ -int mmc_enable(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state == FS_ONLINE) || (fsp->state == FS_OFFLINE), - "mmc_enable(), invalid state"); - - BlockDeviceInfo bdinfo; - SDCDriver *sdcp = fsp->config->sdcp; - const SDCConfig *sdccfg = fsp->config->sdccfg; - - if (fsp->state == FS_OFFLINE) { - /* Enable power to eMMC */ - palClearLine(fsp->config->mmc_pwr); - - /* Initializes MMC SDC interface */ - sdcStart(sdcp, sdccfg); - - /* Connect to eMMC device */ - if (sdcConnect(sdcp)) { - sdcStop(sdcp); - palSetLine(fsp->config->mmc_pwr); - return LFS_ERR_IO; - } - - /* Clear error flags from connecting */ - sdcGetAndClearErrors(sdcp); - - /* Retrieve block information */ - blkGetInfo(sdcp, &bdinfo); - fsp->lfscfg.block_size = bdinfo.blk_size; - fsp->lfscfg.block_count = bdinfo.blk_num; - - /* Fetch info about eMMC device */ - _mmcsd_unpack_mmc_cid((MMCSDBlockDevice*)sdcp, &fsp->mmc_cid); - _mmcsd_unpack_csd_mmc((MMCSDBlockDevice*)sdcp, &fsp->mmc_csd); - - fsp->state = FS_ONLINE; - } - - return LFS_ERR_OK; -} - -/** - * @brief Disconnect and disable eMMC. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @notapi - */ -int mmc_disable(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state == FS_ONLINE) || (fsp->state == FS_OFFLINE), - "mmc_disable(), invalid state"); - - SDCDriver *sdcp = fsp->config->sdcp; - - if (fsp->state == FS_ONLINE) { - /* Disconnect from eMMC device and stop interface */ - sdcDisconnect(sdcp); - sdcStop(sdcp); - - /* Disable power to eMMC */ - palSetLine(fsp->config->mmc_pwr); - - fsp->state = FS_OFFLINE; - } - - return LFS_ERR_OK; -} - -/** - * @brief Operations to perform before accessing filesystem. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @notapi - */ -static inline int fs_access_start(FSDriver *fsp) -{ - if (fsp->state != FS_MOUNTED) { - return fs_mount(fsp, false); - } - return LFS_ERR_OK; -} - -/** - * @brief Operations to perform when done accessing filesystem. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @notapi - */ -static inline int fs_access_end(FSDriver *fsp) -{ - /* TODO: unmount if okay */ - (void)fsp; - return LFS_ERR_OK; -} - -/* TODO: Implement static buffers for files */ -void *fs_alloc_file(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - - void *file = NULL; - fsp->err = LFS_ERR_OK; - - file = chGuardedPoolAllocTimeout(&fsp->file_pool, TIME_IMMEDIATE); - if (file == NULL) { - fsp->err = LFS_ERR_NOMEM; - } - - return file; -} - -void fs_free_file(FSDriver *fsp, void *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - - chGuardedPoolFree(&fsp->file_pool, file); -} - -lfs_dir_t *fs_alloc_dir(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - - void *dir = NULL; - fsp->err = LFS_ERR_OK; - - dir = chGuardedPoolAllocTimeout(&fsp->dir_pool, TIME_IMMEDIATE); - if (dir == NULL) { - fsp->err = LFS_ERR_NOMEM; - } - - return dir; -} - -void fs_free_dir(FSDriver *fsp, lfs_dir_t *dir) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL); - - chGuardedPoolFree(&fsp->dir_pool, dir); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. - * - * @param[out] fsp Pointer to the @p FSDriver object - * - * @init - */ -void fs_init(FSDriver *fsp) -{ - fsp->config = NULL; - fsp->err = LFS_ERR_OK; - - /* Initialize lfscfg */ - fsp->lfscfg.context = NULL; - fsp->lfscfg.read = mmc_read; /* Read operation */ - fsp->lfscfg.prog = mmc_prog; /* Program oepration */ - fsp->lfscfg.erase = mmc_erase; /* Erase operation */ - fsp->lfscfg.sync = mmc_sync; /* Sync operation */ - fsp->lfscfg.lock = mmc_lock; /* Lock block device */ - fsp->lfscfg.unlock = mmc_unlock; /* Unlock block device */ - fsp->lfscfg.block_size = 0; - fsp->lfscfg.block_count = 0; - fsp->lfscfg.read_size = 16; /* TODO: Check these values */ - fsp->lfscfg.prog_size = 16; /* TODO: Check these values */ - fsp->lfscfg.block_cycles = -1; /* Disable LFS wear leveling */ - fsp->lfscfg.cache_size = FS_CACHE_SIZE; - fsp->lfscfg.lookahead_size = FS_LOOKAHEAD_SIZE; - fsp->lfscfg.read_buffer = fsp->read_buf; - fsp->lfscfg.prog_buffer = fsp->prog_buf; - fsp->lfscfg.lookahead_buffer= fsp->lookahead_buf; - fsp->lfscfg.name_max = 0; /* Default to LFS_NAME_MAX */ - fsp->lfscfg.file_max = 0; /* Default to LFS_FILE_MAX */ - fsp->lfscfg.attr_max = 0; /* Default to LFS_ATTR_MAX */ - fsp->lfscfg.metadata_max = 0; /* Default to block_size */ - - chMtxObjectInit(&fsp->mutex); - chGuardedPoolObjectInitAligned(&fsp->file_pool, sizeof(lfs_file_t), PORT_NATURAL_ALIGN); - chGuardedPoolLoadArray(&fsp->file_pool, fsp->file, FS_MAX_HANDLERS); - chGuardedPoolObjectInitAligned(&fsp->dir_pool, sizeof(lfs_dir_t), PORT_NATURAL_ALIGN); - chGuardedPoolLoadArray(&fsp->dir_pool, fsp->dir, FS_MAX_HANDLERS); - - fsp->state = FS_STOP; -} - -/** - * @brief Configures and activates Filesystem Driver. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] config Pointer to the @p FSConfig object - * - * @api - */ -void fs_start(FSDriver *fsp, const FSConfig *config) -{ - /* Sanity checks */ - osalDbgCheck((fsp != NULL) && (config != NULL)); - osalDbgAssert((fsp->state == FS_STOP) || (fsp->state == FS_OFFLINE), - "fs_start(), invalid state"); - - fsp->config = config; - fsp->lfscfg.context = fsp; - fsp->state = FS_OFFLINE; -} - -/** - * @brief Deactivates the Filesystem Driver. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @api - */ -void fs_stop(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state == FS_STOP) || (fsp->state == FS_OFFLINE), - "fs_stop(), invalid state"); - - fsp->state = FS_STOP; -} - -/** - * @brief Formats the filesystem. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @api - */ -int fs_format(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_format(), invalid state"); - - fs_state_t last_state; - fsp->err = LFS_ERR_OK; - last_state = fsp->state; - - /* Unmount volume if currently mounted */ - if (fsp->state == FS_MOUNTED) { - fsp->err = fs_unmount(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - } - - /* Enable eMMC if not already enabled */ - if (fsp->state == FS_OFFLINE) { - fsp->err = mmc_enable(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - } - - /* Format LFS file system */ - fsp->err = lfs_format(&fsp->lfs, &fsp->lfscfg); - if (fsp->err == LFS_ERR_OK) { - /* Restore state */ - if (last_state == FS_OFFLINE) { - fsp->err = mmc_disable(fsp); - } else if (last_state == FS_MOUNTED) { - fsp->err = fs_mount(fsp, false); - } - } - - return fsp->err; -} - -/** - * @brief Mounts the filesystem. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] format Format the volume if unable to mount - * - * @return Negative error code on failure - * @api - */ -int fs_mount(FSDriver *fsp, bool format) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_mount(), invalid state"); - - fsp->err = LFS_ERR_OK; - - /* Start eMMC if not already online */ - if (fsp->state == FS_OFFLINE) { - fsp->err = mmc_enable(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - } - - /* Mount LFS file system if not yet mounted */ - if (fsp->state == FS_ONLINE) { - fsp->err = lfs_mount(&fsp->lfs, &fsp->lfscfg); - if (fsp->err != LFS_ERR_OK && format == true) { - /* On failure, attempt format if allowed */ - fsp->err = lfs_format(&fsp->lfs, &fsp->lfscfg); - if (fsp->err == LFS_ERR_OK) { - fsp->err = lfs_mount(&fsp->lfs, &fsp->lfscfg); - } - } - fsp->state = FS_MOUNTED; - } - - return fsp->err; -} - -/** - * @brief Unmounts the filesystem. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Negative error code on failure - * @api - */ -int fs_unmount(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_unmount(), invalid state"); - - fsp->err = LFS_ERR_OK; - - /* Unmount LFS file system if mounted */ - if (fsp->state == FS_MOUNTED) { - fsp->err = lfs_unmount(&fsp->lfs); - fsp->state = FS_ONLINE; - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - } - - if (fsp->state == FS_ONLINE) { - fsp->err = mmc_disable(fsp); - } - - return fsp->err; -} - -/** - * @brief Removes a file or directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * - * @return Negative error code on failure - * @api - */ -int fs_remove(FSDriver *fsp, const char *path) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_remove(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_remove(&fsp->lfs, path); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Renames a file or directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] oldpath Old pathname - * @param[in] newpath New pathname - * - * @return Negative error code on failure - * @api - */ -int fs_rename(FSDriver *fsp, const char *oldpath, const char *newpath) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_remove(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_rename(&fsp->lfs, oldpath, newpath); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Get info about a file or directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * @param[out] info Info structure to fill out - * - * @return Negative error code on failure - * @api - */ -int fs_stat(FSDriver *fsp, const char *path, struct lfs_info *info) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_remove(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_stat(&fsp->lfs, path, info); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Get attribute from file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * @param[in] type Attribute type - * @param[out] buffer The buffer to write the attribute to - * @param[in] size Maximum size of buffer - * - * @return The size of the attribute in the filesyste - * or negative error code - * @api - */ -lfs_ssize_t fs_getattr(FSDriver *fsp, const char *path, uint8_t type, void *buffer, lfs_size_t size) -{ - lfs_ssize_t ret_size; - /* Sanity checks */ - osalDbgCheck(fsp != NULL && buffer != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_getattr(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - ret_size = lfs_getattr(&fsp->lfs, path, type, buffer, size); - if (ret_size < 0) { - fsp->err = ret_size; - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - return ret_size; -} - -/** - * @brief Set attribute on file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * @param[in] type Attribute type - * @param[out] buffer The buffer to write the attribute to - * @param[in] size Maximum size of buffer - * - * @return Negative error code on failure - * @api - */ -int fs_setattr(FSDriver *fsp, const char *path, uint8_t type, const void *buffer, lfs_size_t size) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && buffer != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_getattr(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_setattr(&fsp->lfs, path, type, buffer, size); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Remove attribute from file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * @param[in] type Attribute type - * - * @return Negative error code on failure - * @api - */ -int fs_removeattr(FSDriver *fsp, const char *path, uint8_t type) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_getattr(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_removeattr(&fsp->lfs, path, type); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Return filesystem size in blocks. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Filesystem size in blocks or negative error code on failure - * @api - */ -lfs_size_t fs_size(FSDriver *fsp) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_size(), invalid state"); - - lfs_ssize_t ret_size; - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - ret_size = lfs_fs_size(&fsp->lfs); - if (ret_size < 0) { - fsp->err = ret_size; - return ret_size; - } - - fsp->err = fs_access_end(fsp); - return ret_size; -} - -/** - * @brief Return filesystem utilization as percentage. - * - * @param[in] fsp Pointer to the @p FSDriver object - * - * @return Filesystem utilization percent or negative error code on failure - * @api - */ -uint8_t fs_usage(FSDriver *fsp) -{ - return fs_size(fsp) / fsp->lfscfg.block_count; -} - -/** - * @brief Opens a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname of the file - * @param[in] flags Flags for opening the file - * - * @return File handler pointer - * @api - */ -lfs_file_t *file_open(FSDriver *fsp, const char *path, int flags) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "file_open(), invalid state"); - - lfs_file_t *file = NULL; - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return NULL; - } - - file = fs_alloc_file(fsp); - - if (file != NULL) { - fsp->err = lfs_file_open(&fsp->lfs, file, path, flags); - if (fsp->err != LFS_ERR_OK) { - fs_free_file(fsp, file); - file = NULL; - } - } - - return file; -} - -/** - * @brief Closes a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer to close - * - * @return Negative error code on failure - * @api - */ -int file_close(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_close(), invalid state"); - - fsp->err = LFS_ERR_OK; - - fsp->err = lfs_file_close(&fsp->lfs, file); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fs_free_file(fsp, file); - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Syncs a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * - * @return Negative error code on failure - * @api - */ -int file_sync(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_sync(), invalid state"); - - fsp->err = lfs_file_sync(&fsp->lfs, file); - - return fsp->err; -} - -/** - * @brief Reads from a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * @param[out] buffer Buffer to read into - * @param[in] size Maximum number of bytes to read - * - * @return Offset position or negative error code on failure - * @api - */ -lfs_ssize_t file_read(FSDriver *fsp, lfs_file_t *file, void *buffer, lfs_size_t size) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL && buffer != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_read(), invalid state"); - - lfs_ssize_t ret_size; - fsp->err = LFS_ERR_OK; - - ret_size = lfs_file_read(&fsp->lfs, file, buffer, size); - if (ret_size < 0) { - fsp->err = ret_size; - } - - return ret_size; -} - -/** - * @brief Writes to a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * @param[in] buffer Buffer to write from - * @param[in] size Maximum number of bytes to write - * - * @return Offset position or negative error code on failure - * @api - */ -lfs_ssize_t file_write(FSDriver *fsp, lfs_file_t *file, const void *buffer, lfs_size_t size) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL && buffer != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_read(), invalid state"); - - lfs_ssize_t ret_size; - fsp->err = LFS_ERR_OK; - - ret_size = lfs_file_write(&fsp->lfs, file, buffer, size); - if (ret_size < 0) { - fsp->err = ret_size; - } - - return ret_size; -} - -/** - * @brief Seeks in a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * @param[in] off Offset to seek to - * @param[in] whence Where to start offset at - * - * @return Offset position or negative error code on failure - * @api - */ -lfs_soff_t file_seek(FSDriver *fsp, lfs_file_t *file, lfs_soff_t off, int whence) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_seek(), invalid state"); - - lfs_soff_t ret_off; - fsp->err = LFS_ERR_OK; - - ret_off = lfs_file_seek(&fsp->lfs, file, off, whence); - if (ret_off < 0) { - fsp->err = ret_off; - } - - return ret_off; -} - -/** - * @brief Truncate a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * @param[in] size Size to truncate to - * - * @return Negative error code on failure - * @api - */ -int file_truncate(FSDriver *fsp, lfs_file_t *file, lfs_soff_t size) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_truncate(), invalid state"); - - fsp->err = lfs_file_truncate(&fsp->lfs, file, size); - - return fsp->err; -} - -/** - * @brief Return position in a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * - * @return Offset position or negative error code on failure - * @api - */ -lfs_soff_t file_tell(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_tell(), invalid state"); - - lfs_soff_t off; - fsp->err = LFS_ERR_OK; - - off = lfs_file_tell(&fsp->lfs, file); - if (off < 0) { - fsp->err = off; - } - - return off; -} - -/** - * @brief Set position to start of file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * - * @return Negative error code on failure - * @api - */ -int file_rewind(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_rewind(), invalid state"); - - fsp->err = lfs_file_rewind(&fsp->lfs, file); - - return fsp->err; -} - -/** - * @brief Return size of a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * - * @return Offset position or negative error code - * @api - */ -lfs_soff_t file_size(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_size(), invalid state"); - - lfs_soff_t off; - fsp->err = LFS_ERR_OK; - - off = lfs_file_size(&fsp->lfs, file); - if (off < 0) { - fsp->err = off; - } - - return off; -} - -/** - * @brief Return CRC32 of a file. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] file Open file pointer - * - * @return CRC32 of file - * @api - */ -uint32_t file_crc(FSDriver *fsp, lfs_file_t *file) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && file != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "file_crc(), invalid state"); - - lfs_ssize_t ret_size; - fsp->err = LFS_ERR_OK; - uint32_t crc = 0; - uint8_t buf[512]; - - while ((ret_size = file_read(fsp, file, buf, 512)) > 0) { - crc = crc32(buf, ret_size, crc); - } - if (ret_size < 0) { - fsp->err = ret_size; - } - - return crc; -} - -/** - * @brief Create a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname - * - * @return Negative error code on failure - * @api - */ -int fs_mkdir(FSDriver *fsp, const char *path) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "fs_mkdir(), invalid state"); - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = lfs_mkdir(&fsp->lfs, path); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Opens a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] path Pathname of the directory - * - * @return Directory handler pointer - * @api - */ -lfs_dir_t *dir_open(FSDriver *fsp, const char *path) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL); - osalDbgAssert((fsp->state != FS_UNINIT) && (fsp->state != FS_STOP), - "dir_open(), invalid state"); - - lfs_dir_t *dir = NULL; - - fsp->err = fs_access_start(fsp); - if (fsp->err != LFS_ERR_OK) { - return NULL; - } - - dir = fs_alloc_dir(fsp); - - if (dir != NULL) { - fsp->err = lfs_dir_open(&fsp->lfs, dir, path); - if (fsp->err != LFS_ERR_OK) { - fs_free_dir(fsp, dir); - dir = NULL; - } - } - - return dir; -} - -/** - * @brief Closes a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] dir Open directory pointer to close - * - * @return Negative error code on failure - * @api - */ -int dir_close(FSDriver *fsp, lfs_dir_t *dir) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "dir_close(), invalid state"); - - fsp->err = LFS_ERR_OK; - - fsp->err = lfs_dir_close(&fsp->lfs, dir); - if (fsp->err != LFS_ERR_OK) { - return fsp->err; - } - - fs_free_dir(fsp, dir); - - fsp->err = fs_access_end(fsp); - return fsp->err; -} - -/** - * @brief Reads from a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] dir Open directory pointer - * @param[out] info Info struct to read next entry into - * - * @return Positive value on success, 0 at end of directory - * or negative error code on failure - * @api - */ -int dir_read(FSDriver *fsp, lfs_dir_t *dir, struct lfs_info *info) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL && info != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "dir_read(), invalid state"); - - int ret; - fsp->err = LFS_ERR_OK; - - ret = lfs_dir_read(&fsp->lfs, dir, info); - if (ret < 0) { - fsp->err = ret; - } - - return ret; -} - -/** - * @brief Seeks in a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] dir Open directory pointer - * @param[in] off Offset to seek to (as told by dir_tell) - * - * @return Negative error code on failure - * @api - */ -int dir_seek(FSDriver *fsp, lfs_dir_t *dir, lfs_soff_t off) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "dir_seek(), invalid state"); - - fsp->err = lfs_dir_seek(&fsp->lfs, dir, off); - - return fsp->err; -} - -/** - * @brief Return position in a directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] dir Open directory pointer - * - * @return Offset position or negative error code on failure - * @api - */ -lfs_soff_t dir_tell(FSDriver *fsp, lfs_dir_t *dir) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "dir_tell(), invalid state"); - - lfs_soff_t off; - fsp->err = LFS_ERR_OK; - - off = lfs_dir_tell(&fsp->lfs, dir); - if (off < 0) { - fsp->err = off; - } - - return off; -} - -/** - * @brief Set position to start of directory. - * - * @param[in] fsp Pointer to the @p FSDriver object - * @param[in] dir Open directory pointer - * - * @return Negative error code on failure - * @api - */ -int dir_rewind(FSDriver *fsp, lfs_dir_t *dir) -{ - /* Sanity checks */ - osalDbgCheck(fsp != NULL && dir != NULL); - osalDbgAssert(fsp->state == FS_MOUNTED, - "dir_rewind(), invalid state"); - - fsp->err = lfs_dir_rewind(&fsp->lfs, dir); - - return fsp->err; -} - -/** @} */ diff --git a/common/fs.mk b/common/fs.mk deleted file mode 100644 index bfdd156f..00000000 --- a/common/fs.mk +++ /dev/null @@ -1,16 +0,0 @@ -# Required libraries for filesystem - -LITTLEFS_SRC = $(PROJ_ROOT)/ext/littlefs - -# List of all littlefs sources -FSSRC := $(LITTLEFS_SRC)/lfs.c \ - $(PROJ_SRC)/lfs_util.c \ - $(PROJ_SRC)/fs.c - -# Required include directories -FSINC := $(PROJ_SRC)/include \ - $(LITTLEFS_SRC) - -# Shared variables -ALLCSRC += $(FSSRC) -ALLINC += $(FSINC) diff --git a/common/include/README.md b/common/include/README.md deleted file mode 100644 index 05f586f5..00000000 --- a/common/include/README.md +++ /dev/null @@ -1 +0,0 @@ -# Common Header Files diff --git a/common/include/aprs.h b/common/include/aprs.h deleted file mode 100644 index 5ec3fd7c..00000000 --- a/common/include/aprs.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file aprs.h - * @brief Automatic Packet Reporting System (APRS) support library. - * - * @addtogroup APRS - * @{ - */ -#ifndef _APRS_H_ -#define _APRS_H_ - -/*===========================================================================*/ -/* Constants. */ -/*===========================================================================*/ - - -/** - * @name Automatic Packet Reporting System (APRS) Packets - * @{ - */ -/** @} */ - -/*===========================================================================*/ -/* Pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Data structures and types. */ -/*===========================================================================*/ - -/** - * @name APRS data structure. - * @{ - */ -/** @} */ - -/*===========================================================================*/ -/* Macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _APRS_H_ */ - -/** @} */ diff --git a/common/include/ax25.h b/common/include/ax25.h deleted file mode 100644 index bccdd79f..00000000 --- a/common/include/ax25.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * @file ax25.h - * @brief AX.25 protocol support library. - * - * @addtogroup AX25 - * @{ - */ -#ifndef _AX25_H_ -#define _AX25_H_ - -#include "frame_buf.h" - -/*===========================================================================*/ -/* Constants. */ -/*===========================================================================*/ - -/** - * @brief AX.25 Frames - * @{ - */ -/** - * @name AX.25 address fields - * @{ - */ -#define AX25_ADDR_EXT_Pos (0U) -#define AX25_ADDR_EXT_Msk (0x1U << AX25_ADDR_EXT_Pos) -#define AX25_ADDR_EXT AX25_ADDR_EXT_Msk -#define AX25_ADDR_CHAR_Pos (1U) -#define AX25_ADDR_CHAR_Msk (0xFEU << AX25_ADDR_CHAR_Pos) -#define AX25_ADDR_CHAR AX25_ADDR_CHAR_Msk -/** @} */ - -/** - * @name AX.25 SSID fields - * @{ - */ -#define AX25_SSID_EXT_Pos (0U) -#define AX25_SSID_EXT_Msk (0x1U << AX25_SSID_EXT_Pos) -#define AX25_SSID_EXT AX25_SSID_EXT_Msk -#define AX25_SSID_VAL_Pos (1U) -#define AX25_SSID_VAL_Msk (0xFU << AX25_SSID_VAL_Pos) -#define AX25_SSID_VAL AX25_SSID_VAL_Msk -#define AX25_SSID_RESERVED_Pos (5U) -#define AX25_SSID_RESERVED_Msk (0x3U << AX25_SSID_RESERVED_Pos) -#define AX25_SSID_RESERVED AX25_SSID_RESERVED_Msk -#define AX25_SSID_CMD_RESP_Pos (7U) -#define AX25_SSID_CMD_RESP_Msk (0x1U << AX25_SSID_CMD_RESP_Pos) -#define AX25_SSID_CMD_RESP AX25_SSID_CMD_RESP_Msk -#define AX25_SSID(ssid) (((ssid << AX25_SSID_VAL_Pos) & AX25_SSID_VAL_Msk) | AX25_SSID_RESERVED) -/** @} */ - -/** - * @name AX.25 Control field - * @{ - */ -#define AX25_CTRL_IFRAME (0x00U) -#define AX25_CTRL_SFRAME (0x01U) -#define AX25_CTRL_UFRAME (0x03U) -#define AX25_CTRL_SEND_SEQ_Pos (1U) -#define AX25_CTRL_SEND_SEQ_Msk (0x7U << AX25_CTRL_SEND_SEQ_Pos) -#define AX25_CTRL_SEND_SEQ AX25_CTRL_SEND_SEQ_Msk -#define AX25_CTRL_SUP_Pos (2U) -#define AX25_CTRL_SUP_Msk (0x3U << AX25_CTRL_SUP_Pos) -#define AX25_CTRL_SUP AX25_CTRL_SUP_Msk -#define AX25_SUP_RR (0x0U) -#define AX25_SUP_RNR (0x1U) -#define AX25_SUP_REJ (0x2U) -#define AX25_SUP_SREJ (0x3U) -#define AX25_CTRL_U_FLD_Pos (2U) -#define AX25_CTRL_U_FLD_Msk (0x3BU << AX25_CTRL_U_FLD_Pos) -#define AX25_CTRL_U_FLD AX25_CTRL_U_FLD_Msk -#define AX25_UFRAME_UI (0x00U) -#define AX25_UFRAME_DM (0x03U) -#define AX25_UFRAME_SABM (0x0BU) -#define AX25_UFRAME_DISC (0x10U) -#define AX25_UFRAME_UA (0x18U) -#define AX25_UFRAME_SABME (0x1BU) -#define AX25_UFRAME_FRMR (0x21U) -#define AX25_UFRAME_XID (0x2BU) -#define AX25_UFRAME_TEST (0x38U) -#define AX25_CTRL_POLL_FINAL_Pos (4U) -#define AX25_CTRL_POLL_FINAL_Msk (0x1U << AX25_CTRL_POLL_FINAL_Pos) -#define AX25_CTRL_POLL_FINAL AX25_CTRL_POLL_FINAL_Msk -#define AX25_CTRL_RECV_SEQ_Pos (5U) -#define AX25_CTRL_RECV_SEQ_Msk (0x7U << AX25_CTRL_RECV_SEQ_Pos) -#define AX25_CTRL_RECV_SEQ AX25_CTRL_RECV_SEQ_Msk -/** @} */ - -/** - * @name AX.25 PID values - * @{ - */ -#define AX25_PID_NONE (0xF0U) -/** @} */ - -/** - * @name AX.25 Maximum values size - * @{ - */ -#define AX25_MAX_PAYLOAD_LEN (256U) -#define AX25_MAX_HDR_LEN (sizeof(ax25_hdr_t)) -#define AX25_MAX_FRAME_LEN (AX25_MAX_PAYLOAD_LEN + AX25_MAX_HDR_LEN) -/** @} */ - -/** @} */ - -/*===========================================================================*/ -/* Pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Data structures and types. */ -/*===========================================================================*/ - -/** - * @name AX.25 Link Descriptor - * @{ - */ -typedef struct { - const char *dest; - uint8_t dest_ssid; - const char *src; - uint8_t src_ssid; - uint8_t control; - uint8_t sid; -} ax25_link_t; -/** @} */ - -/** - * @name AX.25 frame data structure. - * @{ - */ -typedef struct __attribute__((packed)) { - char dest[6]; - uint8_t dest_ssid; - char src[6]; - uint8_t src_ssid; - uint8_t control; - uint8_t sid; -} ax25_hdr_t; -/** @} */ - -/*===========================================================================*/ -/* Macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void *ax25_sdu(fb_t *fb, const void *arg); - -#ifdef __cplusplus -} -#endif - -#endif /* _AX25_H_ */ - -/** @} */ diff --git a/common/include/ax5043.h b/common/include/ax5043.h deleted file mode 100644 index 8aa4be44..00000000 --- a/common/include/ax5043.h +++ /dev/null @@ -1,2923 +0,0 @@ -/** - * @file ax5043.h - * @brief AX5043 Radio. - * - * @addtogroup AX5043 - * @{ - */ -#ifndef _AX5043_H_ -#define _AX5043_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief AX5043 Driver version string. - */ -#define AX5043_VERSION "1.0.0" - -/** - * @brief AX5043 Driver version major number. - */ -#define AX5043_MAJOR 1 - -/** - * @brief AX5043 Driver version minor number. - */ -#define AX5043_MINOR 0 - -/** - * @brief AX5043 Driver version patch number. - */ -#define AX5043_PATCH 0 -/** @} */ - -/** - * @name AX5043 Register Addresses - * @{ - */ -/* Revision and Interface Probing */ -#define AX5043_REG_REVISION 0x000U -#define AX5043_REG_SCRATCH 0x001U - -/* Operating Mode */ -#define AX5043_REG_PWRMODE 0x002U - -/* Voltage Regulator */ -#define AX5043_REG_POWSTAT 0x003U -#define AX5043_REG_POWSTICKYSTAT 0x004U -#define AX5043_REG_POWIRQMASK 0x005U - -/* Interrupt Control */ -#define AX5043_REG_IRQMASK 0x006U -#define AX5043_REG_IRQMASK1 0x006U -#define AX5043_REG_IRQMASK0 0x007U -#define AX5043_REG_RADIOEVENTMASK 0x008U -#define AX5043_REG_RADIOEVENTMASK1 0x008U -#define AX5043_REG_RADIOEVENTMASK0 0x009U -#define AX5043_REG_IRQINVERSION 0x00AU -#define AX5043_REG_IRQINVERSION1 0x00AU -#define AX5043_REG_IRQINVERSION0 0x00BU -#define AX5043_REG_IRQREQUEST 0x00CU -#define AX5043_REG_IRQREQUEST1 0x00CU -#define AX5043_REG_IRQREQUEST0 0x00DU -#define AX5043_REG_RADIOEVENTREQ 0x00EU -#define AX5043_REG_RADIOEVENTREQ1 0x00EU -#define AX5043_REG_RADIOEVENTREQ0 0x00FU - -/* Modulation and Framing */ -#define AX5043_REG_MODULATION 0x010U -#define AX5043_REG_ENCODING 0x011U -#define AX5043_REG_FRAMING 0x012U -#define AX5043_REG_CRCINIT 0x014U -#define AX5043_REG_CRCINIT3 0x014U -#define AX5043_REG_CRCINIT2 0x015U -#define AX5043_REG_CRCINIT1 0x016U -#define AX5043_REG_CRCINIT0 0x017U - -/* Forward Error Correction */ -#define AX5043_REG_FEC 0x018U -#define AX5043_REG_FECSYNC 0x019U -#define AX5043_REG_FECSTATUS 0x01AU - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01CU -#define AX5043_REG_XTALSTATUS 0x01DU - -/* Pin Configuration */ -#define AX5043_REG_PINSTATE 0x020U -#define AX5043_REG_PINFUNCSYSCLK 0x021U -#define AX5043_REG_PINFUNCDCLK 0x022U -#define AX5043_REG_PINFUNCDATA 0x023U -#define AX5043_REG_PINFUNCIRQ 0x024U -#define AX5043_REG_PINFUNCANTSEL 0x025U -#define AX5043_REG_PINFUNCPWRAMP 0x026U -#define AX5043_REG_PWRAMP 0x027U - -/* FIFO */ -#define AX5043_REG_FIFOSTAT 0x028U -#define AX5043_REG_FIFODATA 0x029U -#define AX5043_REG_FIFOCOUNT 0x02AU -#define AX5043_REG_FIFOCOUNT1 0x02AU -#define AX5043_REG_FIFOCOUNT0 0x02BU -#define AX5043_REG_FIFOFREE 0x02CU -#define AX5043_REG_FIFOFREE1 0x02CU -#define AX5043_REG_FIFOFREE0 0x02DU -#define AX5043_REG_FIFOTHRESH 0x02EU -#define AX5043_REG_FIFOTHRESH1 0x02EU -#define AX5043_REG_FIFOTHRESH0 0x02FU - -/* Synthesizer */ -#define AX5043_REG_PLLLOOP 0x030U -#define AX5043_REG_PLLCPI 0x031U -#define AX5043_REG_PLLVCODIV 0x032U -#define AX5043_REG_PLLRANGINGA 0x033U -#define AX5043_REG_FREQA 0x034U -#define AX5043_REG_FREQA3 0x034U -#define AX5043_REG_FREQA2 0x035U -#define AX5043_REG_FREQA1 0x036U -#define AX5043_REG_FREQA0 0x037U -#define AX5043_REG_PLLLOOPBOOST 0x038U -#define AX5043_REG_PLLCPIBOOST 0x039U -#define AX5043_REG_PLLRANGINGB 0x03BU -#define AX5043_REG_FREQB 0x03CU -#define AX5043_REG_FREQB3 0x03CU -#define AX5043_REG_FREQB2 0x03DU -#define AX5043_REG_FREQB1 0x03EU -#define AX5043_REG_FREQB0 0x03FU - -/* Signal Strength */ -#define AX5043_REG_RSSI 0x040U -#define AX5043_REG_BGNDRSSI 0x041U -#define AX5043_REG_DIVERSITY 0x042U -#define AX5043_REG_AGCCOUNTER 0x043U - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE 0x045U -#define AX5043_REG_TRKDATARATE2 0x045U -#define AX5043_REG_TRKDATARATE1 0x046U -#define AX5043_REG_TRKDATARATE0 0x047U -#define AX5043_REG_TRKAMPL 0x048U -#define AX5043_REG_TRKAMPL1 0x048U -#define AX5043_REG_TRKAMPL0 0x049U -#define AX5043_REG_TRKPHASE 0x04AU -#define AX5043_REG_TRKPHASE1 0x04AU -#define AX5043_REG_TRKPHASE0 0x04BU -#define AX5043_REG_TRKRFFREQ 0x04DU -#define AX5043_REG_TRKRFFREQ2 0x04DU -#define AX5043_REG_TRKRFFREQ1 0x04EU -#define AX5043_REG_TRKRFFREQ0 0x04FU -#define AX5043_REG_TRKFREQ 0x050U -#define AX5043_REG_TRKFREQ1 0x050U -#define AX5043_REG_TRKFREQ0 0x051U -#define AX5043_REG_TRKFSKDEMOD 0x052U -#define AX5043_REG_TRKFSKDEMOD1 0x052U -#define AX5043_REG_TRKFSKDEMOD0 0x053U - -/* Timers */ -#define AX5043_REG_TIMER 0x059U -#define AX5043_REG_TIMER2 0x059U -#define AX5043_REG_TIMER1 0x05AU -#define AX5043_REG_TIMER0 0x05BU - -/* Wakeup Timer */ -#define AX5043_REG_WAKEUPTIMER 0x068U -#define AX5043_REG_WAKEUPTIMER1 0x068U -#define AX5043_REG_WAKEUPTIMER0 0x069U -#define AX5043_REG_WAKEUP 0x06AU -#define AX5043_REG_WAKEUP1 0x06AU -#define AX5043_REG_WAKEUP0 0x06BU -#define AX5043_REG_WAKEUPFREQ 0x06CU -#define AX5043_REG_WAKEUPFREQ1 0x06CU -#define AX5043_REG_WAKEUPFREQ0 0x06DU -#define AX5043_REG_WAKEUPXOEARLY 0x06EU - -/* PHY Layer Parameters */ -/* Receiver Parameters */ -#define AX5043_REG_IFFREQ 0x100U -#define AX5043_REG_IFFREQ1 0x100U -#define AX5043_REG_IFFREQ0 0x101U -#define AX5043_REG_DECIMATION 0x102U -#define AX5043_REG_RXDATARATE 0x103U -#define AX5043_REG_RXDATARATE2 0x103U -#define AX5043_REG_RXDATARATE1 0x104U -#define AX5043_REG_RXDATARATE0 0x105U -#define AX5043_REG_MAXDROFFSET 0x106U -#define AX5043_REG_MAXDROFFSET2 0x106U -#define AX5043_REG_MAXDROFFSET1 0x107U -#define AX5043_REG_MAXDROFFSET0 0x108U -#define AX5043_REG_MAXRFOFFSET 0x109U -#define AX5043_REG_MAXRFOFFSET2 0x109U -#define AX5043_REG_MAXRFOFFSET1 0x10AU -#define AX5043_REG_MAXRFOFFSET0 0x10BU -#define AX5043_REG_FSKDMAX 0x10CU -#define AX5043_REG_FSKDMAX1 0x10CU -#define AX5043_REG_FSKDMAX0 0x10DU -#define AX5043_REG_FSKDMIN 0x10EU -#define AX5043_REG_FSKDMIN1 0x10EU -#define AX5043_REG_FSKDMIN0 0x10FU -#define AX5043_REG_AFSKSPACE 0x110U -#define AX5043_REG_AFSKSPACE1 0x110U -#define AX5043_REG_AFSKSPACE0 0x111U -#define AX5043_REG_AFSKMARK 0x112U -#define AX5043_REG_AFSKMARK1 0x112U -#define AX5043_REG_AFSKMARK0 0x113U -#define AX5043_REG_AFSKCTRL 0x114U -#define AX5043_REG_AMPLFILTER 0x115U -#define AX5043_REG_FREQUENCYLEAK 0x116U -#define AX5043_REG_RXPARAMSETS 0x117U -#define AX5043_REG_RXPARAMCURSET 0x118U - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120U -#define AX5043_REG_AGCTARGET0 0x121U -#define AX5043_REG_AGCAHYST0 0x122U -#define AX5043_REG_AGCMINMAX0 0x123U -#define AX5043_REG_TIMEGAIN0 0x124U -#define AX5043_REG_DRGAIN0 0x125U -#define AX5043_REG_PHASEGAIN0 0x126U -#define AX5043_REG_FREQGAINA0 0x127U -#define AX5043_REG_FREQGAINB0 0x128U -#define AX5043_REG_FREQGAINC0 0x129U -#define AX5043_REG_FREQGAIND0 0x12AU -#define AX5043_REG_AMPLGAIN0 0x12BU -#define AX5043_REG_FREQDEV0 0x12CU -#define AX5043_REG_FREQDEV10 0x12CU -#define AX5043_REG_FREQDEV00 0x12DU -#define AX5043_REG_FOURFSK0 0x12EU -#define AX5043_REG_BBOFFSRES0 0x12FU - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130U -#define AX5043_REG_AGCTARGET1 0x131U -#define AX5043_REG_AGCAHYST1 0x132U -#define AX5043_REG_AGCMINMAX1 0x133U -#define AX5043_REG_TIMEGAIN1 0x134U -#define AX5043_REG_DRGAIN1 0x135U -#define AX5043_REG_PHASEGAIN1 0x136U -#define AX5043_REG_FREQGAINA1 0x137U -#define AX5043_REG_FREQGAINB1 0x138U -#define AX5043_REG_FREQGAINC1 0x139U -#define AX5043_REG_FREQGAIND1 0x13AU -#define AX5043_REG_AMPLGAIN1 0x13BU -#define AX5043_REG_FREQDEV1 0x13CU -#define AX5043_REG_FREQDEV11 0x13CU -#define AX5043_REG_FREQDEV01 0x13DU -#define AX5043_REG_FOURFSK1 0x13EU -#define AX5043_REG_BBOFFSRES1 0x13FU - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140U -#define AX5043_REG_AGCTARGET2 0x141U -#define AX5043_REG_AGCAHYST2 0x142U -#define AX5043_REG_AGCMINMAX2 0x143U -#define AX5043_REG_TIMEGAIN2 0x144U -#define AX5043_REG_DRGAIN2 0x145U -#define AX5043_REG_PHASEGAIN2 0x146U -#define AX5043_REG_FREQGAINA2 0x147U -#define AX5043_REG_FREQGAINB2 0x148U -#define AX5043_REG_FREQGAINC2 0x149U -#define AX5043_REG_FREQGAIND2 0x14AU -#define AX5043_REG_AMPLGAIN2 0x14BU -#define AX5043_REG_FREQDEV2 0x14CU -#define AX5043_REG_FREQDEV12 0x14CU -#define AX5043_REG_FREQDEV02 0x14DU -#define AX5043_REG_FOURFSK2 0x14EU -#define AX5043_REG_BBOFFSRES2 0x14FU - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150U -#define AX5043_REG_AGCTARGET3 0x151U -#define AX5043_REG_AGCAHYST3 0x152U -#define AX5043_REG_AGCMINMAX3 0x153U -#define AX5043_REG_TIMEGAIN3 0x154U -#define AX5043_REG_DRGAIN3 0x155U -#define AX5043_REG_PHASEGAIN3 0x156U -#define AX5043_REG_FREQGAINA3 0x157U -#define AX5043_REG_FREQGAINB3 0x158U -#define AX5043_REG_FREQGAINC3 0x159U -#define AX5043_REG_FREQGAIND3 0x15AU -#define AX5043_REG_AMPLGAIN3 0x15BU -#define AX5043_REG_FREQDEV3 0x15CU -#define AX5043_REG_FREQDEV13 0x15CU -#define AX5043_REG_FREQDEV03 0x15DU -#define AX5043_REG_FOURFSK3 0x15EU -#define AX5043_REG_BBOFFSRES3 0x15FU - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160U -#define AX5043_REG_FSKDEV 0x161U -#define AX5043_REG_FSKDEV2 0x161U -#define AX5043_REG_FSKDEV1 0x162U -#define AX5043_REG_FSKDEV0 0x163U -#define AX5043_REG_MODCFGA 0x164U -#define AX5043_REG_TXRATE 0x165U -#define AX5043_REG_TXRATE2 0x165U -#define AX5043_REG_TXRATE1 0x166U -#define AX5043_REG_TXRATE0 0x167U -#define AX5043_REG_TXPWRCOEFFA 0x168U -#define AX5043_REG_TXPWRCOEFFA1 0x168U -#define AX5043_REG_TXPWRCOEFFA0 0x169U -#define AX5043_REG_TXPWRCOEFFB 0x16AU -#define AX5043_REG_TXPWRCOEFFB1 0x16AU -#define AX5043_REG_TXPWRCOEFFB0 0x16BU -#define AX5043_REG_TXPWRCOEFFC 0x16CU -#define AX5043_REG_TXPWRCOEFFC1 0x16CU -#define AX5043_REG_TXPWRCOEFFC0 0x16DU -#define AX5043_REG_TXPWRCOEFFD 0x16EU -#define AX5043_REG_TXPWRCOEFFD1 0x16EU -#define AX5043_REG_TXPWRCOEFFD0 0x16FU -#define AX5043_REG_TXPWRCOEFFE 0x170U -#define AX5043_REG_TXPWRCOEFFE1 0x170U -#define AX5043_REG_TXPWRCOEFFE0 0x171U - -/* PLL Parameters */ -#define AX5043_REG_PLLVCOI 0x180U -#define AX5043_REG_PLLVCOIR 0x181U -#define AX5043_REG_PLLLOCKDET 0x182U -#define AX5043_REG_PLLRNGCLK 0x183U - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184U - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188U -#define AX5043_REG_BBOFFSCAP 0x189U - -/* MAC Layer Parameters */ -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200U -#define AX5043_REG_PKTLENCFG 0x201U -#define AX5043_REG_PKTLENOFFSET 0x202U -#define AX5043_REG_PKTMAXLEN 0x203U -#define AX5043_REG_PKTADDR 0x204U -#define AX5043_REG_PKTADDR3 0x204U -#define AX5043_REG_PKTADDR2 0x205U -#define AX5043_REG_PKTADDR1 0x206U -#define AX5043_REG_PKTADDR0 0x207U -#define AX5043_REG_PKTADDRMASK 0x208U -#define AX5043_REG_PKTADDRMASK3 0x208U -#define AX5043_REG_PKTADDRMASK2 0x209U -#define AX5043_REG_PKTADDRMASK1 0x20AU -#define AX5043_REG_PKTADDRMASK0 0x20BU - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT 0x210U -#define AX5043_REG_MATCH0PAT3 0x210U -#define AX5043_REG_MATCH0PAT2 0x211U -#define AX5043_REG_MATCH0PAT1 0x212U -#define AX5043_REG_MATCH0PAT0 0x213U -#define AX5043_REG_MATCH0LEN 0x214U -#define AX5043_REG_MATCH0MIN 0x215U -#define AX5043_REG_MATCH0MAX 0x216U -#define AX5043_REG_MATCH1PAT 0x218U -#define AX5043_REG_MATCH1PAT1 0x218U -#define AX5043_REG_MATCH1PAT0 0x219U -#define AX5043_REG_MATCH1LEN 0x21CU -#define AX5043_REG_MATCH1MIN 0x21DU -#define AX5043_REG_MATCH1MAX 0x21EU - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220U -#define AX5043_REG_TMGTXSETTLE 0x221U -#define AX5043_REG_TMGRXBOOST 0x223U -#define AX5043_REG_TMGRXSETTLE 0x224U -#define AX5043_REG_TMGRXOFFSACQ 0x225U -#define AX5043_REG_TMGRXCOARSEAGC 0x226U -#define AX5043_REG_TMGRXAGC 0x227U -#define AX5043_REG_TMGRXRSSI 0x228U -#define AX5043_REG_TMGRXPREAMBLE1 0x229U -#define AX5043_REG_TMGRXPREAMBLE2 0x22AU -#define AX5043_REG_TMGRXPREAMBLE3 0x22BU -#define AX5043_REG_RSSIREFERENCE 0x22CU -#define AX5043_REG_RSSIABSTHR 0x22DU -#define AX5043_REG_BGNDRSSIGAIN 0x22EU -#define AX5043_REG_BGNDRSSITHR 0x22FU -#define AX5043_REG_PKTCHUNKSIZE 0x230U -#define AX5043_REG_PKTMISCFLAGS 0x231U -#define AX5043_REG_PKTSTOREFLAGS 0x232U -#define AX5043_REG_PKTACCEPTFLAGS 0x233U - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300U -#define AX5043_REG_GPADCPERIOD 0x301U -#define AX5043_REG_GPADC13VALUE 0x308U -#define AX5043_REG_GPADC13VALUE1 0x308U -#define AX5043_REG_GPADC13VALUE0 0x309U - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310U -#define AX5043_REG_LPOSCSTATUS 0x311U -#define AX5043_REG_LPOSCKFILT 0x312U -#define AX5043_REG_LPOSCKFILT1 0x312U -#define AX5043_REG_LPOSCKFILT0 0x313U -#define AX5043_REG_LPOSCREF 0x314U -#define AX5043_REG_LPOSCREF1 0x314U -#define AX5043_REG_LPOSCREF0 0x315U -#define AX5043_REG_LPOSCFREQ 0x316U -#define AX5043_REG_LPOSCFREQ1 0x316U -#define AX5043_REG_LPOSCFREQ0 0x317U -#define AX5043_REG_LPOSCPER 0x318U -#define AX5043_REG_LPOSCPER1 0x318U -#define AX5043_REG_LPOSCPER0 0x319U - -/* DAC */ -#define AX5043_REG_DACVALUE 0x330U -#define AX5043_REG_DACVALUE1 0x330U -#define AX5043_REG_DACVALUE0 0x331U -#define AX5043_REG_DACCONFIG 0x332U - -/* Performance Tuning Registers */ -#define AX5043_REG_0xF00 0xF00U -#define AX5043_REG_0xF08 0xF08U -#define AX5043_REG_POWCTRL1 0xF08U -#define AX5043_REG_0xF0C 0xF0CU -#define AX5043_REG_0xF0D 0xF0DU -#define AX5043_REG_REF 0xF0DU -#define AX5043_REG_0xF10 0xF10U -#define AX5043_REG_XTALOSC 0xF10U -#define AX5043_REG_0xF11 0xF11U -#define AX5043_REG_XTALAMPL 0xF11U -#define AX5043_REG_0xF18 0xF18U -#define AX5043_REG_0xF1C 0xF1CU -#define AX5043_REG_0xF21 0xF21U -#define AX5043_REG_0xF22 0xF22U -#define AX5043_REG_0xF23 0xF23U -#define AX5043_REG_0xF26 0xF26U -#define AX5043_REG_0xF30 0xF30U -#define AX5043_REG_0xF31 0xF31U -#define AX5043_REG_0xF32 0xF32U -#define AX5043_REG_0xF33 0xF33U -#define AX5043_REG_0xF34 0xF34U -#define AX5043_REG_0xF35 0xF35U -#define AX5043_REG_XTALDIV 0xF35U -#define AX5043_REG_0xF44 0xF44U -#define AX5043_REG_0xF72 0xF72U -/** @} */ - -/** - * @name AX5043 REVISION register - * @{ - */ -#define AX5043_REVISION_Pos (0U) -#define AX5043_REVISION_Msk (0xFFU << AX5043_REVISION_Pos) -#define AX5043_REVISION AX5043_REVISION_Msk -/** @} */ - -/** - * @name AX5043 SCRATCH register - * @{ - */ -#define AX5043_SCRATCH_Pos (0U) -#define AX5043_SCRATCH_Msk (0xFFU << AX5043_SCRATCH_Pos) -#define AX5043_SCRATCH AX5043_SCRATCH_Msk -/** @} */ - -/** - * @name AX5043 PWRMODE register fields - * @{ - */ -#define AX5043_PWRMODE_Pos (0U) -#define AX5043_PWRMODE_Msk (0xFU << AX5043_PWRMODE_Pos) -#define AX5043_PWRMODE AX5043_PWRMODE_Msk -#define AX5043_PWRMODE_POWERDOWN (0x0U) -#define AX5043_PWRMODE_DEEPSLEEP (0x1U) -#define AX5043_PWRMODE_STANDBY (0x5U) -#define AX5043_PWRMODE_FIFO_EN (0x7U) -#define AX5043_PWRMODE_RX_SYNTH (0x8U) -#define AX5043_PWRMODE_RX_FULL (0x9U) -#define AX5043_PWRMODE_RX_WOR (0xBU) -#define AX5043_PWRMODE_TX_SYNTH (0xCU) -#define AX5043_PWRMODE_TX_FULL (0xDU) -#define AX5043_PWRMODE_WDS_Pos (4U) -#define AX5043_PWRMODE_WDS_Msk (0x1U << AX5043_PWRMODE_WDS_Pos) -#define AX5043_PWRMODE_WDS AX5043_PWRMODE_WDS_Msk -#define AX5043_PWRMODE_REFEN_Pos (5U) -#define AX5043_PWRMODE_REFEN_Msk (0x1U << AX5043_PWRMODE_REFEN_Pos) -#define AX5043_PWRMODE_REFEN AX5043_PWRMODE_REFEN_Msk -#define AX5043_PWRMODE_XOEN_Pos (6U) -#define AX5043_PWRMODE_XOEN_Msk (0x1U << AX5043_PWRMODE_XOEN_Pos) -#define AX5043_PWRMODE_XOEN AX5043_PWRMODE_XOEN_Msk -#define AX5043_PWRMODE_RESET_Pos (7U) -#define AX5043_PWRMODE_RESET_Msk (0x1U << AX5043_PWRMODE_RESET_Pos) -#define AX5043_PWRMODE_RESET AX5043_PWRMODE_RESET_Msk -/** @} */ - -/** - * @name AX5043 POWSTAT/POWSTICKYSTAT/POWIRQMASK register fields - * @{ - */ -#define AX5043_POWIRQ_SVIO_Pos (0U) -#define AX5043_POWIRQ_SVIOgsk (0x1U << AX5043_POWIRQ_MSVIO_Pos) -#define AX5043_POWIRQ_SVIO AX5043_POWIRQgSVIO_Msk -#define AX5043_POWIRQ_SBEVMODEM_Pos (1U) -#define AX5043_POWIRQ_SBEVMODEMgsk (0x1U << AX5043_POWIRQ_MSBEVMODEM_Pos) -#define AX5043_POWIRQ_SBEVMODEM AX5043_POWIRQgSBEVMODEM_Msk -#define AX5043_POWIRQ_SBEVANA_Pos (2U) -#define AX5043_POWIRQ_SBEVANAgsk (0x1U << AX5043_POWIRQ_MSBEVANA_Pos) -#define AX5043_POWIRQ_SBEVANA AX5043_POWIRQgSBEVANA_Msk -#define AX5043_POWIRQ_SVMODEM_Pos (3U) -#define AX5043_POWIRQ_SVMODEMgsk (0x1U << AX5043_POWIRQ_MSVMODEM_Pos) -#define AX5043_POWIRQ_SVMODEM AX5043_POWIRQgSVMODEM_Msk -#define AX5043_POWIRQ_SVANA_Pos (4U) -#define AX5043_POWIRQ_SVANAgsk (0x1U << AX5043_POWIRQ_MSVANA_Pos) -#define AX5043_POWIRQ_SVANA AX5043_POWIRQgSVANA_Msk -#define AX5043_POWIRQ_SVREF_Pos (5U) -#define AX5043_POWIRQ_SVREFgsk (0x1U << AX5043_POWIRQ_MSVREF_Pos) -#define AX5043_POWIRQ_SVREF AX5043_POWIRQ_SMVREFgsk -#define AX5043_POWIRQ_SREF_Pos (6U) -#define AX5043_POWIRQ_SREFgsk (0x1U << AX5043_POWIRQ_MSREF_Pos) -#define AX5043_POWIRQ_SREF AX5043_POWIRQgSREF_Msk -#define AX5043_POWIRQ_PWRGOOD_Pos (7U) -#define AX5043_POWIRQ_PWRGOODgsk (0x1U << AX5043_POWIRQ_MPWRGOOD_Pos) -#define AX5043_POWIRQ_PWRGOOD AX5043_POWIRQgPWRGOOD_Msk -/** @} */ - -/** - * @name AX5043 IRQMASK/IRQINVERSION/IRQREQUEST register fields - * @{ - */ -#define AX5043_IRQ_FIFONOTEMPTY_Pos (0U) -#define AX5043_IRQ_FIFONOTEMPTY_Msk (0x1U << AX5043_IRQ_FIFONOTEMPTY_Pos) -#define AX5043_IRQ_FIFONOTEMPTY AX5043_IRQ_FIFONOTEMPTY_Msk -#define AX5043_IRQ_FIFONOTFULL_Pos (1U) -#define AX5043_IRQ_FIFONOTFULL_Msk (0x1U << AX5043_IRQ_FIFONOTFULL_Pos) -#define AX5043_IRQ_FIFONOTFULL AX5043_IRQ_FIFONOTFULL_Msk -#define AX5043_IRQ_FIFOTHRCNT_Pos (2U) -#define AX5043_IRQ_FIFOTHRCNT_Msk (0x1U << AX5043_IRQ_FIFOTHRCNT_Pos) -#define AX5043_IRQ_FIFOTHRCNT AX5043_IRQ_FIFOTHRCNT_Msk -#define AX5043_IRQ_FIFOTHRFREE_Pos (3U) -#define AX5043_IRQ_FIFOTHRFREE_Msk (0x1U << AX5043_IRQ_FIFOTHRFREE_Pos) -#define AX5043_IRQ_FIFOTHRFREE AX5043_IRQ_FIFOTHRFREE_Msk -#define AX5043_IRQ_FIFOERROR_Pos (4U) -#define AX5043_IRQ_FIFOERROR_Msk (0x1U << AX5043_IRQ_FIFOERROR_Pos) -#define AX5043_IRQ_FIFOERROR AX5043_IRQ_FIFOERROR_Msk -#define AX5043_IRQ_PLLUNLOCK_Pos (5U) -#define AX5043_IRQ_PLLUNLOCK_Msk (0x1U << AX5043_IRQ_PLLUNLOCK_Pos) -#define AX5043_IRQ_PLLUNLOCK AX5043_IRQ_PLLUNLOCK_Msk -#define AX5043_IRQ_RADIOCTRL_Pos (6U) -#define AX5043_IRQ_RADIOCTRL_Msk (0x1U << AX5043_IRQ_RADIOCTRL_Pos) -#define AX5043_IRQ_RADIOCTRL AX5043_IRQ_RADIOCTRL_Msk -#define AX5043_IRQ_POWER_Pos (7U) -#define AX5043_IRQ_POWER_Msk (0x1U << AX5043_IRQ_POWER_Pos) -#define AX5043_IRQ_POWER AX5043_IRQ_POWER_Msk -#define AX5043_IRQ_XTALREADY_Pos (8U) -#define AX5043_IRQ_XTALREADY_Msk (0x1U << AX5043_IRQ_XTALREADY_Pos) -#define AX5043_IRQ_XTALREADY AX5043_IRQ_XTALREADY_Msk -#define AX5043_IRQ_WAKEUPTIMER_Pos (9U) -#define AX5043_IRQ_WAKEUPTIMER_Msk (0x1U << AX5043_IRQ_WAKEUPTIMER_Pos) -#define AX5043_IRQ_WAKEUPTIMER AX5043_IRQ_WAKEUPTIMER_Msk -#define AX5043_IRQ_LPOSC_Pos (10U) -#define AX5043_IRQ_LPOSC_Msk (0x1U << AX5043_IRQ_LPOSC_Pos) -#define AX5043_IRQ_LPOSC AX5043_IRQ_LPOSC_Msk -#define AX5043_IRQ_GPADC_Pos (11U) -#define AX5043_IRQ_GPADC_Msk (0x1U << AX5043_IRQ_GPADC_Pos) -#define AX5043_IRQ_GPADC AX5043_IRQ_GPADC_Msk -#define AX5043_IRQ_PLLRNGDONE_Pos (12U) -#define AX5043_IRQ_PLLRNGDONE_Msk (0x1U << AX5043_IRQ_PLLRNGDONE_Pos) -#define AX5043_IRQ_PLLRNGDONE AX5043_IRQ_PLLRNGDONE_Msk -/** @} */ - -/** - * @name AX5043 RADIOEVENTMASK/RADIOEVENTREQ register fields - * @{ - */ -#define AX5043_RADIOEVENT_DONE_Pos (0U) -#define AX5043_RADIOEVENT_DONE_Msk (0x1U << AX5043_RADIOEVENT_DONE_Pos) -#define AX5043_RADIOEVENT_DONE AX5043_RADIOEVENT_DONE_Msk -#define AX5043_RADIOEVENT_SETTLED_Pos (1U) -#define AX5043_RADIOEVENT_SETTLED_Msk (0x1U << AX5043_RADIOEVENT_SETTLED_Pos) -#define AX5043_RADIOEVENT_SETTLED AX5043_RADIOEVENT_SETTLED_Msk -#define AX5043_RADIOEVENT_RADIOSTATECHG_Pos (2U) -#define AX5043_RADIOEVENT_RADIOSTATECHG_Msk (0x1U << AX5043_RADIOEVENT_RADIOSTATECHG_Pos) -#define AX5043_RADIOEVENT_RADIOSTATECHG AX5043_RADIOEVENT_RADIOSTATECHG_Msk -#define AX5043_RADIOEVENT_RXPARAMSETCHG_Pos (3U) -#define AX5043_RADIOEVENT_RXPARAMSETCHG_Msk (0x1U << AX5043_RADIOEVENT_RXPARAMSETCHG_Pos) -#define AX5043_RADIOEVENT_RXPARAMSETCHG AX5043_RADIOEVENT_RXPARAMSETCHG_Msk -#define AX5043_RADIOEVENT_FRAMECLK_Pos (4U) -#define AX5043_RADIOEVENT_FRAMECLK_Msk (0x1U << AX5043_RADIOEVENT_FRAMECLK_Pos) -#define AX5043_RADIOEVENT_FRAMECLK AX5043_RADIOEVENT_FRAMECLK_Msk -/** @} */ - -/** - * @name AX5043 MODULATION register fields - * @{ - */ -#define AX5043_MODULATION_Pos (0U) -#define AX5043_MODULATION_Msk (0xFU << AX5043_MODULATION_Pos) -#define AX5043_MODULATION AX5043_MODULATION_Msk -#define AX5043_MODULATION_ASK (0x0U) -#define AX5043_MODULATION_ASK_COHERENT (0x1U) -#define AX5043_MODULATION_PSK (0x4U) -#define AX5043_MODULATION_OQSK (0x6U) -#define AX5043_MODULATION_MSK (0x7U) -#define AX5043_MODULATION_FSK (0x8U) -#define AX5043_MODULATION_4FSK (0x9U) -#define AX5043_MODULATION_AFSK (0xAU) -#define AX5043_MODULATION_FM (0xBU) -#define AX5043_MODULATION_RXHALFSPEED_Pos (4U) -#define AX5043_MODULATION_RXHALFSPEED_Msk (0x1U << AX5043_MODULATION_RXHALFSPEED_Pos) -#define AX5043_MODULATION_RXHALFSPEED AX5043_MODULATION_RXHALFSPEED_Msk -/** @} */ - -/** - * @name AX5043 ENCODING register fields - * @{ - */ -#define AX5043_ENCODING_Pos (0U) -#define AX5043_ENCODING_Msk (0xFU << AX5043_ENCODING_Pos) -#define AX5043_ENCODING AX5043_ENCODING_Msk -#define AX5043_ENCODING_INV_Pos (0U) -#define AX5043_ENCODING_INV_Msk (0x1U << AX5043_ENCODING_INV_Pos) -#define AX5043_ENCODING_INV AX5043_ENCODING_INV_Msk -#define AX5043_ENCODING_DIFF_Pos (1U) -#define AX5043_ENCODING_DIFF_Msk (0x1U << AX5043_ENCODING_DIFF_Pos) -#define AX5043_ENCODING_DIFF AX5043_ENCODING_DIFF_Msk -#define AX5043_ENCODING_SCRAM_Pos (2U) -#define AX5043_ENCODING_SCRAM_Msk (0x1U << AX5043_ENCODING_SCRAM_Pos) -#define AX5043_ENCODING_SCRAM AX5043_ENCODING_SCRAM_Msk -#define AX5043_ENCODING_MANCH_Pos (3U) -#define AX5043_ENCODING_MANCH_Msk (0x1U << AX5043_ENCODING_MANCH_Pos) -#define AX5043_ENCODING_MANCH AX5043_ENCODING_MANCH_Msk -#define AX5043_ENCODING_NOSYNC_Pos (4U) -#define AX5043_ENCODING_NOSYNC_Msk (0x1U << AX5043_ENCODING_NOSYNC_Pos) -#define AX5043_ENCODING_NOSYNC AX5043_ENCODING_NOSYNC_Msk -/* Customary Encodings */ -#define AX5043_ENCODING_NRZ (0x0U) /* MANCH=0 SCRAM=0 DIFF=0 INV=0 */ -#define AX5043_ENCODING_NRZI (0x3U) /* MANCH=0 SCRAM=0 DIFF=1 INV=1 */ -#define AX5043_ENCODING_NRZ_SCRAM (0x4U) /* MANCH=0 SCRAM=1 DIFF=0 INV=0 */ -#define AX5043_ENCODING_NRZI_SCRAM (0x7U) /* MANCH=0 SCRAM=1 DIFF=1 INV=1 */ -#define AX5043_ENCODING_MANCHESTER (0x8U) /* MANCH=1 SCRAM=0 DIFF=0 INV=0 */ -#define AX5043_ENCODING_FM0 (0xAU) /* MANCH=1 SCRAM=0 DIFF=1 INV=0 */ -#define AX5043_ENCODING_FM1 (0xBU) /* MANCH=1 SCRAM=0 DIFF=1 INV=1 */ -/** @} */ - -/** - * @name AX5043 FRAMING register fields - * @{ - */ -#define AX5043_FRAMING_FABORT_Pos (0U) -#define AX5043_FRAMING_FABORT_Msk (0x1U << AX5043_FRAMING_FABORT_Pos) -#define AX5043_FRAMING_FABORT AX5043_FRAMING_FABORT_Msk -#define AX5043_FRAMING_FRMMODE_Pos (1U) -#define AX5043_FRAMING_FRMMODE_Msk (0x7U << AX5043_FRAMING_FRMMODE_Pos) -#define AX5043_FRAMING_FRMMODE AX5043_FRAMING_FRMMODE_Msk -#define AX5043_FRMMODE_RAW (0x0U) -#define AX5043_FRMMODE_RAW_SOFTBITS (0x1U) -#define AX5043_FRMMODE_HDLC (0x2U) -#define AX5043_FRMMODE_RAW_PATMATCH (0x3U) -#define AX5043_FRMMODE_WMBUS (0x4U) -#define AX5043_FRMMODE_WMBUS_4TO6 (0x5U) -#define AX5043_FRAMING_CRCMODE_Pos (4U) -#define AX5043_FRAMING_CRCMODE_Msk (0x7U << AX5043_FRAMING_CRCMODE_Pos) -#define AX5043_FRAMING_CRCMODE AX5043_FRAMING_CRCMODE_Msk -#define AX5043_CRCMODE_OFF (0x0U) -#define AX5043_CRCMODE_CCITT (0x1U) -#define AX5043_CRCMODE_CRC16 (0x2U) -#define AX5043_CRCMODE_DNP (0x3U) -#define AX5043_CRCMODE_CRC32 (0x6U) -#define AX5043_FRAMING_FRMRX_Pos (7U) -#define AX5043_FRAMING_FRMRX_Msk (0x1U << AX5043_FRAMING_FRMRX_Pos) -#define AX5043_FRAMING_FRMRX AX5043_FRAMING_FRMRX_Msk -/** @} */ - -/** - * @name AX5043 CRCINIT register fields - * @{ - */ -#define AX5043_CRCINIT_Pos (0U) -#define AX5043_CRCINIT_Msk (0xFFFFFFFFU << AX5043_CRCINIT_Pos) -#define AX5043_CRCINIT AX5043_CRCINIT_Msk -/** @} */ - -/** - * @name AX5043 FEC register fields - * @{ - */ -#define AX5043_FEC_FECENA_Pos (0U) -#define AX5043_FEC_FECENA_Msk (0x1U << AX5043_FEC_FECENA_Pos) -#define AX5043_FEC_FECENA AX5043_FEC_FECENA_Msk -#define AX5043_FEC_FECINPSHIFT_Pos (1U) -#define AX5043_FEC_FECINPSHIFT_Msk (0x7U << AX5043_FEC_FECINPSHIFT_Pos) -#define AX5043_FEC_FECINPSHIFT AX5043_FEC_FECINPSHIFT_Msk -#define AX5043_FEC_FECPOS_Pos (4U) -#define AX5043_FEC_FECPOS_Msk (0x1U << AX5043_FEC_FECPOS_Pos) -#define AX5043_FEC_FECPOS AX5043_FEC_FECPOS_Msk -#define AX5043_FEC_FECNEG_Pos (5U) -#define AX5043_FEC_FECNEG_Msk (0x1U << AX5043_FEC_FECNEG_Pos) -#define AX5043_FEC_FECNEG AX5043_FEC_FECNEG_Msk -#define AX5043_FEC_RSTVITERBI_Pos (6U) -#define AX5043_FEC_RSTVITERBI_Msk (0x1U << AX5043_FEC_RSTVITERBI_Pos) -#define AX5043_FEC_RSTVITERBI AX5043_FEC_RSTVITERBI_Msk -#define AX5043_FEC_SHORTMEM_Pos (7U) -#define AX5043_FEC_SHORTMEM_Msk (0x1U << AX5043_FEC_SHORTMEM_Pos) -#define AX5043_FEC_SHORTMEM AX5043_FEC_SHORTMEM_Msk -/** @} */ - -/** - * @name AX5043 FECSYNC register fields - * @{ - */ -#define AX5043_FECSYNC_Pos (0U) -#define AX5043_FECSYNC_Msk (0xFFU << AX5043_FECSYNC_Pos) -#define AX5043_FECSYNC AX5043_FECSYNC_Msk -/** @} */ - -/** - * @name AX5043 FECSTATUS register fields - * @{ - */ -#define AX5043_FECSTATUS_MAXMETRIC_Pos (0U) -#define AX5043_FECSTATUS_MAXMETRIC_Msk (0x7FU << AX5043_FECSTATUS_MAXMETRIC_Pos) -#define AX5043_FECSTATUS_MAXMETRIC AX5043_FECSTATUS_MAXMETRIC_Msk -#define AX5043_FECSTATUS_FECINV_Pos (7U) -#define AX5043_FECSTATUS_FECINV_Msk (0x1U << AX5043_FECSTATUS_FECINV_Pos) -#define AX5043_FECSTATUS_FECINV AX5043_FECSTATUS_FECINV_Msk -/** @} */ - -/** - * @name AX5043 RADIOSTATE register fields - * @{ - */ -#define AX5043_RADIOSTATE_Pos (0U) -#define AX5043_RADIOSTATE_Msk (0xFU << AX5043_RADIOSTATE_Pos) -#define AX5043_RADIOSTATE AX5043_RADIOSTATE_Msk -#define AX5043_RADIOSTATE_IDLE (0x0U) -#define AX5043_RADIOSTATE_POWERDOWN (0x1U) -#define AX5043_RADIOSTATE_TX_PLL_SET (0x4U) -#define AX5043_RADIOSTATE_TX (0x6U) -#define AX5043_RADIOSTATE_TX_TAIL (0x7U) -#define AX5043_RADIOSTATE_RX_PLL_SET (0x8U) -#define AX5043_RADIOSTATE_RX_ANTSEL (0x9U) -#define AX5043_RADIOSTATE_RX_PREAMBLE1 (0xCU) -#define AX5043_RADIOSTATE_RX_PREAMBLE2 (0xDU) -#define AX5043_RADIOSTATE_RX_PREAMBLE3 (0xEU) -#define AX5043_RADIOSTATE_RX (0xFU) -/** @} */ - -/** - * @name AX5043 XTALSTATUS register fields - * @{ - */ -#define AX5043_XTALSTATUS_XTALRUN_Pos (0U) -#define AX5043_XTALSTATUS_XTALRUN_Msk (0x1U << AX5043_XTALSTATUS_XTALRUN_Pos) -#define AX5043_XTALSTATUS_XTALRUN AX5043_XTALSTATUS_XTALRUN_Msk - -/** - * @name AX5043 PINSTATE register fields - * @{ - */ -#define AX5043_PINSTATE_PSSYSCLK_Pos (0U) -#define AX5043_PINSTATE_PSSYSCLK_Msk (0x1U << AX5043_PINSTATE_PSSYSCLK_Pos) -#define AX5043_PINSTATE_PSSYSCLK AX5043_PINSTATE_PSSYSCLK_Msk -#define AX5043_PINSTATE_PSDCLK_Pos (1U) -#define AX5043_PINSTATE_PSDCLK_Msk (0x1U << AX5043_PINSTATE_PSDCLK_Pos) -#define AX5043_PINSTATE_PSDCLK AX5043_PINSTATE_PSDCLK_Msk -#define AX5043_PINSTATE_PSDATA_Pos (2U) -#define AX5043_PINSTATE_PSDATA_Msk (0x1U << AX5043_PINSTATE_PSDATA_Pos) -#define AX5043_PINSTATE_PSDATA AX5043_PINSTATE_PSDATA_Msk -#define AX5043_PINSTATE_PSIRQ_Pos (3U) -#define AX5043_PINSTATE_PSIRQ_Msk (0x1U << AX5043_PINSTATE_PSIRQ_Pos) -#define AX5043_PINSTATE_PSIRQ AX5043_PINSTATE_PSIRQ_Msk -#define AX5043_PINSTATE_PSANTSEL_Pos (4U) -#define AX5043_PINSTATE_PSANTSEL_Msk (0x1U << AX5043_PINSTATE_PSANTSEL_Pos) -#define AX5043_PINSTATE_PSANTSEL AX5043_PINSTATE_PSANTSEL_Msk -#define AX5043_PINSTATE_PSPWRAMP_Pos (5U) -#define AX5043_PINSTATE_PSPWRAMP_Msk (0x1U << AX5043_PINSTATE_PSPWRAMP_Pos) -#define AX5043_PINSTATE_PSPWRAMP AX5043_PINSTATE_PSPWRAMP_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCSYSCLK register fields - * @{ - */ -#define AX5043_PINFUNCSYSCLK_Pos (0U) -#define AX5043_PINFUNCSYSCLK_Msk (0x1FU << AX5043_PINFUNCSYSCLK_Pos) -#define AX5043_PINFUNCSYSCLK AX5043_PINFUNCSYSCLK_Msk -#define AX5043_PFSYSCLK_OUT_0 (0x00U) -#define AX5043_PFSYSCLK_OUT_1 (0x01U) -#define AX5043_PFSYSCLK_OUT_Z (0x02U) -#define AX5043_PFSYSCLK_OUT_XTAL_INV (0x03U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV1 (0x04U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV2 (0x05U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV4 (0x06U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV8 (0x07U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV16 (0x08U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV32 (0x09U) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV64 (0x0AU) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV128 (0x0BU) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV256 (0x0CU) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV512 (0x0DU) -#define AX5043_PFSYSCLK_OUT_XTAL_DIV1024 (0x0EU) -#define AX5043_PFSYSCLK_OUT_LPOSC (0x0FU) -#define AX5043_PFSYSCLK_OUT_TEST_OBS (0x1FU) -#define AX5043_PINFUNCSYSCLK_PUSYSCLK_Pos (7U) -#define AX5043_PINFUNCSYSCLK_PUSYSCLK_Msk (0x1U << AX5043_PINFUNCSYSCLK_PUSYSCLK_Pos) -#define AX5043_PINFUNCSYSCLK_PUSYSCLK AX5043_PINFUNCSYSCLK_PUSYSCLK_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCDCLK register fields - * @{ - */ -#define AX5043_PINFUNCDCLK_Pos (0U) -#define AX5043_PINFUNCDCLK_Msk (0x7U << AX5043_PINFUNCDCLK_Pos) -#define AX5043_PINFUNCDCLK AX5043_PINFUNCDCLK_Msk -#define AX5043_PFDCLK_OUT_0 (0x0U) -#define AX5043_PFDCLK_OUT_1 (0x1U) -#define AX5043_PFDCLK_OUT_Z (0x2U) -#define AX5043_PFDCLK_IN_MODEM_IO (0x3U) -#define AX5043_PFDCLK_OUT_MODEM (0x4U) -#define AX5043_PFDCLK_OUT_MODEM_IO (0x5U) -#define AX5043_PFDCLK_OUT_TEST_OBS (0x7U) -#define AX5043_PINFUNCDCLK_PIDCLK_Pos (6U) -#define AX5043_PINFUNCDCLK_PIDCLK_Msk (0x1U << AX5043_PINFUNCDCLK_PIDCLK_Pos) -#define AX5043_PINFUNCDCLK_PIDCLK AX5043_PINFUNCDCLK_PIDCLK_Msk -#define AX5043_PINFUNCDCLK_PUDCLK_Pos (7U) -#define AX5043_PINFUNCDCLK_PUDCLK_Msk (0x1U << AX5043_PINFUNCDCLK_PUDCLK_Pos) -#define AX5043_PINFUNCDCLK_PUDCLK AX5043_PINFUNCDCLK_PUDCLK_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCDATA register fields - * @{ - */ -#define AX5043_PINFUNCDATA_Pos (0U) -#define AX5043_PINFUNCDATA_Msk (0xFU << AX5043_PINFUNCDATA_Pos) -#define AX5043_PINFUNCDATA AX5043_PINFUNCDATA_Msk -#define AX5043_PFDATA_OUT_0 (0x0U) -#define AX5043_PFDATA_OUT_1 (0x1U) -#define AX5043_PFDATA_OUT_Z (0x2U) -#define AX5043_PFDATA_IO_FRAME (0x3U) -#define AX5043_PFDATA_IO_MODEM (0x4U) -#define AX5043_PFDATA_IO_MODEM_ASYNC (0x5U) -#define AX5043_PFDATA_OUT_MODEM (0x7U) -#define AX5043_PFDATA_OUT_TEST_OBS (0xFU) -#define AX5043_PINFUNCDATA_PIDATA_Pos (6U) -#define AX5043_PINFUNCDATA_PIDATA_Msk (0x1U << AX5043_PINFUNCDATA_PIDATA_Pos) -#define AX5043_PINFUNCDATA_PIDATA AX5043_PINFUNCDATA_PIDATA_Msk -#define AX5043_PINFUNCDATA_PUDATA_Pos (7U) -#define AX5043_PINFUNCDATA_PUDATA_Msk (0x1U << AX5043_PINFUNCDATA_PUDATA_Pos) -#define AX5043_PINFUNCDATA_PUDATA AX5043_PINFUNCDATA_PUDATA_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCIRQ register fields - * @{ - */ -#define AX5043_PINFUNCIRQ_Pos (0U) -#define AX5043_PINFUNCIRQ_Msk (0x7U << AX5043_PINFUNCIRQ_Pos) -#define AX5043_PINFUNCIRQ AX5043_PINFUNCIRQ_Msk -#define AX5043_PFIRQ_OUT_0 (0x0U) -#define AX5043_PFIRQ_OUT_1 (0x1U) -#define AX5043_PFIRQ_OUT_Z (0x2U) -#define AX5043_PFIRQ_OUT_IRQ (0x3U) -#define AX5043_PFIRQ_OUT_TEST_OBS (0x7U) -#define AX5043_PINFUNCIRQ_PIIRQ_Pos (6U) -#define AX5043_PINFUNCIRQ_PIIRQ_Msk (0x1U << AX5043_PINFUNCIRQ_PIIRQ_Pos) -#define AX5043_PINFUNCIRQ_PIIRQ AX5043_PINFUNCIRQ_PIIRQ_Msk -#define AX5043_PINFUNCIRQ_PUIRQ_Pos (7U) -#define AX5043_PINFUNCIRQ_PUIRQ_Msk (0x1U << AX5043_PINFUNCIRQ_PUIRQ_Pos) -#define AX5043_PINFUNCIRQ_PUIRQ AX5043_PINFUNCIRQ_PUIRQ_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCANTSEL register fields - * @{ - */ -#define AX5043_PINFUNCANTSEL_Pos (0U) -#define AX5043_PINFUNCANTSEL_Msk (0x7U << AX5043_PINFUNCANTSEL_Pos) -#define AX5043_PINFUNCANTSEL AX5043_PINFUNCANTSEL_Msk -#define AX5043_PFANTSEL_OUT_0 (0x0U) -#define AX5043_PFANTSEL_OUT_1 (0x1U) -#define AX5043_PFANTSEL_OUT_Z (0x2U) -#define AX5043_PFANTSEL_OUT_BB_TUNE_CLK (0x3U) -#define AX5043_PFANTSEL_OUT_TCXO_EN (0x4U) -#define AX5043_PFANTSEL_OUT_DAC (0x5U) -#define AX5043_PFANTSEL_OUT_DIVERSE_ANTSEL (0x6U) -#define AX5043_PFANTSEL_OUT_TEST_OBS (0x7U) -#define AX5043_PINFUNCANTSEL_PIANTSEL_Pos (6U) -#define AX5043_PINFUNCANTSEL_PIANTSEL_Msk (0x1U << AX5043_PINFUNCANTSEL_PIANTSEL_Pos) -#define AX5043_PINFUNCANTSEL_PIANTSEL AX5043_PINFUNCANTSEL_PIANTSEL_Msk -#define AX5043_PINFUNCANTSEL_PUANTSEL_Pos (7U) -#define AX5043_PINFUNCANTSEL_PUANTSEL_Msk (0x1U << AX5043_PINFUNCANTSEL_PUANTSEL_Pos) -#define AX5043_PINFUNCANTSEL_PUANTSEL AX5043_PINFUNCANTSEL_PUANTSEL_Msk -/** @} */ - -/** - * @name AX5043 PINFUNCPWRAMP register fields - * @{ - */ -#define AX5043_PINFUNCPWRAMP_Pos (0U) -#define AX5043_PINFUNCPWRAMP_Msk (0xFU << AX5043_PINFUNCPWRAMP_Pos) -#define AX5043_PINFUNCPWRAMP AX5043_PINFUNCPWRAMP_Msk -#define AX5043_PFPWRAMP_OUT_0 (0x0U) -#define AX5043_PFPWRAMP_OUT_1 (0x1U) -#define AX5043_PFPWRAMP_OUT_Z (0x2U) -#define AX5043_PFPWRAMP_IN_DIBIT_SYNC (0x3U) -#define AX5043_PFPWRAMP_OUT_DIBIT_SYNC (0x4U) -#define AX5043_PFPWRAMP_OUT_DAC (0x5U) -#define AX5043_PFPWRAMP_OUT_PWRAMP_CTRL (0x6U) -#define AX5043_PFPWRAMP_OUT_TXCO_EN (0x7U) -#define AX5043_PFPWRAMP_OUT_TEST_OBS (0xFU) -#define AX5043_PINFUNCPWRAMP_PIPWRAMP_Pos (6U) -#define AX5043_PINFUNCPWRAMP_PIPWRAMP_Msk (0x1U << AX5043_PINFUNCPWRAMP_PIPWRAMP_Pos) -#define AX5043_PINFUNCPWRAMP_PIPWRAMP AX5043_PINFUNCPWRAMP_PIPWRAMP_Msk -#define AX5043_PINFUNCPWRAMP_PUPWRAMP_Pos (7U) -#define AX5043_PINFUNCPWRAMP_PUPWRAMP_Msk (0x1U << AX5043_PINFUNCPWRAMP_PUPWRAMP_Pos) -#define AX5043_PINFUNCPWRAMP_PUPWRAMP AX5043_PINFUNCPWRAMP_PUPWRAMP_Msk -/** @} */ - -/** - * @name AX5043 PWRAMP register fields - * @{ - */ -#define AX5043_PWRAMP_Pos (0U) -#define AX5043_PWRAMP_Msk (0x1U << AX5043_PWRAMP_Pos) -#define AX5043_PWRAMP AX5043_PWRAMP_Msk -/** @} */ - -/** - * @name AX5043 FIFOSTAT register fields - * @{ - */ -#define AX5043_FIFOSTAT_FIFOCMD_Pos (0U) -#define AX5043_FIFOSTAT_FIFOCMD_Msk (0x3FU << AX5043_FIFOSTAT_FIFOCMD_Pos) -#define AX5043_FIFOSTAT_FIFOCMD AX5043_FIFOSTAT_FIFOCMD_Msk -#define AX5043_FIFOCMD_NOP (0x00U) -#define AX5043_FIFOCMD_ASK_COHERENT (0x01U) -#define AX5043_FIFOCMD_CLEAR_FIFOERR (0x02U) -#define AX5043_FIFOCMD_CLEAR_FIFODAT (0x03U) -#define AX5043_FIFOCMD_COMMIT (0x04U) -#define AX5043_FIFOCMD_ROLLBACK (0x05U) -#define AX5043_FIFOSTAT_FIFOEMPTY_Pos (0U) -#define AX5043_FIFOSTAT_FIFOEMPTY_Msk (0x1U << AX5043_FIFOSTAT_FIFOEMPTY_Pos) -#define AX5043_FIFOSTAT_FIFOEMPTY AX5043_FIFOSTAT_FIFOEMPTY_Msk -#define AX5043_FIFOSTAT_FIFOFULL_Pos (1U) -#define AX5043_FIFOSTAT_FIFOFULL_Msk (0x1U << AX5043_FIFOSTAT_FIFOFULL_Pos) -#define AX5043_FIFOSTAT_FIFOFULL AX5043_FIFOSTAT_FIFOFULL_Msk -#define AX5043_FIFOSTAT_FIFOUNDER_Pos (2U) -#define AX5043_FIFOSTAT_FIFOUNDER_Msk (0x1U << AX5043_FIFOSTAT_FIFOUNDER_Pos) -#define AX5043_FIFOSTAT_FIFOUNDER AX5043_FIFOSTAT_FIFOUNDER_Msk -#define AX5043_FIFOSTAT_FIFOOVER_Pos (3U) -#define AX5043_FIFOSTAT_FIFOOVER_Msk (0x1U << AX5043_FIFOSTAT_FIFOOVER_Pos) -#define AX5043_FIFOSTAT_FIFOOVER AX5043_FIFOSTAT_FIFOOVER_Msk -#define AX5043_FIFOSTAT_FIFOCNTTHR_Pos (4U) -#define AX5043_FIFOSTAT_FIFOCNTTHR_Msk (0x1U << AX5043_FIFOSTAT_FIFOCNTTHR_Pos) -#define AX5043_FIFOSTAT_FIFOCNTTHR AX5043_FIFOSTAT_FIFOCNTTHR_Msk -#define AX5043_FIFOSTAT_FIFOFREETHR_Pos (5U) -#define AX5043_FIFOSTAT_FIFOFREETHR_Msk (0x1U << AX5043_FIFOSTAT_FIFOFREETHR_Pos) -#define AX5043_FIFOSTAT_FIFOFREETHR AX5043_FIFOSTAT_FIFOFREETHR_Msk -#define AX5043_FIFOSTAT_FIFOAUTOCOMMIT_Pos (7U) -#define AX5043_FIFOSTAT_FIFOAUTOCOMMIT_Msk (0x1U << AX5043_FIFOSTAT_FIFOAUTOCOMMIT_Pos) -#define AX5043_FIFOSTAT_FIFOAUTOCOMMIT AX5043_FIFOSTAT_FIFOAUTOCOMMIT_Msk -/** @} */ - -/** - * @name AX5043 FIFODATA register fields - * @{ - */ -#define AX5043_FIFODATA_Pos (0U) -#define AX5043_FIFODATA_Msk (0xFFU << AX5043_FIFODATA_Pos) -#define AX5043_FIFODATA AX5043_FIFODATA_Msk -/** @} */ - -/** - * @name AX5043 FIFOCOUNT register fields - * @{ - */ -#define AX5043_FIFOCOUNT_Pos (0U) -#define AX5043_FIFOCOUNT_Msk (0x1FFU << AX5043_FIFOCOUNT_Pos) -#define AX5043_FIFOCOUNT AX5043_FIFOCOUNT_Msk -/** @} */ - -/** - * @name AX5043 FIFOFREE register fields - * @{ - */ -#define AX5043_FIFOFREE_Pos (0U) -#define AX5043_FIFOFREE_Msk (0x1FFU << AX5043_FIFOFREE_Pos) -#define AX5043_FIFOFREE AX5043_FIFOFREE_Msk -/** @} */ - -/** - * @name AX5043 FIFOTHRESH register fields - * @{ - */ -#define AX5043_FIFOTHRESH_Pos (0U) -#define AX5043_FIFOTHRESH_Msk (0x1FFU << AX5043_FIFOTHRESH_Pos) -#define AX5043_FIFOTHRESH AX5043_FIFOTHRESH_Msk -/** @} */ - -/** - * @name AX5043 PLLLOOP/PLLLOOPBOOST register fields - * @{ - */ -#define AX5043_PLLLOOP_FLT_Pos (0U) -#define AX5043_PLLLOOP_FLT_Msk (0x3U << AX5043_PLLLOOP_FLT_Pos) -#define AX5043_PLLLOOP_FLT AX5043_PLLLOOP_FLT_Msk -#define AX5043_FLT_EXTERN (0x0U) -#define AX5043_FLT_INTERN_100KHZ (0x1U) -#define AX5043_FLT_INTERN_200KHZ (0x2U) -#define AX5043_FLT_INTERN_300KHZ (0x3U) -#define AX5043_PLLLOOP_FLTEN_Pos (2U) -#define AX5043_PLLLOOP_FLTEN_Msk (0x1U << AX5043_PLLLOOP_FLTEN_Pos) -#define AX5043_PLLLOOP_FLTEN AX5043_PLLLOOP_FLTEN_Msk -#define AX5043_PLLLOOP_DIRECT_Pos (3U) -#define AX5043_PLLLOOP_DIRECT_Msk (0x1U << AX5043_PLLLOOP_DIRECT_Pos) -#define AX5043_PLLLOOP_DIRECT AX5043_PLLLOOP_DIRECT_Msk -#define AX5043_PLLLOOP_FREQSEL_Pos (7U) -#define AX5043_PLLLOOP_FREQSEL_Msk (0x1U << AX5043_PLLLOOP_FREQSEL_Pos) -#define AX5043_PLLLOOP_FREQSEL AX5043_PLLLOOP_FREQSEL_Msk -/** @} */ - -/** - * @name AX5043 PLLCPI/PLLCPIBOOST register fields - * @{ - */ -#define AX5043_PLLCPI_Pos (0U) -#define AX5043_PLLCPI_Msk (0xFFU << AX5043_PLLCPI_Pos) -#define AX5043_PLLCPI AX5043_PLLCPI_Msk -/** @} */ - -/** - * @name AX5043 PLLVCODIV register fields - * @{ - */ -#define AX5043_PLLVCODIV_REFDIV_Pos (0U) -#define AX5043_PLLVCODIV_REFDIV_Msk (0x3U << AX5043_PLLVCODIV_REFDIV_Pos) -#define AX5043_PLLVCODIV_REFDIV AX5043_PLLVCODIV_REFDIV_Msk -#define AX5043_REFDIV_XTAL_DIV1 (0x0U) -#define AX5043_REFDIV_XTAL_DIV2 (0x1U) -#define AX5043_REFDIV_XTAL_DIV4 (0x2U) -#define AX5043_REFDIV_XTAL_DIV8 (0x3U) -#define AX5043_PLLVCODIV_RFDIV_Pos (2U) -#define AX5043_PLLVCODIV_RFDIV_Msk (0x1U << AX5043_PLLVCODIV_RFDIV_Pos) -#define AX5043_PLLVCODIV_RFDIV AX5043_PLLVCODIV_RFDIV_Msk -#define AX5043_PLLVCODIV_VCOSEL_Pos (4U) -#define AX5043_PLLVCODIV_VCOSEL_Msk (0x1U << AX5043_PLLVCODIV_VCOSEL_Pos) -#define AX5043_PLLVCODIV_VCOSEL AX5043_PLLVCODIV_VCOSEL_Msk -#define AX5043_PLLVCODIV_VCO2INT_Pos (5U) -#define AX5043_PLLVCODIV_VCO2INT_Msk (0x1U << AX5043_PLLVCODIV_VCO2INT_Pos) -#define AX5043_PLLVCODIV_VCO2INT AX5043_PLLVCODIV_VCO2INT_Msk -#define AX5043_PLLVCODIV_VCOIMAN_Pos (6U) -#define AX5043_PLLVCODIV_VCOIMAN_Msk (0x1U << AX5043_PLLVCODIV_VCOIMAN_Pos) -#define AX5043_PLLVCODIV_VCOIMAN AX5043_PLLVCODIV_VCOIMAN_Msk -/** @} */ - -/** - * @name AX5043 PLLRANGINGA/PLLRANGINGB register fields - * @{ - */ -#define AX5043_PLLRANGING_VCOR_Pos (0U) -#define AX5043_PLLRANGING_VCOR_Msk (0xFU << AX5043_PLLRANGING_VCOR_Pos) -#define AX5043_PLLRANGING_VCOR AX5043_PLLRANGING_VCOR_Msk -#define AX5043_PLLRANGING_RNGSTART_Pos (4U) -#define AX5043_PLLRANGING_RNGSTART_Msk (0x1U << AX5043_PLLRANGING_RNGSTART_Pos) -#define AX5043_PLLRANGING_RNGSTART AX5043_PLLRANGING_RNGSTART_Msk -#define AX5043_PLLRANGING_RNGERR_Pos (5U) -#define AX5043_PLLRANGING_RNGERR_Msk (0x1U << AX5043_PLLRANGING_RNGERR_Pos) -#define AX5043_PLLRANGING_RNGERR AX5043_PLLRANGING_RNGERR_Msk -#define AX5043_PLLRANGING_PLLLOCK_Pos (6U) -#define AX5043_PLLRANGING_PLLLOCK_Msk (0x1U << AX5043_PLLRANGING_PLLLOCK_Pos) -#define AX5043_PLLRANGING_PLLLOCK AX5043_PLLRANGING_PLLLOCK_Msk -#define AX5043_PLLRANGING_STICKYLOCK_Pos (7U) -#define AX5043_PLLRANGING_STICKYLOCK_Msk (0x1U << AX5043_PLLRANGING_STICKYLOCK_Pos) -#define AX5043_PLLRANGING_STICKYLOCK AX5043_PLLRANGING_STICKYLOCK_Msk -/** @} */ - -/** - * @name AX5043 FREQA/FREQB register fields - * @{ - */ -#define AX5043_FREQ_Pos (0U) -#define AX5043_FREQ_Msk (0xFFFFFFFFU << AX5043_FREQ_Pos) -#define AX5043_FREQ AX5043_FREQ_Msk -/** @} */ - -/** - * @name AX5043 RSSI register fields - * @{ - */ -#define AX5043_RSSI_Pos (0U) -#define AX5043_RSSI_Msk (0xFFU << AX5043_RSSI_Pos) -#define AX5043_RSSI AX5043_RSSI_Msk -/** @} */ - -/** - * @name AX5043 BGNDRSSI register fields - * @{ - */ -#define AX5043_BGNDRSSI_Pos (0U) -#define AX5043_BGNDRSSI_Msk (0xFFU << AX5043_BGNDRSSI_Pos) -#define AX5043_BGNDRSSI AX5043_BGNDRSSI_Msk -/** @} */ - -/** - * @name AX5043 DIVERSITY register fields - * @{ - */ -#define AX5043_DIVERSITY_DIVENA_Pos (0U) -#define AX5043_DIVERSITY_DIVENA_Msk (0x1U << AX5043_DIVERSITY_DIVENA_Pos) -#define AX5043_DIVERSITY_DIVENA AX5043_DIVERSITY_DIVENA_Msk -#define AX5043_DIVERSITY_ANTSEL_Pos (1U) -#define AX5043_DIVERSITY_ANTSEL_Msk (0x1U << AX5043_DIVERSITY_ANTSEL_Pos) -#define AX5043_DIVERSITY_ANTSEL AX5043_DIVERSITY_ANTSEL_Msk -/** @} */ - -/** - * @name AX5043 AGCCOUNTER register fields - * @{ - */ -#define AX5043_AGCCOUNTER_Pos (0U) -#define AX5043_AGCCOUNTER_Msk (0xFFU << AX5043_AGCCOUNTER_Pos) -#define AX5043_AGCCOUNTER AX5043_AGCCOUNTER_Msk -/** @} */ - -/** - * @name AX5043 TRKDATARATE register fields - * @{ - */ -#define AX5043_TRKDATARATE_Pos (0U) -#define AX5043_TRKDATARATE_Msk (0xFFFFFFU << AX5043_TRKDATARATE_Pos) -#define AX5043_TRKDATARATE AX5043_TRKDATARATE_Msk -/** @} */ - -/** - * @name AX5043 TRKAMPL register fields - * @{ - */ -#define AX5043_TRKAMPL_Pos (0U) -#define AX5043_TRKAMPL_Msk (0xFFFFU << AX5043_TRKAMPL_Pos) -#define AX5043_TRKAMPL AX5043_TRKAMPL_Msk -/** @} */ - -/** - * @name AX5043 TRKPHASE register fields - * @{ - */ -#define AX5043_TRKPHASE_Pos (0U) -#define AX5043_TRKPHASE_Msk (0xFFFU << AX5043_TRKPHASE_Pos) -#define AX5043_TRKPHASE AX5043_TRKPHASE_Msk -/** @} */ - -/** - * @name AX5043 TRKRFFREQ register fields - * @{ - */ -#define AX5043_TRKRFFREQ_Pos (0U) -#define AX5043_TRKRFFREQ_Msk (0xFFFFFU << AX5043_TRKRFFREQ_Pos) -#define AX5043_TRKRFFREQ AX5043_TRKRFFREQ_Msk -/** @} */ - -/** - * @name AX5043 TRKFREQ register fields - * @{ - */ -#define AX5043_TRKFREQ_Pos (0U) -#define AX5043_TRKFREQ_Msk (0xFFFFU << AX5043_TRKFREQ_Pos) -#define AX5043_TRKFREQ AX5043_TRKFREQ_Msk -/** @} */ - -/** - * @name AX5043 TRKFSKDEMOD register fields - * @{ - */ -#define AX5043_TRKFSKDEMOD_Pos (0U) -#define AX5043_TRKFSKDEMOD_Msk (0x3FFFU << AX5043_TRKFSKDEMOD_Pos) -#define AX5043_TRKFSKDEMOD AX5043_TRKFSKDEMOD_Msk -/** @} */ - -/** - * @name AX5043 TRKAFSKDEMOD register fields - * @{ - */ -#define AX5043_TRKAFSKDEMOD_Pos (0U) -#define AX5043_TRKAFSKDEMOD_Msk (0xFFFFU << AX5043_TRKAFSKDEMOD_Pos) -#define AX5043_TRKAFSKDEMOD AX5043_TRKAFSKDEMOD_Msk -/** @} */ - -/** - * @name AX5043 Tracking register reset fields - * - * @note For writes to TRKDATARATE, TRKAMPL, TRKPHASE registers - * TODO: Verify these are correct? - * @{ - */ -#define AX5043_TRACKING_DTRKRESET_Pos (3U) -#define AX5043_TRACKING_DTRKRESET_Msk (0x1U << AX5043_TRACKING_DTRKRESET_Pos) -#define AX5043_TRACKING_DTRKRESET AX5043_TRACKING_DTRKRESET_Msk -#define AX5043_TRACKING_ATRKRESET_Pos (4U) -#define AX5043_TRACKING_ATRKRESET_Msk (0x1U << AX5043_TRACKING_ATRKRESET_Pos) -#define AX5043_TRACKING_ATRKRESET AX5043_TRACKING_ATRKRESET_Msk -#define AX5043_TRACKING_PTRKRESET_Pos (5U) -#define AX5043_TRACKING_PTRKRESET_Msk (0x1U << AX5043_TRACKING_PTRKRESET_Pos) -#define AX5043_TRACKING_PTRKRESET AX5043_TRACKING_PTRKRESET_Msk -#define AX5043_TRACKING_RTRKRESET_Pos (6U) -#define AX5043_TRACKING_RTRKRESET_Msk (0x1U << AX5043_TRACKING_RTRKRESET_Pos) -#define AX5043_TRACKING_RTRKRESET AX5043_TRACKING_RTRKRESET_Msk -#define AX5043_TRACKING_FTRKRESET_Pos (7U) -#define AX5043_TRACKING_FTRKRESET_Msk (0x1U << AX5043_TRACKING_FTRKRESET_Pos) -#define AX5043_TRACKING_FTRKRESET AX5043_TRACKING_FTRKRESET_Msk -/** @} */ - -/** - * @name AX5043 TIMER register fields - * @{ - */ -#define AX5043_TIMER_Pos (0U) -#define AX5043_TIMER_Msk (0xFFFFFFU << AX5043_TIMER_Pos) -#define AX5043_TIMER AX5043_TIMER_Msk -/** @} */ - -/** - * @name AX5043 WAKEUPTIMER register fields - * @{ - */ -#define AX5043_WAKEUPTIMER_Pos (0U) -#define AX5043_WAKEUPTIMER_Msk (0xFFFFU << AX5043_WAKEUPTIMER_Pos) -#define AX5043_WAKEUPTIMER AX5043_WAKEUPTIMER_Msk -/** @} */ - -/** - * @name AX5043 WAKEUP register fields - * @{ - */ -#define AX5043_WAKEUP_Pos (0U) -#define AX5043_WAKEUP_Msk (0xFFFFU << AX5043_WAKEUP_Pos) -#define AX5043_WAKEUP AX5043_WAKEUP_Msk -/** @} */ - -/** - * @name AX5043 WAKEUPFREQ register fields - * @{ - */ -#define AX5043_WAKEUPFREQ_Pos (0U) -#define AX5043_WAKEUPFREQ_Msk (0xFFFFU << AX5043_WAKEUPFREQ_Pos) -#define AX5043_WAKEUPFREQ AX5043_WAKEUPFREQ_Msk -/** @} */ - -/** - * @name AX5043 WAKEUPXOEARLY register fields - * @{ - */ -#define AX5043_WAKEUPXOEARLY_Pos (0U) -#define AX5043_WAKEUPXOEARLY_Msk (0xFFU << AX5043_WAKEUPXOEARLY_Pos) -#define AX5043_WAKEUPXOEARLY AX5043_WAKEUPXOEARLY_Msk -/** @} */ - -/** - * @name AX5043 IFFREQ register fields - * @{ - */ -#define AX5043_IFFREQ_Pos (0U) -#define AX5043_IFFREQ_Msk (0xFFFFU << AX5043_IFFREQ_Pos) -#define AX5043_IFFREQ AX5043_IFFREQ_Msk -/** @} */ - -/** - * @name AX5043 DECIMATION register fields - * @{ - */ -#define AX5043_DECIMATION_Pos (0U) -#define AX5043_DECIMATION_Msk (0x7F << AX5043_DECIMATION_Pos) -#define AX5043_DECIMATION AX5043_DECIMATION_Msk -/** @} */ - -/** - * @name AX5043 RXDATARATE register fields - * @{ - */ -#define AX5043_RXDATARATE_Pos (0U) -#define AX5043_RXDATARATE_Msk (0xFFFFFFU << AX5043_RXDATARATE_Pos) -#define AX5043_RXDATARATE AX5043_RXDATARATE_Msk -/** @} */ - -/** - * @name AX5043 MAXDROFFSET register fields - * @{ - */ -#define AX5043_MAXDROFFSET_Pos (0U) -#define AX5043_MAXDROFFSET_Msk (0xFFFFFFU << AX5043_MAXDROFFSET_Pos) -#define AX5043_MAXDROFFSET AX5043_MAXDROFFSET_Msk -/** @} */ - -/** - * @name AX5043 MAXRFOFFSET register fields - * @{ - */ -#define AX5043_MAXRFOFFSET_Pos (0U) -#define AX5043_MAXRFOFFSET_Msk (0xFFFFFU << AX5043_MAXRFOFFSET_Pos) -#define AX5043_MAXRFOFFSET AX5043_MAXRFOFFSET_Msk -#define AX5043_MAXRFOFFSET_FREQOFFSCORR_Pos (23U) -#define AX5043_MAXRFOFFSET_FREQOFFSCORR_Msk (0x1U << AX5043_MAXRFOFFSET_FREQOFFSCORR_Pos) -#define AX5043_MAXRFOFFSET_FREQOFFSCORR AX5043_MAXRFOFFSET_FREQOFFSCORR_Msk -/** @} */ - -/** - * @name AX5043 FSKDMAX register fields - * @{ - */ -#define AX5043_FSKDMAX_Pos (0U) -#define AX5043_FSKDMAX_Msk (0xFFFFU << AX5043_FSKDMAX_Pos) -#define AX5043_FSKDMAX AX5043_FSKDMAX_Msk -/** @} */ - -/** - * @name AX5043 FSKDMIN register fields - * @{ - */ -#define AX5043_FSKDMIN_Pos (0U) -#define AX5043_FSKDMIN_Msk (0xFFFFU << AX5043_FSKDMIN_Pos) -#define AX5043_FSKDMIN AX5043_FSKDMIN_Msk -/** @} */ - -/** - * @name AX5043 AFSKSPACE register fields - * TODO: Verify the field width here - * @{ - */ -#define AX5043_AFSKSPACE_Pos (0U) -#define AX5043_AFSKSPACE_Msk (0xFFFFU << AX5043_AFSKSPACE_Pos) -#define AX5043_AFSKSPACE AX5043_AFSKSPACE_Msk -/** @} */ - -/** - * @name AX5043 AFSKMARK register fields - * TODO: Verify the field width here - * @{ - */ -#define AX5043_AFSKMARK_Pos (0U) -#define AX5043_AFSKMARK_Msk (0xFFFFU << AX5043_AFSKMARK_Pos) -#define AX5043_AFSKMARK AX5043_AFSKMARK_Msk -/** @} */ - -/** - * @name AX5043 AFSKCTRL register fields - * @{ - */ -#define AX5043_AFSKCTRL_AFSKSHIFT_Pos (0U) -#define AX5043_AFSKCTRL_AFSKSHIFT_Msk (0x1FU << AX5043_AFSKCTRL_AFSKSHIFT_Pos) -#define AX5043_AFSKCTRL_AFSKSHIFT AX5043_AFSKCTRL_AFSKSHIFT_Msk -/** @} */ - -/** - * @name AX5043 AMPLFILTER register fields - * @{ - */ -#define AX5043_AMPLFILTER_Pos (0U) -#define AX5043_AMPLFILTER_Msk (0xFU << AX5043_AMPLFILTER_Pos) -#define AX5043_AMPLFILTER AX5043_AMPLFILTER_Msk -/** @} */ - -/** - * @name AX5043 FREQUENCYLEAK register fields - * @{ - */ -#define AX5043_FREQUENCYLEAK_Pos (0U) -#define AX5043_FREQUENCYLEAK_Msk (0xFU << AX5043_FREQUENCYLEAK_Pos) -#define AX5043_FREQUENCYLEAK AX5043_FREQUENCYLEAK_Msk -/** @} */ - -/** - * @name AX5043 RXPARAMSETS register fields - * @{ - */ -#define AX5043_RXPARAMSETS_RXPS0_Pos (0U) -#define AX5043_RXPARAMSETS_RXPS0_Msk (0x3U << AX5043_RXPARAMSETS_RXPS0_Pos) -#define AX5043_RXPARAMSETS_RXPS0 AX5043_RXPARAMSETS_RXPS0_Msk -#define AX5043_RXPARAMSETS_RXPS1_Pos (2U) -#define AX5043_RXPARAMSETS_RXPS1_Msk (0x3U << AX5043_RXPARAMSETS_RXPS1_Pos) -#define AX5043_RXPARAMSETS_RXPS1 AX5043_RXPARAMSETS_RXPS1_Msk -#define AX5043_RXPARAMSETS_RXPS2_Pos (4U) -#define AX5043_RXPARAMSETS_RXPS2_Msk (0x3U << AX5043_RXPARAMSETS_RXPS2_Pos) -#define AX5043_RXPARAMSETS_RXPS2 AX5043_RXPARAMSETS_RXPS2_Msk -#define AX5043_RXPARAMSETS_RXPS3_Pos (6U) -#define AX5043_RXPARAMSETS_RXPS3_Msk (0x3U << AX5043_RXPARAMSETS_RXPS3_Pos) -#define AX5043_RXPARAMSETS_RXPS3 AX5043_RXPARAMSETS_RXPS3_Msk -/** @} */ - -/** - * @name AX5043 RXPARAMCURSET register fields - * @{ - */ -#define AX5043_RXPARAMCURSET_RXSI_Pos (0U) -#define AX5043_RXPARAMCURSET_RXSI_Msk (0x3U << AX5043_RXPARAMCURSET_RXSI_Pos) -#define AX5043_RXPARAMCURSET_RXSI AX5043_RXPARAMCURSET_RXSI_Msk -#define AX5043_RXPARAMCURSET_RXSN_Pos (2U) -#define AX5043_RXPARAMCURSET_RXSN_Msk (0x3U << AX5043_RXPARAMCURSET_RXSN_Pos) -#define AX5043_RXPARAMCURSET_RXSN AX5043_RXPARAMCURSET_RXSN_Msk -#define AX5043_RXPARAMCURSET_RXSI_FUNC_Pos (4U) -#define AX5043_RXPARAMCURSET_RXSI_FUNC_Msk (0x1U << AX5043_RXPARAMCURSET_RXSI_FUNC_Pos) -#define AX5043_RXPARAMCURSET_RXSI_FUNC AX5043_RXPARAMCURSET_RXSI_FUNC_Msk -/** @} */ - -/** - * @name AX5043 AGCGAIN 0/1/2/3 register fields - * @{ - */ -#define AX5043_AGCGAIN_AGCATTACK_Pos (0U) -#define AX5043_AGCGAIN_AGCATTACK_Msk (0xFU << AX5043_AGCGAIN_AGCATTACK_Pos) -#define AX5043_AGCGAIN_AGCATTACK AX5043_AGCGAIN_AGCATTACK_Msk -#define AX5043_AGCGAIN_AGCDECAY_Pos (4U) -#define AX5043_AGCGAIN_AGCDECAY_Msk (0xFU << AX5043_AGCGAIN_AGCDECAY_Pos) -#define AX5043_AGCGAIN_AGCDECAY AX5043_AGCGAIN_AGCDECAY_Msk -/** @} */ - -/** - * @name AX5043 AGCTARGET 0/1/2/3 register fields - * @{ - */ -#define AX5043_AGCTARGET_Pos (0U) -#define AX5043_AGCTARGET_Msk (0xFFU << AX5043_AGCTARGET_Pos) -#define AX5043_AGCTARGET AX5043_AGCTARGET_Msk -/** @} */ - -/** - * @name AX5043 AGCAHYST 0/1/2/3 register fields - * @{ - */ -#define AX5043_AGCAHYST_Pos (0U) -#define AX5043_AGCAHYST_Msk (0x7U << AX5043_AGCAHYST_Pos) -#define AX5043_AGCAHYST AX5043_AGCAHYST_Msk -/** @} */ - -/** - * @name AX5043 AGCMINMAX 0/1/2/3 register fields - * @{ - */ -#define AX5043_AGCMINMAX_AGCMINDA_Pos (0U) -#define AX5043_AGCMINMAX_AGCMINDA_Msk (0x7U << AX5043_AGCMINMAX_AGCMINDA_Pos) -#define AX5043_AGCMINMAX_AGCMINDA AX5043_AGCMINMAX_AGCMINDA_Msk -#define AX5043_AGCMINMAX_AGCMAXDA_Pos (4U) -#define AX5043_AGCMINMAX_AGCMAXDA_Msk (0x7U << AX5043_AGCMINMAX_AGCMAXDA_Pos) -#define AX5043_AGCMINMAX_AGCMAXDA AX5043_AGCMINMAX_AGCMAXDA_Msk -/** @} */ - -/** - * @name AX5043 TIMEGAIN 0/1/2/3 register fields - * @{ - */ -#define AX5043_TIMEGAIN_E_Pos (0U) -#define AX5043_TIMEGAIN_E_Msk (0xFU << AX5043_TIMEGAIN_E_Pos) -#define AX5043_TIMEGAIN_E AX5043_TIMEGAIN_E_Msk -#define AX5043_TIMEGAIN_M_Pos (4U) -#define AX5043_TIMEGAIN_M_Msk (0xFU << AX5043_TIMEGAIN_M_Pos) -#define AX5043_TIMEGAIN_M AX5043_TIMEGAIN_M_Msk -/** @} */ - -/** - * @name AX5043 DRGAIN 0/1/2/3 register fields - * @{ - */ -#define AX5043_DRGAIN_E_Pos (0U) -#define AX5043_DRGAIN_E_Msk (0xFU << AX5043_DRGAIN_E_Pos) -#define AX5043_DRGAIN_E AX5043_DRGAIN_E_Msk -#define AX5043_DRGAIN_M_Pos (4U) -#define AX5043_DRGAIN_M_Msk (0xFU << AX5043_DRGAIN_M_Pos) -#define AX5043_DRGAIN_M AX5043_DRGAIN_M_Msk -/** @} */ - -/** - * @name AX5043 PHASEGAIN 0/1/2/3 register fields - * @{ - */ -#define AX5043_PHASEGAIN_Pos (0U) -#define AX5043_PHASEGAIN_Msk (0xFU << AX5043_PHASEGAIN_Pos) -#define AX5043_PHASEGAIN AX5043_PHASEGAIN_Msk -#define AX5043_PHASEGAIN_FILTERIDX_Pos (6U) -#define AX5043_PHASEGAIN_FILTERIDX_Msk (0x3U << AX5043_PHASEGAIN_FILTERIDX_Pos) -#define AX5043_PHASEGAIN_FILTERIDX AX5043_PHASEGAIN_FILTERIDX_Msk -/** @} */ - -/** - * @name AX5043 FREQGAINA 0/1/2/3 register fields - * @{ - */ -#define AX5043_FREQGAINA_Pos (0U) -#define AX5043_FREQGAINA_Msk (0xFU << AX5043_FREQGAINA_Pos) -#define AX5043_FREQGAINA AX5043_FREQGAINA_Msk -#define AX5043_FREQGAINA_FREQAMPLGATE_Pos (4U) -#define AX5043_FREQGAINA_FREQAMPLGATE_Msk (0x1U << AX5043_FREQGAINA_FREQAMPLGATE_Pos) -#define AX5043_FREQGAINA_FREQAMPLGATE AX5043_FREQGAINA_FREQAMPLGATE_Msk -#define AX5043_FREQGAINA_FREQHALFMOD_Pos (5U) -#define AX5043_FREQGAINA_FREQHALFMOD_Msk (0x1U << AX5043_FREQGAINA_FREQHALFMOD_Pos) -#define AX5043_FREQGAINA_FREQHALFMOD AX5043_FREQGAINA_FREQHALFMOD_Msk -#define AX5043_FREQGAINA_FREQMODULO_Pos (6U) -#define AX5043_FREQGAINA_FREQMODULO_Msk (0x1U << AX5043_FREQGAINA_FREQMODULO_Pos) -#define AX5043_FREQGAINA_FREQMODULO AX5043_FREQGAINA_FREQMODULO_Msk -#define AX5043_FREQGAINA_FREQLIM_Pos (7U) -#define AX5043_FREQGAINA_FREQLIM_Msk (0x1U << AX5043_FREQGAINA_FREQLIM_Pos) -#define AX5043_FREQGAINA_FREQLIM AX5043_FREQGAINA_FREQLIM_Msk -/** @} */ - -/** - * @name AX5043 FREQGAINB 0/1/2/3 register fields - * @{ - */ -#define AX5043_FREQGAINB_Pos (0U) -#define AX5043_FREQGAINB_Msk (0x1FU << AX5043_FREQGAINB_Pos) -#define AX5043_FREQGAINB AX5043_FREQGAINB_Msk -#define AX5043_FREQGAINB_FREQAVG_Pos (6U) -#define AX5043_FREQGAINB_FREQAVG_Msk (0x1U << AX5043_FREQGAINB_FREQAVG_Pos) -#define AX5043_FREQGAINB_FREQAVG AX5043_FREQGAINB_FREQAVG_Msk -#define AX5043_FREQGAINB_FREQFREEZE_Pos (7U) -#define AX5043_FREQGAINB_FREQFREEZE_Msk (0x1U << AX5043_FREQGAINB_FREQFREEZE_Pos) -#define AX5043_FREQGAINB_FREQFREEZE AX5043_FREQGAINB_FREQFREEZE_Msk -/** @} */ - -/** - * @name AX5043 FREQGAINC 0/1/2/3 register fields - * @{ - */ -#define AX5043_FREQGAINC_Pos (0U) -#define AX5043_FREQGAINC_Msk (0x1FU << AX5043_FREQGAINC_Pos) -#define AX5043_FREQGAINC AX5043_FREQGAINC_Msk -/** @} */ - -/** - * @name AX5043 FREQGAIND 0/1/2/3 register fields - * @{ - */ -#define AX5043_FREQGAIND_Pos (0U) -#define AX5043_FREQGAIND_Msk (0x1FU << AX5043_FREQGAIND_Pos) -#define AX5043_FREQGAIND AX5043_FREQGAIND_Msk -#define AX5043_FREQGAIND_RFFREQFREEZE_Pos (7U) -#define AX5043_FREQGAIND_RFFREQFREEZE_Msk (0x1U << AX5043_FREQGAIND_RFFREQFREEZE_Pos) -#define AX5043_FREQGAIND_RFFREQFREEZE AX5043_FREQGAIND_RFFREQFREEZE_Msk -/** @} */ - -/** - * @name AX5043 AMPLGAIN 0/1/2/3 register fields - * @{ - */ -#define AX5043_AMPLGAIN_Pos (0U) -#define AX5043_AMPLGAIN_Msk (0xFU << AX5043_AMPLGAIN_Pos) -#define AX5043_AMPLGAIN AX5043_AMPLGAIN_Msk -#define AX5043_AMPLGAIN_AMPLAGC_Pos (6U) -#define AX5043_AMPLGAIN_AMPLAGC_Msk (0x1U << AX5043_AMPLGAIN_AMPLAGC_Pos) -#define AX5043_AMPLGAIN_AMPLAGC AX5043_AMPLGAIN_AMPLAGC_Msk -#define AX5043_AMPLGAIN_AMPLAVG_Pos (7U) -#define AX5043_AMPLGAIN_AMPLAVG_Msk (0x1U << AX5043_AMPLGAIN_AMPLAVG_Pos) -#define AX5043_AMPLGAIN_AMPLAVG AX5043_AMPLGAIN_AMPLAVG_Msk -/** @} */ - -/** - * @name AX5043 FREQDEV 0/1/2/3 register fields - * @{ - */ -#define AX5043_FREQDEV_Pos (0U) -#define AX5043_FREQDEV_Msk (0xFFFU << AX5043_FREQDEV_Pos) -#define AX5043_FREQDEV AX5043_FREQDEV_Msk -/** @} */ - -/** - * @name AX5043 FOURFSK register fields - * @{ - */ -#define AX5043_FOURFSK_DEVDECAY_Pos (0U) -#define AX5043_FOURFSK_DEVDECAY_Msk (0xFU << AX5043_FOURFSK_DEVDECAY_Pos) -#define AX5043_FOURFSK_DEVDECAY AX5043_FOURFSK_DEVDECAY_Msk -#define AX5043_FOURFSK_DEVUPDATE_Pos (4U) -#define AX5043_FOURFSK_DEVUPDATE_Msk (0x1U << AX5043_FOURFSK_DEVUPDATE_Pos) -#define AX5043_FOURFSK_DEVUPDATE AX5043_FOURFSK_DEVUPDATE_Msk -/** @} */ - -/** - * @name AX5043 BBOFFSRES 0/1/2/3 register fields - * @{ - */ -#define AX5043_BBOFFSRES_RESINTA_Pos (0U) -#define AX5043_BBOFFSRES_RESINTA_Msk (0xFU << AX5043_BBOFFSRES_RESINTA_Pos) -#define AX5043_BBOFFSRES_RESINTA AX5043_BBOFFSRES_RESINTA_Msk -#define AX5043_BBOFFSRES_RESINTB_Pos (4U) -#define AX5043_BBOFFSRES_RESINTB_Msk (0xFU << AX5043_BBOFFSRES_RESINTB_Pos) -#define AX5043_BBOFFSRES_RESINTB AX5043_BBOFFSRES_RESINTB_Msk -/** @} */ - -/** - * @name AX5043 MODCFGF register fields - * @{ - */ -#define AX5043_MODCFGF_FREQSHAPE_Pos (0U) -#define AX5043_MODCFGF_FREQSHAPE_Msk (0x3U << AX5043_MODCFGF_FREQSHAPE_Pos) -#define AX5043_MODCFGF_FREQSHAPE AX5043_MODCFGF_FREQSHAPE_Msk -#define AX5043_FREQSHAPE_EXTERN_LOOP_FILT (0x0U) -#define AX5043_FREQSHAPE_GAUSS_BT_0_3 (0x2U) -#define AX5043_FREQSHAPE_GAUSS_BT_0_5 (0x3U) -/** @} */ - -/** - * @name AX5043 FSKDEV register fields - * @{ - */ -#define AX5043_FSKDEV_Pos (0U) -#define AX5043_FSKDEV_Msk (0xFFFFFFU << AX5043_FSKDEV_Pos) -#define AX5043_FSKDEV AX5043_FSKDEV_Msk -#define AX5043_FSKDEV_FMSHIFT_Pos (0U) -#define AX5043_FSKDEV_FMSHIFT_Msk (0x3U << AX5043_FSKDEV_FMSHIFT_Pos) -#define AX5043_FSKDEV_FMSHIFT AX5043_FSKDEV_FMSHIFT_Msk -#define AX5043_FSKDEV_FMINPUT_Pos (8U) -#define AX5043_FSKDEV_FMINPUT_Msk (0x3U << AX5043_FSKDEV_FMINPUT_Pos) -#define AX5043_FSKDEV_FMINPUT AX5043_FSKDEV_FMINPUT_Msk -#define AX5043_FSKDEV_FMSEXT_Pos (14U) -#define AX5043_FSKDEV_FMSEXT_Msk (0x1U << AX5043_FSKDEV_FMSEXT_Pos) -#define AX5043_FSKDEV_FMSEXT AX5043_FSKDEV_FMSEXT_Msk -#define AX5043_FSKDEV_FMOFFS_Pos (15U) -#define AX5043_FSKDEV_FMOFFS_Msk (0x1U << AX5043_FSKDEV_FMOFFS_Pos) -#define AX5043_FSKDEV_FMOFFS AX5043_FSKDEV_FMOFFS_Msk -/** @} */ - -/** - * @name AX5043 MODCFGA register fields - * @{ - */ -#define AX5043_MODCFGA_TXDIFF_Pos (0U) -#define AX5043_MODCFGA_TXDIFF_Msk (0x1U << AX5043_MODCFGA_TXDIFF_Pos) -#define AX5043_MODCFGA_TXDIFF AX5043_MODCFGA_TXDIFF_Msk -#define AX5043_MODCFGA_TXSE_Pos (1U) -#define AX5043_MODCFGA_TXSE_Msk (0x1U << AX5043_MODCFGA_TXSE_Pos) -#define AX5043_MODCFGA_TXSE AX5043_MODCFGA_TXSE_Msk -#define AX5043_MODCFGA_AMPLSHAPE_Pos (2U) -#define AX5043_MODCFGA_AMPLSHAPE_Msk (0x1U << AX5043_MODCFGA_AMPLSHAPE_Pos) -#define AX5043_MODCFGA_AMPLSHAPE AX5043_MODCFGA_AMPLSHAPE_Msk -#define AX5043_AMPLSHAPE_UNSHAPED (0x0U) -#define AX5043_AMPLSHAPE_RAISEDCOS (0x1U) -#define AX5043_MODCFGA_SLOWRAMP_Pos (4U) -#define AX5043_MODCFGA_SLOWRAMP_Msk (0x3U << AX5043_MODCFGA_SLOWRAMP_Pos) -#define AX5043_MODCFGA_SLOWRAMP AX5043_MODCFGA_SLOWRAMP_Msk -#define AX5043_SLOWRAMP_1BIT (0x0U) -#define AX5043_SLOWRAMP_2BIT (0x1U) -#define AX5043_SLOWRAMP_4BIT (0x2U) -#define AX5043_SLOWRAMP_8BIT (0x3U) -#define AX5043_MODCFGA_PTTLCKGATE_Pos (6U) -#define AX5043_MODCFGA_PTTLCKGATE_Msk (0x1U << AX5043_MODCFGA_PTTLCKGATE_Pos) -#define AX5043_MODCFGA_PTTLCKGATE AX5043_MODCFGA_PTTLCKGATE_Msk -#define AX5043_MODCFGA_BROWNGATE_Pos (7U) -#define AX5043_MODCFGA_BROWNGATE_Msk (0x1U << AX5043_MODCFGA_BROWNGATE_Pos) -#define AX5043_MODCFGA_BROWNGATE AX5043_MODCFGA_BROWNGATE_Msk -/** @} */ - -/** - * @name AX5043 TXRATE register fields - * @{ - */ -#define AX5043_TXRATE_Pos (0U) -#define AX5043_TXRATE_Msk (0xFFFFFFU << AX5043_TXRATE_Pos) -#define AX5043_TXRATE AX5043_TXRATE_Msk -/** @} */ - -/** - * @name AX5043 TXPWRCOEFF A/B/C/D/E register fields - * @{ - */ -#define AX5043_TXPWRCOEFF_Pos (0U) -#define AX5043_TXPWRCOEFF_Msk (0xFFFFU << AX5043_TXPWRCOEFF_Pos) -#define AX5043_TXPWRCOEFF AX5043_TXPWRCOEFF_Msk -/** @} */ - -/** - * @name AX5043 PLLVCOI register fields - * @{ - */ -#define AX5043_PLLVCOI_VCOI_Pos (0U) -#define AX5043_PLLVCOI_VCOI_Msk (0x3FU << AX5043_PLLVCOI_VCOI_Pos) -#define AX5043_PLLVCOI_VCOI AX5043_PLLVCOI_VCOI_Msk -#define AX5043_PLLVCOI_VCOIE_Pos (7U) -#define AX5043_PLLVCOI_VCOIE_Msk (0x1U << AX5043_PLLVCOI_VCOIE_Pos) -#define AX5043_PLLVCOI_VCOIE AX5043_PLLVCOI_VCOIE_Msk -/** @} */ - -/** - * @name AX5043 PLLVCOIR register fields - * @{ - */ -#define AX5043_PLLVCOIR_Pos (0U) -#define AX5043_PLLVCOIR_Msk (0x3FU << AX5043_PLLVCOIR_Pos) -#define AX5043_PLLVCOIR AX5043_PLLVCOIR_Msk -/** @} */ - -/** - * @name AX5043 PLLLOCKDET register fields - * @{ - */ -#define AX5043_PLLLOCKDET_LOCKDETDLY_Pos (0U) -#define AX5043_PLLLOCKDET_LOCKDETDLY_Msk (0x3U << AX5043_PLLLOCKDET_LOCKDETDLY_Pos) -#define AX5043_PLLLOCKDET_LOCKDETDLY AX5043_PLLLOCKDET_LOCKDETDLY_Msk -#define AX5043_LOCKDETDLY_6NS (0x0U) -#define AX5043_LOCKDETDLY_9NS (0x1U) -#define AX5043_LOCKDETDLY_12NS (0x2U) -#define AX5043_LOCKDETDLY_14NS (0x3U) -#define AX5043_PLLLOCKDET_LOCKDETDLYM_Pos (2U) -#define AX5043_PLLLOCKDET_LOCKDETDLYM_Msk (0x1U << AX5043_PLLLOCKDET_LOCKDETDLYM_Pos) -#define AX5043_PLLLOCKDET_LOCKDETDLYM AX5043_PLLLOCKDET_LOCKDETDLYM_Msk -#define AX5043_PLLLOCKDET_LOCKDETDLYR_Pos (6U) -#define AX5043_PLLLOCKDET_LOCKDETDLYR_Msk (0x3U << AX5043_PLLLOCKDET_LOCKDETDLYR_Pos) -#define AX5043_PLLLOCKDET_LOCKDETDLYR AX5043_PLLLOCKDET_LOCKDETDLYR_Msk -/** @} */ - -/** - * @name AX5043 PLLRNGCLK register fields - * @{ - */ -#define AX5043_PLLRNGCLK_Pos (0U) -#define AX5043_PLLRNGCLK_Msk (0x7U << AX5043_PLLRNGCLK_Pos) -#define AX5043_PLLRNGCLK AX5043_PLLRNGCLK_Msk -/** @} */ - -/** - * @name AX5043 XTALCAP register fields - * @{ - */ -#define AX5043_XTALCAP_Pos (0U) -#define AX5043_XTALCAP_Msk (0xFFU << AX5043_XTALCAP_Pos) -#define AX5043_XTALCAP AX5043_XTALCAP_Msk -/** @} */ - -/** - * @name AX5043 BBTUNE register fields - * @{ - */ -#define AX5043_BBTUNE_Pos (0U) -#define AX5043_BBTUNE_Msk (0xFU << AX5043_BBTUNE_Pos) -#define AX5043_BBTUNE AX5043_BBTUNE_Msk -#define AX5043_BBTUNE_BBTUNERUN_Pos (4U) -#define AX5043_BBTUNE_BBTUNERUN_Msk (0x1U << AX5043_BBTUNE_BBTUNERUN_Pos) -#define AX5043_BBTUNE_BBTUNERUN AX5043_BBTUNE_BBTUNERUN_Msk -/** @} */ - -/** - * @name AX5043 BBOFFSCAP register fields - * @{ - */ -#define AX5043_BBOFFSCAP_CAPINTA_Pos (0U) -#define AX5043_BBOFFSCAP_CAPINTA_Msk (0x7U << AX5043_BBOFFSCAP_CAPINTA_Pos) -#define AX5043_BBOFFSCAP_CAPINTA AX5043_BBOFFSCAP_CAPINTA_Msk -#define AX5043_BBOFFSCAP_CAPINTB_Pos (4U) -#define AX5043_BBOFFSCAP_CAPINTB_Msk (0x7U << AX5043_BBOFFSCAP_CAPINTB_Pos) -#define AX5043_BBOFFSCAP_CAPINTB AX5043_BBOFFSCAP_CAPINTB_Msk -/** @} */ - -/** - * @name AX5043 PKTADDRCFG register fields - * @{ - */ -#define AX5043_PKTADDRCFG_ADDRPOS_Pos (0U) -#define AX5043_PKTADDRCFG_ADDRPOS_Msk (0xFU << AX5043_PKTADDRCFG_ADDRPOS_Pos) -#define AX5043_PKTADDRCFG_ADDRPOS AX5043_PKTADDRCFG_ADDRPOS_Msk -#define AX5043_PKTADDRCFG_FECSYNCDIS_Pos (5U) -#define AX5043_PKTADDRCFG_FECSYNCDIS_Msk (0x1U << AX5043_PKTADDRCFG_FECSYNCDIS_Pos) -#define AX5043_PKTADDRCFG_FECSYNCDIS AX5043_PKTADDRCFG_FECSYNCDIS_Msk -#define AX5043_PKTADDRCFG_CRCSKIPFIRST_Pos (6U) -#define AX5043_PKTADDRCFG_CRCSKIPFIRST_Msk (0x1U << AX5043_PKTADDRCFG_CRCSKIPFIRST_Pos) -#define AX5043_PKTADDRCFG_CRCSKIPFIRST AX5043_PKTADDRCFG_CRCSKIPFIRST_Msk -#define AX5043_PKTADDRCFG_MSBFIRST_Pos (7U) -#define AX5043_PKTADDRCFG_MSBFIRST_Msk (0x1U << AX5043_PKTADDRCFG_MSBFIRST_Pos) -#define AX5043_PKTADDRCFG_MSBFIRST AX5043_PKTADDRCFG_MSBFIRST_Msk -/** @} */ - -/** - * @name AX5043 PKTLENCFG register fields - * @{ - */ -#define AX5043_PKTLENCFG_LENPOS_Pos (0U) -#define AX5043_PKTLENCFG_LENPOS_Msk (0xFU << AX5043_PKTLENCFG_LENPOS_Pos) -#define AX5043_PKTLENCFG_LENPOS AX5043_PKTLENCFG_LENPOS_Msk -#define AX5043_PKTLENCFG_LENBITS_Pos (4U) -#define AX5043_PKTLENCFG_LENBITS_Msk (0xFU << AX5043_PKTLENCFG_LENBITS_Pos) -#define AX5043_PKTLENCFG_LENBITS AX5043_PKTLENCFG_LENBITS_Msk -/** @} */ - -/** - * @name AX5043 PKTLENOFFSET register fields - * @{ - */ -#define AX5043_PKTLENOFFSET_Pos (0U) -#define AX5043_PKTLENOFFSET_Msk (0xFFU << AX5043_PKTLENOFFSET_Pos) -#define AX5043_PKTLENOFFSET AX5043_PKTLENOFFSET_Msk -/** @} */ - -/** - * @name AX5043 PKTMAXLEN register fields - * @{ - */ -#define AX5043_PKTMAXLEN_Pos (0U) -#define AX5043_PKTMAXLEN_Msk (0xFFU << AX5043_PKTMAXLEN_Pos) -#define AX5043_PKTMAXLEN AX5043_PKTMAXLEN_Msk -/** @} */ - -/** - * @name AX5043 PKTADDR register fields - * @{ - */ -#define AX5043_PKTADDR_Pos (0U) -#define AX5043_PKTADDR_Msk (0xFFFFFFFFU << AX5043_PKTADDR_Pos) -#define AX5043_PKTADDR AX5043_PKTADDR_Msk -/** @} */ - -/** - * @name AX5043 PKTADDRMASK register fields - * @{ - */ -#define AX5043_PKTADDRMASK_Pos (0U) -#define AX5043_PKTADDRMASK_Msk (0xFFFFFFFFU << AX5043_PKTADDRMASK_Pos) -#define AX5043_PKTADDRMASK AX5043_PKTADDRMASK_Msk -/** @} */ - -/** - * @name AX5043 MATCH0PAT register fields - * @{ - */ -#define AX5043_MATCH0PAT_Pos (0U) -#define AX5043_MATCH0PAT_Msk (0xFFFFFFFFU << AX5043_MATCH0PAT_Pos) -#define AX5043_MATCH0PAT AX5043_MATCH0PAT_Msk -/** @} */ - -/** - * @name AX5043 MATCH0LEN register fields - * @{ - */ -#define AX5043_MATCH0LEN_Pos (0U) -#define AX5043_MATCH0LEN_Msk (0x1FU << AX5043_MATCH0LEN_Pos) -#define AX5043_MATCH0LEN AX5043_MATCH0LEN_Msk -#define AX5043_MATCH0LEN_MATCH0RAW_Pos (7U) -#define AX5043_MATCH0LEN_MATCH0RAW_Msk (0x1U << AX5043_MATCH0LEN_MATCH0RAW_Pos) -#define AX5043_MATCH0LEN_MATCH0RAW AX5043_MATCH0LEN_MATCH0RAW_Msk -/** @} */ - -/** - * @name AX5043 MATCH0MIN register fields - * @{ - */ -#define AX5043_MATCH0MIN_Pos (0U) -#define AX5043_MATCH0MIN_Msk (0x1FU << AX5043_MATCH0MIN_Pos) -#define AX5043_MATCH0MIN AX5043_MATCH0MIN_Msk -/** @} */ - -/** - * @name AX5043 MATCH0MAX register fields - * @{ - */ -#define AX5043_MATCH0MAX_Pos (0U) -#define AX5043_MATCH0MAX_Msk (0x1FU << AX5043_MATCH0MAX_Pos) -#define AX5043_MATCH0MAX AX5043_MATCH0MAX_Msk -/** @} */ - -/** - * @name AX5043 MATCH1PAT register fields - * @{ - */ -#define AX5043_MATCH1PAT_Pos (0U) -#define AX5043_MATCH1PAT_Msk (0xFFFFU << AX5043_MATCH1PAT_Pos) -#define AX5043_MATCH1PAT AX5043_MATCH1PAT_Msk -/** @} */ - -/** - * @name AX5043 MATCH1LEN register fields - * @{ - */ -#define AX5043_MATCH1LEN_Pos (0U) -#define AX5043_MATCH1LEN_Msk (0xFU << AX5043_MATCH1LEN_Pos) -#define AX5043_MATCH1LEN AX5043_MATCH1LEN_Msk -#define AX5043_MATCH1LEN_MATCH1RAW_Pos (7U) -#define AX5043_MATCH1LEN_MATCH1RAW_Msk (0x1U << AX5043_MATCH1LEN_MATCH1RAW_Pos) -#define AX5043_MATCH1LEN_MATCH1RAW AX5043_MATCH1LEN_MATCH1RAW_Msk -/** @} */ - -/** - * @name AX5043 MATCH1MIN register fields - * @{ - */ -#define AX5043_MATCH1MIN_Pos (0U) -#define AX5043_MATCH1MIN_Msk (0xFU << AX5043_MATCH1MIN_Pos) -#define AX5043_MATCH1MIN AX5043_MATCH1MIN_Msk -/** @} */ - -/** - * @name AX5043 MATCH1MAX register fields - * @{ - */ -#define AX5043_MATCH1MAX_Pos (0U) -#define AX5043_MATCH1MAX_Msk (0xFU << AX5043_MATCH1MAX_Pos) -#define AX5043_MATCH1MAX AX5043_MATCH1MAX_Msk -/** @} */ - -/** - * @name AX5043 TMGTXBOOST register fields - * @{ - */ -#define AX5043_TMGTXBOOST_M_Pos (0U) -#define AX5043_TMGTXBOOST_M_Msk (0x1FU << AX5043_TMGTXBOOST_M_Pos) -#define AX5043_TMGTXBOOST_M AX5043_TMGTXBOOST_M_Msk -#define AX5043_TMGTXBOOST_E_Pos (5U) -#define AX5043_TMGTXBOOST_E_Msk (0x7U << AX5043_TMGTXBOOST_E_Pos) -#define AX5043_TMGTXBOOST_E AX5043_TMGTXBOOST_E_Msk -/** @} */ - -/** - * @name AX5043 TMGTXSETTLE register fields - * @{ - */ -#define AX5043_TMGTXSETTLE_M_Pos (0U) -#define AX5043_TMGTXSETTLE_M_Msk (0x1FU << AX5043_TMGTXSETTLE_M_Pos) -#define AX5043_TMGTXSETTLE_M AX5043_TMGTXSETTLE_M_Msk -#define AX5043_TMGTXSETTLE_E_Pos (5U) -#define AX5043_TMGTXSETTLE_E_Msk (0x7U << AX5043_TMGTXSETTLE_E_Pos) -#define AX5043_TMGTXSETTLE_E AX5043_TMGTXSETTLE_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXBOOST register fields - * @{ - */ -#define AX5043_TMGRXBOOST_M_Pos (0U) -#define AX5043_TMGRXBOOST_M_Msk (0x1FU << AX5043_TMGRXBOOST_M_Pos) -#define AX5043_TMGRXBOOST_M AX5043_TMGRXBOOST_M_Msk -#define AX5043_TMGRXBOOST_E_Pos (5U) -#define AX5043_TMGRXBOOST_E_Msk (0x7U << AX5043_TMGRXBOOST_E_Pos) -#define AX5043_TMGRXBOOST_E AX5043_TMGRXBOOST_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXSETTLE register fields - * @{ - */ -#define AX5043_TMGRXSETTLE_M_Pos (0U) -#define AX5043_TMGRXSETTLE_M_Msk (0x1FU << AX5043_TMGRXSETTLE_M_Pos) -#define AX5043_TMGRXSETTLE_M AX5043_TMGRXSETTLE_M_Msk -#define AX5043_TMGRXSETTLE_E_Pos (5U) -#define AX5043_TMGRXSETTLE_E_Msk (0x7U << AX5043_TMGRXSETTLE_E_Pos) -#define AX5043_TMGRXSETTLE_E AX5043_TMGRXSETTLE_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXOFFSACQ register fields - * @{ - */ -#define AX5043_TMGRXOFFSACQ_M_Pos (0U) -#define AX5043_TMGRXOFFSACQ_M_Msk (0x1FU << AX5043_TMGRXOFFSACQ_M_Pos) -#define AX5043_TMGRXOFFSACQ_M AX5043_TMGRXOFFSACQ_M_Msk -#define AX5043_TMGRXOFFSACQ_E_Pos (5U) -#define AX5043_TMGRXOFFSACQ_E_Msk (0x7U << AX5043_TMGRXOFFSACQ_E_Pos) -#define AX5043_TMGRXOFFSACQ_E AX5043_TMGRXOFFSACQ_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXCOARSEAGC register fields - * @{ - */ -#define AX5043_TMGRXCOARSEAGC_M_Pos (0U) -#define AX5043_TMGRXCOARSEAGC_M_Msk (0x1FU << AX5043_TMGRXCOARSEAGC_M_Pos) -#define AX5043_TMGRXCOARSEAGC_M AX5043_TMGRXCOARSEAGC_M_Msk -#define AX5043_TMGRXCOARSEAGC_E_Pos (0U) -#define AX5043_TMGRXCOARSEAGC_E_Msk (0x7U << AX5043_TMGRXCOARSEAGC_E_Pos) -#define AX5043_TMGRXCOARSEAGC_E AX5043_TMGRXCOARSEAGC_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXAGC register fields - * @{ - */ -#define AX5043_TMGRXAGC_M_Pos (0U) -#define AX5043_TMGRXAGC_M_Msk (0x1FU << AX5043_TMGRXAGC_M_Pos) -#define AX5043_TMGRXAGC_M AX5043_TMGRXAGC_M_Msk -#define AX5043_TMGRXAGC_E_Pos (5U) -#define AX5043_TMGRXAGC_E_Msk (0x7U << AX5043_TMGRXAGC_E_Pos) -#define AX5043_TMGRXAGC_E AX5043_TMGRXAGC_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXRSSI register fields - * @{ - */ -#define AX5043_TMGRXRSSI_M_Pos (0U) -#define AX5043_TMGRXRSSI_M_Msk (0x1FU << AX5043_TMGRXRSSI_M_Pos) -#define AX5043_TMGRXRSSI_M AX5043_TMGRXRSSI_M_Msk -#define AX5043_TMGRXRSSI_E_Pos (5U) -#define AX5043_TMGRXRSSI_E_Msk (0x7U << AX5043_TMGRXRSSI_E_Pos) -#define AX5043_TMGRXRSSI_E AX5043_TMGRXRSSI_E_Msk -/** @} */ - -/** - * @name AX5043 TMGRXPREAMBLE 1/2/3 register fields - * @{ - */ -#define AX5043_TMGRXPREAMBLE_M_Pos (0U) -#define AX5043_TMGRXPREAMBLE_M_Msk (0x1FU << AX5043_TMGRXPREAMBLE_M_Pos) -#define AX5043_TMGRXPREAMBLE_M AX5043_TMGRXPREAMBLE_M_Msk -#define AX5043_TMGRXPREAMBLE_E_Pos (5U) -#define AX5043_TMGRXPREAMBLE_E_Msk (0x7U << AX5043_TMGRXPREAMBLE_E_Pos) -#define AX5043_TMGRXPREAMBLE_E AX5043_TMGRXPREAMBLE_E_Msk -/** @} */ - -/** - * @name AX5043 RSSIREFERENCE register fields - * @{ - */ -#define AX5043_RSSIREFERENCE_Pos (0U) -#define AX5043_RSSIREFERENCE_Msk (0xFFU << AX5043_RSSIREFERENCE_Pos) -#define AX5043_RSSIREFERENCE AX5043_RSSIREFERENCE_Msk -/** @} */ - -/** - * @name AX5043 RSSIABSTHR register fields - * @{ - */ -#define AX5043_RSSIABSTHR_Pos (0U) -#define AX5043_RSSIABSTHR_Msk (0xFFU << AX5043_RSSIABSTHR_Pos) -#define AX5043_RSSIABSTHR AX5043_RSSIABSTHR_Msk -/** @} */ - -/** - * @name AX5043 BGNDRSSIGAIN register fields - * @{ - */ -#define AX5043_BGNDRSSIGAIN_Pos (0U) -#define AX5043_BGNDRSSIGAIN_Msk (0xFU << AX5043_BGNDRSSIGAIN_Pos) -#define AX5043_BGNDRSSIGAIN AX5043_BGNDRSSIGAIN_Msk -/** @} */ - -/** - * @name AX5043 BGNDRSSITHR register fields - * @{ - */ -#define AX5043_BGNDRSSITHR_Pos (0U) -#define AX5043_BGNDRSSITHR_Msk (0x3FU << AX5043_BGNDRSSITHR_Pos) -#define AX5043_BGNDRSSITHR AX5043_BGNDRSSITHR_Msk -/** @} */ - -/** - * @name AX5043 PKTCHUNKSIZE register fields - * @{ - */ -#define AX5043_PKTCHUNKSIZE_Pos (0U) -#define AX5043_PKTCHUNKSIZE_Msk (0xFU << AX5043_PKTCHUNKSIZE_Pos) -#define AX5043_PKTCHUNKSIZE AX5043_PKTCHUNKSIZE_Msk -#define AX5043_PKTCHUNKSIZE_1 (0x1U) -#define AX5043_PKTCHUNKSIZE_2 (0x2U) -#define AX5043_PKTCHUNKSIZE_4 (0x3U) -#define AX5043_PKTCHUNKSIZE_8 (0x4U) -#define AX5043_PKTCHUNKSIZE_16 (0x5U) -#define AX5043_PKTCHUNKSIZE_32 (0x6U) -#define AX5043_PKTCHUNKSIZE_64 (0x7U) -#define AX5043_PKTCHUNKSIZE_96 (0x8U) -#define AX5043_PKTCHUNKSIZE_128 (0x9U) -#define AX5043_PKTCHUNKSIZE_160 (0xAU) -#define AX5043_PKTCHUNKSIZE_192 (0xBU) -#define AX5043_PKTCHUNKSIZE_224 (0xCU) -#define AX5043_PKTCHUNKSIZE_240 (0xDU) -/** @} */ - -/** - * @name AX5043 PKTMISCFLAGS register fields - * @{ - */ -#define AX5043_PKTMISCFLAGS_RXRSSICLK_Pos (0U) -#define AX5043_PKTMISCFLAGS_RXRSSICLK_Msk (0x1U << AX5043_PKTMISCFLAGS_RXRSSICLK_Pos) -#define AX5043_PKTMISCFLAGS_RXRSSICLK AX5043_PKTMISCFLAGS_RXRSSICLK_Msk -#define AX5043_PKTMISCFLAGS_RXAGCCLK_Pos (1U) -#define AX5043_PKTMISCFLAGS_RXAGCCLK_Msk (0x1U << AX5043_PKTMISCFLAGS_RXAGCCLK_Pos) -#define AX5043_PKTMISCFLAGS_RXAGCCLK AX5043_PKTMISCFLAGS_RXAGCCLK_Msk -#define AX5043_PKTMISCFLAGS_BGNDRSSI_Pos (2U) -#define AX5043_PKTMISCFLAGS_BGNDRSSI_Msk (0x1U << AX5043_PKTMISCFLAGS_BGNDRSSI_Pos) -#define AX5043_PKTMISCFLAGS_BGNDRSSI AX5043_PKTMISCFLAGS_BGNDRSSI_Msk -#define AX5043_PKTMISCFLAGS_AGCSETTLDET_Pos (3U) -#define AX5043_PKTMISCFLAGS_AGCSETTLDET_Msk (0x1U << AX5043_PKTMISCFLAGS_AGCSETTLDET_Pos) -#define AX5043_PKTMISCFLAGS_AGCSETTLDET AX5043_PKTMISCFLAGS_AGCSETTLDET_Msk -#define AX5043_PKTMISCFLAGS_WORMULTIPKT_Pos (4U) -#define AX5043_PKTMISCFLAGS_WORMULTIPKT_Msk (0x1U << AX5043_PKTMISCFLAGS_WORMULTIPKT_Pos) -#define AX5043_PKTMISCFLAGS_WORMULTIPKT AX5043_PKTMISCFLAGS_WORMULTIPKT_Msk -/** @} */ - -/** - * @name AX5043 PKTSTOREFLAGS register fields - * @{ - */ -#define AX5043_PKTSTOREFLAGS_TIMER_Pos (0U) -#define AX5043_PKTSTOREFLAGS_TIMER_Msk (0x1U << AX5043_PKTSTOREFLAGS_TIMER_Pos) -#define AX5043_PKTSTOREFLAGS_TIMER AX5043_PKTSTOREFLAGS_TIMER_Msk -#define AX5043_PKTSTOREFLAGS_FOFFS_Pos (1U) -#define AX5043_PKTSTOREFLAGS_FOFFS_Msk (0x1U << AX5043_PKTSTOREFLAGS_FOFFS_Pos) -#define AX5043_PKTSTOREFLAGS_FOFFS AX5043_PKTSTOREFLAGS_FOFFS_Msk -#define AX5043_PKTSTOREFLAGS_RFOFFS_Pos (2U) -#define AX5043_PKTSTOREFLAGS_RFOFFS_Msk (0x1U << AX5043_PKTSTOREFLAGS_RFOFFS_Pos) -#define AX5043_PKTSTOREFLAGS_RFOFFS AX5043_PKTSTOREFLAGS_RFOFFS_Msk -#define AX5043_PKTSTOREFLAGS_DR_Pos (3U) -#define AX5043_PKTSTOREFLAGS_DR_Msk (0x1U << AX5043_PKTSTOREFLAGS_DR_Pos) -#define AX5043_PKTSTOREFLAGS_DR AX5043_PKTSTOREFLAGS_DR_Msk -#define AX5043_PKTSTOREFLAGS_RSSI_Pos (4U) -#define AX5043_PKTSTOREFLAGS_RSSI_Msk (0x1U << AX5043_PKTSTOREFLAGS_RSSI_Pos) -#define AX5043_PKTSTOREFLAGS_RSSI AX5043_PKTSTOREFLAGS_RSSI_Msk -#define AX5043_PKTSTOREFLAGS_CRCB_Pos (5U) -#define AX5043_PKTSTOREFLAGS_CRCB_Msk (0x1U << AX5043_PKTSTOREFLAGS_CRCB_Pos) -#define AX5043_PKTSTOREFLAGS_CRCB AX5043_PKTSTOREFLAGS_CRCB_Msk -#define AX5043_PKTSTOREFLAGS_ANTRSSI_Pos (6U) -#define AX5043_PKTSTOREFLAGS_ANTRSSI_Msk (0x1U << AX5043_PKTSTOREFLAGS_ANTRSSI_Pos) -#define AX5043_PKTSTOREFLAGS_ANTRSSI AX5043_PKTSTOREFLAGS_ANTRSSI_Msk -/** @} */ - -/** - * @name AX5043 PKTACCEPTFLAGS register fields - * @{ - */ -#define AX5043_PKTACCEPTFLAGS_RESIDUE_Pos (0U) -#define AX5043_PKTACCEPTFLAGS_RESIDUE_Msk (0x1U << AX5043_PKTACCEPTFLAGS_RESIDUE_Pos) -#define AX5043_PKTACCEPTFLAGS_RESIDUE AX5043_PKTACCEPTFLAGS_RESIDUE_Msk -#define AX5043_PKTACCEPTFLAGS_ABRT_Pos (1U) -#define AX5043_PKTACCEPTFLAGS_ABRT_Msk (0x1U << AX5043_PKTACCEPTFLAGS_ABRT_Pos) -#define AX5043_PKTACCEPTFLAGS_ABRT AX5043_PKTACCEPTFLAGS_ABRT_Msk -#define AX5043_PKTACCEPTFLAGS_CRCF_Pos (2U) -#define AX5043_PKTACCEPTFLAGS_CRCF_Msk (0x1U << AX5043_PKTACCEPTFLAGS_CRCF_Pos) -#define AX5043_PKTACCEPTFLAGS_CRCF AX5043_PKTACCEPTFLAGS_CRCF_Msk -#define AX5043_PKTACCEPTFLAGS_ADDRF_Pos (3U) -#define AX5043_PKTACCEPTFLAGS_ADDRF_Msk (0x1U << AX5043_PKTACCEPTFLAGS_ADDRF_Pos) -#define AX5043_PKTACCEPTFLAGS_ADDRF AX5043_PKTACCEPTFLAGS_ADDRF_Msk -#define AX5043_PKTACCEPTFLAGS_SZF_Pos (4U) -#define AX5043_PKTACCEPTFLAGS_SZF_Msk (0x1U << AX5043_PKTACCEPTFLAGS_SZF_Pos) -#define AX5043_PKTACCEPTFLAGS_SZF AX5043_PKTACCEPTFLAGS_SZF_Msk -#define AX5043_PKTACCEPTFLAGS_LRGP_Pos (5U) -#define AX5043_PKTACCEPTFLAGS_LRGP_Msk (0x1U << AX5043_PKTACCEPTFLAGS_LRGP_Pos) -#define AX5043_PKTACCEPTFLAGS_LRGP AX5043_PKTACCEPTFLAGS_LRGP_Msk -/** @} */ - -/** - * @name AX5043 GPADCCTRL register fields - * @{ - */ -#define AX5043_GPADCCTRL_CHISOL_Pos (0U) -#define AX5043_GPADCCTRL_CHISOL_Msk (0x1U << AX5043_GPADCCTRL_CHISOL_Pos) -#define AX5043_GPADCCTRL_CHISOL AX5043_GPADCCTRL_CHISOL_Msk -#define AX5043_GPADCCTRL_CONT_Pos (1U) -#define AX5043_GPADCCTRL_CONT_Msk (0x1U << AX5043_GPADCCTRL_CONT_Pos) -#define AX5043_GPADCCTRL_CONT AX5043_GPADCCTRL_CONT_Msk -#define AX5043_GPADCCTRL_GPADC13_Pos (2U) -#define AX5043_GPADCCTRL_GPADC13_Msk (0x1U << AX5043_GPADCCTRL_GPADC13_Pos) -#define AX5043_GPADCCTRL_GPADC13 AX5043_GPADCCTRL_GPADC13_Msk -#define AX5043_GPADCCTRL_BUSY_Pos (7U) -#define AX5043_GPADCCTRL_BUSY_Msk (0x1U << AX5043_GPADCCTRL_BUSY_Pos) -#define AX5043_GPADCCTRL_BUSY AX5043_GPADCCTRL_BUSY_Msk -/** @} */ - -/** - * @name AX5043 GPADCPERIOD register fields - * @{ - */ -#define AX5043_GPADCPERIOD_Pos (0U) -#define AX5043_GPADCPERIOD_Msk (0xFFU << AX5043_GPADCPERIOD_Pos) -#define AX5043_GPADCPERIOD AX5043_GPADCPERIOD_Msk -/** @} */ - -/** - * @name AX5043 GPADC13VALUE register fields - * @{ - */ -#define AX5043_GPADC13VALUE_Pos (0U) -#define AX5043_GPADC13VALUE_Msk (0x3FFU << AX5043_GPADC13VALUE_Pos) -#define AX5043_GPADC13VALUE AX5043_GPADC13VALUE_Msk -/** @} */ - -/** - * @name AX5043 LPOSCCONFIG register fields - * @{ - */ -#define AX5043_LPOSCCONFIG_ENA_Pos (0U) -#define AX5043_LPOSCCONFIG_ENA_Msk (0x1U << AX5043_LPOSCCONFIG_ENA_Pos) -#define AX5043_LPOSCCONFIG_ENA AX5043_LPOSCCONFIG_ENA_Msk -#define AX5043_LPOSCCONFIG_FAST_Pos (1U) -#define AX5043_LPOSCCONFIG_FAST_Msk (0x1U << AX5043_LPOSCCONFIG_FAST_Pos) -#define AX5043_LPOSCCONFIG_FAST AX5043_LPOSCCONFIG_FAST_Msk -/* TODO: Verify which bit is IRQF/IRQR, manual is inconsistent */ -#define AX5043_LPOSCCONFIG_IRQF_Pos (2U) -#define AX5043_LPOSCCONFIG_IRQF_Msk (0x1U << AX5043_LPOSCCONFIG_IRQF_Pos) -#define AX5043_LPOSCCONFIG_IRQF AX5043_LPOSCCONFIG_IRQF_Msk -#define AX5043_LPOSCCONFIG_IRQR_Pos (3U) -#define AX5043_LPOSCCONFIG_IRQR_Msk (0x1U << AX5043_LPOSCCONFIG_IRQR_Pos) -#define AX5043_LPOSCCONFIG_IRQR AX5043_LPOSCCONFIG_IRQR_Msk -#define AX5043_LPOSCCONFIG_CALIBF_Pos (4U) -#define AX5043_LPOSCCONFIG_CALIBF_Msk (0x1U << AX5043_LPOSCCONFIG_CALIBF_Pos) -#define AX5043_LPOSCCONFIG_CALIBF AX5043_LPOSCCONFIG_CALIBF_Msk -#define AX5043_LPOSCCONFIG_CALIBR_Pos (5U) -#define AX5043_LPOSCCONFIG_CALIBR_Msk (0x1U << AX5043_LPOSCCONFIG_CALIBR_Pos) -#define AX5043_LPOSCCONFIG_CALIBR AX5043_LPOSCCONFIG_CALIBR_Msk -#define AX5043_LPOSCCONFIG_OSCDOUBLE_Pos (6U) -#define AX5043_LPOSCCONFIG_OSCDOUBLE_Msk (0x1U << AX5043_LPOSCCONFIG_OSCDOUBLE_Pos) -#define AX5043_LPOSCCONFIG_OSCDOUBLE AX5043_LPOSCCONFIG_OSCDOUBLE_Msk -#define AX5043_LPOSCCONFIG_OSCINVERT_Pos (7U) -#define AX5043_LPOSCCONFIG_OSCINVERT_Msk (0x1U << AX5043_LPOSCCONFIG_OSCINVERT_Pos) -#define AX5043_LPOSCCONFIG_OSCINVERT AX5043_LPOSCCONFIG_OSCINVERT_Msk -/** @} */ - -/** - * @name AX5043 LPOSCSTATUS register fields - * @{ - */ -#define AX5043_LPOSCSTATUS_EDGE_Pos (0U) -#define AX5043_LPOSCSTATUS_EDGE_Msk (0x1U << AX5043_LPOSCSTATUS_EDGE_Pos) -#define AX5043_LPOSCSTATUS_EDGE AX5043_LPOSCSTATUS_EDGE_Msk -#define AX5043_LPOSCSTATUS_IRQ_Pos (1U) -#define AX5043_LPOSCSTATUS_IRQ_Msk (0x1U << AX5043_LPOSCSTATUS_IRQ_Pos) -#define AX5043_LPOSCSTATUS_IRQ AX5043_LPOSCSTATUS_IRQ_Msk -/** @} */ - -/** - * @name AX5043 LPOSCFILT register fields - * @{ - */ -#define AX5043_LPOSCFILT_Pos (0U) -#define AX5043_LPOSCFILT_Msk (0xFFFFU << AX5043_LPOSCFILT_Pos) -#define AX5043_LPOSCFILT AX5043_LPOSCFILT_Msk -/** @} */ - -/** - * @name AX5043 LPOSCREF register fields - * @{ - */ -#define AX5043_LPOSCREF_Pos (0U) -#define AX5043_LPOSCREF_Msk (0xFFFFU << AX5043_LPOSCREF_Pos) -#define AX5043_LPOSCREF AX5043_LPOSCREF_Msk -/** @} */ - -/** - * @name AX5043 LPOSCFREQ register fields - * TODO: Verify the field width here - * @{ - */ -#define AX5043_LPOSCFREQ_Pos (0U) -#define AX5043_LPOSCFREQ_Msk (0x3FFU << AX5043_LPOSCFREQ_Pos) -#define AX5043_LPOSCFREQ AX5043_LPOSCFREQ_Msk -/** @} */ - -/** - * @name AX5043 LPOSCPER register fields - * @{ - */ -#define AX5043_LPOSCPER_Pos (0U) -#define AX5043_LPOSCPER_Msk (0xFFFFU << AX5043_LPOSCPER_Pos) -#define AX5043_LPOSCPER AX5043_LPOSCPER_Msk -/** @} */ - -/** - * @name AX5043 DACVALUE register fields - * @{ - */ -#define AX5043_DACVALUE_Pos (0U) -#define AX5043_DACVALUE_Msk (0xFFFU << AX5043_DACVALUE_Pos) -#define AX5043_DACVALUE AX5043_DACVALUE_Msk -#define AX5043_DACVALUE_DACSHIFT_Pos (0U) -#define AX5043_DACVALUE_DACSHIFT_Msk (0xFU << AX5043_DACVALUE_DACSHIFT_Pos) -#define AX5043_DACVALUE_DACSHIFT AX5043_DACVALUE_DACSHIFT_Msk -/** @} */ - -/** - * @name AX5043 DACCONFIG register fields - * @{ - */ -#define AX5043_DACCONFIG_DACINPUT_Pos (0U) -#define AX5043_DACCONFIG_DACINPUT_Msk (0xFU << AX5043_DACCONFIG_DACINPUT_Pos) -#define AX5043_DACCONFIG_DACINPUT AX5043_DACCONFIG_DACINPUT_Msk -#define AX5043_DACINPUT_DACVALUER (0x0U) -#define AX5043_DACINPUT_TRKAMPLITUDE (0x1U) -#define AX5043_DACINPUT_TRKRFFREQUENCY (0x2U) -#define AX5043_DACINPUT_TRKFREQUENCY (0x3U) -#define AX5043_DACINPUT_FSKDEMOD (0x4U) -#define AX5043_DACINPUT_AFSKDEMOD (0x5U) -#define AX5043_DACINPUT_RXSOFTDATA (0x6U) -#define AX5043_DACINPUT_RSSI (0x7U) -#define AX5043_DACINPUT_SAMPLE_ROT_I (0x8U) -#define AX5043_DACINPUT_SAMPLE_ROT_Q (0x9U) -#define AX5043_DACINPUT_GPADC13 (0xCU) -#define AX5043_DACCONFIG_DACCLKX2_Pos (6U) -#define AX5043_DACCONFIG_DACCLKX2_Msk (0x1U << AX5043_DACCONFIG_DACCLKX2_Pos) -#define AX5043_DACCONFIG_DACCLKX2 AX5043_DACCONFIG_DACCLKX2_Msk -#define AX5043_DACCONFIG_DACPWM_Pos (7U) -#define AX5043_DACCONFIG_DACPWM_Msk (0x1U << AX5043_DACCONFIG_DACPWM_Pos) -#define AX5043_DACCONFIG_DACPWM AX5043_DACCONFIG_DACPWM_Msk -/** @} */ - -/** - * @name AX5043 PERFTUNE registers - * @{ - */ -#define AX5043_0xF00_DEFVAL (0x0FU) -#define AX5043_0xF08_DEFVAL (0x04U) -#define AX5043_0xF0C_DEFVAL (0x00U) -#define AX5043_0xF0D_DEFVAL (0x03U) -#define AX5043_0xF10_CRYSTAL (0x03U) -#define AX5043_0xF10_TCXO (0x04U) -#define AX5043_0xF10_GT_43MHZ (0x0DU) -#define AX5043_0xF11_TCXO (0x00U) -#define AX5043_0xF11_CRYSTAL (0x07U) -/* TODO: Try to figure out 0xF18 values */ -#define AX5043_0xF1C_DEFVAL (0x07U) -#define AX5043_0xF21_DEFVAL (0x5CU) -#define AX5043_0xF22_DEFVAL (0x53U) -#define AX5043_0xF23_DEFVAL (0x76U) -#define AX5043_0xF26_DEFVAL (0x92U) -#define AX5043_0xF30_DEFVAL (0x3FU) -#define AX5043_0xF31_DEFVAL (0xF0U) -#define AX5043_0xF32_DEFVAL (0x3FU) -#define AX5043_0xF33_DEFVAL (0xF0U) -#define AX5043_0xF34_NORFDIV (0x08U) -#define AX5043_0xF34_RFDIV (0x28U) -#define AX5043_0xF35_XTALDIV1 (0x10U) -#define AX5043_0xF35_XTALDIV2 (0x11U) -#define AX5043_0xF44_DEFVAL (0x24U) -#define AX5043_0xF72_NORAWSOFTBITS (0x00U) -#define AX5043_0xF72_RAWSOFTBITS (0x06U) -/** @} */ - -/** - * @name AX5043 SPI Status Bits - * @{ - */ -#define AX5043_STATUS_GPADC_INT_Pos (1U) -#define AX5043_STATUS_GPADC_INT_Msk (0x1U << AX5043_STATUS_GPADC_INT_Pos) -#define AX5043_STATUS_GPADC_INT AX5043_STATUS_GPADC_INT_Msk -#define AX5043_STATUS_LPOSC_INT_Pos (2U) -#define AX5043_STATUS_LPOSC_INT_Msk (0x1U << AX5043_STATUS_LPOSC_INT_Pos) -#define AX5043_STATUS_LPOSC_INT AX5043_STATUS_LPOSC_INT_Msk -#define AX5043_STATUS_WAKEUP_INT_Pos (3U) -#define AX5043_STATUS_WAKEUP_INT_Msk (0x1U << AX5043_STATUS_WAKEUP_INT_Pos) -#define AX5043_STATUS_WAKEUP_INT AX5043_STATUS_WAKEUP_INT_Msk -#define AX5043_STATUS_XTAL_INT_Pos (4U) -#define AX5043_STATUS_XTAL_INT_Msk (0x1U << AX5043_STATUS_XTAL_INT_Pos) -#define AX5043_STATUS_XTAL_INT AX5043_STATUS_XTAL_INT_Msk -#define AX5043_STATUS_RADIOEVENT_INT_Pos (5U) -#define AX5043_STATUS_RADIOEVENT_INT_Msk (0x1U << AX5043_STATUS_RADIOEVENT_INT_Pos) -#define AX5043_STATUS_RADIOEVENT_INT AX5043_STATUS_RADIOEVENT_INT_Msk -#define AX5043_STATUS_PWR_INT_Pos (6U) -#define AX5043_STATUS_PWR_INT_Msk (0x1U << AX5043_STATUS_PWR_INT_Pos) -#define AX5043_STATUS_PWR_INT AX5043_STATUS_PWR_INT_Msk -#define AX5043_STATUS_PWRGOOD_Pos (7U) -#define AX5043_STATUS_PWRGOOD_Msk (0x1U << AX5043_STATUS_PWRGOOD_Pos) -#define AX5043_STATUS_PWRGOOD AX5043_STATUS_PWRGOOD_Msk -#define AX5043_STATUS_FIFO_EMPTY_Pos (8U) -#define AX5043_STATUS_FIFO_EMPTY_Msk (0x1U << AX5043_STATUS_FIFO_EMPTY_Pos) -#define AX5043_STATUS_FIFO_EMPTY AX5043_STATUS_FIFO_EMPTY_Msk -#define AX5043_STATUS_FIFO_FULL_Pos (9U) -#define AX5043_STATUS_FIFO_FULL_Msk (0x1U << AX5043_STATUS_FIFO_FULL_Pos) -#define AX5043_STATUS_FIFO_FULL AX5043_STATUS_FIFO_FULL_Msk -#define AX5043_STATUS_THR_COUNT_Pos (10U) -#define AX5043_STATUS_THR_COUNT_Msk (0x1U << AX5043_STATUS_THR_COUNT_Pos) -#define AX5043_STATUS_THR_COUNT AX5043_STATUS_THR_COUNT_Msk -#define AX5043_STATUS_THR_FREE_Pos (11U) -#define AX5043_STATUS_THR_FREE_Msk (0x1U << AX5043_STATUS_THR_FREE_Pos) -#define AX5043_STATUS_THR_FREE AX5043_STATUS_THR_FREE_Msk -#define AX5043_STATUS_FIFO_UNDER_Pos (12U) -#define AX5043_STATUS_FIFO_UNDER_Msk (0x1U << AX5043_STATUS_FIFO_UNDER_Pos) -#define AX5043_STATUS_FIFO_UNDER AX5043_STATUS_FIFO_UNDER_Msk -#define AX5043_STATUS_FIFO_OVER_Pos (13U) -#define AX5043_STATUS_FIFO_OVER_Msk (0x1U << AX5043_STATUS_FIFO_OVER_Pos) -#define AX5043_STATUS_FIFO_OVER AX5043_STATUS_FIFO_OVER_Msk -#define AX5043_STATUS_PLL_LOCK_Pos (14U) -#define AX5043_STATUS_PLL_LOCK_Msk (0x1U << AX5043_STATUS_PLL_LOCK_Pos) -#define AX5043_STATUS_PLL_LOCK AX5043_STATUS_PLL_LOCK_Msk -/** @} */ - -/** - * @name AX5043 FIFO chunk header fields and encodings - * @{ - */ -#define AX5043_FIFOCHUNK_CMD_Pos (0U) -#define AX5043_FIFOCHUNK_CMD_Msk (0x1FU << AX5043_FIFOCHUNK_CMD_Pos) -#define AX5043_FIFOCHUNK_CMD AX5043_FIFOCHUNK_CMD_Msk -#define AX5043_CHUNKCMD_NOP (0x00U) -#define AX5043_CHUNKCMD_DATA (0x01U) -#define AX5043_CHUNKCMD_REPEATDATA (0x02U) -#define AX5043_CHUNKCMD_TIMER (0x10U) -#define AX5043_CHUNKCMD_RSSI (0x11U) -#define AX5043_CHUNKCMD_FREQOFFS (0x12U) -#define AX5043_CHUNKCMD_RFFREQOFFS (0x13U) -#define AX5043_CHUNKCMD_DATARATE (0x14U) -#define AX5043_CHUNKCMD_ANTRSSI (0x15U) -#define AX5043_CHUNKCMD_TXCTRL (0x1CU) -#define AX5043_CHUNKCMD_TXPWR (0x1DU) -#define AX5043_FIFOCHUNK_SIZE_Pos (5U) -#define AX5043_FIFOCHUNK_SIZE_Msk (0x7U << AX5043_FIFOCHUNK_SIZE_Pos) -#define AX5043_FIFOCHUNK_SIZE AX5043_FIFOCHUNK_SIZE_Msk -#define AX5043_CHUNKSIZE_VAR (0x7U) -/** @} */ - -/** - * @name AX5043 FIFO TXCTRL Command flags - * @{ - */ -#define AX5043_CHUNK_TXCTRL_PASTATE_Pos (0U) -#define AX5043_CHUNK_TXCTRL_PASTATE_Msk (0x1U << AX5043_CHUNK_TXCTRL_PASTATE_Pos) -#define AX5043_CHUNK_TXCTRL_PASTATE AX5043_CHUNK_TXCTRL_PASTATE_Msk -#define AX5043_CHUNK_TXCTRL_SETPA_Pos (1U) -#define AX5043_CHUNK_TXCTRL_SETPA_Msk (0x1U << AX5043_CHUNK_TXCTRL_SETPA_Pos) -#define AX5043_CHUNK_TXCTRL_SETPA AX5043_CHUNK_TXCTRL_SETPA_Msk -#define AX5043_CHUNK_TXCTRL_ANTSTATE_Pos (2U) -#define AX5043_CHUNK_TXCTRL_ANTSTATE_Msk (0x1U << AX5043_CHUNK_TXCTRL_ANTSTATE_Pos) -#define AX5043_CHUNK_TXCTRL_ANTSTATE AX5043_CHUNK_TXCTRL_ANTSTATE_Msk -#define AX5043_CHUNK_TXCTRL_SETANT_Pos (3U) -#define AX5043_CHUNK_TXCTRL_SETANT_Msk (0x1U << AX5043_CHUNK_TXCTRL_SETANT_Pos) -#define AX5043_CHUNK_TXCTRL_SETANT AX5043_CHUNK_TXCTRL_SETANT_Msk -#define AX5043_CHUNK_TXCTRL_TXDIFF_Pos (4U) -#define AX5043_CHUNK_TXCTRL_TXDIFF_Msk (0x1U << AX5043_CHUNK_TXCTRL_TXDIFF_Pos) -#define AX5043_CHUNK_TXCTRL_TXDIFF AX5043_CHUNK_TXCTRL_TXDIFF_Msk -#define AX5043_CHUNK_TXCTRL_TXSE_Pos (5U) -#define AX5043_CHUNK_TXCTRL_TXSE_Msk (0x1U << AX5043_CHUNK_TXCTRL_TXSE_Pos) -#define AX5043_CHUNK_TXCTRL_TXSE AX5043_CHUNK_TXCTRL_TXSE_Msk -#define AX5043_CHUNK_TXCTRL_SETTX_Pos (6U) -#define AX5043_CHUNK_TXCTRL_SETTX_Msk (0x1U << AX5043_CHUNK_TXCTRL_SETTX_Pos) -#define AX5043_CHUNK_TXCTRL_SETTX AX5043_CHUNK_TXCTRL_SETTX_Msk -/** @} */ - -/** - * @name AX5043 FIFO REPEATDATA Command flags - * @{ - */ -#define AX5043_CHUNK_REPEATDATA_PKTSTART_Pos (0U) -#define AX5043_CHUNK_REPEATDATA_PKTSTART_Msk (0x1U << AX5043_CHUNK_REPEATDATA_PKTSTART_Pos) -#define AX5043_CHUNK_REPEATDATA_PKTSTART AX5043_CHUNK_REPEATDATA_PKTSTART_Msk -#define AX5043_CHUNK_REPEATDATA_PKTEND_Pos (1U) -#define AX5043_CHUNK_REPEATDATA_PKTEND_Msk (0x1U << AX5043_CHUNK_REPEATDATA_PKTEND_Pos) -#define AX5043_CHUNK_REPEATDATA_PKTEND AX5043_CHUNK_REPEATDATA_PKTEND_Msk -#define AX5043_CHUNK_REPEATDATA_RESIDUE_Pos (2U) -#define AX5043_CHUNK_REPEATDATA_RESIDUE_Msk (0x1U << AX5043_CHUNK_REPEATDATA_RESIDUE_Pos) -#define AX5043_CHUNK_REPEATDATA_RESIDUE AX5043_CHUNK_REPEATDATA_RESIDUE_Msk -#define AX5043_CHUNK_REPEATDATA_NOCRC_Pos (3U) -#define AX5043_CHUNK_REPEATDATA_NOCRC_Msk (0x1U << AX5043_CHUNK_REPEATDATA_NOCRC_Pos) -#define AX5043_CHUNK_REPEATDATA_NOCRC AX5043_CHUNK_REPEATDATA_NOCRC_Msk -#define AX5043_CHUNK_REPEATDATA_RAW_Pos (4U) -#define AX5043_CHUNK_REPEATDATA_RAW_Msk (0x1U << AX5043_CHUNK_REPEATDATA_RAW_Pos) -#define AX5043_CHUNK_REPEATDATA_RAW AX5043_CHUNK_REPEATDATA_RAW_Msk -#define AX5043_CHUNK_REPEATDATA_UNENC_Pos (5U) -#define AX5043_CHUNK_REPEATDATA_UNENC_Msk (0x1U << AX5043_CHUNK_REPEATDATA_UNENC_Pos) -#define AX5043_CHUNK_REPEATDATA_UNENC AX5043_CHUNK_REPEATDATA_UNENC_Msk -/** @} */ - -/** - * @name AX5043 FIFO DATA TX flags - * @{ - */ -#define AX5043_CHUNK_DATATX_PKTSTART_Pos (0U) -#define AX5043_CHUNK_DATATX_PKTSTART_Msk (0x1U << AX5043_CHUNK_DATATX_PKTSTART_Pos) -#define AX5043_CHUNK_DATATX_PKTSTART AX5043_CHUNK_DATATX_PKTSTART_Msk -#define AX5043_CHUNK_DATATX_PKTEND_Pos (1U) -#define AX5043_CHUNK_DATATX_PKTEND_Msk (0x1U << AX5043_CHUNK_DATATX_PKTEND_Pos) -#define AX5043_CHUNK_DATATX_PKTEND AX5043_CHUNK_DATATX_PKTEND_Msk -#define AX5043_CHUNK_DATATX_RESIDUE_Pos (2U) -#define AX5043_CHUNK_DATATX_RESIDUE_Msk (0x1U << AX5043_CHUNK_DATATX_RESIDUE_Pos) -#define AX5043_CHUNK_DATATX_RESIDUE AX5043_CHUNK_DATATX_RESIDUE_Msk -#define AX5043_CHUNK_DATATX_NOCRC_Pos (3U) -#define AX5043_CHUNK_DATATX_NOCRC_Msk (0x1U << AX5043_CHUNK_DATATX_NOCRC_Pos) -#define AX5043_CHUNK_DATATX_NOCRC AX5043_CHUNK_DATATX_NOCRC_Msk -#define AX5043_CHUNK_DATATX_RAW_Pos (4U) -#define AX5043_CHUNK_DATATX_RAW_Msk (0x1U << AX5043_CHUNK_DATATX_RAW_Pos) -#define AX5043_CHUNK_DATATX_RAW AX5043_CHUNK_DATATX_RAW_Msk -#define AX5043_CHUNK_DATATX_UNENC_Pos (5U) -#define AX5043_CHUNK_DATATX_UNENC_Msk (0x1U << AX5043_CHUNK_DATATX_UNENC_Pos) -#define AX5043_CHUNK_DATATX_UNENC AX5043_CHUNK_DATATX_UNENC_Msk -/** @} */ - -/** - * @name AX5043 FIFO DATA RX flags - * @{ - */ -#define AX5043_CHUNK_DATARX_PKTSTART_Pos (0U) -#define AX5043_CHUNK_DATARX_PKTSTART_Msk (0x1U << AX5043_CHUNK_DATARX_PKTSTART_Pos) -#define AX5043_CHUNK_DATARX_PKTSTART AX5043_CHUNK_DATARX_PKTSTART_Msk -#define AX5043_CHUNK_DATARX_PKTEND_Pos (1U) -#define AX5043_CHUNK_DATARX_PKTEND_Msk (0x1U << AX5043_CHUNK_DATARX_PKTEND_Pos) -#define AX5043_CHUNK_DATARX_PKTEND AX5043_CHUNK_DATARX_PKTEND_Msk -#define AX5043_CHUNK_DATARX_RESIDUE_Pos (2U) -#define AX5043_CHUNK_DATARX_RESIDUE_Msk (0x1U << AX5043_CHUNK_DATARX_RESIDUE_Pos) -#define AX5043_CHUNK_DATARX_RESIDUE AX5043_CHUNK_DATARX_RESIDUE_Msk -#define AX5043_CHUNK_DATARX_CRCFAIL_Pos (3U) -#define AX5043_CHUNK_DATARX_CRCFAIL_Msk (0x1U << AX5043_CHUNK_DATARX_CRCFAIL_Pos) -#define AX5043_CHUNK_DATARX_CRCFAIL AX5043_CHUNK_DATARX_CRCFAIL_Msk -#define AX5043_CHUNK_DATARX_ADDRFAIL_Pos (4U) -#define AX5043_CHUNK_DATARX_ADDRFAIL_Msk (0x1U << AX5043_CHUNK_DATARX_ADDRFAIL_Pos) -#define AX5043_CHUNK_DATARX_ADDRFAIL AX5043_CHUNK_DATARX_ADDRFAIL_Msk -#define AX5043_CHUNK_DATARX_SIZEFAIL_Pos (5U) -#define AX5043_CHUNK_DATARX_SIZEFAIL_Msk (0x1U << AX5043_CHUNK_DATARX_SIZEFAIL_Pos) -#define AX5043_CHUNK_DATARX_SIZEFAIL AX5043_CHUNK_DATARX_SIZEFAIL_Msk -#define AX5043_CHUNK_DATARX_ABORT_Pos (6U) -#define AX5043_CHUNK_DATARX_ABORT_Msk (0x1U << AX5043_CHUNK_DATARX_ABORT_Pos) -#define AX5043_CHUNK_DATARX_ABORT AX5043_CHUNK_DATARX_ABORT_Msk -/** @} */ - -/** - * @name AX5043 Frequency ranges - * @{ - */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief AX5043 SPI interface switch. - * @details If set to @p TRUE the support for SPI is included. - * @note The default is @p TRUE. - */ -#if !defined(AX5043_USE_SPI) || defined(__DOXYGEN__) -#define AX5043_USE_SPI TRUE -#endif - -/** - * @brief AX5043 shared SPI switch. - * @details If set to @p TRUE the device acquires SPI bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION. - */ -#if !defined(AX5043_SHARED_SPI) || defined(__DOXYGEN__) -#define AX5043_SHARED_SPI FALSE -#endif - -/** - * @brief Maximum frequency for RFDIV = 0 (DIV 1) - */ -#if !defined(AX5043_RFDIV_DIV1_MAX) || defined(__DOXYGEN__) -#define AX5043_RFDIV_DIV1_MAX (1050000000U) -#endif - -/** - * @brief Minimum frequency for RFDIV = 0 (DIV 1) - */ -#if !defined(AX5043_RFDIV_DIV1_MIN) || defined(__DOXYGEN__) -#define AX5043_RFDIV_DIV1_MIN (800000000U) -#endif - -/** - * @brief Maximum frequency for RFDIV = 1 (DIV 2) - */ -#if !defined(AX5043_RFDIV_DIV2_MAX) || defined(__DOXYGEN__) -#define AX5043_RFDIV_DIV2_MAX (525000000U) -#endif - -/** - * @brief Maximum frequency for RFDIV = 1 (DIV 2) - */ -#if !defined(AX5043_RFDIV_DIV2_MIN) || defined(__DOXYGEN__) -#define AX5043_RFDIV_DIV2_MIN (400000000U) -#endif - -/** - * @brief FIFO Write Length - */ -#if !defined(AX5043_FIFO_WRITE_LEN) || defined(__DOXYGEN__) -#define AX5043_FIFO_WRITE_LEN (128U) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if AX5043_USE_SPI && !HAL_USE_SPI -#error "AX5043_USE_SPI requires HAL_USE_SPI" -#endif - -#if AX5043_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION -#error "AX5043_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION" -#endif - -#if (AX5043_FIFO_WRITE_LEN > 256U) -#error "AX5043_FIFO_WRITE_LEN must be less than or equal to 256" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name AX5043 data structures and types. - * @{ - */ -/** - * @brief Structure representing a AX5043 driver. - */ -typedef struct AX5043Driver AX5043Driver; - -/** - * @brief AX5043 status bits. - */ -typedef uint16_t ax5043_status_t; - -/** - * @brief AX5043 TX buffer fill callback type. - * @details Callback used to fill the TX buffer with more data. - * - * @param arg User provided pointer - * - * @return The number of bytes written to the buffer. - * If 0, TX terminates. - */ -typedef size_t (*ax5043_tx_cb_t)(void *arg); - -/** - * @name AX5043 chunk structures. - * @{ - */ -/** - * @brief RSSI - */ -typedef struct __attribute__((packed)) { - int8_t rssi; -} ax5043_chunk_rssi_t; - -/** - * @brief TXCTRL - */ -typedef struct __attribute__((packed)) { - uint8_t header; - uint8_t length; - uint8_t flags; -} ax5043_chunk_txctrl_t; - -/** - * @brief FREQOFFS - */ -typedef struct __attribute__((packed)) { - uint16_t freqoffs; -} ax5043_chunk_freqoffs_t; - -/** - * @brief ANTRSSI2 - */ -typedef struct __attribute__((packed)) { - int8_t rssi; - int8_t bgndnoise; -} ax5043_chunk_antrssi2_t; - -/** - * @brief REPEATDATA - */ -typedef struct __attribute__((packed)) { - uint8_t header; - uint8_t length; - uint8_t flags; - uint8_t repeatcnt; - uint8_t data; -} ax5043_chunk_repeatdata_t; - -/** - * @brief TIMER - */ -typedef struct __attribute__((packed)) { - uint32_t timer; -} ax5043_chunk_timer_t; - -/** - * @brief RFFREQOFFS - */ -typedef struct __attribute__((packed)) { - uint32_t rffreqoffs; -} ax5043_chunk_rffreqoffs_t; - -/** - * @brief DATARATE - */ -typedef struct __attribute__((packed)) { - uint32_t datarate; -} ax5043_chunk_datarate_t; - -/** - * @brief ANTRSSI3 - */ -typedef struct __attribute__((packed)) { - int8_t ant0rssi; - int8_t ant1rssi; - int8_t bgndnoise; -} ax5043_chunk_antrssi3_t; - -/** - * @brief DATA RX - */ -typedef struct __attribute__((packed)) { - uint8_t flags; - uint8_t data[]; -} ax5043_chunk_data_t; - -/** - * @brief DATA TX - */ -typedef struct __attribute__((packed)) { - uint8_t header; - uint8_t length; - uint8_t flags; - uint8_t data[]; -} ax5043_chunk_data_tx_t; - -/** - * @brief TXPWR - */ -typedef struct __attribute__((packed)) { - uint8_t header; - uint8_t length; - uint16_t txpwrcoeffa; - uint16_t txpwrcoeffb; - uint16_t txpwrcoeffc; - uint16_t txpwrcoeffd; - uint16_t txpwrcoeffe; -} ax5043_chunk_txpwr_t; - -/** - * @brief FIFO Chunk union type - */ -typedef union __attribute__((packed)) { - ax5043_chunk_rssi_t rssi; - ax5043_chunk_freqoffs_t freqoffs; - ax5043_chunk_antrssi2_t antrssi2; - ax5043_chunk_timer_t timer; - ax5043_chunk_rffreqoffs_t rffreqoffs; - ax5043_chunk_datarate_t datarate; - ax5043_chunk_antrssi3_t antrssi3; - ax5043_chunk_data_t data; -} ax5043_rx_chunk_t; -/** @} */ - -/** - * @brief Ax5043 Register value pair type - */ -typedef struct { - uint16_t reg; - uint32_t val; - size_t len; -} ax5043_profile_t; - -/** - * @brief Error codes - */ -typedef enum { - AX5043_ERR_NOERROR, - AX5043_ERR_NOTSUPPORTED, - AX5043_ERR_BUSY, - AX5043_ERR_TIMEOUT, - AX5043_ERR_INVALID, - AX5043_ERR_NOCHIP, - AX5043_ERR_RANGING, - AX5043_ERR_LOCKLOST, - AX5043_ERR_RETRANSMISSION, - AX5043_ERR_RESYNC, - AX5043_ERR_RESYNCTIMEOUT, - AX5043_ERR_RECEIVESTART, - AX5043_ERR_FIFO_CHUNK, - AX5043_ERR_FIFO_CMD, - AX5043_ERR_UNEXPECTED_STATE, - AX5043_ERR_NOT_CONNECTED, - AX5043_ERR_REG_NOT_IN_CONF, - AX5043_ERR_VAL_NOT_IN_CONF, - AX5043_ERR_PLLRNG_VAL -} ax5043_err_t; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - AX5043_UNINIT, /**< Not initialized. */ - AX5043_STOP, /**< Stopped. */ - AX5043_RESET, /**< Reset. */ - AX5043_READY, /**< Ready. */ - AX5043_RX, /**< Receive. */ - AX5043_WOR, /**< Wake-On-Radio. */ - AX5043_TX /**< Transmit. */ -} ax5043_state_t; - -/** - * @brief AX5043 configuration structure. - */ -typedef struct{ -#if (AX5043_USE_SPI) || defined(__DOXYGEN__) - /** - * @brief SPI driver associated with this AX5043. - */ - SPIDriver *spip; - /** - * @brief SPI configuration associated with this AX5043. - */ - const SPIConfig *spicfg; - /** - * @brief PAL Line for MISO, to detect status of device - */ - ioline_t miso; -#endif /* AX5043_USE_SPI */ - /** - * @brief PAL Line for IRQ signal from radio - */ - ioline_t irq; - /** - * @brief XTAL Frequency in Hz - */ - uint32_t xtal_freq; - /** - * @brief Receive FIFO - */ - objects_fifo_t *fifo; - /** - * @brief Optional frame buffer PHY argument - */ - const void *phy_arg; - /** - * @brief Profile register values table - * @note This is for initial configuration and performance tuning. - * Certain registers may be overwritten later, either by - * the driver or a future call to @p ax5043SetProfile. - */ - const ax5043_profile_t *profile; - /** - * @brief Preamble pointer and length - */ - const void *preamble; - size_t preamble_len; - /** - * @brief Postamble pointer and length - */ - const void *postamble; - size_t postamble_len; -} AX5043Config; - -/** - * @brief AX5043 Radio class. - */ -struct AX5043Driver { - /* Driver state */ - ax5043_state_t state; - /* Current configuration data */ - const AX5043Config *config; - /* AX5043 Status bits as of last exchange */ - ax5043_status_t status; - /* Error state of device */ - ax5043_err_t error; - - /* TX state lock */ - mutex_t tx_lock; - - /* IRQ worker thread */ - thread_t *irq_worker; - /* IRQ event Source */ - event_source_t irq_event; - /* RX worker thread */ - thread_t *rx_worker; - - /* Currently active profile */ - const ax5043_profile_t *profile; - - /* Preamble buffer and length */ - const void *preamble; - size_t preamble_len; - /* Postamble buffer and length */ - const void *postamble; - size_t postamble_len; - - /* Last VCOR returned from ranging */ - uint8_t vcora; - uint8_t vcorb; - - /* RX information */ - uint32_t timer; - uint32_t datarate; - uint32_t freq_off; - uint32_t rf_freq_off; - int8_t rssi; - int8_t ant0rssi; - int8_t ant1rssi; - int8_t bgndnoise; -}; -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#define AX5043_FREQ_TO_REG(freq, ref) (((freq * UINT64_C(0x2000000) + ref) / (ref * 2)) | 0x01U) -#define AX5043_REG_TO_FREQ(reg, ref) (((reg & ~UINT64_C(1)) * ref) / UINT64_C(0x1000000)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void ax5043ObjectInit(AX5043Driver *devp); -void ax5043Start(AX5043Driver *devp, const AX5043Config *config); -void ax5043Stop(AX5043Driver *devp); - -void ax5043Idle(AX5043Driver *devp); -void ax5043RX(AX5043Driver *devp, bool chan_b, bool wor); -void ax5043TX(AX5043Driver *devp, const ax5043_profile_t *profile, const void *buf, size_t len, size_t total_len, ax5043_tx_cb_t tx_cb, void *tx_cb_arg, bool chan_b); -void ax5043TXRaw(AX5043Driver *devp, const ax5043_profile_t *profile, const void *buf, size_t len, size_t total_len, ax5043_tx_cb_t tx_cb, void *tx_cb_arg, bool chan_b); - -void ax5043SetProfile(AX5043Driver *devp, const ax5043_profile_t *profile); -const ax5043_profile_t *ax5043GetProfile(AX5043Driver *devp); -uint8_t ax5043SetFreq(AX5043Driver *devp, uint32_t freq, uint8_t vcor, bool chan_b); -uint32_t ax5043GetFreq(AX5043Driver *devp); -void ax5043SetPreamble(AX5043Driver *devp, const void *preamble, size_t len); -const void *ax5043GetPreamble(AX5043Driver *devp); -void ax5043SetPostamble(AX5043Driver *devp, const void *postamble, size_t len); -const void *ax5043GetPostamble(AX5043Driver *devp); - -ax5043_status_t ax5043Exchange(AX5043Driver *devp, uint16_t reg, bool write, const void *txbuf, void *rxbuf, size_t n); -ax5043_status_t ax5043GetStatus(AX5043Driver *devp); -uint8_t ax5043ReadU8(AX5043Driver *devp, uint16_t reg); -uint16_t ax5043ReadU16(AX5043Driver *devp, uint16_t reg); -uint32_t ax5043ReadU24(AX5043Driver *devp, uint16_t reg); -uint32_t ax5043ReadU32(AX5043Driver *devp, uint16_t reg); -void ax5043WriteU8(AX5043Driver *devp, uint16_t reg, uint8_t value); -void ax5043WriteU16(AX5043Driver *devp, uint16_t reg, uint16_t value); -void ax5043WriteU24(AX5043Driver *devp, uint16_t reg, uint32_t value); -void ax5043WriteU32(AX5043Driver *devp, uint16_t reg, uint32_t value); - -#ifdef __cplusplus -} -#endif - -#endif /* _AX5043_H_ */ - -/** @} */ diff --git a/common/include/can_bootloader.h b/common/include/can_bootloader.h deleted file mode 100644 index 9a44a095..00000000 --- a/common/include/can_bootloader.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _CAN_BOOTLOADER_H_ -#define _CAN_BOOTLOADER_H_ -#include "ch.h" -#include "hal.h" - -#define CAN_BOOTLOADER_ENABLE_SERIAL_DEBUG 0 - -#define ORESAT_F0_FLASH_PAGE_SIZE 2048 - -#define BOOTLOADER_EXPECTED_FIRST_FRAME_ID 0x79 -#define STM32_BOOTLOADER_SYNCHRONIZATION_SID 0x79 -#define CAN_ANNOUNCE_MAGIC_NUMBER 0x04030201 -#define STM32_BOOTLOADER_CAN_ACK 0x79 -#define STM32_BOOTLOADER_CAN_NACK 0x1F -#define STM32_BOOTLOADER_CAN_ANNOUNCE 0x47 -#define CAN_BOOTLOADER_WRITE_MEMORY_RESPONSE_SID 0x04 - - -typedef enum { - //ORESAT_BOOTLOADER_CAN_COMMAND_GET = 0x00, - ORESAT_BOOTLOADER_CAN_COMMAND_GET = 0x37, - - //ORESAT_BOOTLOADER_CAN_COMMAND_GET_VERSION = 0x01, - //ORESAT_BOOTLOADER_CAN_COMMAND_GET_ID = 0x02, - //ORESAT_BOOTLOADER_CAN_COMMAND_SPEED = 0x03, - ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY = 0x11, - ORESAT_BOOTLOADER_CAN_COMMAND_GO = 0x21, - ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY = 0x31, - ORESAT_BOOTLOADER_CAN_COMMAND_ERASE = 0x43, - //ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_PROTECT = 0x63, - //ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_UNPROTECT = 0x73, - //ORESAT_BOOTLOADER_CAN_COMMAND_READOUT_PROTECT = 0x82, - //ORESAT_BOOTLOADER_CAN_COMMAND_READOUT_UNPROTECT = 0x92, - ORESAT_BOOTLOADER_CAN_COMMAND_SET_OPT_DATA = 0x65 -} oresat_bootloader_can_command_t; - - -typedef uint32_t (*firmware_read_function_ptr_t)(const uint32_t offset, uint8_t *dest_buffer, const uint32_t number_of_bytes, void *arg0); - -typedef struct { - CANDriver *canp; - BaseSequentialStream *chp;//debug stream - uint32_t low_cpu_id; - bool stm32_bootloader_mode; - - void *read_function_arg0; - - uint32_t read_fail_count; - uint32_t write_fail_count; - uint32_t erase_fail_count; - uint32_t verify_fail_count; - uint32_t ack_count; - uint32_t nack_count; - uint32_t unknown_count; - uint32_t can_tx_fail_count; - uint32_t initiate_connection_count; - uint32_t connection_verify_fail; - - uint32_t update_duration_ms; -} can_bootloader_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -bool can_api_init_can_bootloader_config_t(can_bootloader_config_t *can_bl_config, CANDriver *canp, BaseSequentialStream *chp, const uint32_t low_cpu_id, const bool stm32_bootloader_mode, void *read_function_arg0); - -bool can_bootloader_initiate(can_bootloader_config_t *can_bl_config, const uint32_t timeout_ms); -void print_can_bootloader_config_t(BaseSequentialStream *chp, can_bootloader_config_t *can_bl_config); -bool oresat_firmware_update_m0(can_bootloader_config_t *can_bl_config, const uint32_t base_address, const uint32_t total_firmware_length_bytes, firmware_read_function_ptr_t read_function_pointer); - -const char* oresat_bootloader_can_command_t_to_str(const oresat_bootloader_can_command_t v); - -bool can_bootloader_set_opt_data(can_bootloader_config_t *can_bl_config, const uint8_t data_0_value, const uint8_t data_1_value); - -void can_api_purge_rx_buffer(can_bootloader_config_t *can_bl_config); -void can_api_print_rx_frame(BaseSequentialStream *chp, CANRxFrame *msg, const char *pre_msg, const char *post_msg); -void can_api_print_tx_frame(BaseSequentialStream *chp, CANTxFrame *msg, const char *pre_msg, const char *post_msg); -msg_t can_api_receive(can_bootloader_config_t *can_bl_config, CANRxFrame *msg, const uint32_t timeout_ms); - -//bool can_bootloader_test(can_bootloader_config_t *can_bl_config); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _CAN_BOOTLOADER_H_ */ diff --git a/common/include/can_hw.h b/common/include/can_hw.h index b0d67853..b48928fa 100644 --- a/common/include/can_hw.h +++ b/common/include/can_hw.h @@ -21,12 +21,6 @@ extern "C" { #if defined(STM32F0XX) // ~87.5% sample point 1Mbps based on 48MHz APB Clock #define CAN_BTR(n) (CAN_BTR_SJW(0)|CAN_BTR_TS1(12)|CAN_BTR_TS2(1)|CAN_BTR_BRP((3000/n)-1)) -#elif defined(STM32F4XX) -// ~87.5% sample point 1Mbps based on 42MHz APB1 Clock -#define CAN_BTR(n) (CAN_BTR_SJW(0)|CAN_BTR_TS1(10)|CAN_BTR_TS2(1)|CAN_BTR_BRP((3000/n)-1)) -#elif defined(STM32L4XX) -// ~87.5% sample point 1Mbps based on 80MHz APB1 Clock -#define CAN_BTR(n) (CAN_BTR_SJW(0)|CAN_BTR_TS1(12)|CAN_BTR_TS2(1)|CAN_BTR_BRP((5000/n)-1)) #else #error "No CAN Config for this MCU" #endif diff --git a/common/include/fram.h b/common/include/fram.h deleted file mode 100644 index 08f7196d..00000000 --- a/common/include/fram.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * @file fram.h - * @brief F-RAM Driver. - * - * @addtogroup FRAM - * @ingroup ORESAT - * @{ - */ -#ifndef _FRAM_H_ -#define _FRAM_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief FRAM Driver version string. - */ -#define FRAM_VERSION "1.0.0" - -/** - * @brief FRAM Driver version major number. - */ -#define FRAM_MAJOR 1 - -/** - * @brief FRAM Driver version minor number. - */ -#define FRAM_MINOR 0 - -/** - * @brief FRAM Driver version patch number. - */ -#define FRAM_PATCH 0 -/** @} */ - -/** - * @name FRAM Properties - * @{ - */ -/** - * @brief FRAM size. - */ -#define FRAM_SIZE 0x2000U -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FRAM I2C interface switch. - * @details If set to @p TRUE the support for I2C is included. - * @note The default is @p TRUE. - */ -#if !defined(FRAM_USE_I2C) || defined(__DOXYGEN__) -#define FRAM_USE_I2C TRUE -#endif - -/** - * @brief FRAM shared I2C switch. - * @details If set to @p TRUE the device acquires I2C bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION. - */ -#if !defined(FRAM_SHARED_I2C) || defined(__DOXYGEN__) -#define FRAM_SHARED_I2C FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if FRAM_USE_I2C && !HAL_USE_I2C -#error "FRAM_USE_I2C requires HAL_USE_I2C" -#endif - -#if FRAM_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION -#error "FRAM_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name FRAM data structures and types. - * @{ - */ -/** - * @brief Structure representing a FRAM driver. - */ -typedef struct FRAMDriver FRAMDriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - FRAM_UNINIT = 0, /**< Not initialized. */ - FRAM_STOP = 1, /**< Stopped. */ - FRAM_READY = 2, /**< Ready. */ -} fram_state_t; - -/** - * @brief FRAM configuration structure. - */ -typedef struct { -#if (FRAM_USE_I2C) || defined(__DOXYGEN__) - /** - * @brief I2C driver associated with this FRAM. - */ - I2CDriver *i2cp; - /** - * @brief I2C configuration associated with this FRAM. - */ - const I2CConfig *i2ccfg; - /** - * @brief FRAM Slave Address - */ - i2caddr_t saddr; -#endif /* FRAM_USE_I2C */ -} FRAMConfig; - -/** - * @brief @p FRAM specific methods. - */ -#define _fram_methods_alone - -/** - * @brief @p FRAM specific methods with inherited ones. - */ -#define _fram_methods \ - _base_object_methods - -/** - * @extends BaseObjectVMT - * - * @brief @p FRAM virtual methods table. - */ -struct FRAMVMT { - _fram_methods -}; - -/** - * @brief @p FRAMDriver specific data. - */ -#define _fram_data \ - _base_object_data \ - /* Driver state.*/ \ - fram_state_t state; \ - /* Current configuration data.*/ \ - const FRAMConfig *config; - -/** - * @brief FRAM Power Monitor class. - */ -struct FRAMDriver { - /** @brief Virtual Methods Table.*/ - const struct FRAMVMT *vmt; - _fram_data -}; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -extern FRAMDriver FRAMD1; - -void framObjectInit(FRAMDriver *devp); -void framStart(FRAMDriver *devp, const FRAMConfig *config); -void framStop(FRAMDriver *devp); -void framRead(FRAMDriver *devp, uint16_t addr, void *buf, size_t n); -void framWrite(FRAMDriver *devp, uint16_t addr, void *buf, size_t n); -void framErase(FRAMDriver *devp, uint16_t addr, size_t n); -void framEraseAll(FRAMDriver *devp); -#ifdef __cplusplus -} -#endif - -#endif /* _FRAM_H_ */ - -/** @} */ - diff --git a/common/include/fs.h b/common/include/fs.h deleted file mode 100644 index 7a089183..00000000 --- a/common/include/fs.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * @file fs.h - * @brief Filesystem driver. - * - * @addtogroup Filesystem - * @ingroup ORESAT - * @{ - */ -#ifndef _FS_H_ -#define _FS_H_ - -#include "lfs.h" -#include "lfs_util.h" - -/*============================================================================*/ -/* Driver constants. */ -/*============================================================================*/ - -/*============================================================================*/ -/* Driver pre-compile time settings. */ -/*============================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Filesystem Cache Sizes - */ -#if !defined(FS_CACHE_SIZE) || defined(__DOXYGEN__) -#define FS_CACHE_SIZE (512U) -#endif - -/** - * @brief Filesystem Lookahead buffer size - */ -#if !defined(FS_LOOKAHEAD_SIZE) || defined(__DOXYGEN__) -#define FS_LOOKAHEAD_SIZE (16U) -#endif - -/** - * @brief Maximum number of files open - */ -#if !defined(FS_MAX_HANDLERS) || defined(__DOXYGEN__) -#define FS_MAX_HANDLERS (4U) -#endif - -/** @} */ - -/*============================================================================*/ -/* Derived constants and error checks. */ -/*============================================================================*/ - -/*============================================================================*/ -/* Driver data structures and types. */ -/*============================================================================*/ - -/** - * @name Filesystem data structures and types. - * @{ - */ -/** - * @brief Structure representing a INA226 driver. - */ -typedef struct FSDriver FSDriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - FS_UNINIT = 0, /**< Not initialized. */ - FS_STOP = 1, /**< Stopped. */ - FS_OFFLINE = 2, /**< eMMC is offline. */ - FS_ONLINE = 3, /**< eMMC is online. */ - FS_MOUNTED = 4 /**< Filesystem is mounted. */ -} fs_state_t; - -/** - * @brief Filesystem configuration structure. - */ -typedef struct { - /** - * @brief SDC driver associated with this filesystem. - */ - SDCDriver *sdcp; - /** - * @brief SDC configuration associated with this filesystem. - */ - const SDCConfig *sdccfg; - /** - * @brief GPIO Line for enabling eMMC - */ - ioline_t mmc_pwr; -} FSConfig; - -/** - * @brief Filesystem driver object - */ -struct FSDriver { - /* Driver state */ - fs_state_t state; - /* Current configuration */ - const FSConfig *config; - /* Filesystem mutex */ - mutex_t mutex; - /* LFS object */ - lfs_t lfs; - /* LFS configuration */ - struct lfs_config lfscfg; - /* Last LFS error */ - int err; - /* MMC CID field */ - unpacked_mmc_cid_t mmc_cid; - /* MMC CSD field */ - unpacked_mmc_csd_t mmc_csd; - /* Guarded file pool */ - guarded_memory_pool_t file_pool; - lfs_file_t file[FS_MAX_HANDLERS]; - /* Guarded dir pool */ - guarded_memory_pool_t dir_pool; - lfs_file_t dir[FS_MAX_HANDLERS]; - /* TODO: Implement static file buffers */ - /* Read buffer */ - uint8_t read_buf[FS_CACHE_SIZE]; - /* Program buffer */ - uint8_t prog_buf[FS_CACHE_SIZE]; - /* Lookahead buffer */ - uint8_t lookahead_buf[FS_LOOKAHEAD_SIZE]; -}; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Default filesystem object */ -extern FSDriver FSD1; - -/* Driver functions */ -void fs_init(FSDriver *fsp); -void fs_start(FSDriver *fsp, const FSConfig *config); -void fs_stop(FSDriver *fsp); - -/* Filesystem operations */ -int fs_format(FSDriver *fsp); -int fs_mount(FSDriver *fsp, bool format); -int fs_unmount(FSDriver *fsp); -int fs_remove(FSDriver *fsp, const char *path); -int fs_rename(FSDriver *fsp, const char *oldpath, const char *newpath); -int fs_stat(FSDriver *fsp, const char *path, struct lfs_info *info); -lfs_ssize_t fs_getattr(FSDriver *fsp, const char *path, uint8_t type, void *buffer, lfs_size_t size); -int fs_setattr(FSDriver *fsp, const char *path, uint8_t type, const void *buffer, lfs_size_t size); -int fs_removeattr(FSDriver *fsp, const char *path, uint8_t type); -lfs_size_t fs_size(FSDriver *fsp); -uint8_t fs_usage(FSDriver *fsp); - -/* File operations */ -lfs_file_t *file_open(FSDriver *fsp, const char *path, int flags); -int file_close(FSDriver *fsp, lfs_file_t *file); -int file_sync(FSDriver *fsp, lfs_file_t *file); -lfs_ssize_t file_read(FSDriver *fsp, lfs_file_t *file, void *buffer, lfs_size_t size); -lfs_ssize_t file_write(FSDriver *fsp, lfs_file_t *file, const void *buffer, lfs_size_t size); -lfs_soff_t file_seek(FSDriver *fsp, lfs_file_t *file, lfs_soff_t off, int whence); -int file_truncate(FSDriver *fsp, lfs_file_t *file, lfs_soff_t size); -lfs_soff_t file_tell(FSDriver *fsp, lfs_file_t *file); -int file_rewind(FSDriver *fsp, lfs_file_t *file); -lfs_soff_t file_size(FSDriver *fsp, lfs_file_t *file); -uint32_t file_crc(FSDriver *fsp, lfs_file_t *file); - -/* Directory operations */ -int fs_mkdir(FSDriver *fsp, const char *path); -lfs_dir_t *dir_open(FSDriver *fsp, const char *path); -int dir_close(FSDriver *fsp, lfs_dir_t *dir); -int dir_read(FSDriver *fsp, lfs_dir_t *dir, struct lfs_info *info); -int dir_seek(FSDriver *fsp, lfs_dir_t *dir, lfs_soff_t off); -lfs_soff_t dir_tell(FSDriver *fsp, lfs_dir_t *dir); -int dir_rewind(FSDriver *fsp, lfs_dir_t *dir); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/common/include/lfs_util_custom.h b/common/include/lfs_util_custom.h deleted file mode 100644 index c10318c2..00000000 --- a/common/include/lfs_util_custom.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * lfs utility functions - * - * Copyright (c) 2017, Arm Limited. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef LFS_CONF_H -#define LFS_CONF_H - -// System includes -#include -#include -#include -#include -#include "ch.h" -#include "hal.h" - -#define LFS_THREADSAFE - -#ifndef LFS_NO_MALLOC -#include -#endif -#if !defined(LFS_NO_DEBUG) || \ - !defined(LFS_NO_WARN) || \ - !defined(LFS_NO_ERROR) || \ - defined(LFS_YES_TRACE) -#include "chprintf.h" -#endif - -#ifdef __cplusplus -extern "C" -{ -#endif - - -// Macros, may be replaced by system specific wrappers. Arguments to these -// macros must not have side-effects as the macros can be removed for a smaller -// code footprint - -// Logging functions -#ifdef LFS_YES_TRACE -#define LFS_TRACE_(fmt, ...) \ - chprintf((BaseSequentialStream*)&SD3, "%s:%d:trace: " fmt "%s\r\n", __FILE__, __LINE__, __VA_ARGS__) -#define LFS_TRACE(...) LFS_TRACE_(__VA_ARGS__, "") -#else -#define LFS_TRACE(...) -#endif - -#ifndef LFS_NO_DEBUG -#define LFS_DEBUG_(fmt, ...) \ - chprintf((BaseSequentialStream*)&SD3, "%s:%d:debug: " fmt "%s\r\n", __FILE__, __LINE__, __VA_ARGS__) -#define LFS_DEBUG(...) LFS_DEBUG_(__VA_ARGS__, "") -#else -#define LFS_DEBUG(...) -#endif - -#ifndef LFS_NO_WARN -#define LFS_WARN_(fmt, ...) \ - chprintf((BaseSequentialStream*)&SD3, "%s:%d:warn: " fmt "%s\r\n", __FILE__, __LINE__, __VA_ARGS__) -#define LFS_WARN(...) LFS_WARN_(__VA_ARGS__, "") -#else -#define LFS_WARN(...) -#endif - -#ifndef LFS_NO_ERROR -#define LFS_ERROR_(fmt, ...) \ - chprintf((BaseSequentialStream*)&SD3, "%s:%d:error: " fmt "%s\r\n", __FILE__, __LINE__, __VA_ARGS__) -#define LFS_ERROR(...) LFS_ERROR_(__VA_ARGS__, "") -#else -#define LFS_ERROR(...) -#endif - -// Runtime assertions -#ifndef LFS_NO_ASSERT -#define LFS_ASSERT(test) chDbgCheck(test) -#else -#define LFS_ASSERT(test) -#endif - - -// Builtin functions, these may be replaced by more efficient -// toolchain-specific implementations. LFS_NO_INTRINSICS falls back to a more -// expensive basic C implementation for debugging purposes - -// Min/max functions for unsigned 32-bit numbers -static inline uint32_t lfs_max(uint32_t a, uint32_t b) { - return (a > b) ? a : b; -} - -static inline uint32_t lfs_min(uint32_t a, uint32_t b) { - return (a < b) ? a : b; -} - -// Align to nearest multiple of a size -static inline uint32_t lfs_aligndown(uint32_t a, uint32_t alignment) { - return a - (a % alignment); -} - -static inline uint32_t lfs_alignup(uint32_t a, uint32_t alignment) { - return lfs_aligndown(a + alignment-1, alignment); -} - -// Find the smallest power of 2 greater than or equal to a -static inline uint32_t lfs_npw2(uint32_t a) { -#if !defined(LFS_NO_INTRINSICS) && (defined(__GNUC__) || defined(__CC_ARM)) - return 32 - __builtin_clz(a-1); -#else - uint32_t r = 0; - uint32_t s; - a -= 1; - s = (a > 0xffff) << 4; a >>= s; r |= s; - s = (a > 0xff ) << 3; a >>= s; r |= s; - s = (a > 0xf ) << 2; a >>= s; r |= s; - s = (a > 0x3 ) << 1; a >>= s; r |= s; - return (r | (a >> 1)) + 1; -#endif -} - -// Count the number of trailing binary zeros in a -// lfs_ctz(0) may be undefined -static inline uint32_t lfs_ctz(uint32_t a) { -#if !defined(LFS_NO_INTRINSICS) && defined(__GNUC__) - return __builtin_ctz(a); -#else - return lfs_npw2((a & -a) + 1) - 1; -#endif -} - -// Count the number of binary ones in a -static inline uint32_t lfs_popc(uint32_t a) { -#if !defined(LFS_NO_INTRINSICS) && (defined(__GNUC__) || defined(__CC_ARM)) - return __builtin_popcount(a); -#else - a = a - ((a >> 1) & 0x55555555); - a = (a & 0x33333333) + ((a >> 2) & 0x33333333); - return (((a + (a >> 4)) & 0xf0f0f0f) * 0x1010101) >> 24; -#endif -} - -// Find the sequence comparison of a and b, this is the distance -// between a and b ignoring overflow -static inline int lfs_scmp(uint32_t a, uint32_t b) { - return (int)(unsigned)(a - b); -} - -// Convert between 32-bit little-endian and native order -static inline uint32_t lfs_fromle32(uint32_t a) { -#if !defined(LFS_NO_INTRINSICS) && ( \ - (defined( BYTE_ORDER ) && defined( ORDER_LITTLE_ENDIAN ) && BYTE_ORDER == ORDER_LITTLE_ENDIAN ) || \ - (defined(__BYTE_ORDER ) && defined(__ORDER_LITTLE_ENDIAN ) && __BYTE_ORDER == __ORDER_LITTLE_ENDIAN ) || \ - (defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) - return a; -#elif !defined(LFS_NO_INTRINSICS) && ( \ - (defined( BYTE_ORDER ) && defined( ORDER_BIG_ENDIAN ) && BYTE_ORDER == ORDER_BIG_ENDIAN ) || \ - (defined(__BYTE_ORDER ) && defined(__ORDER_BIG_ENDIAN ) && __BYTE_ORDER == __ORDER_BIG_ENDIAN ) || \ - (defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)) - return __builtin_bswap32(a); -#else - return (((uint8_t*)&a)[0] << 0) | - (((uint8_t*)&a)[1] << 8) | - (((uint8_t*)&a)[2] << 16) | - (((uint8_t*)&a)[3] << 24); -#endif -} - -static inline uint32_t lfs_tole32(uint32_t a) { - return lfs_fromle32(a); -} - -// Convert between 32-bit big-endian and native order -static inline uint32_t lfs_frombe32(uint32_t a) { -#if !defined(LFS_NO_INTRINSICS) && ( \ - (defined( BYTE_ORDER ) && defined( ORDER_LITTLE_ENDIAN ) && BYTE_ORDER == ORDER_LITTLE_ENDIAN ) || \ - (defined(__BYTE_ORDER ) && defined(__ORDER_LITTLE_ENDIAN ) && __BYTE_ORDER == __ORDER_LITTLE_ENDIAN ) || \ - (defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) - return __builtin_bswap32(a); -#elif !defined(LFS_NO_INTRINSICS) && ( \ - (defined( BYTE_ORDER ) && defined( ORDER_BIG_ENDIAN ) && BYTE_ORDER == ORDER_BIG_ENDIAN ) || \ - (defined(__BYTE_ORDER ) && defined(__ORDER_BIG_ENDIAN ) && __BYTE_ORDER == __ORDER_BIG_ENDIAN ) || \ - (defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)) - return a; -#else - return (((uint8_t*)&a)[0] << 24) | - (((uint8_t*)&a)[1] << 16) | - (((uint8_t*)&a)[2] << 8) | - (((uint8_t*)&a)[3] << 0); -#endif -} - -static inline uint32_t lfs_tobe32(uint32_t a) { - return lfs_frombe32(a); -} - -// Calculate CRC-32 with polynomial = 0x04c11db7 -uint32_t lfs_crc(uint32_t crc, const void *buffer, size_t size); - -// Allocate memory, only used if buffers are not provided to littlefs -// Note, memory must be 64-bit aligned -static inline void *lfs_malloc(size_t size) { -#ifndef LFS_NO_MALLOC - return malloc(size); -#else - (void)size; - return NULL; -#endif -} - -// Deallocate memory, only used if buffers are not provided to littlefs -static inline void lfs_free(void *p) { -#ifndef LFS_NO_MALLOC - free(p); -#else - (void)p; -#endif -} - - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif diff --git a/common/include/max580x.h b/common/include/max580x.h deleted file mode 100644 index 26fdda4e..00000000 --- a/common/include/max580x.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - * @file max580x.h - * @brief MAX580X Digital to Analog Converter. - * - * @addtogroup MAX580X - * @ingroup ORESAT - * @{ - */ -#ifndef _MAX580X_H_ -#define _MAX580X_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief MAX580X Driver version string. - */ -#define MAX580X_VERSION "1.0.0" - -/** - * @brief MAX580X Driver version major number. - */ -#define MAX580X_MAJOR 1 - -/** - * @brief MAX580X Driver version minor number. - */ -#define MAX580X_MINOR 0 - -/** - * @brief MAX580X Driver version patch number. - */ -#define MAX580X_PATCH 0 -/** @} */ - -/** - * @name MAX580X Registers - * @{ - */ -#define MAX580X_AD_NOP (0U << 4) -#define MAX580X_AD_REF (2U << 4) -#define MAX580X_AD_SOFTWARE (3U << 4) -#define MAX580X_AD_POWER (4U << 4) -#define MAX580X_AD_CONFIG (5U << 4) -#define MAX580X_AD_DEFAULT (6U << 4) -#define MAX580X_AD_RETURN (7U << 4) -#define MAX580X_AD_CODE (8U << 4) -#define MAX580X_AD_LOAD (9U << 4) -#define MAX580X_AD_CODE_LOAD (10U << 4) -/** @} */ - -/** - * @name MAX580X REF Register fields - * @{ - */ -#define MAX580X_REF_EXT (0U << 0) -#define MAX580X_REF_2500 (1U << 0) -#define MAX580X_REF_2048 (2U << 0) -#define MAX580X_REF_4096 (3U << 0) -#define MAX580X_REF_INT_STBY (1U << 2) -#define MAX580X_REF_INT_EN (1U << 3) -/** @} */ - -/** - * @name MAX580X SOFTWARE Register fields - * @{ - */ -#define MAX580X_SOFTWARE_END (0U << 0) -#define MAX580X_SOFTWARE_GATE (1U << 0) -#define MAX580X_SOFTWARE_CLR (4U << 0) -#define MAX580X_SOFTWARE_RST (5U << 0) -/** @} */ - -/** - * @name MAX580X POWER Register fields - * @{ - */ -#define MAX580X_POWER_NORMAL (0U << 6) -#define MAX580X_POWER_1K (1U << 6) -#define MAX580X_POWER_100K (2U << 6) -#define MAX580X_POWER_HI_Z (3U << 6) -/** @} */ - -/** - * @name MAX580X CONFIG Register fields - * @{ - */ -#define MAX580X_CONFIG_AUX_GATE (3U << 3) -#define MAX580X_CONFIG_AUX_CLEAR (6U << 3) -#define MAX580X_CONFIG_AUX_NONE (7U << 3) -/** @} */ - -/** - * @name MAX580X DEFAULT Register Fields - * @{ - */ -#define MAX580X_DEFAULT_POR (0U << 5) -#define MAX580X_DEFAULT_ZERO (1U << 5) -#define MAX580X_DEFAULT_MID (2U << 5) -#define MAX580X_DEFAULT_FULL (3U << 5) -#define MAX580X_DEFAULT_RETURN (4U << 5) -/** @} */ - -/** - * @name MAX580X RETURN/CODE Data Fields - * @{ - */ -#define MAX580X_DAC2VAL(field,res) __REVSH(field >> (16 - res)) -#define MAX580X_VAL2DAC(val,res) __REVSH(val << (16 - res)) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief MAX580X I2C interface switch. - * @details If set to @p TRUE the support for I2C is included. - * @note The default is @p TRUE. - */ -#if !defined(MAX580X_USE_I2C) || defined(__DOXYGEN__) -#define MAX580X_USE_I2C TRUE -#endif - -/** - * @brief MAX580X shared I2C switch. - * @details If set to @p TRUE the device acquires I2C bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION. - */ -#if !defined(MAX580X_SHARED_I2C) || defined(__DOXYGEN__) -#define MAX580X_SHARED_I2C FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if MAX580X_USE_I2C && !HAL_USE_I2C -#error "MAX580X_USE_I2C requires HAL_USE_I2C" -#endif - -#if MAX580X_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION -#error "MAX580X_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name MAX580X data structures and types. - * @{ - */ -/** - * @brief Structure representing a MAX580X driver. - */ -typedef struct MAX580XDriver MAX580XDriver; - -/** - * @name MAX580X Part IDs - */ -typedef enum { - MAX5805 = 0x82, - MAX5803 = 0x8A, - MAX5804 = 0x92, -} max580x_devid_t; - -/** - * @name MAX580X DAC Resolutions - */ -typedef enum { - MAX5803_RES = 8, - MAX5804_RES = 10, - MAX5805_RES = 12, -} max580x_res_t; - -/** - * @name MAX580X DAC Registers - */ -typedef enum { - MAX580X_RETURN = MAX580X_AD_RETURN, - MAX580X_CODE = MAX580X_AD_CODE, - MAX580X_CODE_LOAD = MAX580X_AD_CODE_LOAD, -} max580x_reg_t; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MAX580X_UNINIT = 0, /**< Not initialized. */ - MAX580X_STOP = 1, /**< Stopped. */ - MAX580X_READY = 2, /**< Ready. */ -} max580x_state_t; - -/** - * @brief MAX580X configuration structure. - */ -typedef struct { -#if (MAX580X_USE_I2C) || defined(__DOXYGEN__) - /** - * @brief I2C driver associated with this MAX580X. - */ - I2CDriver *i2cp; - /** - * @brief I2C configuration associated with this MAX580X. - */ - const I2CConfig *i2ccfg; - /** - * @brief MAX580X Slave Address - */ - i2caddr_t saddr; -#endif /* MAX580X_USE_I2C */ - /** - * @brief MAX580X reference configuration - */ - uint8_t ref; - /** - * @brief MAX580X power configuration - */ - uint8_t power; - /** - * @brief MAX580X aux configuration - */ - uint8_t aux; - /** - * @brief MAX580X default configuration - */ - uint8_t default_cfg; -} MAX580XConfig; - -/** - * @brief @p MAX580X specific methods. - */ -#define _max580x_methods_alone - -/** - * @brief @p MAX580X specific methods with inherited ones. - */ -#define _max580x_methods \ - _base_object_methods - -/** - * @extends BaseObjectVMT - * - * @brief @p MAX580X virtual methods table. - */ -struct MAX580XVMT { - _max580x_methods -}; - -/** - * @brief @p MAX580XDriver specific data. - */ -#define _max580x_data \ - _base_object_data \ - /* Driver state.*/ \ - max580x_state_t state; \ - /* Current configuration data.*/ \ - const MAX580XConfig *config; \ - max580x_res_t res; \ - uint16_t range; - -/** - * @brief MAX710 GPIO Expander class. - */ -struct MAX580XDriver { - /** @brief Virtual Mthods Table.*/ - const struct MAX580XVMT *vmt; - _max580x_data -}; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void max580xObjectInit(MAX580XDriver *devp); -void max580xStart(MAX580XDriver *devp, const MAX580XConfig *config); -void max580xStop(MAX580XDriver *devp); -uint16_t max580xReadRaw(MAX580XDriver *devp, max580x_reg_t reg); -void max580xWriteRaw(MAX580XDriver *devp, max580x_reg_t reg, uint16_t value); -uint32_t max580xReadVoltage(MAX580XDriver *devp, max580x_reg_t reg); -void max580xWriteVoltage(MAX580XDriver *devp, max580x_reg_t reg, uint32_t voltage); -void max580xLoad(MAX580XDriver *devp); -#ifdef __cplusplus -} -#endif - -#endif /* _MAX580X_H_ */ - -/** @} */ diff --git a/common/include/max7310.h b/common/include/max7310.h deleted file mode 100644 index ee558ed8..00000000 --- a/common/include/max7310.h +++ /dev/null @@ -1,283 +0,0 @@ -/** - * @file max7310.h - * @brief MAX7310 GPIO Expander header. - * - * @addtogroup MAX7310 - * @ingroup ORESAT - * @{ - */ -#ifndef _MAX7310_H_ -#define _MAX7310_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief MAX7310 Driver version string. - */ -#define MAX7310_VERSION "1.0.0" - -/** - * @brief MAX7310 Driver version major number. - */ -#define MAX7310_MAJOR 1 - -/** - * @brief MAX7310 Driver version minor number. - */ -#define MAX7310_MINOR 0 - -/** - * @brief MAX7310 Driver version patch number. - */ -#define MAX7310_PATCH 0 -/** @} */ - -/** - * @name MAX7310 Device Characteristics - * - * @{ - */ - -#define MAX7310_MIN_ADDR 0x8 -#define MAX7310_MAX_ADDR 0x3F - -/** @} */ - -/** - * @name MAX7310 Register addresses - * @{ - */ -#define MAX7310_AD_INPUT 0x00 -#define MAX7310_AD_ODR 0x01 -#define MAX7310_AD_POL 0x02 -#define MAX7310_AD_MODE 0x03 -#define MAX7310_AD_TIMEOUT 0x04 -/** @} */ - -/** - * @name MAX7310 General IO pin register bits - * @{ - */ -#define MAX7310_REG_MASK 0xFF -#define MAX7310_PIN_MASK(n) (1 << n) -/** @} */ - -/** - * @name MAX7310 Output data register bits - * @{ - */ -#define MAX7310_PIN_ODR_LOW(n) (0 << n) -#define MAX7310_PIN_ODR_HIGH(n) (1 << n) -/** @} */ - -/** - * @name MAX7310 Polarity register bits - * @{ - */ -#define MAX7310_PIN_POL_STD(n) (0 << n) -#define MAX7310_PIN_POL_INV(n) (1 << n) -/** @} */ - -/** - * @name MAX7310 Mode register bits - * @{ - */ -#define MAX7310_PIN_MODE_OUTPUT(n) (0 << n) -#define MAX7310_PIN_MODE_INPUT(n) (1 << n) -/** @} */ - -/** - * @name MAX7310_TIMEOUT register bits - * @{ - */ -#define MAX7310_TIMEOUT_MASK 0x01 -#define MAX7310_TIMEOUT_EN 1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief MAX7310 I2C interface switch. - * @details If set to @p TRUE the support for I2C is included. - * @note The default is @p TRUE. - */ -#if !defined(MAX7310_USE_I2C) || defined(__DOXYGEN__) -#define MAX7310_USE_I2C TRUE -#endif - -/** - * @brief MAX7310 shared I2C switch. - * @details If set to @p TRUE the device acquires I2C bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION. - */ -#if !defined(MAX7310_SHARED_I2C) || defined(__DOXYGEN__) -#define MAX7310_SHARED_I2C FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if MAX7310_USE_I2C && !HAL_USE_I2C -#error "MAX7310_USE_I2C requires HAL_USE_I2C" -#endif - -#if MAX7310_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION -#error "MAX7310_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name MAX7310 data structures and types. - * @{ - */ -/** - * @brief Structure representing a MAX7310 driver. - */ -typedef struct MAX7310Driver MAX7310Driver; - -/** - * @brief MAX7310 timout configuration. - */ -typedef enum { - MAX7310_TIMEOUT_DISABLED = 0x00, /**< Timeout disabled. */ - MAX7310_TIMEOUT_ENABLED = 0x01 /**< Timeout enabled. */ -} max7310_timeout_t; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MAX7310_UNINIT = 0, /**< Not initialized. */ - MAX7310_STOP = 1, /**< Stopped. */ - MAX7310_READY = 2, /**< Ready. */ -} max7310_state_t; - -/** - * @brief MAX7310 configuration structure. - */ -typedef struct { -#if (MAX7310_USE_I2C) || defined(__DOXYGEN__) - /** - * @brief I2C driver associated with this MAX7310. - */ - I2CDriver *i2cp; - /** - * @brief I2C configuration associated with this MAX7310. - */ - const I2CConfig *i2ccfg; - /** - * @brief MAX7310 Slave Address - */ - i2caddr_t saddr; -#endif /* MAX7310_USE_I2C */ - /** - * @brief MAX7310 output states - */ - uint8_t odr; - /** - * @brief MAX7310 polarity inversion - */ - uint8_t pol; - /** - * @brief MAX7310 IO mode - */ - uint8_t iomode; - /** - * @brief MAX7310 timeout setting - */ - max7310_timeout_t timeout; -} MAX7310Config; - -/** - * @brief @p MAX7310 specific methods. - */ -#define _max7310_methods_alone \ - /* Change output state of MAX7310 ports.*/ \ - msg_t (*set_output)(MAX7310Driver *devp, uint8_t output); \ - /* Change polarity of MAX7310 ports.*/ \ - msg_t (*set_polarity)(MAX7310Driver *devp, uint8_t polarity); \ - /* Change IO mode of MAX7310 ports.*/ \ - msg_t (*set_iomode)(MAX7310Driver *devp, uint8_t iomode); \ - /* Change timeout setting of MAX7310.*/ \ - msg_t (*set_timeout)(MAX7310Driver *devp, max7310_timeout_t timeout); - -/** - * @brief @p MAX7310 specific methods with inherited ones. - */ -#define _max7310_methods \ - _base_object_methods - -/** - * @extends BaseObjectVMT - * - * @brief @p MAX7310 virtual methods table. - */ -struct MAX7310VMT { - _max7310_methods -}; - -/** - * @brief @p MAX7310Driver specific data. - */ -#define _max7310_data \ - _base_object_data \ - /* Driver state.*/ \ - max7310_state_t state; \ - /* Current configuration data.*/ \ - const MAX7310Config *config; - -/** - * @brief MAX710 GPIO Expander class. - */ -struct MAX7310Driver { - /** @brief Virtual Mthods Table.*/ - const struct MAX7310VMT *vmt; - _max7310_data -}; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void max7310ObjectInit(MAX7310Driver *devp); -void max7310Start(MAX7310Driver *devp, const MAX7310Config *config); -void max7310Stop(MAX7310Driver *devp); -uint8_t max7310ReadRaw(MAX7310Driver *devp, uint8_t reg); -void max7310WriteRaw(MAX7310Driver *devp, uint8_t reg, uint8_t value); -void max7310SetPin(MAX7310Driver *devp, uint8_t pin); -void max7310ClearPin(MAX7310Driver *devp, uint8_t pin); -void max7310TogglePin(MAX7310Driver *devp, uint8_t pin); -#ifdef __cplusplus -} -#endif - -#endif /* _MAX7310_H_ */ - -/** @} */ diff --git a/common/include/mmc5883ma.h b/common/include/mmc5883ma.h deleted file mode 100644 index 8979c8a7..00000000 --- a/common/include/mmc5883ma.h +++ /dev/null @@ -1,426 +0,0 @@ -/** - * @file mmc5883ma.h - * @brief MMC5883MA Power Monitor. - * - * @addtogroup MMC5883MA - * @ingroup ORESAT - * @{ - */ -#ifndef _MMC5883MA_H_ -#define _MMC5883MA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ - - -#define MMC5883MA_I2C_ADDRESS_READ (0x30) -#define MMC5883MA_I2C_ADDRESS_WRITE (0x30) - -#define MMC5883MA_EXPECTED_PRODUCT_CODE 0x0C - -//#define HMC5883L_I2C_ADDRESS_READ 0x3D -//#define HMC5883L_I2C_ADDRESSW_WRITE 0x3C -//#define HMC5883L_ID_REGISTER_A 0x0A - - -/** - * @brief MMC5883MA Driver version string. - */ -//#define MMC5883MA_VERSION "1.0.0" - -/** - * @brief MMC5883MA Driver version major number. - */ -//#define MMC5883MA_MAJOR 1 - -/** - * @brief MMC5883MA Driver version minor number. - */ -//#define MMC5883MA_MINOR 0 - -/** - * @brief MMC5883MA Driver version patch number. - */ -//#define MMC5883MA_PATCH 0 -/** @} */ - -/** - * @name MMC5883MA Register Addresses - * @{ - */ -#define MMC5883MA_AD_PRDCT_ID_1 0x2F -#define MMC5883MA_AD_Z_THRSHLD 0x0D -#define MMC5883MA_AD_Y_THRSHLD 0x0C -#define MMC5883MA_AD_X_THRSHLD 0x0B -#define MMC5883MA_AD_INTRNLCTRL2 0x0A -#define MMC5883MA_AD_INTRNLCTRL1 0x09 -#define MMC5883MA_AD_INTRNLCTRL0 0x08 -#define MMC5883MA_AD_STATUS 0x07 -#define MMC5883MA_AD_TEMPERATURE_OUT 0x06 -#define MMC5883MA_AD_ZOUT_HIGH 0x05 -#define MMC5883MA_AD_ZOUT_LOW 0x04 -#define MMC5883MA_AD_YOUT_HIGH 0x03 -#define MMC5883MA_AD_YOUT_LOW 0x02 -#define MMC5883MA_AD_XOUT_HIGH 0x01 -#define MMC5883MA_AD_XOUT_LOW 0x00 -/** @} */ - -/** - * @name MMC5883MA Product Id_1 register fields - * @{ - */ -#define MMC5883MA_PRDCT_ID_1_Pos (0U) -#define MMC5883MA_PRDCT_ID_1_Msk (0x7U << MMC5883MA_PRDCT_ID_1_Pos) -#define MMC5883MA_PRDCT_ID MMC5883MA_PRDCT_ID_1_Msk -#define MMC5883MA_PRDCT_ID_RST (0x0CU << MMC5883MA_PRDCT_ID_1_Pos) -/** @} */ - -/** - * @name MMC5883MA Z Threshold register fields - * @{ - */ -#define MMC5883MA_Z_THRSHLD_Z_MAG_TH_Pos (0U) -#define MMC5883MA_Z_THRSHLD_Z_MAG_TH_Msk (0xFFU << MMC5883MA_Z_THRSHLD_Z_MAG_TH_Pos) -#define MMC5883MA_Z_THRSHLD_Z_MAG_TH MMC5883MA_Z_THRSHLD_Z_MAG_TH_Msk -#define MMC5883MA_Z_THRSHLD_Z_MAG_TH_RST (0x00U << MMC5883MA_Z_THRSHLD_Z_MAG_TH_Pos) -/** @} */ - -/** - * @name MMC5883MA Y Threshold register fields - * @{ - */ -#define MMC5883MA_Y_THRSHLD_Y_MAG_TH_Pos (0U) -#define MMC5883MA_Y_THRSHLD_Y_MAG_TH_Msk (0xFFU << MMC5883MA_Y_THRSHLD_Y_MAG_TH_Pos) -#define MMC5883MA_Y_THRSHLD_Y_MAG_TH MMC5883MA_Y_THRSHLD_Y_MAG_TH_Msk -#define MMC5883MA_Y_THRSHLD_Y_MAG_TH_RST (0x00U << MMC5883MA_Y_THRSHLD_Y_MAG_TH_Pos) -/** @} */ - -/** - * @name MMC5883MA X Threshold register fields - * @{ - */ -//#define MMC5883MA_X_THRSHLD_X_MAG_TH_Pos (0U) -#define MMC5883MA_X_THRSHLD_X_MAG_TH_Msk (0xFFU << MMC5883MA_X_THRSHLD_X_MAG_TH_Pos) -#define MMC5883MA_X_THRSHLD_X_MAG_TH MMC5883MA_X_THRSHLD_X_MAG_TH_Msk -#define MMC5883MA_X_THRSHLD_X_MAG_TH_Pos (0x00U << MMC5883MA_X_THRSHLD_X_MAG_TH_Pos) -/** @} */ - -/** - * @name MMC5883MA Internal Control_2 register fields - * @{ - */ -#define MMC5883MA_INTRNLCTRL2_CM_FREQ_2200_mHz (0x03) -#define MMC5883MA_INTRNLCTRL2_CM_FREQ_1_Hz (0x04) - -#define MMC5883MA_INTRNLCTRL2_CM_FREQ_RST (0x1U << MMC5883MA_INTRNL_CTRL_2_CM_FREQ_Pos) -#define MMC5883MA_INTRNLCTRL2_MDT_Pos (5U) -#define MMC5883MA_INTRNLCTRL2_MDT_Msk (0x1U << MMC5883MA_INTRNLCTRL2_MDT_Pos) -#define MMC5883MA_INTRNLCTRL2_MDT MMC5883MA_INTRNLCTRL2_MDT_Msk -#define MMC5883MA_INTRNLCTRL2_MDT_EN (0x1U << MMC5883MA_INTRNLCTRL2_MDT_Pos) -#define MMC5883MA_INTRNLCTRL2_MDT_RST (0x0U << MMC5883MA_INTRNLCTRL2_MDT_Pos) -#define MMC5883MA_INTRNLCTRL2_MEAS_DONE_Pos (6U) -#define MMC5883MA_INTRNLCTRL2_MEAS_DONE_Msk (0x1U << MMC5883MA_INTRNLCTRL2_MEAS_DONE_Pos) -#define MMC5883MA_INTRNLCTRL2_MEAS_DONE MMC5883MA_INTRNLCTRL2_MEAS_DONE_Msk -#define MMC5883MA_INTRNLCTRL2_MEAS_DONE_EN (0x1U << MMC5883MA_INTRNLCTRL2_MEAS_DONE_Pos) -#define MMC5883MA_INTRNLCTRL2_MEAS_DONE_RST (0x0U << MMC5883MA_INTRNLCTRL2_MEAS_DONE_Pos) -/** @} */ - -/** - * @name MMC5883MA Internal Control_1 register fields - * @{ - */ -#define MMC5883MA_INTRNLCTRL1_BW_Pos (0U) -#define MMC5883MA_INTRNLCTRL1_BW_Msk (0x3U << MMC5883MA_INTRNLCTRL1_BW_Pos) -#define MMC5883MA_INTRNLCTRL1_BW MMC5883MA_INTRNLCTRL1_BW_Msk -#define MMC5883MA_INTRNLCTRL1_BW_ODR_100Hz (0x0U << MMC5883MA_INTRNLCTRL1_BW_Pos) -#define MMC5883MA_INTRNLCTRL1_BW_ODR_200Hz (0x1U << MMC5883MA_INTRNLCTRL1_BW_Pos) -#define MMC5883MA_INTRNLCTRL1_BW_ODR_400Hz (0x2U << MMC5883MA_INTRNLCTRL1_BW_Pos) -#define MMC5883MA_INTRNLCTRL1_BW_ODR_600Hz (0x3U << MMC5883MA_INTRNLCTRL1_BW_Pos) -#define MMC5883MA_INTRNLCTRL1_SW_RST_Pos (7U) -#define MMC5883MA_INTRNLCTRL1_SW_RST_CMD (0x1U << MMC5883MA_INTRNLCTRL1_SW_RST_Pos) -/** @} */ - -/** - * @name MMC5883MA Internal Control_0 register fields - * @{ - */ -#define MMC5883MA_INTRNLCTRL0_TM_M_Pos (0U) -#define MMC5883MA_INTRNLCTRL0_TM_M_Msk (0x1U << MMC5883MA_INTRNLCTRL0_TM_M_Pos) -#define MMC5883MA_INTRNLCTRL0_TM_M MMC5883MA_INTRNLCTRL0_TM_M_Msk -#define MMC5883MA_INTRNLCTRL0_TM_M_INIT (0x1U << MMC5883MA_INTRNLCTRL0_TM_M_Pos) -#define MMC5883MA_INTRNLCTRL0_TM_T_Pos (1U) -#define MMC5883MA_INTRNLCTRL0_TM_T_Msk (0x1U << MMC5883MA_INTRNLCTRL0_TM_T_Pos) -#define MMC5883MA_INTRNLCTRL0_TM_T MMC5883MA_INTRNLCTRL0_TM_T_Msk -#define MMC5883MA_INTRNLCTRL0_TM_T_INIT (0x1U << MMC5883MA_INTRNLCTRL0_TM_T_Pos) -#define MMC5883MA_INTRNLCTRL0_STRT_MDT_Pos (2U) -#define MMC5883MA_INTRNLCTRL0_STRT_MDT_Msk (0x1U << MMC5883MA_INTRNLCTRL0_STRT_MDT_Pos) -#define MMC5883MA_INTRNLCTRL0_STRT_MDT MMC5883MA_INTRNLCTRL0_STRT_MDT_Msk -#define MMC5883MA_INTRNLCTRL0_STRT_MDT_CMD (0x1U << MMC5883MA_INTRNLCTRL0_STRT_MDT_Pos) -#define MMC5883MA_INTRNLCTRL0_SET_Pos (3U) -#define MMC5883MA_INTRNLCTRL0_SET_Msk (0x1U << MMC5883MA_INTRNLCTRL0_SET_Pos) -#define MMC5883MA_INTRNLCTRL0_SET MMC5883MA_INTRNLCTRL0_SET_Msk -#define MMC5883MA_INTRNLCTRL0_SET_CMD (0x1U << MMC5883MA_INTRNLCTRL0_SET_Pos) -#define MMC5883MA_INTRNLCTRL0_RST_Pos (4U) -#define MMC5883MA_INTRNLCTRL0_RST_Msk (0x1U << MMC5883MA_INTRNLCTRL0_RST_Pos) -#define MMC5883MA_INTRNLCTRL0_RST MMC5883MA_INTRNLCTRL0_RST_Msk -#define MMC5883MA_INTRNLCTRL0_RST_CMD (0x1U << MMC5883MA_INTRNLCTRL0_RST_Pos) -#define MMC5883MA_INTRNLCTRL0_OTP_Pos (6U) -#define MMC5883MA_INTRNLCTRL0_OTP_Msk (0x1U << MMC5883MA_INTRNLCTRL0_OTP_Pos) -#define MMC5883MA_INTRNLCTRL0_OTP MMC5883MA_INTRNLCTRL0_OTP_Msk -#define MMC5883MA_INTRNLCTRL0_OTP_READ (0x1U << MMC5883MA_INTRNLCTRL0_OTP_Pos) -#define MMC5883MA_INTRNLCTRL0_TST_PIN_Pos (7U) -#define MMC5883MA_INTRNLCTRL0_TST_PIN_Msk (0x1U << MMC5883MA_INTRNLCTRL0_TST_PIN_Pos) -#define MMC5883MA_INTRNLCTRL0_TST_PIN MMC5883MA_INTRNLCTRL0_TST_PIN_Msk -#define MMC5883MA_INTRNLCTRL0_TST_PIN_SLCT (0x1U << MMC5883MA_INTRNLCTRL0_TST_PIN_Pos) -/** @} */ - -/** - * @name MMC5883MA Status register fields - * @{ - */ -#define MMC5883MA_STATUS_MEAS_M_DONE_Pos (0U) -#define MMC5883MA_STATUS_MEAS_M_DONE_Msk (0x1U << MMC5883MA_STATUS_MEAS_M_DONE_Pos) -#define MMC5883MA_STATUS_MEAS_M_DONE MMC5883MA_STATUS_MEAS_M_DONE_Msk -#define MMC5883MA_STATUS_MEAS_M_DONE_CLR (0x1U << MMC5883MA_STATUS_MEAS_M_DONE_Pos) -#define MMC5883MA_STATUS_MEAS_T_DONE_Pos (1U) -#define MMC5883MA_STATUS_MEAS_T_DONE_Msk (0x1U << MMC5883MA_STATUS_MEAS_T_DONE_Pos) -#define MMC5883MA_STATUS_MEAS_T_DONE MMC5883MA_STATUS_MEAS_T_DONE_Msk -#define MMC5883MA_STATUS_MEAS_T_DONE_CLR (0x1U << MMC5883MA_STATUS_MEAS_T_DONE_Pos) -#define MMC5883MA_STATUS_MD_Pos (2U) -#define MMC5883MA_STATUS_MD_Msk (0x1U << MMC5883MA_STATUS_MD_Pos) -#define MMC5883MA_STATUS_MD MMC5883MA_STATUS_MD_Msk -#define MMC5883MA_STATUS_MD_CLR (0x1U << MMC5883MA_STATUS_MD_Pos) -#define MMC5883MA_STATUS_PUMP_ON_Pos (3U) -#define MMC5883MA_STATUS_PUMP_ON_Msk (0x1U << MMC5883MA_STATUS_PUMP_ON_Pos) -#define MMC5883MA_STATUS_PUMP_ON MMC5883MA_STATUS_PUMP_ON_Msk -#define MMC5883MA_STATUS_OTP_RD_DONE_Pos (4U) -#define MMC5883MA_STATUS_OTP_RD_DONE_Msk (0x1U << MMC5883MA_STATUS_OTP_RD_DONE_Pos) -#define MMC5883MA_STATUS_OTP_RD_DONE MMC5883MA_STATUS_OTP_RD_DONE_Msk -/** @} */ - -/** - * @name MMC5883MA Temperature Out register fields - * @{ - */ -#define MMC5883MA_TEMPERATURE_OUT_Pos (0U) -#define MMC5883MA_TEMPERATURE_OUT_Msk (0xFFU << MMC5883MA_TEMPERATURE_Pos) -#define MMC5883MA_TEMPERATURE_OUT MMC5883MA_TEMPERATURE_Msk -/** @} */ - -/** - * @name MMC5883MA Zout High register fields - * @{ - */ -#define MMC5883MA_ZOUT_H_Pos (0U) -#define MMC5883MA_ZOUT_H_Msk (0xFFU << MMC5883MA_ZOUT_H_Pos) -#define MMC5883MA_ZOUT_H MMC5883MA_ZOUT_H_Msk -/** @} */ - -/** - * @name MMC5883MA Zout Low register fields - * @{ - */ -#define MMC5883MA_ZOUT_L_Pos (0U) -#define MMC5883MA_ZOUT_L_Msk (0xFFU << MMC5883MA_ZOUT_L_Pos) -#define MMC5883MA_ZOUT_L MMC5883MA_ZOUT_L_Msk -/** @} */ - -/** - * @name MMC5883MA Yout High register fields - * @{ - */ -#define MMC5883MA_YOUT_H_Pos (0U) -#define MMC5883MA_YOUT_H_Msk (0xFFU << MMC5883MA_YOUT_H_Pos) -//#define MMC5883MA_YOUT_H_Msk MMC5883MA_YOUT_H_Msk -/** @} */ - -/** - * @name MMC5883MA Yout Low register fields - * @{ - */ -#define MMC5883MA_YOUT_L_Pos (0U) -#define MMC5883MA_YOUT_L_Msk (0xFFU << MMC5883MA_YOUT_L_Pos) -#define MMC5883MA_YOUT_L MMC5883MA_YOUT_L_Msk -/** @} */ - -/** - * @name MMC5883MA Xout High register fields - * @{ - */ -#define MMC5883MA_XOUT_H_Pos (0U) -#define MMC5883MA_XOUT_H_Msk (0xFFU << MMC5883MA_XOUT_H_Pos) -#define MMC5883MA_XOUT_H MMC5883MA_XOUT_H_Msk -/** @} */ - -/** - * @name MMC5883MA Xout Low register fields - * @{ - */ -#define MMC5883MA_XOUT_L_Pos (0U) -#define MMC5883MA_XOUT_L_Msk (0xFFU << MMC5883MA_XOUT_L_Pos) -#define MMC5883MA_XOUT_L MMC5883MA_XOUT_L_Msk -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief MMC5883MA I2C interface switch. - * @details If set to @p TRUE the support for I2C is included. - * @note The default is @p TRUE. - */ -#if !defined(MMC5883MA_USE_I2C) || defined(__DOXYGEN__) -#define MMC5883MA_USE_I2C TRUE -#endif - -/** - * @brief MMC5883MA shared I2C switch. - * @details If set to @p TRUE the device acquires I2C bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION. - */ -#if !defined(MMC5883MA_SHARED_I2C) || defined(__DOXYGEN__) -#define MMC5883MA_SHARED_I2C FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if MMC5883MA_USE_I2C && !HAL_USE_I2C -#error "MMC5883MA_USE_I2C requires HAL_USE_I2C" -#endif - -#if MMC5883MA_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION -#error "MMC5883MA_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name MMC5883MA data structures and types. - * @{ - */ -/** - * @brief Structure representing a MMC5883MA driver. - */ -typedef struct MMC5883MADriver MMC5883MADriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MMC5883MA_UNINIT = 0, /**< Not initialized. */ - MMC5883MA_STOP = 1, /**< Stopped. */ - MMC5883MA_READY = 2, /**< Ready. */ -} mmc5883ma_state_t; - -/** - * @brief MMC5883MA configuration structure. - */ -typedef struct { -#if (MMC5883MA_USE_I2C) || defined(__DOXYGEN__) - /** - * @brief I2C driver associated with this MMC5883MA. - */ - I2CDriver *i2cp; - /** - * @brief I2C configuration associated with this MMC5883MA. - */ - const I2CConfig *i2ccfg; - /** - * @brief MMC5883MA Slave Address - */ - //i2caddr_t saddr; -#endif /* MMC5883MA_USE_I2C */ -} MMC5883MAConfig; - -/** - * @brief @p MMC5883MA specific methods. - */ -#define _mmc5883ma_methods_alone - -/** - * @brief @p MMC5883MA specific methods with inherited ones. - */ -#define _mmc5883ma_methods \ - _base_object_methods - -/** - * @extends BaseObjectVMT - * - * @brief @p MMC5883MA virtual methods table. - */ -struct MMC5883MAVMT { - _mmc5883ma_methods -}; - -/** - * @brief @p MMC5883MADriver specific data. - */ -#define _mmc5883ma_data \ - _base_object_data \ - /* Driver state.*/ \ - mmc5883ma_state_t state; \ - /* Current configuration data.*/ \ - const MMC5883MAConfig *config; \ - float bridge_offset_estimate_x; \ - float bridge_offset_estimate_y; \ - float bridge_offset_estimate_z; \ - uint32_t read_call_count; - -/** - * @brief MMC5883MA Power Monitor class. - */ -struct MMC5883MADriver { - /** @brief Virtual Methods Table.*/ - const struct MMC5883MAVMT *vmt; - _mmc5883ma_data -}; - -/** @} */ - -typedef struct { - int16_t mx; - int16_t my; - int16_t mz; -} mmc5883ma_data_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void mmc5883maObjectInit(MMC5883MADriver *devp); -bool mmc5883maStart(MMC5883MADriver *devp, const MMC5883MAConfig *config); -void mmc5883maStop(MMC5883MADriver *devp); -bool mmc5883maReadData(MMC5883MADriver *devp, mmc5883ma_data_t *dest); -bool mmc5883maI2CReadRegister3(I2CDriver *i2cp, const uint8_t i2c_address, const uint8_t reg_number, uint8_t *dest_value); -bool mmc5883maI2CReadRegister4(I2CDriver *i2cp, const uint8_t i2c_address, const uint8_t reg_number, uint16_t *dest_value); -#ifdef __cplusplus -} -#endif - -#endif /* _MMC5883MA_H_ */ - -/** @} */ diff --git a/common/include/morse.h b/common/include/morse.h deleted file mode 100644 index 3312530d..00000000 --- a/common/include/morse.h +++ /dev/null @@ -1,24 +0,0 @@ -/** - * @file morse.h - * @brief Morse code support code. - * - * @addtogroup MORSE - * @ingroup ORESAT - * @{ - */ -#ifndef _MORSE_H_ -#define _MORSE_H_ - -#ifdef __cplusplus -extern "C" { -#endif -void ax5043_morse_dot_dash(AX5043Driver *devp, uint16_t dot_dash_time); -const char *ax5043_ascii_to_morse(char letter); -void ax5043_send_cw(AX5043Driver *devp, int wpm, char beaconMessage[], uint16_t pktlen ); -#ifdef __cplusplus -} -#endif - -#endif /* _MORSE_H_ */ - -/** @} */ diff --git a/common/include/node_mgr.h b/common/include/node_mgr.h deleted file mode 100644 index a71b1ffe..00000000 --- a/common/include/node_mgr.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _NODE_MGR_H_ -#define _NODE_MGR_H_ - -#include "ch.h" -#include "hal.h" -#include "CANopen.h" -#include "OD.h" - -typedef struct oresat_node { - uint8_t id; - i2caddr_t opd_addr; - uint16_t timeout; - bool autostart; - char *name; -} oresat_node_t; - -#ifdef __cplusplus -extern "C" { -#endif - -extern THD_WORKING_AREA(node_mgr_wa, 0x400); -extern THD_FUNCTION(node_mgr, arg); -int node_enable(uint8_t id, bool enable); -int node_status(uint8_t id, CO_NMT_internalState_t *state); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif /*_NODE_MGR_H_*/ diff --git a/common/include/opd.h b/common/include/opd.h deleted file mode 100644 index e571ba72..00000000 --- a/common/include/opd.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef OPD_H -#define OPD_H - -#define OPD_MIN_ADDR 0x8 -#define OPD_MAX_ADDR 0x3F - -/* IO Pin Assignments */ -#define OPD_SCL 0U -#define OPD_SDA 1U -#define OPD_FAULT 2U -#define OPD_EN 3U -#define OPD_CB_RESET 4U -#define OPD_BOOT0 5U -#define OPD_LINUX_BOOT 6U -#define OPD_PIN7 7U - -#define OPD_PIN_MASK(n) (1U << (n)) - -#define OPD_PIN_ODR_LOW(n) (0U << (n)) -#define OPD_PIN_ODR_HIGH(n) (1U << (n)) -#define OPD_PIN_POL_STD(n) (0U << (n)) -#define OPD_PIN_POL_INV(n) (1U << (n)) -#define OPD_PIN_MODE_OUTPUT(n) (0U << (n)) -#define OPD_PIN_MODE_INPUT(n) (1U << (n)) - -/* IO Pin Configurations */ -#define OPD_ODR_VAL (OPD_PIN_ODR_LOW(OPD_SCL) | \ - OPD_PIN_ODR_LOW(OPD_SDA) | \ - OPD_PIN_ODR_LOW(OPD_FAULT) | \ - OPD_PIN_ODR_LOW(OPD_EN) | \ - OPD_PIN_ODR_LOW(OPD_CB_RESET) | \ - OPD_PIN_ODR_LOW(OPD_BOOT0) | \ - OPD_PIN_ODR_HIGH(OPD_LINUX_BOOT) | \ - OPD_PIN_ODR_LOW(OPD_PIN7)) -#define OPD_POL_VAL (OPD_PIN_POL_STD(OPD_SCL) | \ - OPD_PIN_POL_STD(OPD_SDA) | \ - OPD_PIN_POL_INV(OPD_FAULT) | \ - OPD_PIN_POL_STD(OPD_EN) | \ - OPD_PIN_POL_STD(OPD_CB_RESET) | \ - OPD_PIN_POL_STD(OPD_BOOT0) | \ - OPD_PIN_POL_STD(OPD_LINUX_BOOT) | \ - OPD_PIN_POL_STD(OPD_PIN7)) -#define OPD_MODE_VAL (OPD_PIN_MODE_INPUT(OPD_SCL) | \ - OPD_PIN_MODE_INPUT(OPD_SDA) | \ - OPD_PIN_MODE_INPUT(OPD_FAULT) | \ - OPD_PIN_MODE_OUTPUT(OPD_EN) | \ - OPD_PIN_MODE_OUTPUT(OPD_CB_RESET) | \ - OPD_PIN_MODE_OUTPUT(OPD_BOOT0) | \ - OPD_PIN_MODE_OUTPUT(OPD_LINUX_BOOT)| \ - OPD_PIN_MODE_OUTPUT(OPD_PIN7)) - -typedef struct { - uint8_t input; - uint8_t odr; - uint8_t pol; - uint8_t mode; - uint8_t timeout; -} opd_status_t; - -void opd_init(void); -void opd_start(void); -void opd_stop(void); -void opd_scan(bool restart); -bool opd_probe(i2caddr_t addr, bool restart); -int opd_enable(i2caddr_t addr, bool enable); -int opd_disable(i2caddr_t addr); -int opd_reset(i2caddr_t addr); -int opd_status(i2caddr_t addr, opd_status_t *status); - -int opd_boot(i2caddr_t addr); -int opd_linux_recover(i2caddr_t addr, bool enable); -#endif diff --git a/common/include/oresat_f0.h b/common/include/oresat_f0.h index 74cc046b..5a44bf1c 100644 --- a/common/include/oresat_f0.h +++ b/common/include/oresat_f0.h @@ -5,7 +5,7 @@ extern "C" { #endif -// See STM32F091xC-bootloader.ld/STM32F4091xC-app.ld for definitions and +// See STM32F091xC-bootloader.ld/STM32F091xC-app.ld for definitions and // rules_memory.ld for declarations. extern uint8_t __flash0_base__[]; extern uint8_t __flash0_end__[]; diff --git a/common/include/radio.h b/common/include/radio.h deleted file mode 100644 index 92a6cf95..00000000 --- a/common/include/radio.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file radio.h - * @brief OreSat radio support library. - * - * @addtogroup RADIO - * @ingroup ORESAT - * @{ - */ -#ifndef _RADIO_H_ -#define _RADIO_H_ - -#include "ch.h" -#include "hal.h" -#include "ax5043.h" -#include "si41xx.h" -#include "frame_buf.h" - -/*===========================================================================*/ -/* Constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Pre-compile time settings. */ -/*===========================================================================*/ - -#if !defined(RADIO_FIFO_COUNT) || defined(__DOXYGEN__) -#define RADIO_FIFO_COUNT 8U -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Data structures and types. */ -/*===========================================================================*/ - -typedef struct { - SI41XXDriver *devp; - SI41XXConfig *cfgp; - const char *name; -} synth_dev_t; - -typedef struct { - AX5043Driver *devp; - const AX5043Config *cfgp; - const char *name; -} radio_dev_t; - -typedef struct { - AX5043Driver *devp; - const ax5043_profile_t *profile; - const char *name; -} radio_cfg_t; - -/*===========================================================================*/ -/* Macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -extern synth_dev_t synth_devices[]; -extern radio_dev_t radio_devices[]; -extern radio_cfg_t radio_cfgs[]; -extern objects_fifo_t rx_fifo; -extern objects_fifo_t tx_fifo; - -void radio_init(void); -void radio_start(void); -void radio_stop(void); - -void pdu_send(fb_t *fb, void *arg); -void pdu_send_ahead(fb_t *fb, void *arg); -fb_t *pdu_recv(void *arg); - -#ifdef __cplusplus -} -#endif - -#endif /* _RADIO_H_ */ - -/** @} */ diff --git a/common/include/rtc.h b/common/include/rtc.h deleted file mode 100644 index 417d3c0c..00000000 --- a/common/include/rtc.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef RTC_H -#define RTC_H - -#include -#include "ch.h" -#include "hal.h" -#include "CANopen.h" - -/* Preamble definitions - * While Level 1 Time Codes are generally preferred by CCSDS, we are using - * Level 2 Time Codes (meaning Agency Defined). In this case we are using - * the UNIX Epoch of Jan 1, 1970. - * Refer to CCSDS 301.0-B-4 for Time Code Formats. - * TODO: Verify that the bit order is correct for preambles - */ -#define TIME_CUC_PREAMBLE 0x2E /* CCSDS Unsegmented Time Code (CUC) Preamble */ -#define TIME_CDS_PREAMBLE 0x49 /* CCSDS Day Segmented Time Code (CDS) Preamble */ - -#define RTC_WEEKDAY_SEL RTC_ALRMAR_WDSEL -#define RTC_DATE_MASK RTC_ALRMAR_MSK4 -#define RTC_HOUR_MASK RTC_ALRMAR_MSK3 -#define RTC_MIN_MASK RTC_ALRMAR_MSK2 -#define RTC_SEC_MASK RTC_ALRMAR_MSK1 - -/* CCSDS Unsegmented Time Code (CUC) data type */ -typedef union { - uint64_t raw; - struct { - uint32_t coarse:32; - uint32_t fine:24; - }; -} time_scet_t; - -/* CCSDS Day Segmented Time Code (CDS) data type */ -typedef union { - uint64_t raw; - struct { - uint16_t day:16; - uint32_t ms:32; - uint16_t us:16; - }; -} time_utc_t; - -#ifdef __cplusplus -extern "C" { -#endif - -time_t rtcConvertDateTimeToUnix(const RTCDateTime *timespec, uint32_t *msec); -void rtcConvertUnixToDateTime(RTCDateTime *timespec, time_t unix_time, uint32_t msec); - -void rtcGetTimeTm(struct tm *tim, uint32_t *msec); -void rtcSetTimeTm(const struct tm *tim, uint32_t msec); -time_t rtcGetTimeUnix(uint32_t *msec); -void rtcSetTimeUnix(time_t unix_time, uint32_t msec); -void rtcGetTimeSCET(time_scet_t *scet); -void rtcSetTimeSCET(const time_scet_t *scet); -void rtcGetTimeUTC(time_utc_t *utc); -void rtcSetTimeUTC(const time_utc_t *utc); - -uint32_t rtcEncodeAlarm(const RTCDateTime *timespec, uint32_t flags); -uint32_t rtcEncodeRelAlarm(const RTCDateTime *timespec, int days, int hours, int minutes, int seconds); - -/* -CO_SDO_abortCode_t OD_SCET_Func(CO_ODF_arg_t *ODF_arg); -CO_SDO_abortCode_t OD_UTC_Func(CO_ODF_arg_t *ODF_arg); -*/ - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif /*RTC_H*/ diff --git a/common/include/sensors.h b/common/include/sensors.h index 5b733abe..06f96af4 100644 --- a/common/include/sensors.h +++ b/common/include/sensors.h @@ -17,52 +17,6 @@ extern "C" { ADC_SMPR_SMP_239P5, /* SMPR */ \ ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17 /* CHSELR */ #define ADC_ENABLE_SENSORS(adc) {adcSTM32SetCCR(ADC_CCR_TSEN | ADC_CCR_VREFEN);} -#elif defined(STM32F4xx_MCUCONF) -#define TS_CAL1_BASE ((uint32_t)0x1FFF7A2C) -#define TS_CAL2_BASE ((uint32_t)0x1FFF7A2E) -#define VREFINT_CAL_BASE ((uint32_t)0x1FFF7A2A) -#define TS_CAL1_TEMP 30 -#define TS_CAL2_TEMP 110 -#define VREFINT_CAL_VOLT 330 -#define ADC_REG_CFG 0, /* CR1 */ \ - ADC_CR2_SWSTART, /* CR2 */ \ - ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_480) /* SMPR1 */ \ - | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_480), \ - 0, /* SMPR2 */ \ - 0, /* HTR */ \ - 0, /* LTR */ \ - 0, /* SQR1 */ \ - 0, /* SQR2 */ \ - ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) /* SQR3 */ \ - | ADC_SQR3_SQ2_N(ADC_CHANNEL_VREFINT) -#define ADC_ENABLE_SENSORS(adc) {adcSTM32EnableTSVREFE();} -#elif defined(STM32L4xx_MCUCONF) -#define TS_CAL1_BASE ((uint32_t)0x1FFF75A8) -#define TS_CAL2_BASE ((uint32_t)0x1FFF75CA) -#define VREFINT_CAL_BASE ((uint32_t)0x1FFF75AA) -#define TS_CAL1_TEMP 30 -#define TS_CAL2_TEMP 130 -#define VREFINT_CAL_VOLT 330 -#define ADC_REG_CFG ADC_CFGR_CONT, /* CFGR */ \ - 0, /* CFGR2 */ \ - ADC_TR(0, 4095), /* TR1 */ \ - 0, /* TR2 */ \ - 0, /* TR3 */ \ - 0, /* AWD2CR */ \ - 0, /* AWD3CR */ \ - { /* SMPR[2] */ \ - 0, \ - ADC_SMPR2_SMP_AN16(ADC_SMPR_SMP_47P5) \ - | ADC_SMPR2_SMP_AN17(ADC_SMPR_SMP_47P5), \ - }, \ - { /* SQR[4] */ \ - ADC_SQR1_SQ1_N(ADC_CHANNEL_IN16) \ - | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN17), \ - 0, \ - 0, \ - 0 \ - } -#define ADC_ENABLE_SENSORS(adc) {adcSTM32EnableTS(adc); adcSTM32EnableVREF(adc);} #else #error "No Sensors Config for this MCU" #endif diff --git a/common/include/si41xx.h b/common/include/si41xx.h deleted file mode 100644 index 288768dd..00000000 --- a/common/include/si41xx.h +++ /dev/null @@ -1,390 +0,0 @@ -/** - * @file si41xx.h - * @brief SI41XX Radio. - * - * @addtogroup SI41XX - * @ingroup ORESAT - * @{ - */ -#ifndef _SI41XX_H_ -#define _SI41XX_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief SI41XX Driver version string. - */ -#define SI41XX_VERSION "1.0.0" - -/** - * @brief SI41XX Driver version major number. - */ -#define SI41XX_MAJOR 1 - -/** - * @brief SI41XX Driver version minor number. - */ -#define SI41XX_MINOR 0 - -/** - * @brief SI41XX Driver version patch number. - */ -#define SI41XX_PATCH 0 -/** @} */ - -/** - * @name Device Types - * @{ - */ -#define SI4112 0 -#define SI4113 1 -#define SI4122 2 -#define SI4123 3 -#define SI4133 4 -/** @} */ - -/** - * @name SI41XX Register Addresses - * @{ - */ -#define SI41XX_REG_CONFIG 0x0U -#define SI41XX_REG_PHASE_GAIN 0x1U -#define SI41XX_REG_PWRDOWN 0x2U -#define SI41XX_REG_RF1_NDIV 0x3U -#define SI41XX_REG_RF2_NDIV 0x4U -#define SI41XX_REG_IF_NDIV 0x5U -#define SI41XX_REG_RF1_RDIV 0x6U -#define SI41XX_REG_RF2_RDIV 0x7U -#define SI41XX_REG_IF_RDIV 0x8U -/** @} */ - -/** - * @name SI41XX Main Configuration register fields - * @{ - */ -#define SI41XX_CONFIG_RFPWR_Pos (1U) -#define SI41XX_CONFIG_RFPWR_Msk (0x1U << SI41XX_CONFIG_RFPWR_Pos) -#define SI41XX_CONFIG_RFPWR SI41XX_CONFIG_RFPWR_Msk -#define SI41XX_CONFIG_AUTOKP_Pos (2U) -#define SI41XX_CONFIG_AUTOKP_Msk (0x1U << SI41XX_CONFIG_AUTOKP_Pos) -#define SI41XX_CONFIG_AUTOKP SI41XX_CONFIG_AUTOKP_Msk -#define SI41XX_CONFIG_AUTOPDB_Pos (3U) -#define SI41XX_CONFIG_AUTOPDB_Msk (0x1U << SI41XX_CONFIG_AUTOPDB_Pos) -#define SI41XX_CONFIG_AUTOPDB SI41XX_CONFIG_AUTOPDB_Msk -#define SI41XX_CONFIG_LPWR_Pos (5U) -#define SI41XX_CONFIG_LPWR_Msk (0x1U << SI41XX_CONFIG_LPWR_Pos) -#define SI41XX_CONFIG_LPWR SI41XX_CONFIG_LPWR_Msk -#define SI41XX_CONFIG_IFDIV_Pos (10U) -#define SI41XX_CONFIG_IFDIV_Msk (0x3U << SI41XX_CONFIG_IFDIV_Pos) -#define SI41XX_CONFIG_IFDIV SI41XX_CONFIG_IFDIV_Msk -#define SI41XX_IFDIV_DIV1 (0x0U) -#define SI41XX_IFDIV_DIV2 (0x1U) -#define SI41XX_IFDIV_DIV4 (0x2U) -#define SI41XX_IFDIV_DIV8 (0x3U) -#define SI41XX_CONFIG_AUXSEL_Pos (12U) -#define SI41XX_CONFIG_AUXSEL_Msk (0x3U << SI41XX_CONFIG_AUXSEL_Pos) -#define SI41XX_CONFIG_AUXSEL SI41XX_CONFIG_AUXSEL_Msk -#define SI41XX_AUXSEL_LOW (0x1U) -#define SI41XX_AUXSEL_LOCKDET (0x3U) -/** @} */ - -/** - * @name SI41XX Phase Detector Gain register fields - * @{ - */ -#define SI41XX_PHASEGAIN_KP1_Pos (0U) -#define SI41XX_PHASEGAIN_KP1_Msk (0x3U << SI41XX_PHASEGAIN_KP1_Pos) -#define SI41XX_PHASEGAIN_KP1 SI41XX_PHASEGAIN_KP1_Msk -#define SI41XX_PHASEGAIN_KP2_Pos (2U) -#define SI41XX_PHASEGAIN_KP2_Msk (0x3U << SI41XX_PHASEGAIN_KP2_Pos) -#define SI41XX_PHASEGAIN_KP2 SI41XX_PHASEGAIN_KP2_Msk -#define SI41XX_PHASEGAIN_KPI_Pos (4U) -#define SI41XX_PHASEGAIN_KPI_Msk (0x3U << SI41XX_PHASEGAIN_KPI_Pos) -#define SI41XX_PHASEGAIN_KPI SI41XX_PHASEGAIN_KPI_Msk -/** @} */ - -/** - * @name SI41XX Powerdown register fields - * @{ - */ -#define SI41XX_POWERDOWN_PBRB_Pos (0U) -#define SI41XX_POWERDOWN_PBRB_Msk (0x1U << SI41XX_POWERDOWN_PBRB_Pos) -#define SI41XX_POWERDOWN_PBRB SI41XX_POWERDOWN_PBRB_Msk -#define SI41XX_POWERDOWN_PBIB_Pos (1U) -#define SI41XX_POWERDOWN_PBIB_Msk (0x1U << SI41XX_POWERDOWN_PBIB_Pos) -#define SI41XX_POWERDOWN_PBIB SI41XX_POWERDOWN_PBIB_Msk -/** @} */ - -/** - * @name SI41XX RF1 N-Divider register fields - * @{ - */ -#define SI41XX_RF1_NDIV_Pos (0U) -#define SI41XX_RF1_NDIV_Msk (0x3FFFFU << SI41XX_RF1_NDIV_Pos) -#define SI41XX_RF1_NDIV SI41XX_RF1_NDIV_Msk -/** @} */ - -/** - * @name SI41XX RF2 N-Divider register fields - * @{ - */ -#define SI41XX_RF2_NDIV_Pos (0U) -#define SI41XX_RF2_NDIV_Msk (0x1FFFFU << SI41XX_RF2_NDIV_Pos) -#define SI41XX_RF2_NDIV SI41XX_RF2_NDIV_Msk -/** @} */ - -/** - * @name SI41XX IF N-Divider register fields - * @{ - */ -#define SI41XX_IF_NDIV_Pos (0U) -#define SI41XX_IF_NDIV_Msk (0xFFFFU << SI41XX_IF_NDIV_Pos) -#define SI41XX_IF_NDIV SI41XX_IF_NDIV_Msk -/** @} */ - -/** - * @name SI41XX RF1 R-Divider register fields - * @{ - */ -#define SI41XX_RF1_RDIV_Pos (0U) -#define SI41XX_RF1_RDIV_Msk (0x1FFFU << SI41XX_RF1_RDIV_Pos) -#define SI41XX_RF1_RDIV SI41XX_RF1_RDIV_Msk -/** @} */ - -/** - * @name SI41XX RF2 R-Divider register fields - * @{ - */ -#define SI41XX_RF2_RDIV_Pos (0U) -#define SI41XX_RF2_RDIV_Msk (0x1FFFU << SI41XX_RF2_RDIV_Pos) -#define SI41XX_RF2_RDIV SI41XX_RF2_RDIV_Msk -/** @} */ - -/** - * @name SI41XX IF R-Divider register fields - * @{ - */ -#define SI41XX_IF_RDIV_Pos (0U) -#define SI41XX_IF_RDIV_Msk (0x1FFFU << SI41XX_IF_RDIV_Pos) -#define SI41XX_IF_RDIV SI41XX_IF_RDIV_Msk -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief SI41XX device type. - * @details Defines the device type, which defines features availabe. - * @note The default is @p TRUE. - */ -#if !defined(SI41XX_DEVICE) || defined(__DOXYGEN__) -#define SI41XX_DEVICE SI4133 -#endif - -/** - * @brief SI41XX Mutual Exclusion. - * @details Enables mutual exclusion code for SI41XX driver. - * @note The default is @p TRUE. - */ -#if !defined(SI41XX_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SI41XX_USE_MUTUAL_EXCLUSION FALSE -#endif - -/** - * @brief SI41XX SERIAL interface switch. - * @details If set to @p TRUE the support for SI41XX SERIAL is included. - * @note The default is @p TRUE. - */ -#if !defined(SI41XX_USE_SERIAL) || defined(__DOXYGEN__) -#define SI41XX_USE_SERIAL TRUE -#endif - -/** - * @brief SI41XX shared SERIAL switch. - * @details If set to @p TRUE the device acquires SI41XX SERIAL bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires SI41XX_USE_MUTUAL_EXCLUSION. - */ -#if !defined(SI41XX_SHARED_SERIAL) || defined(__DOXYGEN__) -#define SI41XX_SHARED_SERIAL FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if SI41XX_USE_SERIAL && !HAL_USE_PAL -#error "SI41XX_USE_SERIAL requires HAL_USE_PAL" -#endif - -#if SI41XX_SHARED_SERIAL && !SI41XX_USE_MUTUAL_EXCLUSION -#error "SI41XX_SHARED_SERIAL requires SI41XX_USE_MUTUAL_EXCLUSION" -#endif - -#if (SI41XX_DEVICE != SI4112 && \ - SI41XX_DEVICE != SI4113 && \ - SI41XX_DEVICE != SI4122 && \ - SI41XX_DEVICE != SI4123 && \ - SI41XX_DEVICE != SI4133) -#error "SI41XX_DEVICE is unknown device type" -#endif - -#if (SI41XX_DEVICE == SI4112 || SI41XX_DEVICE == SI4122 || SI41XX_DEVICE == SI4123 || SI41XX_DEVICE == SI4133) -#define SI41XX_HAS_IF TRUE -#else -#define SI41XX_HAS_IF FALSE -#endif - -#if (SI41XX_DEVICE == SI4113 || SI41XX_DEVICE == SI4123 || SI41XX_DEVICE == SI4133) -#define SI41XX_HAS_RF1 TRUE -#else -#define SI41XX_HAS_RF1 FALSE -#endif - -#if (SI41XX_DEVICE == SI4113 || SI41XX_DEVICE == SI4122 || SI41XX_DEVICE == SI4133) -#define SI41XX_HAS_RF2 TRUE -#else -#define SI41XX_HAS_RF2 FALSE -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name SI41XX data structures and types. - * @{ - */ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SI41XX_UNINIT, /**< Not initialized. */ - SI41XX_STOP, /**< Stopped. */ - SI41XX_READY /**< Ready. */ -} si41xx_state_t; - -/** - * @brief SI41XX configuration structure. - */ -typedef struct{ -#if (SI41XX_USE_SERIAL) || defined(__DOXYGEN__) - /** - * @brief SI41XX SERIAL Enable Line. - */ - ioline_t sen; - /** - * @brief SI41XX SERIAL CLK Line. - */ - ioline_t sclk; - /** - * @brief SI41XX SERIAL DATA Line. - */ - ioline_t sdata; -#endif /* SI41XX_USE_SERIAL */ - /** - * @brief SI41XX Reference frequency. - */ - uint32_t ref_freq; -#if SI41XX_HAS_IF - /** - * @brief SI41XX IF Output Divider register value. - */ - uint8_t if_div; - /** - * @brief SI41XX IF N-Divider value. - */ - uint32_t if_n; - /** - * @brief SI41XX IF R-Divider value. - */ - uint32_t if_r; -#endif /* SI41XX_HAS_IF */ -#if SI41XX_HAS_RF1 - /** - * @brief SI41XX RF1 N-Divider value. - */ - uint32_t rf1_n; - /** - * @brief SI41XX RF1 R-Divider value. - */ - uint32_t rf1_r; -#endif /* SI41XX_HAS_RF1 */ -#if SI41XX_HAS_RF2 - /** - * @brief SI41XX RF2 N-Divider value. - */ - uint32_t rf2_n; - /** - * @brief SI41XX RF2 R-Divider value. - */ - uint32_t rf2_r; -#endif /* SI41XX_HAS_RF2 */ -} SI41XXConfig; - -/** - * @brief SI41XX Radio class. - */ -typedef struct SI41XXDriver { - /** - * @brief Driver state. - */ - si41xx_state_t state; - /** - * @brief Current configuration data. - */ - SI41XXConfig *config; -#if SI41XX_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* SI41XX_USE_MUTUAL_EXCLUSION */ - uint8_t pwr; -} SI41XXDriver; -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void si41xxObjectInit(SI41XXDriver *devp); -void si41xxStart(SI41XXDriver *devp, SI41XXConfig *config); -void si41xxStop(SI41XXDriver *devp); -void si41xxWriteRaw(SI41XXDriver *devp, uint8_t reg, uint32_t data); -#if SI41XX_HAS_IF -bool si41xxSetIF(SI41XXDriver *devp, uint32_t freq); -bool si41xxSetIFDiv(SI41XXDriver *devp, uint8_t div); -#endif -#if SI41XX_HAS_RF1 -bool si41xxSetRF1(SI41XXDriver *devp, uint32_t freq); -#endif -#if SI41XX_HAS_RF2 -bool si41xxSetRF2(SI41XXDriver *devp, uint32_t freq); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _SI41XX_H_ */ - -/** @} */ diff --git a/common/lfs_util.c b/common/lfs_util.c deleted file mode 100644 index ebddd989..00000000 --- a/common/lfs_util.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * lfs util functions - * - * Copyright (c) 2017, Arm Limited. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "lfs_util.h" - -// Software CRC implementation with small lookup table -uint32_t lfs_crc(uint32_t crc, const void *buffer, size_t size) { - static const uint32_t rtable[16] = { - 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, - 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, - 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, - 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c, - }; - - const uint8_t *data = buffer; - - for (size_t i = 0; i < size; i++) { - crc = (crc >> 4) ^ rtable[(crc ^ (data[i] >> 0)) & 0xf]; - crc = (crc >> 4) ^ rtable[(crc ^ (data[i] >> 4)) & 0xf]; - } - - return crc; -} diff --git a/common/max580x.c b/common/max580x.c deleted file mode 100644 index 73815885..00000000 --- a/common/max580x.c +++ /dev/null @@ -1,369 +0,0 @@ -/** - * @file max580x.c - * @brief MAX580X Digital to Analog Converter. - * - * @addtogroup MAX580X - * @ingrup ORESAT - * @{ - */ - -#include "hal.h" -#include "max580x.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -typedef union { - struct __attribute__((packed)) { - uint8_t reg; - union { - uint8_t data[2]; - uint16_t value; - }; - }; - uint8_t buf[3]; -} i2cbuf_t; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (MAX580X_USE_I2C) || defined(__DOXYGEN__) -/** - * @brief Reads registers value using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] reg first sub-register address - * @param[out] rxbuf pointer to an output buffer - * @param[in] n number of consecutive register to read - * @return the operation status. - * @notapi - */ -msg_t max580xI2CReadRegister(I2CDriver *i2cp, i2caddr_t sad, uint8_t reg, - uint8_t* rxbuf, size_t n) { - return i2cMasterTransmitTimeout(i2cp, sad, ®, 1, rxbuf, n, - TIME_INFINITE); -} - -/** - * @brief Writes a value into a register using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] txbuf buffer containing reg in first byte and high - * and low data bytes - * @param[in] n size of txbuf - * @return the operation status. - * @notapi - */ -msg_t max580xI2CWriteRegister(I2CDriver *i2cp, i2caddr_t sad, uint8_t *txbuf, - size_t n) { - return i2cMasterTransmitTimeout(i2cp, sad, txbuf, n, NULL, 0, - TIME_INFINITE); -} -#endif /* MAX580X_USE_I2C */ - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct MAX580XVMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. - * - * @param[out] devp pointer to the @p MAX580XDriver object - * - * @init - */ -void max580xObjectInit(MAX580XDriver *devp) { - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = MAX580X_STOP; -} - -/** - * @brief Configures and activates MAX580X Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * @param[in] config pointer to the @p MAX580XConfig object - * - * @api - */ -void max580xStart(MAX580XDriver *devp, const MAX580XConfig *config) { - i2cbuf_t buf; - - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == MAX580X_STOP) || - (devp->state == MAX580X_READY), - "max580xStart(), invalid state"); - - devp->config = config; - buf.value = 0; - - /* Configuring common registers.*/ -#if MAX580X_USE_I2C -#if MAX580X_SHARED_I2C - i2cAcquireBus(config->i2cp); -#endif /* MAX580X_SHARED_I2C */ - - i2cStart(config->i2cp, config->i2ccfg); - buf.reg = MAX580X_AD_SOFTWARE | MAX580X_SOFTWARE_RST; - max580xI2CWriteRegister(config->i2cp, config->saddr, - buf.buf, sizeof(i2cbuf_t)); - buf.reg = MAX580X_AD_REF | config->ref; - max580xI2CWriteRegister(config->i2cp, config->saddr, - buf.buf, sizeof(i2cbuf_t)); - buf.reg = MAX580X_AD_POWER; - buf.data[1] = config->power; - max580xI2CWriteRegister(config->i2cp, config->saddr, - buf.buf, sizeof(i2cbuf_t)); - buf.reg = MAX580X_AD_CONFIG; - buf.data[1] = config->aux; - max580xI2CWriteRegister(config->i2cp, config->saddr, - buf.buf, sizeof(i2cbuf_t)); - buf.reg = MAX580X_AD_DEFAULT; - buf.data[1] = config->default_cfg; - max580xI2CWriteRegister(config->i2cp, config->saddr, - buf.buf, sizeof(i2cbuf_t)); - max580xI2CReadRegister(config->i2cp, config->saddr, MAX580X_AD_NOP, buf.data, sizeof(buf.data)); - switch (buf.data[1]) { - case MAX5805: - devp->res = MAX5805_RES; - devp->range = 4096; - break; - case MAX5803: - devp->res = MAX5803_RES; - devp->range = 256; - break; - case MAX5804: - devp->res = MAX5804_RES; - devp->range = 1024; - break; - default: - devp->res = 0; - devp->range = 0; - break; - } - -#if MAX580X_SHARED_I2C - i2cReleaseBus(config->i2cp); -#endif /* MAX580X_SHARED_I2C */ -#endif /* MAX580X_USE_I2C */ - devp->state = MAX580X_READY; -} - -/** - * @brief Deactivates the MAX580X Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * - * @api - */ -void max580xStop(MAX580XDriver *devp) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == MAX580X_STOP) || (devp->state == MAX580X_READY), - "max580xStop(), invalid state"); - - if (devp->state == MAX580X_READY) { -#if MAX580X_USE_I2C -#if MAX580X_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX580X_SHARED_I2C */ - - /* Reset to input.*/ - buf.reg = MAX580X_AD_SOFTWARE | MAX580X_SOFTWARE_RST; - max580xI2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(i2cbuf_t)); - - i2cStop(devp->config->i2cp); -#if MAX580X_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX580X_SHARED_I2C */ -#endif /* MAX580X_USE_I2C */ - } - devp->state = MAX580X_STOP; -} - -/** - * @brief Reads MAX580X DAC Register as raw value. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * @param[in] reg the DAC register to read from - * - * @api - */ -uint16_t max580xReadRaw(MAX580XDriver *devp, max580x_reg_t reg) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == MAX580X_READY, - "max580xReadRaw(), invalid state"); - -#if MAX580X_USE_I2C -#if MAX580X_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX580X_SHARED_I2C */ - - buf.reg = reg; - max580xI2CReadRegister(devp->config->i2cp, devp->config->saddr, buf.reg, buf.data, sizeof(buf.data)); - -#if MAX580X_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX580X_SHARED_I2C */ -#endif /* MAX580X_USE_I2C */ - return MAX580X_DAC2VAL(buf.value, devp->res); -} - -/** - * @brief Writes MAX580X DAC Register as raw value. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * @param[in] reg the DAC register to write the value into - * @param[in] value the value to write to a DAC register - * - * @api - */ -void max580xWriteRaw(MAX580XDriver *devp, max580x_reg_t reg, uint16_t value) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == MAX580X_READY, - "max580xWriteRaw(), invalid state"); - -#if MAX580X_USE_I2C -#if MAX580X_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX580X_SHARED_I2C */ - - buf.reg = reg; - buf.value = MAX580X_VAL2DAC(value, devp->res); - max580xI2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX580X_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX580X_SHARED_I2C */ -#endif /* MAX580X_USE_I2C */ -} - -/** - * @brief Reads MAX580X DAC Register as a voltage. - * @details This only works when using an internal reference and assumes sufficient supply. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * @param[in] reg the DAC register to read from - * - * @api - */ -uint32_t max580xReadVoltage(MAX580XDriver *devp, max580x_reg_t reg) { - uint32_t voltage; - - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->config->ref != MAX580X_REF_EXT, - "max580xReadVoltage(), REF_EXT not allowed"); - - /* TODO: Clean this up, it's terrible */ - voltage = max580xReadRaw(devp, reg) * 10; - switch (devp->config->ref & 3U) { - case MAX580X_REF_2500: - voltage = voltage * 2500; - break; - case MAX580X_REF_2048: - voltage = voltage * 2048; - break; - case MAX580X_REF_4096: - voltage = voltage * 4096; - break; - } - voltage /= devp->range; - - return voltage; -} - -/** - * @brief Writes MAX580X DAC Register as a voltage. - * @details This only works when using an internal reference and assumes sufficient supply. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * @param[in] reg the DAC register to write the value into - * @param[in] voltage the voltage to write to a DAC register - * - * @api - */ -void max580xWriteVoltage(MAX580XDriver *devp, max580x_reg_t reg, uint32_t voltage) { - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->config->ref != MAX580X_REF_EXT, - "max580xWriteVoltage(), REF_EXT not allowed"); - - /* TODO: Clean this up, it's terrible */ - /* TODO: Bounds checking */ - voltage -= (voltage % 5); - voltage *= devp->range; - switch (devp->config->ref & 3U) { - case MAX580X_REF_2500: - voltage /= 25000; - break; - case MAX580X_REF_2048: - voltage /= 20480; - break; - case MAX580X_REF_4096: - voltage /= 40960; - break; - } - max580xWriteRaw(devp, reg, voltage); -} - -/** - * @brief Execute MAX580X LOAD instruction. - * - * @param[in] devp pointer to the @p MAX580XDriver object - * - * @api - */ -void max580xLoad(MAX580XDriver *devp) { - i2cbuf_t buf; - osalDbgCheck(devp != NULL); - osalDbgAssert(devp->state == MAX580X_READY, - "max580xReadRaw(), invalid state"); - -#if MAX580X_USE_I2C -#if MAX580X_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX580X_SHARED_I2C */ - - buf.reg = MAX580X_AD_LOAD; - buf.value = 0; - max580xI2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX580X_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX580X_SHARED_I2C */ -#endif /* MAX580X_USE_I2C */ -} - -/** @} */ diff --git a/common/max580x.mk b/common/max580x.mk deleted file mode 100644 index fe9e70a1..00000000 --- a/common/max580x.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the MAX580X device files. -MAX580XSRC := $(PROJ_SRC)/max580x.c - -# Required include directories -MAX580XINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(MAX580XSRC) -ALLINC += $(MAX580XINC) diff --git a/common/max7310.c b/common/max7310.c deleted file mode 100644 index 9b212c97..00000000 --- a/common/max7310.c +++ /dev/null @@ -1,368 +0,0 @@ -/** - * @file max7310.c - * @brief MAX7310 GPIO Expander code. - * - * @addtogroup MAX7310 - * @ingrup ORESAT - * @{ - */ - -#include "hal.h" -#include "max7310.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -typedef union { - struct __attribute__((packed)) { - uint8_t reg; - uint8_t data; - }; - uint8_t buf[2]; -} i2cbuf_t; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (MAX7310_USE_I2C) || defined(__DOXYGEN__) -/** - * @brief Reads registers value using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] reg first sub-register address - * @param[out] rxbuf pointer to an output buffer - * @param[in] n number of consecutive register to read - * @return the operation status. - * @notapi - */ -msg_t max7310I2CReadRegister(I2CDriver *i2cp, i2caddr_t sad, uint8_t reg, - uint8_t* rxbuf, size_t n) { - return i2cMasterTransmitTimeout(i2cp, sad, ®, 1, rxbuf, n, - TIME_MS2I(10)); -} - -/** - * @brief Writes a value into a register using I2C. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] txbuf buffer containing command in first byte and high - * and low data bytes - * @param[in] n size of txbuf - * @return the operation status. - * @notapi - */ -msg_t max7310I2CWriteRegister(I2CDriver *i2cp, i2caddr_t sad, uint8_t *txbuf, - size_t n) { - return i2cMasterTransmitTimeout(i2cp, sad, txbuf, n, NULL, 0, - TIME_MS2I(10)); -} -#endif /* MAX7310_USE_I2C */ - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct MAX7310VMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. - * - * @param[out] devp pointer to the @p MAX7310Driver object - * - * @init - */ -void max7310ObjectInit(MAX7310Driver *devp) { - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = MAX7310_STOP; -} - -/** - * @brief Configures and activates MAX7310 Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] config pointer to the @p MAX7310Config object - * - * @api - */ -void max7310Start(MAX7310Driver *devp, const MAX7310Config *config) { - i2cbuf_t buf; - osalDbgCheck((devp != NULL) && (config != NULL)); - - osalDbgAssert((devp->state == MAX7310_STOP) || - (devp->state == MAX7310_READY), - "max7310Start(), invalid state"); - - devp->config = config; - - /* Configuring common registers.*/ -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(config->i2cp); -#endif /* MAX7310_SHARED_I2C */ - - i2cStart(config->i2cp, config->i2ccfg); - buf.reg = MAX7310_AD_ODR; - buf.data = config->odr; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - buf.reg = MAX7310_AD_POL; - buf.data = config->pol; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - buf.reg = MAX7310_AD_MODE; - buf.data = config->iomode; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - buf.reg = MAX7310_AD_TIMEOUT; - buf.data = config->timeout; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ - devp->state = MAX7310_READY; -} - -/** - * @brief Deactivates the MAX7310 Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MAX7310Driver object - * - * @api - */ -void max7310Stop(MAX7310Driver *devp) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - - osalDbgAssert((devp->state == MAX7310_STOP) || (devp->state == MAX7310_READY), - "max7310Stop(), invalid state"); - - if (devp->state == MAX7310_READY) { -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - /* Reset to input.*/ - buf.reg = MAX7310_AD_MODE; - buf.data = 0xFF; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - - /* Reset output reg to 0.*/ - buf.reg = MAX7310_AD_ODR; - buf.data = 0; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - - /* Reset polarity.*/ - buf.reg = MAX7310_AD_POL; - buf.data = 0xF0; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - - /* Reset timeout.*/ - buf.reg = MAX7310_AD_TIMEOUT; - buf.data = MAX7310_TIMEOUT_ENABLED; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, - buf.buf, sizeof(buf)); - - i2cStop(devp->config->i2cp); -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ - } - devp->state = MAX7310_STOP; -} - -/** - * @brief Reads MAX7310 register as raw value. - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] reg the register to read - * - * @api - */ -uint8_t max7310ReadRaw(MAX7310Driver *devp, uint8_t reg) { - uint8_t value; - - osalDbgCheck(devp != NULL); - - osalDbgAssert(devp->state == MAX7310_READY, - "max7310ReadRaw(), invalid state"); - -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - max7310I2CReadRegister(devp->config->i2cp, devp->config->saddr, reg, &value, sizeof(value)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ - return value; -} - -/** - * @brief Writes MAX7310 register as raw value. - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] reg the register to write to - * @param[in] value the value to write - * - * @api - */ -void max7310WriteRaw(MAX7310Driver *devp, uint8_t reg, uint8_t value) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - - osalDbgAssert(devp->state == MAX7310_READY, - "max7310WriteRaw(), invalid state"); - -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - buf.reg = reg; - buf.data = value; - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ -} - -/** - * @brief Sets MAX7310 pin - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] pin pin to set - * - * @api - */ -void max7310SetPin(MAX7310Driver *devp, uint8_t pin) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - - osalDbgAssert(devp->state == MAX7310_READY, - "max7310SetPin(), invalid state"); - -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - buf.reg = MAX7310_AD_ODR; - max7310I2CReadRegister(devp->config->i2cp, devp->config->saddr, buf.reg, &buf.data, sizeof(buf.data)); - buf.data |= MAX7310_PIN_MASK(pin); - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ -} - -/** - * @brief Clear MAX7310 pin - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] pin pin to clear - * - * @api - */ -void max7310ClearPin(MAX7310Driver *devp, uint8_t pin) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - - osalDbgAssert(devp->state == MAX7310_READY, - "max7310SetPin(), invalid state"); - -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - buf.reg = MAX7310_AD_ODR; - max7310I2CReadRegister(devp->config->i2cp, devp->config->saddr, buf.reg, &buf.data, sizeof(buf.data)); - buf.data &= ~MAX7310_PIN_MASK(pin); - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ -} - -/** - * @brief Toggle MAX7310 pin - * - * @param[in] devp pointer to the @p MAX7310Driver object - * @param[in] pin pin to toggle - * - * @api - */ -void max7310TogglePin(MAX7310Driver *devp, uint8_t pin) { - i2cbuf_t buf; - - osalDbgCheck(devp != NULL); - - osalDbgAssert(devp->state == MAX7310_READY, - "max7310SetPin(), invalid state"); - -#if MAX7310_USE_I2C -#if MAX7310_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MAX7310_SHARED_I2C */ - - buf.reg = MAX7310_AD_ODR; - max7310I2CReadRegister(devp->config->i2cp, devp->config->saddr, buf.reg, &buf.data, sizeof(buf.data)); - buf.data ^= MAX7310_PIN_MASK(pin); - max7310I2CWriteRegister(devp->config->i2cp, devp->config->saddr, buf.buf, sizeof(buf)); - -#if MAX7310_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MAX7310_SHARED_I2C */ -#endif /* MAX7310_USE_I2C */ -} - -/** @} */ diff --git a/common/max7310.mk b/common/max7310.mk deleted file mode 100644 index d697f591..00000000 --- a/common/max7310.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the MAX7310 device files. -MAX7310SRC := $(PROJ_SRC)/max7310.c - -# Required include directories -MAX7310INC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(MAX7310SRC) -ALLINC += $(MAX7310INC) diff --git a/common/mmc5883ma.c b/common/mmc5883ma.c deleted file mode 100644 index d40dd06d..00000000 --- a/common/mmc5883ma.c +++ /dev/null @@ -1,353 +0,0 @@ -/** - * @file mmc5883ma.c - * @brief MMC5883MA Magnetometer - * - * @addtogroup MMC5883MA - * @ingrup ORESAT - * @{ - */ - -#include "ch.h" -#include "hal.h" -#include "mmc5883ma.h" -#include "string.h" -#include "chprintf.h" - - -#define DEBUG_SD (BaseSequentialStream*) &SD2 - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -//typedef union { -// struct __attribute__((packed)) { -// uint8_t reg; -// union { -// uint8_t data[2]; -// uint16_t value; -// }; -// }; -// uint8_t buf[3]; -//} i2cbuf_t; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -#define MMC5883MA_DEFAULT_I2C_TIMEOUT 50 - -#if (MMC5883MA_USE_I2C) || defined(__DOXYGEN__) - -bool mmc5883maI2CWriteRegister2(I2CDriver *i2cp, const uint8_t reg_number, const uint8_t value) { - uint8_t tx[2]; - tx[0] = reg_number; - tx[1] = value; - - if( i2cMasterTransmitTimeout(i2cp, MMC5883MA_I2C_ADDRESS_WRITE, tx, 2, NULL, 0, MMC5883MA_DEFAULT_I2C_TIMEOUT) == MSG_OK ) { - return(true); - } - return(false); -} - -bool mmc5883maI2CReadRegister2(I2CDriver *i2cp, const uint8_t reg_number, uint8_t *dest_value) { - uint8_t tx[2]; - tx[0] = reg_number; - tx[1] = 0; - uint8_t rx[2]; - rx[0] = 0; - rx[1] = 0; - - if( i2cMasterTransmitTimeout(i2cp, (i2caddr_t) MMC5883MA_I2C_ADDRESS_READ, tx, 1, rx, 1, MMC5883MA_DEFAULT_I2C_TIMEOUT) == MSG_OK ) { - *dest_value = rx[0]; - return(true); - } - return(false); -} - - -bool mmc5883maI2CReadRegister3(I2CDriver *i2cp, const uint8_t i2c_address, const uint8_t reg_number, uint8_t *dest_value) { - uint8_t tx[2]; - tx[0] = reg_number; - tx[1] = 0; - uint8_t rx[2]; - rx[0] = 0; - rx[1] = 0; - - if( i2cMasterTransmitTimeout(i2cp, (i2caddr_t) i2c_address, tx, 1, rx, 1, MMC5883MA_DEFAULT_I2C_TIMEOUT) == MSG_OK ) { - *dest_value = rx[0]; - return(true); - } - return(false); -} - -bool mmc5883maI2CReadRegister4(I2CDriver *i2cp, const uint8_t i2c_address, const uint8_t reg_number, uint16_t *dest_value) { - uint8_t tx[2]; - tx[0] = reg_number; - tx[1] = 0; - uint8_t rx[2]; - rx[0] = 0; - rx[1] = 0; - - if( i2cMasterTransmitTimeout(i2cp, (i2caddr_t) i2c_address, tx, 1, rx, 2, MMC5883MA_DEFAULT_I2C_TIMEOUT) == MSG_OK ) { - *dest_value = rx[0] | rx[1]; - return(true); - } - return(false); -} - -#endif /* MMC5883MA_USE_I2C */ - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct MMC5883MAVMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - - -bool mmc5883maReadData(MMC5883MADriver *devp, mmc5883ma_data_t *dest) { - osalDbgCheck((devp != NULL)); -// osalDbgAssert((devp->state != MMC5883MA_READY), -// "mmc5883maStart(), invalid state"); - - if( devp->state != MMC5883MA_READY ) { - return(false); - } - - - devp->read_call_count++; - - - - bool ret = false; - - /* Configuring common registers.*/ -#if MMC5883MA_USE_I2C -#if MMC5883MA_SHARED_I2C - i2cAcquireBus(config->i2cp); -#endif /* MMC5883MA_SHARED_I2C */ - - - uint8_t rx[10]; - memset(rx, 0, sizeof(rx)); - - uint8_t reg = MMC5883MA_AD_XOUT_LOW; - - i2cStart(devp->config->i2cp, devp->config->i2ccfg); - msg_t r = i2cMasterTransmitTimeout(devp->config->i2cp, MMC5883MA_I2C_ADDRESS_READ, ®, 1, rx, 6, MMC5883MA_DEFAULT_I2C_TIMEOUT); - i2cStop(devp->config->i2cp); - - dest->mx = (rx[0] << 8) | rx[1]; - dest->my = (rx[2] << 8) | rx[3]; - dest->mz = (rx[4] << 8) | rx[5]; - - if( r == MSG_OK ) { - ret = true; - - if( devp->read_call_count > 20 ) { - //This will periodically clear any bias on the magnetometer - devp->read_call_count = 0; - - i2cStart(devp->config->i2cp, devp->config->i2ccfg); - if( ! mmc5883maI2CWriteRegister2(devp->config->i2cp, MMC5883MA_AD_INTRNLCTRL0, MMC5883MA_INTRNLCTRL0_SET)) { - - } - i2cStop(devp->config->i2cp); - chThdSleepMilliseconds(1); - - - memset(rx, 0, sizeof(rx)); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); - msg_t r = i2cMasterTransmitTimeout(devp->config->i2cp, MMC5883MA_I2C_ADDRESS_READ, ®, 1, rx, 6, MMC5883MA_DEFAULT_I2C_TIMEOUT); - i2cStop(devp->config->i2cp); - - mmc5883ma_data_t dest_temp; - dest_temp.mx = (rx[0] << 8) | rx[1]; - dest_temp.my = (rx[2] << 8) | rx[3]; - dest_temp.mz = (rx[4] << 8) | rx[5]; - - - const int32_t delta_set_reset_x = dest_temp.mx - dest->mx; - const int32_t delta_set_reset_y = dest_temp.my - dest->my; - const int32_t delta_set_reset_z = dest_temp.mz - dest->mz; - - const float bridge_offset_midpoint_x = ((float) delta_set_reset_x) / 2.0; - const float bridge_offset_midpoint_y = ((float) delta_set_reset_y) / 2.0; - const float bridge_offset_midpoint_z = ((float) delta_set_reset_z) / 2.0; - - //Modify tracked bridge offset estimate, but filter the data slightly. - const float filter_coefficient = 4.0; - devp->bridge_offset_estimate_x = devp->bridge_offset_estimate_x + ((bridge_offset_midpoint_x - devp->bridge_offset_estimate_x) / filter_coefficient); - devp->bridge_offset_estimate_y = devp->bridge_offset_estimate_y + ((bridge_offset_midpoint_y - devp->bridge_offset_estimate_y) / filter_coefficient); - devp->bridge_offset_estimate_z = devp->bridge_offset_estimate_z + ((bridge_offset_midpoint_z - devp->bridge_offset_estimate_z) / filter_coefficient); - - i2cStart(devp->config->i2cp, devp->config->i2ccfg); - if( ! mmc5883maI2CWriteRegister2(devp->config->i2cp, MMC5883MA_AD_INTRNLCTRL0, MMC5883MA_INTRNLCTRL0_RST)) { - - } - i2cStop(devp->config->i2cp); - chThdSleepMilliseconds(1); - } - - dest->mx += devp->bridge_offset_estimate_x; - dest->my += devp->bridge_offset_estimate_y; - dest->mz += devp->bridge_offset_estimate_z; - } - -#if MMC5883MA_SHARED_I2C - i2cReleaseBus(config->i2cp); -#endif /* MMC5883MA_SHARED_I2C */ -#endif /* MMC5883MA_USE_I2C */ - - return(ret); -} - -/** - * @brief Initializes an instance. - * - * @param[out] devp pointer to the @p MMC5883MADriver object - * - * @init - */ -void mmc5883maObjectInit(MMC5883MADriver *devp) { - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = MMC5883MA_STOP; - - devp->bridge_offset_estimate_x = 0; - devp->bridge_offset_estimate_y = 0; - devp->bridge_offset_estimate_z = 0; - devp->read_call_count = 0; -} - -bool mmc5883maSoftReset(MMC5883MADriver *devp) { - chprintf(DEBUG_SD, "Resetting MMC5883...\r\n"); - bool r = mmc5883maI2CWriteRegister2(devp->config->i2cp, MMC5883MA_AD_INTRNLCTRL1, MMC5883MA_INTRNLCTRL1_SW_RST_CMD); - chThdSleepMilliseconds(5); - return(r); -} - -/** - * @brief Configures and activates MMC5883MA Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MMC5883MADriver object - * @param[in] config pointer to the @p MMC5883MAConfig object - * - * @api - */ -uint8_t mmc5883ma_product_id_readback; - -bool mmc5883maStart(MMC5883MADriver *devp, const MMC5883MAConfig *config) { - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == MMC5883MA_STOP) || - (devp->state == MMC5883MA_READY), - "mmc5883maStart(), invalid state"); - - devp->config = config; - - /* Configuring common registers.*/ -#if MMC5883MA_USE_I2C -#if MMC5883MA_SHARED_I2C - i2cAcquireBus(config->i2cp); -#endif /* MMC5883MA_SHARED_I2C */ - - i2cStart(config->i2cp, config->i2ccfg); - - devp->state = MMC5883MA_READY; - - - bool found_mmc5883ma_flag = false; - - //Probe I2C bus to see what's attached - if( ! mmc5883maI2CReadRegister3(devp->config->i2cp, MMC5883MA_I2C_ADDRESS_READ, MMC5883MA_AD_PRDCT_ID_1, &mmc5883ma_product_id_readback) ) { - chprintf(DEBUG_SD, "Failed to read product code from MMC5883MA chip, i2c comm failure\r\n"); - } else { - if( mmc5883ma_product_id_readback == MMC5883MA_EXPECTED_PRODUCT_CODE ) { - chprintf(DEBUG_SD, "Successfully read product code from MMC5883MA (good), 0x%X\r\n", mmc5883ma_product_id_readback); - found_mmc5883ma_flag = true; - } else { - chprintf(DEBUG_SD, "ERROR: unexpected product ID code from MMC5883MA, read 0x%X, expected 0x%X\r\n", mmc5883ma_product_id_readback, MMC5883MA_EXPECTED_PRODUCT_CODE); - } - } - - if( found_mmc5883ma_flag ) { - mmc5883maSoftReset(devp); - - if( ! mmc5883maI2CReadRegister2(devp->config->i2cp, MMC5883MA_AD_PRDCT_ID_1, &mmc5883ma_product_id_readback) ) { - devp->state = MMC5883MA_STOP; - } else { - chprintf(DEBUG_SD, "Read MMC5883MA product code as 0x%X, expected 0x%X\r\n", mmc5883ma_product_id_readback, MMC5883MA_EXPECTED_PRODUCT_CODE); - if( mmc5883ma_product_id_readback != MMC5883MA_EXPECTED_PRODUCT_CODE ) { - chprintf(DEBUG_SD, "ERROR: Read incorrect MMC5883MA product code!!!\r\n"); - devp->state = MMC5883MA_STOP; - } - } - - if( devp->state == MMC5883MA_READY ) { - if( ! mmc5883maI2CWriteRegister2(devp->config->i2cp, MMC5883MA_AD_INTRNLCTRL2, MMC5883MA_INTRNLCTRL2_CM_FREQ_1_Hz)) { - devp->state = MMC5883MA_STOP; - } - } - } else { - devp->state = MMC5883MA_STOP; - } - - i2cStop(devp->config->i2cp); - -#if MMC5883MA_SHARED_I2C - i2cReleaseBus(config->i2cp); -#endif /* MMC5883MA_SHARED_I2C */ -#endif /* MMC5883MA_USE_I2C */ - - - return(devp->state == MMC5883MA_READY); -} - -/** - * @brief Deactivates the MMC5883MA Complex Driver peripheral. - * - * @param[in] devp pointer to the @p MMC5883MADriver object - * - * @api - */ -void mmc5883maStop(MMC5883MADriver *devp) { - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == MMC5883MA_STOP) || (devp->state == MMC5883MA_READY), - "mmc5883maStop(), invalid state"); - - if (devp->state == MMC5883MA_READY) { -#if MMC5883MA_USE_I2C -#if MMC5883MA_SHARED_I2C - i2cAcquireBus(devp->config->i2cp); - i2cStart(devp->config->i2cp, devp->config->i2ccfg); -#endif /* MMC5883MA_SHARED_I2C */ - - //The MMC will be in low power mode after being reset - mmc5883maSoftReset(devp); - - i2cStop(devp->config->i2cp); -#if MMC5883MA_SHARED_I2C - i2cReleaseBus(devp->config->i2cp); -#endif /* MMC5883MA_SHARED_I2C */ -#endif /* MMC5883MA_USE_I2C */ - } - devp->state = MMC5883MA_STOP; -} - - - -/** @} */ diff --git a/common/mmc5883ma.mk b/common/mmc5883ma.mk deleted file mode 100644 index 42ad92c7..00000000 --- a/common/mmc5883ma.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the MMC5883MA device files. -MMC5883MASRC := $(PROJ_SRC)/mmc5883ma.c - -# Required include directories -MMC5883MAINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(MMC5883MASRC) -ALLINC += $(MMC5883MAINC) diff --git a/common/morse.c b/common/morse.c deleted file mode 100644 index 7a7b2721..00000000 --- a/common/morse.c +++ /dev/null @@ -1,169 +0,0 @@ -#include "morse.h" -#include "ax5043.h" - -/** - * @brief Morse code for alphabets and numbers. - */ -static const char *alpha[] = { - ".-", //A - "-...", //B - "-.-.", //C - "-..", //D - ".", //E - "..-.", //F - "--.", //G - "....", //H - "..", //I - ".---", //J - "-.-", //K - ".-..", //L - "--", //M - "-.", //N - "---", //O - ".--.", //P - "--.-", //Q - ".-.", //R - "...", //S - "-", //T - "..-", //U - "...-", //V - ".--", //W - "-..-", //X - "-.--", //Y - "--..", //Z -}; - -static const char *num[] = { - "-----", //0 - ".----", //1 - "..---", //2 - "...--", //3 - "....-", //4 - ".....", //5 - "-....", //6 - "--...", //7 - "---..", //8 - "----.", //9 -}; - -/** - * @brief Prepare for CW mode - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - */ -uint8_t ax5043_prepare_cw(AX5043Driver *devp){ - ax5043WriteU24(devp, AX5043_REG_FSKDEV, 0x000000U); - ax5043WriteU24(devp, AX5043_REG_TXRATE, 0x000001U); - - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_FULL); - - /* This is not mentioned in datasheet or programming manual but is required. - * Removing this will make the transmission to transmit in low power for a few seconds - * before it reaches peak power */ - /* FIFO reset */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, AX5043_FIFOCMD_CLEAR_FIFODAT); - ax5043WriteU8(devp, AX5043_REG_FIFODATA, (AX5043_CHUNKCMD_REPEATDATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 3))); - /* Preamble flag */ - ax5043WriteU8(devp, AX5043_REG_FIFODATA, AX5043_CHUNK_DATATX_UNENC | AX5043_CHUNK_DATATX_NOCRC); - ax5043WriteU8(devp, AX5043_REG_FIFODATA, 0xFF); - /* Preamble */ - ax5043WriteU8(devp, AX5043_REG_FIFODATA, 0x55); - /* FIFO Commit */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, 0x04); - - ax5043SetPWRMode(devp, AX5043_PWRMODE_STANDBY); - devp->state = AX5043_CW; - return 0; -} - -/** - * @brief Send Morse dot and dash over the air - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] dot_dash_time time in milliseconds for transmiter to be on. - */ -void ax5043_morse_dot_dash(AX5043Driver *devp, uint16_t dot_dash_time){ - ax5043SetPWRMode(devp, AX5043_PWRMODE_TX_FULL); - ax5043WriteU8(devp, AX5043_REG_FIFODATA, (AX5043_CHUNKCMD_REPEATDATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 3))); - /* Preamble flag */ - ax5043WriteU8(devp, AX5043_REG_FIFODATA, AX5043_CHUNK_DATATX_UNENC | AX5043_CHUNK_DATATX_NOCRC); - ax5043WriteU8(devp, AX5043_REG_FIFODATA, 0xFF); - /* Preamble */ - ax5043WriteU8(devp, AX5043_REG_FIFODATA, 0x00); - /* FIFO Commit */ - ax5043WriteU8(devp, AX5043_REG_FIFOSTAT, 0x04); - chThdSleepMilliseconds(dot_dash_time); - ax5043SetPWRMode(devp, AX5043_PWRMODE_STANDBY); - -} - -/** - * @brief Convert an alphabet or number to morse dot and dash - * - * @param[in] letter An alphabet or number. - * - * @return Length of packet received. - */ -const char *ax5043_ascii_to_morse(char letter){ - letter = tolower(letter); - - if (isalpha(letter)){ - return alpha[letter-'a']; - } - else if (isdigit(letter)){ - return num[letter-'0']; - } - - return " "; -} - -/** - * @brief Convert a message to morse code and transmit it. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] wpm words per minute. - * @param[in] beaconMessage Message to be transmitted. - * @param[in] pktlen Length of packet/beacon message. - */ -void ax5043_send_cw(AX5043Driver *devp, int wpm, char beaconMessage[], uint16_t pktlen ){ - int element; - int index = 0; - const char *morse; - - uint16_t ditLength = 1200/wpm; - uint16_t letter_space = ditLength*3; - uint16_t word_space = ditLength*7; - uint16_t element_space = ditLength; - uint16_t dash = ditLength*3; - - while (index < pktlen){ - morse = ax5043_ascii_to_morse(beaconMessage[index]); - - element = 0; - while (morse[element] != '\0'){ - switch(morse[element]){ - case '-': - ax5043_morse_dot_dash(devp, dash); - break; - case '.': - ax5043_morse_dot_dash(devp, ditLength); - break; - } - - if (morse[element] == ' '){ - chThdSleepMilliseconds(word_space); - } - else if (morse[element+1] != '\0'){ - chThdSleepMilliseconds(element_space); - } - else if (morse[element+1] == '\0'){ - chThdSleepMilliseconds(letter_space); - } - element++; - } - - index++; - } -} diff --git a/common/node_mgr.c b/common/node_mgr.c deleted file mode 100644 index 6cbac29a..00000000 --- a/common/node_mgr.c +++ /dev/null @@ -1,133 +0,0 @@ -#include "node_mgr.h" -#include "opd.h" - -#define MGR_EVENT_WAKEUP EVENT_MASK(0) -#define MGR_EVENT_TERMINATE EVENT_MASK(1) -#define MGR_EVENT_CHANGE EVENT_MASK(2) -#define MGR_EVENT_ONLINE EVENT_MASK(3) -#define MGR_EVENT_OFFLINE EVENT_MASK(4) -#define MGR_EVENT_BOOT EVENT_MASK(5) - -typedef struct oresat_node_state { - const oresat_node_t *desc; - CO_NMT_internalState_t state; - uint8_t attempts; - bool enable; -} node_state_t; - -/* TODO: Don't use extern, switch to some system config/object struct */ -extern CO_t *CO; - -node_state_t node_state[OD_CNT_HB_CONS]; -EVENTSOURCE_DECL(mgr_change_event); - -void node_change_cb(uint8_t nodeId, uint8_t idx, CO_NMT_internalState_t state, void *object) -{ - (void)nodeId; - node_state_t *node = object; - syssts_t sts; - sts = chSysGetStatusAndLockX(); - node->state = state; - chEvtBroadcastFlagsI(&mgr_change_event, idx); - chSysRestoreStatusX(sts); -} - -THD_WORKING_AREA(node_mgr_wa, 0x400); -THD_FUNCTION(node_mgr, arg) -{ - const oresat_node_t *node = arg; - event_listener_t mgr_change_el; - eventmask_t event; - eventflags_t idx; - - opd_init(); - opd_start(); - - for (int i = 0; node[i].id != 0; i++) { - OD_IO_t hbcons_io; - uint32_t hbcons_entry = node[i].id << 16 | node[i].timeout; - OD_size_t count; - OD_getSub(OD_ENTRY_H1016_consumerHeartbeatTime, i + 1, &hbcons_io, false); - hbcons_io.write(&hbcons_io.stream, &hbcons_entry, sizeof(hbcons_entry), &count); - node_state[i].desc = &node[i]; - node_state[i].attempts = 0; - if (node[i].opd_addr == 0x00 || node[i].autostart) - node_enable(node[i].id, true); - } - - chEvtRegisterMaskWithFlags(&mgr_change_event, &mgr_change_el, MGR_EVENT_CHANGE, ALL_EVENTS); - - while (!chThdShouldTerminateX()) { - event = chEvtWaitAnyTimeout(MGR_EVENT_WAKEUP | MGR_EVENT_TERMINATE | MGR_EVENT_CHANGE, TIME_INFINITE); - if (event & MGR_EVENT_TERMINATE) - continue; - if (event & MGR_EVENT_CHANGE) { - idx = chEvtGetAndClearFlags(&mgr_change_el); - node_state_t *node = &node_state[idx]; - switch (node->state) { - case CO_NMT_UNKNOWN: - if (node->desc->opd_addr && node->enable) { - if (node->attempts < 3) { - node_enable(node->desc->id, false); - chThdSleepMilliseconds(500); - node_enable(node->desc->id, true); - node->attempts++; - } else { - node_enable(node->desc->id, false); - } - } - break; - case CO_NMT_INITIALIZING: - break; - case CO_NMT_PRE_OPERATIONAL: - case CO_NMT_OPERATIONAL: - node->attempts = 0; - break; - case CO_NMT_STOPPED: - break; - default: - break; - } - } - } - - chEvtUnregister(&mgr_change_event, &mgr_change_el); - for (int i = 0; node[i].id != 0; i++) { - node_enable(node[i].id, false); - OD_IO_t hbcons_io; - uint32_t hbcons_entry = 0; - OD_size_t count; - OD_getSub(OD_ENTRY_H1016_consumerHeartbeatTime, i + 1, &hbcons_io, false); - hbcons_io.write(&hbcons_io.stream, &hbcons_entry, sizeof(hbcons_entry), &count); - } - opd_stop(); -} - -int node_enable(uint8_t id, bool enable) -{ - int8_t idx = CO_HBconsumer_getIdxByNodeId(CO->HBcons, id); - if (idx < 0) - return -1; - node_state_t *node = &node_state[idx]; - node->enable = enable; - if (enable) { - CO_HBconsumer_initCallbackNmtChanged(CO->HBcons, idx, node, node_change_cb); - } else { - CO_HBconsumer_initCallbackNmtChanged(CO->HBcons, idx, NULL, NULL); - } - if (node->desc->opd_addr) { - return opd_enable(node->desc->opd_addr, enable); - } - return 0; -} - -int node_status(uint8_t id, CO_NMT_internalState_t *state) -{ - int8_t idx = CO_HBconsumer_getIdxByNodeId(CO->HBcons, id); - if (idx < 0) - return -1; - node_state_t *node = &node_state[idx]; - if (state) - *state = node->state; - return node->enable; -} diff --git a/common/node_mgr.mk b/common/node_mgr.mk deleted file mode 100644 index e1183d2a..00000000 --- a/common/node_mgr.mk +++ /dev/null @@ -1,12 +0,0 @@ -# Required libraries for node manager -include $(PROJ_SRC)/opd.mk - -# List of all the node manager files. -NODEMGRSRC := $(PROJ_SRC)/node_mgr.c - -# Required include directories -NODEMGRINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(NODEMGRSRC) -ALLINC += $(NODEMGRINC) diff --git a/common/opd.c b/common/opd.c deleted file mode 100644 index bd0bb753..00000000 --- a/common/opd.c +++ /dev/null @@ -1,312 +0,0 @@ -#include "hal.h" -#include "max7310.h" -#include "opd.h" - -#define OPD_RESET_TIME 250 -#define OPD_I2C_TRIES 3 - -static struct { - MAX7310Driver dev; - MAX7310Config config; - bool valid; -} opd_dev[OPD_MAX_ADDR + 1]; - -static const I2CConfig i2cconfig = { - OPMODE_I2C, - 100000, - STD_DUTY_CYCLE, -}; - -static MAX7310Config defconfig = { - &I2CD1, - &i2cconfig, - 0x00, - OPD_ODR_VAL, - OPD_POL_VAL, - OPD_MODE_VAL, - MAX7310_TIMEOUT_ENABLED -}; - -/** - * OPD Control Functions - */ - -void opd_init(void) -{ - for (i2caddr_t i = MAX7310_MIN_ADDR; i <= MAX7310_MAX_ADDR; i++) { - max7310ObjectInit(&opd_dev[i].dev); - opd_dev[i].config = defconfig; - opd_dev[i].config.saddr = i; - opd_dev[i].valid = false; - } -} - -void opd_start(void) -{ -#ifdef LINE_OPD_ENABLE - /* Enable the subsystem if the device has a control line */ - palClearLine(LINE_OPD_ENABLE); - chThdSleepMilliseconds(600); -#endif /* LINE_OPD_ENABLE */ - - /* Start the I2C driver */ - i2cStart(&I2CD1, &i2cconfig); - /* Probe all devices on the bus */ - opd_scan(true); -} - -void opd_stop(void) -{ - /* Forcefully disable all devices */ - for (i2caddr_t i = MAX7310_MIN_ADDR; i <= MAX7310_MAX_ADDR; i++) { - max7310Stop(&opd_dev[i].dev); - opd_dev[i].valid = false; - } - /* Stop the I2C driver */ - i2cStop(&I2CD1); -#ifdef LINE_OPD_ENABLE - /* Disable the subsystem if the device has a control line */ - palSetLine(LINE_OPD_ENABLE); -#endif /* LINE_OPD_ENABLE */ -} - -void opd_scan(bool restart) -{ - for (i2caddr_t i = MAX7310_MIN_ADDR; i <= MAX7310_MAX_ADDR; i++) { - opd_probe(i, restart); - } -} - -bool opd_probe(i2caddr_t addr, bool restart) -{ - msg_t result; - uint8_t temp; - - /* Probe the device */ - i2cAcquireBus(&I2CD1); - i2cStart(&I2CD1, &i2cconfig); - result = i2cMasterReceiveTimeout(&I2CD1, addr, &temp, 1, TIME_MS2I(10)); - i2cReleaseBus(&I2CD1); - if (result == MSG_OK) { - /* If a device responded, set as valid and (re)start if needed */ - if (opd_dev[addr].valid != true || restart) { - max7310Stop(&opd_dev[addr].dev); - max7310Start(&opd_dev[addr].dev, &opd_dev[addr].config); - } - opd_dev[addr].valid = true; - } else { - /* If no response, ensure address is stopped and set as invalid */ - max7310Stop(&opd_dev[addr].dev); - opd_dev[addr].valid = false; - } - - /* Return the result of the probe */ - return opd_dev[addr].valid; -} - -int opd_enable(i2caddr_t addr, bool enable) -{ - /* Ensure device is valid */ - if (opd_dev[addr].valid != true) { - return -1; - } - - if (enable) { - max7310SetPin(&opd_dev[addr].dev, OPD_EN); - } else { - max7310ClearPin(&opd_dev[addr].dev, OPD_EN); - } - - return 0; -} - -int opd_reset(i2caddr_t addr) -{ - /* Ensure device is valid */ - if (opd_dev[addr].valid != true) { - return -1; - } - - max7310SetPin(&opd_dev[addr].dev, OPD_CB_RESET); - chThdSleepMilliseconds(OPD_RESET_TIME); - max7310ClearPin(&opd_dev[addr].dev, OPD_CB_RESET); - return 0; -} - -int opd_status(i2caddr_t addr, opd_status_t *status) -{ - /* Ensure device is valid */ - if (opd_dev[addr].valid != true) { - return -1; - } - - status->input = max7310ReadRaw(&opd_dev[addr].dev, MAX7310_AD_INPUT); - status->odr = max7310ReadRaw(&opd_dev[addr].dev, MAX7310_AD_ODR); - status->pol = max7310ReadRaw(&opd_dev[addr].dev, MAX7310_AD_POL); - status->mode = max7310ReadRaw(&opd_dev[addr].dev, MAX7310_AD_MODE); - status->timeout = max7310ReadRaw(&opd_dev[addr].dev, MAX7310_AD_TIMEOUT); - return 0; -} - -/** - * I2C over OPD support functions - */ -void opd_i2c_start(MAX7310Driver *devp) -{ - uint8_t reg; - - reg = max7310ReadRaw(devp, MAX7310_AD_MODE); - reg &= ~MAX7310_PIN_MASK(OPD_SDA); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - reg &= ~MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); -} - -void opd_i2c_stop(MAX7310Driver *devp) -{ - uint8_t reg; - - reg = max7310ReadRaw(devp, MAX7310_AD_MODE); - reg &= ~(MAX7310_PIN_MASK(OPD_SCL) | MAX7310_PIN_MASK(OPD_SDA)); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - reg |= MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - reg |= MAX7310_PIN_MASK(OPD_SDA); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); -} - -void opd_i2c_transmit(i2caddr_t addr, uint8_t *txbuf, size_t txsize, uint8_t *rxbuf, size_t rxsize) -{ - MAX7310Driver *devp; - uint8_t tries; - uint8_t reg; - - if (opd_dev[addr].valid != true) - return; - - devp = &opd_dev[addr].dev; - - /* Assert start condition on I2C */ - opd_i2c_start(devp); - - /* Transmit all bytes */ - for (size_t i = 0; i < txsize; i++) { - uint8_t byte = txbuf[i]; - - /* Transmit 8 bits per byte */ - for (int j = 0; j < 8; j++) { - reg = max7310ReadRaw(devp, MAX7310_AD_MODE); - - /* Set SDA based on MSB of byte */ - reg = (reg & ~MAX7310_PIN_MASK(OPD_SDA)) | ((byte & 0x80) ? MAX7310_PIN_MASK(OPD_SDA) : 0); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - - /* Cycle SCL */ - reg |= MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - reg &= ~MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - - /* Shift next bit into MSB */ - byte <<= 1; - } - - /* Wait for ACK after all bits sent */ - tries = OPD_I2C_TRIES; - reg |= MAX7310_PIN_MASK(OPD_SDA); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - reg |= MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - while (!(max7310ReadRaw(devp, MAX7310_AD_INPUT) & MAX7310_PIN_MASK(OPD_SCL))); - while ((max7310ReadRaw(devp, MAX7310_AD_INPUT) & MAX7310_PIN_MASK(OPD_SDA)) && tries) - tries--; - reg &= ~(MAX7310_PIN_MASK(OPD_SCL) | MAX7310_PIN_MASK(OPD_SDA)); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - if (tries == 0) - goto opd_i2c_fail; - } - - for (size_t i = 0; i < rxsize; i++) { - uint8_t byte = 0; - - reg |= MAX7310_PIN_MASK(OPD_SDA); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - for (int j = 0; j < 8; j++) { - /* Cycle SCL while reading pin */ - reg |= MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - byte = ((byte << 1) | (max7310ReadRaw(devp, MAX7310_AD_INPUT) & MAX7310_PIN_MASK(OPD_SDA) ? 1 : 0)); - reg &= ~MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - } - - if (i < rxsize - 1) { - reg &= ~MAX7310_PIN_MASK(OPD_SDA); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - } - reg |= MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - while (!(max7310ReadRaw(devp, MAX7310_AD_INPUT) & MAX7310_PIN_MASK(OPD_SCL))); - reg &= ~MAX7310_PIN_MASK(OPD_SCL); - max7310WriteRaw(devp, MAX7310_AD_MODE, reg); - - rxbuf[i] = byte; - } - -opd_i2c_fail: - opd_i2c_stop(devp); - return; -} - -int opd_boot(i2caddr_t addr) -{ - MAX7310Driver *devp; - uint8_t txbuf[10]; - uint8_t rxbuf[10]; - int retval; - - if (opd_dev[addr].valid != true) - return -1; - devp = &opd_dev[addr].dev; - - max7310ClearPin(devp, OPD_EN); - max7310SetPin(devp, OPD_BOOT0); - max7310SetPin(devp, OPD_EN); - chThdSleepMilliseconds(2); - - txbuf[0] = 0x82U; - txbuf[1] = 0x01U; - txbuf[2] = 0xFEU; - opd_i2c_transmit(addr, txbuf, 3, NULL, 0); - - txbuf[0] = 0x83U; - opd_i2c_transmit(addr, txbuf, 1, rxbuf, 1); - if (rxbuf[0] != 0x79) - return rxbuf[0]; - - opd_i2c_transmit(addr, txbuf, 1, rxbuf, 1); - retval = rxbuf[0]; - - opd_i2c_transmit(addr, txbuf, 1, rxbuf, 1); - if (rxbuf[0] != 0x79) - return rxbuf[0]; - - max7310ClearPin(devp, OPD_BOOT0); - - return retval; -} - -int opd_linux_recover(i2caddr_t addr, bool enable) -{ - if (opd_dev[addr].valid != true) { - return -1; - } - - if (enable) { - max7310ClearPin(&opd_dev[addr].dev, OPD_LINUX_BOOT); - } else { - max7310SetPin(&opd_dev[addr].dev, OPD_LINUX_BOOT); - } - return 0; - -} diff --git a/common/opd.mk b/common/opd.mk deleted file mode 100644 index 315de7b2..00000000 --- a/common/opd.mk +++ /dev/null @@ -1,12 +0,0 @@ -# Required libraries for OPD -include $(PROJ_SRC)/max7310.mk - -# List of all the OPD device files. -OPDSRC := $(PROJ_SRC)/opd.c - -# Required include directories -OPDINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(OPDSRC) -ALLINC += $(OPDINC) diff --git a/common/radio.c b/common/radio.c deleted file mode 100644 index c490c864..00000000 --- a/common/radio.c +++ /dev/null @@ -1,121 +0,0 @@ -/** - * @file radio.c - * @brief OreSat radio support library. - * - * @addtogroup RADIO - * @{ - */ -#include -#include "ch.h" -#include "hal.h" -#include "radio.h" - -/*===========================================================================*/ -/* Local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Local variables and types. */ -/*===========================================================================*/ - -/* Frame buffer allocation pool */ -objects_fifo_t rx_fifo; -static msg_t rx_fifo_msgs[RADIO_FIFO_COUNT]; -static fb_t rx_fifo_buf[RADIO_FIFO_COUNT]; -objects_fifo_t tx_fifo; -static msg_t tx_fifo_msgs[RADIO_FIFO_COUNT]; -static fb_t tx_fifo_buf[RADIO_FIFO_COUNT]; - -/*===========================================================================*/ -/* Local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Interface implementation. */ -/*===========================================================================*/ - -fb_t *__fb_alloc(size_t len, void *arg) { - (void)len; - osalDbgCheck(arg != NULL); - objects_fifo_t *fifo = arg; - fb_t *fb = chFifoTakeObjectTimeout(fifo, TIME_INFINITE); - memset(fb, 0, sizeof(fb_t)); - return fb; -} - -void __fb_free(fb_t *fb, void *arg) { - osalDbgCheck(fb != NULL && arg != NULL); - objects_fifo_t *fifo = arg; - chFifoReturnObject(fifo, fb); -} - -/*===========================================================================*/ -/* Exported functions. */ -/*===========================================================================*/ - -void radio_init(void) -{ - /* Initialize frame buffer FIFO */ - chFifoObjectInit(&rx_fifo, sizeof(fb_t), RADIO_FIFO_COUNT, rx_fifo_buf, rx_fifo_msgs); - chFifoObjectInit(&tx_fifo, sizeof(fb_t), RADIO_FIFO_COUNT, tx_fifo_buf, tx_fifo_msgs); - - /* Initialize radio systems */ - for (int i = 0; radio_devices[i].devp != NULL; i++) { - ax5043ObjectInit(radio_devices[i].devp); - } - for (int i = 0; synth_devices[i].devp != NULL; i++) { - si41xxObjectInit(synth_devices[i].devp); - } -} - -void radio_start(void) -{ - /* Start radio systems */ - for (int i = 0; radio_devices[i].devp != NULL; i++) { - ax5043Start(radio_devices[i].devp, radio_devices[i].cfgp); - } - for (int i = 0; synth_devices[i].devp != NULL; i++) { - si41xxStart(synth_devices[i].devp, synth_devices[i].cfgp); - } -} - -void radio_stop(void) -{ - for (int i = 0; radio_devices[i].devp != NULL; i++) { - ax5043Stop(radio_devices[i].devp); - } - for (int i = 0; synth_devices[i].devp != NULL; i++) { - si41xxStop(synth_devices[i].devp); - } -} - -void pdu_send(fb_t *fb, void *arg) -{ - osalDbgCheck(fb != NULL && arg != NULL); - objects_fifo_t *fifo = arg; - chFifoSendObject(fifo, fb); -} - -void pdu_send_ahead(fb_t *fb, void *arg) -{ - osalDbgCheck(fb != NULL && arg != NULL); - objects_fifo_t *fifo = arg; - chFifoSendObjectAhead(fifo, fb); -} - -fb_t *pdu_recv(void *arg) -{ - osalDbgCheck(arg != NULL); - fb_t *fb; - objects_fifo_t *fifo = arg; - if (chFifoReceiveObjectTimeout(fifo, (void**)&fb, TIME_MS2I(1000)) != MSG_OK) { - fb = NULL; - } - return fb; -} - -/** @} */ diff --git a/common/radio.mk b/common/radio.mk deleted file mode 100644 index bacf1d45..00000000 --- a/common/radio.mk +++ /dev/null @@ -1,17 +0,0 @@ -CCSDS_ROOT = $(PROJ_ROOT)/ext/OpenCCSDS - -# Required libraries for RADIO -include $(CCSDS_ROOT)/ccsds.mk -include $(PROJ_SRC)/si41xx.mk -include $(PROJ_SRC)/ax5043.mk -include $(PROJ_SRC)/aprs.mk - -# List of all the RADIO device files. -RADIOSRC := $(PROJ_SRC)/radio.c \ - -# Required include directories -RADIOINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(RADIOSRC) $(CCSDS_SRC) -ALLINC += $(RADIOINC) $(CCSDS_INC) diff --git a/common/rtc.c b/common/rtc.c deleted file mode 100644 index 58a93a5d..00000000 --- a/common/rtc.c +++ /dev/null @@ -1,291 +0,0 @@ -#include "rtc.h" - -/** - * @brief Convert @p RTCDateTime to Unix time. - * - * @param[in] timespec Pointer to a @p RTCDateTime structure - * @param[out] msec Pointer to milliseconds value or @p NULL - * - * @return Unix time - * @api - */ -time_t rtcConvertDateTimeToUnix(const RTCDateTime *timespec, uint32_t *msec) -{ - osalDbgCheck(timespec != NULL); - struct tm tim; - - rtcConvertDateTimeToStructTm(timespec, &tim, msec); - return mktime(&tim); -} - -/** - * @brief Convert Unix time to @p RTCDateTime. - * - * @param[out] timespec Pointer to a @p RTCDateTime structure - * @param[in] unix_time Unix time value - * @param[in] msec Milliseconds value - * - * @api - */ -void rtcConvertUnixToDateTime(RTCDateTime *timespec, time_t unix_time, uint32_t msec) -{ - osalDbgCheck(timespec != NULL); - struct tm tim; - struct tm *canary; - - canary = gmtime_r(&unix_time, &tim); - osalDbgCheck(&tim == canary); - - rtcConvertStructTmToDateTime(&tim, msec, timespec); - return; -} - -/** - * @brief Get time as struct tm - * - * @param[out] tim Pointer to struct tm to fill - * @param[out] msec Pointer to millisecond variable - * - * @api - */ -void rtcGetTimeTm(struct tm *tim, uint32_t *msec) -{ - osalDbgCheck(tim != NULL); - RTCDateTime timespec; - - rtcGetTime(&RTCD1, ×pec); - rtcConvertDateTimeToStructTm(×pec, tim, msec); -} - -/** - * @brief Set time from struct tm - * - * @param[in] tim Pointer to struct tm to use - * @param[in] msec Milliseconds value - * - * @api - */ -void rtcSetTimeTm(const struct tm *tim, uint32_t msec) -{ - osalDbgCheck(tim != NULL); - RTCDateTime timespec; - - rtcConvertStructTmToDateTime(tim, msec, ×pec); - rtcSetTime(&RTCD1, ×pec); -} - -/** - * @brief Get time as Unix time_t - * - * @param[out] msec Pointer to millisecond variable - * - * @return Current time as time_t - * @api - */ -time_t rtcGetTimeUnix(uint32_t *msec) -{ - struct tm tim; - - rtcGetTimeTm(&tim, msec); - - return mktime(&tim); -} - -/** - * @brief Set time from Unix time_t - * - * @param[in] unix_time Unix time to set RTC to - * @param[in] msec Milliseconds value - * - * @api - */ -void rtcSetTimeUnix(time_t unix_time, uint32_t msec) -{ - struct tm tim; - struct tm *canary; - - canary = gmtime_r(&unix_time, &tim); - osalDbgCheck(&tim == canary); - - rtcSetTimeTm(&tim, msec); -} - -/** - * @brief Get time as CCSDS SCET object - * - * @param[out] scet Pointer to SCET struct - * - * @api - */ -void rtcGetTimeSCET(time_scet_t *scet) -{ - osalDbgCheck(scet != NULL); - uint32_t fine; - scet->coarse = rtcGetTimeUnix(&fine); - scet->fine = fine & 0xFFFFFFU; -} - -/** - * @brief Set time from CCSDS SCET object - * - * @param[in] scet Pointer to SCET struct - * - * @api - */ -void rtcSetTimeSCET(const time_scet_t *scet) -{ - osalDbgCheck(scet != NULL); - rtcSetTimeUnix(scet->coarse, scet->fine); -} - -/** - * @brief Get time as CCSDS UTC object - * - * @param[out] scet Pointer to UTC struct - * - * @api - */ -void rtcGetTimeUTC(time_utc_t *utc) -{ - osalDbgCheck(utc != NULL); - RTCDateTime timespec; - struct tm tim; - - rtcGetTime(&RTCD1, ×pec); - rtcConvertDateTimeToStructTm(×pec, &tim, NULL); - mktime(&tim); - - utc->day = (tim.tm_year - 70) * 365 + tim.tm_yday; - utc->ms = timespec.millisecond; - utc->us = 0; -} - -/** - * @brief Set time from CCSDS UTC object - * - * @param[in] scet Pointer to UTC struct - * - * @api - */ -void rtcSetTimeUTC(const time_utc_t *utc) -{ - osalDbgCheck(utc != NULL); - /* TODO: Implement */ - (void)utc; -} - -/** - * @brief Converts time from timespec to ALRMxR register encoding - * - * @param[in] timespec Pointer to a @p RTCDateTime structure - * @param[in] flags Configuration flags - * - * @return The ALRMxR register encoding. - * @api - */ -uint32_t rtcEncodeAlarm(const RTCDateTime *timespec, uint32_t flags) -{ - osalDbgCheck(timespec != NULL); - uint32_t n, alrmr = 0; - - /* Subseconds cannot be set.*/ - n = timespec->millisecond / 1000; - - /* Seconds conversion.*/ - if ((flags & RTC_SEC_MASK) == 0) { - alrmr |= ((n % 10) << RTC_ALRMAR_SU_Pos); - n /= 10; - alrmr |= ((n % 6) << RTC_ALRMAR_ST_Pos); - n /= 6; - } - - /* Minutes conversion.*/ - if ((flags & RTC_MIN_MASK) == 0) { - alrmr |= ((n % 10) << RTC_ALRMAR_MNU_Pos); - n /= 10; - alrmr |= ((n % 6) << RTC_ALRMAR_MNT_Pos); - n /= 6; - } - - /* Hours conversion.*/ - if ((flags & RTC_HOUR_MASK) == 0) { - alrmr |= ((n % 10) << RTC_ALRMAR_HU_Pos); - n /= 10; - alrmr |= (n << RTC_ALRMAR_HT_Pos); - } - - /* Days conversion.*/ - if ((flags & RTC_DATE_MASK) == 0) { - if (flags & RTC_WEEKDAY_SEL) { - n = timespec->dayofweek; - alrmr |= (n << RTC_ALRMAR_DU_Pos); - } else { - n = timespec->day; - alrmr |= ((n % 10) << RTC_ALRMAR_DU_Pos); - n /= 10; - alrmr |= ((n % 10) << RTC_ALRMAR_DT_Pos); - } - } - - /* Set flags */ - alrmr |= flags; - - return alrmr; -} - -/** - * @brief Generates ALRMxR register value for time relative to timespec - * - * @param[in] timespec Pointer to a @p RTCDateTime structure - * @param[in] days Days to elapse - * @param[in] hours Hours to elapse - * @param[in] minutes Minutes to elapse - * @param[in] seconds Seconds to elapse - * - * @return The ALRMxR register encoding. - * @api - */ -uint32_t rtcEncodeRelAlarm(const RTCDateTime *timespec, int days, int hours, int minutes, int seconds) -{ - RTCDateTime alarm_timespec; - struct tm tim; - - /* Get current time */ - rtcConvertDateTimeToStructTm(timespec, &tim, NULL); - /* Add offsets for desired elapsed time */ - tim.tm_yday += days; - tim.tm_hour += hours; - tim.tm_min += minutes; - tim.tm_sec += seconds; - /* Recalculate struct tm and convert to timespec */ - mktime(&tim); - rtcConvertStructTmToDateTime(&tim, 0, &alarm_timespec); - /* Return the encoded alarm value */ - return rtcEncodeAlarm(&alarm_timespec, 0); -} - -/* TODO: Move these out of RTC probably */ -/* TODO: Re-implement these using new OD interface */ -/* -CO_SDO_abortCode_t OD_SCET_Func(CO_ODF_arg_t *ODF_arg) -{ - if (ODF_arg->reading) { - rtcGetTimeSCET((time_scet_t*)ODF_arg->data); - } else { - rtcSetTimeSCET((time_scet_t*)ODF_arg->data); - } - - return CO_SDO_AB_NONE; -} - -CO_SDO_abortCode_t OD_UTC_Func(CO_ODF_arg_t *ODF_arg) -{ - if (ODF_arg->reading) { - rtcGetTimeUTC((time_utc_t*)ODF_arg->data); - } else { - rtcSetTimeUTC((time_utc_t*)ODF_arg->data); - } - - return CO_SDO_AB_NONE; -} -*/ diff --git a/common/rtc.mk b/common/rtc.mk deleted file mode 100644 index 9a983b8f..00000000 --- a/common/rtc.mk +++ /dev/null @@ -1,12 +0,0 @@ -# Required libraries for RTC and time management -#include $(PROJ_SRC)/library.mk - -# List of all the time subsystem source files -RTCSRC := $(PROJ_SRC)/rtc.c - -# Required include directories -RTCINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(RTCSRC) -ALLINC += $(RTCINC) diff --git a/common/si41xx.c b/common/si41xx.c deleted file mode 100644 index 48080d53..00000000 --- a/common/si41xx.c +++ /dev/null @@ -1,482 +0,0 @@ -/** - * @file si41xx.c - * @brief SI41XX Radio. - * - * @addtogroup SI41XX - * @ingrup ORESAT - * @{ - */ - -#include "hal.h" -#include "si41xx.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @name SI41XX SERIAL Word fields - * @{ - */ -#define SI41XX_ADDRESS_Pos (0U) -#define SI41XX_ADDRESS_Msk (0xFU << SI41XX_ADDRESS_Pos) -#define SI41XX_ADDRESS SI41XX_ADDRESS_Msk -#define SI41XX_DATA_Pos (4U) -#define SI41XX_DATA_Msk (0x3FFFFU << SI41XX_DATA_Pos) -#define SI41XX_DATA SI41XX_DATA_Msk -#define SI41XX_MSB_Pos (21U) -#define SI41XX_MSB_Msk (0x1U << SI41XX_MSB_Pos) -#define SI41XX_MSB SI41XX_MSB_Msk -#define SI41XX_WORD_Pos (0U) -#define SI41XX_WORD_Msk (0x3FFFFFU << SI41XX_WORD_Pos) -#define SI41XX_WORD SI41XX_WORD_Msk -/** @} */ - -/** - * @name Maximum phase detector frequency - * @{ - */ -#define SI41XX_MAX_PHASEDET (1000000U) -#define SI41XX_MIN_PHASEDET (10000U) -/** @} */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (SI41XX_USE_SERIAL) || defined(__DOXYGEN__) -/** - * @brief Writes to an SI41xx device using its serial interface. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] addr Register address - * @param[in] data Data to write to register - * - * @notapi - */ -void si41xxWriteRegister(SI41XXDriver *devp, uint8_t addr, uint32_t data) { - uint32_t i = 22; - uint32_t word = _VAL2FLD(SI41XX_ADDRESS, addr) - | _VAL2FLD(SI41XX_DATA, data); - - osalDbgCheck((devp != NULL) && (devp->config != NULL)); - - palClearLine(devp->config->sen); - - while (i--) { - palClearLine(devp->config->sclk); - - palWriteLine(devp->config->sdata, (word & SI41XX_MSB ? PAL_HIGH : PAL_LOW)); - palSetLine(devp->config->sclk); - word <<= 1; - } - - palClearLine(devp->config->sclk); - palSetLine(devp->config->sen); - palSetLine(devp->config->sclk); -} - -#if (SI41XX_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the SI41XX bus. - * @details This function tries to gain ownership to the SI41XX bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option @p SI41XX_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * - * @notapi - */ -void si41xxAcquireBus(SI41XXDriver *devp) { - osalDbgCheck(devp != NULL); - - osalMutexLock(&devp->mutex); -} - -/** - * @brief Releases exclusive access to the SI41XX bus. - * @pre In order to use this function the option @p SI41XX_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * - * @notapi - */ -void si41xxReleaseBus(SI41XXDriver *devp) { - osalDbgCheck(devp != NULL); - - osalMutexUnlock(&devp->mutex); -} -#endif /* SI41XX_USE_MUTUAL_EXCLUSION */ -#endif /* SI41XX_USE_SERIAL */ - -/** - * @brief Calculates N-Div and R-Div values. - * @details This function calculates N and R division values needed to provided - * the specified frequency from the reference frequency defined in the - * device configuration. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] freq Desired output frequency - * @param[out] ndiv Calculated N-Divider value - * @param[out] rdiv Calculated R-Divider value - * - * @return Successfully found values within phase detector frequency bounds - * @notapi - */ -bool si41xxCalcDiv(SI41XXDriver *devp, uint32_t freq, uint32_t *ndiv, uint32_t *rdiv) { - osalDbgCheck(devp != NULL && devp->config != NULL && ndiv != NULL && rdiv != NULL); - osalDbgAssert(devp->config->ref_freq != 0 && freq != 0, - "si41xxCalcDiv(), non-zero values required"); - - uint32_t ref_freq = devp->config->ref_freq; - uint32_t phasedet = ref_freq, gcd = freq; - - /* Find GCD of both frequencies */ - while (phasedet != gcd) { - if (phasedet > gcd) { - phasedet -= gcd; - } else { - gcd -= phasedet; - } - } - - /* Divide until frequency is less than the maximum */ - while (phasedet >= SI41XX_MAX_PHASEDET) { - phasedet /= 2; - } - if (phasedet < SI41XX_MIN_PHASEDET) { - return false; - } - - /* Calculate needed N and R values */ - *ndiv = freq / phasedet; - *rdiv = ref_freq / phasedet; - return true; -} - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. - * - * @param[out] devp Pointer to the @p SI41XXDriver object - * - * @init - */ -void si41xxObjectInit(SI41XXDriver *devp) { - devp->config = NULL; - -#if SI41XX_USE_MUTUAL_EXCLUSION - osalMutexObjectInit(&devp->mutex); -#endif - - devp->state = SI41XX_STOP; -} - -/** - * @brief Configures and activates SI41XX Driver peripheral. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] config Pointer to the @p SI41XXConfig object - * - * @api - */ -void si41xxStart(SI41XXDriver *devp, SI41XXConfig *config) { - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == SI41XX_STOP) || (devp->state == SI41XX_READY), - "si41xxStart(), invalid state"); - - devp->config = config; - devp->pwr = 0; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - si41xxWriteRegister(devp, SI41XX_REG_CONFIG, SI41XX_CONFIG_AUTOKP | - _VAL2FLD(SI41XX_CONFIG_AUXSEL, SI41XX_AUXSEL_LOCKDET) | - _VAL2FLD(SI41XX_CONFIG_IFDIV, config->if_div)); - si41xxWriteRegister(devp, SI41XX_REG_PHASE_GAIN, 0x00000U); - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); -#if SI41XX_HAS_IF - devp->pwr |= SI41XX_POWERDOWN_PBIB; - si41xxWriteRegister(devp, SI41XX_REG_IF_NDIV, _VAL2FLD(SI41XX_IF_NDIV, devp->config->if_n)); - si41xxWriteRegister(devp, SI41XX_REG_IF_RDIV, _VAL2FLD(SI41XX_IF_RDIV, devp->config->if_r)); -#endif -#if SI41XX_HAS_RF1 - devp->pwr |= SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_RF1_NDIV, _VAL2FLD(SI41XX_RF1_NDIV, devp->config->rf1_n)); - si41xxWriteRegister(devp, SI41XX_REG_RF1_RDIV, _VAL2FLD(SI41XX_RF1_RDIV, devp->config->rf1_r)); -#endif -#if SI41XX_HAS_RF2 - devp->pwr |= SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_RF2_NDIV, _VAL2FLD(SI41XX_RF2_NDIV, devp->config->rf2_n)); - si41xxWriteRegister(devp, SI41XX_REG_RF2_RDIV, _VAL2FLD(SI41XX_RF2_RDIV, devp->config->rf2_r)); -#endif - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - devp->state = SI41XX_READY; -} - -/** - * @brief Deactivates the SI41XX Complex Driver peripheral. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * - * @api - */ -void si41xxStop(SI41XXDriver *devp) { - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_STOP) || (devp->state == SI41XX_READY), - "si41xxStop(), invalid state"); - - devp->pwr = 0U; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - si41xxWriteRegister(devp, SI41XX_REG_CONFIG, 0x00000U); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - devp->state = SI41XX_STOP; -} - -/** - * @brief Writes a raw value to an SI41XX register. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] reg The register to write to - * @param[in] value The value to write - * - * @api - */ -void si41xxWriteRaw(SI41XXDriver *devp, uint8_t reg, uint32_t value) { - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_STOP) || (devp->state == SI41XX_READY), - "si41xxWriteRaw(), invalid state"); - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - si41xxWriteRegister(devp, reg, value); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ -} - -#if (SI41XX_HAS_IF) || defined(__DOXYGEN__) -/** - * @brief Sets IF N and R values to provide the desired frequency. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] freq The desired frequency - * - * @return Successfully set frequency - * @api - */ -bool si41xxSetIF(SI41XXDriver *devp, uint32_t freq) { - uint32_t n, r; - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_READY), - "si41xxSetIF(), invalid state"); - - /* Calculate N and R values */ - if (!si41xxCalcDiv(devp, freq << devp->config->if_div, &n, &r)) { - return false; - } - - /* Check that values are within bounds of programmable values */ - if (n >= (SI41XX_IF_NDIV + 1) || r >= (SI41XX_IF_RDIV + 1)) { - return false; - } - devp->config->if_n = n; - devp->config->if_r = r; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - devp->pwr &= ~SI41XX_POWERDOWN_PBIB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - si41xxWriteRegister(devp, SI41XX_REG_IF_NDIV, _VAL2FLD(SI41XX_IF_NDIV, n)); - si41xxWriteRegister(devp, SI41XX_REG_IF_RDIV, _VAL2FLD(SI41XX_IF_RDIV, r)); - devp->pwr |= SI41XX_POWERDOWN_PBIB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - return true; -} - -/** - * @brief Sets IF divider value. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] div The divisor value (1,2,4,8) - * - * @return Successfully set divisor - * @api - */ -bool si41xxSetIFDiv(SI41XXDriver *devp, uint8_t div) { - uint8_t i; - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_READY), - "si41xxSetIFDiv(), invalid state"); - - /* Check that values are within bounds of programmable values */ - if (!((div != 0) && ((div & (div - 1)) == 0))) { - /* Not a power of 2 */ - return false; - } - for (i = 0; i < 4 && (div & 0xEU); i++, div >>= 1); - if (i == 4) { - return false; - } - devp->config->if_div = i; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - si41xxWriteRegister(devp, SI41XX_REG_CONFIG, _VAL2FLD(SI41XX_CONFIG_IFDIV, i)); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - return true; -} -#endif /* SI41XX_HAS_IF */ - -#if (SI41XX_HAS_RF1) || defined(__DOXYGEN__) -/** - * @brief Sets RF1 dividers to provide the desired frequency. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] freq The desired frequency - * - * @return Successfully set frequency - * @api - */ -bool si41xxSetRF1(SI41XXDriver *devp, uint32_t freq) { - uint32_t n, r; - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_READY), - "si41xxSetRF1(), invalid state"); - - /* Calculate N and R values */ - if (!si41xxCalcDiv(devp, freq, &n, &r)) { - return false; - } - - /* Check that values are within bounds of programmable values */ - if (n >= (SI41XX_RF1_NDIV + 1) || r >= (SI41XX_RF1_RDIV + 1)) { - return false; - } - devp->config->rf1_n = n; - devp->config->rf1_r = r; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - devp->pwr &= ~SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - si41xxWriteRegister(devp, SI41XX_REG_RF1_NDIV, _VAL2FLD(SI41XX_RF1_NDIV, n)); - si41xxWriteRegister(devp, SI41XX_REG_RF1_RDIV, _VAL2FLD(SI41XX_RF1_RDIV, r)); - devp->pwr |= SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - return true; -} -#endif /* SI41XX_HAS_RF1 */ - -#if (SI41XX_HAS_RF2) || defined(__DOXYGEN__) -/** - * @brief Sets RF2 dividers to provide the desired frequency. - * - * @param[in] devp Pointer to the @p SI41XXDriver object - * @param[in] freq The desired frequency - * - * @return Successfully set frequency - * @api - */ -bool si41xxSetRF2(SI41XXDriver *devp, uint32_t freq) { - uint32_t n, r; - osalDbgCheck(devp != NULL); - osalDbgAssert((devp->state == SI41XX_READY), - "si41xxSetRF2(), invalid state"); - - /* Calculate N and R values */ - if (!si41xxCalcDiv(devp, freq, &n, &r)) { - return false; - } - - /* Check that values are within bounds of programmable values */ - if (n >= (SI41XX_RF2_NDIV + 1) || r >= (SI41XX_RF2_RDIV + 1)) { - return false; - } - devp->config->rf2_n = n; - devp->config->rf2_r = r; - -#if SI41XX_USE_SERIAL -#if SI41XX_SHARED_SERIAL - si41xxAcquireBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ - - devp->pwr &= ~SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - si41xxWriteRegister(devp, SI41XX_REG_RF2_NDIV, _VAL2FLD(SI41XX_RF2_NDIV, n)); - si41xxWriteRegister(devp, SI41XX_REG_RF2_RDIV, _VAL2FLD(SI41XX_RF2_RDIV, r)); - devp->pwr |= SI41XX_POWERDOWN_PBRB; - si41xxWriteRegister(devp, SI41XX_REG_PWRDOWN, devp->pwr); - -#if SI41XX_SHARED_SERIAL - si41xxReleaseBus(devp); -#endif /* SI41XX_SHARED_SERIAL */ -#endif /* SI41XX_USE_SERIAL */ - return true; -} -#endif /* SI41XX_HAS_RF2 */ - -/** @} */ diff --git a/common/si41xx.mk b/common/si41xx.mk deleted file mode 100644 index 5d42eba0..00000000 --- a/common/si41xx.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the SI41XX device files. -SI41XXSRC := $(PROJ_SRC)/si41xx.c - -# Required include directories -SI41XXINC := $(PROJ_SRC)/include - -# Shared variables -ALLCSRC += $(SI41XXSRC) -ALLINC += $(SI41XXINC) diff --git a/ext/OpenCCSDS b/ext/OpenCCSDS deleted file mode 160000 index 87cae72e..00000000 --- a/ext/OpenCCSDS +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 87cae72ec21cc553bdd19666fdf55cace6b95c4b diff --git a/ext/littlefs b/ext/littlefs deleted file mode 160000 index 1863dc78..00000000 --- a/ext/littlefs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 1863dc7883d82bd6ca79faa164b65341064d1c16 diff --git a/ld/STM32F439xI.ld b/ld/STM32F439xI.ld deleted file mode 100644 index 6cbb2a16..00000000 --- a/ld/STM32F439xI.ld +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F429xI memory setup. - * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash0 (rx) : org = 0x08000000, len = 1M - flash1 (rx) : org = 0x08100000, len = 1M - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ - ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 (wx) : org = 0x20020000, len = 64k /* SRAM3 */ - ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash0); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash0); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash0); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash0); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Generic rules inclusion.*/ -INCLUDE rules.ld diff --git a/ld/STM32F446xE.ld b/ld/STM32F446xE.ld deleted file mode 100644 index de7d56ce..00000000 --- a/ld/STM32F446xE.ld +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * ST32F446xE memory setup. - * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash0 (rx) : org = 0x08000000, len = 512k - flash1 (rx) : org = 0x00000000, len = 0 - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ - ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 (wx) : org = 0x00000000, len = 16k /* SRAM2 */ - ram3 (wx) : org = 0x00000000, len = 0 - ram4 (wx) : org = 0x00000000, len = 0 - ram5 (wx) : org = 0x00000000, len = 0 - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash0); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash0); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash0); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash0); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Generic rules inclusion.*/ -INCLUDE rules.ld diff --git a/ld/STM32L452xE.ld b/ld/STM32L452xE.ld deleted file mode 100644 index e97963bd..00000000 --- a/ld/STM32L452xE.ld +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L452xE memory setup. - */ -MEMORY -{ - flash0 (rx) : org = 0x08000000, len = 256k - flash1 (rx) : org = 0x08040000, len = 256k - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 128k - ram1 (wx) : org = 0x00000000, len = 0 - ram2 (wx) : org = 0x00000000, len = 0 - ram3 (wx) : org = 0x00000000, len = 0 - ram4 (wx) : org = 0x10000000, len = 32k /* This memory also mapped at address 0x20020000 */ - ram5 (wx) : org = 0x00000000, len = 0 - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash0); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash0); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash0); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash0); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Generic rules inclusion.*/ -INCLUDE rules.ld diff --git a/profiles/oresat_battery.xpd b/profiles/oresat_battery.xpd deleted file mode 100644 index 7a354c53..00000000 --- a/profiles/oresat_battery.xpd +++ /dev/null @@ -1,318 +0,0 @@ - - - - - - - CANopen device profile - 1.1 - - - Device - - 1 - 1 - CANopen - - - - - Portland State Aerospace Society - 0 - OreSat Battery - 0 - - OreSat Battery Application Object Dictionary - - 0 - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CANopen communication network profile - 1.1 - - - CommunicationNetwork - - 1 - 1 - CANopen - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/profiles/oresat_node.xpd b/profiles/oresat_node.xpd deleted file mode 100644 index 45144c32..00000000 --- a/profiles/oresat_node.xpd +++ /dev/null @@ -1,6537 +0,0 @@ - - - - - - - CANopen device profile - 1.1 - - - Device - - 1 - 1 - CANopen - - - - - Portland State Aerospace Society - 0 - OreSat Node - 0 - - OreSat Node Default Profile - - 0 - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * bit 16-31: Additional information -* bit 0-15: Device profile number - - - - - - - * bit 7: manufacturer specific -* bit 6: Reserved (always 0) -* bit 5: device profile specific -* bit 4: communication error (overrun, error state) -* bit 3: temperature -* bit 2: voltage -* bit 1: current -* bit 0: generic error - - - - - - - - - - - * Sub Index 0: Contains number of actual errors. 0 can be written to clear error history. -* sub-index 1 and above: - * bit 16-31: Manufacturer specific additional information - * bit 0-15: Error code as transmited in the Emergency object - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * bit 31: set to 0 -* bit 30: If set, CANopen device generates SYNC object -* bit 11-29: set to 0 -* bit 0-10: 11-bit CAN-ID - - - - - - - Period of SYNC transmission in µs (0 = transmission disabled). - - - - - - - Synchronous window leghth in µs (0 = not used). All synchronous PDOs must be transmitted within this time window. - - - - - - - - - - - - - - - - - - - - - - - - Sub-indexes 1 and above: -* Reading provides information about its storage functionality: - * bit 1: If set, CANopen device saves parameters autonomously - * bit 0: If set, CANopen device saves parameters on command -* Writing value 0x65766173 ('s','a','v','e' from LSB to MSB) stores corresponding data. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Sub-indexes 1 and above: -* Reading provides information about its restoring capability: - * bit 0: If set, CANopen device restores parameters -* Writing value 0x64616F6C ('l','o','a','d' from LSB to MSB) restores corresponding data. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * bit 31: If set, EMCY does NOT exist / is NOT valid -* bit 11-30: set to 0 -* bit 0-10: 11-bit CAN-ID - - - - - - - Inhibit time of emergency message in multiples of 100µs. The value 0 disables the inhibit time. - - - - - - Consumer Heartbeat Time: - * bit 24-31: set to 0 - * bit 16-23: Node ID of the monitored node. If 0 or greater than 127, sub-entry is not used. - * bit 0-15: Heartbeat time in ms (if 0, sub-intry is not used). Value should be higher than the corresponding producer heartbeat time. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Heartbeat producer time in ms (0 = disable transmission). - - - - - - - * Vendor-ID, assigned by CiA -* Product code, manufacturer specific -* Revision number: - * bit 16-31: Major revision number (CANopen behavior has changed) - * bit 0-15: Minor revision num. (CANopen behavior has not changed) -* Serial number, manufacturer specific - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Value 0: SYNC message is transmitted with data length 0. -* Value 1: reserved. -* Value 2-240: SYNC message has one data byte, which contains the counter. -* Value 241-255: reserved. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Emergency consumer 1 to 127: -* bit 31: If set, EMCY consumer does NOT exist / is NOT valid -* bit 11-30: set to 0 -* bit 0-10: 11-bit CAN-ID - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - If error is detected and operating NMT state is NMT operational, this object defines behavior of the device. - -Value definition for all subindexes: - 0x00 - if operational, switch to NMT pre-operational - 0x01 - do nothing - 0x02 - switch to NMT stopped - -01 - Communication error - bus off or Heartbeat consumer error. -02 - Communication other error (critical errors - see 'Error status bits') except CAN bus passive but including bus off or Heartbeat consumer. -03 - Communication passive - any communication error including CAN bus passive. -04 - Generic error (critical errors - see 'Error status bits'). -05 - Device profile error - bit 5 in error register is set. -06 - Manufacturer specific error - bit 7 in error register is set. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Sub-indexes 1 and 2: - * bit 31: If set, SDO does NOT exist / is NOT valid - * bit 30: If set, value is assigned dynamically - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Node-ID of the SDO client, 0x01 to 0x7F - - - - - - - - - - - - - - - - - - - - - - - - - - * Sub-indexes 1 and 2: - * bit 31: If set, SDO does NOT exist / is NOT valid - * bit 30: If set, value is assigned dynamically - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Node-ID of the SDO client, 0x01 to 0x7F - - - - - - - - - - - - - - - - - - - - - - - - - - - * Sub-indexes 1 and 2: - * bit 31: If set, SDO does NOT exist / is NOT valid - * bit 30: If set, value is assigned dynamically - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Node-ID of the SDO server, 0x01 to 0x7F - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 11-30: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0-240: synchronous, processed after next reception of SYNC object - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Event timer in ms (0 = disabled) for deadline monitoring. - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * COB-ID used by RPDO: - * bit 31: If set, PDO does not exist / is not valid - * bit 30: If set, NO RTR is allowed on this PDO - * bit 11-29: set to 0 - * bit 0-10: 11-bit CAN-ID -* Transmission type: - * Value 0: synchronous (acyclic) - * Value 1-240: synchronous (cyclic every (1-240)-th sync) - * Value 241-253: not used - * Value 254: event-driven (manufacturer-specific) - * Value 255: event-driven (device profile and application profile specific) -* Inhibit time in multiple of 100µs, if the transmission type is set to 254 or 255 (0 = disabled). -* Event timer interval in ms, if the transmission type is set to 254 or 255 (0 = disabled). -* SYNC start value - * Value 0: Counter of the SYNC message shall not be processed. - * Value 1-240: The SYNC message with the counter value equal to this value shall be regarded as the first received SYNC message. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * Number of mapped application objects in PDO: - * Value 0: mapping is disabled. - * Value 1: sub-index 0x01 is valid. - * Value 2-8: sub-indexes 0x01 to (0x02 to 0x08) are valid. -* Application object 1-8: - * bit 16-31: index - * bit 8-15: sub-index - * bit 0-7: data length in bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This object configures the start-up behavior of a device that is able to perform the NMT. - - - - - - CAN Bus redundancy management as defined in ECSS-E-ST-50-15C - - - - - - - - - - Bdefault specifies the bus to be considered active after a node power-on, node hardware reset. - - - - - Ttoggle specifies the number of Consumer Heartbeat times during which the node is required to be listeningfor an NMT HB message on a particular bus before switching to the other bus. - - - - - Ntoggle specifies the number of toggles between the Nominal and Redundant bus in case of no HB message being detected. If an even number is used the last toggle puts the system into Bdefault. - - - - - The counter of Ntoggles (bus toggles) shows the count of the number of toggles that have already been performed by the device. - - - - - CCSDS Unsegmented Time Code (CUC) object for Spacecraft Elapsed Time (SCET) get/set methods - - - - - CCSDS Day Segmented Time Code (CDS) object for UTC time get/set methods - - - - - Unique Device ID of MCU - - - - - - - - - - - - - - - - - - - - - - - - Calibration values as read from the MCU - - - - - - - - - Temperature Sensor Calibration 1 - - - - - Temperature Sensor Calibration 2 - - - - - Interal VREF calibration value - - - - - Common MCU sensors between all boards. This provides the calculated values based on calibration data as well as the raw values read from the sensors directly. - - - - - - - - - MCU temperature in 1°C. - - - - - MCU Internal VREF voltage in 0.02V. - - - - - MCU VBAT voltage in 0.02V. - - - - - VBUSP current draw in 0.02mA. - - - - - Raw MCU temperature sensor value. - - - - - Raw MCU Internal VREF sensor value. - - - - - Raw MCU VBAT sensor value. - - - - - Raw VBUSP Current sensor value. - - - - - Error Status Bits indicates error conditions inside stack or inside application. Specific bit is set by CO_errorReport() function, when error occurs in program. It can be reset by CO_errorReset() function, if error is solved. Emergency message is sent on each change of any Error Status Bit. If critical bits are set, node will not be able to stay in operational state. For more information see file CO_Emergency.h. - -Default error status bits are: - -Communication or protocol errors from driver (informative): -00 - ERROR_NO_ERROR - Error Reset or No Error. -01 - ERROR_CAN_BUS_WARNING - CAN bus warning. -02 - ERROR_RXMSG_WRONG_LENGTH - Wrong data length of received CAN message. -03 - ERROR_RXMSG_OVERFLOW - Previous received CAN message wasn't processed yet. -04 - ERROR_RPDO_WRONG_LENGTH - Wrong data length of received PDO. -05 - ERROR_RPDO_OVERFLOW - Previous received PDO wasn't processed yet. -06 - ERROR_CAN_RX_BUS_PASSIVE - CAN receive bus is passive. -07 - ERROR_CAN_TX_BUS_PASSIVE - CAN transmit bus is passive. - -Communication or protocol errors from driver (critical): -08 - ERROR_08_reserved - (reserved) -09 - ERROR_09_reserved - (reserved) -0A - ERROR_CAN_TX_BUS_OFF - CAN transmit bus is off. -0B - ERROR_CAN_RXB_OVERFLOW - CAN module receive buffer has overflowed. -0C - ERROR_CAN_TX_OVERFLOW - CAN transmit buffer has overflowed. -0D - ERROR_TPDO_OUTSIDE_WINDOW - TPDO is outside SYNC window. -0E - ERROR_CAN_CONFIGURATION_FAILED - Configuration of CAN module CAN failed (Rx or Tx). -0F - ERROR_0F_reserved - (reserved) - -Communication or protocol errors (informative): -10 - ERROR_NMT_WRONG_COMMAND - Wrong NMT command received. -11 - ERROR_SYNC_EARLY - SYNC message was too early. -12 - ERROR_12_reserved - (reserved) -13 - ERROR_13_reserved - (reserved) -14 - ERROR_14_reserved - (reserved) -15 - ERROR_15_reserved - (reserved) -16 - ERROR_16_reserved - (reserved) -17 - ERROR_17_reserved - (reserved) - -Communication or protocol errors (critical): -18 - ERROR_SYNC_TIME_OUT - SYNC message timeout. -19 - ERROR_SYNC_LENGTH - Unexpected SYNC data length -1A - ERROR_PDO_WRONG_MAPPING - Error with PDO mapping. -1B - ERROR_HEARTBEAT_CONSUMER - Heartbeat consumer timeout. -1C - ERROR_HEARTBEAT_CONSUMER_REMOTE_RESET - Heartbeat consumer detected remote node reset. -1D - ERROR_1D_reserved - (reserved) -1E - ERROR_1E_reserved - (reserved) -1F - ERROR_1F_reserved - (reserved) - -Generic errors (informative): -20 - ERROR_20_reserved - (reserved) -21 - ERROR_21_reserved - (reserved) -22 - ERROR_22_reserved - (reserved) -23 - ERROR_23_reserved - (reserved) -24 - ERROR_24_reserved - (reserved) -25 - ERROR_25_reserved - (reserved) -26 - ERROR_26_reserved - (reserved) -27 - ERROR_27_reserved - (reserved) - -Generic errors (critical): -28 - ERROR_WRONG_ERROR_REPORT - Wrong parameters to <CO_errorReport()> function. -29 - ERROR_ISR_TIMER_OVERFLOW - Timer task has overflowed. -2A - ERROR_MEMORY_ALLOCATION_ERROR - Unable to allocate memory for objects. -2B - ERROR_GENERIC_ERROR - Generic error, test usage. -2C - ERROR_MAIN_TIMER_OVERFLOW - Mainline function exceeded maximum execution time. -2D - ERROR_INTERNAL_STATE_APPL - Error in application software internal state. -2E - ERROR_2E_reserved - (reserved) -2F - ERROR_2F_reserved - (reserved) - -Manufacturer specific errors: -Manufacturer may define its own constants up to index 0xFF. Of course, he must then define large enough buffer for error status bits (up to 32 bytes). - - - - - - - - - - CANopen communication network profile - 1.1 - - - CommunicationNetwork - - 1 - 1 - CANopen - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/profiles/oresat_solar.xpd b/profiles/oresat_solar.xpd deleted file mode 100644 index 08468223..00000000 --- a/profiles/oresat_solar.xpd +++ /dev/null @@ -1,271 +0,0 @@ - - - - - - - CANopen device profile - 1.1 - - - Device - - 1 - 1 - CANopen - - - - - Portland State Aerospace Society - 0 - OreSat Solar Board - 0 - - OreSat Solar Board Object Dictionary - - 0 - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CANopen communication network profile - 1.1 - - - CommunicationNetwork - - 1 - 1 - CANopen - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/src/archive/app_acs_bldc_f0/Makefile b/src/archive/app_acs_bldc_f0/Makefile deleted file mode 100644 index 4edcd3c2..00000000 --- a/src/archive/app_acs_bldc_f0/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x200 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_acs_bldc - -# Target settings. -MCU = cortex-m0 -BOARD = ST_NUCLEO32_F042K6 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F042x6.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_acs_bldc_f0/README.md b/src/archive/app_acs_bldc_f0/README.md deleted file mode 100644 index 55f3c8e2..00000000 --- a/src/archive/app_acs_bldc_f0/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` diff --git a/src/archive/app_acs_bldc_f0/cfg/chconf.h b/src/archive/app_acs_bldc_f0/cfg/chconf.h deleted file mode 100644 index 6f3b51a9..00000000 --- a/src/archive/app_acs_bldc_f0/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_acs_bldc_f0/cfg/halconf.h b/src/archive/app_acs_bldc_f0/cfg/halconf.h deleted file mode 100644 index 0874eeae..00000000 --- a/src/archive/app_acs_bldc_f0/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_acs_bldc_f0/cfg/mcuconf.h b/src/archive/app_acs_bldc_f0/cfg/mcuconf.h deleted file mode 100644 index 78e88016..00000000 --- a/src/archive/app_acs_bldc_f0/cfg/mcuconf.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 12 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_USART1SW STM32_USART1SW_PCLK -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 -#define STM32_IRQ_USART1_PRIORITY 3 -#define STM32_IRQ_USART2_PRIORITY 3 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_acs_bldc_f0/main.c b/src/archive/app_acs_bldc_f0/main.c deleted file mode 100644 index c0250515..00000000 --- a/src/archive/app_acs_bldc_f0/main.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -//=== Project header files -//#include "oresat.h" -#include "acs_bldc.h" - -//=== Serial configuration -static SerialConfig ser_cfg = { - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - -// bldc control thread -static THD_WORKING_AREA(wa_bldcThread,128); -static THD_FUNCTION(bldcThread,arg){ - (void)arg; - chRegSetThreadName("bldc"); -// bldcSinStart(); - - while(!chThdShouldTerminateX()){ - chThdSleepMilliseconds(500); - } -} - -static void app_init(void){ - // Start up debug output - bldcInit(); - sdStart(&SD2, &ser_cfg); -} - -static void app_main(void){ - chThdCreateStatic( - wa_bldcThread, - sizeof(wa_bldcThread), - NORMALPRIO, - bldcThread, - NULL - ); - - /* - * Begin main loop - */ - while (true){ - chThdSleepMilliseconds(1000); - } -} - -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - //oresat_init(0); - - // Initialize and start app - app_init(); - app_main(); - - return 0; -} diff --git a/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.c b/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.c deleted file mode 100644 index a899cc5e..00000000 --- a/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.c +++ /dev/null @@ -1,255 +0,0 @@ -#include "acs_bldc.h" - -BldcConfig bldc; - -#ifdef SADDLE -#define STEPS 384 // for ease of calculations - -sinctrl_t sinctrl[STEPS]={ - 127,131,135,138,142,145,149,152,155,159,162,165,168,171,174,177,180,183,186, - 189,192,194,197,200,202,205,207,210,212,214,217,219,221,223,225,227,229,231, - 232,234,236,237,239,240,242,243,244,245,247,248,249,250,250,251,252,253,253, - 254,254,255,255,255,255,255,255,255,255,255,255,255,254,254,253,253,252,252, - 251,250,249,248,247,246,245,244,242,241,240,238,237,235,233,232,230,228,226, - 224,222,222,225,226,228,230,232,234,235,237,238,240,241,243,244,245,246,247, - 248,249,250,251,252,252,253,254,254,254,255,255,255,255,255,255,255,255,255, - 255,254,254,254,253,252,252,251,250,249,248,247,246,245,244,243,241,240,238, - 237,235,234,232,230,228,227,225,223,220,218,216,214,212,209,207,204,202,199, - 197,194,191,188,185,183,180,177,174,171,167,164,161,158,154,151,148,144,141, - 137,134,130,127,123,119,116,112,108,104,101, 97, 93, 89, 85, 81, 77, 73, 69, - 65, 61, 57, 53, 49, 45, 41, 36, 32, 28, 24, 20, 16, 12, 7, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 6, 10, 15, 19, 23, 27, 31, 35, - 39, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 99,103,107,111, - 115,118,121,124 -}; - -#endif - -#ifndef SADDLE -#define STEPS 180 -//#define STEPS 90 -//#define STEPS 360 -//#define STEPS 720 - // TODO: This has too many steps in it. we should redo this manually maybe -//* -sinctrl_t sinctrl[STEPS] = { - 5000,5174,5349,5523,5696,5868,6040,6210, - 6378,6545,6710,6873,7034,7192,7347,7500, - 7650,7796,7939,8078,8214,8346,8473,8597, - 8716,8830,8940,9045,9145,9240,9330,9415, - 9494,9568,9636,9698,9755,9806,9851,9891, - 9924,9951,9973,9988,9997,10000,9997,9988, - 9973,9951,9924,9891,9851,9806,9755,9698, - 9636,9568,9494,9415,9330,9240,9145,9045, - 8940,8830,8716,8597,8473,8346,8214,8078, - 7939,7796,7650,7500,7347,7192,7034,6873, - 6710,6545,6378,6210,6040,5868,5696,5523, - 5349,5174,5000,4826,4651,4477,4304,4132, - 3960,3790,3622,3455,3290,3127,2966,2808, - 2653,2500,2350,2204,2061,1922,1786,1654, - 1527,1403,1284,1170,1060,955,855,760, - 670,585,506,432,364,302,245,194, - 149,109,76,49,27,12,3,0, - 3,12,27,49,76,109,149,194, - 245,302,364,432,506,585,670,760, - 855,955,1060,1170,1284,1403,1527,1654, - 1786,1922,2061,2204,2350,2500,2653,2808, - 2966,3127,3290,3455,3622,3790,3960,4132, - 4304,4477,4651,4826 -}; -//*/ -/* -sinctrl_t sinctrl[STEPS] = { - 5000,5349,5696,6040,6378,6710,7034,7347, - 7650,7939,8214,8473,8716,8940,9145,9330, - 9494,9636,9755,9851,9924,9973,9997,9997, - 9973,9924,9851,9755,9636,9494,9330,9145, - 8940,8716,8473,8214,7939,7650,7347,7034, - 6710,6378,6040,5696,5349,5000,4651,4304, - 3960,3622,3290,2966,2653,2350,2061,1786, - 1527,1284,1060,855,670,506,364,245, - 149,76,27,3,3,27,76,149, - 245,364,506,670,855,1060,1284,1527, - 1786,2061,2350,2653,2966,3290,3622,3960, - 4304,4651 -}; -//*/ -/* -sinctrl_t sinctrl[STEPS] = { - 4980,5068,5155,5242,5329,5416,5503,5590,5676,5763,5849,5934,6020,6105,6190,6274, - 6359,6442,6525,6608,6690,6772,6853,6934,7014,7093,7172,7250,7328,7404,7480,7556, - 7630,7704,7776,7848,7919,7989,8059,8127,8194,8261,8326,8390,8454,8516,8577,8637, - 8696,8754,8811,8866,8920,8974,9025,9076,9126,9174,9221,9266,9311,9353,9395,9435, - 9474,9512,9548,9583,9616,9648,9679,9708,9736,9762,9787,9810,9832,9852,9871,9889, - 9904,9919,9932,9943,9953,9961,9968,9974,9977,9980,9980,9980,9977,9974,9968,9961, - 9953,9943,9932,9919,9904,9889,9871,9852,9832,9810,9787,9762,9736,9708,9679,9648, - 9616,9583,9548,9512,9474,9435,9395,9353,9311,9266,9221,9174,9126,9076,9025,8974, - 8920,8866,8811,8754,8696,8637,8577,8516,8454,8390,8326,8261,8194,8127,8059,7989, - 7919,7848,7776,7704,7630,7556,7480,7404,7328,7250,7172,7093,7014,6934,6853,6772, - 6690,6608,6525,6442,6359,6274,6190,6105,6020,5934,5849,5763,5676,5590,5503,5416, - 5329,5242,5155,5068,4980,4893,4806,4719,4632,4545,4458,4371,4285,4198,4112,4026, - 3941,3856,3771,3686,3602,3519,3435,3353,3270,3189,3107,3027,2947,2867,2789,2710, - 2633,2556,2480,2405,2331,2257,2184,2113,2041,1971,1902,1834,1766,1700,1635,1570, - 1507,1445,1384,1324,1265,1207,1150,1095,1040,987,935,885,835,787,740,695,650, - 607,566,525,486,449,413,378,344,312,282,253,225,199,174,151,129,109,90,72,56, - 42,29,18,8,0,0,0,0,0,0,0,0,0,0,0,8,18,29,42,56,72,90,109,129,151,174,199,225, - 253,282,312,344,378,413,449,486,525,566,607,650,695,740,787,835,885,935,987,1040, - 1095,1150,1207,1265,1324,1384,1445,1507,1570,1635,1700,1766,1834,1902,1971,2041, - 2113,2184,2257,2331,2405,2480,2556,2633,2710,2789,2867,2947,3027,3107,3189,3270, - 3353,3435,3519,3602,3686,3771,3856,3941,4026,4112,4198,4285,4371,4458,4545,4632, - 4719,4806,4893 -}; -//*/ -/* -sinctrl_t sinctrl[STEPS] = { - 5000,5087,5174,5262,5349,5436,5523,5609, - 5696,5782,5868,5954,6040,6125,6210,6294, - 6378,6462,6545,6628,6710,6792,6873,6954, - 7034,7113,7192,7270,7347,7424,7500,7575, - 7650,7723,7796,7868,7939,8009,8078,8147, - 8214,8280,8346,8410,8473,8536,8597,8657, - 8716,8774,8830,8886,8940,8993,9045,9096, - 9145,9193,9240,9286,9330,9373,9415,9455, - 9494,9532,9568,9603,9636,9668,9698,9728, - 9755,9782,9806,9830,9851,9872,9891,9908, - 9924,9938,9951,9963,9973,9981,9988,9993, - 9997,9999,10000,9999,9997,9993,9988,9981, - 9973,9963,9951,9938,9924,9908,9891,9872, - 9851,9830,9806,9782,9755,9728,9698,9668, - 9636,9603,9568,9532,9494,9455,9415,9373, - 9330,9286,9240,9193,9145,9096,9045,8993, - 8940,8886,8830,8774,8716,8657,8597,8536, - 8473,8410,8346,8280,8214,8147,8078,8009, - 7939,7868,7796,7723,7650,7575,7500,7424, - 7347,7270,7192,7113,7034,6954,6873,6792, - 6710,6628,6545,6462,6378,6294,6210,6125, - 6040,5954,5868,5782,5696,5609,5523,5436, - 5349,5262,5174,5087,5000,4913,4826,4738, - 4651,4564,4477,4391,4304,4218,4132,4046, - 3960,3875,3790,3706,3622,3538,3455,3372, - 3290,3208,3127,3046,2966,2887,2808,2730, - 2653,2576,2500,2425,2350,2277,2204,2132, - 2061,1991,1922,1853,1786,1720,1654,1590, - 1527,1464,1403,1343,1284,1226,1170,1114, - 1060,1007,955,904,855,807,760,714, - 670,627,585,545,506,468,432,397, - 364,332,302,272,245,218,194,170, - 149,128,109,92,76,62,49,37, - 27,19,12,7,3,1,0,1, - 3,7,12,19,27,37,49,62, - 76,92,109,128,149,170,194,218, - 245,272,302,332,364,397,432,468, - 506,545,585,627,670,714,760,807, - 855,904,955,1007,1060,1114,1170,1226, - 1284,1343,1403,1464,1527,1590,1654,1720, - 1786,1853,1922,1991,2061,2132,2204,2277, - 2350,2425,2500,2576,2653,2730,2808,2887, - 2966,3046,3127,3208,3290,3372,3455,3538, - 3622,3706,3790,3875,3960,4046,4132,4218, - 4304,4391,4477,4564,4651,4738,4826,4913, -}; -//*/ - -/* -sinctrl_t sinctrl[STEPS] = { - 5000,5044,5087,5131,5174,5218,5262,5305, - 5349,5392,5436,5479,5523,5566,5609,5653, - 5696,5739,5782,5825,5868,5911,5954,5997, - 6040,6082,6125,6167,6210,6252,6294,6336, - 6378,6420,6462,6504,6545,6587,6628,6669, - 6710,6751,6792,6833,6873,6913,6954,6994, - 7034,7073,7113,7153,7192,7231,7270,7309, - 7347,7386,7424,7462,7500,7538,7575,7612, - 7650,7686,7723,7760,7796,7832,7868,7904, - 7939,7974,8009,8044,8078,8113,8147,8180, - 8214,8247,8280,8313,8346,8378,8410,8442, - 8473,8505,8536,8566,8597,8627,8657,8686, - 8716,8745,8774,8802,8830,8858,8886,8913, - 8940,8967,8993,9019,9045,9071,9096,9121, - 9145,9169,9193,9217,9240,9263,9286,9308, - 9330,9352,9373,9394,9415,9435,9455,9475, - 9494,9513,9532,9550,9568,9585,9603,9619, - 9636,9652,9668,9683,9698,9713,9728,9742, - 9755,9769,9782,9794,9806,9818,9830,9841, - 9851,9862,9872,9881,9891,9900,9908,9916, - 9924,9931,9938,9945,9951,9957,9963,9968, - 9973,9977,9981,9985,9988,9991,9993,9995, - 9997,9998,9999,10000,10000,10000,9999,9998, - 9997,9995,9993,9991,9988,9985,9981,9977, - 9973,9968,9963,9957,9951,9945,9938,9931, - 9924,9916,9908,9900,9891,9881,9872,9862, - 9851,9841,9830,9818,9806,9794,9782,9769, - 9755,9742,9728,9713,9698,9683,9668,9652, - 9636,9619,9603,9585,9568,9550,9532,9513, - 9494,9475,9455,9435,9415,9394,9373,9352, - 9330,9308,9286,9263,9240,9217,9193,9169, - 9145,9121,9096,9071,9045,9019,8993,8967, - 8940,8913,8886,8858,8830,8802,8774,8745, - 8716,8686,8657,8627,8597,8566,8536,8505, - 8473,8442,8410,8378,8346,8313,8280,8247, - 8214,8180,8147,8113,8078,8044,8009,7974, - 7939,7904,7868,7832,7796,7760,7723,7686, - 7650,7612,7575,7538,7500,7462,7424,7386, - 7347,7309,7270,7231,7192,7153,7113,7073, - 7034,6994,6954,6913,6873,6833,6792,6751, - 6710,6669,6628,6587,6545,6504,6462,6420, - 6378,6336,6294,6252,6210,6167,6125,6082, - 6040,5997,5954,5911,5868,5825,5782,5739, - 5696,5653,5609,5566,5523,5479,5436,5392, - 5349,5305,5262,5218,5174,5131,5087,5044, - 5000,4956,4913,4869,4826,4782,4738,4695, - 4651,4608,4564,4521,4477,4434,4391,4347, - 4304,4261,4218,4175,4132,4089,4046,4003, - 3960,3918,3875,3833,3790,3748,3706,3664, - 3622,3580,3538,3496,3455,3413,3372,3331, - 3290,3249,3208,3167,3127,3087,3046,3006, - 2966,2927,2887,2847,2808,2769,2730,2691, - 2653,2614,2576,2538,2500,2462,2425,2388, - 2350,2314,2277,2240,2204,2168,2132,2096, - 2061,2026,1991,1956,1922,1887,1853,1820, - 1786,1753,1720,1687,1654,1622,1590,1558, - 1527,1495,1464,1434,1403,1373,1343,1314, - 1284,1255,1226,1198,1170,1142,1114,1087, - 1060,1033,1007,981,955,929,904,879, - 855,831,807,783,760,737,714,692, - 670,648,627,606,585,565,545,525, - 506,487,468,450,432,415,397,381, - 364,348,332,317,302,287,272,258, - 245,231,218,206,194,182,170,159, - 149,138,128,119,109,100,92,84, - 76,69,62,55,49,43,37,32, - 27,23,19,15,12,9,7,5, - 3,2,1,0,0,0,1,2, - 3,5,7,9,12,15,19,23, - 27,32,37,43,49,55,62,69, - 76,84,92,100,109,119,128,138, - 149,159,170,182,194,206,218,231, - 245,258,272,287,302,317,332,348, - 364,381,397,415,432,450,468,487, - 506,525,545,565,585,606,627,648, - 670,692,714,737,760,783,807,831, - 855,879,904,929,955,981,1007,1033, - 1060,1087,1114,1142,1170,1198,1226,1255, - 1284,1314,1343,1373,1403,1434,1464,1495, - 1527,1558,1590,1622,1654,1687,1720,1753, - 1786,1820,1853,1887,1922,1956,1991,2026, - 2061,2096,2132,2168,2204,2240,2277,2314, - 2350,2388,2425,2462,2500,2538,2576,2614, - 2653,2691,2730,2769,2808,2847,2887,2927, - 2966,3006,3046,3087,3127,3167,3208,3249, - 3290,3331,3372,3413,3455,3496,3538,3580, - 3622,3664,3706,3748,3790,3833,3875,3918, - 3960,4003,4046,4089,4132,4175,4218,4261, - 4304,4347,4391,4434,4477,4521,4564,4608, - 4651,4695,4738,4782,4826,4869,4913,4956, -}; -//*/ - -#endif - diff --git a/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.h b/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.h deleted file mode 100644 index ba310740..00000000 --- a/src/archive/app_acs_bldc_f0/scratch/acs_sinlut.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef SINLUT_H -#define SINLUT_H - -typedef struct{ - sinctl_t *sinctl; - int steps; -}sinlut; - -sinctrl_t sinctrl360[] = { - 5000,5087,5174,5262,5349,5436,5523,5609, - 5696,5782,5868,5954,6040,6125,6210,6294, - 6378,6462,6545,6628,6710,6792,6873,6954, - 7034,7113,7192,7270,7347,7424,7500,7575, - 7650,7723,7796,7868,7939,8009,8078,8147, - 8214,8280,8346,8410,8473,8536,8597,8657, - 8716,8774,8830,8886,8940,8993,9045,9096, - 9145,9193,9240,9286,9330,9373,9415,9455, - 9494,9532,9568,9603,9636,9668,9698,9728, - 9755,9782,9806,9830,9851,9872,9891,9908, - 9924,9938,9951,9963,9973,9981,9988,9993, - 9997,9999,10000,9999,9997,9993,9988,9981, - 9973,9963,9951,9938,9924,9908,9891,9872, - 9851,9830,9806,9782,9755,9728,9698,9668, - 9636,9603,9568,9532,9494,9455,9415,9373, - 9330,9286,9240,9193,9145,9096,9045,8993, - 8940,8886,8830,8774,8716,8657,8597,8536, - 8473,8410,8346,8280,8214,8147,8078,8009, - 7939,7868,7796,7723,7650,7575,7500,7424, - 7347,7270,7192,7113,7034,6954,6873,6792, - 6710,6628,6545,6462,6378,6294,6210,6125, - 6040,5954,5868,5782,5696,5609,5523,5436, - 5349,5262,5174,5087,5000,4913,4826,4738, - 4651,4564,4477,4391,4304,4218,4132,4046, - 3960,3875,3790,3706,3622,3538,3455,3372, - 3290,3208,3127,3046,2966,2887,2808,2730, - 2653,2576,2500,2425,2350,2277,2204,2132, - 2061,1991,1922,1853,1786,1720,1654,1590, - 1527,1464,1403,1343,1284,1226,1170,1114, - 1060,1007,955,904,855,807,760,714, - 670,627,585,545,506,468,432,397, - 364,332,302,272,245,218,194,170, - 149,128,109,92,76,62,49,37, - 27,19,12,7,3,1,0,1, - 3,7,12,19,27,37,49,62, - 76,92,109,128,149,170,194,218, - 245,272,302,332,364,397,432,468, - 506,545,585,627,670,714,760,807, - 855,904,955,1007,1060,1114,1170,1226, - 1284,1343,1403,1464,1527,1590,1654,1720, - 1786,1853,1922,1991,2061,2132,2204,2277, - 2350,2425,2500,2576,2653,2730,2808,2887, - 2966,3046,3127,3208,3290,3372,3455,3538, - 3622,3706,3790,3875,3960,4046,4132,4218, - 4304,4391,4477,4564,4651,4738,4826,4913, -}; -#endif diff --git a/src/archive/app_acs_bldc_f0/source/README.md b/src/archive/app_acs_bldc_f0/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_acs_bldc_f0/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_acs_bldc_f0/source/acs_bldc.c b/src/archive/app_acs_bldc_f0/source/acs_bldc.c deleted file mode 100644 index 6d015171..00000000 --- a/src/archive/app_acs_bldc_f0/source/acs_bldc.c +++ /dev/null @@ -1,221 +0,0 @@ -#include "acs_bldc.h" - -BldcConfig bldc; - -//* -sinctrl_t sinctrl360[] = { - 5000,5087,5174,5262,5349,5436,5523,5609, - 5696,5782,5868,5954,6040,6125,6210,6294, - 6378,6462,6545,6628,6710,6792,6873,6954, - 7034,7113,7192,7270,7347,7424,7500,7575, - 7650,7723,7796,7868,7939,8009,8078,8147, - 8214,8280,8346,8410,8473,8536,8597,8657, - 8716,8774,8830,8886,8940,8993,9045,9096, - 9145,9193,9240,9286,9330,9373,9415,9455, - 9494,9532,9568,9603,9636,9668,9698,9728, - 9755,9782,9806,9830,9851,9872,9891,9908, - 9924,9938,9951,9963,9973,9981,9988,9993, - 9997,9999,10000,9999,9997,9993,9988,9981, - 9973,9963,9951,9938,9924,9908,9891,9872, - 9851,9830,9806,9782,9755,9728,9698,9668, - 9636,9603,9568,9532,9494,9455,9415,9373, - 9330,9286,9240,9193,9145,9096,9045,8993, - 8940,8886,8830,8774,8716,8657,8597,8536, - 8473,8410,8346,8280,8214,8147,8078,8009, - 7939,7868,7796,7723,7650,7575,7500,7424, - 7347,7270,7192,7113,7034,6954,6873,6792, - 6710,6628,6545,6462,6378,6294,6210,6125, - 6040,5954,5868,5782,5696,5609,5523,5436, - 5349,5262,5174,5087,5000,4913,4826,4738, - 4651,4564,4477,4391,4304,4218,4132,4046, - 3960,3875,3790,3706,3622,3538,3455,3372, - 3290,3208,3127,3046,2966,2887,2808,2730, - 2653,2576,2500,2425,2350,2277,2204,2132, - 2061,1991,1922,1853,1786,1720,1654,1590, - 1527,1464,1403,1343,1284,1226,1170,1114, - 1060,1007,955,904,855,807,760,714, - 670,627,585,545,506,468,432,397, - 364,332,302,272,245,218,194,170, - 149,128,109,92,76,62,49,37, - 27,19,12,7,3,1,0,1, - 3,7,12,19,27,37,49,62, - 76,92,109,128,149,170,194,218, - 245,272,302,332,364,397,432,468, - 506,545,585,627,670,714,760,807, - 855,904,955,1007,1060,1114,1170,1226, - 1284,1343,1403,1464,1527,1590,1654,1720, - 1786,1853,1922,1991,2061,2132,2204,2277, - 2350,2425,2500,2576,2653,2730,2808,2887, - 2966,3046,3127,3208,3290,3372,3455,3538, - 3622,3706,3790,3875,3960,4046,4132,4218, - 4304,4391,4477,4564,4651,4738,4826,4913 -}; -//*/ - -/* -static sinctrl_t sinctrlSaddle[384] = { - 127,131,135,138,142,145,149,152, - 155,159,162,165,168,171,174,177, - 180,183,186,189,192,194,197,200, - 202,205,207,210,212,214,217,219, - 221,223,225,227,229,231,232,234, - 236,237,239,240,242,243,244,245, - 247,248,249,250,250,251,252,253, - 253,254,254,255,255,255,255,255, - 255,255,255,255,255,255,254,254, - 253,253,252,252,251,250,249,248, - 247,246,245,244,242,241,240,238, - 237,235,233,232,230,228,226,224, - 222,222,225,226,228,230,232,234, - 235,237,238,240,241,243,244,245, - 246,247,248,249,250,251,252,252, - 253,254,254,254,255,255,255,255, - 255,255,255,255,255,255,254,254, - 254,253,252,252,251,250,249,248, - 247,246,245,244,243,241,240,238, - 237,235,234,232,230,228,227,225, - 223,220,218,216,214,212,209,207, - 204,202,199,197,194,191,188,185, - 183,180,177,174,171,167,164,161, - 158,154,151,148,144,141,137,134, - 130,127,123,119,116,112,108,104, - 101, 97, 93, 89, 85, 81, 77, 73, - 69, 65, 61, 57, 53, 49, 45, 41, - 36, 32, 28, 24, 20, 16, 12, 7, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 2, 6, 10, 15, 19, 23, 27, 31, - 35, 39, 44, 48, 52, 56, 60, 64, - 68, 72, 76, 80, 84, 88, 92, 96, - 99,103,107,111,115,118,121,124 -}; -//*/ - - -// pwm period callback -static void pwmpcb(PWMDriver *pwmp) { - (void)pwmp; - - palClearLine(LINE_LED_GREEN); - - ++bldc.count; - - if(bldc.count==bldc.stretch){ - ++bldc.u; - ++bldc.v; - ++bldc.w; - - if(bldc.u >= bldc.period){ - bldc.u = 0; - } - if(bldc.v >= bldc.period){ - bldc.v = 0; - } - if(bldc.w >= bldc.period){ - bldc.w = 0; - } - - bldc.count=0; - } -} - -static sinctrl_t scale(sinctrl_t duty_cycle){ - return (duty_cycle*bldc.scale)/10; -} - -static void pwmCallback(uint8_t channel,sinctrl_t step){ - palSetLine(LINE_LED_GREEN); - pwmEnableChannelI( - &PWMD1, - channel, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(sinctrl360[step])) - ); -} - -static void pwmUcb(PWMDriver *pwmp){ // channel 1 callback - (void)pwmp; - pwmCallback(PWM_U,bldc.u); -} - -static void pwmVcb(PWMDriver *pwmp){ // channel 2 callback - (void)pwmp; - pwmCallback(PWM_V,bldc.v); -} - -static void pwmWcb(PWMDriver *pwmp){ // channel 3 callback - (void)pwmp; - pwmCallback(PWM_W,bldc.w); -} - -static PWMConfig pwmcfg = { - PWM_TIMER_FREQ, - PWM_PERIOD, - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmUcb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmVcb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmWcb}, - {PWM_OUTPUT_ACTIVE_HIGH,NULL} - }, - 0, - 0, - 0 -}; - - -extern void bldcInit(){ - bldc.period = PERIOD; - bldc.stretch = STRETCH; - bldc.scale = SCALE; - //bldc.sinctrl_size = sizeof(sinctrl)/sizeof(sinctrl_t); - bldc.phase_shift = bldc.period/3; - bldc.count=0; - bldc.u = 0; - bldc.v = bldc.u + bldc.phase_shift; - bldc.w = bldc.v + bldc.phase_shift; - - pwmStart(&PWMD1, &pwmcfg); - pwmEnablePeriodicNotification(&PWMD1); - -// palSetPadMode(GPIOA, 11, PAL_MODE_ALTERNATE(0)); - - pwmEnableChannel(&PWMD1,PWM_U,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.u)); - pwmEnableChannel(&PWMD1,PWM_V,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.v)); - pwmEnableChannel(&PWMD1,PWM_W,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.w)); - - // enable pwm center aligned mode - // TODO: This is not working. needs more research - // - //PWMD1.tim->CR1 |= STM32_TIM_CR1_CMS(0x01); - - pwmEnableChannelNotification(&PWMD1,PWM_U); - pwmEnableChannelNotification(&PWMD1,PWM_V); - pwmEnableChannelNotification(&PWMD1,PWM_W); -} - -extern void bldcStart(){ - -} - -extern void bldcStop(){ - -} - -extern void bldcSinStart(){ - -} - diff --git a/src/archive/app_acs_bldc_f0/source/acs_bldc.h b/src/archive/app_acs_bldc_f0/source/acs_bldc.h deleted file mode 100644 index 595746a3..00000000 --- a/src/archive/app_acs_bldc_f0/source/acs_bldc.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef ACS_BLDC_H -#define ACS_BLDC_H - -#include "ch.h" -#include "hal.h" -//#include "acs_sinlut.h" - -#define SCALE 9 -#define PERIOD 360 -#define STRETCH 1 - -#define sinctrl_t int -//#define sinctrl_t uint32_t // in testing - -typedef struct{ - sinctrl_t u,v,w,phase_shift; - int sinctrl_size; - int count; - int scale; - int period; - int stretch; - sinctrl_t *sinctrl; -} BldcConfig; - -//* -#define PWM_TIMER_FREQ 48e6 // Hz -#define PWM_FREQ 30000// periods per sec -//*/ - -#define PWM_PERIOD PWM_TIMER_FREQ/PWM_FREQ - -#define PWM_U 0U -#define PWM_V 1U -#define PWM_W 2U -#define PWM_D 3U - -extern void bldcInit(void); -extern void bldcStart(void); -extern void bldcStop(void); - -extern void bldcSinStart(void); - -#endif diff --git a/src/archive/app_acs_bldc_f4/Makefile b/src/archive/app_acs_bldc_f4/Makefile deleted file mode 100644 index 3c0c6601..00000000 --- a/src/archive/app_acs_bldc_f4/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_acs_bldc - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_F446RE - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_acs_bldc_f4/README.md b/src/archive/app_acs_bldc_f4/README.md deleted file mode 100644 index 55f3c8e2..00000000 --- a/src/archive/app_acs_bldc_f4/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` diff --git a/src/archive/app_acs_bldc_f4/cfg/chconf.h b/src/archive/app_acs_bldc_f4/cfg/chconf.h deleted file mode 100644 index 8e12427c..00000000 --- a/src/archive/app_acs_bldc_f4/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_acs_bldc_f4/cfg/halconf.h b/src/archive/app_acs_bldc_f4/cfg/halconf.h deleted file mode 100644 index 067f2147..00000000 --- a/src/archive/app_acs_bldc_f4/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_acs_bldc_f4/cfg/mcuconf.h b/src/archive/app_acs_bldc_f4/cfg/mcuconf.h deleted file mode 100644 index 59626a7e..00000000 --- a/src/archive/app_acs_bldc_f4/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_acs_bldc_f4/main.c b/src/archive/app_acs_bldc_f4/main.c deleted file mode 100644 index f649b654..00000000 --- a/src/archive/app_acs_bldc_f4/main.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -//=== Project header files -//#include "can.h" -#include "acs_bldc.h" - -//=== Serial configuration -static SerialConfig ser_cfg = { - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - -// bldc control thread -static THD_WORKING_AREA(wa_bldcThread,128); -static THD_FUNCTION(bldcThread,arg){ - (void)arg; - chRegSetThreadName("bldc"); -// bldcSinStart(); - - while(!chThdShouldTerminateX()){ - chThdSleepMilliseconds(500); - } -} - -static void app_init(void){ - // Start up debug output - bldcInit(); - sdStart(&SD2, &ser_cfg); -} - -static void app_main(void){ - chThdCreateStatic( - wa_bldcThread, - sizeof(wa_bldcThread), - NORMALPRIO, - bldcThread, - NULL - ); - - /* - * Begin main loop - */ - while (true){ - chThdSleepMilliseconds(1000); - } -} - -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - // Initialize CAN Subsystem - //can_init(); - // Start CAN threads - //can_start(); - - // Initialize and start app - app_init(); - app_main(); - - return 0; -} - -//! @} diff --git a/src/archive/app_acs_bldc_f4/source/README.md b/src/archive/app_acs_bldc_f4/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_acs_bldc_f4/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_acs_bldc_f4/source/acs_bldc.c b/src/archive/app_acs_bldc_f4/source/acs_bldc.c deleted file mode 100644 index f6c1b45a..00000000 --- a/src/archive/app_acs_bldc_f4/source/acs_bldc.c +++ /dev/null @@ -1,149 +0,0 @@ -#include "acs_bldc.h" - -int sinctrl[] = { - 4980,5068,5155,5242,5329,5416,5503,5590,5676,5763,5849,5934,6020,6105,6190,6274, - 6359,6442,6525,6608,6690,6772,6853,6934,7014,7093,7172,7250,7328,7404,7480,7556, - 7630,7704,7776,7848,7919,7989,8059,8127,8194,8261,8326,8390,8454,8516,8577,8637, - 8696,8754,8811,8866,8920,8974,9025,9076,9126,9174,9221,9266,9311,9353,9395,9435, - 9474,9512,9548,9583,9616,9648,9679,9708,9736,9762,9787,9810,9832,9852,9871,9889, - 9904,9919,9932,9943,9953,9961,9968,9974,9977,9980,9980,9980,9977,9974,9968,9961, - 9953,9943,9932,9919,9904,9889,9871,9852,9832,9810,9787,9762,9736,9708,9679,9648, - 9616,9583,9548,9512,9474,9435,9395,9353,9311,9266,9221,9174,9126,9076,9025,8974, - 8920,8866,8811,8754,8696,8637,8577,8516,8454,8390,8326,8261,8194,8127,8059,7989, - 7919,7848,7776,7704,7630,7556,7480,7404,7328,7250,7172,7093,7014,6934,6853,6772, - 6690,6608,6525,6442,6359,6274,6190,6105,6020,5934,5849,5763,5676,5590,5503,5416, - 5329,5242,5155,5068,4980,4893,4806,4719,4632,4545,4458,4371,4285,4198,4112,4026, - 3941,3856,3771,3686,3602,3519,3435,3353,3270,3189,3107,3027,2947,2867,2789,2710, - 2633,2556,2480,2405,2331,2257,2184,2113,2041,1971,1902,1834,1766,1700,1635,1570, - 1507,1445,1384,1324,1265,1207,1150,1095,1040,987,935,885,835,787,740,695,650, - 607,566,525,486,449,413,378,344,312,282,253,225,199,174,151,129,109,90,72,56, - 42,29,18,8,0,0,0,0,0,0,0,0,0,0,0,8,18,29,42,56,72,90,109,129,151,174,199,225, - 253,282,312,344,378,413,449,486,525,566,607,650,695,740,787,835,885,935,987,1040, - 1095,1150,1207,1265,1324,1384,1445,1507,1570,1635,1700,1766,1834,1902,1971,2041, - 2113,2184,2257,2331,2405,2480,2556,2633,2710,2789,2867,2947,3027,3107,3189,3270, - 3353,3435,3519,3602,3686,3771,3856,3941,4026,4112,4198,4285,4371,4458,4545,4632, - 4719,4806,4893,4980 -}; - -BldcConfig bldc; - -// pwm period callback -static void pwmpcb(PWMDriver *pwmp) { - (void)pwmp; - - palClearLine(LINE_LED_GREEN); - -// if(bldc.count==0){ - ++bldc.u; - ++bldc.v; - ++bldc.w; - - if(bldc.u >= 360){ - bldc.u = 0; - } - if(bldc.v >= 360){ - bldc.v = 0; - } - if(bldc.w >= 360){ - bldc.w = 0; - } - bldc.count=0; -// } -// ++bldc.count; -} - -int scale(int duty_cycle){ - return duty_cycle;//*5/10+2000; -} - -static void pwmc1cb(PWMDriver *pwmp){ // channel 1 callback - (void)pwmp; - palSetLine(LINE_LED_GREEN); - pwmEnableChannelI( - &PWMD1, - PWM_CH1, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(sinctrl[bldc.u])) - ); -} - -static void pwmc2cb(PWMDriver *pwmp){ // channel 2 callback - (void)pwmp; - palSetLine(LINE_LED_GREEN); - pwmEnableChannelI( - &PWMD1, - PWM_CH2, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(sinctrl[bldc.v])) - ); -} - -static void pwmc3cb(PWMDriver *pwmp){ // channel 3 callback - (void)pwmp; - palSetLine(LINE_LED_GREEN); - pwmEnableChannelI( - &PWMD1, - PWM_CH3, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(sinctrl[bldc.w])) - ); -} - -static PWMConfig pwmcfg = { - PWM_TIMER_FREQ, - PWM_PERIOD, - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmc1cb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmc2cb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmc3cb}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, - 0, - 0 -}; - -extern void bldcInit(){ - bldc.sinctrl_size = sizeof(sinctrl)/sizeof(int); - bldc.phase_shift = bldc.sinctrl_size/3; - bldc.u = 0; - bldc.v = bldc.u + bldc.phase_shift; - bldc.w = bldc.v + bldc.phase_shift; - bldc.count=0; - - pwmStart(&PWMD1, &pwmcfg); - pwmEnablePeriodicNotification(&PWMD1); - - palSetPadMode(GPIOPort, ACH1, PAL_MODE_ALTERNATE(1)); - palSetPadMode(GPIOPort, ACH2, PAL_MODE_ALTERNATE(1)); - palSetPadMode(GPIOPort, ACH3, PAL_MODE_ALTERNATE(1)); - - palSetPadMode(GPIOComp, BCH1, PAL_MODE_ALTERNATE(1)); - palSetPadMode(GPIOComp, BCH2, PAL_MODE_ALTERNATE(1)); - palSetPadMode(GPIOComp, BCH3, PAL_MODE_ALTERNATE(1)); - - -//* - pwmEnableChannel(&PWMD1,PWM_CH1,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.u)); - pwmEnableChannel(&PWMD1,PWM_CH2,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.v)); - pwmEnableChannel(&PWMD1,PWM_CH3,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.w)); -//*/ - - // enable pwm center aligned mode -// PWMD1.tim->CR1 |= STM32_TIM_CR1_CMS(0x01); - - pwmEnableChannelNotification(&PWMD1,PWM_CH1); - pwmEnableChannelNotification(&PWMD1,PWM_CH2); - pwmEnableChannelNotification(&PWMD1,PWM_CH3); -} - -extern void bldcStart(){ - -} - -extern void bldcStop(){ - -} - -extern void bldcSinStart(){ - -} - diff --git a/src/archive/app_acs_bldc_f4/source/acs_bldc.h b/src/archive/app_acs_bldc_f4/source/acs_bldc.h deleted file mode 100644 index fbb61b72..00000000 --- a/src/archive/app_acs_bldc_f4/source/acs_bldc.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef ACS_BLDC_H -#define ACS_BLDC_H - -#include "ch.h" -#include "hal.h" - -typedef struct{ - int u; - int v; - int w; - int count; - int sinctrl_size; - int phase_shift; -} BldcConfig; - -#define GPIOPort GPIOA -// Pin number -#define ACH1 8U -#define ACH2 9U -#define ACH3 10U - -#define GPIOComp GPIOB -#define BCH1 13U -#define BCH2 14U -#define BCH3 15U - - -/* -#define PWM_TIMER_FREQ 40000U -#define PWM_FREQ 360U // periods per sec -//*/ -//* -//#define PWM_TIMER_FREQ 40000 // Hz -#define PWM_TIMER_FREQ 1e6 // Hz -#define PWM_FREQ 20000// periods per sec -//*/ -#define PWM_PERIOD PWM_TIMER_FREQ/PWM_FREQ - -#define PWM_CH1 0U -#define PWM_CH2 1U -#define PWM_CH3 2U - -#define PWM_DC_CH1 2000U -#define PWM_DC_CH2 4000U -#define PWM_DC_CH3 8000U - -extern void bldcInit(void); -extern void bldcStart(void); -extern void bldcStop(void); - -extern void bldcSinStart(void); - -#endif diff --git a/src/archive/app_acs_bldc_f4/source/thread1.c b/src/archive/app_acs_bldc_f4/source/thread1.c deleted file mode 100644 index 031e4904..00000000 --- a/src/archive/app_acs_bldc_f4/source/thread1.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "thread1.h" - -// Example blinker thread -THD_WORKING_AREA(waThread1, 128); -THD_FUNCTION(Thread1, arg) { - - (void)arg; - chRegSetThreadName("thread1"); - - while (!chThdShouldTerminateX()) { - palClearLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - palSetLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - } -} diff --git a/src/archive/app_acs_bldc_f4/source/thread1.h b/src/archive/app_acs_bldc_f4/source/thread1.h deleted file mode 100644 index 32f225d5..00000000 --- a/src/archive/app_acs_bldc_f4/source/thread1.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _THREAD1_H_ -#define _THREAD1_H_ - -#include "ch.h" -#include "hal.h" - -// Example blinker thread prototypes -extern THD_WORKING_AREA(waThread1, 128); -extern THD_FUNCTION(Thread1, arg); - -#endif diff --git a/src/archive/app_ax5043_HDLC_rx/Makefile b/src/archive/app_ax5043_HDLC_rx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_HDLC_rx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_HDLC_rx/README.md b/src/archive/app_ax5043_HDLC_rx/README.md deleted file mode 100644 index 251e4488..00000000 --- a/src/archive/app_ax5043_HDLC_rx/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_FulDuplex_ground - -This is used to transmit semtech radio packets signal. -This creates a instruction packet at 735.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_HDLC_rx/conf/chconf.h b/src/archive/app_ax5043_HDLC_rx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_HDLC_rx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_HDLC_rx/conf/halconf.h b/src/archive/app_ax5043_HDLC_rx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_HDLC_rx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_HDLC_rx/conf/mcuconf.h b/src/archive/app_ax5043_HDLC_rx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_HDLC_rx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_HDLC_rx/main.c b/src/archive/app_ax5043_HDLC_rx/main.c deleted file mode 100644 index 87a2e556..00000000 --- a/src/archive/app_ax5043_HDLC_rx/main.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - - - //uint16_t reg=0; - uint8_t value=0; - uint8_t value1=0x55; - uint8_t ret_value[3]={0,0,0}; - //int i; - - - ax5043_read_reg(&SPID2, AX5043_REG_REV, value, ret_value); - chThdSleepMilliseconds(1500); - - - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - chprintf(DEBUG_CHP, "\r\r scratch ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_write_reg(&SPID2, AX5043_REG_SCRATCH, value1, ret_value); - chprintf(DEBUG_CHP, "\r\r scratch ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - chprintf(DEBUG_CHP, "\r\r scratch ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - - - - ax5043_prepare_rx(&SPID2); - - - - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - /* Enabling events on both edges of the button line.*/ - //palEnableLineEvent(LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE); - palEnableLineEvent(LINE_ARD_A5, PAL_EVENT_MODE_RISING_EDGE); - //ax5043_write_reg(&SPID2, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - //ax5043_write_reg(&SPID2, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - //ax5043_write_reg(&SPID2, AX5043_REG_IRQREQUEST0, (uint8_t)0x00, ret_value); - //ax5043_write_reg(&SPID2, AX5043_REG_IRQREQUEST1, (uint8_t)0x00, ret_value); - - while(true) - { - //palWaitLineTimeout(LINE_BUTTON, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_INFINITE); - palWaitLineTimeout(LINE_ARD_A5, TIME_MS2I(5000)); - - if (palReadLine(LINE_ARD_A5)) - chprintf(DEBUG_CHP, "\r\r int line is HIGH ** \r\n"); - else - chprintf(DEBUG_CHP, "\r\r int line is LOW ** \r\n"); -/* - ax5043_read_reg(&SPID2, AX5043_REG_IRQREQUEST0, value, ret_value); - chprintf(DEBUG_CHP, "\r\r IRQREQUEST0 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_IRQREQUEST1, value, ret_value); - chprintf(DEBUG_CHP, "\r\r IRQREQUEST1 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_RADIOEVENTREQ0, value, ret_value); - chprintf(DEBUG_CHP, "\r\r RADIOEVENTREQ0 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_RADIOEVENTREQ1, value, ret_value); - chprintf(DEBUG_CHP, "\r\r RADIOEVENTREQ1 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_IRQMASK0, value, ret_value); - chprintf(DEBUG_CHP, "\r\r IRQMASK0 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); - ax5043_read_reg(&SPID2, AX5043_REG_IRQMASK1, value, ret_value); - chprintf(DEBUG_CHP, "\r\r IRQMASK1 ret_value=0x%x 0x%x, --\r\n", ret_value[0],ret_value[1]); -*/ - chprintf(DEBUG_CHP, "Reading FIFO\r\n"); - //ax5043_receive(&SPID2); - receive_loop(&SPID2); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_HDLC_rx/source/README.md b/src/archive/app_ax5043_HDLC_rx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_HDLC_rx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_HDLC_rx/source/ax5043.c b/src/archive/app_ax5043_HDLC_rx/source/ax5043.c deleted file mode 100644 index 1902a9a8..00000000 --- a/src/archive/app_ax5043_HDLC_rx/source/ax5043.c +++ /dev/null @@ -1,1273 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_phy_channelbusy = -87 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 184; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 72; -const uint8_t axradio_phy_preamble_byte = 0x7e; -const uint8_t axradio_phy_preamble_flags = 0x38; -const uint8_t axradio_phy_preamble_appendbits = 0; -const uint8_t axradio_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 3; -const uint8_t axradio_framing_addrlen = 1; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 0; -const uint8_t axradio_framing_lenmask = 0xff; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; -const uint8_t axradio_phy_innerfreqloop = 0; - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x--\r\n", command_buf[0],command_buf[1]); - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x--\r\n", ret_value[0],ret_value[1]); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x, [2]=0x%x--\r\n", command_buf[0],command_buf[1],command_buf[2]); - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x , [2]=0x%x--\r\n", ret_value[0],ret_value[1],ret_value[2]); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Writes to an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - //uint8_t return_val; - //int num_retries = 1; - //return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - ax5043_write_reg_spi(spip, reg, value, ret_value); - -/* - while (num_retries > 0 && return_val != 0x80) - { - chThdSleepMicroseconds(100); - return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - num_retries--; - //chprintf(DEBUG_CHP, "\r\r num_retries= %d --\r\n", num_retries); - }*/ - -} - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r spi read reg=0x%x, value=0x%x ret=0x%x %x--\r\n", command_buf[0],command_buf[1], ret_value[0],ret_value[1]); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r spi read reg=0x%x %x, value=0x%x ret=0x%x %x %x--\r\n", command_buf[0],command_buf[1],command_buf[2],ret_value[0],ret_value[1],ret_value[2]); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x15, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - chThdSleepMilliseconds(10); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - chThdSleepMilliseconds(10); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - chThdSleepMilliseconds(10); - - -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x32, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - //int num_retries; - //uint8_t pll_range_done = 0; - //uint8_t pll_range_after; - //uint8_t vcoi_save; - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); //reset is causing problems and hence disabling it.need to remove it - - //adding two more lines to diable the interrupts. Need to remove it later - //ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - //ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet. Not used in thsi version of code. - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_transmit(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - int i=0; - ax5043_full_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - //send out the preamble - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xE0, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //sync word - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xA1, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x18, ret_value);//sync flags - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - - -/* seems this will not get executed based on logic - //send out the preamble. again? - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //writting preamble based on address register. pretty weird. - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x41), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1C, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); -*/ - - //write MAC and packet - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0C, ret_value);//packet length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x03, ret_value);//packet details like raw packet - - - //length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0B, ret_value); - //address values - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x34, ret_value); - for (i=0;i<8;i++) - { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x36, ret_value);//some random data - } - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - -} - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit_isr \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - -uint8_t axradio_rxbuffer[256]; - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - - -uint8_t receive_loop(SPIDriver * spip) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown chunk in FIFO\r\n"); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // purge FIFO - } - while (--i); - break; - } - } - - chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - -//!@ - diff --git a/src/archive/app_ax5043_HDLC_rx/source/ax5043.h b/src/archive/app_ax5043_HDLC_rx/source/ax5043.h deleted file mode 100644 index 0f82d6bb..00000000 --- a/src/archive/app_ax5043_HDLC_rx/source/ax5043.h +++ /dev/null @@ -1,732 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_transmit(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; -uint8_t receive_loop(SPIDriver * spip); - -#endif -//! @} diff --git a/src/archive/app_ax5043_HDLC_tx/Makefile b/src/archive/app_ax5043_HDLC_tx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_HDLC_tx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_HDLC_tx/README.md b/src/archive/app_ax5043_HDLC_tx/README.md deleted file mode 100644 index fbb1fadd..00000000 --- a/src/archive/app_ax5043_HDLC_tx/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_ax5043_HDLC_FEC_tx - -This is used to transmit sax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_HDLC_tx/axradiolab_435.5_100.xml b/src/archive/app_ax5043_HDLC_tx/axradiolab_435.5_100.xml deleted file mode 100755 index c4c4e786..00000000 --- a/src/archive/app_ax5043_HDLC_tx/axradiolab_435.5_100.xml +++ /dev/null @@ -1,287 +0,0 @@ - - - -0 -0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -0 -0 -1000.000000 -200 -0 -0 - - -0xAB -0x00 -0 - - -0 -1 -1 -0 -0 -1 - - -0x01 -0x00 -0x01 -0x00 -0x00 -0x01 -0x07 -0x03 -0x01 -0x01 -0x01 -0x0 -0x0 - - -435500000.000000 -1 -0x00 -0x19 -0x02 -0x01 -0x09 -0x09 -1200.000000 -2200.000000 -48000000.000000 -871.000000 -
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-200000.000000 -0x09 -0.500000 -12500.000000 -10.000000 -75000.000000 -0x00 -0x00 -0x03 -1 -0 -10 -0 --87 -0 -0 -0 -50000.000000 - - -32 -0xAA -1 -0 -0x00 -240 -1 -0x02 -32 -0x33553355 -1 -0x02 -0x08 -0x00 -0xC8 -0x01 -0x00 -0x3432 -0x3433 -0xFF -0 -0 -0 -0x2 -0xFFFFFFFF -0x20 -0 -0 -3 -0 -0 -0 -0 -86_A2_40_40_40_40_60_96_8E_6E_B4_AC_AC_61_3F_F0_3A_43_51_20_20_20_20_20_20_20_3A_54_65_73_74_7B_30_30_30_30_31 - - -32768.000000 -200.000000 -3.000000 -180.000000 -10 -3 -600.000000 -0.001495 -0.000458 -0.001923 - - -1 -0 -0 0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 - - - diff --git a/src/archive/app_ax5043_HDLC_tx/axradiolab_g3ruh.xml b/src/archive/app_ax5043_HDLC_tx/axradiolab_g3ruh.xml deleted file mode 100755 index 1397636e..00000000 --- a/src/archive/app_ax5043_HDLC_tx/axradiolab_g3ruh.xml +++ /dev/null @@ -1,287 +0,0 @@ - - - -0 -0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -0 -0 -1000.000000 -200 -0 -0 - - -0xA3 -0x00 -0 - - -0 -1 -1 -0 -0 -1 - - -0x01 -0x00 -0x01 -0x00 -0x00 -0x01 -0x07 -0x03 -0x01 -0x01 -0x01 -0x0 -0x0 - - -433920000.000000 -1 -0x00 -0x19 -0x02 -0x10 -0x09 -0x0B -1200.000000 -2200.000000 -48000000.000000 -867.840000 -
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-50000.000000 -0x08 -0.625000 -3000.000000 -10.000000 -14400.000000 -0x07 -0x00 -0x03 -1 -0 -10 -0 --93 -0 -0 -0 -11999.999520 - - -40 -0xAA -0 -0 -0xC0 -240 -1 -0x02 -32 -0x33553355 -0 -0x00 -0x00 -0x25 -0xC8 -0x00 -0x00 -0x3432 -0x3433 -0x0 -0 -0 -0 -0x2 -0xFFFFFFFF -0x20 -0 -0 -0 -0 -0 -0 -0 -86_A2_40_40_40_40_60_96_8E_6E_B4_AC_AC_61_3F_F0_3A_43_51_20_20_20_20_20_20_20_3A_54_65_73_74_7B_30_30_30_30_31 - - -32768.000000 -200.000000 -3.000000 -180.000000 -10 -3 -600.000000 -0.001495 -0.000458 -0.001923 - - -1 -0 -0 0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 -0 0 - - - diff --git a/src/archive/app_ax5043_HDLC_tx/conf/chconf.h b/src/archive/app_ax5043_HDLC_tx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_HDLC_tx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_HDLC_tx/conf/halconf.h b/src/archive/app_ax5043_HDLC_tx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_HDLC_tx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_HDLC_tx/conf/mcuconf.h b/src/archive/app_ax5043_HDLC_tx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_HDLC_tx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_HDLC_tx/main.c b/src/archive/app_ax5043_HDLC_tx/main.c deleted file mode 100644 index 8c9dfc13..00000000 --- a/src/archive/app_ax5043_HDLC_tx/main.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x32, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 0; -const uint8_t framing_counter_pos = 0; - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - -/* - uint8_t rx_buf[2]={0x00 ,0 }; - uint8_t command_buf[2] = {0x00 ,0x00 }; - - while (true) - { - //uint8_t command_buf[6]; - //uint8_t rx_bufi=0; - - //command_buf[0] = AD_READ_BLK_LADR; - - //command_buf[1] = (uint8_t) (AD_MISC_FW >> 24); - //command_buf[2] = (uint8_t) (AD_MISC_FW >> 16); - //command_buf[3] = (uint8_t) (AD_MISC_FW >> 8); - //command_buf[4] = (uint8_t) (AD_MISC_FW); - //ommand_buf[5] = 0; - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x --\r\n", AD_MISC_FW); - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x %x %x %x %x %x --\r\n", command_buf[0],command_buf[1],command_buf[2],command_buf[3],command_buf[4],command_buf[5]); - - spiSelect(&SPID2); - spiStartExchange(&SPID2, 2, command_buf, rx_buf); - while((SPID2).state != SPI_READY) { } - chprintf(DEBUG_CHP, "\r\r Sent to Radio-- 0x%x 0x%x --\r\n", command_buf[0],command_buf[1]); - chprintf(DEBUG_CHP, "\r\r Radio returned-- 0x%x 0x%x --\r\n", rx_buf[0],rx_buf[1]); - spiUnselect(&SPID2); - chThdSleepMilliseconds(500); - command_buf[0] = command_buf[0] +1; - - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } -*/ - //uint16_t reg=0; - uint8_t value=0; - uint8_t value1=0x55; - uint8_t ret_value[3]={0,0,0}; - //int i; - - - ax5043_read_reg(&SPID2, AX5043_REG_REV, value, ret_value); - chThdSleepMilliseconds(1500); - - - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_SCRATCH, value1, ret_value); - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - chThdSleepMilliseconds(1500); - - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - -/* - while(true) - { - - reg = 0x314; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = 0x314; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - value1 =value1+1; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r written reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value1,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - }*/ - - //ax5043_prepare_tx(&SPID2); - -/* - while(true) - { - //ax5043_prepare_tx(&SPID2); - chThdSleepMilliseconds(3000); - chprintf(DEBUG_CHP, "Writting FIFO\r\n"); - ax5043_transmit(&SPID2); - chThdSleepMilliseconds(1000); - ax5043_shutdown(&SPID2); - } -*/ - -/* - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x10, ret_value);//packet length - //ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x24, ret_value);//packet details like raw packet - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x08, ret_value);//packet details like raw packet - for (i=0;i<16;i++) - { - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//some random data - } - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit -*/ - //ax5043_transmit(&SPID2); - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending another packet...\r\n"); - transmit_packet(&SPID2, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(3000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_HDLC_tx/source/README.md b/src/archive/app_ax5043_HDLC_tx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_HDLC_tx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_HDLC_tx/source/ax5043.c b/src/archive/app_ax5043_HDLC_tx/source/ax5043.c deleted file mode 100644 index 1902a9a8..00000000 --- a/src/archive/app_ax5043_HDLC_tx/source/ax5043.c +++ /dev/null @@ -1,1273 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_phy_channelbusy = -87 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 184; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 72; -const uint8_t axradio_phy_preamble_byte = 0x7e; -const uint8_t axradio_phy_preamble_flags = 0x38; -const uint8_t axradio_phy_preamble_appendbits = 0; -const uint8_t axradio_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 3; -const uint8_t axradio_framing_addrlen = 1; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 0; -const uint8_t axradio_framing_lenmask = 0xff; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; -const uint8_t axradio_phy_innerfreqloop = 0; - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x--\r\n", command_buf[0],command_buf[1]); - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x--\r\n", ret_value[0],ret_value[1]); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x, [2]=0x%x--\r\n", command_buf[0],command_buf[1],command_buf[2]); - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x , [2]=0x%x--\r\n", ret_value[0],ret_value[1],ret_value[2]); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Writes to an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - //uint8_t return_val; - //int num_retries = 1; - //return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - ax5043_write_reg_spi(spip, reg, value, ret_value); - -/* - while (num_retries > 0 && return_val != 0x80) - { - chThdSleepMicroseconds(100); - return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - num_retries--; - //chprintf(DEBUG_CHP, "\r\r num_retries= %d --\r\n", num_retries); - }*/ - -} - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r spi read reg=0x%x, value=0x%x ret=0x%x %x--\r\n", command_buf[0],command_buf[1], ret_value[0],ret_value[1]); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r spi read reg=0x%x %x, value=0x%x ret=0x%x %x %x--\r\n", command_buf[0],command_buf[1],command_buf[2],ret_value[0],ret_value[1],ret_value[2]); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x15, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - chThdSleepMilliseconds(10); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - chThdSleepMilliseconds(10); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - chThdSleepMilliseconds(10); - - -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x32, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - //int num_retries; - //uint8_t pll_range_done = 0; - //uint8_t pll_range_after; - //uint8_t vcoi_save; - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); //reset is causing problems and hence disabling it.need to remove it - - //adding two more lines to diable the interrupts. Need to remove it later - //ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - //ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet. Not used in thsi version of code. - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_transmit(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - int i=0; - ax5043_full_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - //send out the preamble - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xE0, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //sync word - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xA1, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x18, ret_value);//sync flags - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - - -/* seems this will not get executed based on logic - //send out the preamble. again? - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //writting preamble based on address register. pretty weird. - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x41), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1C, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); -*/ - - //write MAC and packet - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0C, ret_value);//packet length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x03, ret_value);//packet details like raw packet - - - //length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0B, ret_value); - //address values - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x34, ret_value); - for (i=0;i<8;i++) - { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x36, ret_value);//some random data - } - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - -} - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit_isr \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - -uint8_t axradio_rxbuffer[256]; - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - - -uint8_t receive_loop(SPIDriver * spip) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown chunk in FIFO\r\n"); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // purge FIFO - } - while (--i); - break; - } - } - - chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - -//!@ - diff --git a/src/archive/app_ax5043_HDLC_tx/source/ax5043.h b/src/archive/app_ax5043_HDLC_tx/source/ax5043.h deleted file mode 100644 index 0f82d6bb..00000000 --- a/src/archive/app_ax5043_HDLC_tx/source/ax5043.h +++ /dev/null @@ -1,732 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_transmit(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; -uint8_t receive_loop(SPIDriver * spip); - -#endif -//! @} diff --git a/src/archive/app_ax5043_driver/Makefile b/src/archive/app_ax5043_driver/Makefile deleted file mode 100644 index bcf1683b..00000000 --- a/src/archive/app_ax5043_driver/Makefile +++ /dev/null @@ -1,208 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = hard -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_ax45043_driver - -# Target settings. -MCU = cortex-m4 -BOARD = ORESAT_C3_V3 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -#include $(PROJ_SRC)/oresat.mk -include $(PROJ_SRC)/si41xx.mk -include $(PROJ_SRC)/ax5043.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk -include $(CHIBIOS)/os/various/shell/shell.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DSHELL_CONFIG_FILE -DAX5043_SHARED_SPI -DSI41XX_DEVICE=SI4112 - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_ax5043_driver/README.md b/src/archive/app_ax5043_driver/README.md deleted file mode 100644 index 8befef31..00000000 --- a/src/archive/app_ax5043_driver/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_ax45043_driver - -This is used to transmit ax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This in TX mode pairs with " app_ax5043_engr_rx ". The sent and received packet numbers are shown in serial terminal. - diff --git a/src/archive/app_ax5043_driver/Supporting_Py/ax5043_config_str.txt b/src/archive/app_ax5043_driver/Supporting_Py/ax5043_config_str.txt deleted file mode 100644 index 914f7a0e..00000000 --- a/src/archive/app_ax5043_driver/Supporting_Py/ax5043_config_str.txt +++ /dev/null @@ -1,280 +0,0 @@ -AX5043_REV -AX5043_SCRATCH -AX5043_PWRMODE -AX5043_POWSTAT -AX5043_POWSTICKYSTAT -AX5043_POWIRQMASK -AX5043_IRQMASK1 -AX5043_IRQMASK0 -AX5043_RADIOEVENTMASK1 -AX5043_RADIOEVENTMASK0 -AX5043_IRQREQUEST1 -AX5043_IRQREQUEST0 -AX5043_RADIOEVENTREQ1 -AX5043_RADIOEVENTREQ0 -AX5043_MODULATION -AX5043_ENCODING -AX5043_FRAMING -AX5043_CRCINIT3 -AX5043_CRCINIT2 -AX5043_CRCINIT1 -AX5043_CRCINIT0 -AX5043_FEC -AX5043_FECSYNC -AX5043_FECSTATUS -AX5043_RADIOSTATE -AX5043_XTALSTATUS -AX5043_PINSTATE -AX5043_PINFUNCSYSCLK -AX5043_PINFUNCDCLK -AX5043_PINFUNCDATA -AX5043_PINFUNCIRQ -AX5043_PINFUNCANTSEL -AX5043_PINFUNCPWRAMP -AX5043_PWRAMP -AX5043_FIFOSTAT -AX5043_FIFODATA -AX5043_FIFOCOUNT1 -AX5043_FIFOCOUNT0 -AX5043_FIFOFREE1 -AX5043_FIFOFREE0 -AX5043_FIFOTHRESH1 -AX5043_FIFOTHRESH0 -AX5043_PLLLOOP -AX5043_PLLCPI -AX5043_PLLVCODIV -AX5043_PLLRANGINGA -AX5043_FREQA3 -AX5043_FREQA2 -AX5043_FREQA1 -AX5043_FREQA0 -AX5043_PLLLOOPBOOST -AX5043_PLLCPIBOOST -AX5043_PLLRANGINGB -AX5043_FREQB3 -AX5043_FREQB2 -AX5043_FREQB1 -AX5043_FREQB0 -AX5043_RSSI -AX5043_BGNDRSSI -AX5043_DIVERSITY -AX5043_AGCCOUNTER -AX5043_TRKDATARATE2 -AX5043_TRKDATARATE1 -AX5043_TRKDATARATE0 -AX5043_TRKAMPL1 -AX5043_TRKAMPL0 -AX5043_TRKPHASE1 -AX5043_TRKPHASE0 -AX5043_TRKRFFREQ2 -AX5043_TRKRFFREQ1 -AX5043_TRKRFFREQ0 -AX5043_TRKFREQ1 -AX5043_TRKFREQ0 -AX5043_TRKFSKDEMOD1 -AX5043_TRKFSKDEMOD0 -AX5043_TIMER2 -AX5043_TIMER1 -AX5043_TIMER0 -AX5043_WAKEUPTIMER1 -AX5043_WAKEUPTIMER0 -AX5043_WAKEUP1 -AX5043_WAKEUP0 -AX5043_WAKEUPFREQ1 -AX5043_WAKEUPFREQ0 -AX5043_WAKEUPXOEARLY -AX5043_IFFREQ1 -AX5043_IFFREQ0 -AX5043_DECIMATION -AX5043_RXDATARATE2 -AX5043_RXDATARATE1 -AX5043_RXDATARATE0 -AX5043_MAXDROFFSET2 -AX5043_MAXDROFFSET1 -AX5043_MAXDROFFSET0 -AX5043_MAXRFOFFSET2 -AX5043_MAXRFOFFSET1 -AX5043_MAXRFOFFSET0 -AX5043_FSKDMAX1 -AX5043_FSKDMAX0 -AX5043_FSKDMIN1 -AX5043_FSKDMIN0 -AX5043_AFSKSPACE1 -AX5043_AFSKSPACE0 -AX5043_AFSKMARK1 -AX5043_AFSKMARK0 -AX5043_AFSKCTRL -AX5043_AMPLFILTER -AX5043_FREQUENCYLEAK -AX5043_RXPARAMSETS -AX5043_RXPARAMCURSET -AX5043_AGCGAIN0 -AX5043_AGCTARGET0 -AX5043_AGCAHYST0 -AX5043_AGCMINMAX0 -AX5043_TIMEGAIN0 -AX5043_DRGAIN0 -AX5043_PHASEGAIN0 -AX5043_FREQUENCYGAINA0 -AX5043_FREQUENCYGAINB0 -AX5043_FREQUENCYGAINC0 -AX5043_FREQUENCYGAIND0 -AX5043_AMPLITUDEGAIN0 -AX5043_FREQDEV10 -AX5043_FREQDEV00 -AX5043_FOURFSK0 -AX5043_BBOFFSRES0 -AX5043_AGCGAIN1 -AX5043_AGCTARGET1 -AX5043_AGCAHYST1 -AX5043_AGCMINMAX1 -AX5043_TIMEGAIN1 -AX5043_DRGAIN1 -AX5043_PHASEGAIN1 -AX5043_FREQUENCYGAINA1 -AX5043_FREQUENCYGAINB1 -AX5043_FREQUENCYGAINC1 -AX5043_FREQUENCYGAIND1 -AX5043_AMPLITUDEGAIN1 -AX5043_FREQDEV11 -AX5043_FREQDEV01 -AX5043_FOURFSK1 -AX5043_BBOFFSRES1 -AX5043_AGCGAIN2 -AX5043_AGCTARGET2 -AX5043_AGCAHYST2 -AX5043_AGCMINMAX2 -AX5043_TIMEGAIN2 -AX5043_DRGAIN2 -AX5043_PHASEGAIN2 -AX5043_FREQGAINA2 -AX5043_FREQGAINB2 -AX5043_FREQGAINC2 -AX5043_FREQGAIND2 -AX5043_AMPLGAIN2 -AX5043_FREQDEV12 -AX5043_FREQDEV02 -AX5043_FOURFSK2 -AX5043_BBOFFSRES2 -AX5043_AGCGAIN3 -AX5043_AGCTARGET3 -AX5043_AGCAHYST3 -AX5043_AGCMINMAX3 -AX5043_TIMEGAIN3 -AX5043_DRGAIN3 -AX5043_PHASEGAIN3 -AX5043_FREQUENCYGAINA3 -AX5043_FREQUENCYGAINB3 -AX5043_FREQUENCYGAINC3 -AX5043_FREQUENCYGAIND3 -AX5043_AMPLITUDEGAIN3 -AX5043_FREQDEV13 -AX5043_FREQDEV03 -AX5043_FOURFSK3 -AX5043_BBOFFSRES3 -AX5043_MODCFGF -AX5043_FSKDEV2 -AX5043_FSKDEV1 -AX5043_FSKDEV0 -AX5043_MODCFGA -AX5043_TXRATE2 -AX5043_TXRATE1 -AX5043_TXRATE0 -AX5043_TXPWRCOEFFA1 -AX5043_TXPWRCOEFFA0 -AX5043_TXPWRCOEFFB1 -AX5043_TXPWRCOEFFB0 -AX5043_TXPWRCOEFFC1 -AX5043_TXPWRCOEFFC0 -AX5043_TXPWRCOEFFD1 -AX5043_TXPWRCOEFFD0 -AX5043_TXPWRCOEFFE1 -AX5043_TXPWRCOEFFE0 -AX5043_PLLVCOI -AX5043_PLLVCOIR -AX5043_PLLLOCKDET -AX5043_PLLRNGCLK -AX5043_XTALCAP -AX5043_BBTUNE -AX5043_BBOFFSCAP -AX5043_PKTADDRCFG -AX5043_PKTLENCFG -AX5043_PKTLENOFFSET -AX5043_PKTMAXLEN -AX5043_PKTADDR3 -AX5043_PKTADDR2 -AX5043_PKTADDR1 -AX5043_PKTADDR0 -AX5043_PKTADDRMASK3 -AX5043_PKTADDRMASK2 -AX5043_PKTADDRMASK1 -AX5043_PKTADDRMASK0 -AX5043_MATCH0PAT3 -AX5043_MATCH0PAT2 -AX5043_MATCH0PAT1 -AX5043_MATCH0PAT0 -AX5043_MATCH0LEN -AX5043_MATCH0MIN -AX5043_MATCH0MAX -AX5043_MATCH1PAT1 -AX5043_MATCH1PAT0 -AX5043_MATCH1LEN -AX5043_MATCH1MIN -AX5043_MATCH1MAX -AX5043_TMGTXBOOST -AX5043_TMGTXSETTLE -AX5043_TMGRXBOOST -AX5043_TMGRXSETTLE -AX5043_TMGRXOFFSACQ -AX5043_TMGRXCOARSEAGC -AX5043_TMGRXAGC -AX5043_TMGRXRSSI -AX5043_TMGRXPREAMBLE1 -AX5043_TMGRXPREAMBLE2 -AX5043_TMGRXPREAMBLE3 -AX5043_RSSIREFERENCE -AX5043_RSSIABSTHR -AX5043_BGNDRSSIGAIN -AX5043_BGNDRSSITHR -AX5043_PKTCHUNKSIZE -AX5043_PKTMISCFLAGS -AX5043_PKTSTOREFLAGS -AX5043_PKTACCEPTFLAGS -AX5043_GPADCCTRL -AX5043_GPADCPERIOD -AX5043_GPADC13VALUE1 -AX5043_GPADC13VALUE0 -AX5043_LPOSCCONFIG -AX5043_LPOSCSTATUS -AX5043_LPOSCKFILT1 -AX5043_LPOSCKFILT0 -AX5043_LPOSCREF1 -AX5043_LPOSCREF0 -AX5043_LPOSCFREQ1 -AX5043_LPOSCFREQ0 -AX5043_LPOSCPER1 -AX5043_LPOSCPER0 -AX5043_DACVALUE1 -AX5043_DACVALUE0 -AX5043_DACCONFIG -AX5043_REF -AX5043_0xF00 -AX5043_0xF0C -AX5043_0xF0D -AX5043_XTALOSC -AX5043_XTALAMPL -AX5043_0xF1C -AX5043_0xF18 -AX5043_0xF21 -AX5043_0xF22 -AX5043_0xF23 -AX5043_0xF26 -AX5043_0xF30 -AX5043_0xF31 -AX5043_0xF32 -AX5043_0xF33 -AX5043_0xF34 -AX5043_0xF35 -AX5043_0xF44 -AX5043_0xF72 -AX5043_XTALDIV \ No newline at end of file diff --git a/src/archive/app_ax5043_driver/Supporting_Py/xml_to_csv.py b/src/archive/app_ax5043_driver/Supporting_Py/xml_to_csv.py deleted file mode 100644 index 07298dfe..00000000 --- a/src/archive/app_ax5043_driver/Supporting_Py/xml_to_csv.py +++ /dev/null @@ -1,36 +0,0 @@ -# -*- coding: utf-8 -*- -""" -Created on Fri Oct 4 14:29:50 2019 - -@author: MALADAS -""" - -import xml.etree.ElementTree as ET -import csv - -#Open config xml -tree = ET.parse("sample_config.xml") -root = tree.getroot() - -#Open structure of config -f= open("ax5043_config_str.txt","r") -regnames = f.readlines() - -# open a file for writing reg values -reg_data = open('ax5043_regs.csv', 'w') -csvwriter = csv.writer(reg_data) - -regs = [] - - -for reg in regnames: - try: - value = root.find(reg.strip()).text - regs.append(value) - except: - regs.append(0x00) - - - -csvwriter.writerow(regs) -reg_data.close() \ No newline at end of file diff --git a/src/archive/app_ax5043_driver/cfg/CO_driver_custom.h b/src/archive/app_ax5043_driver/cfg/CO_driver_custom.h deleted file mode 100644 index 7bbd300e..00000000 --- a/src/archive/app_ax5043_driver/cfg/CO_driver_custom.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_SDO_CLI_ENABLE | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL | \ - CO_CONFIG_FLAG_CALLBACK_PRE | \ - CO_CONFIG_FLAG_TIMERNEXT | \ - CO_CONFIG_FLAG_OD_DYNAMIC) - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_FLAG_CALLBACK_PRE | \ - CO_CONFIG_FLAG_TIMERNEXT | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/archive/app_ax5043_driver/cfg/chconf.h b/src/archive/app_ax5043_driver/cfg/chconf.h deleted file mode 100644 index 53dfa662..00000000 --- a/src/archive/app_ax5043_driver/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_driver/cfg/halconf.h b/src/archive/app_ax5043_driver/cfg/halconf.h deleted file mode 100644 index 48198c04..00000000 --- a/src/archive/app_ax5043_driver/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS TRUE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_LINE -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_driver/cfg/mcuconf.h b/src/archive/app_ax5043_driver/cfg/mcuconf.h deleted file mode 100644 index 1e200710..00000000 --- a/src/archive/app_ax5043_driver/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 16 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 8 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 8 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSE -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_driver/main.c b/src/archive/app_ax5043_driver/main.c deleted file mode 100644 index 1789f042..00000000 --- a/src/archive/app_ax5043_driver/main.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" -#include "shell.h" - -/* Project header files */ -#include "cmd.h" - -/** - * @brief App Initialization - */ -static void app_init(void) -{ - /* Initialize shell and start serial interface */ - shellInit(); - sdStart(&SD3, NULL); -} - -/** - * @brief Main Application - */ -int main(void) -{ - halInit(); - chSysInit(); - - // Initialize and start - app_init(); - - /* Initialize shell worker thread */ - chThdCreateStatic(cmd_wa, sizeof(cmd_wa), NORMALPRIO, cmd, NULL); - - while (true) { - palToggleLine(LINE_WDT); - chThdSleepMilliseconds(250); - } - return 0; -} diff --git a/src/archive/app_ax5043_driver/main_ax25_rx.c b/src/archive/app_ax5043_driver/main_ax25_rx.c deleted file mode 100644 index 9ccef7a3..00000000 --- a/src/archive/app_ax5043_driver/main_ax25_rx.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x32, 0x34, 0x00, 0x00} -}; - -/* -const struct axradio_address_mask localaddr_tx = { - { 0x33, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; -*/ -// TX: fcarrier=435.500MHz dev= 3.200kHz br= 9.600kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 14.400kHz br= 9.600kBit/s -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08,common}, - {AX5043_REG_ENCODING, 0x07,common}, - {AX5043_REG_FRAMING, 0x14,common}, - {AX5043_REG_CRCINIT3, 0x00,common}, - {AX5043_REG_CRCINIT2, 0x00,common}, - {AX5043_REG_CRCINIT1, 0xFF,common}, - {AX5043_REG_CRCINIT0, 0xFF,common}, - {AX5043_REG_PINFUNCSYSCLK, 0x01,common}, - {AX5043_REG_PINFUNCDCLK, 0x01,common}, - {AX5043_REG_PINFUNCDATA, 0x01,common}, - {AX5043_REG_PINFUNCANTSEL, 0x01,common}, - {AX5043_REG_PINFUNCPWRAMP, 0x07,common}, - {AX5043_REG_WAKEUPXOEARLY, 0x01,common}, - {AX5043_REG_IFFREQ1, 0x02,common}, - {AX5043_REG_IFFREQ0, 0x0C,common}, - {AX5043_REG_DECIMATION, 0x14,common}, - {AX5043_REG_RXDATARATE2, 0x00,common}, - {AX5043_REG_RXDATARATE1, 0x3E,common}, - {AX5043_REG_RXDATARATE0, 0x80,common}, - {AX5043_REG_MAXDROFFSET2, 0x00,common}, - {AX5043_REG_MAXDROFFSET1, 0x00,common}, - {AX5043_REG_MAXDROFFSET0, 0x00,common}, - {AX5043_REG_MAXRFOFFSET2, 0x80,common}, - {AX5043_REG_MAXRFOFFSET1, 0x01,common}, - {AX5043_REG_MAXRFOFFSET0, 0x2F,common}, - {AX5043_REG_FSKDMAX1, 0x00,common}, - {AX5043_REG_FSKDMAX0, 0xA6,common}, - {AX5043_REG_FSKDMIN1, 0xFF,common}, - {AX5043_REG_FSKDMIN0, 0x5A,common}, - {AX5043_REG_AMPLFILTER, 0x00,common}, - {AX5043_REG_RXPARAMSETS, 0xF4,common}, - {AX5043_REG_AGCGAIN0, 0xC5,common}, - {AX5043_REG_AGCTARGET0, 0x84,common}, - {AX5043_REG_TIMEGAIN0, 0xF8,common}, - {AX5043_REG_DRGAIN0, 0xF2,common}, - {AX5043_REG_PHASEGAIN0, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA0,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB0,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC0,0x0A,common}, - {AX5043_REG_FREQUENCYGAIND0,0x0A,common}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06,common}, - {AX5043_REG_FREQDEV10, 0x00,common}, - {AX5043_REG_FREQDEV00, 0x00,common}, - {AX5043_REG_BBOFFSRES0, 0x00,common}, - {AX5043_REG_AGCGAIN1, 0xC5,common}, - {AX5043_REG_AGCTARGET1, 0x84,common}, - {AX5043_REG_AGCAHYST1, 0x00,common}, - {AX5043_REG_AGCMINMAX1, 0x00,common}, - {AX5043_REG_TIMEGAIN1, 0xF6,common}, - {AX5043_REG_DRGAIN1, 0xF1,common}, - {AX5043_REG_PHASEGAIN1, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA1,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB1,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC1,0x0A,common}, - {AX5043_REG_FREQUENCYGAIND1,0x0A,common}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06,common}, - {AX5043_REG_FREQDEV11, 0x00,common}, - {AX5043_REG_FREQDEV01, 0x25,common}, - {AX5043_REG_FOURFSK1, 0x16,common}, - {AX5043_REG_BBOFFSRES1, 0x00,common}, - {AX5043_REG_AGCGAIN3, 0xFF,common}, - {AX5043_REG_AGCTARGET3, 0x84,common}, - {AX5043_REG_AGCAHYST3, 0x00,common}, - {AX5043_REG_AGCMINMAX3, 0x00,common}, - {AX5043_REG_TIMEGAIN3, 0xF5,common}, - {AX5043_REG_DRGAIN3, 0xF0,common}, - {AX5043_REG_PHASEGAIN3, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA3,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB3,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC3,0x0D,common}, - {AX5043_REG_FREQUENCYGAIND3,0x0D,common}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06,common}, - {AX5043_REG_FREQDEV13, 0x00,common}, - {AX5043_REG_FREQDEV03, 0x25,common}, - {AX5043_REG_FOURFSK3, 0x16,common}, - {AX5043_REG_BBOFFSRES3, 0x00,common}, - {AX5043_REG_MODCFGF, 0x02,common}, - {AX5043_REG_FSKDEV2, 0x00,common}, - {AX5043_REG_FSKDEV1, 0x04,common}, - {AX5043_REG_FSKDEV0, 0x5E,common}, - {AX5043_REG_MODCFGA, 0x05,common}, - {AX5043_REG_TXRATE2, 0x00,common}, - {AX5043_REG_TXRATE1, 0x0D,common}, - {AX5043_REG_TXRATE0, 0x1B,common}, - {AX5043_REG_TXPWRCOEFFB1, 0x07,common}, - {AX5043_REG_TXPWRCOEFFB0, 0x00,common}, - {AX5043_REG_PLLVCOI, 0x99,common}, - {AX5043_REG_PLLRNGCLK, 0x05,common}, - {AX5043_REG_BBTUNE, 0x0F,common}, - {AX5043_REG_BBOFFSCAP, 0x77,common}, - {AX5043_REG_PKTADDRCFG, 0x00,common}, - {AX5043_REG_PKTLENCFG, 0x00,common}, - {AX5043_REG_PKTLENOFFSET, 0x15,common}, - {AX5043_REG_PKTMAXLEN, 0xF0,common}, - {AX5043_REG_MATCH0PAT3, 0xAA,common}, - {AX5043_REG_MATCH0PAT2, 0xCC,common}, - {AX5043_REG_MATCH0PAT1, 0xAA,common}, - {AX5043_REG_MATCH0PAT0, 0xCC,common}, - {AX5043_REG_MATCH1PAT1, 0x55,common}, - {AX5043_REG_MATCH1PAT0, 0x55,common}, - {AX5043_REG_MATCH1LEN, 0x0A,common}, - {AX5043_REG_MATCH1MAX, 0x0A,common}, - {AX5043_REG_TMGTXBOOST, 0x5B,common}, - {AX5043_REG_TMGTXSETTLE, 0x3E,common}, - {AX5043_REG_TMGRXOFFSACQ, 0x00,common}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C,common}, - {AX5043_REG_TMGRXRSSI, 0x03,common}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17,common}, - {AX5043_REG_RSSIABSTHR, 0xE3,common}, - {AX5043_REG_BGNDRSSITHR, 0x00,common}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D,common}, - {AX5043_REG_PKTACCEPTFLAGS, 0x39,common}, - {AX5043_REG_DACVALUE1, 0x00,common}, - {AX5043_REG_DACVALUE0, 0x00,common}, - {AX5043_REG_DACCONFIG, 0x00,common}, - {AX5043_REG_REF, 0x03,common}, - {AX5043_REG_XTALOSC, 0x04,common}, - {AX5043_REG_XTALAMPL, 0x00,common}, - {AX5043_REG_0xF1C, 0x07,common}, - {AX5043_REG_0xF21, 0x68,common}, - {AX5043_REG_0xF22, 0XFF,common}, - {AX5043_REG_0xF23, 0x84,common}, - {AX5043_REG_0xF26, 0x98,common}, - {AX5043_REG_0xF34, 0x28,common}, - {AX5043_REG_0xF35, 0x11,common}, - {AX5043_REG_0xF44, 0x25,common}, - {AX5043_REG_PINFUNCIRQ, 0x03,common}, - {AX5043_REG_PKTSTOREFLAGS, 0x14,common}, - {AX5043_REG_PLLLOOP, 0x09,tx}, - {AX5043_REG_PLLCPI, 0x02,tx}, - {AX5043_REG_PLLVCODIV, 0x24,tx}, - {AX5043_REG_XTALCAP, 0x00,tx}, - {AX5043_REG_0xF00, 0x0F,tx}, - {AX5043_REG_0xF18, 0x06,tx}, - {AX5043_REG_PLLLOOP, 0x0B,rx}, - {AX5043_REG_PLLCPI, 0x10,rx}, - {AX5043_REG_PLLVCODIV, 0x25,rx}, - {AX5043_REG_XTALCAP, 0x00,rx}, - {AX5043_REG_0xF00, 0x0F,rx}, - {AX5043_REG_0xF18, 0x02,rx}, - {AX5043_REG_TMGRXAGC, 0x00,rx_cont}, - {AX5043_REG_TMGRXPREAMBLE1, 0x00,rx_cont}, - {AX5043_REG_PKTMISCFLAGS, 0x00,rx_cont}, - {AX5043_REG_PKTADDR0, 0x00,local_address}, - {AX5043_REG_PKTADDR1, 0x00,local_address}, - {AX5043_REG_PKTADDR2, 0x00,local_address}, - {AX5043_REG_PKTADDR3, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK0, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK1, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK2, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK3, 0x00,local_address}, - {AX5043_REG_END, 0x00,common} -}; - - -ax5043_confval_t conf_values[]={ - {AXRADIO_PHY_PN9 ,0}, - {AXRADIO_PHY_NRCHANNELS ,1}, - {AXRADIO_PHY_CHANFREQ ,0X0912AAAB }, - {AXRADIO_PHY_CHANPLLRNGINIT ,0X0A }, - {AXRADIO_PHY_CHANVCOIINIT ,0X98}, - {AXRADIO_PHY_CHANPLLRNG ,0}, - {AXRADIO_PHY_CHANVCOI ,0}, - {AXRADIO_PHY_VCOCALIB ,0}, - {AXRADIO_PHY_MAXFREQOFFSET ,913}, - {AXRADIO_PHY_RSSIOFFSET ,64}, - {AXRADIO_PHY_RSSIREFERENCE ,313}, - {AXRADIO_PHY_CHANNELBUSY ,-23}, - {AXRADIO_PHY_CS_PERIOD ,7}, - {AXRADIO_PHY_CS_ENABLED ,0}, - {AXRADIO_PHY_LBT_RETRIES ,0}, - {AXRADIO_PHY_LBT_FORCETX ,0}, - {AXRADIO_PHY_PREAMBLE_WOR_LONGLEN ,9}, - {AXRADIO_PHY_PREAMBLE_WOR_LEN ,40}, - {AXRADIO_PHY_PREAMBLE_LONGLEN ,0}, - {AXRADIO_PHY_PREAMBLE_LEN ,40}, - {AXRADIO_PHY_PREAMBLE_BYTE ,0X7E}, - {AXRADIO_PHY_PREAMBLE_FLAGS ,0X18}, - {AXRADIO_PHY_PREAMBLE_APPENDBITS ,0}, - {AXRADIO_PHY_PREAMBLE_APPENDPATTERN ,0X00}, - {AXRADIO_FRAMING_MACLEN ,0}, - {AXRADIO_FRAMING_ADDRLEN ,0}, - {AXRADIO_FRAMING_DESTADDRPOS ,0}, - {AXRADIO_FRAMING_SOURCEADDRPOS ,0XFF}, - {AXRADIO_FRAMING_LENPOS ,0}, - {AXRADIO_FRAMING_LENOFFS ,21}, - {AXRADIO_FRAMING_LENMASK ,0X00}, - {AXRADIO_FRAMING_SWCRCLEN ,0}, - {AXRADIO_FRAMING_SYNCLEN ,32}, - {AXRADIO_FRAMING_SYNCWORD0 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD1 ,0XAA}, - {AXRADIO_FRAMING_SYNCWORD2 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD3 ,0XAA}, - {AXRADIO_FRAMING_SYNCFLAGS ,0X18}, - {AXRADIO_FRAMING_ENABLE_SFDCALLBACK ,0}, - {AXRADIO_FRAMING_ACK_TIMEOUT ,8}, - {AXRADIO_FRAMING_ACK_DELAY ,313}, - {AXRADIO_FRAMING_ACK_RETRANSMISSIONS ,0}, - {AXRADIO_FRAMING_ACK_SEQNRPOS ,0XFF}, - {AXRADIO_FRAMING_MINPAYLOADLEN ,0}, - {AXRADIO_WOR_PERIOD ,128}, - {AXRADIO_PHY_INNERFREQLOOP ,0}, - {AXRADIO_PHY_END ,0} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; - - -//Radio driver configurations - -static AX5043Config axcfg1 = -{ - &SPID2, - LINE_SX_INT0, - reg_values, - conf_values, - AX5043_MODE_RX, - &radio1_rx_mb -}; -AX5043Driver axd1; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - - // Creating the mailboxes. - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - - //initiating radio driver - ax5043ObjectInit(&axd1); - ax5043Start(&axd1, &axcfg1); -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - uint8_t packet_len=0; - //uint8_t ret_value[3]={0,0,0}; - - /* Enabling events on both edges of the button line.*/ - //palEnableLineEvent(LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE); - palEnableLineEvent(LINE_SX_INT0, PAL_EVENT_MODE_RISING_EDGE); - - - while(true) - { - //palWaitLineTimeout(LINE_BUTTON, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_MS2I(5000)); - - palWaitLineTimeout(LINE_SX_INT0, TIME_MS2I(5000)); - - if (palReadLine(LINE_SX_INT0)) - chprintf(DEBUG_CHP, "\r\r INFO: interrupt happened ** \r\n"); - else - chprintf(DEBUG_CHP, "\r\r INFO: interrupt timeout** \r\n"); - - packet_len=receive_loop(&axd1, axradio_rxbuffer); - //chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x\r\n", axd1.rf_freq_off3, axd1.rf_freq_off2, axd1.rf_freq_off1); - //chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)axd1.rssi); - if(packet_len > 0) - chprintf(DEBUG_CHP,"INFO: Received packet %d\r\n",axradio_rxbuffer[3]); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_driver/main_ax25_tx.c b/src/archive/app_ax5043_driver/main_ax25_tx.c deleted file mode 100644 index fd904ef3..00000000 --- a/src/archive/app_ax5043_driver/main_ax25_tx.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; - -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3E, 0x54, 0x65, 0x73, 0x74 }; -const uint8_t framing_insert_counter = 0; -const uint8_t framing_counter_pos = 0; - -// TX: fcarrier=435.500MHz dev= 3.200kHz br= 9.600kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 14.400kHz br= 9.600kBit/s -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08,common}, - {AX5043_REG_ENCODING, 0x07,common}, - {AX5043_REG_FRAMING, 0x14,common}, - {AX5043_REG_CRCINIT3, 0x00,common}, - {AX5043_REG_CRCINIT2, 0x00,common}, - {AX5043_REG_CRCINIT1, 0xFF,common}, - {AX5043_REG_CRCINIT0, 0xFF,common}, - {AX5043_REG_PINFUNCSYSCLK, 0x01,common}, - {AX5043_REG_PINFUNCDCLK, 0x01,common}, - {AX5043_REG_PINFUNCDATA, 0x01,common}, - {AX5043_REG_PINFUNCANTSEL, 0x01,common}, - {AX5043_REG_PINFUNCPWRAMP, 0x07,common}, - {AX5043_REG_WAKEUPXOEARLY, 0x01,common}, - {AX5043_REG_IFFREQ1, 0x02,common}, - {AX5043_REG_IFFREQ0, 0x0C,common}, - {AX5043_REG_DECIMATION, 0x14,common}, - {AX5043_REG_RXDATARATE2, 0x00,common}, - {AX5043_REG_RXDATARATE1, 0x3E,common}, - {AX5043_REG_RXDATARATE0, 0x80,common}, - {AX5043_REG_MAXDROFFSET2, 0x00,common}, - {AX5043_REG_MAXDROFFSET1, 0x00,common}, - {AX5043_REG_MAXDROFFSET0, 0x00,common}, - {AX5043_REG_MAXRFOFFSET2, 0x80,common}, - {AX5043_REG_MAXRFOFFSET1, 0x01,common}, - {AX5043_REG_MAXRFOFFSET0, 0x2F,common}, - {AX5043_REG_FSKDMAX1, 0x00,common}, - {AX5043_REG_FSKDMAX0, 0xA6,common}, - {AX5043_REG_FSKDMIN1, 0xFF,common}, - {AX5043_REG_FSKDMIN0, 0x5A,common}, - {AX5043_REG_AMPLFILTER, 0x00,common}, - {AX5043_REG_RXPARAMSETS, 0xF4,common}, - {AX5043_REG_AGCGAIN0, 0xC5,common}, - {AX5043_REG_AGCTARGET0, 0x84,common}, - {AX5043_REG_TIMEGAIN0, 0xF8,common}, - {AX5043_REG_DRGAIN0, 0xF2,common}, - {AX5043_REG_PHASEGAIN0, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA0,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB0,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC0,0x0A,common}, - {AX5043_REG_FREQUENCYGAIND0,0x0A,common}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06,common}, - {AX5043_REG_FREQDEV10, 0x00,common}, - {AX5043_REG_FREQDEV00, 0x00,common}, - {AX5043_REG_BBOFFSRES0, 0x00,common}, - {AX5043_REG_AGCGAIN1, 0xC5,common}, - {AX5043_REG_AGCTARGET1, 0x84,common}, - {AX5043_REG_AGCAHYST1, 0x00,common}, - {AX5043_REG_AGCMINMAX1, 0x00,common}, - {AX5043_REG_TIMEGAIN1, 0xF6,common}, - {AX5043_REG_DRGAIN1, 0xF1,common}, - {AX5043_REG_PHASEGAIN1, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA1,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB1,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC1,0x0A,common}, - {AX5043_REG_FREQUENCYGAIND1,0x0A,common}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06,common}, - {AX5043_REG_FREQDEV11, 0x00,common}, - {AX5043_REG_FREQDEV01, 0x25,common}, - {AX5043_REG_FOURFSK1, 0x16,common}, - {AX5043_REG_BBOFFSRES1, 0x00,common}, - {AX5043_REG_AGCGAIN3, 0xFF,common}, - {AX5043_REG_AGCTARGET3, 0x84,common}, - {AX5043_REG_AGCAHYST3, 0x00,common}, - {AX5043_REG_AGCMINMAX3, 0x00,common}, - {AX5043_REG_TIMEGAIN3, 0xF5,common}, - {AX5043_REG_DRGAIN3, 0xF0,common}, - {AX5043_REG_PHASEGAIN3, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA3,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB3,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC3,0x0D,common}, - {AX5043_REG_FREQUENCYGAIND3,0x0D,common}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06,common}, - {AX5043_REG_FREQDEV13, 0x00,common}, - {AX5043_REG_FREQDEV03, 0x25,common}, - {AX5043_REG_FOURFSK3, 0x16,common}, - {AX5043_REG_BBOFFSRES3, 0x00,common}, - {AX5043_REG_MODCFGF, 0x02,common}, - {AX5043_REG_FSKDEV2, 0x00,common}, - {AX5043_REG_FSKDEV1, 0x04,common}, - {AX5043_REG_FSKDEV0, 0x5E,common}, - {AX5043_REG_MODCFGA, 0x05,common}, - {AX5043_REG_TXRATE2, 0x00,common}, - {AX5043_REG_TXRATE1, 0x0D,common}, - {AX5043_REG_TXRATE0, 0x1B,common}, - {AX5043_REG_TXPWRCOEFFB1, 0x07,common}, - {AX5043_REG_TXPWRCOEFFB0, 0x00,common}, - {AX5043_REG_PLLVCOI, 0x99,common}, - {AX5043_REG_PLLRNGCLK, 0x05,common}, - {AX5043_REG_BBTUNE, 0x0F,common}, - {AX5043_REG_BBOFFSCAP, 0x77,common}, - {AX5043_REG_PKTADDRCFG, 0x00,common}, - {AX5043_REG_PKTLENCFG, 0x00,common}, - {AX5043_REG_PKTLENOFFSET, 0x15,common}, - {AX5043_REG_PKTMAXLEN, 0xF0,common}, - {AX5043_REG_MATCH0PAT3, 0xAA,common}, - {AX5043_REG_MATCH0PAT2, 0xCC,common}, - {AX5043_REG_MATCH0PAT1, 0xAA,common}, - {AX5043_REG_MATCH0PAT0, 0xCC,common}, - {AX5043_REG_MATCH1PAT1, 0x55,common}, - {AX5043_REG_MATCH1PAT0, 0x55,common}, - {AX5043_REG_MATCH1LEN, 0x0A,common}, - {AX5043_REG_MATCH1MAX, 0x0A,common}, - {AX5043_REG_TMGTXBOOST, 0x5B,common}, - {AX5043_REG_TMGTXSETTLE, 0x3E,common}, - {AX5043_REG_TMGRXOFFSACQ, 0x00,common}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C,common}, - {AX5043_REG_TMGRXRSSI, 0x03,common}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17,common}, - {AX5043_REG_RSSIABSTHR, 0xE3,common}, - {AX5043_REG_BGNDRSSITHR, 0x00,common}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D,common}, - {AX5043_REG_PKTACCEPTFLAGS, 0x39,common}, - {AX5043_REG_DACVALUE1, 0x00,common}, - {AX5043_REG_DACVALUE0, 0x00,common}, - {AX5043_REG_DACCONFIG, 0x00,common}, - {AX5043_REG_REF, 0x03,common}, - {AX5043_REG_XTALOSC, 0x04,common}, - {AX5043_REG_XTALAMPL, 0x00,common}, - {AX5043_REG_0xF1C, 0x07,common}, - {AX5043_REG_0xF21, 0x68,common}, - {AX5043_REG_0xF22, 0XFF,common}, - {AX5043_REG_0xF23, 0x84,common}, - {AX5043_REG_0xF26, 0x98,common}, - {AX5043_REG_0xF34, 0x28,common}, - {AX5043_REG_0xF35, 0x11,common}, - {AX5043_REG_0xF44, 0x25,common}, - {AX5043_REG_PINFUNCIRQ, 0x03,common}, - {AX5043_REG_PKTSTOREFLAGS, 0x14,common}, - {AX5043_REG_PLLLOOP, 0x09,tx}, - {AX5043_REG_PLLCPI, 0x02,tx}, - {AX5043_REG_PLLVCODIV, 0x24,tx}, - {AX5043_REG_XTALCAP, 0x00,tx}, - {AX5043_REG_0xF00, 0x0F,tx}, - {AX5043_REG_0xF18, 0x06,tx}, - {AX5043_REG_PLLLOOP, 0x0B,rx}, - {AX5043_REG_PLLCPI, 0x10,rx}, - {AX5043_REG_PLLVCODIV, 0x25,rx}, - {AX5043_REG_XTALCAP, 0x00,rx}, - {AX5043_REG_0xF00, 0x0F,rx}, - {AX5043_REG_0xF18, 0x02,rx}, - {AX5043_REG_TMGRXAGC, 0x00,rx_cont}, - {AX5043_REG_TMGRXPREAMBLE1, 0x00,rx_cont}, - {AX5043_REG_PKTMISCFLAGS, 0x00,rx_cont}, - {AX5043_REG_PKTADDR0, 0x00,local_address}, - {AX5043_REG_PKTADDR1, 0x00,local_address}, - {AX5043_REG_PKTADDR2, 0x00,local_address}, - {AX5043_REG_PKTADDR3, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK0, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK1, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK2, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK3, 0x00,local_address}, - {AX5043_REG_END, 0x00,common} -}; - - -ax5043_confval_t conf_values[]={ - {AXRADIO_PHY_PN9 ,0}, - {AXRADIO_PHY_NRCHANNELS ,1}, - {AXRADIO_PHY_CHANFREQ ,0X0912AAAB }, - {AXRADIO_PHY_CHANPLLRNGINIT ,0X0A }, - {AXRADIO_PHY_CHANVCOIINIT ,0X98}, - {AXRADIO_PHY_CHANPLLRNG ,0}, - {AXRADIO_PHY_CHANVCOI ,0}, - {AXRADIO_PHY_VCOCALIB ,0}, - {AXRADIO_PHY_MAXFREQOFFSET ,913}, - {AXRADIO_PHY_RSSIOFFSET ,64}, - {AXRADIO_PHY_RSSIREFERENCE ,313}, - {AXRADIO_PHY_CHANNELBUSY ,-23}, - {AXRADIO_PHY_CS_PERIOD ,7}, - {AXRADIO_PHY_CS_ENABLED ,0}, - {AXRADIO_PHY_LBT_RETRIES ,0}, - {AXRADIO_PHY_LBT_FORCETX ,0}, - {AXRADIO_PHY_PREAMBLE_WOR_LONGLEN ,9}, - {AXRADIO_PHY_PREAMBLE_WOR_LEN ,40}, - {AXRADIO_PHY_PREAMBLE_LONGLEN ,0}, - {AXRADIO_PHY_PREAMBLE_LEN ,40}, - {AXRADIO_PHY_PREAMBLE_BYTE ,0X7E}, - {AXRADIO_PHY_PREAMBLE_FLAGS ,0X18}, - {AXRADIO_PHY_PREAMBLE_APPENDBITS ,0}, - {AXRADIO_PHY_PREAMBLE_APPENDPATTERN ,0X00}, - {AXRADIO_FRAMING_MACLEN ,0}, - {AXRADIO_FRAMING_ADDRLEN ,0}, - {AXRADIO_FRAMING_DESTADDRPOS ,0}, - {AXRADIO_FRAMING_SOURCEADDRPOS ,0XFF}, - {AXRADIO_FRAMING_LENPOS ,0}, - {AXRADIO_FRAMING_LENOFFS ,21}, - {AXRADIO_FRAMING_LENMASK ,0X00}, - {AXRADIO_FRAMING_SWCRCLEN ,0}, - {AXRADIO_FRAMING_SYNCLEN ,32}, - {AXRADIO_FRAMING_SYNCWORD0 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD1 ,0XAA}, - {AXRADIO_FRAMING_SYNCWORD2 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD3 ,0XAA}, - {AXRADIO_FRAMING_SYNCFLAGS ,0X18}, - {AXRADIO_FRAMING_ENABLE_SFDCALLBACK ,0}, - {AXRADIO_FRAMING_ACK_TIMEOUT ,8}, - {AXRADIO_FRAMING_ACK_DELAY ,313}, - {AXRADIO_FRAMING_ACK_RETRANSMISSIONS ,0}, - {AXRADIO_FRAMING_ACK_SEQNRPOS ,0XFF}, - {AXRADIO_FRAMING_MINPAYLOADLEN ,0}, - {AXRADIO_WOR_PERIOD ,128}, - {AXRADIO_PHY_INNERFREQLOOP ,0}, - {AXRADIO_PHY_END ,0} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; - - -//Radio driver configurations - -static AX5043Config axcfg1 = -{ - &SPID2, - LINE_SX_INT0, - reg_values, - conf_values, - AX5043_MODE_TX, - &radio1_rx_mb -}; -AX5043Driver axd1; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - - // Creating the mailboxes. - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - - //initiating radio driver - ax5043ObjectInit(&axd1); - ax5043Start(&axd1, &axcfg1); - - - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending packet %d\r\n",pkt_counter); - transmit_packet(&axd1, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(5000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_driver/main_cw.c b/src/archive/app_ax5043_driver/main_cw.c deleted file mode 100644 index 67214fcf..00000000 --- a/src/archive/app_ax5043_driver/main_cw.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" -#include "morse.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; - -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 1; -const uint8_t framing_counter_pos = 0; - -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08,common}, - {AX5043_REG_ENCODING, 0x00,common}, - {AX5043_REG_FRAMING, 0x24,common}, - {AX5043_REG_CRCINIT3, 0x00,common}, - {AX5043_REG_CRCINIT2, 0x00,common}, - {AX5043_REG_CRCINIT1, 0xFF,common}, - {AX5043_REG_CRCINIT0, 0xFF,common}, - {AX5043_REG_PINFUNCSYSCLK, 0x01,common}, - {AX5043_REG_PINFUNCDCLK, 0x01,common}, - {AX5043_REG_PINFUNCDATA, 0x01,common}, - {AX5043_REG_PINFUNCANTSEL, 0x01,common}, - {AX5043_REG_PINFUNCPWRAMP, 0x07,common}, - {AX5043_REG_WAKEUPXOEARLY, 0x01,common}, - {AX5043_REG_IFFREQ1, 0x0B,common}, - {AX5043_REG_IFFREQ0, 0x09,common}, - {AX5043_REG_DECIMATION, 0x02,common}, - {AX5043_REG_RXDATARATE2, 0x00,common}, - {AX5043_REG_RXDATARATE1, 0x3C,common}, - {AX5043_REG_RXDATARATE0, 0x00,common}, - {AX5043_REG_MAXDROFFSET2, 0x00,common}, - {AX5043_REG_MAXDROFFSET1, 0x00,common}, - {AX5043_REG_MAXDROFFSET0, 0x00,common}, - {AX5043_REG_MAXRFOFFSET2, 0x80,common}, - {AX5043_REG_MAXRFOFFSET1, 0x01,common}, - {AX5043_REG_MAXRFOFFSET0, 0x30,common}, - {AX5043_REG_FSKDMAX1, 0x00,common}, - {AX5043_REG_FSKDMAX0, 0xA6,common}, - {AX5043_REG_FSKDMIN1, 0xFF,common}, - {AX5043_REG_FSKDMIN0, 0x5A,common}, - {AX5043_REG_AMPLFILTER, 0x00,common}, - {AX5043_REG_RXPARAMSETS, 0xF4,common}, - {AX5043_REG_AGCGAIN0, 0x83,common}, - {AX5043_REG_AGCTARGET0, 0x84,common}, - {AX5043_REG_TIMEGAIN0, 0xF8,common}, - {AX5043_REG_DRGAIN0, 0xF2,common}, - {AX5043_REG_PHASEGAIN0, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA0,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB0,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC0,0x05,common}, - {AX5043_REG_FREQUENCYGAIND0,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06,common}, - {AX5043_REG_FREQDEV10, 0x00,common}, - {AX5043_REG_FREQDEV00, 0x00,common}, - {AX5043_REG_BBOFFSRES0, 0x00,common}, - {AX5043_REG_AGCGAIN1, 0x83,common}, - {AX5043_REG_AGCTARGET1, 0x84,common}, - {AX5043_REG_AGCAHYST1, 0x00,common}, - {AX5043_REG_AGCMINMAX1, 0x00,common}, - {AX5043_REG_TIMEGAIN1, 0xF6,common}, - {AX5043_REG_DRGAIN1, 0xF1,common}, - {AX5043_REG_PHASEGAIN1, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA1,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB1,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC1,0x05,common}, - {AX5043_REG_FREQUENCYGAIND1,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06,common}, - {AX5043_REG_FREQDEV11, 0x00,common}, - {AX5043_REG_FREQDEV01, 0x1C,common}, - {AX5043_REG_FOURFSK1, 0x16,common}, - {AX5043_REG_BBOFFSRES1, 0x00,common}, - {AX5043_REG_AGCGAIN3, 0xFF,common}, - {AX5043_REG_AGCTARGET3, 0x84,common}, - {AX5043_REG_AGCAHYST3, 0x00,common}, - {AX5043_REG_AGCMINMAX3, 0x00,common}, - {AX5043_REG_TIMEGAIN3, 0xF5,common}, - {AX5043_REG_DRGAIN3, 0xF0,common}, - {AX5043_REG_PHASEGAIN3, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA3,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB3,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC3,0x09,common}, - {AX5043_REG_FREQUENCYGAIND3,0x09,common}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06,common}, - {AX5043_REG_FREQDEV13, 0x00,common}, - {AX5043_REG_FREQDEV03, 0x1C,common}, - {AX5043_REG_FOURFSK3, 0x16,common}, - {AX5043_REG_BBOFFSRES3, 0x00,common}, - {AX5043_REG_MODCFGF, 0x02,common}, - {AX5043_REG_FSKDEV2, 0x00,common}, - {AX5043_REG_FSKDEV1, 0x00,common}, - {AX5043_REG_FSKDEV0, 0x00,common}, - {AX5043_REG_MODCFGA, 0x05,common}, - {AX5043_REG_TXRATE2, 0x00,common}, - {AX5043_REG_TXRATE1, 0x00,common}, - {AX5043_REG_TXRATE0, 0x01,common}, - {AX5043_REG_TXPWRCOEFFB1, 0x07,common}, - {AX5043_REG_TXPWRCOEFFB0, 0x00,common}, - {AX5043_REG_PLLVCOI, 0x98,common}, - {AX5043_REG_PLLRNGCLK, 0x05,common}, - {AX5043_REG_BBTUNE, 0x03,common}, - {AX5043_REG_BBOFFSCAP, 0x77,common}, - {AX5043_REG_PKTADDRCFG, 0x00,common}, - {AX5043_REG_PKTLENCFG, 0x82,common}, - {AX5043_REG_PKTLENOFFSET, 0x00,common}, - {AX5043_REG_PKTMAXLEN, 0xC8,common}, - {AX5043_REG_MATCH0PAT3, 0xAA,common}, - {AX5043_REG_MATCH0PAT2, 0xCC,common}, - {AX5043_REG_MATCH0PAT1, 0xAA,common}, - {AX5043_REG_MATCH0PAT0, 0xCC,common}, - {AX5043_REG_MATCH1PAT1, 0x55,common}, - {AX5043_REG_MATCH1PAT0, 0x55,common}, - {AX5043_REG_MATCH1LEN, 0x8A,common}, - {AX5043_REG_MATCH1MAX, 0x0A,common}, - {AX5043_REG_TMGTXBOOST, 0x5B,common}, - {AX5043_REG_TMGTXSETTLE, 0x3E,common}, - {AX5043_REG_TMGRXOFFSACQ, 0x00,common}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C,common}, - {AX5043_REG_TMGRXRSSI, 0x03,common}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17,common}, - {AX5043_REG_RSSIABSTHR, 0xEB,common}, - {AX5043_REG_BGNDRSSITHR, 0x00,common}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D,common}, - {AX5043_REG_PKTACCEPTFLAGS, 0x20,common}, - {AX5043_REG_DACVALUE1, 0x00,common}, - {AX5043_REG_DACVALUE0, 0x00,common}, - {AX5043_REG_DACCONFIG, 0x00,common}, - {AX5043_REG_REF, 0x03,common}, - {AX5043_REG_XTALOSC, 0x04,common}, - {AX5043_REG_XTALAMPL, 0x00,common}, - {AX5043_REG_0xF1C, 0x07,common}, - {AX5043_REG_0xF21, 0x68,common}, - {AX5043_REG_0xF22, 0XFF,common}, - {AX5043_REG_0xF23, 0x84,common}, - {AX5043_REG_0xF26, 0x98,common}, - {AX5043_REG_0xF34, 0x28,common}, - {AX5043_REG_0xF35, 0x11,common}, - {AX5043_REG_0xF44, 0x25,common}, - {AX5043_REG_PINFUNCIRQ, 0x03,common}, - {AX5043_REG_PKTSTOREFLAGS, 0x14,common}, - {AX5043_REG_PLLLOOP, 0x09,tx}, - {AX5043_REG_PLLCPI, 0x02,tx}, - {AX5043_REG_PLLVCODIV, 0x24,tx}, - {AX5043_REG_XTALCAP, 0x00,tx}, - {AX5043_REG_0xF00, 0x0F,tx}, - {AX5043_REG_0xF18, 0x06,tx}, - {AX5043_REG_PLLLOOP, 0x09,rx}, - {AX5043_REG_PLLCPI, 0x01,rx}, - {AX5043_REG_PLLVCODIV, 0x25,rx}, - {AX5043_REG_XTALCAP, 0x00,rx}, - {AX5043_REG_0xF00, 0x0F,rx}, - {AX5043_REG_0xF18, 0x02,rx}, - {AX5043_REG_TMGRXAGC, 0x00,rx_cont}, - {AX5043_REG_TMGRXPREAMBLE1, 0x00,rx_cont}, - {AX5043_REG_PKTMISCFLAGS, 0x00,rx_cont}, - {AX5043_REG_PKTADDR0, 0x32,local_address}, - {AX5043_REG_PKTADDR1, 0x34,local_address}, - {AX5043_REG_PKTADDR2, 0x00,local_address}, - {AX5043_REG_PKTADDR3, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK0, 0xFF,local_address}, - {AX5043_REG_PKTADDRMASK1, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK2, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK3, 0x00,local_address}, - {AX5043_REG_END, 0x00,common} -}; - - -ax5043_confval_t conf_values[]={ - {AXRADIO_PHY_PN9 ,0}, - {AXRADIO_PHY_NRCHANNELS ,1}, - {AXRADIO_PHY_CHANFREQ ,0X0912AAAB }, - {AXRADIO_PHY_CHANPLLRNGINIT ,0X0A }, - {AXRADIO_PHY_CHANVCOIINIT ,0X98}, - {AXRADIO_PHY_CHANPLLRNG ,0}, - {AXRADIO_PHY_CHANVCOI ,0}, - {AXRADIO_PHY_VCOCALIB ,0}, - {AXRADIO_PHY_MAXFREQOFFSET ,913}, - {AXRADIO_PHY_RSSIOFFSET ,64}, - {AXRADIO_PHY_RSSIREFERENCE ,313}, - {AXRADIO_PHY_CHANNELBUSY ,-23}, - {AXRADIO_PHY_CS_PERIOD ,7}, - {AXRADIO_PHY_CS_ENABLED ,0}, - {AXRADIO_PHY_LBT_RETRIES ,0}, - {AXRADIO_PHY_LBT_FORCETX ,0}, - {AXRADIO_PHY_PREAMBLE_WOR_LONGLEN ,23}, - {AXRADIO_PHY_PREAMBLE_WOR_LEN ,184}, - {AXRADIO_PHY_PREAMBLE_LONGLEN ,0}, - {AXRADIO_PHY_PREAMBLE_LEN ,72}, - {AXRADIO_PHY_PREAMBLE_BYTE ,0X7E}, - {AXRADIO_PHY_PREAMBLE_FLAGS ,0X38}, - {AXRADIO_PHY_PREAMBLE_APPENDBITS ,0}, - {AXRADIO_PHY_PREAMBLE_APPENDPATTERN ,0X00}, - {AXRADIO_FRAMING_MACLEN ,3}, - {AXRADIO_FRAMING_ADDRLEN ,1}, - {AXRADIO_FRAMING_DESTADDRPOS ,0}, - {AXRADIO_FRAMING_SOURCEADDRPOS ,0XFF}, - {AXRADIO_FRAMING_LENPOS ,2}, - {AXRADIO_FRAMING_LENOFFS ,0}, - {AXRADIO_FRAMING_LENMASK ,0XFF}, - {AXRADIO_FRAMING_SWCRCLEN ,0}, - {AXRADIO_FRAMING_SYNCLEN ,32}, - {AXRADIO_FRAMING_SYNCWORD0 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD1 ,0XAA}, - {AXRADIO_FRAMING_SYNCWORD2 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD3 ,0XAA}, - {AXRADIO_FRAMING_SYNCFLAGS ,0X38}, - {AXRADIO_FRAMING_ENABLE_SFDCALLBACK ,0}, - {AXRADIO_FRAMING_ACK_TIMEOUT ,8}, - {AXRADIO_FRAMING_ACK_DELAY ,313}, - {AXRADIO_FRAMING_ACK_RETRANSMISSIONS ,0}, - {AXRADIO_FRAMING_ACK_SEQNRPOS ,0XFF}, - {AXRADIO_FRAMING_MINPAYLOADLEN ,0}, - {AXRADIO_WOR_PERIOD ,128}, - {AXRADIO_PHY_INNERFREQLOOP ,0}, - {AXRADIO_PHY_END ,0} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; - - -//Radio driver configurations - -static AX5043Config axcfg1 = -{ - &SPID2, - LINE_SX_INT0, - reg_values, - conf_values, - AX5043_MODE_CW, - &radio1_rx_mb -}; -AX5043Driver axd1; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - - // Creating the mailboxes. - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - - //initiating radio driver - ax5043ObjectInit(&axd1); - ax5043Start(&axd1, &axcfg1); - - - - // This is for CW - - char cw_message[] = "KG7ZVV Malay Das testing AX5043"; - int wpm = 22; - for (;;) { - chprintf(DEBUG_CHP,"INFO: Sending CW %d\r\n", sizeof(cw_message)); - - ax5043_send_cw(&axd1, wpm, cw_message, sizeof(cw_message)); - - chThdSleepMilliseconds(500); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_driver/main_engr_rx.c b/src/archive/app_ax5043_driver/main_engr_rx.c deleted file mode 100644 index 2cd7ec8c..00000000 --- a/src/archive/app_ax5043_driver/main_engr_rx.c +++ /dev/null @@ -1,415 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x32, 0x34, 0x00, 0x00} -}; - -/* -const struct axradio_address_mask localaddr_tx = { - { 0x33, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; -*/ - -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08,common}, - {AX5043_REG_ENCODING, 0x00,common}, - {AX5043_REG_FRAMING, 0x24,common}, - {AX5043_REG_CRCINIT3, 0x00,common}, - {AX5043_REG_CRCINIT2, 0x00,common}, - {AX5043_REG_CRCINIT1, 0xFF,common}, - {AX5043_REG_CRCINIT0, 0xFF,common}, - {AX5043_REG_PINFUNCSYSCLK, 0x01,common}, - {AX5043_REG_PINFUNCDCLK, 0x01,common}, - {AX5043_REG_PINFUNCDATA, 0x01,common}, - {AX5043_REG_PINFUNCANTSEL, 0x01,common}, - {AX5043_REG_PINFUNCPWRAMP, 0x07,common}, - {AX5043_REG_WAKEUPXOEARLY, 0x01,common}, - {AX5043_REG_IFFREQ1, 0x0B,common}, - {AX5043_REG_IFFREQ0, 0x09,common}, - {AX5043_REG_DECIMATION, 0x02,common}, - {AX5043_REG_RXDATARATE2, 0x00,common}, - {AX5043_REG_RXDATARATE1, 0x3C,common}, - {AX5043_REG_RXDATARATE0, 0x00,common}, - {AX5043_REG_MAXDROFFSET2, 0x00,common}, - {AX5043_REG_MAXDROFFSET1, 0x00,common}, - {AX5043_REG_MAXDROFFSET0, 0x00,common}, - {AX5043_REG_MAXRFOFFSET2, 0x80,common}, - {AX5043_REG_MAXRFOFFSET1, 0x01,common}, - {AX5043_REG_MAXRFOFFSET0, 0x30,common}, - {AX5043_REG_FSKDMAX1, 0x00,common}, - {AX5043_REG_FSKDMAX0, 0xA6,common}, - {AX5043_REG_FSKDMIN1, 0xFF,common}, - {AX5043_REG_FSKDMIN0, 0x5A,common}, - {AX5043_REG_AMPLFILTER, 0x00,common}, - {AX5043_REG_RXPARAMSETS, 0xF4,common}, - {AX5043_REG_AGCGAIN0, 0x83,common}, - {AX5043_REG_AGCTARGET0, 0x84,common}, - {AX5043_REG_TIMEGAIN0, 0xF8,common}, - {AX5043_REG_DRGAIN0, 0xF2,common}, - {AX5043_REG_PHASEGAIN0, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA0,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB0,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC0,0x05,common}, - {AX5043_REG_FREQUENCYGAIND0,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06,common}, - {AX5043_REG_FREQDEV10, 0x00,common}, - {AX5043_REG_FREQDEV00, 0x00,common}, - {AX5043_REG_BBOFFSRES0, 0x00,common}, - {AX5043_REG_AGCGAIN1, 0x83,common}, - {AX5043_REG_AGCTARGET1, 0x84,common}, - {AX5043_REG_AGCAHYST1, 0x00,common}, - {AX5043_REG_AGCMINMAX1, 0x00,common}, - {AX5043_REG_TIMEGAIN1, 0xF6,common}, - {AX5043_REG_DRGAIN1, 0xF1,common}, - {AX5043_REG_PHASEGAIN1, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA1,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB1,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC1,0x05,common}, - {AX5043_REG_FREQUENCYGAIND1,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06,common}, - {AX5043_REG_FREQDEV11, 0x00,common}, - {AX5043_REG_FREQDEV01, 0x1C,common}, - {AX5043_REG_FOURFSK1, 0x16,common}, - {AX5043_REG_BBOFFSRES1, 0x00,common}, - {AX5043_REG_AGCGAIN3, 0xFF,common}, - {AX5043_REG_AGCTARGET3, 0x84,common}, - {AX5043_REG_AGCAHYST3, 0x00,common}, - {AX5043_REG_AGCMINMAX3, 0x00,common}, - {AX5043_REG_TIMEGAIN3, 0xF5,common}, - {AX5043_REG_DRGAIN3, 0xF0,common}, - {AX5043_REG_PHASEGAIN3, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA3,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB3,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC3,0x09,common}, - {AX5043_REG_FREQUENCYGAIND3,0x09,common}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06,common}, - {AX5043_REG_FREQDEV13, 0x00,common}, - {AX5043_REG_FREQDEV03, 0x1C,common}, - {AX5043_REG_FOURFSK3, 0x16,common}, - {AX5043_REG_BBOFFSRES3, 0x00,common}, - {AX5043_REG_MODCFGF, 0x02,common}, - {AX5043_REG_FSKDEV2, 0x00,common}, - {AX5043_REG_FSKDEV1, 0x22,common}, - {AX5043_REG_FSKDEV0, 0x22,common}, - {AX5043_REG_MODCFGA, 0x05,common}, - {AX5043_REG_TXRATE2, 0x00,common}, - {AX5043_REG_TXRATE1, 0x88,common}, - {AX5043_REG_TXRATE0, 0x89,common}, - {AX5043_REG_TXPWRCOEFFB1, 0x07,common}, - {AX5043_REG_TXPWRCOEFFB0, 0x00,common}, - {AX5043_REG_PLLVCOI, 0x98,common}, - {AX5043_REG_PLLRNGCLK, 0x05,common}, - {AX5043_REG_BBTUNE, 0x03,common}, - {AX5043_REG_BBOFFSCAP, 0x77,common}, - {AX5043_REG_PKTADDRCFG, 0x00,common}, - {AX5043_REG_PKTLENCFG, 0x82,common}, - {AX5043_REG_PKTLENOFFSET, 0x00,common}, - {AX5043_REG_PKTMAXLEN, 0xC8,common}, - {AX5043_REG_MATCH0PAT3, 0xAA,common}, - {AX5043_REG_MATCH0PAT2, 0xCC,common}, - {AX5043_REG_MATCH0PAT1, 0xAA,common}, - {AX5043_REG_MATCH0PAT0, 0xCC,common}, - {AX5043_REG_MATCH1PAT1, 0x55,common}, - {AX5043_REG_MATCH1PAT0, 0x55,common}, - {AX5043_REG_MATCH1LEN, 0x8A,common}, - {AX5043_REG_MATCH1MAX, 0x0A,common}, - {AX5043_REG_TMGTXBOOST, 0x5B,common}, - {AX5043_REG_TMGTXSETTLE, 0x3E,common}, - {AX5043_REG_TMGRXOFFSACQ, 0x00,common}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C,common}, - {AX5043_REG_TMGRXRSSI, 0x03,common}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17,common}, - {AX5043_REG_RSSIABSTHR, 0xEB,common}, - {AX5043_REG_BGNDRSSITHR, 0x00,common}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D,common}, - {AX5043_REG_PKTACCEPTFLAGS, 0x20,common}, - {AX5043_REG_DACVALUE1, 0x00,common}, - {AX5043_REG_DACVALUE0, 0x00,common}, - {AX5043_REG_DACCONFIG, 0x00,common}, - {AX5043_REG_REF, 0x03,common}, - {AX5043_REG_XTALOSC, 0x04,common}, - {AX5043_REG_XTALAMPL, 0x00,common}, - {AX5043_REG_0xF1C, 0x07,common}, - {AX5043_REG_0xF21, 0x68,common}, - {AX5043_REG_0xF22, 0XFF,common}, - {AX5043_REG_0xF23, 0x84,common}, - {AX5043_REG_0xF26, 0x98,common}, - {AX5043_REG_0xF34, 0x28,common}, - {AX5043_REG_0xF35, 0x11,common}, - {AX5043_REG_0xF44, 0x25,common}, - {AX5043_REG_PINFUNCIRQ, 0x03,common}, - {AX5043_REG_PKTSTOREFLAGS, 0x14,common}, - {AX5043_REG_PLLLOOP, 0x09,tx}, - {AX5043_REG_PLLCPI, 0x02,tx}, - {AX5043_REG_PLLVCODIV, 0x24,tx}, - {AX5043_REG_XTALCAP, 0x00,tx}, - {AX5043_REG_0xF00, 0x0F,tx}, - {AX5043_REG_0xF18, 0x06,tx}, - {AX5043_REG_PLLLOOP, 0x09,rx}, - {AX5043_REG_PLLCPI, 0x01,rx}, - {AX5043_REG_PLLVCODIV, 0x25,rx}, - {AX5043_REG_XTALCAP, 0x00,rx}, - {AX5043_REG_0xF00, 0x0F,rx}, - {AX5043_REG_0xF18, 0x02,rx}, - {AX5043_REG_TMGRXAGC, 0x00,rx_cont}, - {AX5043_REG_TMGRXPREAMBLE1, 0x00,rx_cont}, - {AX5043_REG_PKTMISCFLAGS, 0x00,rx_cont}, - {AX5043_REG_PKTADDR0, 0x33,local_address}, - {AX5043_REG_PKTADDR1, 0x34,local_address}, - {AX5043_REG_PKTADDR2, 0x00,local_address}, - {AX5043_REG_PKTADDR3, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK0, 0xFF,local_address}, - {AX5043_REG_PKTADDRMASK1, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK2, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK3, 0x00,local_address}, - {AX5043_REG_END, 0x00,common} -}; - - -ax5043_confval_t conf_values[]={ - {AXRADIO_PHY_PN9 ,0}, - {AXRADIO_PHY_NRCHANNELS ,1}, - {AXRADIO_PHY_CHANFREQ ,0X0912AAAB }, - {AXRADIO_PHY_CHANPLLRNGINIT ,0X0A }, - {AXRADIO_PHY_CHANVCOIINIT ,0X98}, - {AXRADIO_PHY_CHANPLLRNG ,0}, - {AXRADIO_PHY_CHANVCOI ,0}, - {AXRADIO_PHY_VCOCALIB ,0}, - {AXRADIO_PHY_MAXFREQOFFSET ,913}, - {AXRADIO_PHY_RSSIOFFSET ,64}, - {AXRADIO_PHY_RSSIREFERENCE ,313}, - {AXRADIO_PHY_CHANNELBUSY ,-23}, - {AXRADIO_PHY_CS_PERIOD ,7}, - {AXRADIO_PHY_CS_ENABLED ,0}, - {AXRADIO_PHY_LBT_RETRIES ,0}, - {AXRADIO_PHY_LBT_FORCETX ,0}, - {AXRADIO_PHY_PREAMBLE_WOR_LONGLEN ,23}, - {AXRADIO_PHY_PREAMBLE_WOR_LEN ,184}, - {AXRADIO_PHY_PREAMBLE_LONGLEN ,0}, - {AXRADIO_PHY_PREAMBLE_LEN ,72}, - {AXRADIO_PHY_PREAMBLE_BYTE ,0X7E}, - {AXRADIO_PHY_PREAMBLE_FLAGS ,0X38}, - {AXRADIO_PHY_PREAMBLE_APPENDBITS ,0}, - {AXRADIO_PHY_PREAMBLE_APPENDPATTERN ,0X00}, - {AXRADIO_FRAMING_MACLEN ,3}, - {AXRADIO_FRAMING_ADDRLEN ,1}, - {AXRADIO_FRAMING_DESTADDRPOS ,0}, - {AXRADIO_FRAMING_SOURCEADDRPOS ,0XFF}, - {AXRADIO_FRAMING_LENPOS ,2}, - {AXRADIO_FRAMING_LENOFFS ,0}, - {AXRADIO_FRAMING_LENMASK ,0XFF}, - {AXRADIO_FRAMING_SWCRCLEN ,0}, - {AXRADIO_FRAMING_SYNCLEN ,32}, - {AXRADIO_FRAMING_SYNCWORD0 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD1 ,0XAA}, - {AXRADIO_FRAMING_SYNCWORD2 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD3 ,0XAA}, - {AXRADIO_FRAMING_SYNCFLAGS ,0X38}, - {AXRADIO_FRAMING_ENABLE_SFDCALLBACK ,0}, - {AXRADIO_FRAMING_ACK_TIMEOUT ,8}, - {AXRADIO_FRAMING_ACK_DELAY ,313}, - {AXRADIO_FRAMING_ACK_RETRANSMISSIONS ,0}, - {AXRADIO_FRAMING_ACK_SEQNRPOS ,0XFF}, - {AXRADIO_FRAMING_MINPAYLOADLEN ,0}, - {AXRADIO_WOR_PERIOD ,128}, - {AXRADIO_PHY_INNERFREQLOOP ,0}, - {AXRADIO_PHY_END ,0} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; - - -//Radio driver configurations - -static AX5043Config axcfg1 = -{ - &SPID2, - LINE_SX_INT0, - reg_values, - conf_values, - AX5043_MODE_RX, - &radio1_rx_mb -}; -AX5043Driver axd1; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - - // Creating the mailboxes. - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - - //initiating radio driver - ax5043ObjectInit(&axd1); - ax5043Start(&axd1, &axcfg1); -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - uint8_t packet_len=0; - //uint8_t ret_value[3]={0,0,0}; - - /* Enabling events on both edges of the button line.*/ - //palEnableLineEvent(LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE); - palEnableLineEvent(LINE_SX_INT0, PAL_EVENT_MODE_RISING_EDGE); - - - while(true) - { - //palWaitLineTimeout(LINE_BUTTON, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_MS2I(5000)); - - palWaitLineTimeout(LINE_SX_INT0, TIME_MS2I(5000)); - - if (palReadLine(LINE_SX_INT0)) - chprintf(DEBUG_CHP, "\r\r INFO: interrupt happened ** \r\n"); - else - chprintf(DEBUG_CHP, "\r\r INFO: interrupt timeout** \r\n"); - - packet_len=receive_loop(&axd1, axradio_rxbuffer); - //chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x\r\n", axd1.rf_freq_off3, axd1.rf_freq_off2, axd1.rf_freq_off1); - //chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)axd1.rssi); - if(packet_len > 0) - chprintf(DEBUG_CHP,"INFO: Received packet %d\r\n",axradio_rxbuffer[3]); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_driver/main_engr_tx.c b/src/archive/app_ax5043_driver/main_engr_tx.c deleted file mode 100644 index eca93c1d..00000000 --- a/src/archive/app_ax5043_driver/main_engr_tx.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; - -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 1; -const uint8_t framing_counter_pos = 0; - -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08,common}, - {AX5043_REG_ENCODING, 0x00,common}, - {AX5043_REG_FRAMING, 0x24,common}, - {AX5043_REG_CRCINIT3, 0x00,common}, - {AX5043_REG_CRCINIT2, 0x00,common}, - {AX5043_REG_CRCINIT1, 0xFF,common}, - {AX5043_REG_CRCINIT0, 0xFF,common}, - {AX5043_REG_PINFUNCSYSCLK, 0x01,common}, - {AX5043_REG_PINFUNCDCLK, 0x01,common}, - {AX5043_REG_PINFUNCDATA, 0x01,common}, - {AX5043_REG_PINFUNCANTSEL, 0x01,common}, - {AX5043_REG_PINFUNCPWRAMP, 0x07,common}, - {AX5043_REG_WAKEUPXOEARLY, 0x01,common}, - {AX5043_REG_IFFREQ1, 0x0B,common}, - {AX5043_REG_IFFREQ0, 0x09,common}, - {AX5043_REG_DECIMATION, 0x02,common}, - {AX5043_REG_RXDATARATE2, 0x00,common}, - {AX5043_REG_RXDATARATE1, 0x3C,common}, - {AX5043_REG_RXDATARATE0, 0x00,common}, - {AX5043_REG_MAXDROFFSET2, 0x00,common}, - {AX5043_REG_MAXDROFFSET1, 0x00,common}, - {AX5043_REG_MAXDROFFSET0, 0x00,common}, - {AX5043_REG_MAXRFOFFSET2, 0x80,common}, - {AX5043_REG_MAXRFOFFSET1, 0x01,common}, - {AX5043_REG_MAXRFOFFSET0, 0x30,common}, - {AX5043_REG_FSKDMAX1, 0x00,common}, - {AX5043_REG_FSKDMAX0, 0xA6,common}, - {AX5043_REG_FSKDMIN1, 0xFF,common}, - {AX5043_REG_FSKDMIN0, 0x5A,common}, - {AX5043_REG_AMPLFILTER, 0x00,common}, - {AX5043_REG_RXPARAMSETS, 0xF4,common}, - {AX5043_REG_AGCGAIN0, 0x83,common}, - {AX5043_REG_AGCTARGET0, 0x84,common}, - {AX5043_REG_TIMEGAIN0, 0xF8,common}, - {AX5043_REG_DRGAIN0, 0xF2,common}, - {AX5043_REG_PHASEGAIN0, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA0,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB0,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC0,0x05,common}, - {AX5043_REG_FREQUENCYGAIND0,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06,common}, - {AX5043_REG_FREQDEV10, 0x00,common}, - {AX5043_REG_FREQDEV00, 0x00,common}, - {AX5043_REG_BBOFFSRES0, 0x00,common}, - {AX5043_REG_AGCGAIN1, 0x83,common}, - {AX5043_REG_AGCTARGET1, 0x84,common}, - {AX5043_REG_AGCAHYST1, 0x00,common}, - {AX5043_REG_AGCMINMAX1, 0x00,common}, - {AX5043_REG_TIMEGAIN1, 0xF6,common}, - {AX5043_REG_DRGAIN1, 0xF1,common}, - {AX5043_REG_PHASEGAIN1, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA1,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB1,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC1,0x05,common}, - {AX5043_REG_FREQUENCYGAIND1,0x05,common}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06,common}, - {AX5043_REG_FREQDEV11, 0x00,common}, - {AX5043_REG_FREQDEV01, 0x1C,common}, - {AX5043_REG_FOURFSK1, 0x16,common}, - {AX5043_REG_BBOFFSRES1, 0x00,common}, - {AX5043_REG_AGCGAIN3, 0xFF,common}, - {AX5043_REG_AGCTARGET3, 0x84,common}, - {AX5043_REG_AGCAHYST3, 0x00,common}, - {AX5043_REG_AGCMINMAX3, 0x00,common}, - {AX5043_REG_TIMEGAIN3, 0xF5,common}, - {AX5043_REG_DRGAIN3, 0xF0,common}, - {AX5043_REG_PHASEGAIN3, 0xC3,common}, - {AX5043_REG_FREQUENCYGAINA3,0x0F,common}, - {AX5043_REG_FREQUENCYGAINB3,0x1F,common}, - {AX5043_REG_FREQUENCYGAINC3,0x09,common}, - {AX5043_REG_FREQUENCYGAIND3,0x09,common}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06,common}, - {AX5043_REG_FREQDEV13, 0x00,common}, - {AX5043_REG_FREQDEV03, 0x1C,common}, - {AX5043_REG_FOURFSK3, 0x16,common}, - {AX5043_REG_BBOFFSRES3, 0x00,common}, - {AX5043_REG_MODCFGF, 0x02,common}, - {AX5043_REG_FSKDEV2, 0x00,common}, - {AX5043_REG_FSKDEV1, 0x22,common}, - {AX5043_REG_FSKDEV0, 0x22,common}, - {AX5043_REG_MODCFGA, 0x05,common}, - {AX5043_REG_TXRATE2, 0x00,common}, - {AX5043_REG_TXRATE1, 0x88,common}, - {AX5043_REG_TXRATE0, 0x89,common}, - {AX5043_REG_TXPWRCOEFFB1, 0x07,common}, - {AX5043_REG_TXPWRCOEFFB0, 0x00,common}, - {AX5043_REG_PLLVCOI, 0x98,common}, - {AX5043_REG_PLLRNGCLK, 0x05,common}, - {AX5043_REG_BBTUNE, 0x03,common}, - {AX5043_REG_BBOFFSCAP, 0x77,common}, - {AX5043_REG_PKTADDRCFG, 0x00,common}, - {AX5043_REG_PKTLENCFG, 0x82,common}, - {AX5043_REG_PKTLENOFFSET, 0x00,common}, - {AX5043_REG_PKTMAXLEN, 0xC8,common}, - {AX5043_REG_MATCH0PAT3, 0xAA,common}, - {AX5043_REG_MATCH0PAT2, 0xCC,common}, - {AX5043_REG_MATCH0PAT1, 0xAA,common}, - {AX5043_REG_MATCH0PAT0, 0xCC,common}, - {AX5043_REG_MATCH1PAT1, 0x55,common}, - {AX5043_REG_MATCH1PAT0, 0x55,common}, - {AX5043_REG_MATCH1LEN, 0x8A,common}, - {AX5043_REG_MATCH1MAX, 0x0A,common}, - {AX5043_REG_TMGTXBOOST, 0x5B,common}, - {AX5043_REG_TMGTXSETTLE, 0x3E,common}, - {AX5043_REG_TMGRXOFFSACQ, 0x00,common}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C,common}, - {AX5043_REG_TMGRXRSSI, 0x03,common}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17,common}, - {AX5043_REG_RSSIABSTHR, 0xEB,common}, - {AX5043_REG_BGNDRSSITHR, 0x00,common}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D,common}, - {AX5043_REG_PKTACCEPTFLAGS, 0x20,common}, - {AX5043_REG_DACVALUE1, 0x00,common}, - {AX5043_REG_DACVALUE0, 0x00,common}, - {AX5043_REG_DACCONFIG, 0x00,common}, - {AX5043_REG_REF, 0x03,common}, - {AX5043_REG_XTALOSC, 0x04,common}, - {AX5043_REG_XTALAMPL, 0x00,common}, - {AX5043_REG_0xF1C, 0x07,common}, - {AX5043_REG_0xF21, 0x68,common}, - {AX5043_REG_0xF22, 0XFF,common}, - {AX5043_REG_0xF23, 0x84,common}, - {AX5043_REG_0xF26, 0x98,common}, - {AX5043_REG_0xF34, 0x28,common}, - {AX5043_REG_0xF35, 0x11,common}, - {AX5043_REG_0xF44, 0x25,common}, - {AX5043_REG_PINFUNCIRQ, 0x03,common}, - {AX5043_REG_PKTSTOREFLAGS, 0x14,common}, - {AX5043_REG_PLLLOOP, 0x09,tx}, - {AX5043_REG_PLLCPI, 0x02,tx}, - {AX5043_REG_PLLVCODIV, 0x24,tx}, - {AX5043_REG_XTALCAP, 0x00,tx}, - {AX5043_REG_0xF00, 0x0F,tx}, - {AX5043_REG_0xF18, 0x06,tx}, - {AX5043_REG_PLLLOOP, 0x09,rx}, - {AX5043_REG_PLLCPI, 0x01,rx}, - {AX5043_REG_PLLVCODIV, 0x25,rx}, - {AX5043_REG_XTALCAP, 0x00,rx}, - {AX5043_REG_0xF00, 0x0F,rx}, - {AX5043_REG_0xF18, 0x02,rx}, - {AX5043_REG_TMGRXAGC, 0x00,rx_cont}, - {AX5043_REG_TMGRXPREAMBLE1, 0x00,rx_cont}, - {AX5043_REG_PKTMISCFLAGS, 0x00,rx_cont}, - {AX5043_REG_PKTADDR0, 0x32,local_address}, - {AX5043_REG_PKTADDR1, 0x34,local_address}, - {AX5043_REG_PKTADDR2, 0x00,local_address}, - {AX5043_REG_PKTADDR3, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK0, 0xFF,local_address}, - {AX5043_REG_PKTADDRMASK1, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK2, 0x00,local_address}, - {AX5043_REG_PKTADDRMASK3, 0x00,local_address}, - {AX5043_REG_END, 0x00,common} -}; - - -ax5043_confval_t conf_values[]={ - {AXRADIO_PHY_PN9 ,0}, - {AXRADIO_PHY_NRCHANNELS ,1}, - {AXRADIO_PHY_CHANFREQ ,0X0912AAAB }, - {AXRADIO_PHY_CHANPLLRNGINIT ,0X0A }, - {AXRADIO_PHY_CHANVCOIINIT ,0X98}, - {AXRADIO_PHY_CHANPLLRNG ,0}, - {AXRADIO_PHY_CHANVCOI ,0}, - {AXRADIO_PHY_VCOCALIB ,0}, - {AXRADIO_PHY_MAXFREQOFFSET ,913}, - {AXRADIO_PHY_RSSIOFFSET ,64}, - {AXRADIO_PHY_RSSIREFERENCE ,313}, - {AXRADIO_PHY_CHANNELBUSY ,-23}, - {AXRADIO_PHY_CS_PERIOD ,7}, - {AXRADIO_PHY_CS_ENABLED ,0}, - {AXRADIO_PHY_LBT_RETRIES ,0}, - {AXRADIO_PHY_LBT_FORCETX ,0}, - {AXRADIO_PHY_PREAMBLE_WOR_LONGLEN ,23}, - {AXRADIO_PHY_PREAMBLE_WOR_LEN ,184}, - {AXRADIO_PHY_PREAMBLE_LONGLEN ,0}, - {AXRADIO_PHY_PREAMBLE_LEN ,72}, - {AXRADIO_PHY_PREAMBLE_BYTE ,0X7E}, - {AXRADIO_PHY_PREAMBLE_FLAGS ,0X38}, - {AXRADIO_PHY_PREAMBLE_APPENDBITS ,0}, - {AXRADIO_PHY_PREAMBLE_APPENDPATTERN ,0X00}, - {AXRADIO_FRAMING_MACLEN ,3}, - {AXRADIO_FRAMING_ADDRLEN ,1}, - {AXRADIO_FRAMING_DESTADDRPOS ,0}, - {AXRADIO_FRAMING_SOURCEADDRPOS ,0XFF}, - {AXRADIO_FRAMING_LENPOS ,2}, - {AXRADIO_FRAMING_LENOFFS ,0}, - {AXRADIO_FRAMING_LENMASK ,0XFF}, - {AXRADIO_FRAMING_SWCRCLEN ,0}, - {AXRADIO_FRAMING_SYNCLEN ,32}, - {AXRADIO_FRAMING_SYNCWORD0 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD1 ,0XAA}, - {AXRADIO_FRAMING_SYNCWORD2 ,0XCC}, - {AXRADIO_FRAMING_SYNCWORD3 ,0XAA}, - {AXRADIO_FRAMING_SYNCFLAGS ,0X38}, - {AXRADIO_FRAMING_ENABLE_SFDCALLBACK ,0}, - {AXRADIO_FRAMING_ACK_TIMEOUT ,8}, - {AXRADIO_FRAMING_ACK_DELAY ,313}, - {AXRADIO_FRAMING_ACK_RETRANSMISSIONS ,0}, - {AXRADIO_FRAMING_ACK_SEQNRPOS ,0XFF}, - {AXRADIO_FRAMING_MINPAYLOADLEN ,0}, - {AXRADIO_WOR_PERIOD ,128}, - {AXRADIO_PHY_INNERFREQLOOP ,0}, - {AXRADIO_PHY_END ,0} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; - - -//Radio driver configurations - -static AX5043Config axcfg1 = -{ - &SPID2, - LINE_SX_INT0, - reg_values, - conf_values, - AX5043_MODE_TX, - &radio1_rx_mb -}; -AX5043Driver axd1; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - - // Creating the mailboxes. - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - - //initiating radio driver - ax5043ObjectInit(&axd1); - ax5043Start(&axd1, &axcfg1); - - - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending packet %d\r\n",pkt_counter); - transmit_packet(&axd1, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(3000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_driver/source/README.md b/src/archive/app_ax5043_driver/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_driver/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_driver/source/ax5043.c b/src/archive/app_ax5043_driver/source/ax5043.c deleted file mode 100644 index b9ceee88..00000000 --- a/src/archive/app_ax5043_driver/source/ax5043.c +++ /dev/null @@ -1,1065 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include -#include -#include "ch.h" -#include "hal.h" -//#include "chprintf.h" -#include "ax5043.h" - -//#define DEBUG_SERIAL SD2 -//#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -/** - * @brief Morse code for alphabets and numbers. - */ -static const char *alpha[] = { - ".-", //A - "-...", //B - "-.-.", //C - "-..", //D - ".", //E - "..-.", //F - "--.", //G - "....", //H - "..", //I - ".---", //J - "-.-", //K - ".-..", //L - "--", //M - "-.", //N - "---", //O - ".--.", //P - "--.-", //Q - ".-.", //R - "...", //S - "-", //T - "..-", //U - "...-", //V - ".--", //W - "-..-", //X - "-.--", //Y - "--..", //Z -}; - -static const char *num[] = { - "-----", //0 - ".----", //1 - "..---", //2 - "...--", //3 - "....-", //4 - ".....", //5 - "-....", //6 - "--...", //7 - "---..", //8 - "----.", //9 -}; - - -/** - * @brief Writes to an AX5043 register. - * - * @param[in] spip pointer to the @p SPIDriver object. - * @param[in] reg AX5043 register address. - * @param[in] value AX5043 register value. - * @param[out] ret_value Complete AX5043 returned value. - * - * @return Most significant status bit. - */ -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]){ - uint8_t command_buf[3] = {0,0,0}; - if(reg < 0x0070){ - command_buf[0]=0x80|reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - else{ - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - /*Retun status from Ax5043 while writting the register.*/ - return ret_value[0]; -} - -/** - * @brief Reads AX5043 register.. - * - * @param[in] spip pointer to the @p SPIDriver object. - * @param[in] reg AX5043 register address. - * @param[in] value AX5043 register value. - * @param[out] ret_value Complete AX5043 returned value. - * - * @return Register content. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]){ - uint8_t command_buf[3] = {0,0,0 }; - if(reg < 0x0070){ - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - /* Return the reg value when reading the register.*/ - return ret_value[1]; - } - else{ - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - /* Return the reg value when reading the register.*/ - return ret_value[2]; - } -} - -/** - * @brief Sets powermode register of AX5043. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] reg_value powermode register value. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_set_pwrmode(AX5043Driver *devp, uint8_t reg_value){ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - SPIDriver *spip = devp->config->spip; - - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | reg_value; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - devp->status_code = ret_value[0]; - /*Return last status from Ax5043 while writting the register. - Normal value is 0x80 0r 0x88*/ - return ret_value[0]; -} - -/** - * @brief Resets the AX5043. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_reset(AX5043Driver *devp){ - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - - /* Reset the chip through powermode register.*/ - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - - /* Write to powermode register for enabling XOEN and REFIN and shutdown mode. - Page 33 in programming manual.*/ - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA){ - devp->error_code = AXRADIO_ERR_NOT_CONNECTED; - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55){ - devp->error_code = AXRADIO_ERR_NOT_CONNECTED; - } - /*Return last status from Ax5043 while writting the register.*/ - return ret_value[0]; -} - -/** - * @brief Writes to AX5043 FIFO - * - * @param[in] spip pointer to the @p SPIDriver object. - * @param[in] ptr Pointer to array to be written to FIFO. - * @param[in] len length of array to be written to FIFO. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len){ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * @brief Reads to AX5043 FIFO - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] axradio_rxbuffer[] Pointer to array where the packet will be kept. - * @param[in] len Maximum length of array to be read FIFO. - * - * @param[out] Bytes read from FIFO. - */ -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t ret_value[3]={0,0,0}; - uint8_t bytes_read = 0; - while (len--) { - axradio_rxbuffer[bytes_read] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - bytes_read++; - } - return bytes_read; -} - -/** - * @brief Sets AX5043 registers. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] group register group that needs to be written. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_set_regs_group(AX5043Driver *devp, ax5043_reg_group_t group) { - uint8_t rxbuf[3] = {0, 0, 0}; - int i = 0; - ax5043_regval_t* entry = devp->config->reg_values; - while (entry[i].reg != AX5043_REG_END) { - if (entry[i].group == group){ - ax5043_write_reg(devp->config->spip, entry[i].reg, entry[i].val, rxbuf); - } - i++; - } - devp->status_code = rxbuf[0]; - /*Return last status from Ax5043 while writting the register.*/ - return rxbuf[0]; -} - -/** - * @brief Gets AX5043 register values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] reg_name register name. - * - * @return register value. - */ -uint8_t ax5043_get_reg_val(AX5043Driver *devp, uint16_t reg_name) { - int i = 0; - ax5043_regval_t* entry = devp->config->reg_values; - while (entry[i].reg != AX5043_REG_END) { - if (entry[i].reg == reg_name){ - return entry[i].val; - } - i++; - } - devp->error_code = AXRADIO_ERR_REG_NOT_IN_CONF; - return 0; -} - -/** - * @brief Gets AX5043 configuration values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] conf_name configuration variable name. - * - * @retrun value in configuration variable. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint32_t ax5043_get_conf_val(AX5043Driver *devp, uint8_t conf_name) { - int i = 0; - ax5043_confval_t* entry = devp->config->conf_values; - while (entry[i].conf_name != AXRADIO_PHY_END) { - if (entry[i].conf_name == conf_name){ - return entry[i].val; - } - i++; - } - devp->error_code = AXRADIO_ERR_VAL_NOT_IN_CONF; - return 0; -} - -/** - * @brief Sets AX5043 configuration values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] conf_name configuration variable name. - * @param[in] value value in configuration variable. - * - * @return 0 if successful, else 0x11. - */ -uint8_t ax5043_set_conf_val(AX5043Driver *devp, uint8_t conf_name, uint32_t value) { - int i = 0; - ax5043_confval_t* entry = devp->config->conf_values; - while (entry[i].conf_name != AXRADIO_PHY_END) { - if (entry[i].conf_name == conf_name){ - entry[i].val = value; - return 0; - } - i++; - } - devp->error_code = AXRADIO_ERR_VAL_NOT_IN_CONF; - return AXRADIO_ERR_VAL_NOT_IN_CONF; -} - -/** - * @brief prepare AX5043 for tx. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(AX5043Driver *devp){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - ax5043_set_pwrmode(devp, AX5043_FIFO_ENABLED); - ax5043_set_regs_group(devp,tx); - ax5043_init_registers_common(devp); - - /* Set FIFO threshold and interrupt mask.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - /* Wait for xtal.*/ - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - devp->status_code = ret_value[0]; - devp->state = AX5043_TX; -} - -/** - * @brief prepare AX5043 for rx. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(AX5043Driver *devp){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_regs_group(devp,rx); - ax5043_init_registers_common(devp); - - /* Updates RSSI reference value, Sets a group of RX registers.*/ - uint8_t rssireference = ax5043_get_conf_val(devp, AXRADIO_PHY_RSSIREFERENCE) ; - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, rssireference, ret_value); - ax5043_set_regs_group(devp,rx_cont); - /* Resets FIFO, changes powermode to FULL RX.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value); - ax5043_set_pwrmode(devp, AX5043_FULL_RX); - /* Sets FIFO threshold and interrupt mask.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - devp->status_code = ret_value[0]; - devp->state = AX5043_RX; -} - -/** - * @brief Does PLL ranging. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @returns PLLVCOI Register content. - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t axradio_get_pllvcoi(AX5043Driver *devp){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t x = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANVCOIINIT) ; - uint8_t pll_init_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNGINIT); - uint8_t pll_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - if (x & 0x80) { - if (!(pll_init_val & 0xF0)) { - x += (pll_val & 0x0F) - (pll_init_val & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - -/** - * @brief Initialized AX5043 registers common to RX and TX. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_init_registers_common(AX5043Driver *devp){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t rng = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - if (rng & 0x20) - devp->status_code = AXRADIO_ERR_PLLRNG_VAL; - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } - else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(devp); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - /** - * @brief Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO Standardize the error handling. - */ -void ax5043_init(AX5043Driver *devp){ - SPIDriver *spip = devp->config->spip; - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(devp); - - ax5043_set_regs_group(devp,common); - ax5043_set_regs_group(devp,tx); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - /* Wait for Xtal.*/ - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0){ - chThdSleepMilliseconds(1); - } - - /* Set frequency.*/ - uint32_t f = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANFREQ); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - /* PLL autoranging.*/ - uint8_t r; - uint8_t pll_init_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNGINIT); - if( !(pll_init_val & 0xF0) ) { // start values for ranging available - r = pll_init_val | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - int8_t value = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - ax5043_set_conf_val(devp, AXRADIO_PHY_CHANPLLRNG, value); - devp->state = AX5043_PLL_RANGE_DONE; - - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - ax5043_set_regs_group(devp,common); - ax5043_set_regs_group(devp,rx); - - uint8_t pll_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (pll_val & 0x0F), ret_value); - f = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANFREQ); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - ax5043_set_regs_group(devp,local_address); -} - - /** - * @brief Transmit loop to transmit bytes of a packet. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] packet_len Complete packet length including mac. - * @param[in] axradio_txbuffer pointer to packet. - * @param[in] packet_bytes_sent length before the packet. - * - * @api - * TODO Standardize the error handling, remove packet_bytes_sent, simplify the code. - */ -void transmit_loop(AX5043Driver *devp, uint16_t packet_len,uint8_t axradio_txbuffer[]){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t free_fifo_bytes; - uint8_t packet_end_indicator = 0; - uint16_t packet_bytes_sent = 0; - uint8_t flags = 0; - uint16_t packet_len_to_be_sent = 0; - uint8_t synclen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCLEN); - - while (packet_end_indicator == 0) { - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - free_fifo_bytes = 0xff; - else - free_fifo_bytes = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - /* Make sure sixteen bytes in FIFO are free. We can do with minimum 4 bytes free but taking in 16 here.*/ - if (free_fifo_bytes < 19) { - /* FIFO commit.*/ - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); - continue; - } - - switch (devp->state) { - case AX5043_TX_LONGPREAMBLE: - if (!packet_bytes_sent) { - devp->state = AX5043_TX_SHORTPREAMBLE; - packet_bytes_sent = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_LEN); - break; - } - - free_fifo_bytes = 7; - if (packet_bytes_sent < 7) - free_fifo_bytes = packet_bytes_sent; - packet_bytes_sent -= free_fifo_bytes; - free_fifo_bytes <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_FLAGS), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, free_fifo_bytes, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE), ret_value); - break; - - case AX5043_TX_SHORTPREAMBLE: - if (!packet_bytes_sent) { - uint8_t preamble_appendbits = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_APPENDBITS); - if (preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_APPENDPATTERN); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-preamble_appendbits); - byte |= 0x80 >> preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-preamble_appendbits); - byte |= 0x01 << preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && synclen) { - /* Write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS. - Chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT).*/ - int8_t len_byte = synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - /* SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits.*/ - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCFLAGS) | i, ret_value); - - uint8_t syncword[4] = {ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD0), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD1), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD2), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD3)}; - for (i = 0; i < len_byte; ++i) { - ax5043_write_reg(spip,AX5043_REG_FIFODATA, syncword[i], ret_value); - } - } - devp->state = AX5043_TX_PACKET; - continue; - } - free_fifo_bytes = 255; - if (packet_bytes_sent < 255*8) - free_fifo_bytes = packet_bytes_sent >> 3; - if (free_fifo_bytes) { - packet_bytes_sent -= ((uint16_t)free_fifo_bytes) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_FLAGS), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, free_fifo_bytes, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE), ret_value); - continue; - } - { - uint8_t byte = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE) ; - free_fifo_bytes = packet_bytes_sent; - packet_bytes_sent = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - /* MSB first -> stop bit below.*/ - byte &= 0xFF << (8-free_fifo_bytes); - byte |= 0x80 >> free_fifo_bytes; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-free_fifo_bytes); - byte |= 0x01 << free_fifo_bytes; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case AX5043_TX_PACKET: - flags = 0; - packet_len_to_be_sent = 0; - if (!packet_bytes_sent) - /* Flag byte indicates packetstart.*/ - flags |= 0x01; - - packet_len_to_be_sent = packet_len - packet_bytes_sent; - /* 3 bytes of FIFO commands are written before payload can be written to FIFO.*/ - if (free_fifo_bytes >= packet_len_to_be_sent + 3) { - /* Flag byte indicates packet end.*/ - flags |= 0x02; - } - else{ - packet_len_to_be_sent = free_fifo_bytes - 3; - } - - - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - /* Write FIFO chunk length byte. Length includes the flag byte, thus the +1.*/ - ax5043_write_reg(spip,AX5043_REG_FIFODATA, packet_len_to_be_sent + 1, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[packet_bytes_sent], packet_len_to_be_sent); - packet_bytes_sent += packet_len_to_be_sent; - if (flags & 0x02){ - packet_end_indicator = 1; - /* Enable radio event done (REVRDONE) event.*/ - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - } - break; - - default: - packet_end_indicator = 1; - devp->error_code = AXRADIO_ERR_UNEXPECTED_STATE; - } - } - devp->state = AX5043_TX; -} - -/** - * @brief Transmits a packet. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] addr remote destination address of packet. - * @param[in] pkt pointer to packet. - * @param[in] pktlen packet length. - * - * @param[out] AXRADIO_ERR Error code. - * - * @api - * TODO Standardize the error handling, Maybe move address to a driver config structure - */ -uint8_t transmit_packet(AX5043Driver *devp, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) { - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - uint16_t packet_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - uint8_t axradio_localaddr[4]; - - uint8_t maclen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_MACLEN); - uint8_t destaddrpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_DESTADDRPOS); - uint8_t addrlen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_ADDRLEN); - uint8_t sourceaddrpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_SOURCEADDRPOS); - uint8_t lenmask = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENMASK); - uint8_t lenoffs = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENOFFS); - uint8_t lenpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENPOS); - - axradio_localaddr[0] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR0); - axradio_localaddr[1] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR1); - axradio_localaddr[2] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR2); - axradio_localaddr[3] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR3); - - packet_len = pktlen + maclen; - if (packet_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - - /* Prepare the MAC segment of the packet.*/ - memset(axradio_txbuffer, 0, maclen); - memcpy(&axradio_txbuffer[maclen], pkt, pktlen); - if (destaddrpos != 0xff) - memcpy(&axradio_txbuffer[destaddrpos], &addr->addr, addrlen); - if (sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[sourceaddrpos], axradio_localaddr, addrlen); - if (lenmask) { - /* Calculate payload length and update the MAC of payload.*/ - uint8_t len_byte = (uint8_t)(packet_len - lenoffs) & lenmask; - axradio_txbuffer[lenpos] = (axradio_txbuffer[lenpos] & (uint8_t)~lenmask) | len_byte; - } - /*Clear radioevent flag. This indicator is set when packet is out.*/ - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - /* Clear leftover FIFO data & flags.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); - devp->state = AX5043_TX_LONGPREAMBLE; - - /*Code for 4-FSK mode.*/ - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - /* Length including flags.*/ - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); - /* Flag PKTSTART -> dibit sync.*/ - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); - /* Dummy byte for forcing dibit sync.*/ - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); - } - transmit_loop(devp, packet_len, axradio_txbuffer); - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - devp->error_code = AXRADIO_ERR_NOERROR; - return AXRADIO_ERR_NOERROR; -} - -/** - * @brief Receive loop to recieve bytes from FIFO. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[out] axradio_rxbuffer[] Pointer to array where the packet will be kept. - * - * @return Length of packet received. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t receive_loop(AX5043Driver *devp, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - uint8_t fifo_cmd; - uint8_t i; - uint8_t chunk_len; - uint8_t bytesRead = 0; - - /* Clear interrupt.*/ - ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - devp->state = AX5043_RX_LOOP; - /* Loop until FIFO not empty.*/ - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { - /* FIFO read comman.*/ - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - /* Top 3 bits encode payload length.*/ - chunk_len = (fifo_cmd & 0xE0) >> 5; - /* 7 means variable length, get length byte from next read.*/ - if (chunk_len == 7) - chunk_len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (chunk_len!=0){ - /* Discard the flag.*/ - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chunk_len = chunk_len - 1; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, chunk_len); - } - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (chunk_len == 3){ - devp->rf_freq_off3 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->rf_freq_off2 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->rf_freq_off1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - } - else{ - for(i=0;idropped[i] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (chunk_len == 2){ - devp->rf_freq_off3 = 0; - devp->rf_freq_off2 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->rf_freq_off1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - } - else{ - for(i=0;idropped[i] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - case AX5043_FIFOCMD_RSSI: - if (chunk_len == 1){ - devp->rssi = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - } - else{ - for(i=0;idropped[i] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - default: - devp->error_code = AXRADIO_ERR_FIFO_CMD; - for(i=0;idropped[i] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - } - } - devp->state = AX5043_RX; - } - return bytesRead; -} - -/** - * @brief Prepare for CW mode - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @return Length of packet received. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t ax5043_prepare_cw(AX5043Driver *devp){ - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x01, ret_value); - - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - - /* This is not mentioned in datasheet or programming manual but is required. - * Removing this will make the transmission to transmit in low power for a few seconds - * before it reaches peak power.*/ - /* FIFO reset.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_FIFOCMD_REPEATDATA|0x60), ret_value); - /* Preamble flag.*/ - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xff, ret_value); - /* Preamble.*/ - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); - /* FIFO Commit.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value); - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - devp->state = AX5043_CW; - return 0; -} - -/** - * @brief Send Morse dot and dash over the air - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] dot_dash_time time in milliseconds for transmiter to be on. - */ -void ax5043_morse_dot_dash(AX5043Driver *devp, uint16_t dot_dash_time){ - - uint8_t ret_value[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_FIFOCMD_REPEATDATA|0x60), ret_value); - /* Preamble flag.*/ - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - /* Preamble.*/ - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - /* FIFO Commit.*/ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value); - chThdSleepMilliseconds(dot_dash_time); - ax5043_set_pwrmode(devp, AX5043_STANDBY); - -} - -/** - * @brief Convert an alphabet or number to morse dot and dash - * - * @param[in] letter An alphabet or number. - * - * @return Length of packet received. - */ -const char *ax5043_ascii_to_morse(char letter){ - letter = tolower(letter); - - if (isalpha(letter)){ - return alpha[letter-'a']; - } - else if (isdigit(letter)){ - return num[letter-'0']; - } - - return SPACE; -} - -/** - * @brief Convert a message to morse code and transmit it. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] wpm words per minute. - * @param[in] beaconMessage Message to be transmitted. - * @param[in] pktlen Length of packet/beacon message. - */ -void ax5043_send_cw(AX5043Driver *devp, int wpm, char beaconMessage[], uint16_t pktlen ){ - int element; - int index = 0; - const char *morse; - - uint16_t ditLength = 1200/wpm; - uint16_t letter_space = ditLength*3; - uint16_t word_space = ditLength*7; - uint16_t element_space = ditLength; - uint16_t dash = ditLength*3; - - while (index < pktlen){ - morse = ax5043_ascii_to_morse(beaconMessage[index]); - - element = 0; - while (morse[element] != '\0'){ - switch(morse[element]){ - case '-': - ax5043_morse_dot_dash(devp, dash); - break; - case '.': - ax5043_morse_dot_dash(devp, ditLength); - break; - } - - if (morse[element] == ' '){ - chThdSleepMilliseconds(word_space); - } - else if (morse[element+1] != '\0'){ - chThdSleepMilliseconds(element_space); - } - else if (morse[element+1] == '\0'){ - chThdSleepMilliseconds(letter_space); - } - element++; - } - - index++; - } -} -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct AX5043VMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance. Radio is still uninitialized. - * - * @param[out] devp pointer to the @p AX5043Driver object - * - * @init - */ -void ax5043ObjectInit(AX5043Driver *devp) { - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = AX5043_UNINIT; -} - -/** - * @brief Configures and activates the AX5043 Radio Driver. - * - * @param[in] devp pointer to the @p AX5043Driver object - * @param[in] config pointer to the @p AX5043Config object - */ -void ax5043Start(AX5043Driver *devp, const AX5043Config *config) { - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == AX5043_UNINIT) || - (devp->state == AX5043_READY), - "ax5043Start(), invalid state"); - - devp->config = config; - devp->rf_freq_off3 = 0; - devp->rf_freq_off2 = 0; - devp->rf_freq_off1 = 0; - devp->rssi = 0; - devp->error_code = 0; - devp->status_code = 0; - - ax5043_init(devp); - switch(config->ax5043_mode) { - case AX5043_MODE_RX: - ax5043_prepare_rx(devp); - break; - case AX5043_MODE_TX: - ax5043_prepare_tx(devp); - break; - case AX5043_MODE_CW: - ax5043_prepare_cw(devp); - break; - case AX5043_MODE_OFF: - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - break; - default: - ax5043_prepare_rx(devp); - } -} - -/** - * @brief Stops the AX5043 Radio Driver. - * - * @param[in] devp pointer to the @p AX5043Driver object - */ -void ax5043Stop(AX5043Driver *devp) { - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - devp->state = AX5043_OFF; - /* TODO: verify if additional driver things needs to be done.*/ - devp->state = AX5043_STOP; -} - -//!@ diff --git a/src/archive/app_ax5043_driver/source/ax5043.h b/src/archive/app_ax5043_driver/source/ax5043.h deleted file mode 100644 index 9853717a..00000000 --- a/src/archive/app_ax5043_driver/source/ax5043.h +++ /dev/null @@ -1,732 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr); -void ax5043_set_local_addr(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_rx/Makefile b/src/archive/app_ax5043_engr_rx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_engr_rx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_engr_rx/README.md b/src/archive/app_ax5043_engr_rx/README.md deleted file mode 100644 index 251e4488..00000000 --- a/src/archive/app_ax5043_engr_rx/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_FulDuplex_ground - -This is used to transmit semtech radio packets signal. -This creates a instruction packet at 735.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_engr_rx/conf/chconf.h b/src/archive/app_ax5043_engr_rx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_engr_rx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_rx/conf/halconf.h b/src/archive/app_ax5043_engr_rx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_engr_rx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_rx/conf/mcuconf.h b/src/archive/app_ax5043_engr_rx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_engr_rx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_engr_rx/main.c b/src/archive/app_ax5043_engr_rx/main.c deleted file mode 100644 index dce9c29d..00000000 --- a/src/archive/app_ax5043_engr_rx/main.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - - -const struct axradio_address remoteaddr_tx = { - { 0x32, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x33, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0 -}; - - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - - - - - - //uint16_t reg=0; - //uint8_t value=0; - //uint8_t value1=0x55; - //uint8_t ret_value[3]={0,0,0}; - //int i; - - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - ax5043_set_addr(&SPID2, localaddr_tx); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - - - - ax5043_prepare_rx(&SPID2); - - - - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - uint8_t packet_len=0; - uint8_t ret_value[3]={0,0,0}; - - /* Enabling events on both edges of the button line.*/ - //palEnableLineEvent(LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE); - palEnableLineEvent(LINE_SX_INT0, PAL_EVENT_MODE_RISING_EDGE); - - - while(true) - { - //palWaitLineTimeout(LINE_BUTTON, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_MS2I(5000)); - - palWaitLineTimeout(LINE_SX_INT0, TIME_MS2I(5000)); - - if (palReadLine(LINE_SX_INT0)) - chprintf(DEBUG_CHP, "\r\r int line is HIGH ** \r\n"); - else - chprintf(DEBUG_CHP, "\r\r int line is LOW ** \r\n"); - - packet_len=receive_loop(&SPID2, axradio_rxbuffer); - - if(packet_len > 0) - chprintf(DEBUG_CHP,"INFO: Received packet %d\r\n",axradio_rxbuffer[3]); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_engr_rx/source/README.md b/src/archive/app_ax5043_engr_rx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_engr_rx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_engr_rx/source/ax5043.c b/src/archive/app_ax5043_engr_rx/source/ax5043.c deleted file mode 100644 index 6e730683..00000000 --- a/src/archive/app_ax5043_engr_rx/source/ax5043.c +++ /dev/null @@ -1,1175 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_phy_channelbusy = -87 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 184; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 72; -const uint8_t axradio_phy_preamble_byte = 0x7e; -const uint8_t axradio_phy_preamble_flags = 0x38; -const uint8_t axradio_phy_preamble_appendbits = 0; -const uint8_t axradio_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 3; -const uint8_t axradio_framing_addrlen = 1; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 0; -const uint8_t axradio_framing_lenmask = 0xff; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; -const uint8_t axradio_phy_innerfreqloop = 0; - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - //chprintf(DEBUG_CHP,"INFO: Write Reg 0x%x status: 0x%x %x %x \r\n", reg, ret_value[0], ret_value[1], ret_value[2]); - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP,"INFO: Read Reg 0x%x status: 0x%x %x %x \r\n", reg, ret_value[0], ret_value[1], ret_value[2]); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP,"INFO: Read Reg 0x%x status: 0x%x %x %x \r\n", reg, ret_value[0], ret_value[1], ret_value[2]); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x14, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - //ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - //chThdSleepMilliseconds(10); - - -} - - -/** - * sets AX5043 address registers - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr) -{ - uint8_t ret_value[3]={0,0,0}; - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)local_addr.addr[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)local_addr.addr[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)local_addr.addr[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)local_addr.addr[3], ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)local_addr.mask[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)local_addr.mask[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)local_addr.mask[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)local_addr.mask[3], ret_value); -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - //ax5043_set_local_addr(spip); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - //ax5043_set_local_addr(spip); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * The logic is similar to transmit_isr() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Logic similar to axradio_transmit() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - //ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - //chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - - -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown FIFO cmd %x \r\n", fifo_cmd); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - int8_t data; - data = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);// purge FIFO - chprintf(DEBUG_CHP,"Unknown: %x \r\n", data); - } - while (--i); - break; - } - } - - //chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_rx/source/ax5043.h b/src/archive/app_ax5043_engr_rx/source/ax5043.h deleted file mode 100644 index 9853717a..00000000 --- a/src/archive/app_ax5043_engr_rx/source/ax5043.h +++ /dev/null @@ -1,732 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr); -void ax5043_set_local_addr(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx/Makefile b/src/archive/app_ax5043_engr_tx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_engr_tx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_engr_tx/README.md b/src/archive/app_ax5043_engr_tx/README.md deleted file mode 100644 index fbb1fadd..00000000 --- a/src/archive/app_ax5043_engr_tx/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_ax5043_HDLC_FEC_tx - -This is used to transmit sax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_engr_tx/conf/chconf.h b/src/archive/app_ax5043_engr_tx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_engr_tx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx/conf/halconf.h b/src/archive/app_ax5043_engr_tx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_engr_tx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx/conf/mcuconf.h b/src/archive/app_ax5043_engr_tx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_engr_tx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_engr_tx/main.c b/src/archive/app_ax5043_engr_tx/main.c deleted file mode 100644 index 78124fe1..00000000 --- a/src/archive/app_ax5043_engr_tx/main.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x32, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 1; -const uint8_t framing_counter_pos = 0; - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - - //uint16_t reg=0; - //uint8_t value=0; - //uint8_t value1=0x55; - //uint8_t ret_value[3]={0,0,0}; - //int i; - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - ax5043_set_addr(&SPID2, localaddr_tx); - ax5043_prepare_tx(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending packet %d\r\n",pkt_counter); - transmit_packet(&SPID2, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(3000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_engr_tx/source/README.md b/src/archive/app_ax5043_engr_tx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_engr_tx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_engr_tx/source/ax5043.c b/src/archive/app_ax5043_engr_tx/source/ax5043.c deleted file mode 100644 index a4a5ab4b..00000000 --- a/src/archive/app_ax5043_engr_tx/source/ax5043.c +++ /dev/null @@ -1,1171 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_phy_channelbusy = -87 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 184; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 72; -const uint8_t axradio_phy_preamble_byte = 0x7e; -const uint8_t axradio_phy_preamble_flags = 0x38; -const uint8_t axradio_phy_preamble_appendbits = 0; -const uint8_t axradio_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 3; -const uint8_t axradio_framing_addrlen = 1; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 0; -const uint8_t axradio_framing_lenmask = 0xff; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; -const uint8_t axradio_phy_innerfreqloop = 0; - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x14, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - //ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - //chThdSleepMilliseconds(10); - - -} - - -/** - * sets AX5043 address registers - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr) -{ - uint8_t ret_value[3]={0,0,0}; - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)local_addr.addr[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)local_addr.addr[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)local_addr.addr[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)local_addr.addr[3], ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)local_addr.mask[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)local_addr.mask[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)local_addr.mask[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)local_addr.mask[3], ret_value); -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - //ax5043_set_local_addr(spip); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - //ax5043_set_local_addr(spip); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * The logic is similar to transmit_isr() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Logic similar to axradio_transmit() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - //ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - //chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - - -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown FIFO cmd %x \r\n", fifo_cmd); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - int8_t data; - data = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);// purge FIFO - chprintf(DEBUG_CHP,"Unknown: %x \r\n", data); - } - while (--i); - break; - } - } - - //chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx/source/ax5043.h b/src/archive/app_ax5043_engr_tx/source/ax5043.h deleted file mode 100644 index 9853717a..00000000 --- a/src/archive/app_ax5043_engr_tx/source/ax5043.h +++ /dev/null @@ -1,732 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr); -void ax5043_set_local_addr(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx_clean/Makefile b/src/archive/app_ax5043_engr_tx_clean/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_engr_tx_clean/README.md b/src/archive/app_ax5043_engr_tx_clean/README.md deleted file mode 100644 index fbb1fadd..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_ax5043_HDLC_FEC_tx - -This is used to transmit sax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_engr_tx_clean/conf/chconf.h b/src/archive/app_ax5043_engr_tx_clean/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx_clean/conf/halconf.h b/src/archive/app_ax5043_engr_tx_clean/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx_clean/conf/mcuconf.h b/src/archive/app_ax5043_engr_tx_clean/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_engr_tx_clean/main.c b/src/archive/app_ax5043_engr_tx_clean/main.c deleted file mode 100644 index b0629328..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/main.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043_common.h" -#include "ax5043_engr.h" - - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x32, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 1; -const uint8_t framing_counter_pos = 0; - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - - uint16_t pkt_counter = 0; - - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - - //uint16_t reg=0; - //uint8_t value=0; - //uint8_t value1=0x55; - //uint8_t ret_value[3]={0,0,0}; - //int i; - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - ax5043_set_addr(&SPID2, localaddr_tx); - ax5043_prepare_tx(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending packet %d\r\n",pkt_counter); - transmit_packet(&SPID2, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(3000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_engr_tx_clean/source/README.md b/src/archive/app_ax5043_engr_tx_clean/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.c b/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.c deleted file mode 100644 index e0b1e7e2..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.c +++ /dev/null @@ -1,326 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043_common.h" - - - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * sets AX5043 address registers - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr) -{ - uint8_t ret_value[3]={0,0,0}; - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)local_addr.addr[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)local_addr.addr[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)local_addr.addr[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)local_addr.addr[3], ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)local_addr.mask[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)local_addr.mask[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)local_addr.mask[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)local_addr.mask[3], ret_value); -} - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - //ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - //chThdSleepMilliseconds(10); - - -} - - - - - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - //chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.h b/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.h deleted file mode 100644 index 889a88a2..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_common.h +++ /dev/null @@ -1,712 +0,0 @@ -/*! \file ax5043_common.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_COMMON_H -#define _AX5043_COMMON_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr); -void ax5043_reset(SPIDriver * spip); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.c b/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.c deleted file mode 100644 index 53651c41..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.c +++ /dev/null @@ -1,849 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043_common.h" -#include "ax5043_engr.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_phy_channelbusy = -87 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 184; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 72; -const uint8_t axradio_phy_preamble_byte = 0x7e; -const uint8_t axradio_phy_preamble_flags = 0x38; -const uint8_t axradio_phy_preamble_appendbits = 0; -const uint8_t axradio_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 3; -const uint8_t axradio_framing_addrlen = 1; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 0; -const uint8_t axradio_framing_lenmask = 0xff; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; -const uint8_t axradio_phy_innerfreqloop = 0; - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x14, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - - - - - - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - //ax5043_set_local_addr(spip); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - //ax5043_set_local_addr(spip); - -} - - - - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet - * The logic is similar to transmit_isr() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Logic similar to axradio_transmit() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - //ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown FIFO cmd %x \r\n", fifo_cmd); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - int8_t data; - data = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);// purge FIFO - chprintf(DEBUG_CHP,"Unknown: %x \r\n", data); - } - while (--i); - break; - } - } - - //chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.h b/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.h deleted file mode 100644 index 711e9f74..00000000 --- a/src/archive/app_ax5043_engr_tx_clean/source/ax5043_engr.h +++ /dev/null @@ -1,34 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_ENGR_H -#define _AX5043_ENGR_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); -void ax5043_init(SPIDriver * spip); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -uint8_t receive_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/Makefile b/src/archive/app_ax5043_engr_tx_full_duplex/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/README.md b/src/archive/app_ax5043_engr_tx_full_duplex/README.md deleted file mode 100644 index fbb1fadd..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_ax5043_HDLC_FEC_tx - -This is used to transmit sax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/conf/chconf.h b/src/archive/app_ax5043_engr_tx_full_duplex/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/conf/halconf.h b/src/archive/app_ax5043_engr_tx_full_duplex/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/conf/mcuconf.h b/src/archive/app_ax5043_engr_tx_full_duplex/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/main.c b/src/archive/app_ax5043_engr_tx_full_duplex/main.c deleted file mode 100644 index 98b66e18..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/main.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043_common.h" -#include "ax5043_engr_f1.h" -#include "ax5043_engr_f2.h" - - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x32, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} -}; - -uint8_t axradio_rxbuffer[256]; //buffer to receive radio data - -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3A, 0x43, 0x51, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3A, 0x54, 0x65, 0x73, 0x74, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x31 }; -const uint8_t framing_insert_counter = 1; -const uint8_t framing_counter_pos = 0; - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); -} - - - - -THD_WORKING_AREA(waAx5043_rx, 1024); -THD_FUNCTION(ax5043_rx, arg) -{ - (void)arg; - uint8_t packet_len=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_f2_init(&SPID1); - ax5043_set_addr(&SPID1, localaddr_tx); - chprintf(DEBUG_CHP, "done reseting AX5043 rx \r\n"); - chThdSleepMilliseconds(50); - - ax5043_f2_init(&SPID1); - ax5043_f2_prepare_rx(&SPID1); - - /* Enabling events on both edges of the button line.*/ - //palEnableLineEvent(LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE); - palEnableLineEvent(LINE_SX_INT0, PAL_EVENT_MODE_RISING_EDGE); - - - - //palWaitLineTimeout(LINE_BUTTON, TIME_INFINITE); - //palWaitLineTimeout(LINE_ARD_A5, TIME_INFINITE); - while(true) - { - palWaitLineTimeout(LINE_SX_INT0, TIME_MS2I(5000)); - - if (palReadLine(LINE_SX_INT0)) - chprintf(DEBUG_CHP, "\r\r int line is HIGH ** \r\n"); - else - chprintf(DEBUG_CHP, "\r\r int line is LOW ** \r\n"); - - packet_len=receive_f2_loop(&SPID1, axradio_rxbuffer); - - if(packet_len > 0) - chprintf(DEBUG_CHP,"INFO: Received packet %d\r\n",axradio_rxbuffer[3]); - } - - -} - - -THD_WORKING_AREA(waAx5043_tx, 1024); -THD_FUNCTION(ax5043_tx, arg) -{ - (void)arg; - uint16_t pkt_counter = 0; - - chThdSleepMilliseconds(500); - ax5043_f1_init(&SPID2); - ax5043_set_addr(&SPID2, localaddr_tx); - ax5043_f1_prepare_tx(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043 tx\r\n"); - - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending packet %d\r\n",pkt_counter); - transmit_f1_packet(&SPID2, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(5000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(15000); - chprintf(DEBUG_CHP, "."); - //palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - chThdCreateStatic(waAx5043_rx, sizeof(waAx5043_rx), NORMALPRIO, ax5043_rx, NULL); - chThdSleepMilliseconds(5000); - chThdCreateStatic(waAx5043_tx, sizeof(waAx5043_tx), NORMALPRIO, ax5043_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/README.md b/src/archive/app_ax5043_engr_tx_full_duplex/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.c b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.c deleted file mode 100644 index e8431a62..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.c +++ /dev/null @@ -1,323 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043_common.h" - - - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - //uint8_t rx_buf[2]={0 ,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * sets AX5043 address registers - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr) -{ - uint8_t ret_value[3]={0,0,0}; - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)local_addr.addr[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)local_addr.addr[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)local_addr.addr[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)local_addr.addr[3], ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)local_addr.mask[0], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)local_addr.mask[1], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)local_addr.mask[2], ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)local_addr.mask[3], ret_value); -} - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(1); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - //ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - //chThdSleepMilliseconds(10); - - -} - - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - - - -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t loc = 0; - while (len--) { - axradio_rxbuffer[loc] = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - //chprintf(DEBUG_CHP,"Packet: %x \r\n", axradio_rxbuffer[loc]); - loc++; - } - return loc; -} - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.h b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.h deleted file mode 100644 index 889a88a2..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_common.h +++ /dev/null @@ -1,712 +0,0 @@ -/*! \file ax5043_common.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_COMMON_H -#define _AX5043_COMMON_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_set_addr(SPIDriver * spip, const struct axradio_address_mask local_addr); -void ax5043_reset(SPIDriver * spip); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) ; - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.c b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.c deleted file mode 100644 index 1936d185..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.c +++ /dev/null @@ -1,845 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043_common.h" -#include "ax5043_engr_f1.h" - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_f1_phy_pn9 = 0; -const uint8_t axradio_f1_phy_nrchannels = 1; -const uint32_t axradio_f1_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_f1_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_f1_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_f1_phy_chanpllrng[1]; -uint8_t axradio_f1_phy_chanvcoi[1]; -const uint8_t axradio_f1_phy_vcocalib = 0; -const int32_t axradio_f1_phy_maxfreqoffset = 913; -const int8_t axradio_f1_phy_rssioffset = 64; -// axradio_f1_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_f1_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_f1_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_f1_phy_channelbusy = -87 + 64; -const uint16_t axradio_f1_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_f1_phy_cs_enabled = 0; -const uint8_t axradio_f1_phy_lbt_retries = 0; -const uint8_t axradio_f1_phy_lbt_forcetx = 0; -const uint16_t axradio_f1_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_f1_phy_preamble_wor_len = 184; -const uint16_t axradio_f1_phy_preamble_longlen = 0; -const uint16_t axradio_f1_phy_preamble_len = 72; -const uint8_t axradio_f1_phy_preamble_byte = 0x7e; -const uint8_t axradio_f1_phy_preamble_flags = 0x38; -const uint8_t axradio_f1_phy_preamble_appendbits = 0; -const uint8_t axradio_f1_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_f1_framing_maclen = 3; -const uint8_t axradio_f1_framing_addrlen = 1; -const uint8_t axradio_f1_framing_destaddrpos = 0; -const uint8_t axradio_f1_framing_sourceaddrpos = 0xff; -const uint8_t axradio_f1_framing_lenpos = 2; -const uint8_t axradio_f1_framing_lenoffs = 0; -const uint8_t axradio_f1_framing_lenmask = 0xff; -const uint8_t axradio_f1_framing_swcrclen = 0; - -const uint8_t axradio_f1_framing_synclen = 32; -const uint8_t axradio_f1_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_f1_framing_syncflags = 0x38; -const uint8_t axradio_f1_framing_enable_sfdcallback = 0; - -const uint32_t axradio_f1_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_f1_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_f1_framing_ack_retransmissions = 0; -const uint8_t axradio_f1_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_f1_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_f1_wor_period = 128; -const uint8_t axradio_f1_phy_innerfreqloop = 0; - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_f1_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x14, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - - - - - - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_f1_set_regs_tx(spip); - ax5043_f1_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - //ax5043_f1_set_local_addr(spip); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_f1_set_regs_rx(spip); - ax5043_f1_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_f1_phy_rssireference, ret_value); - ax5043_f1_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - //ax5043_f1_set_local_addr(spip); - -} - - - - -uint8_t axradio_f1_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_f1_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_f1_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_f1_phy_chanpllrng[0] & 0x0F) - (axradio_f1_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - - - void ax5043_f1_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_f1_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_f1_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f1_init(SPIDriver * spip) -{ - - - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); - - - //ax5043_shutdown(spip); - ax5043_f1_set_regs(spip); - ax5043_f1_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_f1_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - - //PLL autoranging - uint8_t r; - if( !(axradio_f1_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_f1_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_f1_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_f1_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_f1_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_f1_set_regs(spip); - ax5043_f1_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_f1_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_f1_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet - * The logic is similar to transmit_isr() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_f1_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_f1_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_f1_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_f1_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_f1_phy_preamble_appendbits); - byte |= 0x80 >> axradio_f1_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_f1_phy_preamble_appendbits); - byte |= 0x01 << axradio_f1_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_f1_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_f1_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f1_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_f1_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Logic similar to axradio_transmit() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_f1_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_f1_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_f1_framing_maclen); - memcpy(&axradio_txbuffer[axradio_f1_framing_maclen], pkt, pktlen); - if (axradio_f1_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_f1_framing_destaddrpos], &addr->addr, axradio_f1_framing_addrlen); - if (axradio_f1_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_f1_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_f1_framing_addrlen); - if (axradio_f1_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_f1_framing_lenoffs) & axradio_f1_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_f1_framing_lenpos] = (axradio_txbuffer[axradio_f1_framing_lenpos] & (uint8_t)~axradio_f1_framing_lenmask) | len_byte; - } -/* - if (axradio_f1_framing_swcrclen) - axradio_txbuffer_len = axradio_f1_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_f1_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_f1_phy_preamble_longlen; -*/ - //ax5043_f1_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_f1_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - -uint8_t receive_f1_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_f1_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_f1_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown FIFO cmd %x \r\n", fifo_cmd); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - int8_t data; - data = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);// purge FIFO - chprintf(DEBUG_CHP,"Unknown: %x \r\n", data); - } - while (--i); - break; - } - } - - //chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.h b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.h deleted file mode 100644 index 88e4ecfb..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f1.h +++ /dev/null @@ -1,34 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_ENGR_F1_H -#define _AX5043_ENGR_F1_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - -void ax5043_f1_set_regs(SPIDriver * spip); -void ax5043_f1_set_regs_tx(SPIDriver * spip); -void ax5043_f1_set_regs_rx(SPIDriver * spip); -void ax5043_f1_set_regs_rxcont(SPIDriver * spip); -void ax5043_f1_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_f1_prepare_tx(SPIDriver * spip); -void ax5043_f1_prepare_rx(SPIDriver * spip); -uint8_t axradio_f1_get_pllvcoi(SPIDriver * spip); -void ax5043_f1_init_registers_common(SPIDriver * spip); -void ax5043_f1_init(SPIDriver * spip); -void transmit_f1_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -uint8_t transmit_f1_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -uint8_t receive_f1_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.c b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.c deleted file mode 100644 index 076cec2e..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.c +++ /dev/null @@ -1,844 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043_common.h" -#include "ax5043_engr_f2.h" - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_f2_phy_pn9 = 0; -const uint8_t axradio_f2_phy_nrchannels = 1; -const uint32_t axradio_f2_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_f2_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_f2_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_f2_phy_chanpllrng[1]; -uint8_t axradio_f2_phy_chanvcoi[1]; -const uint8_t axradio_f2_phy_vcocalib = 0; -const int32_t axradio_f2_phy_maxfreqoffset = 913; -const int8_t axradio_f2_phy_rssioffset = 64; -// axradio_f2_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_f2_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_f2_phy_rssireference = (int8_t)(0xF9 + 64); -const int8_t axradio_f2_phy_channelbusy = -87 + 64; -const uint16_t axradio_f2_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_f2_phy_cs_enabled = 0; -const uint8_t axradio_f2_phy_lbt_retries = 0; -const uint8_t axradio_f2_phy_lbt_forcetx = 0; -const uint16_t axradio_f2_phy_preamble_wor_longlen = 23; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_f2_phy_preamble_wor_len = 184; -const uint16_t axradio_f2_phy_preamble_longlen = 0; -const uint16_t axradio_f2_phy_preamble_len = 72; -const uint8_t axradio_f2_phy_preamble_byte = 0x7e; -const uint8_t axradio_f2_phy_preamble_flags = 0x38; -const uint8_t axradio_f2_phy_preamble_appendbits = 0; -const uint8_t axradio_f2_phy_preamble_appendpattern = 0x00; - -//framing variables generated from radiolab -const uint8_t axradio_f2_framing_maclen = 3; -const uint8_t axradio_f2_framing_addrlen = 1; -const uint8_t axradio_f2_framing_destaddrpos = 0; -const uint8_t axradio_f2_framing_sourceaddrpos = 0xff; -const uint8_t axradio_f2_framing_lenpos = 2; -const uint8_t axradio_f2_framing_lenoffs = 0; -const uint8_t axradio_f2_framing_lenmask = 0xff; -const uint8_t axradio_f2_framing_swcrclen = 0; - -const uint8_t axradio_f2_framing_synclen = 32; -const uint8_t axradio_f2_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_f2_framing_syncflags = 0x38; -const uint8_t axradio_f2_framing_enable_sfdcallback = 0; - -const uint32_t axradio_f2_framing_ack_timeout = 8; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_f2_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_f2_framing_ack_retransmissions = 0; -const uint8_t axradio_f2_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_f2_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_f2_wor_period = 128; -const uint8_t axradio_f2_phy_innerfreqloop = 0; - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 12.500kHz br= 50.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw= 75.000kHz br= 50.000kBit/s -void ax5043_f2_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x24, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0x83, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x1C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x22, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x88, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x89, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x82, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); // - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); // - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x8A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xEB, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); - - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTSTOREFLAGS, (uint8_t)0x14, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xB5, ret_value); -} - - - - - - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_f2_set_regs_tx(spip); - ax5043_f2_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - - //set address values - //ax5043_f2_set_local_addr(spip); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - //ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_f2_set_regs_rx(spip); - ax5043_f2_init_registers_common(spip); - - - //follows code from function ax5043_receiver_on_continuous() in easyax5043.c from radiolab - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_f2_phy_rssireference, ret_value); - ax5043_f2_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - //set address values - //ax5043_f2_set_local_addr(spip); - -} - - - -uint8_t axradio_f2_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_f2_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_f2_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_f2_phy_chanpllrng[0] & 0x0F) - (axradio_f2_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - - - void ax5043_f2_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_f2_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_f2_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_f2_init(SPIDriver * spip) -{ - - - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); - - - //ax5043_shutdown(spip); - ax5043_f2_set_regs(spip); - ax5043_f2_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_f2_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - - //PLL autoranging - uint8_t r; - if( !(axradio_f2_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_f2_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_f2_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_f2_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_f2_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_f2_set_regs(spip); - ax5043_f2_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_f2_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_f2_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet - * The logic is similar to transmit_isr() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_f2_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_f2_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_f2_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_f2_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_f2_phy_preamble_appendbits); - byte |= 0x80 >> axradio_f2_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_f2_phy_preamble_appendbits); - byte |= 0x01 << axradio_f2_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_f2_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_f2_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_f2_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_f2_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Logic similar to axradio_transmit() - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_f2_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_f2_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_f2_framing_maclen); - memcpy(&axradio_txbuffer[axradio_f2_framing_maclen], pkt, pktlen); - if (axradio_f2_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_f2_framing_destaddrpos], &addr->addr, axradio_f2_framing_addrlen); - if (axradio_f2_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_f2_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_f2_framing_addrlen); - if (axradio_f2_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_f2_framing_lenoffs) & axradio_f2_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_f2_framing_lenpos] = (axradio_txbuffer[axradio_f2_framing_lenpos] & (uint8_t)~axradio_f2_framing_lenmask) | len_byte; - } -/* - if (axradio_f2_framing_swcrclen) - axradio_txbuffer_len = axradio_f2_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_f2_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_f2_phy_preamble_longlen; -*/ - //ax5043_f2_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_f2_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - -uint8_t receive_f2_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]) { - uint8_t ret_value[3]={0,0,0}; - uint8_t fifo_cmd; - uint8_t i; - uint8_t b0; - uint8_t b1; - uint8_t b2; - uint8_t b3; - uint8_t len = ax5043_read_reg(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected - - uint8_t bytesRead = 0; - - - chprintf(DEBUG_CHP,"INFO: Waiting for a packet\r\n"); - while ((ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value) & 0x01) != 1) { // FIFO not empty - fifo_cmd = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // read command - len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len - if (len == 7) - len = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // 7 means variable length, -> get length byte - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (!len) - break; - ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); // Discard the flags - --len; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, len); - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (axradio_f2_phy_innerfreqloop || len != 3) - goto dropchunk; - i = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - i &= 0x0F; - i |= 1 + (uint8_t)~(i & 0x08); - b3 = ((int8_t)i) >> 8; - b2 = i; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\r\n", b3, b2, b1, b0); - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (!axradio_f2_phy_innerfreqloop || len != 2) - goto dropchunk; - b1 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - b0 = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: Frequency offset: 0x%02x%02x\r\n", b1, b2); - break; - - case AX5043_FIFOCMD_RSSI: - if (len != 1) - goto dropchunk; - { - int8_t r; - r = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - - chprintf(DEBUG_CHP,"INFO: RSSI %d\r\n", (int)r); - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unknown FIFO cmd %x \r\n", fifo_cmd); - dropchunk: - chprintf(DEBUG_CHP, "WARNING: Discarding chunk in FIFO\r\n"); - if (!len) - break; - i = len; - do { - int8_t data; - data = ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);// purge FIFO - chprintf(DEBUG_CHP,"Unknown: %x \r\n", data); - } - while (--i); - break; - } - } - - //chprintf(DEBUG_CHP, "INFO: Done waiting for a packet\r\n"); - - return bytesRead; - -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.h b/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.h deleted file mode 100644 index d97597fe..00000000 --- a/src/archive/app_ax5043_engr_tx_full_duplex/source/ax5043_engr_f2.h +++ /dev/null @@ -1,34 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_ENGR_F2_H -#define _AX5043_ENGR_F2_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - -void ax5043_f2_set_regs(SPIDriver * spip); -void ax5043_f2_set_regs_tx(SPIDriver * spip); -void ax5043_f2_set_regs_rx(SPIDriver * spip); -void ax5043_f2_set_regs_rxcont(SPIDriver * spip); -void ax5043_f2_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_f2_prepare_tx(SPIDriver * spip); -void ax5043_f2_prepare_rx(SPIDriver * spip); -uint8_t axradio_f2_get_pllvcoi(SPIDriver * spip); -void ax5043_f2_init_registers_common(SPIDriver * spip); -void ax5043_f2_init(SPIDriver * spip); -void transmit_f2_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -uint8_t transmit_f2_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -uint8_t receive_f2_loop(SPIDriver * spip, uint8_t axradio_rxbuffer[]); - -#endif -//! @} diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/Makefile b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/README.md b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/README.md deleted file mode 100644 index d1c09fb5..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# app_ax5043_g3ruh_ax25_aprs_tx - -This is used to transmit ax5043 radio g3ruh ax.25 signal. -This creates a g3ruh packet at 435.5 MhZ in a fixed interval. This mode is suppossed to be transmitted from satellite. This pairs with " app_ax5043_g3ruh_ax25_aprs_rx " which can receive this packet. - -This mode is for amatuer radio group and will not be used for ground control. - diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/chconf.h b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/halconf.h b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/mcuconf.h b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/main.c b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/main.c deleted file mode 100644 index 61936d3e..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/main.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" - - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -const struct axradio_address remoteaddr_tx = { - { 0x33, 0x34, 0x00, 0x00} -}; -const struct axradio_address_mask localaddr_tx = { - { 0x32, 0x34, 0x00, 0x00}, - { 0x00, 0x00, 0x00, 0x00} -}; -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3E, 0x54, 0x65, 0x73, 0x74 }; - -const uint8_t framing_insert_counter = 0; -const uint8_t framing_counter_pos = 0; - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - -/* - uint8_t rx_buf[2]={0x00 ,0 }; - uint8_t command_buf[2] = {0x00 ,0x00 }; - - while (true) - { - //uint8_t command_buf[6]; - //uint8_t rx_bufi=0; - - //command_buf[0] = AD_READ_BLK_LADR; - - //command_buf[1] = (uint8_t) (AD_MISC_FW >> 24); - //command_buf[2] = (uint8_t) (AD_MISC_FW >> 16); - //command_buf[3] = (uint8_t) (AD_MISC_FW >> 8); - //command_buf[4] = (uint8_t) (AD_MISC_FW); - //ommand_buf[5] = 0; - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x --\r\n", AD_MISC_FW); - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x %x %x %x %x %x --\r\n", command_buf[0],command_buf[1],command_buf[2],command_buf[3],command_buf[4],command_buf[5]); - - spiSelect(&SPID2); - spiStartExchange(&SPID2, 2, command_buf, rx_buf); - while((SPID2).state != SPI_READY) { } - chprintf(DEBUG_CHP, "\r\r Sent to Radio-- 0x%x 0x%x --\r\n", command_buf[0],command_buf[1]); - chprintf(DEBUG_CHP, "\r\r Radio returned-- 0x%x 0x%x --\r\n", rx_buf[0],rx_buf[1]); - spiUnselect(&SPID2); - chThdSleepMilliseconds(500); - command_buf[0] = command_buf[0] +1; - - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } -*/ - //uint16_t reg=0; - uint8_t value=0; - uint8_t value1=0x55; - uint8_t ret_value[3]={0,0,0}; - //int i; - - - ax5043_read_reg(&SPID2, AX5043_REG_REV, value, ret_value); - chThdSleepMilliseconds(1500); - - - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_SCRATCH, value1, ret_value); - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - chThdSleepMilliseconds(1500); - - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - -/* - while(true) - { - - reg = 0x314; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = 0x314; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - value1 =value1+1; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r written reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value1,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - }*/ - - //ax5043_prepare_tx(&SPID2); - -/* - while(true) - { - //ax5043_prepare_tx(&SPID2); - chThdSleepMilliseconds(3000); - chprintf(DEBUG_CHP, "Writting FIFO\r\n"); - ax5043_transmit(&SPID2); - chThdSleepMilliseconds(1000); - ax5043_shutdown(&SPID2); - } -*/ - -/* - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x10, ret_value);//packet length - //ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x24, ret_value);//packet details like raw packet - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x08, ret_value);//packet details like raw packet - for (i=0;i<16;i++) - { - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//some random data - } - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit -*/ - //ax5043_transmit(&SPID2); - - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf(DEBUG_CHP,"INFO: Sending another packet...\r\n"); - transmit_packet(&SPID2, &remoteaddr_tx, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(3000); - } - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} - diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/README.md b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.c b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.c deleted file mode 100644 index 523870fb..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.c +++ /dev/null @@ -1,1187 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x090a2fc9 }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x99 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 910; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF7 + 64); -const int8_t axradio_phy_channelbusy = -93 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 9; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 40; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 40; -const uint8_t axradio_phy_preamble_byte = 0x55; -const uint8_t axradio_phy_preamble_flags = 0x18; -const uint8_t axradio_phy_preamble_appendbits = 4; -const uint8_t axradio_phy_preamble_appendpattern = 0x03; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 0; -const uint8_t axradio_framing_addrlen = 0; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 0; -const uint8_t axradio_framing_lenoffs = 21; -const uint8_t axradio_framing_lenmask = 0x00; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa}; -const uint8_t axradio_framing_syncflags = 0x18; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 13; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; - - - - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x--\r\n", command_buf[0],command_buf[1]); - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x--\r\n", ret_value[0],ret_value[1]); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x, [2]=0x%x--\r\n", command_buf[0],command_buf[1],command_buf[2]); - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x , [2]=0x%x--\r\n", ret_value[0],ret_value[1],ret_value[2]); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Writes to an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - //uint8_t return_val; - //int num_retries = 1; - //return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - ax5043_write_reg_spi(spip, reg, value, ret_value); - -/* - while (num_retries > 0 && return_val != 0x80) - { - chThdSleepMicroseconds(100); - return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - num_retries--; - //chprintf(DEBUG_CHP, "\r\r num_retries= %d --\r\n", num_retries); - }*/ - -} - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=433.910MHz dev= 3.200kHz br= 9.600kBit/s pwr= 10.0dBm -// RX: fcarrier=433.910MHz bw= 14.400kHz br= 9.600kBit/s - -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x14, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_CRCINIT3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_CRCINIT2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_CRCINIT1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_CRCINIT0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x0C, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x14, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x2F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0xC5, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0xC5, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x5E, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x1B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x99, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x15, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xE3, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x39, ret_value); //original 20, 3f=accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x10, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xE7, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * switch off xtal for AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_off_xtal(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(10); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - chThdSleepMilliseconds(1); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - chThdSleepMilliseconds(10); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - chThdSleepMilliseconds(10); - - -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x32, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - //int num_retries; - //uint8_t pll_range_done = 0; - //uint8_t pll_range_after; - //uint8_t vcoi_save; - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); //reset is causing problems and hence disabling it.need to remove it - - //adding two more lines to diable the interrupts. Need to remove it later - //ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - //ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet. Not used in thsi version of code. - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_transmit(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - int i=0; - ax5043_full_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - //send out the preamble - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xE0, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //sync word - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xA1, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x18, ret_value);//sync flags - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - - -/* seems this will not get executed based on logic - //send out the preamble. again? - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //writting preamble based on address register. pretty weird. - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x41), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1C, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); -*/ - - //write MAC and packet - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0C, ret_value);//packet length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x03, ret_value);//packet details like raw packet - - - //length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0B, ret_value); - //address values - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x34, ret_value); - for (i=0;i<8;i++) - { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x36, ret_value);//some random data - } - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - -} - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit_isr \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.h b/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.h deleted file mode 100644 index 4a4e9b99..00000000 --- a/src/archive/app_ax5043_g3ruh_ax25_aprs_tx/source/ax5043.h +++ /dev/null @@ -1,730 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_transmit(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); - -#endif -//! @} diff --git a/src/archive/app_ax5043_morse_tx/Makefile b/src/archive/app_ax5043_morse_tx/Makefile deleted file mode 100644 index 2d3f679b..00000000 --- a/src/archive/app_ax5043_morse_tx/Makefile +++ /dev/null @@ -1,237 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = HDLC_FEC_RX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk diff --git a/src/archive/app_ax5043_morse_tx/README.md b/src/archive/app_ax5043_morse_tx/README.md deleted file mode 100644 index 251e4488..00000000 --- a/src/archive/app_ax5043_morse_tx/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_FulDuplex_ground - -This is used to transmit semtech radio packets signal. -This creates a instruction packet at 735.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_ax5043_morse_tx/conf/chconf.h b/src/archive/app_ax5043_morse_tx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_ax5043_morse_tx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_morse_tx/conf/halconf.h b/src/archive/app_ax5043_morse_tx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_ax5043_morse_tx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_ax5043_morse_tx/conf/mcuconf.h b/src/archive/app_ax5043_morse_tx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_ax5043_morse_tx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_ax5043_morse_tx/main.c b/src/archive/app_ax5043_morse_tx/main.c deleted file mode 100644 index 1226a212..00000000 --- a/src/archive/app_ax5043_morse_tx/main.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "ax5043.h" -#include "morse.h" - -//#include "adf7030.h" - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg_rx = -{ - false, - NULL, // Operation complete callback - GPIOA, // Slave select port - GPIOA_SPI1_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg_tx = -{ - false, - NULL, // Operation complete callback - GPIOB, // Slave select port - GPIOB_SPI2_NSS, // Slave select pad - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - -/* - * Initialize the SPI drivers and configure the adf7030 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - - chThdSleepMilliseconds(1000); - spiStart(&SPID1, &spicfg_rx); - spiStart(&SPID2, &spicfg_tx); - //spiSelect(&SPID2); - chThdSleepMilliseconds(1000); - - - -/* - uint8_t rx_buf[2]={0x00 ,0 }; - uint8_t command_buf[2] = {0x00 ,0x00 }; - - while (true) - { - //uint8_t command_buf[6]; - //uint8_t rx_bufi=0; - - //command_buf[0] = AD_READ_BLK_LADR; - - //command_buf[1] = (uint8_t) (AD_MISC_FW >> 24); - //command_buf[2] = (uint8_t) (AD_MISC_FW >> 16); - //command_buf[3] = (uint8_t) (AD_MISC_FW >> 8); - //command_buf[4] = (uint8_t) (AD_MISC_FW); - //ommand_buf[5] = 0; - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x --\r\n", AD_MISC_FW); - //chprintf(DEBUG_CHP, "\r\r request-- 0x%x %x %x %x %x %x --\r\n", command_buf[0],command_buf[1],command_buf[2],command_buf[3],command_buf[4],command_buf[5]); - - spiSelect(&SPID2); - spiStartExchange(&SPID2, 2, command_buf, rx_buf); - while((SPID2).state != SPI_READY) { } - chprintf(DEBUG_CHP, "\r\r Sent to Radio-- 0x%x 0x%x --\r\n", command_buf[0],command_buf[1]); - chprintf(DEBUG_CHP, "\r\r Radio returned-- 0x%x 0x%x --\r\n", rx_buf[0],rx_buf[1]); - spiUnselect(&SPID2); - chThdSleepMilliseconds(500); - command_buf[0] = command_buf[0] +1; - - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } -*/ - uint16_t reg=0; - uint8_t value=0; - uint8_t value1=0x55; - uint8_t ret_value[3]={0,0,0}; - int i; - - - ax5043_read_reg(&SPID2, AX5043_REG_REV, value, ret_value); - chThdSleepMilliseconds(1500); - - - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_SCRATCH, value1, ret_value); - ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, value, ret_value); - chThdSleepMilliseconds(1500); - - - - chprintf(DEBUG_CHP, "Configuring AX5043\r\n"); - chThdSleepMilliseconds(50); - ax5043_init(&SPID2); - chprintf(DEBUG_CHP, "done reseting AX5043\r\n"); - -/* - while(true) - { - - reg = 0x314; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = 0x314; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg 220 contents=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - value1 =value1+1; - ax5043_write_reg(&SPID2, reg, value1, ret_value); - //chprintf(DEBUG_CHP, "\r\r written reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value1,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - - reg = AX5043_REG_SCRATCH; - ax5043_read_reg(&SPID2, reg, value, ret_value); - //chprintf(DEBUG_CHP, "\r\r reg=0x%x, value=0x%x, ret_value=0x%x 0x%x, --\r\n", reg,value,ret_value[0],ret_value[1]); - chThdSleepMilliseconds(1500); - }*/ - - ax5043_prepare_tx(&SPID2); - //ax5043_write_reg(&SPID2, AX5043_REG_MODULATION, (uint8_t)0x01, ret_value); - ax5043_full_tx(&SPID2); - //ax5043_transmit(&SPID2); - - - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - ax5043_standby(&SPID2); - chThdSleepMilliseconds(10000); - SetWpm(5); - SetMessage("KG7ZVV Malay Das testing AX5043"); - - while(true){ - SendMessage(&SPID2); - chThdSleepMilliseconds(5000); - chprintf(DEBUG_CHP, "=====================\r\n"); - } - - - /* - // Below loop is for OOK code - while(true) - { - - //ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - //ax5043_standby(&SPID2); - //ax5043_synth_tx(&SPID2); - //ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_standby(&SPID2); - chprintf(DEBUG_CHP, "Stop\r\n"); - chThdSleepMilliseconds(2000); - - - ax5043_full_tx(&SPID2); - chprintf(DEBUG_CHP, "Start\r\n"); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xF0, ret_value);//preamble - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - chThdSleepMilliseconds(2000); - } - - //very old loop. - while(true) - { - ax5043_prepare_tx(&SPID2); - chThdSleepMilliseconds(3000); - chprintf(DEBUG_CHP, "Writting FIFO\r\n"); - ax5043_transmit(&SPID2); - chThdSleepMilliseconds(1000); - //ax5043_shutdown(&SPID2); - } */ - - /* - while(true) - { - ax5043_standby(&SPID2); - //ax5043_synth_tx(&SPID2); - chprintf(DEBUG_CHP, "Stop\r\n"); - chThdSleepMilliseconds(2000); - ax5043_full_tx(&SPID2); - chprintf(DEBUG_CHP, "Start\r\n"); - chThdSleepMilliseconds(2000); - } - */ - - -/* - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x10, ret_value);//packet length - //ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x24, ret_value);//packet details like raw packet - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x08, ret_value);//packet details like raw packet - for (i=0;i<16;i++) - { - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//some random data - } - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit -*/ - //ax5043_transmit(&SPID2); - -} - - -/* - * main loop blinks the led - */ -static void main_loop(void) -{ - chThdSleepMilliseconds(500); - - - while (true) - { - chThdSleepMilliseconds(500); - chprintf(DEBUG_CHP, "."); - palTogglePad(GPIOA, GPIOA_SX_TESTOUT); - } - -} - - -/* - * Entry to our code - */ -int main(void) -{ - halInit(); - chSysInit(); - app_init(); - - // Enabling events on both edges of the button line.*/ - //palEnableLineEvent(GPIOC_SX_DIO3, PAL_EVENT_MODE_RISING_EDGES); - - //chThdCreateStatic(waThread_sx1236_rx, sizeof(waThread_sx1236_rx), NORMALPRIO, Thread_sx1236_rx, NULL); - //chThdSleepMilliseconds(500); - //chThdCreateStatic(waThread_sx1236_tx, sizeof(waThread_sx1236_tx), NORMALPRIO, Thread_sx1236_tx, NULL); - chThdSleepMilliseconds(500); - - main_loop(); - return 0; -} - - - diff --git a/src/archive/app_ax5043_morse_tx/source/README.md b/src/archive/app_ax5043_morse_tx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_ax5043_morse_tx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_ax5043_morse_tx/source/ax5043.c b/src/archive/app_ax5043_morse_tx/source/ax5043.c deleted file mode 100644 index 809bf0fa..00000000 --- a/src/archive/app_ax5043_morse_tx/source/ax5043.c +++ /dev/null @@ -1,1179 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "ax5043.h" - - - - - -// physical layer from config.c file generated from radiolab -const uint8_t axradio_phy_pn9 = 0; -const uint8_t axradio_phy_nrchannels = 1; -const uint32_t axradio_phy_chanfreq[1] = { 0x0912aaab }; -const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a }; -const uint8_t axradio_phy_chanvcoiinit[1] = { 0x98 }; -uint8_t axradio_phy_chanpllrng[1]; -uint8_t axradio_phy_chanvcoi[1]; -const uint8_t axradio_phy_vcocalib = 0; -const int32_t axradio_phy_maxfreqoffset = 913; -const int8_t axradio_phy_rssioffset = 64; -// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128) -// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR -const int8_t axradio_phy_rssireference = (int8_t)(0xF7 + 64); -const int8_t axradio_phy_channelbusy = -93 + 64; -const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms -const uint8_t axradio_phy_cs_enabled = 0; -const uint8_t axradio_phy_lbt_retries = 0; -const uint8_t axradio_phy_lbt_forcetx = 0; -const uint16_t axradio_phy_preamble_wor_longlen = 9; // wor_longlen + wor_len totals to 240.0ms plus 112bits -const uint16_t axradio_phy_preamble_wor_len = 40; -const uint16_t axradio_phy_preamble_longlen = 0; -const uint16_t axradio_phy_preamble_len = 40; -const uint8_t axradio_phy_preamble_byte = 0x55; -const uint8_t axradio_phy_preamble_flags = 0x18; -const uint8_t axradio_phy_preamble_appendbits = 4; -const uint8_t axradio_phy_preamble_appendpattern = 0x03; - -//framing variables generated from radiolab -const uint8_t axradio_framing_maclen = 0; -const uint8_t axradio_framing_addrlen = 0; -const uint8_t axradio_framing_destaddrpos = 0; -const uint8_t axradio_framing_sourceaddrpos = 0xff; -const uint8_t axradio_framing_lenpos = 2; -const uint8_t axradio_framing_lenoffs = 37; -const uint8_t axradio_framing_lenmask = 0x00; -const uint8_t axradio_framing_swcrclen = 0; - -const uint8_t axradio_framing_synclen = 32; -const uint8_t axradio_framing_syncword[] = { 0x33, 0x55, 0x33, 0x55}; -const uint8_t axradio_framing_syncflags = 0x38; -const uint8_t axradio_framing_enable_sfdcallback = 0; - -const uint32_t axradio_framing_ack_timeout = 13; // 98.9ms in wtimer0 units (640Hz) -const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64) -const uint8_t axradio_framing_ack_retransmissions = 0; -const uint8_t axradio_framing_ack_seqnrpos = 0xff; - -const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured -//WOR -const uint16_t axradio_wor_period = 128; - -/** - * writes to an AX5043 register. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0}; - - if(reg < 0x0070) - { - command_buf[0]=0x80|reg; - command_buf[1]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x--\r\n", command_buf[0],command_buf[1]); - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x--\r\n", ret_value[0],ret_value[1]); - } - else - { - command_buf[0]=0xF0|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - //chprintf(DEBUG_CHP, "\r\r written [0]=0x%x, [1]=0x%x, [2]=0x%x--\r\n", command_buf[0],command_buf[1],command_buf[2]); - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - //chprintf(DEBUG_CHP, "\r\r read after writting [0]=0x%x, [1]=0x%x , [2]=0x%x--\r\n", ret_value[0],ret_value[1],ret_value[2]); - } - return ret_value[0]; //retun status while writting the register - -} - - -/** - * Writes to an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value of the register. - */ -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - //uint8_t return_val; - //int num_retries = 1; - //return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - ax5043_write_reg_spi(spip, reg, value, ret_value); - -/* - while (num_retries > 0 && return_val != 0x80) - { - chThdSleepMicroseconds(100); - return_val=ax5043_write_reg_spi(spip, reg, value, ret_value); - num_retries--; - //chprintf(DEBUG_CHP, "\r\r num_retries= %d --\r\n", num_retries); - }*/ - -} - -/** - * Reds an AX5043 register. This has retry logic. This calls the the function ax5043_write_reg_spi. - * @param spip: SPI Configuration, reg: Register address, value: register value, ret_value: returned data. - * @return the value in the register. - */ -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]) -{ - uint8_t command_buf[3] = {0,0,0 }; - - if(reg < 0x0070) - { - command_buf[0]=reg; - command_buf[1]=value; - spiSelect(spip); - spiStartExchange(spip, 2, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[1]; //return the reg value when reading the register - } - else - { - command_buf[0]=0x70|(reg>>8); - command_buf[1]=reg; - command_buf[2]=value; - spiSelect(spip); - spiStartExchange(spip, 3, command_buf, ret_value); - while((*spip).state != SPI_READY) { } - spiUnselect(spip); - return ret_value[2]; //return the reg value when reading the register - } - -} - - - -/** - * Sets AX5043 registers. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -// TX: fcarrier=435.500MHz dev= 25.000kHz br=100.000kBit/s pwr= 10.0dBm -// RX: fcarrier=435.500MHz bw=150.000kHz br=100.000kBit/s -void ax5043_set_regs(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); //was 08 - ax5043_write_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FRAMING, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FEC, (uint8_t)0x13, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCSYSCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDCLK, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCDATA, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCANTSEL, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_PINFUNCPWRAMP, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_WAKEUPXOEARLY, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ1, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_IFFREQ0, (uint8_t)0x0C, ret_value); - ax5043_write_reg(spip, AX5043_REG_DECIMATION, (uint8_t)0x14, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE1, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXDATARATE0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXDROFFSET0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET2, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET1, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_MAXRFOFFSET0, (uint8_t)0x30, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMAX0, (uint8_t)0xA6, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN1, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDMIN0, (uint8_t)0x5A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLFILTER, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xF4, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN0, (uint8_t)0xC5, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET0, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN0, (uint8_t)0xF8, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN0, (uint8_t)0xF2, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN0, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA0,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB0,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC0,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND0,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN0, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV10, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV00, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN1, (uint8_t)0xC5, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET1, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN1, (uint8_t)0xF6, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN1, (uint8_t)0xF1, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN1, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA1,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB1,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC1,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND1,(uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN1, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV11, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV01, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK1, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCTARGET3, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCAHYST3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCMINMAX3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TIMEGAIN3, (uint8_t)0xF5, ret_value); - ax5043_write_reg(spip, AX5043_REG_DRGAIN3, (uint8_t)0xF0, ret_value); - ax5043_write_reg(spip, AX5043_REG_PHASEGAIN3, (uint8_t)0xC3, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINA3,(uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINB3,(uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAINC3,(uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQUENCYGAIND3,(uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_AMPLITUDEGAIN3, (uint8_t)0x06, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x3C, ret_value); - ax5043_write_reg(spip, AX5043_REG_FOURFSK3, (uint8_t)0x16, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSRES3, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGF, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_MODCFGA, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXRATE0, (uint8_t)0x01, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB1, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_TXPWRCOEFFB0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRNGCLK, (uint8_t)0x05, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBTUNE, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_BBOFFSCAP, (uint8_t)0x77, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENCFG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTLENOFFSET, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMAXLEN, (uint8_t)0xC8, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT3, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT2, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT1, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH0PAT0, (uint8_t)0xCC, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0LEN, (uint8_t)0x9F, ret_value); - //ax5043_write_reg(spip, AX5043_REG_MATCH0MAX, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT1, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1PAT0, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1LEN, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_MATCH1MAX, (uint8_t)0x0A, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGTXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXBOOST, (uint8_t)0x5B, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXSETTLE, (uint8_t)0x3E, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXOFFSACQ, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXCOARSEAGC, (uint8_t)0x9C, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXRSSI, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE2, (uint8_t)0x17, ret_value); - ax5043_write_reg(spip, AX5043_REG_RSSIABSTHR, (uint8_t)0xE3, ret_value); - ax5043_write_reg(spip, AX5043_REG_BGNDRSSITHR, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTCHUNKSIZE, (uint8_t)0x0D, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTACCEPTFLAGS, (uint8_t)0x20, ret_value); //original 20, 3f=accept all errors - ax5043_write_reg(spip, AX5043_REG_DACVALUE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACVALUE0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_DACCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_REF, (uint8_t)0x03, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALOSC, (uint8_t)0x04, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALAMPL, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF1C, (uint8_t)0x07, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF21, (uint8_t)0x68, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF22, (uint8_t)0XFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF23, (uint8_t)0x84, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF26, (uint8_t)0x98, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF34, (uint8_t)0x28, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF35, (uint8_t)0x11, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF44, (uint8_t)0x25, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x02, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x24, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x06, ret_value); -} - - -/** - * Sets AX5043 registers for RX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x0B, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x10, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLVCODIV, (uint8_t)0x25, ret_value); - ax5043_write_reg(spip, AX5043_REG_XTALCAP, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF00, (uint8_t)0x0F, ret_value); - ax5043_write_reg(spip, AX5043_REG_0xF18, (uint8_t)0x02, ret_value); -} - - -/** - * Sets AX5043 registers for RX continous. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_TMGRXAGC, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_TMGRXPREAMBLE1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTMISCFLAGS, (uint8_t)0x00, ret_value); -} - - -/** - * Sets AX5043 registers for TX. This is based on config file generated by radio lab. - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_write_reg(spip, AX5043_REG_RXPARAMSETS, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV13, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQDEV03, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_AGCGAIN3, (uint8_t)0xE7, ret_value); -} - -/** - * Shutdown after reset the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_shutdown(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * switch off xtal for AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_off_xtal(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Standby the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_standby(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - //ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN, ret_value); - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_STANDBY; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * Enable FIFO in AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_fifo_en(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FIFO_ENABLED; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * put AX5043 in synthesizer RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - -/** - * changes AX5043 to full RX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_rx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_RX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * put AX5043 in synthesizer TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_synth_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_SYNTH_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - -/** - * changes AX5043 to full TX mode - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_full_tx(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t value; - value = ax5043_read_reg(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, ret_value); - value = value & 0xF0; - value = value | AX5043_FULL_TX; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); -} - - - - - - -/** - * Resets the AX5043 - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_reset(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value = 0; - uint8_t ret_value[3]={0,0,0}; - - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - //spiUnselect(spip); - //chThdSleepMicroseconds(10); - - //Reset the chip through powermode register - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, ret_value); - chThdSleepMilliseconds(10); - //chThdSleepMicroseconds(5); - - //read the powermode register - value=ax5043_read_reg(&SPID2, AX5043_REG_PWRMODE, value, ret_value); - //write to powermode register for enabling XOEN and REFIN and shutdown mode - //page 33 in programming manual - //value = value | AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT; - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, value, ret_value); - chThdSleepMilliseconds(1); - - //ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, ret_value); - value = ax5043_read_reg(&SPID2, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0xAA) - { - chprintf(DEBUG_CHP, "Scratch register does not match 0\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - ax5043_write_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, ret_value); - chThdSleepMilliseconds(10); - value = ax5043_read_reg(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, ret_value); - if (value != 0x55) - { - chprintf(DEBUG_CHP, "Scratch register does not match 1\r\n"); - } - ax5043_write_reg(spip, AX5043_REG_PINFUNCIRQ, (uint8_t)0x02, ret_value); - chThdSleepMilliseconds(10); - - -} - - -/** - * prepare AX5043 for tx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - - ax5043_standby(spip); - ax5043_fifo_en(spip); - ax5043_set_regs_tx(spip); - ax5043_init_registers_common(spip); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x32, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - - //wait for xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - - //ax5043_full_tx(spip); -} - - -/** - * prepare AX5043 for rx - * @param spip: SPI Configuration. - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(SPIDriver * spip) -{ - - //uint8_t reg=0; - //int8_t value= (int8_t)(0xF9 + 64); - uint8_t ret_value[3]={0,0,0}; - - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_STANDBY, ret_value); - ax5043_write_reg(spip, AX5043_REG_LPOSCCONFIG, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_POWERDOWN, ret_value); - - ax5043_set_regs_rx(spip); - ax5043_init_registers_common(spip); - - ax5043_write_reg(spip, AX5043_REG_RSSIREFERENCE, axradio_phy_rssireference, ret_value); - ax5043_set_regs_rxcont(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_PWRMODE, AX5043_FULL_RX, ret_value);//Full RX - - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, ret_value); - - //set address values - ax5043_write_reg(spip, AX5043_REG_PKTADDR0, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR1, (uint8_t)0x34, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDR3, (uint8_t)0x00, ret_value); - //set address mask - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK0, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PKTADDRMASK3, (uint8_t)0x00, ret_value); - -} - - -void ax5043_init_registers_common(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t rng = axradio_phy_chanpllrng[0]; - if (rng & 0x20) - chprintf(DEBUG_CHP, "\r\r ERROR at ax5043_init_registers_common --\r\n"); - if ( ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value) & 0x80) { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), ret_value); - } else { - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), ret_value); - } - rng = axradio_get_pllvcoi(spip); - if (rng & 0x80) - ax5043_write_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), ret_value); -} - - - -uint8_t axradio_get_pllvcoi(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - uint8_t x = axradio_phy_chanvcoiinit[0]; - if (x & 0x80) { - if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) { - x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); -} - - -/** - * Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_init(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - //int num_retries; - //uint8_t pll_range_done = 0; - //uint8_t pll_range_after; - //uint8_t vcoi_save; - uint8_t ret_value[3]={0,0,0}; - - ax5043_reset(spip); //reset is causing problems and hence disabling it.need to remove it - - //adding two more lines to diable the interrupts. Need to remove it later - //ax5043_write_reg(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, ret_value); - //ax5043_write_reg(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, ret_value); - - - //ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, ret_value); - - ax5043_standby(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - - //wait for Xtal - while ((ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value) & 0x01) == 0) - { - chThdSleepMilliseconds(1); - } - chprintf(DEBUG_CHP, "XTAL Status 0x%x \r\n", ax5043_read_reg(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, ret_value)); - - //set frequency based on line 693 on conig.c and 1640 on easyax5043.c from - //codeblocks generated code - uint32_t f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - - //ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - //ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - - //PLL autoranging - uint8_t r; - if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available - r = axradio_phy_chanpllrnginit[0] | 0x10; - } - else { - r = 0x18; - } - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, ret_value); - chThdSleepMilliseconds(1); - while ((ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - axradio_phy_chanpllrng[0] = ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "\r\r PLL ranging done. 0x%x --\r\n", axradio_phy_chanpllrng[0]); - - - //VCOI calibration - /* - ax5043_set_regs_tx(spip); - ax5043_write_reg(spip, AX5043_REG_MODULATION, (uint8_t)0x08, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, ret_value); - value = value | 0x04; - ax5043_write_reg(spip, AX5043_REG_PLLLOOP, value, ret_value); - value=ax5043_read_reg(spip, AX5043_REG_0xF35, (uint8_t)0x00, ret_value); - value = value | 0x80; - if (2 & (uint8_t)~value) - ++value; - ax5043_write_reg(spip, AX5043_REG_0xF35, value, ret_value); - ax5043_synth_tx(spip); - vcoi_save = ax5043_read_reg(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, ret_value); - ax5043_write_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(pll_range_after & 0x0F), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)0xab, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)0xaa, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)0x12, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)0x09, ret_value); - //tune voltage. doesn't make sense. So, not implementing it for now.. - - num_retries = 64; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - num_retries = 32; - while (num_retries > 0) - { - ax5043_write_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x84, ret_value); - do{} while (ax5043_read_reg(spip, AX5043_REG_GPADCCTRL, (uint8_t)0x00, ret_value) & 0x80); - num_retries--; - } - //ax5043_write_reg(spip, AX5043_REG_PLLVCOI, vcoi_save, ret_value); - */ - - ax5043_shutdown(spip); - ax5043_set_regs(spip); - ax5043_set_regs_rx(spip); - - ax5043_read_reg(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(axradio_phy_chanpllrng[0] & 0x0F), ret_value); - f = axradio_phy_chanfreq[0]; - ax5043_write_reg(spip, AX5043_REG_FREQA0, (uint8_t)f, ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), ret_value); - ax5043_write_reg(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), ret_value); - - -} - - - -/** - * Transmits a packet. Not used in thsi version of code. - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_transmit(SPIDriver * spip) -{ - - //uint8_t reg=0; - //uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - int i=0; - ax5043_full_tx(spip); - - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - //send out the preamble - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xE0, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //sync word - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xA1, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x18, ret_value);//sync flags - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xCC, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xAA, ret_value); - - -/* seems this will not get executed based on logic - //send out the preamble. again? - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x02), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1F, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - - - //writting preamble based on address register. pretty weird. - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x41), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x1C, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value); -*/ - - //write MAC and packet - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)AX5043_DATA_CMD, ret_value);//The data follows - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0C, ret_value);//packet length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x03, ret_value);//packet details like raw packet - - - //length - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x0B, ret_value); - //address values - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x33, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x34, ret_value); - for (i=0;i<8;i++) - { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x36, ret_value);//some random data - } - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - -} - -/** - * read FIFO packet for a packet - * @param conf the AX5043 configuration handler - * @return void - * TODO return a -ve return code if there are any errors - */ -void ax5043_receive(SPIDriver * spip) -{ - - //uint8_t reg=0; - uint8_t value=0; - uint8_t ret_value[3]={0,0,0}; - //ax5043_full_rx(spip); - //ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO status value 0x%x \r\n", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO Data 0x%x \r\n", value); - while(!(ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value)&0x01)) - { - value=ax5043_read_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "0x%x ", value); - value=ax5043_read_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, ret_value); - chprintf(DEBUG_CHP, "FIFO 0x%x \r\n", value); - } - - chprintf(DEBUG_CHP, "\r\r finished reading FIFO--\r\n", value); - - -} - - - -/** - * writes to FIFO - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len) -{ - uint8_t ret_value[3]={0,0,0}; - if (!len) - return; - do { - ax5043_write_reg(spip, AX5043_REG_FIFODATA, *ptr++, ret_value); - } while (--len); -} - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt) -{ - uint8_t ret_value[3]={0,0,0}; - - for (;;) { - uint8_t cnt = ax5043_read_reg(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, ret_value); - - if (ax5043_read_reg(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, ret_value)) - cnt = 0xff; - - switch (axradio_trxstate) { - case trxstate_tx_longpreamble: - if (!axradio_txbuffer_cnt) { - axradio_trxstate = trxstate_tx_shortpreamble; - axradio_txbuffer_cnt = axradio_phy_preamble_len; - goto shortpreamble; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 7; - if (axradio_txbuffer_cnt < 7) - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt -= cnt; - cnt <<= 5; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - break; - - case trxstate_tx_shortpreamble: - shortpreamble: - if (!axradio_txbuffer_cnt) { - if (cnt < 15) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - if (axradio_phy_preamble_appendbits) { - uint8_t byte; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - byte = axradio_phy_preamble_appendpattern; - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-axradio_phy_preamble_appendbits); - byte |= 0x80 >> axradio_phy_preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-axradio_phy_preamble_appendbits); - byte |= 0x01 << axradio_phy_preamble_appendbits; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - if ((ax5043_read_reg(spip,AX5043_REG_FRAMING, (uint8_t)0x00, ret_value) & 0x0E) == 0x06 && axradio_framing_synclen) { - // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT) - uint8_t len_byte = axradio_framing_synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;v - len_byte += 7; - len_byte >>= 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncflags | i, ret_value); - for (i = 0; i < len_byte; ++i) { - // better put a brace, it might prevent SDCC from optimizing away the assignement... - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_framing_syncword[i], ret_value); - } - } - axradio_trxstate = trxstate_tx_packet; - continue; - } - if (cnt < 4) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - cnt = 255; - if (axradio_txbuffer_cnt < 255*8) - cnt = axradio_txbuffer_cnt >> 3; - if (cnt) { - axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_flags, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt, ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, axradio_phy_preamble_byte, ret_value); - continue; - } - { - uint8_t byte = axradio_phy_preamble_byte; - cnt = axradio_txbuffer_cnt; - axradio_txbuffer_cnt = 0; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x1C, ret_value); - if (ax5043_read_reg(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, ret_value) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-cnt); - byte |= 0x80 >> cnt; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-cnt); - byte |= 0x01 << cnt; - } - ax5043_write_reg(spip,AX5043_REG_FIFODATA, byte, ret_value); - } - continue; - - case trxstate_tx_packet: - if (cnt < 11) { - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit - chThdSleepMilliseconds(1); - continue; - } - { - uint8_t flags = 0; - if (!axradio_txbuffer_cnt) - flags |= 0x01; // flag byte: pkt_start - { - uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt; - cnt -= 3; - if (cnt >= len) { - cnt = len; - flags |= 0x02; // flag byte: pkt_end - } - } - if (!cnt) - goto pktend; - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, cnt + 1, ret_value); // write FIFO chunk length byte (length includes the flag byte, thus the +1) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, flags, ret_value); - ax5043_writefifo(spip,&axradio_txbuffer[axradio_txbuffer_cnt], cnt); - axradio_txbuffer_cnt += cnt; - if (flags & 0x02) - goto pktend; - } - break; - - default: - chprintf(DEBUG_CHP, "ERROR: Unexpected state found in transmit_isr \r\n"); - } - } - -pktend: - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, ret_value); // enable REVRDONE event - ax5043_write_reg(spip,AX5043_REG_FIFOSTAT, 4, ret_value); // commit -} - - - - - -/** - * Transmits a packet - * Takn from Bradenburg library which seems to be taken from onSemi's code - * @param conf the AX5043 configuration handler - * @return void - * - */ - -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) -{ - uint8_t ret_value[3]={0,0,0}; - axradio_trxstate_t axradio_trxstate; - uint16_t axradio_txbuffer_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - struct axradio_address_mask axradio_localaddr; - uint16_t axradio_txbuffer_cnt = 0; - - axradio_txbuffer_len = pktlen + axradio_framing_maclen; - if (axradio_txbuffer_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - memset(axradio_txbuffer, 0, axradio_framing_maclen); - memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen); - if (axradio_framing_destaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen); - if (axradio_framing_sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen); - if (axradio_framing_lenmask) { - uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1 - axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte; - } -/* - if (axradio_framing_swcrclen) - axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len); - if (axradio_phy_pn9) - pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043_read_reg(spip, AX5043_REG_ENCODING, (uint8_t)0x00, ret_value) & 0x01)); - axradio_txbuffer_cnt = axradio_phy_preamble_longlen; -*/ - ax5043_prepare_tx(spip); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value);; // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, 3, ret_value); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way) - axradio_trxstate = trxstate_tx_longpreamble; - - if ((ax5043_read_reg(spip,AX5043_REG_MODULATION, (uint8_t)0x00, ret_value) & 0x0F) == 9) { // 4-FSK - ax5043_write_reg(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), ret_value); - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 2, ret_value); // length (including flags) - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x01, ret_value); // flag PKTSTART -> dibit sync - ax5043_write_reg(spip,AX5043_REG_FIFODATA, 0x11, ret_value); // dummy byte for forcing dibit sync - } - transmit_loop(spip, axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt); - ax5043_write_reg(spip,AX5043_REG_PWRMODE, AX5043_FULL_TX, ret_value); - - ax5043_read_reg(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, ret_value); - //printf("INFO: Waiting for transmission to complete\n"); - while (ax5043_read_reg(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, ret_value) != 0) { - chThdSleepMilliseconds(1); - } - //printf("INFO: Transmission complete\n"); - - ax5043_write_reg(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, ret_value); - - return AXRADIO_ERR_NOERROR; -} - - - - - -//!@ - diff --git a/src/archive/app_ax5043_morse_tx/source/ax5043.h b/src/archive/app_ax5043_morse_tx/source/ax5043.h deleted file mode 100644 index 4a4e9b99..00000000 --- a/src/archive/app_ax5043_morse_tx/source/ax5043.h +++ /dev/null @@ -1,730 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_H -#define _AX5043_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - -/** - * The maximum allowed frame size - -#define MAX_FRAME_LEN 1024 - -#define RX_BAUDRATE 9600 -#define TX_BAUDRATE 9600 - -#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000 -#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000 - -#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2) - -#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000 -#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000 - -#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2) -#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2) - */ - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* MAC parameters */ - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* Special Functions */ - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/****************************************************************************** - ************************* Register values ************************************ - *****************************************************************************/ -#define AX5043_REV 0x51 -#define AX5043_SCRATCH_TEST 0xAA - -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -#define AX5043_RADIO_STATE_IDLE 0x0 - -#define AX5043_PLLVCOI_MANUAL (1 << 7) - -/** - * Modem Domain Voltage Regulator Ready - */ -#define AX5043_SVMODEM (1 << 3) - -/** - * Init value for the VCO prior starting an autoranging - */ -#define AX5043_VCOR_INIT 8 - -#define AX5043_RFDIV0 0x0 -#define AX5043_RFDIV1 (1 << 2) - -#define AX5043_FREQSHAPE_EXT_FILTER 0x0 -#define AX5043_FREQSHAPE_INVALID 0x1 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2 -#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3 - -/** - * FSK modulation mode - */ -#define AX5043_MODULATION_FSK (1 << 3) - -#define AX5043_ENC_INV 1 -#define AX5043_ENC_DIFF (1 << 1) -#define AX5043_ENC_SCRAM (1 << 2) - -/** - * HDLC Framing mode - */ -#define AX5043_HDLC_FRAMING (1 << 2) - -/** - * HDLC compliant CRC16 - */ -#define AX5043_CRC16_CCITT (1 << 4) - -/** - * FIFO commands - */ - -#define AX5043_NOP_CMD 0x0 -#define AX5043_RSSI_CMD 0x31 -#define AX5043_TXCTRL_CMD 0x3C -#define AX5043_FREQOFFS_CMD 0x52 -#define AX5043_ANTRSSI2_CMD 0x55 -#define AX5043_REPEATDATA_CMD 0x62 -#define AX5043_TIMER_CMD 0x70 -#define AX5043_RFREQOFFS_CMD 0x73 -#define AX5043_DATARATE_CMD 0x74 -#define AX5043_ANTRSSI3_CMD 0x75 -#define AX5043_DATA_CMD 0xE1 -#define AX5043_TXPWR_CMD 0xFD - - -//fifo commands -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - - - -/** - * Poweramp pin function, output/Z pull up for board 0.9 with diodes for 1.4V - */ -#define AX5043_POWERAMP_MODE_OUTPUT (1 << 2) | 1) -#define AX5043_POWERAMP_MODE_PULLUP ((1 << 7) | 1) -#define AX5043_POWERAMP_MODE_DAC ((1 << 2) | 1) -/** - * FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -/** - * Maximum chuck that can be committed on the FIFO - */ -#define AX5043_PKTCHUNKSIZE_240 0xd - -#define AX5043_FIFO_MAX_SIZE 240 - -/** - * When this threshold of free bytes in the TX FIFO is reached, - * an IRQ is raised - */ -#define AX5043_FIFO_FREE_THR 128 - -#define AX5043_IRQMFIFOTHRFREE (1 << 3) -#define AX5043_IRQRFIFOTHRFREE (1 << 3) -#define AX5043_IRQMRADIOCTRL (1 << 6) -#define AX5043_REVMDONE 0x1 - -/** - * TX antenna transmission mode - */ -#define AX5043_TX_SINGLE_ENDED 0x2 - -/** - * Radio confguration information - */ -#define CALLSIGN_STATION (uint8_t*) "KG7ZVV" -#define CALLSIGN_DESTINATION (uint8_t*) "" - -#define APRS_UHF 433800000 -#define APRS_UHF_ALT 432500000 - -/****************************************************************************** - ************************* RF Configuration *********************************** - *****************************************************************************/ -#define RX_FREQ_HZ 433000000 -#define TX_FREQ_HZ APRS_UHF - -/** - * Enables/Disables the appropriate setup for deployment on the devboards or - * the - */ -#define PQWS_DEV_BOARD 0 - -/* Reference Oscillator frequency */ -#if PQWS_DEV_BOARD -#define XTAL_FREQ_HZ 48000000 -#else -#define XTAL_FREQ_HZ 26000000 -#endif - -/** - * External PA Control - */ - -#define AX5043_EXT_PA_ENABLE 0 -#define AX5043_EXT_PA_DISABLE 1 - -/** - * Ramp up/Ramp down period of the power amplifier in microseconds - */ -#define PWRAMP_RAMP_PERIOD_US 200 - -#define AX5043_RF_SWITCH_ENABLE ANTSEL_OUTPUT_1 -#define AX5043_RF_SWITCH_DISABLE ANTSEL_OUTPUT_0 - - -#define PKTDATA_BUFLEN 260 - - -/** - * Define error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b - -#define EXIT_FAILURE 1 // Failing exit status. -#define EXIT_SUCCESS 0 // Successful exit status. - -/** - * Frequency mode A or B actually selects at which registers - * the frequency configuration should be written. - * - * This is quite handy for different RX/TX frequencies, to avoid - * writing every time the two different frequency configurations. - */ -typedef enum { - FREQA_MODE = 0, //!< FREQA_MODE - FREQB_MODE = 1 //!< FREQB_MODE -} freq_mode_t; - -typedef enum { - VCO_INTERNAL = 0, - VCO_EXTERNAL = 1 -} vco_mode_t; - -typedef enum -{ - POWERDOWN, - DEEPSLEEP, - STANDBY, - FIFO_ENABLED, - RECEIVE_MODE, - RECEIVER_RUNNING, - RECEIVER_WOR, - TRANSMIT_MODE, - FULLTX -} power_mode_t; - -typedef enum -{ - ANTSEL_OUTPUT_0 = 0, - ANTSEL_OUTPUT_1, - ANTSEL_OUTPUT_Z, - ANTSEL_OUTPUT_BB_TUBE_CLK, - ANTSEL_OUTPUT_EXT_TCXO_EN, - ANTSEL_OUTPUT_DAC, - ANTSEL_OUTPUT_DIVERSITY, - ANTSEL_OUTPUT_TEST_OBS -} pfantsel_t; - - -typedef enum -{ - PWRAMP_OUTPUT_0 = 0, - PWRAMP_OUTPUT_1, - PWRAMP_OUTPUT_Z, - PWRAMP_INPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DiBit_SYNC, - PWRAMP_OUTPUT_DAC, - PWRAMP_OUTPUT_PA_CTRL, - PWRAMP_OUTPUT_EXT_TCXO_EN, - PWRAMP_OUTPUT_TEST_OBS, -} pfpwramp_t; - -typedef enum -{ - AX5043_OK = 0, - AX5043_INVALID_PARAM = 11, - AX5043_TIMEOUT = 12, - AX5043_NOT_FOUND = 13, - AX5043_AUTORANGING_ERROR = 14 -} ax5043_code_t; - -typedef struct -{ - uint32_t tx_freq; - uint32_t rx_freq; - uint32_t f_xtal; - uint8_t f_xtaldiv; - uint32_t tx_baudrate; - uint32_t rx_baudrate; - SPIDriver *spi; - uint8_t rf_init; - freq_mode_t freqsel; - vco_mode_t vco; -} ax5043_conf_t; - - -typedef enum { - trxstate_off, - trxstate_rx, - trxstate_rxwor, - trxstate_wait_xtal, - trxstate_xtal_ready, - trxstate_pll_ranging, - trxstate_pll_ranging_done, - trxstate_pll_settling, - trxstate_pll_settled, - trxstate_tx_xtalwait, - trxstate_tx_longpreamble, - trxstate_tx_shortpreamble, - trxstate_tx_packet, - trxstate_tx_waitdone, - trxstate_txcw_xtalwait, - trxstate_txstream_xtalwait, - trxstate_txstream -} axradio_trxstate_t; - - -//! Structure containing a four byte X.25 address -struct axradio_address { - uint8_t addr[4]; //!< Four byte X.25 address -}; - -struct axradio_address_mask { - uint8_t addr[4]; - uint8_t mask[4]; -}; - -//function declaration starts here -uint8_t ax5043_write_reg_spi(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_write_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -uint8_t ax5043_read_reg(SPIDriver * spip, uint16_t reg, uint8_t value, uint8_t ret_value[]); -void ax5043_set_regs(SPIDriver * spip); -void ax5043_set_regs_tx(SPIDriver * spip); -void ax5043_set_regs_rx(SPIDriver * spip); -void ax5043_set_regs_rxcont(SPIDriver * spip); -void ax5043_set_regs_rxcont_singleparamset(SPIDriver * spip); -void ax5043_shutdown(SPIDriver * spip); -void ax5043_standby(SPIDriver * spip); -void ax5043_fifo_en(SPIDriver * spip); -void ax5043_full_rx(SPIDriver * spip); -void ax5043_synth_tx(SPIDriver * spip); -void ax5043_full_tx(SPIDriver * spip); -void ax5043_reset(SPIDriver * spip); -void ax5043_prepare_tx(SPIDriver * spip); -void ax5043_prepare_rx(SPIDriver * spip); -void ax5043_init_registers_common(SPIDriver * spip); -uint8_t axradio_get_pllvcoi(SPIDriver * spip); - -void ax5043_init(SPIDriver * spip); -void ax5043_transmit(SPIDriver * spip); -void ax5043_receive(SPIDriver * spip); - - -//functions added from bradenburg's code. -uint8_t transmit_packet(SPIDriver * spip, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -void transmit_loop(SPIDriver * spip, axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt); -void ax5043_writefifo(SPIDriver * spip,const uint8_t *ptr, uint8_t len); - -#endif -//! @} diff --git a/src/archive/app_ax5043_morse_tx/source/morse.c b/src/archive/app_ax5043_morse_tx/source/morse.c deleted file mode 100755 index cac5bc95..00000000 --- a/src/archive/app_ax5043_morse_tx/source/morse.c +++ /dev/null @@ -1,183 +0,0 @@ -/* -The code here refers to logic and snippets from Adam Parker - KD5OOL -*/ - -#include -#include - - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "morse.h" -#include "ax5043.h" - - -#define MAX_MESSAGE_SIZE 512 -char beaconMessage[MAX_MESSAGE_SIZE]; -uint16_t ditLength; - -static const char *alpha[] = { - ".-", //A - "-...", //B - "-.-.", //C - "-..", //D - ".", //E - "..-.", //F - "--.", //G - "....", //H - "..", //I - ".---", //J - "-.-", //K - ".-..", //L - "--", //M - "-.", //N - "---", //O - ".--.", //P - "--.-", //Q - ".-.", //R - "...", //S - "-", //T - "..-", //U - "...-", //V - ".--", //W - "-..-", //X - "-.--", //Y - "--..", //Z -}; - -static const char *num[] = { - "-----", //0 - ".----", //1 - "..---", //2 - "...--", //3 - "....-", //4 - ".....", //5 - "-....", //6 - "--...", //7 - "---..", //8 - "----.", //9 -}; - -void SendDot(SPIDriver * spip) -{ - - uint8_t ret_value[3]={0,0,0}; - - ax5043_full_tx(spip); - chprintf(DEBUG_CHP, "Dot\r\n"); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value);//preamble - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - chThdSleepMilliseconds(DIT_MS); - ax5043_standby(spip); - -} - -void SendDash(SPIDriver * spip) -{ - - uint8_t ret_value[3]={0,0,0}; - - ax5043_full_tx(spip); - chprintf(DEBUG_CHP, "Dash\r\n"); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - ax5043_write_reg(&SPID2, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value);//preamble - ax5043_write_reg(&SPID2, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - chThdSleepMilliseconds(DASH_MS); - ax5043_standby(spip); -} - -void LetterSleep(void) -{ - chThdSleepMilliseconds(LETTER_SPACE_MS); -} - -void WordSleep(void) -{ - chThdSleepMilliseconds(WORD_SPACE_MS); -} - -void ElementSleep(void) -{ - chThdSleepMilliseconds(DIT_MS); -} - -//sets ditLength in ms -void SetWpm(int wpm) -{ - ditLength = 1200/wpm; - chprintf(DEBUG_CHP, "ditLength = %d\r\n", ditLength); -} - -void SetMessage(char *message) -{ - memset(beaconMessage, 0, MAX_MESSAGE_SIZE); - int len = strlen(message); - if (strlen(message) >= MAX_MESSAGE_SIZE) - len = MAX_MESSAGE_SIZE-1; - memcpy(beaconMessage, message, len); -} - -const char *AsciiToMorse(char letter) -{ - letter = tolower(letter); - - if (isalpha(letter)) - { - return alpha[letter-'a']; - } - else if (isdigit(letter)) - { - return num[letter-'0']; - } - - return SPACE; -} - -void SendMessage(SPIDriver * spip) -{ - int element; - int index = 0; - const char *morse; - while (beaconMessage[index] != '\0') - { - morse = AsciiToMorse(beaconMessage[index]); - - element = 0; - while (morse[element] != '\0') - { - switch(morse[element]) - { - case '-': - SendDash(spip); - break; - case '.': - SendDot(spip); - } - - if (morse[element] == ' ') - { - WordSleep(); - } - else if (morse[element+1] != '\0') - { - ElementSleep(); - } - else if (morse[element+1] == '\0') - { - LetterSleep(); - } - element++; - } - - index++; - } -} - - diff --git a/src/archive/app_ax5043_morse_tx/source/morse.h b/src/archive/app_ax5043_morse_tx/source/morse.h deleted file mode 100755 index 3d1a9a2c..00000000 --- a/src/archive/app_ax5043_morse_tx/source/morse.h +++ /dev/null @@ -1,27 +0,0 @@ - -#ifndef _MORSE_H_ -#define _MORSE_H_ - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#define SPACE " " - - -#define LETTER_SPACE_MS (ditLength*3) -#define WORD_SPACE_MS (ditLength*7) -#define DIT_MS (ditLength) -#define DASH_MS (ditLength*3) - - - -void SendDot(SPIDriver * spip); -void SendDash(SPIDriver * spip); -void LetterSleep(void); -void WordSleep(void); -void ElementSleep(void); -void SetWpm(int wpm); -void SetMessage(char *message); -void SendMessage(SPIDriver * spip); - -#endif diff --git a/src/archive/app_can_updater/Makefile b/src/archive/app_can_updater/Makefile deleted file mode 100644 index 5d123e62..00000000 --- a/src/archive/app_can_updater/Makefile +++ /dev/null @@ -1,207 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_f407_discovery - -# Target settings. -MCU = cortex-m4 -BOARD = ORESAT_C3_V3 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -#include $(PROJ_SRC)/oresat.mk -include $(PROJ_SRC)/bootloader.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -#include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_can_updater/cfg/chconf.h b/src/archive/app_can_updater/cfg/chconf.h deleted file mode 100644 index cec42e04..00000000 --- a/src/archive/app_can_updater/cfg/chconf.h +++ /dev/null @@ -1,756 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_can_updater/cfg/halconf.h b/src/archive/app_can_updater/cfg/halconf.h deleted file mode 100644 index 0424c960..00000000 --- a/src/archive/app_can_updater/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_can_updater/cfg/mcuconf.h b/src/archive/app_can_updater/cfg/mcuconf.h deleted file mode 100644 index d193ad22..00000000 --- a/src/archive/app_can_updater/cfg/mcuconf.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF -#define STM32F405_MCUCONF -#define STM32F415_MCUCONF -#define STM32F407_MCUCONF -#define STM32F417_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 5 - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_HOST_WAKEUP_DURATION 2 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_can_updater/main.c b/src/archive/app_can_updater/main.c deleted file mode 100644 index 28bfdc26..00000000 --- a/src/archive/app_can_updater/main.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" -#include "rt_test_root.h" -#include "oslib_test_root.h" -#include "chprintf.h" -#include "string.h" -#include "can_bootloader.h" -#include "oresat_f0.h" - -#include "firmware_blob.h" - -#define DEBUG_SD (BaseSequentialStream *) &SD2 - -/* - * This is a periodic thread that does absolutely nothing except flashing - * a LED. - */ -static THD_WORKING_AREA(waThread1, 128); -static THD_FUNCTION(Thread1, arg) { - (void)arg; - chRegSetThreadName("blinker"); - while (true) { - palSetPad(GPIOD, GPIOD_LED3); /* Orange. */ - chThdSleepMilliseconds(500); - palClearPad(GPIOD, GPIOD_LED3); /* Orange. */ - chThdSleepMilliseconds(500); - } -} - -#define CAN_DRIVER &CAND1 - -#define CAN_BTR(n) (CAN_BTR_SJW(0)|CAN_BTR_TS1(11)|CAN_BTR_TS2(1)|CAN_BTR_BRP((3000/n)-1)) - - - -// xxd -i app_protocard2.crc32.bin > ../../../f4/app_f407_discovery/firmware_blob.h -/* - * This is an example of reading source firmware image data from an in-memory buffer, but this function could be implemented - * to open a file from a file system, seek to an offset in the file, read some data into dest_buffer and close the file. - */ -uint32_t firmware_blob_read_function(const uint32_t offset, uint8_t *dest_buffer, const uint32_t number_of_bytes) { - uint32_t dest_index = 0; - - for(; dest_index < number_of_bytes; dest_index++ ) { - if( (offset + dest_index) < app_protocard2_crc32_bin_len ) { - dest_buffer[dest_index] = app_protocard2_crc32_bin[offset + dest_index]; - } else { - break; - } - } - - return(dest_index); -} - -uint32_t test_read_function(const uint32_t offset, uint8_t *dest_buffer, const uint32_t number_of_bytes) { - chprintf(DEBUG_SD, "Calling test_read_function(%u, x, %u)\r\n", offset, number_of_bytes); - - uint32_t dest_index = 0; - for(; dest_index < number_of_bytes; dest_index++ ) { - dest_buffer[dest_index] = (offset + dest_index) % 0xFF; - } - - return(dest_index); -} - -void test_garbage_can_transmit(void) { - while(1) { - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = 0x55; - tx_msg.DLC = 8; - memset(&tx_msg.data8, 0x55, sizeof(tx_msg.data8)); - - can_api_print_tx_frame(DEBUG_SD, &tx_msg, "", ""); - - canTransmit(CAN_DRIVER, CAN_ANY_MAILBOX, &tx_msg, TIME_MS2I(150)); - chThdSleepMilliseconds(1000); - } -} - - -/* - * Application entry point. - */ -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - /* - * Activates the serial driver 2 using the driver default configuration. - * PA2(TX) and PA3(RX) are routed to USART2. - */ - sdStart(&SD2, NULL); - - palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); - palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); - chprintf(DEBUG_SD, "\r\n=======================================\r\n"); - chprintf(DEBUG_SD, "\r\n=========== discovery =================\r\n"); - chprintf(DEBUG_SD, "STM32_PCLK2 = %u\r\n", STM32_PCLK2); - - - palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(9)); //CAN 1 RX - palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(9)); //CAN 1 TX - - palSetPadMode(GPIOB, 5, PAL_MODE_ALTERNATE(9)); //CAN 2 RX - palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(9)); //CAN 2 TX - - - CANConfig cancfg; - memset(&cancfg, 0, sizeof(cancfg)); - - -#define TARGET_STM32_BOOTLOADER 0 - - - //http://www.bittiming.can-wiki.info/ -#if TARGET_STM32_BOOTLOADER - cancfg.btr = (CAN_BTR_SJW(0) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1) | CAN_BTR_BRP(20)); -#else - cancfg.btr = (CAN_BTR_SJW(0) | CAN_BTR_TS1(10) | CAN_BTR_TS2(1) | CAN_BTR_BRP(2)); -#endif - cancfg.mcr = ( - /* MCR (Master Control Register) */ - CAN_MCR_ABOM | //Automatic Bus-Off Management - CAN_MCR_AWUM | //Automatic Wakeup Mode - CAN_MCR_TXFP | //Transmit FIFO Priority - 0/*CAN_MCR_NART*/ ); // No Automatic Retransmission - - chprintf(DEBUG_SD, "Initializing CAN peripheral with MCR = 0x%X\r\n", cancfg.mcr); - chprintf(DEBUG_SD, "Initializing CAN peripheral with BTR = 0x%X\r\n", cancfg.btr); - - - canSTM32SetFilters(CAN_DRIVER, 0, 0, NULL); - canStart(CAN_DRIVER, &cancfg); - - /* Put CAN module in normal mode */ - //canSTM32SetFilters(&CAND2, 0, 0, NULL); - //canStart(&CAND2, &cancfg); - - chprintf(DEBUG_SD, "Done starting CAN peripheral\r\n"); - - - //can_bootloader_test(CAN_DRIVER, DEBUG_SD); - /* - * Creates the example thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - -#if TARGET_STM32_BOOTLOADER - can_bootloader_config_t can_bl_config; - can_api_init_can_bootloader_config_t(&can_bl_config, CAN_DRIVER, DEBUG_SD, 0, true); - - //can_bootloader_initiate(&can_bl_config, 3000); - //can_bootloader_test(&can_bl_config); - oresat_firmware_update_m0(&can_bl_config, 0x08000000, 16, test_read_function); - -#else - const uint32_t low_cpuid_of_protoboard = 0x1D000800; - can_bootloader_config_t can_bl_config; - can_api_init_can_bootloader_config_t(&can_bl_config, CAN_DRIVER, DEBUG_SD, low_cpuid_of_protoboard, false); - - //test_garbage_can_transmit(); - //oresat_firmware_update_m0(&can_bl_config, ORESAT_F0_FIRMWARE_CRC_ADDRESS, 72, test_read_function); - - oresat_firmware_update_m0(&can_bl_config, ORESAT_F0_FIRMWARE_CRC_ADDRESS, app_protocard2_crc32_bin_len, firmware_blob_read_function); -#endif - - print_can_bootloader_config_t(&can_bl_config); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (true) { -#if 0 - CANTxFrame tx_msg; - memset(&tx_msg, 0, sizeof(tx_msg)); - tx_msg.SID = 0x79; - tx_msg.DLC = 8; - memset(&tx_msg.data8, 0x55, sizeof(tx_msg.data8)); - - can_api_print_tx_frame(DEBUG_SD, &tx_msg, "TXing: ", ""); - - canTransmit(CAN_DRIVER, CAN_ANY_MAILBOX, &tx_msg, TIME_MS2I(150)); - -#endif - -#if 0 - CANRxFrame rx_msg; - memset(&rx_msg, 0, sizeof(rx_msg)); - chprintf(DEBUG_SD, "CAN State: %u\r\n", (CAN_DRIVER)->state); - chprintf(DEBUG_SD, "Attempting CAN RX....\r\n"); - can_api_receive(&can_bl_config, &rx_msg, 1000); -#endif - - -#if 0 - if (palReadPad(GPIOA, GPIOA_BUTTON)) { - test_execute((BaseSequentialStream *)&SD2, &rt_test_suite); - test_execute((BaseSequentialStream *)&SD2, &oslib_test_suite); - } -#endif - chThdSleepMilliseconds(500); - } -} - - - - - - diff --git a/src/archive/app_can_updater/source/firmware_blob.h b/src/archive/app_can_updater/source/firmware_blob.h deleted file mode 100644 index 31c1f659..00000000 --- a/src/archive/app_can_updater/source/firmware_blob.h +++ /dev/null @@ -1,3625 +0,0 @@ -unsigned char app_protocard2_crc32_bin[] = { - 0xf6, 0x37, 0x29, 0xd7, 0xc0, 0xa9, 0x00, 0x00, 0x85, 0x62, 0x34, 0x01, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0xe8, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00, 0x00, - 0x6c, 0x22, 0x00, 0x20, 0x30, 0x00, 0xe8, 0x03 -}; -unsigned int app_protocard2_crc32_bin_len = 43460; diff --git a/src/archive/app_oresat_acs-0.1/Makefile b/src/archive/app_oresat_acs-0.1/Makefile deleted file mode 100644 index 0ebef96e..00000000 --- a/src/archive/app_oresat_acs-0.1/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x200 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x200 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_oresat_acs - -# Target settings. -MCU = cortex-m0 -BOARD = ST_NUCLEO32_F042K6 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F042x6.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_oresat_acs-0.1/README.md b/src/archive/app_oresat_acs-0.1/README.md deleted file mode 100644 index 55f3c8e2..00000000 --- a/src/archive/app_oresat_acs-0.1/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` diff --git a/src/archive/app_oresat_acs-0.1/cfg/chconf.h b/src/archive/app_oresat_acs-0.1/cfg/chconf.h deleted file mode 100644 index 6f3b51a9..00000000 --- a/src/archive/app_oresat_acs-0.1/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-0.1/cfg/halconf.h b/src/archive/app_oresat_acs-0.1/cfg/halconf.h deleted file mode 100644 index af83724c..00000000 --- a/src/archive/app_oresat_acs-0.1/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT TRUE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-0.1/cfg/mcuconf.h b/src/archive/app_oresat_acs-0.1/cfg/mcuconf.h deleted file mode 100644 index cf6d97da..00000000 --- a/src/archive/app_oresat_acs-0.1/cfg/mcuconf.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 12 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_USART1SW STM32_USART1SW_PCLK -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 -#define STM32_IRQ_USART1_PRIORITY 3 -#define STM32_IRQ_USART2_PRIORITY 3 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM14 TRUE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_oresat_acs-0.1/main.c b/src/archive/app_oresat_acs-0.1/main.c deleted file mode 100644 index a7bc5a2d..00000000 --- a/src/archive/app_oresat_acs-0.1/main.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * OreSat: Attitude Control System - * Portland State Aerospace Society (PSAS) - * - * // be wery wery quiet i'm hunting wabbits... - * - * // add your name if you code things - * // and you are paying attention - * // and you want your code things in - * // space - * - * // o_0 - * - * Chad Coates - * - */ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" - -//=== Project header files -#include "oresat.h" -#include "acs.h" - -ACSdata data = {}; - -static SerialConfig ser_cfg = { - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - -static void app_init(void){ - acsInit(&data); - //data.acs[0] = 1; - canRPDOObjectInit(CAN_PDO_1,CAN_ID_DEFAULT,CAN_BUF,data.recv); -// initTPDO(); - canTPDOObjectInit(CAN_PDO_1,CAN_ID_DEFAULT,0,0,CAN_BUF,data.send); - - sdStart(&SD2,&ser_cfg); // Start up debug output -} - -static void app_main(void){ -//* - chThdCreateStatic( - wa_acsThread, - sizeof(wa_acsThread), - NORMALPRIO, - acsThread, - NULL - ); -//*/ -//* - chThdCreateStatic( - wa_spiThread, - sizeof(wa_spiThread), - HIGHPRIO, - spiThread, - NULL - ); - - /*chThdCreateStatic( - wa_debugThread, - sizeof(wa_debugThread), - NORMALPRIO, - debugThread, - NULL - );*/ -//*/ - while(true){ - chThdSleepMilliseconds(1000); - } -} - -int main(void) { - halInit(); - chSysInit(); - - oresat_init(CAN_NODE); - - app_init(); - app_main(); - - return 0; -} diff --git a/src/archive/app_oresat_acs-0.1/source/README.md b/src/archive/app_oresat_acs-0.1/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_oresat_acs-0.1/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_oresat_acs-0.1/source/acs.c b/src/archive/app_oresat_acs-0.1/source/acs.c deleted file mode 100644 index c83b0cae..00000000 --- a/src/archive/app_oresat_acs-0.1/source/acs.c +++ /dev/null @@ -1,495 +0,0 @@ -#include "acs.h" -#include "acs_lut.h" - - -// static virtual_timer_t speed_vt; - -// static sysinterval_t interval = 0; -//static uint32_t anglePrev, angleCurr; -//static uint32_t angleDelta = 0; -//static uint32_t rps = 0; -//static uint32_t time = 0; - -//static systime_t now; -//static systime_t prv; - -BldcConfig bldc; -uint16_t rxbuf[2] = {0}; // receive buffer - -/* -static void gpt4cb(GPTDriver *gptp) { - (void)gptp; - // Perform your action here - - anglePrev = angleCurr; - angleCurr = bldc.position; - angleDelta = 5;//angleCurr - anglePrev; - - rps = angleDelta * 10; - - - gptStartOneShotI(&GPTD14, 100000); // ~100 ns delay, then stop timer -} - -static const GPTConfig gpt4cfg = { - 100000, // 1 MHz timer clock. - gpt4cb, // No callback - 0, 0 -};*/ - -/* -static void speed_cb(void * arg) -{ - //chVTSetI(&speed_vt, TIME_MS2I(100), speed_cb, NULL); - - anglePrev = angleCurr; - angleCurr = bldc.position; - angleDelta = angleCurr - anglePrev; - - rps = angleDelta * 10; -}*/ - -static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { - (void)adcp; - (void)err; -} - -/* - * ADC conversion group. - * Mode: Continuous, 8 samples of 1 channel, SW triggered. - * Channels: A0 - */ -static const ADCConversionGroup adcgrpcfg = { - TRUE, - ADC_GRP_NUM_CHANNELS, - NULL, - adcerrorcallback, - ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */ - ADC_TR(0, 0), /* TR */ - ADC_SMPR_SMP_239P5, /* SMPR */ - ADC_CHSELR_CHSEL0 /* CHSELR */ -}; - - -uint32_t step_size = STRETCH; - -uint32_t current_sin_u, next_sin_u; -uint32_t current_sin_v, next_sin_v; -uint32_t current_sin_w, next_sin_w; -uint16_t sin_diff; -uint16_t sin_size; -uint16_t sin_step = STRETCH; - -THD_WORKING_AREA(wa_acsThread,THREAD_SIZE); -THD_FUNCTION(acsThread,arg) { - (void)arg; - chRegSetThreadName("acsThread"); - - bldcStart(); - - while (!chThdShouldTerminateX()) { - - chprintf(DEBUG_CHP,"enc pos: %u \n\r", bldc.position); - chprintf(DEBUG_CHP,"phase 1: %u \n\r", bldc.u); - chprintf(DEBUG_CHP,"phase 2: %u \n\r", bldc.v); - chprintf(DEBUG_CHP,"phase 3: %u \n\r", bldc.w); - chprintf(DEBUG_CHP,"step_size: %u \n\n\r", step_size); - chThdSleepMilliseconds(500); - - chprintf(DEBUG_CHP, "ADC: %u \n\r", (int)bldc.samples[0]); - - } -} - -THD_WORKING_AREA(wa_spiThread,THREAD_SIZE); -THD_FUNCTION(spiThread,arg){ - (void)arg; - chRegSetThreadName("spiThread"); - - spiStart(&SPID1, &spicfg); // Start driver. - spiAcquireBus(&SPID1); // Gain ownership of bus. - - while (!chThdShouldTerminateX()) { - rxbuf[0] = 0; - spiSelect(&SPID1); // Select slave. - - spiReceive(&SPID1,1,rxbuf); // Receive 1 frame (16 bits). - - spiUnselect(&SPID1); // Unselect slave. - bldc.position = 0x3FFF & rxbuf[0]; - - chThdSleepMicroseconds(1); - } - - spiReleaseBus(&SPID1); // Release ownership of bus. - spiStop(&SPID1); // Stop driver. -} - - -THD_WORKING_AREA(wa_debugThread,THREAD_SIZE); -THD_FUNCTION(debugThread,arg) { - (void)arg; - chRegSetThreadName("debugThread"); - //chThdSleepMilliseconds(100); -} - -/* - Sections off value from encoder (0 - 2^14) - into chunks of 0-360 for the LUT. - TODO MAX: clean this up. -*/ - -static uint16_t chunk0L = 0 * ENCODER_CHUNK_SIZE; -static uint16_t chunk0H = 1 * ENCODER_CHUNK_SIZE; - -static uint16_t chunk1L = 1 * ENCODER_CHUNK_SIZE; -static uint16_t chunk1H = 2 * ENCODER_CHUNK_SIZE; - -static uint16_t chunk2L = 2 * ENCODER_CHUNK_SIZE; -static uint16_t chunk2H = 3 * ENCODER_CHUNK_SIZE; - -static uint16_t chunk3L = 3 * ENCODER_CHUNK_SIZE; -static uint16_t chunk3H = 4 * ENCODER_CHUNK_SIZE; - -static uint16_t chunk4L = 4 * ENCODER_CHUNK_SIZE; -static uint16_t chunk4H = 5 * ENCODER_CHUNK_SIZE; - -static uint16_t chunk5L = 5 * ENCODER_CHUNK_SIZE; -static uint16_t chunk5H = 6 * ENCODER_CHUNK_SIZE; - - -// Uses above defines to translate encoder feedback -// into the proper LUT index. -static uint16_t encoderToLUT(uint16_t position) -{ - uint16_t step = 0; - if (position > chunk0L && position < chunk0H) - { - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - else if (position > chunk1L && position < chunk1H) - { - position = position - (ENCODER_CHUNK_SIZE*1); - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - else if (position > chunk2L && position < chunk2H) - { - - position = position - (ENCODER_CHUNK_SIZE*2); - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - else if (position > chunk3L && position < chunk3H) - { - - position = position - (ENCODER_CHUNK_SIZE*3); - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - else if (position > chunk4L && position < chunk4H) - { - - position = position - (ENCODER_CHUNK_SIZE*4); - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - else if (position > chunk5L && position < chunk5H) - { - - position = position - (ENCODER_CHUNK_SIZE*5); - step = position * STEPS / (ENCODER_CHUNK_SIZE); - } - - return step; -} - -//static uint32_t LUTrevCount = 0; - -// TODO Max, instead of increments of 10%, get finer control. -static sinctrl_t scale(sinctrl_t duty_cycle){ - return (duty_cycle*bldc.scale)/10; -} - -// Temporary for ramping function, hopefully can simulate this with CAN -uint16_t count = 0; - -bool down = false; - - -// TODO Max, find a way to separate the types of control -// easily with CAN. Probably a simple case statement - -// pwm period callback -static void pwmpcb(PWMDriver *pwmp) { - (void)pwmp; - - uint16_t step; - uint16_t next_step; - palClearLine(LINE_LED_GREEN); - - if (count > 2000) - { - if (!down) - { - step_size++; - } - else - { - step_size = step_size - 1; - } - count = 0; - } - - if (step_size >= 80) - { - down = true; - } - else if (step_size < 2) - { - down = false; - } - -// TODO Max, do we want the configure stuff for any reason? -#ifdef CONFIGURE - - if (LUTrevCount < 6 * 360) - { - if (bldc.count == bldc.stretch){ - bldc.u += STEP_SIZE; - bldc.v += STEP_SIZE; - bldc.w += STEP_SIZE; - - LUTrevCount++; - - if(bldc.u >= bldc.steps){ - bldc.u = 0 + bldc.u - bldc.steps; - } - if(bldc.v >= bldc.steps){ - bldc.v = 0 + bldc.v - bldc.steps; - } - if(bldc.w >= bldc.steps){ - bldc.w = 0 + bldc.w - bldc.steps; - } - bldc.count = 0; - } - ++bldc.count; - } - else - { - bldc.u = 0; - bldc.v = 120; - bldc.w = 240; - } - - -#endif - -#ifndef CONFIGURE -#ifdef BRUTEFORCE - bldc.u += step_size; - bldc.v += step_size; - bldc.w += step_size; - - if(bldc.u >= bldc.steps){ - bldc.u = 0 + bldc.u - bldc.steps; - } - if(bldc.v >= bldc.steps){ - bldc.v = 0 + bldc.v - bldc.steps; - } - if(bldc.w >= bldc.steps){ - bldc.w = 0 + bldc.w - bldc.steps; - } -#endif -#ifndef BRUTEFORCE -// This is the encoder feedback. -// TODO Max, this really needs to be cleaned up. -if (sin_step == step_size) -{ - step = encoderToLUT(bldc.position); - next_step = step + SKIP; - - - - bldc.u = (next_step)%360; - bldc.v = (bldc.u + bldc.phase_shift)%360; - bldc.w = (bldc.v + bldc.phase_shift)%360; - -} -#endif -#endif -if (SKIP) -{ -if (sin_step == step_size) -{ - current_sin_u = bldc.sinctrl[bldc.u]; - current_sin_v = bldc.sinctrl[bldc.v]; - current_sin_w = bldc.sinctrl[bldc.w]; - next_sin_u = bldc.sinctrl[bldc.u + 1]; - next_sin_v = bldc.sinctrl[bldc.v + 1]; - next_sin_w = bldc.sinctrl[bldc.w + 1]; - - if (current_sin_u < next_sin_u) - { - sin_diff = next_sin_u - current_sin_u; - - sin_size = sin_diff / step_size; - } - else if (current_sin_v < next_sin_v) - { - sin_diff = next_sin_v - current_sin_v; - sin_size = sin_diff / step_size; - } - else - { - sin_diff = next_sin_w - current_sin_w; - sin_size = sin_diff / step_size; - } -} - -current_sin_u = current_sin_u + sin_size; -current_sin_v = current_sin_v + sin_size; -current_sin_w = current_sin_w + sin_size; - -sin_step = sin_step - 1; - -if (sin_step == 0) -{ - current_sin_u = next_sin_u; - current_sin_v = next_sin_v; - current_sin_w = next_sin_w; - sin_step = step_size; -} -} -else -{ - current_sin_u = bldc.sinctrl[bldc.u]; - current_sin_v = bldc.sinctrl[bldc.v]; - current_sin_w = bldc.sinctrl[bldc.w]; -} - -pwmEnableChannelI( - &PWMD1, - PWM_U, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(current_sin_u))); - -pwmEnableChannelI( - &PWMD1, - PWM_V, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(current_sin_v)) - ); - -pwmEnableChannelI( - &PWMD1, - PWM_W, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(current_sin_w)) - ); - - count++; -} - - - - - -static void pwmCallback(uint8_t channel,sinctrl_t step){ - // palSetLine(LINE_LED_GREEN); - pwmEnableChannelI( - &PWMD1, - channel, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(bldc.sinctrl[step])) - ); - -} - -static void pwmUcb(PWMDriver *pwmp){ // channel 1 callback - (void)pwmp; - //pwmCallback(PWM_U,bldc.u); -} - -static void pwmVcb(PWMDriver *pwmp){ // channel 2 callback - (void)pwmp; - //pwmCallback(PWM_V,bldc.v); -} - -static void pwmWcb(PWMDriver *pwmp){ // channel 3 callback - (void)pwmp; - //pwmCallback(PWM_W,bldc.w); -} - -static PWMConfig pwmcfg = { - PWM_TIMER_FREQ, - PWM_PERIOD, - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmUcb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmVcb}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH,pwmWcb}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, - 0, - 0 -}; - -extern void acsInit(ACSdata *data){ - bldc.data = data; - bldcInit(); - // TODO MAX wrap up into adcInit - adcStart(&ADCD1, NULL); - - /* - * Starts an ADC continuous conversion. - */ - adcStartConversion(&ADCD1, &adcgrpcfg, bldc.samples, ADC_GRP_BUF_DEPTH); - - - //gptStart(&GPTD14, &gpt4cfg); - //gptStartOneShot(&GPTD14, 100000); // ~100 ns delay, then stop timer - - - - //chVTObjectInit(&speed_vt); - //chVTSet(&speed_vt, TIME_MS2I(100), speed_cb, NULL); -} - -extern void bldcInit(){ - bldc.steps = STEPS; - bldc.stretch = STRETCH; - bldc.scale = SCALE; - bldc.sinctrl = sinctrl360; - bldc.count = 0; - bldc.position = 0; - bldc.phase_shift = bldc.steps/3; - bldc.u = 0; - bldc.v = bldc.u + bldc.phase_shift; - bldc.w = bldc.v + bldc.phase_shift; -} - - - -extern void bldcStart(){ - palSetLine(LINE_LED_GREEN); - pwmStart(&PWMD1,&pwmcfg); - pwmEnablePeriodicNotification(&PWMD1); - - pwmEnableChannel(&PWMD1,PWM_U,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.u)); - pwmEnableChannel(&PWMD1,PWM_V,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.v)); - pwmEnableChannel(&PWMD1,PWM_W,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.w)); - - pwmEnableChannelNotification(&PWMD1,PWM_U); - pwmEnableChannelNotification(&PWMD1,PWM_V); - pwmEnableChannelNotification(&PWMD1,PWM_W); -} - -extern void bldcStop(){ - palClearLine(LINE_LED_GREEN); - pwmStop(&PWMD1); -/* - pwmEnablePeriodicNotification(&PWMD1); - - pwmEnableChannel(&PWMD1,PWM_U,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.u)); - pwmEnableChannel(&PWMD1,PWM_V,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.v)); - pwmEnableChannel(&PWMD1,PWM_W,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,bldc.w)); - - pwmEnableChannelNotification(&PWMD1,PWM_U); - pwmEnableChannelNotification(&PWMD1,PWM_V); - pwmEnableChannelNotification(&PWMD1,PWM_W); -*/ -} diff --git a/src/archive/app_oresat_acs-0.1/source/acs.h b/src/archive/app_oresat_acs-0.1/source/acs.h deleted file mode 100644 index baf116c8..00000000 --- a/src/archive/app_oresat_acs-0.1/source/acs.h +++ /dev/null @@ -1,101 +0,0 @@ -#ifndef _ACS_H_ -#define _ACS_H_ - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "string.h" - -//#define BRUTEFORCE -//#define CONFIGURE - -#define CH_DBG_SYSTEM_STATE_CHECK TRUE - -#define THREAD_SIZE (120) -#define CAN_NODE 0x3F // max 0x7f -#define CAN_BUF 8 - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#define SCALE 2 -#define STEPS 360 -#define STRETCH 1 -#define STEP_SIZE 1 -#define SKIP 1 - -#define COIL_NUM 6 - -#define ENCODER_MAX 2^14 -#define ENCODER_MIN 0 -#define ENCODER_CHUNK_SIZE 2730 - -#define PWM_TIMER_FREQ 48e6 // Hz - -//************************************************************** -// -// TODO: we need to do math ASAP -// -#define PWM_FREQ 20e3 // periods per sec -//#define PWM_FREQ 30e3 // periods per sec -#define PWM_PERIOD PWM_TIMER_FREQ/PWM_FREQ - -#define PWM_U 0U -#define PWM_V 1U -#define PWM_W 2U -#define PWM_MTQR 3u - -#define sinctrl_t uint16_t - -#define ADC_GRP_NUM_CHANNELS 1 -#define ADC_GRP_BUF_DEPTH 8 - -typedef struct{ - uint8_t send[CAN_BUF]; - uint8_t recv[CAN_BUF]; -} ACSdata; - -typedef struct{ - int count, // period counter - scale, // scales the duty cycle - steps, // number of steps in lut - stretch; - sinctrl_t u,v,w, // signals - phase_shift; // - uint16_t position; // motor position from encoder - sinctrl_t const *sinctrl; // pointer to the sin lut - - adcsample_t samples[ADC_GRP_NUM_CHANNELS * ADC_GRP_BUF_DEPTH]; // ADC conversion storage array - -} BldcConfig; - -static const SPIConfig spicfg = { - false, // Enables circular buffer if == 1 - NULL, // Operation complete call back. - GPIOA, // Chip select line - GPIOA_SPI1_NSS, // Chip select port - SPI_CR1_BR_0|SPI_CR1_CPHA,//reg 1 mask - SPI_CR2_DS_0|SPI_CR2_DS_1|SPI_CR2_DS_2|SPI_CR2_DS_3,//reg 2 mask -}; - -typedef struct{ - // o_0 -}ACSConfig; - -extern THD_WORKING_AREA(wa_acsThread,THREAD_SIZE); -extern THD_FUNCTION(acsThread,arg); - -extern THD_WORKING_AREA(wa_spiThread,THREAD_SIZE); -extern THD_FUNCTION(spiThread,arg); - -extern THD_WORKING_AREA(wa_debugThread,THREAD_SIZE); -extern THD_FUNCTION(debugThread,arg); - - - -extern void acsInit(void); -extern void bldcInit(void); -extern void bldcStart(void); -extern void bldcStop(void); - -#endif diff --git a/src/archive/app_oresat_acs-0.1/source/acs_lut.h b/src/archive/app_oresat_acs-0.1/source/acs_lut.h deleted file mode 100644 index cf888753..00000000 --- a/src/archive/app_oresat_acs-0.1/source/acs_lut.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef _ACS_LUT_H_ -#define _ACS_LUT_H_ - -#include "acs.h" - -const sinctrl_t sinctrl360[360] = { - 5000,5087,5174,5262,5349,5436,5523,5609, - 5696,5782,5868,5954,6040,6125,6210,6294, - 6378,6462,6545,6628,6710,6792,6873,6954, - 7034,7113,7192,7270,7347,7424,7500,7575, - 7650,7723,7796,7868,7939,8009,8078,8147, - 8214,8280,8346,8410,8473,8536,8597,8657, - 8716,8774,8830,8886,8940,8993,9045,9096, - 9145,9193,9240,9286,9330,9373,9415,9455, - 9494,9532,9568,9603,9636,9668,9698,9728, - 9755,9782,9806,9830,9851,9872,9891,9908, - 9924,9938,9951,9963,9973,9981,9988,9993, - 9997,9999,10000,9999,9997,9993,9988,9981, - 9973,9963,9951,9938,9924,9908,9891,9872, - 9851,9830,9806,9782,9755,9728,9698,9668, - 9636,9603,9568,9532,9494,9455,9415,9373, - 9330,9286,9240,9193,9145,9096,9045,8993, - 8940,8886,8830,8774,8716,8657,8597,8536, - 8473,8410,8346,8280,8214,8147,8078,8009, - 7939,7868,7796,7723,7650,7575,7500,7424, - 7347,7270,7192,7113,7034,6954,6873,6792, - 6710,6628,6545,6462,6378,6294,6210,6125, - 6040,5954,5868,5782,5696,5609,5523,5436, - 5349,5262,5174,5087,5000,4913,4826,4738, - 4651,4564,4477,4391,4304,4218,4132,4046, - 3960,3875,3790,3706,3622,3538,3455,3372, - 3290,3208,3127,3046,2966,2887,2808,2730, - 2653,2576,2500,2425,2350,2277,2204,2132, - 2061,1991,1922,1853,1786,1720,1654,1590, - 1527,1464,1403,1343,1284,1226,1170,1114, - 1060,1007,955,904,855,807,760,714, - 670,627,585,545,506,468,432,397, - 364,332,302,272,245,218,194,170, - 149,128,109,92,76,62,49,37, - 27,19,12,7,3,1,0,1, - 3,7,12,19,27,37,49,62, - 76,92,109,128,149,170,194,218, - 245,272,302,332,364,397,432,468, - 506,545,585,627,670,714,760,807, - 855,904,955,1007,1060,1114,1170,1226, - 1284,1343,1403,1464,1527,1590,1654,1720, - 1786,1853,1922,1991,2061,2132,2204,2277, - 2350,2425,2500,2576,2653,2730,2808,2887, - 2966,3046,3127,3208,3290,3372,3455,3538, - 3622,3706,3790,3875,3960,4046,4132,4218, - 4304,4391,4477,4564,4651,4738,4826,4913 -}; - -#endif diff --git a/src/archive/app_oresat_acs-1.0/Makefile b/src/archive/app_oresat_acs-1.0/Makefile deleted file mode 100644 index 0ebef96e..00000000 --- a/src/archive/app_oresat_acs-1.0/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x200 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x200 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_oresat_acs - -# Target settings. -MCU = cortex-m0 -BOARD = ST_NUCLEO32_F042K6 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F042x6.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_oresat_acs-1.0/README.md b/src/archive/app_oresat_acs-1.0/README.md deleted file mode 100644 index 7816ee1b..00000000 --- a/src/archive/app_oresat_acs-1.0/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` - -Commands for interacting with the can bus - -sudo slcand -o -c -f -s6 /dev/serial/by-id/*CANtact*-if00 -sudo ip link set slcan0 up -candump slcan0 -``` diff --git a/src/archive/app_oresat_acs-1.0/caniface.sh b/src/archive/app_oresat_acs-1.0/caniface.sh deleted file mode 100755 index bbfca201..00000000 --- a/src/archive/app_oresat_acs-1.0/caniface.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -`sudo slcand -o -c -f -s6 /dev/serial/by-id/*CANtact*-if00` -`sudo ip link set slcan0 up` diff --git a/src/archive/app_oresat_acs-1.0/cfg/chconf.h b/src/archive/app_oresat_acs-1.0/cfg/chconf.h deleted file mode 100644 index 6f3b51a9..00000000 --- a/src/archive/app_oresat_acs-1.0/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-1.0/cfg/halconf.h b/src/archive/app_oresat_acs-1.0/cfg/halconf.h deleted file mode 100644 index a06ea4f6..00000000 --- a/src/archive/app_oresat_acs-1.0/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-1.0/cfg/mcuconf.h b/src/archive/app_oresat_acs-1.0/cfg/mcuconf.h deleted file mode 100644 index cde64fa5..00000000 --- a/src/archive/app_oresat_acs-1.0/cfg/mcuconf.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 3 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_SYSCLK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_USART1SW STM32_USART1SW_HSI -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 -#define STM32_IRQ_USART1_PRIORITY 3 -#define STM32_IRQ_USART2_PRIORITY 3 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_oresat_acs-1.0/main.c b/src/archive/app_oresat_acs-1.0/main.c deleted file mode 100644 index e5385dd9..00000000 --- a/src/archive/app_oresat_acs-1.0/main.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" - -//=== Project header files -#include "acs.h" - -// global ACS structure -ACS acs = {}; - -//=== Serial configuration -static SerialConfig ser_cfg ={ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - -/** - * @brief Application initialization section - * - */ -static void app_init(void) { - acsInit(&acs); - - /// initialization of CAN resources for sending and - /// receiving. registers two 8-byte uint8_t arrays - /// with the CAN bus. these are shared resources - /// between the ACS and the CAN bus - canRPDOObjectInit(CAN_PDO_1,CAN_ID_DEFAULT,CAN_BUF_SIZE,acs.can_buf.recv); - canTPDOObjectInit(CAN_PDO_1,CAN_ID_DEFAULT,0,0,CAN_BUF_SIZE,acs.can_buf.send); - /// serial output for debugging - sdStart(&SD2, &ser_cfg); -} - -/** - * @brief main appliction section - * - * starts the acs thread and then sleeps - * - */ -static void app_main(void) { - chThdCreateStatic( - wa_acsThread, - sizeof(wa_acsThread), - NORMALPRIO+1, - acsThread, - &acs - ); - - while (true){ - chThdSleepMilliseconds(1000); - } -} - -/** - * @brief main - * - * calls initialization functions - * and then calls app_main() - * - */ -int main(void){ - halInit(); - chSysInit(); - oresat_init(CAN_NODE); - - /// Initialize and start app - app_init(); - app_main(); - - return 0; -} diff --git a/src/archive/app_oresat_acs-1.0/source/README.md b/src/archive/app_oresat_acs-1.0/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_oresat_acs-1.0/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_oresat_acs-1.0/source/acs.c b/src/archive/app_oresat_acs-1.0/source/acs.c deleted file mode 100644 index d7082c20..00000000 --- a/src/archive/app_oresat_acs-1.0/source/acs.c +++ /dev/null @@ -1,429 +0,0 @@ -#include "acs.h" - -event_listener_t el; - -/** - * @brief cleans up on transition - * - * @param[in] acs pointer to the @p ACS object - * @p ACS caonnot be NULL - */ -static void trans_cleanup(ACS *acs){ - switch(acs->cur_state){ - case ST_OFF: - - break; - case ST_INIT: - - break; - case ST_RDY: - - break; - - case ST_RW: - bldcExit(&acs->motor); - break; - - case ST_MTQR: - mtqrExit(&acs->mtqr); - break; - default: - - break; - } -} - -/** - * @brief updates the recv buffer - * - * @note this is a critical section - * - */ -static void update_recv(ACS *acs,int recv_byte){ - switch(recv_byte){ - case ERROR_CODE: - break; - case ACS_STATE: -// *******critical section********** - chSysLock(); - acs->can_buf.send[recv_byte]=acs->cur_state; - chSysUnlock(); -// *******end critical section********** - break; - default: - break; - } -} - -/** - * @brief returns the off state - * - */ -static int state_off(ACS *acs){ - (void)acs; - return ST_OFF; -} - -/** - * @brief returns the init state - * - */ -static int state_init(ACS *acs){ - (void)acs; - return ST_INIT; -} - -/** - * @brief returns the ready state - * - */ -static int state_rdy(ACS *acs){ - trans_cleanup(acs); - return ST_RDY; -} - -/** - * @brief return the reaction wheel state - * - */ -static int state_rw(ACS *acs){ - trans_cleanup(acs); - bldcInit(&acs->motor); - return ST_RW; -} - -/** - * @brief returns the magnetorquer state - * - */ -static int state_mtqr(ACS *acs){ - trans_cleanup(acs); - return ST_MTQR; -} - -/** - * @brief function to start the the reaction wheels - * - * @note this is a critical section - * - */ -static int trap_rw_start(ACS *acs){ - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_RW_START; - chSysUnlock(); - // *******end critical section********** - bldcStart(&acs->motor); - return EXIT_SUCCESS; -} - -/** - * @brief function to stop the reaction wheels - * - * @note this is a critical section - * - */ -static int trap_rw_stop(ACS *acs){ - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_RW_STOP; - chSysUnlock(); - // *******end critical section********** - bldcStop(&acs->motor); - return EXIT_SUCCESS; -} - -/** - * @brief function to start the magnetorquer - * - * @note this is a critical section - * - */ -static int trap_mtqr_start(ACS *acs){ - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_MTQR_START; - chSysUnlock(); - // *******end critical section********** - mtqrStart(&acs->mtqr); - return EXIT_SUCCESS; -} - -/** - * @brief function to stop the magnetorquer - * - * @note this is a critical section - * - */ -static int trap_mtqr_stop(ACS *acs){ - (void)acs; - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_MTQR_STOP; - chSysUnlock(); - // *******end critical section********** - mtqrStop(&acs->mtqr); - return EXIT_SUCCESS; -} - -/** - * @brief function to change the PWM - * duty cycle for the magnetorquer - * - * @note this is a critical section - * - */ -static int trap_mtqr_dc(ACS *acs){ - (void)acs; - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_MTQR_DC; - chSysUnlock(); - // *******end critical section********** - mtqrSetDC((acs->recv[ARG_BYTE+1]<<8) | acs->recv[ARG_BYTE+2]); - return EXIT_SUCCESS; -} - -/** - * @brief function for function for changing the - * polarity of the magnetorquer - * - * @note this is a critical section - * - */ -static int trap_mtqr_dir(ACS *acs){ - (void)acs; - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_TRAP]=EV_MTQR_STOP; - chSysUnlock(); - // *******end critical section********** - mtqrSetDir(acs->recv[ARG_BYTE+1]); - return EXIT_SUCCESS; -} - -/** - * @brief Changes how many steps are added in between each LUT step - * - */ -static int trap_rw_stretch(ACS *acs){ - (void)acs; - /// TODO: have a better data system. - acs->motor.stretch = acs->data; - return EXIT_SUCCESS; -} - -/** - * @brief Closed loop using encoder, or brute forcing with open loop - * - */ -static int trap_rw_control(ACS *acs){ - (void)acs; - /// TODO: have a better data system. - acs->motor.openLoop = (bool) acs->data; - return EXIT_SUCCESS; -} - -/** - * @brief Changes how many steps are skipped in the LUT when going to next step - * - */ -static int trap_rw_skip(ACS *acs){ - (void)acs; - /// TODO: have a better data system. - acs->motor.skip = acs->data; - return EXIT_SUCCESS; -} - -/** - * @brief Changes the scale factor, modifying LUT value by 0-100% - * - */ -static int trap_rw_scale(ACS *acs){ - (void)acs; - /// TODO: have a better data system. - acs->motor.scale = acs->data; - return EXIT_SUCCESS; -} - -/** - * @brief trap function table - * - * this table defines the events allowed - * to be called in states, and the function - * that needs to be called on a successful - * match - */ -const acs_trap trap[] = { - {ST_RW, EV_RW_START, &trap_rw_start}, - {ST_RW, EV_RW_STOP, &trap_rw_stop}, - {ST_RW, EV_RW_STRETCH, &trap_rw_stretch}, - {ST_RW, EV_RW_CONTROL, &trap_rw_control}, - {ST_RW, EV_RW_SKIP, &trap_rw_skip}, - {ST_RW, EV_RW_SCALE, &trap_rw_scale}, - {ST_MTQR, EV_MTQR_START, &trap_mtqr_start}, - {ST_MTQR, EV_MTQR_STOP, &trap_mtqr_stop}, - {ST_MTQR, EV_MTQR_DC, &trap_mtqr_dc}, - {ST_MTQR, EV_MTQR_DIR, &trap_mtqr_dir}, -}; - -/// determines the total number of events -#define EVENT_COUNT (int)(sizeof(trap)/sizeof(acs_trap)) - -/** - * @brief control falls here when a state change - * request is unrecognized - * - * * @note this is a critical section - * - */ -static int fsm_trap(ACS *acs){ - int i,trap_status; - - for(i = 0;i < EVENT_COUNT;++i){ - if(acs->event == trap[i].event){ - if(trap[i].state == ST_ANY || acs->cur_state == trap[i].state){ - trap_status = (trap[i].fn)(acs); - if(trap_status){ - // *******critical section********** - chSysLock(); - acs->can_buf.send[ERROR_CODE]=77; - chSysUnlock(); - chThdSleepMilliseconds(500); - // *******end critical section********** - } - } - } - } - - return acs->cur_state; -} - -/** - * @brief state transition table - * - * this state transistion table defines - * legal transitions and and what function - * is called upon a successful match in - * the table. - */ -const acs_transition trans[] = { - {ST_INIT, EV_RDY, &state_rdy}, - {ST_INIT, EV_OFF, &state_off}, - {ST_RDY, EV_RW, &state_rw}, - {ST_RDY, EV_MTQR, &state_mtqr}, - {ST_RDY, EV_OFF, &state_off}, - {ST_RW, EV_RDY, &state_rdy}, - {ST_MTQR, EV_RDY, &state_rdy}, - {ST_ANY, EV_ANY, &fsm_trap} -}; - -/// TRANS_COUNT define the total number of legal transitions -#define TRANS_COUNT (int)(sizeof(trans)/sizeof(acs_transition)) - -/** - * @brief waits for events on the CAN bus and processes them - * - * @note this is a critical section - * - */ -static acs_event getNextEvent(ACS *acs){ - acs_event event = EV_ANY; - chEvtWaitAny(ALL_EVENTS); -// ******critical section******* - chSysLock(); - for(int i=0;irecv[i]=acs->can_buf.recv[i]; - acs->can_buf.recv[i]=0; - } - chSysUnlock(); -// ******end critical section******* - - switch(acs->recv[MSG_TYPE]){ - case NOP: - break; - case CHG_STATE: - event = acs->recv[ARG_BYTE]; - acs->data = acs->recv[ARG_BYTE+1]; - break; - case CALL_TRAP: - // event = EV_STATUS; - /// TODO: we should seperate the trap from the - /// state changes in the next version - // state command - break; - default: - break; - } - - if(event < EV_ANY || event >= EV_END){ - return (acs_event)acs->cur_state; - } - - return event; -} - -/** - * @brief the ACS state machine - * - * @note this is a critical section - * - */ -static int acs_statemachine(ACS *acs){ - int i; - acs->cur_state = state_init(acs); - update_recv(acs,ACS_STATE); - - while (!chThdShouldTerminateX() && acs->cur_state != ST_OFF) { - acs->event = getNextEvent(acs); - - // *******critical section********** - chSysLock(); - acs->can_buf.send[LAST_EVENT]=acs->event; - chSysUnlock(); - // *******end critical section********** - - for (i = 0;i < TRANS_COUNT;++i) { - if((acs->cur_state == trans[i].state)||(ST_ANY == trans[i].state)){ - if((acs->event == trans[i].event)||(EV_ANY == trans[i].event)){ - acs->cur_state = (trans[i].fn)(acs); - update_recv(acs,ACS_STATE); - } - } - } - chThdSleepMilliseconds(500); -/* - // this stuff is for debugging - chprintf(DEBUG_CHP, "motor stretch: %d\r\n", acs->motor.stretch); - chprintf(DEBUG_CHP, "motor openLoop: %d\r\n", acs->motor.openLoop); - chprintf(DEBUG_CHP, "motor skip: %d\r\n\n", acs->motor.skip); - chprintf(DEBUG_CHP, "motor scale: %d\r\n\n", acs->motor.scale); - chprintf(DEBUG_CHP, "motor samples: %d\r\n\n", acs->motor.samples[0]); -//*/ - } - - return EXIT_SUCCESS; -} - -/** - * @brief general ACS initialization - * - */ -extern int acsInit(ACS *acs){ - (void)acs; - mtqrInit(&acs->mtqr); - return EXIT_SUCCESS; -} - -/** - * @brief ACS thread and thread working area - * - */ -THD_WORKING_AREA(wa_acsThread,WA_ACS_THD_SIZE); -THD_FUNCTION(acsThread,acs){ - chRegSetThreadName("acsThread"); - chEvtRegister(&rpdo_event,&el,0); - - acs_statemachine(acs); -} - diff --git a/src/archive/app_oresat_acs-1.0/source/acs.h b/src/archive/app_oresat_acs-1.0/source/acs.h deleted file mode 100644 index af8b9081..00000000 --- a/src/archive/app_oresat_acs-1.0/source/acs.h +++ /dev/null @@ -1,176 +0,0 @@ -#ifndef _ACS_H_ -#define _ACS_H_ - -#include "ch.h" -#include "hal.h" -#include "bldc.h" -#include "magnetorquer.h" -#include "chprintf.h" -#include "oresat.h" - -/** - * TODO: Thread sizes cause continual problems for managing memory - * if the threads are too small it breaks, if the thread working - * areas are too large then you run out of memory. One solution - * is to move to a mcu with more memory. - */ -#define WA_ACS_THD_SIZE (1<<7) -#define CAN_NODE 0x3F // max 0x7f -#define CAN_BUF_SIZE 8 - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#define EXIT_SUCCESS 0 -#define EXIT_FAILURE 1 - -/** - * @brief can_msg enumeraton - * - * TODO: This is going to change in v2.0 once a protocol - * is decided for communication with the ACS - * - * Byte Name Use - * 0 MSG_TYPE CHG_STATE is the only current implementation - * 1 ARG_BYTE used for passing arguments - * 2 ARG_BYTE1 used for passing arguments - * 3 ARG_BYTE2 used for passing arguments - * 4 unimplemented - * 5 unimplemented - * 6 unimplemented - * 7 unimplemented - * - */ -typedef enum{ - MSG_TYPE=0, - ARG_BYTE, - ARG_BYTE1, - ARG_BYTE2 -}can_msg; - -/** - * @brief enumeration for the recv buffer - * - * TODO: This is going to change in v2.0 once a protocol - * is decided for communication with the ACS - * - * Byte Name Use - * 0 unimplemented - * 1 STATE current state - * 2 LAST_EVENT last event received - * 3 unimplemented - * 4 unimplemented - * 5 unimplemented - * 6 unimplemented - * 7 unimplemented - * - */ -typedef enum{ - ERROR_CODE = 0, - ACS_STATE, - LAST_EVENT, - LAST_TRAP, -}can_recv; - -/** - * @brief enumeration for CAN message types - * - * TODO: This is going to change in v2.0 once a protocol - * is decided for communication with the ACS - * - */ -typedef enum{ - NOP=0, - CHG_STATE, - CALL_TRAP, -}can_msg_type; - -/** - * @brief enumeration for ACS states - * - * TODO: This is going to change in v2.0 to more - * accurately reflect how the ACS will operate - * - */ -typedef enum{ - ST_ANY=-1, - ST_OFF, - ST_INIT, - ST_RDY, - ST_RW, - ST_MTQR -}acs_state; - -/** - * @brief enumeration for all the possible events - * - * TODO: This is going to change in v2.0 to more - * accurately reflect how the ACS will operate - * - * hexidecimal values are passed to the ACS via - * the bus. - */ -typedef enum { - EV_ANY=-1, ///< -1 - EV_OFF, ///< 0 - EV_INIT, ///< 1 - EV_RDY, ///< 2 - EV_RW, ///< 3 - EV_MTQR, ///< 4 - EV_RW_START, ///< 5 - EV_RW_STOP, ///< 6 - EV_RW_STRETCH, ///< 7 - EV_RW_CONTROL, ///< 8 - EV_RW_SKIP, ///< 9 - EV_RW_SCALE, ///< a - EV_MTQR_START, ///< b - EV_MTQR_STOP, ///< c - EV_MTQR_DC, ///< d - EV_MTQR_DIR, ///< e - EV_END /// this must be the last event -}acs_event; - -/** - * @brief can_buffer structure holds the send and recv - * buffers that are registered with the CAN bus - * - */ -typedef struct{ - uint8_t send[CAN_BUF_SIZE]; - uint8_t recv[CAN_BUF_SIZE]; -}can_buffer; - -/** - * @brief ACS structure for maintaining the ACS state - * - * TODO: This structure is likely to change for v2.0 - */ -typedef struct{ - acs_state cur_state; - acs_event event; /// the most recent event - can_buffer can_buf; - bldc motor; - MTQR mtqr; - /// TODO: find a better way to handle it - /// data was a bandaid - uint8_t data; - uint8_t recv[CAN_BUF_SIZE]; -}ACS; - -/** - * @brief structure for manipulating state transistions - * and trap functions - * - */ -typedef struct{ - acs_state state; - acs_event event; - int (*fn)(ACS *acs); -}acs_transition,acs_trap; - -extern int acsInit(ACS *acs); - -extern THD_WORKING_AREA(wa_acsThread,WA_ACS_THD_SIZE); -extern THD_FUNCTION(acsThread,acs); - -#endif diff --git a/src/archive/app_oresat_acs-1.0/source/bldc.c b/src/archive/app_oresat_acs-1.0/source/bldc.c deleted file mode 100644 index 4a1f317e..00000000 --- a/src/archive/app_oresat_acs-1.0/source/bldc.c +++ /dev/null @@ -1,263 +0,0 @@ -#include "bldc.h" -#include "sin_lut.h" - -bldc *motor; - -/** - * @brief Currently not used. - * - * - */ -static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { - (void)adcp; - (void)err; -} - - -/** - * TODO: combine this with a timer to not spam interrupts so much? - * @brief ADC conversion group, used to configure the ADC driver - * Mode: Continuous, 1 sample of 1 channel, SW triggered. - * Channels: A0 - * Slowest sample rate possible, as putting it too high can lock other systems out. - */ -static const ADCConversionGroup adcgrpcfg = { - TRUE, - ADC_GRP_NUM_CHANNELS, - NULL, - adcerrorcallback, - ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */ - ADC_TR(0, 0), /* TR */ - ADC_SMPR_SMP_239P5, /* SMPR */ - ADC_CHSELR_CHSEL0 /* CHSELR */ -}; - -/** - * @brief Translates encoder position into a useable LUT value - * - * Since it takes 6 passes through the LUT to get one physical - * revolution of the motor, we need a way to index a value - * of 0 - 2^14 into a value of 0 - 360, in 6 separate ranges - * - */ -static uint16_t encoderToLut(uint16_t position){ - uint16_t step = 0; - uint8_t chunk = (position * CHUNK_AMOUNT) / ENCODER_MAX; - step = ((position - chunk_low[chunk]) * (STEPS)) / CHUNK_SIZE; - - return step; -} - -/** - * @brief Handles the SPI transaction, getting the position from the encoder - * - */ -THD_WORKING_AREA(wa_spiThread,THREAD_SIZE); -THD_FUNCTION(spiThread,arg){ - (void)arg; - chRegSetThreadName("spiThread"); - - spiStart(&SPID1,&spicfg); // Start driver. - spiAcquireBus(&SPID1); // Gain ownership of bus. - - while (!chThdShouldTerminateX()) { - motor->spi_rxbuf[0] = 0; - spiSelect(&SPID1); // Select slave. - - while(SPID1.state != SPI_READY) {} - spiReceive(&SPID1,1,motor->spi_rxbuf); // Receive 1 frame (16 bits). - spiUnselect(&SPID1); // Unselect slave. - - motor->position = 0x3FFF & motor->spi_rxbuf[0]; - - } - - spiReleaseBus(&SPID1); // Release ownership of bus. - spiStop(&SPID1); // Stop driver. -} - -/** - * @brief Scales the duty ccycle value from LUT 0 - 100% - * - */ -static sinctrl_t scale(sinctrl_t duty_cycle){ - return ((duty_cycle*motor->scale)/100) + ((10000*(motor->scale/2))/100); -} - -/** - * @brief Periodic callback of the PWM driver - * - * At the end of each period, we call this, and go to the next - * step in the LUT, which changes absed off of closed or open - * loop control. Holds the logic for stretching, skipping, and - * repeating, to modify the LUT values on the fly. - * - */ -static void pwmpcb(PWMDriver *pwmp) { - (void)pwmp; - - /// If open loop, ignore encoder feedback. - if(motor->openLoop){ - motor->u += motor->skip; - motor->v += motor->skip; - motor->w += motor->skip; - - motor->u = motor->u % 360; - motor->v = motor->v % 360; - motor->w = motor->w % 360; - - motor->current_sin_u = motor->sinctrl[motor->u]; - motor->current_sin_v = motor->sinctrl[motor->v]; - motor->current_sin_w = motor->sinctrl[motor->w]; - }else{ - if (motor->stretch_count == 0){ - motor->u = encoderToLut(motor->position); - motor->v = (motor->u + motor->phase_shift) % 360; - motor->w = (motor->v + motor->phase_shift) % 360; - motor->current_sin_u = motor->sinctrl[motor->u]; - motor->current_sin_v = motor->sinctrl[motor->v]; - motor->current_sin_w = motor->sinctrl[motor->w]; - motor->next_sin_u = motor->sinctrl[motor->u+1]; - motor->next_sin_v = motor->sinctrl[motor->v+1]; - motor->next_sin_w = motor->sinctrl[motor->w+1]; - - /// Calculate the difference between the current step in the LUT - /// and the next step in the LUT, and break it up - /// into the desired amount of steps in between the two - motor->sin_diff = (motor->current_sin_u > motor->next_sin_u)? - (motor->current_sin_u - motor->next_sin_u) : - (motor->next_sin_u - motor->current_sin_u); - motor->sin_diff = motor->sin_diff / motor->stretch; - motor->stretch_count = motor->stretch; - } - - motor->current_sin_u += motor->sin_diff; - motor->current_sin_v += motor->sin_diff; - motor->current_sin_w += motor->sin_diff; - - motor->stretch_count = motor->stretch_count - 1; - } - - bldcSetDC(PWM_U,motor->current_sin_u); - bldcSetDC(PWM_V,motor->current_sin_v); - bldcSetDC(PWM_W,motor->current_sin_w); -} - -/** - * @brief Pwm driver configuration structure. - * - * PWM_TIMER_FREQ is our timer clock in Hz - * - * PWM_PERIOD period in ticks - * - * Configured with pwmpcb as the periodic callback - * PWM channels 0,1,2 are all active high, with a complementary output - * and no channel callback - * - */ -static PWMConfig pwmRWcfg = { - PWM_TIMER_FREQ, - PWM_PERIOD, - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH|PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, - 0, - 0 -}; - -/** - * @brief Sets up initial values for the BLDC object - * - */ -extern void bldcInit(bldc *pbldc){ - motor = pbldc; - motor->steps = STEPS; - motor->stretch = STRETCH; - motor->stretch_count = 0; - motor->scale = SCALE; - motor->skip = SKIP; - motor->sinctrl = sinctrl360; - motor->count = 0; - motor->position = 0; - motor->phase_shift = motor->steps/3; - motor->u = 0; - motor->v = motor->u + motor->phase_shift; - motor->w = motor->v + motor->phase_shift; - motor->openLoop = true; - motor->started = FALSE; - - adcStart(&ADCD1, NULL); - adcStartConversion(&ADCD1, &adcgrpcfg, motor->samples, ADC_GRP_BUF_DEPTH); - - motor->p_spi_thread=chThdCreateStatic( - wa_spiThread, - sizeof(wa_spiThread), - NORMALPRIO, - spiThread, - NULL - ); -} - -/** - * @brief Enables the three PWM channels, starting to go through the LUT - * - */ -extern void bldcStart(bldc *pbldc){ - if(pbldc->started){ - return; - } - pwmStart(&PWMD1,&pwmRWcfg); - pwmEnablePeriodicNotification(&PWMD1); - - pwmEnableChannel(&PWMD1,PWM_U,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,motor->u)); - pwmEnableChannel(&PWMD1,PWM_V,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,motor->v)); - pwmEnableChannel(&PWMD1,PWM_W,PWM_PERCENTAGE_TO_WIDTH(&PWMD1,motor->w)); - pbldc->started = TRUE; -} - -/** - * @brief Stops BLDC control - * - */ -extern void bldcStop(bldc *pbldc){ - if(!pbldc->started){ - return; - } - pwmDisableChannel(&PWMD1,PWM_U); - pwmDisableChannel(&PWMD1,PWM_V); - pwmDisableChannel(&PWMD1,PWM_W); - pwmDisablePeriodicNotification(&PWMD1); - pwmStop(&PWMD1); - pbldc->started = FALSE; -} - -/** - * @brief Changes duty cycle for a given channel - * - */ -extern void bldcSetDC(uint8_t channel,uint16_t dc){ - pwmEnableChannelI( - &PWMD1, - channel, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,scale(dc)) - ); -} - -/** - * @ brief Tear down drivers in a sane way. - * - */ -extern void bldcExit(bldc *pbldc){ - if(pbldc->started){ - bldcStop(pbldc); - } - adcStopConversion(&ADCD1); - adcStop(&ADCD1); - chThdTerminate(motor->p_spi_thread); - chThdWait(motor->p_spi_thread); -} diff --git a/src/archive/app_oresat_acs-1.0/source/bldc.h b/src/archive/app_oresat_acs-1.0/source/bldc.h deleted file mode 100644 index 448d5805..00000000 --- a/src/archive/app_oresat_acs-1.0/source/bldc.h +++ /dev/null @@ -1,167 +0,0 @@ -#ifndef _BLDC_H_ -#define _BLDC_H_ - -#include "ch.h" -#include "hal.h" - -#include - -/// TODO: openloop is going away -#define OPENLOOP /// open loop control (oxymoron) - -//#define THREAD_SIZE (1<<7) -/// TODO: had to reduce this to compile with new ADC code -/// We should figure out what an actual good value is -#define THREAD_SIZE (96) - -/// serial debugging -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - - -/** - * TODO: the definitions of STEP, STRETCH, and SKIP - * evolved over the course of various experiments. These - * will completely change in v2.0. Below is their intended and - * eventual meanings. - * - * STEPS: the number of discrete steps in the LUT - * - * STRETCH: How many periods the current LUT value is repeated - * - * SKIP: How many steps are skipped in the LUT to get the next value - * - * SMOOTH: Smoothing out the transition between LUT values by increasing the amount of steps in between - * - * SCALE: Duty cycle scaling factor from 0-100 % - * - */ -#define SCALE 100 -#define STEPS 360 -#define STRETCH 1 -#define SKIP 1 - -/// encoder has 14 bits of precision -#define ENCODER_MAX 1<<14 -/// chunk amount is the number of times through -/// the LUT for 1 revolution of the reaction wheel -#define CHUNK_AMOUNT 6 -/// chunk size is the number -#define CHUNK_SIZE 2730 - -#define PWM_TIMER_FREQ 48e6 /// Hz -#define PWM_FREQ 15e3 /// periods per sec -#define PWM_PERIOD PWM_TIMER_FREQ/PWM_FREQ - -/// PWM signals -#define PWM_U 0U -#define PWM_V 1U -#define PWM_W 2U - -#define ADC_GRP_NUM_CHANNELS 1 -#define ADC_GRP_BUF_DEPTH 8 - -#define sinctrl_t uint16_t - -/** - * @brief The structure that defines and characterizes - * a motor and how it's being control - * - * steps: Steps in the LUT - * - * stretch: How many steps are added in between LUT steps - * - * skip: How many steps are skipped in the LUT - * - * u, v, and w: The three sin signals, that traverse through the LUT - * current_sin_u,v,w and next_sin_u,v,w: Used in calculation of values for stretch - * - * sin_diff: Difference in LUT steps for stretch - * - * position: Position from encode, a value of 0 - 2^14 - * - * openLoop: Controls whether encoder feedback is used - * - * sinctrl: The LUT - * - * spi_rxbuff: Where the encoder position is after SPI transmission - * - * p_spi_thread: Spi thread for the encoder feedback - * - * samples: Samples from the ADC. - * - */ -typedef struct{ - uint16_t count, /// period counter - scale, /// scales the duty cycle - steps, /// number of steps in lut - stretch, - skip; - sinctrl_t u,v,w,/// signals - phase_shift; /// should be by 120 degrees - uint16_t current_sin_u, next_sin_u, - current_sin_v, next_sin_v, - current_sin_w, next_sin_w; - uint8_t stretch_count; - uint8_t sin_diff; - uint16_t position; // motor position from encoder - bool openLoop; - sinctrl_t const *sinctrl; // pointer to the sin lut - uint16_t spi_rxbuf[2]; // receive buffer - thread_t *p_spi_thread; - adcsample_t samples[ADC_GRP_NUM_CHANNELS * ADC_GRP_BUF_DEPTH]; // ADC conversion storage array - int started; -} bldc; - -/** - * @brief The low value used to break up the encoder value into regions - * - * Allows us to translate the encoder 0 - 2^14 into 6 discrete chunks - * of 0-360 for use in the LUT. - * - */ -static const uint16_t chunk_low[6] = { - 0 * CHUNK_SIZE, - 1 * CHUNK_SIZE, - 2 * CHUNK_SIZE, - 3 * CHUNK_SIZE, - 4 * CHUNK_SIZE, - 5 * CHUNK_SIZE -}; - - -/** - * @brief Control structure used to configure the SPI driver - * - * GPIOA_SPI1_NSS is the pin used to initially select the SPI slave. - * The mask for SPI Control Register 1 sets the frequency of data transfers - * and sets the clock polarity. - * The mask for SPI control Register 2 sets the size of the transfer buffer, 16 bits. - * - */ -static const SPIConfig spicfg = { - false, // Not using circular buffer. - NULL, // Not using operation complete callback. - GPIOA, // Chip select line. - GPIOA_SPI1_NSS, // Chip select port. - SPI_CR1_BR_0|SPI_CR1_BR_1|SPI_CR1_BR_2|SPI_CR1_CPHA, // SPI Control Register 1 mask. - SPI_CR2_DS_0|SPI_CR2_DS_1|SPI_CR2_DS_2|SPI_CR2_DS_3, // SPI Control Register 2 mask. -}; - -extern THD_WORKING_AREA(wa_spiThread,THREAD_SIZE); -/// Prototype for spi thread function. -extern THD_FUNCTION(spiThread,arg); - -/// Function prototype with no return type. Takes bldc type as paramater. -extern void bldcInit(bldc *pbldc); -/// Function prototype with no return type. Takes bldc type as paramater. -extern void bldcStart(bldc *pbldc); -/// Function prototype with no return type. Takes bldc type as paramater. -extern void bldcStop(bldc *pbldc); -/// Function prototype with no return type. Takes 8 bit unsigned integer and a -/// 16 bit unsigned integer as argument. -extern void bldcSetDC(uint8_t channel,uint16_t dc); -/// Function prototype with no return type. Takes bldc type as paramater. -extern void bldcExit(bldc *pbldc); - -#endif diff --git a/src/archive/app_oresat_acs-1.0/source/magnetorquer.c b/src/archive/app_oresat_acs-1.0/source/magnetorquer.c deleted file mode 100644 index 90e8af41..00000000 --- a/src/archive/app_oresat_acs-1.0/source/magnetorquer.c +++ /dev/null @@ -1,98 +0,0 @@ -#include "magnetorquer.h" - -/** - * @brief Magnetorquer initialization function. - * - * This function will initialize the driver state to off. - * - */ -extern void mtqrInit(MTQR *mtqr){ - (void)mtqr; - mtqr->started = FALSE; // Initializing state of magnetorquer driver. - palClearPad(GPIOB,ENABLE); // Initializing motor driver state to off. -} - -/** - * @brief Magnetorquer start function. - * - * This function will start the PWM driver and enable - * the STSPIN250 motor driver while providing a - * starting duty cycle. At this point, the state of - * the magnetorquer will be set to true to indicate on - * state. - * - */ -extern void mtqrStart(MTQR *mtqr){ - if(mtqr->started){ // Checking if state is already on. - return; - } - pwmStart(&PWMD1,&pwm_MTQRcfg); // Starting pwm driver. - mtqrSetDC(MTQR_STARTING_DC); // Setting duty cycle of output. - palSetPad(GPIOB,ENABLE); // Turning on motor driver. - mtqr->started = TRUE; // Setting to on state. -} - -/** - * @brief Magnetorquer stop function. - * - * This function will disable the active - * PWM driver and disable the STSPIN250 motor - * driver. - * - */ -extern void mtqrStop(MTQR *mtqr){ - if(!mtqr->started){ // Checking if state is already off. - return; - } - pwmDisableChannel(&PWMD1,PWM_CH_MTQR); // Disabling channel output. - palClearPad(GPIOB,ENABLE); // Shutting off STSPIN250 driver. - pwmStop(&PWMD1); // Stopping PWM driver. - mtqr->started = FALSE; // Changing state to off. -} - -/** - * @brief Magnetorquer set duty cycle function. - * - * This function takes a 16 bit value as parameter and - * sets the duty cycle of the magnetorquer driver using the - * paramater. - * - */ -extern void mtqrSetDC(uint16_t dc){ - pwmEnableChannel( // Setting duty cycle output using paramater. - &PWMD1, - PWM_CH_MTQR, - PWM_PERCENTAGE_TO_WIDTH(&PWMD1,dc) - ); -} - -/** - * @brief Magnetorquer set direction function. - * - * This function sets the phase pin for the STSPIN250 - * motor driver. The phase is set based on the value - * of the paramater given to the function. - * - */ -extern void mtqrSetDir(uint8_t dc){ - if(dc==FORWARD){ // Set phase selection pin based on requested direction. - palClearPad(GPIOA,PH); - }else if(dc==REVERSE){ - palSetPad(GPIOA,PH); - } -} - -/** - * @brief Magnetorquer exit function. - * - * Function to initialize shutdown of driver. - * - */ -extern void mtqrExit(MTQR *mtqr){ - if(!mtqr->started){ // Checking if magnetorquer state is off. - return; - } - mtqrStop(mtqr); // If the state isn't already off, shut down the driver. -} - - diff --git a/src/archive/app_oresat_acs-1.0/source/magnetorquer.h b/src/archive/app_oresat_acs-1.0/source/magnetorquer.h deleted file mode 100644 index 8d7228a7..00000000 --- a/src/archive/app_oresat_acs-1.0/source/magnetorquer.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef _MAGNETORQUER_H_ -#define _MAGNETORQUER_H_ - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#define MTQR_PWM_TIMER_FREQ 2e6 /// PWM Timer frequency -#define MTQR_PWM_FREQ 2e3 /// periods per second - -#define FORWARD 0 -#define REVERSE 1 - -#define MTQR_PWM_PERIOD MTQR_PWM_TIMER_FREQ/MTQR_PWM_FREQ - -#define PWM_CH_MTQR 0 /// pwm channel -#define MTQR_STARTING_DC 5000u /// starting duty cycle -#define PH 9u /// Phase (motor direction) -#define ENABLE GPIOB_EN_MAG /// Chip enable - -#define EXIT_SUCCESS 0 -#define EXIT_FAILURE 1 - -/** - * @brief PWMConfig structure for the magnetorquer - * - */ -static const PWMConfig pwm_MTQRcfg = { - MTQR_PWM_TIMER_FREQ, /// Frequency - MTQR_PWM_PERIOD, /// period duration - NULL, /// Callback - { /// Channels - {PWM_OUTPUT_ACTIVE_HIGH,NULL}, - {PWM_OUTPUT_DISABLED,NULL}, - {PWM_OUTPUT_DISABLED,NULL}, - {PWM_OUTPUT_DISABLED,NULL} - }, - 0, - 0, - 0 -}; - -/** - * @brief MTQR structure for keeping state - * TODO: this structure is not being used effectively - * it may or may not be a good design choice - * - */ -typedef struct{ - uint8_t direction; - int started; - uint16_t pwm_dc; /// duty cycle -}MTQR; - -extern void mtqrInit(MTQR *mtqr); -extern void mtqrStart(MTQR *mtqr); -extern void mtqrStop(MTQR *mtqr); -extern void mtqrSetDC(uint16_t dc); -extern void mtqrSetDir(uint8_t dc); -extern void mtqrExit(MTQR *mtqr); - -#endif diff --git a/src/archive/app_oresat_acs-1.0/source/saddle_lut.h b/src/archive/app_oresat_acs-1.0/source/saddle_lut.h deleted file mode 100644 index d9c0e6b8..00000000 --- a/src/archive/app_oresat_acs-1.0/source/saddle_lut.h +++ /dev/null @@ -1,19 +0,0 @@ - -// https://www.nxp.com/docs/en/application-note/AN4869.pdf -const uint8_t SinusoidalWaveTable[384]={ -127,131,135,138,142,145,149,152,155,159,162,165,168,171,174,177,180,183,186,189,192,194,197,200, -202,205,207,210, 212,214,217,219,221,223,225,227,229,231,232,234,236,237,239,240,242,243,244,245, -247,248,249,250,250,251,252,253,253,254,254,255,255,255,255,255,255,255,255,255,255,255,254,254, -253,253,252,252,251,250,249,248,247,246,245,244,242,241,240,238,237,235,233,232,230,228,226,224, -222,222,225,226,228,230,232,234,235,237,238,240,241,243,244,245,246,247,248,249,250,251,252,252, -253,254,254,254,255,255,255,255,255,255,255,255,255,255,254,254,254,253,252,252,251,250,249,248, -247,246,245,244,243,241,240,238,237,235,234,232,230,228,227,225,223,220,218,216,214,212,209,207, -204,202,199,197,194,191,188,185,183,180,177,174,171,167,164,161,158,154,151,148,144,141,137,134, -130,127,123,119,116,112,108,104,101, 97, 93, 89, 85, 81, 77, 73, 69, 65, 61, 57, 53, 49, 45, 41, -36, 32, 28, 24, 20, 16, 12, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 6, 10, 15, 19, 23, 27, 31, -35, 39, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 99,103,107,111,115,118,121,124 diff --git a/src/archive/app_oresat_acs-1.0/source/sin_lut.h b/src/archive/app_oresat_acs-1.0/source/sin_lut.h deleted file mode 100644 index cf888753..00000000 --- a/src/archive/app_oresat_acs-1.0/source/sin_lut.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef _ACS_LUT_H_ -#define _ACS_LUT_H_ - -#include "acs.h" - -const sinctrl_t sinctrl360[360] = { - 5000,5087,5174,5262,5349,5436,5523,5609, - 5696,5782,5868,5954,6040,6125,6210,6294, - 6378,6462,6545,6628,6710,6792,6873,6954, - 7034,7113,7192,7270,7347,7424,7500,7575, - 7650,7723,7796,7868,7939,8009,8078,8147, - 8214,8280,8346,8410,8473,8536,8597,8657, - 8716,8774,8830,8886,8940,8993,9045,9096, - 9145,9193,9240,9286,9330,9373,9415,9455, - 9494,9532,9568,9603,9636,9668,9698,9728, - 9755,9782,9806,9830,9851,9872,9891,9908, - 9924,9938,9951,9963,9973,9981,9988,9993, - 9997,9999,10000,9999,9997,9993,9988,9981, - 9973,9963,9951,9938,9924,9908,9891,9872, - 9851,9830,9806,9782,9755,9728,9698,9668, - 9636,9603,9568,9532,9494,9455,9415,9373, - 9330,9286,9240,9193,9145,9096,9045,8993, - 8940,8886,8830,8774,8716,8657,8597,8536, - 8473,8410,8346,8280,8214,8147,8078,8009, - 7939,7868,7796,7723,7650,7575,7500,7424, - 7347,7270,7192,7113,7034,6954,6873,6792, - 6710,6628,6545,6462,6378,6294,6210,6125, - 6040,5954,5868,5782,5696,5609,5523,5436, - 5349,5262,5174,5087,5000,4913,4826,4738, - 4651,4564,4477,4391,4304,4218,4132,4046, - 3960,3875,3790,3706,3622,3538,3455,3372, - 3290,3208,3127,3046,2966,2887,2808,2730, - 2653,2576,2500,2425,2350,2277,2204,2132, - 2061,1991,1922,1853,1786,1720,1654,1590, - 1527,1464,1403,1343,1284,1226,1170,1114, - 1060,1007,955,904,855,807,760,714, - 670,627,585,545,506,468,432,397, - 364,332,302,272,245,218,194,170, - 149,128,109,92,76,62,49,37, - 27,19,12,7,3,1,0,1, - 3,7,12,19,27,37,49,62, - 76,92,109,128,149,170,194,218, - 245,272,302,332,364,397,432,468, - 506,545,585,627,670,714,760,807, - 855,904,955,1007,1060,1114,1170,1226, - 1284,1343,1403,1464,1527,1590,1654,1720, - 1786,1853,1922,1991,2061,2132,2204,2277, - 2350,2425,2500,2576,2653,2730,2808,2887, - 2966,3046,3127,3208,3290,3372,3455,3538, - 3622,3706,3790,3875,3960,4046,4132,4218, - 4304,4391,4477,4564,4651,4738,4826,4913 -}; - -#endif diff --git a/src/archive/app_oresat_acs-2.0/Makefile b/src/archive/app_oresat_acs-2.0/Makefile deleted file mode 100644 index 6b12dc59..00000000 --- a/src/archive/app_oresat_acs-2.0/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_oresat_acs - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_F446RE - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_oresat_acs-2.0/README.md b/src/archive/app_oresat_acs-2.0/README.md deleted file mode 100644 index 55f3c8e2..00000000 --- a/src/archive/app_oresat_acs-2.0/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` diff --git a/src/archive/app_oresat_acs-2.0/cfg/chconf.h b/src/archive/app_oresat_acs-2.0/cfg/chconf.h deleted file mode 100644 index 8e12427c..00000000 --- a/src/archive/app_oresat_acs-2.0/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-2.0/cfg/halconf.h b/src/archive/app_oresat_acs-2.0/cfg/halconf.h deleted file mode 100644 index 44d5840c..00000000 --- a/src/archive/app_oresat_acs-2.0/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_oresat_acs-2.0/cfg/mcuconf.h b/src/archive/app_oresat_acs-2.0/cfg/mcuconf.h deleted file mode 100644 index e7f13ef3..00000000 --- a/src/archive/app_oresat_acs-2.0/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_oresat_acs-2.0/main.c b/src/archive/app_oresat_acs-2.0/main.c deleted file mode 100644 index a9644a74..00000000 --- a/src/archive/app_oresat_acs-2.0/main.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -//=== Project header files -#include "oresat.h" - -#include "thread1.h" - -//=== Serial configuration -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -static void app_init(void) { - //=== App initialization - - // Start up debug output - sdStart(&SD2, &ser_cfg); - -} - -static void main_app(void) { - //=== Start application threads - - //Example thread creation - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Begin main loop - */ - while (true) - { - chThdSleepMilliseconds(1000); - } -} - -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - oresat_init(0); - - // Initialize and start app - app_init(); - main_app(); - - return 0; -} diff --git a/src/archive/app_oresat_acs-2.0/source/README.md b/src/archive/app_oresat_acs-2.0/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_oresat_acs-2.0/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_oresat_acs-2.0/source/thread1.c b/src/archive/app_oresat_acs-2.0/source/thread1.c deleted file mode 100644 index 031e4904..00000000 --- a/src/archive/app_oresat_acs-2.0/source/thread1.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "thread1.h" - -// Example blinker thread -THD_WORKING_AREA(waThread1, 128); -THD_FUNCTION(Thread1, arg) { - - (void)arg; - chRegSetThreadName("thread1"); - - while (!chThdShouldTerminateX()) { - palClearLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - palSetLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - } -} diff --git a/src/archive/app_oresat_acs-2.0/source/thread1.h b/src/archive/app_oresat_acs-2.0/source/thread1.h deleted file mode 100644 index 32f225d5..00000000 --- a/src/archive/app_oresat_acs-2.0/source/thread1.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _THREAD1_H_ -#define _THREAD1_H_ - -#include "ch.h" -#include "hal.h" - -// Example blinker thread prototypes -extern THD_WORKING_AREA(waThread1, 128); -extern THD_FUNCTION(Thread1, arg); - -#endif diff --git a/src/archive/app_protodemo/Makefile b/src/archive/app_protodemo/Makefile deleted file mode 100644 index d5ff8b73..00000000 --- a/src/archive/app_protodemo/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x200 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x200 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_protodemo - -# Target settings. -MCU = cortex-m0 -BOARD = ST_NUCLEO32_F042K6 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F042x6.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_protodemo/README.md b/src/archive/app_protodemo/README.md deleted file mode 100644 index 55f3c8e2..00000000 --- a/src/archive/app_protodemo/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# app_template - -This is the template app for new applications. - -To create a new app, simply copy the app_template directory and name it whatever you like. - -``` -cp -R app_template app_ -``` - -If building for a specific board, update the `BOARD =` line to the board -defined in the `boards` directory - -Then, open the Makefile and edit the line `PROJECT =` to whatever name you chose: -``` -PROJECT = app_ -``` diff --git a/src/archive/app_protodemo/cfg/chconf.h b/src/archive/app_protodemo/cfg/chconf.h deleted file mode 100644 index 6f3b51a9..00000000 --- a/src/archive/app_protodemo/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_protodemo/cfg/halconf.h b/src/archive/app_protodemo/cfg/halconf.h deleted file mode 100644 index 534c4bb6..00000000 --- a/src/archive/app_protodemo/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_protodemo/cfg/mcuconf.h b/src/archive/app_protodemo/cfg/mcuconf.h deleted file mode 100644 index 38b66f58..00000000 --- a/src/archive/app_protodemo/cfg/mcuconf.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 3 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_SYSCLK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_USART1SW STM32_USART1SW_HSI -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 -#define STM32_IRQ_USART1_PRIORITY 3 -#define STM32_IRQ_USART2_PRIORITY 3 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_protodemo/main.c b/src/archive/app_protodemo/main.c deleted file mode 100644 index cea09826..00000000 --- a/src/archive/app_protodemo/main.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -//=== Project header files -#include "oresat.h" - -//=== Serial configuration -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -static void app_init(void) { - //=== App initialization - - // Start up debug output - sdStart(&SD2, &ser_cfg); - -} - -static void main_app(void) { - //=== Start application threads - - - /* - * Begin main loop - */ - while (true) - { - chprintf((BaseSequentialStream*)&SD2, "OreSat Protocard V1.1!\r\n"); - palClearLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - palSetLine(LINE_LED_GREEN); - chThdSleepMilliseconds(500); - } -} - -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - oresat_init(0); - - // Initialize and start app - app_init(); - main_app(); - - return 0; -} diff --git a/src/archive/app_protodemo/source/README.md b/src/archive/app_protodemo/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_protodemo/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_radio/Makefile b/src/archive/app_radio/Makefile deleted file mode 100644 index 605c95e7..00000000 --- a/src/archive/app_radio/Makefile +++ /dev/null @@ -1,206 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = hard -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_radio - -# Target settings. -MCU = cortex-m4 -BOARD = ORESAT_C3_V3 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -#include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk -include $(CHIBIOS)/os/various/shell/shell.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DSHELL_CONFIG_FILE -DAX5043_SHARED_SPI - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_radio/README.md b/src/archive/app_radio/README.md deleted file mode 100644 index fbb1fadd..00000000 --- a/src/archive/app_radio/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# app_sx1236_ax5043_HDLC_FEC_tx - -This is used to transmit sax5043 radio packets signal. -This creates a instruction packet at 435.5 MhZ in a fixed interval. This code simulates ground. This pairs with " app_sx1236_FulDuplex_oresat " which receives the instruction and responds with data. the sent and received packet are shown in serial terminal. - diff --git a/src/archive/app_radio/cfg/CO_driver_custom.h b/src/archive/app_radio/cfg/CO_driver_custom.h deleted file mode 100644 index d2edd33e..00000000 --- a/src/archive/app_radio/cfg/CO_driver_custom.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* TODO: These should be in CO_OD.h, but libedssharp does not support this yet */ -#define CO_NO_GFC 0 -#define CO_NO_SRDO 0 - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_FLAG_CALLBACK_PRE | \ - CO_CONFIG_FLAG_TIMERNEXT | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL) - -#define CO_CONFIG_GTW (CO_CONFIG_GTW_ASCII | \ - CO_CONFIG_GTW_ASCII_SDO | \ - CO_CONFIG_GTW_ASCII_NMT | \ - CO_CONFIG_GTW_ASCII_LOG | \ - CO_CONFIG_GTW_ASCII_ERROR_DESC | \ - CO_CONFIG_GTW_ASCII_PRINT_HELP) -#define CO_CONFIG_GTW_BLOCK_DL_LOOP 1 -#define CO_CONFIG_GTWA_COMM_BUF_SIZE 2000 -#define CO_CONFIG_GTWA_LOG_BUF_SIZE 2000 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/archive/app_radio/cfg/chconf.h b/src/archive/app_radio/cfg/chconf.h deleted file mode 100644 index 53dfa662..00000000 --- a/src/archive/app_radio/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_radio/cfg/halconf.h b/src/archive/app_radio/cfg/halconf.h deleted file mode 100644 index 8177d35c..00000000 --- a/src/archive/app_radio/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_LINE -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_radio/cfg/mcuconf.h b/src/archive/app_radio/cfg/mcuconf.h deleted file mode 100644 index 1e200710..00000000 --- a/src/archive/app_radio/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 16 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 8 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 8 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSE -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_radio/cfg/shellconf.h b/src/archive/app_radio/cfg/shellconf.h deleted file mode 100644 index c31de933..00000000 --- a/src/archive/app_radio/cfg/shellconf.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef SHELLCONF_H -#define SHELLCONF_H - -#define SHELL_MAX_ARGUMENTS 10 -#define SHELL_USE_HISTORY TRUE -#define SHELL_USE_ESC_SEQ TRUE -#define SHELL_PROMPT_STR "OreSat> " - -#endif diff --git a/src/archive/app_radio/main.c b/src/archive/app_radio/main.c deleted file mode 100644 index f6bd0792..00000000 --- a/src/archive/app_radio/main.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*************************************************** - * Modification Log - * 04/15/2018 Malay Das Initial Code. - * 08/09/2019 Malay Das Initial Driver. - * 08/23/2019 Malay Das Add mailbox functionality. - ***************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "shell.h" - -#include "chprintf.h" -#include "ax5043.h" - - -//#include "adf7030.h" - -#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) - -ax5043_address_t remoteaddr = { - { 0x33, 0x34, 0x00, 0x00} -}; -ax5043_address_mask_t localaddr = { - { 0x33, 0x34, 0x00, 0x00}, - { 0xFF, 0x00, 0x00, 0x00} // make it { 0x00, 0x00, 0x00, 0x00} to receive AX25 packets -}; - -ax5043_regval_t reg_values[] = { - {AX5043_REG_MODULATION, 0x08}, - {AX5043_REG_ENCODING, 0x07}, - {AX5043_REG_FRAMING, 0x14}, - //{AX5043_REG_FEC, 0x13}, - {AX5043_REG_CRCINIT3, 0x00}, - {AX5043_REG_CRCINIT2, 0x00}, - {AX5043_REG_CRCINIT1, 0xFF}, - {AX5043_REG_CRCINIT0, 0xFF}, - {AX5043_REG_PINFUNCSYSCLK, 0x01}, - {AX5043_REG_PINFUNCDCLK, 0x01}, - {AX5043_REG_PINFUNCDATA, 0x01}, - {AX5043_REG_PINFUNCANTSEL, 0x01}, - {AX5043_REG_PINFUNCPWRAMP, 0x07}, - {AX5043_REG_WAKEUPXOEARLY, 0x01}, - {AX5043_REG_IFFREQ1, 0x02}, - {AX5043_REG_IFFREQ0, 0x0C}, - {AX5043_REG_DECIMATION, 0x14}, - {AX5043_REG_RXDATARATE2, 0x00}, - {AX5043_REG_RXDATARATE1, 0x3E}, - {AX5043_REG_RXDATARATE0, 0x80}, - {AX5043_REG_MAXDROFFSET2, 0x00}, - {AX5043_REG_MAXDROFFSET1, 0x00}, - {AX5043_REG_MAXDROFFSET0, 0x00}, - {AX5043_REG_MAXRFOFFSET2, 0x80}, - {AX5043_REG_MAXRFOFFSET1, 0x01}, - {AX5043_REG_MAXRFOFFSET0, 0x2F}, - {AX5043_REG_FSKDMAX1, 0x00}, - {AX5043_REG_FSKDMAX0, 0xA6}, - {AX5043_REG_FSKDMIN1, 0xFF}, - {AX5043_REG_FSKDMIN0, 0x5A}, - {AX5043_REG_AMPLFILTER, 0x00}, - {AX5043_REG_RXPARAMSETS, 0xF4}, - {AX5043_REG_AGCGAIN0, 0xC5}, - {AX5043_REG_AGCTARGET0, 0x84}, - {AX5043_REG_TIMEGAIN0, 0xF8}, - {AX5043_REG_DRGAIN0, 0xF2}, - {AX5043_REG_PHASEGAIN0, 0xC3}, - {AX5043_REG_FREQUENCYGAINA0,0x0F}, - {AX5043_REG_FREQUENCYGAINB0,0x1F}, - {AX5043_REG_FREQUENCYGAINC0,0x0A}, - {AX5043_REG_FREQUENCYGAIND0,0x0A}, - {AX5043_REG_AMPLITUDEGAIN0, 0x06}, - {AX5043_REG_FREQDEV10, 0x00}, - {AX5043_REG_FREQDEV00, 0x00}, - {AX5043_REG_BBOFFSRES0, 0x00}, - {AX5043_REG_AGCGAIN1, 0xC5}, - {AX5043_REG_AGCTARGET1, 0x84}, - {AX5043_REG_AGCAHYST1, 0x00}, - {AX5043_REG_AGCMINMAX1, 0x00}, - {AX5043_REG_TIMEGAIN1, 0xF6}, - {AX5043_REG_DRGAIN1, 0xF1}, - {AX5043_REG_PHASEGAIN1, 0xC3}, - {AX5043_REG_FREQUENCYGAINA1,0x0F}, - {AX5043_REG_FREQUENCYGAINB1,0x1F}, - {AX5043_REG_FREQUENCYGAINC1,0x0A}, - {AX5043_REG_FREQUENCYGAIND1,0x0A}, - {AX5043_REG_AMPLITUDEGAIN1, 0x06}, - {AX5043_REG_FREQDEV11, 0x00}, - {AX5043_REG_FREQDEV01, 0x25}, - {AX5043_REG_FOURFSK1, 0x16}, - {AX5043_REG_BBOFFSRES1, 0x00}, - {AX5043_REG_AGCGAIN3, 0xFF}, - {AX5043_REG_AGCTARGET3, 0x84}, - {AX5043_REG_AGCAHYST3, 0x00}, - {AX5043_REG_AGCMINMAX3, 0x00}, - {AX5043_REG_TIMEGAIN3, 0xF5}, - {AX5043_REG_DRGAIN3, 0xF0}, - {AX5043_REG_PHASEGAIN3, 0xC3}, - {AX5043_REG_FREQUENCYGAINA3,0x0F}, - {AX5043_REG_FREQUENCYGAINB3,0x1F}, - {AX5043_REG_FREQUENCYGAINC3,0x0D}, - {AX5043_REG_FREQUENCYGAIND3,0x0D}, - {AX5043_REG_AMPLITUDEGAIN3, 0x06}, - {AX5043_REG_FREQDEV13, 0x00}, - {AX5043_REG_FREQDEV03, 0x25}, - {AX5043_REG_FOURFSK3, 0x16}, - {AX5043_REG_BBOFFSRES3, 0x00}, - {AX5043_REG_MODCFGF, 0x02}, - {AX5043_REG_FSKDEV2, 0x00}, - {AX5043_REG_FSKDEV1, 0x04}, - {AX5043_REG_FSKDEV0, 0x5E}, - {AX5043_REG_MODCFGA, 0x05}, - {AX5043_REG_TXRATE2, 0x00}, - {AX5043_REG_TXRATE1, 0x0D}, - {AX5043_REG_TXRATE0, 0x1B}, - {AX5043_REG_TXPWRCOEFFB1, 0x07}, - {AX5043_REG_TXPWRCOEFFB0, 0x00}, - {AX5043_REG_PLLVCOI, 0x99}, - {AX5043_REG_PLLRNGCLK, 0x05}, - {AX5043_REG_BBTUNE, 0x0F}, - {AX5043_REG_BBOFFSCAP, 0x77}, - {AX5043_REG_PKTADDRCFG, 0x00}, - {AX5043_REG_PKTLENCFG, 0x00}, - {AX5043_REG_PKTLENOFFSET, 0x15}, - {AX5043_REG_PKTMAXLEN, 0xF0}, - {AX5043_REG_MATCH0PAT3, 0xAA}, - {AX5043_REG_MATCH0PAT2, 0xCC}, - {AX5043_REG_MATCH0PAT1, 0xAA}, - {AX5043_REG_MATCH0PAT0, 0xCC}, - //{AX5043_REG_MATCH0LEN, 0x9F}, - //{AX5043_REG_MATCH0MAX, 0x1F}, - {AX5043_REG_MATCH1PAT1, 0x55}, - {AX5043_REG_MATCH1PAT0, 0x55}, - {AX5043_REG_MATCH1LEN, 0x0A}, - {AX5043_REG_MATCH1MAX, 0x0A}, - {AX5043_REG_TMGTXBOOST, 0x5B}, - {AX5043_REG_TMGTXSETTLE, 0x3E}, - {AX5043_REG_TMGRXBOOST, 0x5B}, - {AX5043_REG_TMGRXSETTLE, 0x3E}, - {AX5043_REG_TMGRXOFFSACQ, 0x00}, - {AX5043_REG_TMGRXCOARSEAGC, 0x9C}, - {AX5043_REG_TMGRXRSSI, 0x03}, - {AX5043_REG_TMGRXPREAMBLE2, 0x17}, - {AX5043_REG_RSSIABSTHR, 0xE3}, - {AX5043_REG_BGNDRSSITHR, 0x00}, - {AX5043_REG_PKTCHUNKSIZE, 0x0D}, - {AX5043_REG_PKTACCEPTFLAGS, 0x39}, //original 20, 3f=accept all errors - {AX5043_REG_DACVALUE1, 0x00}, - {AX5043_REG_DACVALUE0, 0x00}, - {AX5043_REG_DACCONFIG, 0x00}, - {AX5043_REG_REF, 0x03}, - {AX5043_REG_XTALOSC, 0x04}, - {AX5043_REG_XTALAMPL, 0x00}, - {AX5043_REG_0xF1C, 0x07}, - {AX5043_REG_0xF21, 0x68}, - {AX5043_REG_0xF22, 0XFF}, - {AX5043_REG_0xF23, 0x84}, - {AX5043_REG_0xF26, 0x98}, - {AX5043_REG_0xF34, 0x28}, - {AX5043_REG_0xF35, 0x11}, - {AX5043_REG_0xF44, 0x25}, - {AX5043_REG_PINFUNCIRQ, 0x03}, - {AX5043_REG_PKTSTOREFLAGS, 0x14}, - {0x00, 0x00} -}; - -uint8_t ax5043_rxbuffer[256]; //buffer to receive radio data - -const uint8_t demo_packet[] = { 0x86, 0xA2, 0x40, 0x40, 0x40, 0x40, 0x60, 0x96, 0x8E, 0x6E, 0xB4, 0xAC, 0xAC, 0x61, 0x3F, 0xF0, 0x3E, 0x54, 0x65, 0x73, 0x74 }; - -char cw_message[] = "KG7ZVV Malay Das testing AX5043"; -//const uint8_t framing_insert_counter = 1; //uncomment for normal packets -const uint8_t framing_counter_pos = 0; -const uint8_t framing_insert_counter = 0; //uncomment for Ax.25 packets - - -//mailboxes to receive the radio packets -#define NUM_BUFFERS 16 - -static msg_t radio1_rx_queue[NUM_BUFFERS]; -static mailbox_t radio1_rx_mb; -static msg_t radio2_rx_queue[NUM_BUFFERS]; -static mailbox_t radio2_rx_mb; - - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - -/* - * Receive and Transmit SPI Configurations - */ -static const SPIConfig spicfg1 = -{ - false, - NULL, // Operation complete callback - LINE_AX1_CS, - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - -static const SPIConfig spicfg2 = -{ - false, - NULL, // Operation complete callback - LINE_AX2_CS, - // SPI cr1 data (see 446 ref man.) - SPI_CR1_SPE | // SPI enable - SPI_CR1_MSTR | // Master - //SPI_CR1_BR_2 | - SPI_CR1_BR_1 | - SPI_CR1_BR_0 | // fpclk/16 approx 5Mhz? BR = 0x011 - SPI_CR1_SSM, - 0, // SPI_CR2_SSOE, -}; - - - -static AX5043Config axcfg1 = -{ - &SPID1, - &spicfg1, - LINE_AX1_IRQ, - reg_values, - &radio1_rx_mb, - remoteaddr.addr, - localaddr.addr, - localaddr.mask -}; - -static AX5043Config axcfg2 = -{ - &SPID2, - &spicfg2, - LINE_AX2_IRQ, - reg_values, - &radio2_rx_mb, - remoteaddr.addr, - localaddr.addr, - localaddr.mask -}; - - -static AX5043Driver axd1; -static AX5043Driver axd2; - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - sdStart(&SD2, &ser_cfg); - - /* Creating the mailboxes.*/ - chMBObjectInit(&radio1_rx_mb, radio1_rx_queue, NUM_BUFFERS); - chMBObjectInit(&radio2_rx_mb, radio2_rx_queue, NUM_BUFFERS); - - ax5043Start(&axd1, &axcfg1); -} - - - - - -THD_WORKING_AREA(waAx5043_tx_thd, 1024); -THD_FUNCTION(ax5043_tx_thd, arg) -{ - (void)arg; - uint16_t pkt_counter = 0; - uint8_t ret_value[3]={0,0,0}; - - chThdSleepMilliseconds(500); - - -/* //This is for packet - for (;;) { - static uint8_t demo_packet_[sizeof(demo_packet)]; - //uint16_t pkt_counter = 0; - - ++pkt_counter; - memcpy(demo_packet_, demo_packet, sizeof(demo_packet)); - if (framing_insert_counter) { - demo_packet_[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF); - demo_packet_[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF); - } - - chprintf((BaseSequentialStream *)&SD2,"INFO: Sending packet %d\r\n",pkt_counter); - ax5043_radio2_packet_tx(&ax5043_driver, demo_packet_, sizeof(demo_packet)); - - chThdSleepMilliseconds(5000); - } - */ - - // This is for CW - - - for (;;) { - chprintf((BaseSequentialStream *)&SD2,"INFO: Sending CW %d\r\n", sizeof(cw_message)); - - /*ax5043_radio2_cw_tx(&ax1d, cw_message, sizeof(cw_message));*/ - - chThdSleepMilliseconds(500); - } - -} - - -THD_WORKING_AREA(waradio1_rx, 1024); -THD_FUNCTION(radio1_rx, arg) -{ - (void)arg; - - while (true) { - msg_t pbuf; - /* Waiting for radio1 rx buffer.*/ - msg_t msg = chMBFetchTimeout(&radio1_rx_mb, &pbuf, TIME_MS2I(10000)); - if (msg == MSG_OK) - chprintf((BaseSequentialStream *)&SD2,"INFO: rx on radio 1\r\n"); - } - -} - -THD_WORKING_AREA(waradio2_rx, 1024); -THD_FUNCTION(radio2_rx, arg) -{ - (void)arg; - - while (true) { - msg_t pbuf; - /* Waiting for radio1 rx buffer.*/ - msg_t msg = chMBFetchTimeout(&radio2_rx_mb, &pbuf, TIME_MS2I(10000)); - if (msg == MSG_OK) - chprintf((BaseSequentialStream *)&SD2,"INFO: rx on radio 2\r\n"); - } - -} - -/* - * shell commands - */ -static void mmd(BaseSequentialStream *chp, int argc, char *argv[]) { - - (void)argv; - if (argc > 0) { - chprintf(chp, "Usage: mmd\r\n"); - return; - } - - chprintf(chp, "testing\r\n"); -} - - -static const ShellCommand commands[] = { - {"mmd", mmd}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseSequentialStream *)&SD2, - commands -}; - -/* - * Entry to our code - */ -int main(void) -{ - thread_t *shelltp1; - - halInit(); - chSysInit(); - app_init(); - - ax5043ObjectInit(&axd1); - chThdSleepMilliseconds(5000); - chThdCreateStatic(waAx5043_tx_thd, sizeof(waAx5043_tx_thd), NORMALPRIO,ax5043_tx_thd, NULL); - chThdCreateStatic(waradio1_rx, sizeof(waradio1_rx), NORMALPRIO,radio1_rx, NULL); - chThdCreateStatic(waradio2_rx, sizeof(waradio2_rx), NORMALPRIO,radio2_rx, NULL); - - /* - * Shell manager initialization. - * Event zero is shell exit. - */ - shellInit(); - while (true) { - shelltp1 = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, - "shell1", NORMALPRIO + 1, - shellThread, (void *)&shell_cfg1); - chThdWait(shelltp1); - } - return 0; -} diff --git a/src/archive/app_radio/morse.c b/src/archive/app_radio/morse.c deleted file mode 100644 index 61830afa..00000000 --- a/src/archive/app_radio/morse.c +++ /dev/null @@ -1,188 +0,0 @@ -/* -The code here refers to logic and snippets from Adam Parker - KD5OOL -*/ - -#include -#include - - -#include "ch.h" -#include "hal.h" - -#include "morse.h" -#include "ax5043.h" - - -//#define MAX_MESSAGE_SIZE 512 -//char beaconMessage[MAX_MESSAGE_SIZE]; -uint16_t ditLength; - -/** - * @brief Morse code for alphabet and numbers. - */ -static const char *alpha[] = { - ".-", //A - "-...", //B - "-.-.", //C - "-..", //D - ".", //E - "..-.", //F - "--.", //G - "....", //H - "..", //I - ".---", //J - "-.-", //K - ".-..", //L - "--", //M - "-.", //N - "---", //O - ".--.", //P - "--.-", //Q - ".-.", //R - "...", //S - "-", //T - "..-", //U - "...-", //V - ".--", //W - "-..-", //X - "-.--", //Y - "--..", //Z -}; - -static const char *num[] = { - "-----", //0 - ".----", //1 - "..---", //2 - "...--", //3 - "....-", //4 - ".....", //5 - "-....", //6 - "--...", //7 - "---..", //8 - "----.", //9 -}; - -void SendDot(SPIDriver * spip) -{ - - uint8_t ret_value[3]={0,0,0}; - - ax5043_full_tx(spip); - //chprintf(DEBUG_CHP, "Dot\r\n"); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);//preamble - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - chThdSleepMilliseconds(DIT_MS); - ax5043_standby(spip); - -} - -void SendDash(SPIDriver * spip) -{ - - uint8_t ret_value[3]={0,0,0}; - - ax5043_full_tx(spip); - //chprintf(DEBUG_CHP, "Dash\r\n"); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xFF, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, ret_value);//preamble - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - chThdSleepMilliseconds(DASH_MS); - ax5043_standby(spip); -} - -void LetterSleep(void) -{ - chThdSleepMilliseconds(LETTER_SPACE_MS); -} - -void WordSleep(void) -{ - chThdSleepMilliseconds(WORD_SPACE_MS); -} - -void ElementSleep(void) -{ - chThdSleepMilliseconds(DIT_MS); -} - -//sets ditLength in ms -void SetWpm(int wpm) -{ - ditLength = 1200/wpm; -} - -/* -void SetMessage(char *message) -{ - memset(beaconMessage, 0, MAX_MESSAGE_SIZE); - int len = strlen(message); - if (strlen(message) >= MAX_MESSAGE_SIZE) - len = MAX_MESSAGE_SIZE-1; - memcpy(beaconMessage, message, len); -} -*/ - -const char *AsciiToMorse(char letter) -{ - letter = tolower(letter); - - if (isalpha(letter)) - { - return alpha[letter-'a']; - } - else if (isdigit(letter)) - { - return num[letter-'0']; - } - - return SPACE; -} - - -void SendMessage(SPIDriver * spip, char beaconMessage[], uint16_t pktlen ) -{ - int element; - int index = 0; - const char *morse; - while (index < pktlen) - { - morse = AsciiToMorse(beaconMessage[index]); - - element = 0; - while (morse[element] != '\0') - { - switch(morse[element]) - { - case '-': - SendDash(spip); - break; - case '.': - SendDot(spip); - break; - } - - if (morse[element] == ' ') - { - WordSleep(); - } - else if (morse[element+1] != '\0') - { - ElementSleep(); - } - else if (morse[element+1] == '\0') - { - LetterSleep(); - } - element++; - } - - index++; - //chprintf(DEBUG_CHP, ".. \r\n"); - } -} - diff --git a/src/archive/app_radio/morse.h b/src/archive/app_radio/morse.h deleted file mode 100644 index 513dfbb9..00000000 --- a/src/archive/app_radio/morse.h +++ /dev/null @@ -1,28 +0,0 @@ - -#ifndef _MORSE_H_ -#define _MORSE_H_ - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#define SPACE " " - - -#define LETTER_SPACE_MS (ditLength*3) -#define WORD_SPACE_MS (ditLength*7) -#define DIT_MS (ditLength) -#define DASH_MS (ditLength*3) - - - -void SendDot(SPIDriver * spip); -void SendDash(SPIDriver * spip); -void LetterSleep(void); -void WordSleep(void); -void ElementSleep(void); -void SetWpm(int wpm); -//void SetMessage(char *message); -//void SendMessage(SPIDriver * spip); -void SendMessage(SPIDriver * spip, char beaconMessage[], uint16_t pktlen ); - -#endif diff --git a/src/archive/app_radio/radio.c b/src/archive/app_radio/radio.c deleted file mode 100644 index 90a1913b..00000000 --- a/src/archive/app_radio/radio.c +++ /dev/null @@ -1,356 +0,0 @@ -/*! \file ax5043_driver.c */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include "ch.h" -#include "hal.h" - -#include "ax5043.h" -#include "ax5043_init.h" -#include "ax5043_driver.h" -#include "morse.h" - - -/** - * Change AX5043 radio1 configuraion. - * @param ax5043_driver_p: Radio driver, config: The set-up file details. - * @return Success or error code. - */ -uint8_t ax5043_radio1_chg_config(ax5043_drv_t *ax5043_driver_p, ax5043_config_t * config_p) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - ax5043_init(ax5043_driver_p->ax5043_spip1, config_p); - - switch(ax5043_driver_p->ax5043_mode1) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, config_p); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip1, config_p); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip1); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, config_p); - } - ax5043_set_addr(ax5043_driver_p->ax5043_spip1, config_p->localaddr); - ax5043_driver_p->ax5043_config1 = config_p; - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - return 0; - -} - -/** - * Change AX5043 radio2 configuraion. - * @param ax5043_driver_p: Radio driver, config: The set-up file details. - * @return Success or error code. - */ -uint8_t ax5043_radio2_chg_config(ax5043_drv_t *ax5043_driver_p, ax5043_config_t config) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem2, TIME_MS2I(120)); - ax5043_init(ax5043_driver_p->ax5043_spip2, config); - - switch(ax5043_driver_p->ax5043_mode2) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, config_p); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip2, config_p); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip2); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, config_p); - } - ax5043_set_addr(ax5043_driver_p->ax5043_spip2, config_p->localaddr); - ax5043_driver_p->ax5043_config2 = config_p; - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - return 0; - -} - - - -/** - * Change AX5043 radio1 mode (rx, tx, off). - * @param ax5043_driver_p: Radio driver, mode: rx, tx, off. - * @return Success or error code. - */ -uint8_t ax5043_radio1_mode(ax5043_drv_t *ax5043_driver_p, ax5043_mode_t mode) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - switch(mode) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip1); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - } - ax5043_driver_p->ax5043_mode1 = mode; - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - return 0; - -} - - - -/** - * Change AX5043 radio2 mode (rx, tx, off). - * @param ax5043_driver_p: Radio driver, mode: rx, tx, off. - * @return Success or error code. - */ -uint8_t ax5043_radio2_mode(ax5043_drv_t *ax5043_driver_p, ax5043_mode_t mode) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem2, TIME_MS2I(120)); - switch(mode) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip2); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - } - ax5043_driver_p->ax5043_mode2 = mode; - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - return 0; - -} - - -/** - * Receive packets from AX5043 radio1. - * @param ax5043_driver_p: Radio driver. - * @return The function is an infinite loop waiting to receive data from radio. - */ -uint8_t ax5043_radio1_rx(ax5043_drv_t *ax5043_driver_p) -{ - uint8_t ax5043_rxbuffer[256]; //buffer to receive radio data - uint8_t packet_len=0; - palEnableLineEvent(ax5043_driver_p->ax5043_int1, PAL_EVENT_MODE_RISING_EDGE); - - - - while(true) - { - palWaitLineTimeout(ax5043_driver_p->ax5043_int1, TIME_MS2I(5000)); - - if (ax5043_driver_p->ax5043_mode1 == AX5043_RX) - { - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - packet_len=receive_loop(ax5043_driver_p->ax5043_spip1, ax5043_rxbuffer); - if(packet_len > 0) - { - chprintf(DEBUG_CHP,"INFO:R1 Received packet %d\r\n",ax5043_rxbuffer[3]); - (void)chMBPostTimeout(ax5043_driver_p->ax5043_rx_mb1, (msg_t)ax5043_rxbuffer, TIME_MS2I(10000)); - } - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - } - } - return 0; -} - - -/** - * Receive packets from AX5043 radio2. - * @param ax5043_driver_p: Radio driver. - * @return The function is an infinite loop waiting to receive data from radio. - */ -uint8_t ax5043_radio2_rx(ax5043_drv_t *ax5043_driver_p) -{ - uint8_t ax5043_rxbuffer[256]; //buffer to receive radio data - uint8_t packet_len=0; - palEnableLineEvent(ax5043_driver_p->ax5043_int2, PAL_EVENT_MODE_RISING_EDGE); - - - - while(true) - { - palWaitLineTimeout(ax5043_driver_p->ax5043_int2, TIME_MS2I(5000)); - - if (ax5043_driver_p->ax5043_mode2 == AX5043_RX) - { - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem2, TIME_MS2I(120)); - packet_len=receive_loop(ax5043_driver_p->ax5043_spip2, ax5043_rxbuffer); - - if(packet_len > 0) - { - chprintf(DEBUG_CHP,"INFO:R2 Received packet %d\r\n",ax5043_rxbuffer[3]); - (void)chMBPostTimeout(ax5043_driver_p->ax5043_rx_mb2, (msg_t)ax5043_rxbuffer, TIME_MS2I(10000)); - } - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - } - } - return 0; -} - - -/** - * Send packets via AX5043 radio1. - * @param ax5043_driver_p: Radio driver, pkt: address of the packet, pktlen: length of packet - * @return the value of the register. - */ -uint8_t ax5043_radio1_packet_tx(ax5043_drv_t *ax5043_driver_p, uint8_t *pkt, uint16_t pktlen) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - transmit_packet(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1->remoteaddr, ax5043_driver_p->ax5043_config1->localaddr, pkt, pktlen); - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - return 0; -} - - - -/** - * Send packets via AX5043 radio2. - * @param ax5043_driver_p: Radio driver, pkt: address of the packet, pktlen: length of packet - * @return the value of the register. - */ -uint8_t ax5043_radio2_packet_tx(ax5043_drv_t *ax5043_driver_p, uint8_t *pkt, uint16_t pktlen) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem2, TIME_MS2I(120)); - transmit_packet(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config2->remoteaddr, ax5043_driver_p->ax5043_config2->localaddr, pkt, pktlen); - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - return 0; -} - -/** - * send CW/morse via AX5043 radio. - * @param spip: SPI Configuration - * @return error code - */ -uint8_t ax5043_radio_prepare_cw(SPIDriver * spip) -{ - uint8_t ret_value[3]={0,0,0}; - ax5043_full_tx(spip); - - /** - * This is not mentioned in datasheet or programming manual but is required. - * Removing this will make the transmission to transmit in low power for a few seconds - * before it reaches peak power. - */ - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, ret_value);//FIFO reset - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_REPEATDATA_CMD|0x00), ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, ret_value);//preamble flag - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0xff, ret_value); - ax5043_write_reg(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, ret_value);//preamble - ax5043_write_reg(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, ret_value);//FIFO Commit - - ax5043_standby(spip); - return 0; - -} - - -/** - * send CW/morse via AX5043 radio1. - * @param ax5043_driver_p: Radio driver, pkt: address of the packet, pktlen: length of packet - * @return error code - */ -uint8_t ax5043_radio1_cw_tx(ax5043_drv_t *ax5043_driver_p, char pkt[], uint16_t pktlen) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - ax5043_radio_prepare_cw(ax5043_driver_p->ax5043_spip1); - SetWpm(5); - SendMessage(ax5043_driver_p->ax5043_spip1, pkt, pktlen); - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - return 0; - -} - - - -/** - * send CW/morse via AX5043 radio2. - * @param ax5043_driver_p: Radio driver, pkt: address of the packet, pktlen: length of packet - * @return error code - */ -uint8_t ax5043_radio2_cw_tx(ax5043_drv_t *ax5043_driver_p, char pkt[], uint16_t pktlen) -{ - msg_t msg = chBSemWaitTimeout(ax5043_driver_p->ax5043_bsem1, TIME_MS2I(120)); - ax5043_radio_prepare_cw(ax5043_driver_p->ax5043_spip2); - SetWpm(5); - SendMessage(ax5043_driver_p->ax5043_spip2, pkt, pktlen); - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - return 0; - -} - -THD_WORKING_AREA(waAx5043_radio1, 1024); -THD_FUNCTION(ax5043_radio1, ax5043_driver_ptr) -{ - ax5043_drv_t* ax5043_driver_p=(ax5043_drv_t*)ax5043_driver_ptr; - - chBSemObjectInit(ax5043_driver_p->ax5043_bsem1, true); - ax5043_init(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - - switch(ax5043_driver_p->ax5043_mode1) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip1); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1); - } - ax5043_set_addr(ax5043_driver_p->ax5043_spip1, ax5043_driver_p->ax5043_config1->localaddr); - chBSemSignal(ax5043_driver_p->ax5043_bsem1); - chprintf(DEBUG_CHP, "done reseting AX5043 radio1 \r\n"); - ax5043_radio1_rx(ax5043_driver_p); - -} - - -THD_WORKING_AREA(waAx5043_radio2, 1024); -THD_FUNCTION(ax5043_radio2, ax5043_driver_ptr) -{ - ax5043_drv_t* ax5043_driver_p=(ax5043_drv_t*)ax5043_driver_ptr; - - chBSemObjectInit(ax5043_driver_p->ax5043_bsem2, true); - ax5043_init(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - - switch(ax5043_driver_p->ax5043_mode2) { - case ax5043_rx: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - break; - case ax5043_tx: - ax5043_prepare_tx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - break; - case ax5043_off: - ax5043_shutdown(ax5043_driver_p->ax5043_spip2); - default: - ax5043_prepare_rx(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2); - } - ax5043_set_addr(ax5043_driver_p->ax5043_spip2, ax5043_driver_p->ax5043_config2->localaddr); - chBSemSignal(ax5043_driver_p->ax5043_bsem2); - chprintf(DEBUG_CHP, "done reseting AX5043 radio2 \r\n"); - - ax5043_radio2_rx(ax5043_driver_p); -} - - -uint8_t ax5043_init(ax5043_drv_t *ax5043_driver_p) -{ - - chThdCreateStatic(waAx5043_radio1, sizeof(waAx5043_radio1), NORMALPRIO, ax5043_radio1, ax5043_driver_p); - chThdSleepMilliseconds(5000); - chThdCreateStatic(waAx5043_radio2, sizeof(waAx5043_radio2), NORMALPRIO, ax5043_radio2, ax5043_driver_p); - return 0; -} - - -//!@ diff --git a/src/archive/app_radio/radio.h b/src/archive/app_radio/radio.h deleted file mode 100644 index 741680ea..00000000 --- a/src/archive/app_radio/radio.h +++ /dev/null @@ -1,26 +0,0 @@ -/*! \file ax5043_driver.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_DRIVER_H_ -#define _AX5043_DRIVER_H_ - -//function declaration starts here -uint8_t ax5043_radio1_chg_config(ax5043_drv_t *ax5043_driver_p, ax5043_config_t config); -uint8_t ax5043_radio2_chg_config(ax5043_drv_t *ax5043_driver_p, ax5043_config_t config); -uint8_t ax5043_radio1_mode(ax5043_drv_t *ax5043_driver_p, ax5043_mode_t mode); -uint8_t ax5043_radio2_mode(ax5043_drv_t *ax5043_driver_p, ax5043_mode_t mode); -uint8_t ax5043_radio1_rx(ax5043_drv_t *ax5043_driver_p); -uint8_t ax5043_radio2_rx(ax5043_drv_t *ax5043_driver_p); -uint8_t ax5043_radio1_packet_tx(ax5043_drv_t *ax5043_driver_p, uint8_t *pkt, uint16_t pktlen); -uint8_t ax5043_radio2_packet_tx(ax5043_drv_t *ax5043_driver_p, uint8_t *pkt, uint16_t pktlen); -uint8_t ax5043_radio1_cw_tx(ax5043_drv_t *ax5043_driver_p, char pkt[], uint16_t pktlen); -uint8_t ax5043_radio2_cw_tx(ax5043_drv_t *ax5043_driver_p, char pkt[], uint16_t pktlen); -uint8_t ax5043_init(ax5043_drv_t *ax5043_driver_p); - -#endif -//! @} diff --git a/src/archive/app_radio/source/README.md b/src/archive/app_radio/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_radio/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_radio/source/ax5043.c b/src/archive/app_radio/source/ax5043.c deleted file mode 100644 index d9a5cd36..00000000 --- a/src/archive/app_radio/source/ax5043.c +++ /dev/null @@ -1,1088 +0,0 @@ -/** - * @file ax5043.c - * @brief AX5043 Radio. - * - * @addtogroup AX5043 - * @ingrup ORESAT - * @{ - */ - -#include -#include "ch.h" -#include "hal.h" -#include "ax5043.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -/** - * @brief Morse code for alphabets and numbers. - */ -static const char *alpha[] = { - ".-", //A - "-...", //B - "-.-.", //C - "-..", //D - ".", //E - "..-.", //F - "--.", //G - "....", //H - "..", //I - ".---", //J - "-.-", //K - ".-..", //L - "--", //M - "-.", //N - "---", //O - ".--.", //P - "--.-", //Q - ".-.", //R - "...", //S - "-", //T - "..-", //U - "...-", //V - ".--", //W - "-..-", //X - "-.--", //Y - "--..", //Z -}; - -static const char *num[] = { - "-----", //0 - ".----", //1 - "..---", //2 - "...--", //3 - "....-", //4 - ".....", //5 - "-....", //6 - "--...", //7 - "---..", //8 - "----.", //9 -}; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if (AX5043_USE_SPI) || defined(__DOXYGEN__) -/** - * @brief Reads AX5043 registers using SPI. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip SPI Configuration - * @param[in] reg Register address - * @param[in] value Register value - * @param[out] rxbuf Returned data - * @return The value in the register - * @notapi - */ -uint8_t ax5043SPIReadRegister(SPIDriver *spip, uint16_t reg, uint8_t value, uint8_t rxbuf[]) { - uint8_t cmd[3]; - - /* TODO: Optimize these functions */ - if (reg < 0x0070) { - cmd[0] = reg; - cmd[1] = value; - spiSelect(spip); - spiExchange(spip, 2, cmd, rxbuf); - spiUnselect(spip); - return rxbuf[1]; //return the reg value when reading the register - } else { - cmd[0] = 0x70 | (reg >> 8); - cmd[1] = reg; - cmd[2] = value; - spiSelect(spip); - spiExchange(spip, 3, cmd, rxbuf); - spiUnselect(spip); - return rxbuf[2]; //return the reg value when reading the register - } -} - -/** - * @brief Writes a value into a register using SPI. - * @pre The SPI interface must be initialized and the driver started. - * - * @param spip SPI Driver - * @param[in] reg Register address - * @param[in] value Register value - * @param[out] rxbuf Returned data - * @return The value in the register - * @notapi - */ -uint8_t ax5043SPIWriteRegister(SPIDriver *spip, uint16_t reg, uint8_t value, uint8_t rxbuf[]) { - uint8_t cmd[3]; - - /* TODO: Optimize these functions */ - if (reg < 0x0070) { - cmd[0]=0x80|reg; - cmd[1]=value; - spiSelect(spip); - spiExchange(spip, 2, cmd, rxbuf); - spiUnselect(spip); - } else { - cmd[0]=0xF0|(reg>>8); - cmd[1]=reg; - cmd[2]=value; - spiSelect(spip); - spiExchange(spip, 3, cmd, rxbuf); - spiUnselect(spip); - } - return rxbuf[0]; //retun status while writting the register -} - -/*===========================================================================*/ -/* TODO: Organize these functions and clean up comments */ -/*===========================================================================*/ - -/** - * @brief Sets powermode register of AX5043. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] reg_value powermode register value. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_set_pwrmode(AX5043Driver *devp, uint8_t reg_value){ - uint8_t rxbuf[3]={0,0,0}; - uint8_t value; - SPIDriver *spip = devp->config->spip; - - value = ax5043SPIReadRegister(spip, AX5043_REG_PWRMODE, (uint8_t)0x00, rxbuf); - value = value & 0xF0; - value = value | reg_value; - ax5043SPIWriteRegister(spip, AX5043_REG_PWRMODE, value, rxbuf); - devp->status_code = rxbuf[0]; - /*Return last status from Ax5043 while writting the register. - Normal value is 0x80 0r 0x88*/ - return rxbuf[0]; -} - -/** - * @brief Resets the AX5043. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_reset(AX5043Driver *devp) -{ - SPIDriver *spip = devp->config->spip; - uint8_t value = 0; - uint8_t rxbuf[3]={0,0,0}; - - /* TODO: What's this for? */ - spiSelect(spip); - chThdSleepMicroseconds(5); - spiUnselect(spip); - chThdSleepMicroseconds(5); - spiSelect(spip); - chThdSleepMicroseconds(5); - - /* Reset the chip through powermode register.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_PWRMODE, AX5043_RESET_BIT, rxbuf); - chThdSleepMilliseconds(1); - - /* Write to powermode register for enabling XOEN and REFIN and shutdown mode. - Page 33 in programming manual.*/ - value = ax5043SPIReadRegister(spip, AX5043_REG_PWRMODE, value, rxbuf); - /* TODO: Why are we grabbing the register value if we overwrite it completely? */ - value = AX5043_OSC_EN_BIT | AX5043_REF_EN_BIT | AX5043_POWERDOWN; - ax5043SPIWriteRegister(spip, AX5043_REG_PWRMODE, value, rxbuf); - - ax5043SPIWriteRegister(spip, AX5043_REG_SCRATCH, (uint8_t)0xAA, rxbuf); - value = ax5043SPIReadRegister(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, rxbuf); - if (value != 0xAA) { - devp->error_code = AXRADIO_ERR_NOT_CONNECTED; - } - ax5043SPIWriteRegister(spip, AX5043_REG_SCRATCH, (uint8_t)0x55, rxbuf); - value = ax5043SPIReadRegister(spip, AX5043_REG_SCRATCH, (uint8_t)0x00, rxbuf); - if (value != 0x55) { - devp->error_code = AXRADIO_ERR_NOT_CONNECTED; - } - /*Return last status from Ax5043 while writting the register.*/ - return rxbuf[0]; -} - -/** - * @brief Writes to AX5043 FIFO - * - * @param[in] spip pointer to the @p SPIDriver object. - * @param[in] ptr Pointer to array to be written to FIFO. - * @param[in] len length of array to be written to FIFO. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_writefifo(SPIDriver * spip, const uint8_t *ptr, uint8_t len){ - uint8_t rxbuf[3]={0,0,0}; - if (!len) - return; - do { - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, *ptr++, rxbuf); - } while (--len); -} - -/** - * @brief Reads to AX5043 FIFO - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] axradio_rxbuffer[] Pointer to array where the packet will be kept. - * @param[in] len Maximum length of array to be read FIFO. - * - * @param[out] Bytes read from FIFO. - */ -uint8_t ax5043_readfifo(SPIDriver * spip, uint8_t axradio_rxbuffer[], uint8_t len) { - uint8_t rxbuf[3]={0,0,0}; - uint8_t bytes_read = 0; - while (len--) { - axradio_rxbuffer[bytes_read] = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - bytes_read++; - } - return bytes_read; -} - -/** - * @brief Sets AX5043 registers. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] group register group that needs to be written. - * - * @return Most significant status bits from last SPI call. - */ -uint8_t ax5043_set_regs_group(AX5043Driver *devp, ax5043_reg_group_t group) { - uint8_t rxbuf[3] = {0, 0, 0}; - int i = 0; - ax5043_regval_t* entry = devp->config->reg_values; - while (entry[i].reg != AX5043_REG_END) { - if (entry[i].group == group){ - ax5043SPIWriteRegister(devp->config->spip, entry[i].reg, entry[i].val, rxbuf); - } - i++; - } - devp->status_code = rxbuf[0]; - /*Return last status from Ax5043 while writting the register.*/ - return rxbuf[0]; -} - -/** - * @brief Gets AX5043 register values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] reg_name register name. - * - * @return register value. - */ -uint8_t ax5043_get_reg_val(AX5043Driver *devp, uint16_t reg_name) { - int i = 0; - ax5043_regval_t* entry = devp->config->reg_values; - while (entry[i].reg != AX5043_REG_END) { - if (entry[i].reg == reg_name){ - return entry[i].val; - } - i++; - } - devp->error_code = AXRADIO_ERR_REG_NOT_IN_CONF; - return 0; -} - -/** - * @brief Gets AX5043 configuration values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] conf_name configuration variable name. - * - * @retrun value in configuration variable. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint32_t ax5043_get_conf_val(AX5043Driver *devp, uint8_t conf_name) { - int i = 0; - ax5043_confval_t* entry = devp->config->conf_values; - while (entry[i].conf_name != AXRADIO_PHY_END) { - if (entry[i].conf_name == conf_name){ - return entry[i].val; - } - i++; - } - devp->error_code = AXRADIO_ERR_VAL_NOT_IN_CONF; - return 0; -} - -/** - * @brief Sets AX5043 configuration values from the AX5043 driver structure. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] conf_name configuration variable name. - * @param[in] value value in configuration variable. - * - * @return 0 if successful, else 0x11. - */ -uint8_t ax5043_set_conf_val(AX5043Driver *devp, uint8_t conf_name, uint32_t value) { - int i = 0; - ax5043_confval_t* entry = devp->config->conf_values; - while (entry[i].conf_name != AXRADIO_PHY_END) { - if (entry[i].conf_name == conf_name){ - entry[i].val = value; - return 0; - } - i++; - } - devp->error_code = AXRADIO_ERR_VAL_NOT_IN_CONF; - return AXRADIO_ERR_VAL_NOT_IN_CONF; -} - -/** - * @brief Prepare AX5043 for tx. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_tx(AX5043Driver *devp){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - ax5043_set_pwrmode(devp, AX5043_FIFO_ENABLED); - ax5043_set_regs_group(devp,tx); - ax5043_init_registers_common(devp); - - /* Set FIFO threshold and interrupt mask.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_IRQMASK0, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_IRQMASK1, (uint8_t)0x01, rxbuf); - - /* Wait for xtal.*/ - while ((ax5043SPIReadRegister(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, rxbuf) & 0x01) == 0) { - chThdSleepMilliseconds(1); - } - devp->status_code = rxbuf[0]; - devp->state = AX5043_TX; -} - -/** - * @brief prepare AX5043 for rx. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_prepare_rx(AX5043Driver *devp){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_regs_group(devp,rx); - ax5043_init_registers_common(devp); - - /* Updates RSSI reference value, Sets a group of RX registers.*/ - uint8_t rssireference = ax5043_get_conf_val(devp, AXRADIO_PHY_RSSIREFERENCE) ; - ax5043SPIWriteRegister(spip, AX5043_REG_RSSIREFERENCE, rssireference, rxbuf); - ax5043_set_regs_group(devp,rx_cont); - /* Resets FIFO, changes powermode to FULL RX.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, rxbuf); - ax5043_set_pwrmode(devp, AX5043_FULL_RX); - /* Sets FIFO threshold and interrupt mask.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOTHRESH1, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOTHRESH0, (uint8_t)0x80, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_IRQMASK0, (uint8_t)0x01, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_IRQMASK1, (uint8_t)0x00, rxbuf); - devp->status_code = rxbuf[0]; - devp->state = AX5043_RX; -} - -/** - * @brief Does PLL ranging. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @returns PLLVCOI Register content. - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t axradio_get_pllvcoi(AX5043Driver *devp){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t x = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANVCOIINIT) ; - uint8_t pll_init_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNGINIT); - uint8_t pll_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - if (x & 0x80) { - if (!(pll_init_val & 0xF0)) { - x += (pll_val & 0x0F) - (pll_init_val & 0x0F); - x &= 0x3f; - x |= 0x80; - } - return x; - } - return ax5043SPIReadRegister(spip, AX5043_REG_PLLVCOI, (uint8_t)0x00, rxbuf); -} - -/** - * @brief Initialized AX5043 registers common to RX and TX. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO return a -ve return code if there are any errors - */ -void ax5043_init_registers_common(AX5043Driver *devp){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t rng = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - if (rng & 0x20) - devp->status_code = AXRADIO_ERR_PLLRNG_VAL; - if ( ax5043SPIReadRegister(spip, AX5043_REG_PLLLOOP, (uint8_t)0x00, rxbuf) & 0x80) { - ax5043SPIWriteRegister(spip, AX5043_REG_PLLRANGINGB, (uint8_t)(rng & 0x0F), rxbuf); - } - else { - ax5043SPIWriteRegister(spip, AX5043_REG_PLLRANGINGA, (uint8_t)(rng & 0x0F), rxbuf); - } - rng = axradio_get_pllvcoi(devp); - if (rng & 0x80) - ax5043SPIWriteRegister(spip, AX5043_REG_PLLVCOI, (uint8_t)(rng), rxbuf); -} - -/** - * @brief Initializes AX5043. This is written based on easyax5043.c generated from AX Radiolab. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @api - * TODO Standardize the error handling. - */ -void ax5043_init(AX5043Driver *devp){ - SPIDriver *spip = devp->config->spip; - uint8_t rxbuf[3]={0,0,0}; - - ax5043_reset(devp); - - ax5043_set_regs_group(devp,common); - ax5043_set_regs_group(devp,tx); - - ax5043SPIWriteRegister(spip, AX5043_REG_PLLLOOP, (uint8_t)0x09, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_PLLCPI, (uint8_t)0x08, rxbuf); - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - ax5043SPIWriteRegister(spip, AX5043_REG_MODULATION, (uint8_t)0x08, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, rxbuf); - - /* Wait for Xtal.*/ - while ((ax5043SPIReadRegister(spip, AX5043_REG_XTALSTATUS, (uint8_t)0x00, rxbuf) & 0x01) == 0){ - chThdSleepMilliseconds(1); - } - - /* Set frequency.*/ - uint32_t f = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANFREQ); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA0, (uint8_t)f, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), rxbuf); - - /* PLL autoranging.*/ - uint8_t r; - uint8_t pll_init_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNGINIT); - if( !(pll_init_val & 0xF0) ) { // start values for ranging available - r = pll_init_val | 0x10; - } - else { - r = 0x18; - } - ax5043SPIWriteRegister(spip, AX5043_REG_PLLRANGINGA, (uint8_t)r, rxbuf); - chThdSleepMilliseconds(1); - while ((ax5043SPIReadRegister(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, rxbuf) & 0x10) != 0) - { - chThdSleepMilliseconds(1); - } - int8_t value = ax5043SPIReadRegister(spip, AX5043_REG_PLLRANGINGA, (uint8_t)0x00, rxbuf); - ax5043_set_conf_val(devp, AXRADIO_PHY_CHANPLLRNG, value); - devp->state = AX5043_PLL_RANGE_DONE; - - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - ax5043_set_regs_group(devp,common); - ax5043_set_regs_group(devp,rx); - - uint8_t pll_val = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANPLLRNG); - ax5043SPIReadRegister(spip, AX5043_REG_PLLRANGINGA, (pll_val & 0x0F), rxbuf); - f = ax5043_get_conf_val(devp, AXRADIO_PHY_CHANFREQ); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA0, (uint8_t)f, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA1, (uint8_t)(f >> 8), rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA2, (uint8_t)(f >> 16), rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FREQA3, (uint8_t)(f >> 24), rxbuf); - - ax5043_set_regs_group(devp,local_address); -} - -/** - * @brief Transmit loop to transmit bytes of a packet. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] packet_len Complete packet length including mac. - * @param[in] axradio_txbuffer pointer to packet. - * @param[in] packet_bytes_sent length before the packet. - * - * @api - * TODO Standardize the error handling, remove packet_bytes_sent, simplify the code. - */ -void transmit_loop(AX5043Driver *devp, uint16_t packet_len,uint8_t axradio_txbuffer[]){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - uint8_t free_fifo_bytes; - uint8_t packet_end_indicator = 0; - uint16_t packet_bytes_sent = 0; - uint8_t flags = 0; - uint16_t packet_len_to_be_sent = 0; - uint8_t synclen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCLEN); - - while (packet_end_indicator == 0) { - if (ax5043SPIReadRegister(spip,AX5043_REG_FIFOFREE1, (uint8_t)0x00, rxbuf)) - free_fifo_bytes = 0xff; - else - free_fifo_bytes = ax5043SPIReadRegister(spip,AX5043_REG_FIFOFREE0, (uint8_t)0x00, rxbuf); - /* Make sure sixteen bytes in FIFO are free. We can do with minimum 4 bytes free but taking in 16 here.*/ - if (free_fifo_bytes < 19) { - /* FIFO commit.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_FIFOSTAT, 4, rxbuf); - continue; - } - - switch (devp->state) { - case AX5043_TX_LONGPREAMBLE: - if (!packet_bytes_sent) { - devp->state = AX5043_TX_SHORTPREAMBLE; - packet_bytes_sent = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_LEN); - break; - } - - free_fifo_bytes = 7; - if (packet_bytes_sent < 7) - free_fifo_bytes = packet_bytes_sent; - packet_bytes_sent -= free_fifo_bytes; - free_fifo_bytes <<= 5; - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_FLAGS), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, free_fifo_bytes, rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE), rxbuf); - break; - - case AX5043_TX_SHORTPREAMBLE: - if (!packet_bytes_sent) { - uint8_t preamble_appendbits = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_APPENDBITS); - if (preamble_appendbits) { - uint8_t byte; - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, 0x1C, rxbuf); - byte = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_APPENDPATTERN); - if (ax5043SPIReadRegister(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, rxbuf) & 0x80) { - // msb first -> stop bit below - byte &= 0xFF << (8-preamble_appendbits); - byte |= 0x80 >> preamble_appendbits; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-preamble_appendbits); - byte |= 0x01 << preamble_appendbits; - } - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, byte, rxbuf); - } - if ((ax5043SPIReadRegister(spip,AX5043_REG_FRAMING, (uint8_t)0x00, rxbuf) & 0x0E) == 0x06 && synclen) { - /* Write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS. - Chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT).*/ - int8_t len_byte = synclen; - uint8_t i = (len_byte & 0x07) ? 0x04 : 0; - /* SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits.*/ - len_byte += 7; - len_byte >>= 3; - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCFLAGS) | i, rxbuf); - - uint8_t syncword[4] = {ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD0), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD1), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD2), - ax5043_get_conf_val(devp, AXRADIO_FRAMING_SYNCWORD3)}; - for (i = 0; i < len_byte; ++i) { - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, syncword[i], rxbuf); - } - } - devp->state = AX5043_TX_PACKET; - continue; - } - free_fifo_bytes = 255; - if (packet_bytes_sent < 255*8) - free_fifo_bytes = packet_bytes_sent >> 3; - if (free_fifo_bytes) { - packet_bytes_sent -= ((uint16_t)free_fifo_bytes) << 3; - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_FLAGS), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, free_fifo_bytes, rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, (uint8_t)ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE), rxbuf); - continue; - } - { - uint8_t byte = ax5043_get_conf_val(devp, AXRADIO_PHY_PREAMBLE_BYTE) ; - free_fifo_bytes = packet_bytes_sent; - packet_bytes_sent = 0; - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5), rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, 0x1C, rxbuf); - if (ax5043SPIReadRegister(spip,AX5043_REG_PKTADDRCFG, (uint8_t)0x00, rxbuf) & 0x80) { - /* MSB first -> stop bit below.*/ - byte &= 0xFF << (8-free_fifo_bytes); - byte |= 0x80 >> free_fifo_bytes; - } else { - // lsb first -> stop bit above - byte &= 0xFF >> (8-free_fifo_bytes); - byte |= 0x01 << free_fifo_bytes; - } - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, byte, rxbuf); - } - continue; - - case AX5043_TX_PACKET: - flags = 0; - packet_len_to_be_sent = 0; - if (!packet_bytes_sent) - /* Flag byte indicates packetstart.*/ - flags |= 0x01; - - packet_len_to_be_sent = packet_len - packet_bytes_sent; - /* 3 bytes of FIFO commands are written before payload can be written to FIFO.*/ - if (free_fifo_bytes >= packet_len_to_be_sent + 3) { - /* Flag byte indicates packet end.*/ - flags |= 0x02; - } - else{ - packet_len_to_be_sent = free_fifo_bytes - 3; - } - - - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), rxbuf); - /* Write FIFO chunk length byte. Length includes the flag byte, thus the +1.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, packet_len_to_be_sent + 1, rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, flags, rxbuf); - ax5043_writefifo(spip,&axradio_txbuffer[packet_bytes_sent], packet_len_to_be_sent); - packet_bytes_sent += packet_len_to_be_sent; - if (flags & 0x02){ - packet_end_indicator = 1; - /* Enable radio event done (REVRDONE) event.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_RADIOEVENTMASK0, 0x01, rxbuf); - ax5043SPIWriteRegister(spip,AX5043_REG_FIFOSTAT, 4, rxbuf); // commit - } - break; - - default: - packet_end_indicator = 1; - devp->error_code = AXRADIO_ERR_UNEXPECTED_STATE; - } - } - devp->state = AX5043_TX; -} - -/** - * @brief Transmits a packet. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] addr remote destination address of packet. - * @param[in] pkt pointer to packet. - * @param[in] pktlen packet length. - * - * @param[out] AXRADIO_ERR Error code. - * - * @api - * TODO Standardize the error handling, Maybe move address to a driver config structure - */ -uint8_t transmit_packet(AX5043Driver *devp, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) { - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - uint16_t packet_len; - uint8_t axradio_txbuffer[PKTDATA_BUFLEN]; - uint8_t axradio_localaddr[4]; - - uint8_t maclen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_MACLEN); - uint8_t destaddrpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_DESTADDRPOS); - uint8_t addrlen = ax5043_get_conf_val(devp, AXRADIO_FRAMING_ADDRLEN); - uint8_t sourceaddrpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_SOURCEADDRPOS); - uint8_t lenmask = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENMASK); - uint8_t lenoffs = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENOFFS); - uint8_t lenpos = ax5043_get_conf_val(devp, AXRADIO_FRAMING_LENPOS); - - axradio_localaddr[0] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR0); - axradio_localaddr[1] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR1); - axradio_localaddr[2] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR2); - axradio_localaddr[3] = ax5043_get_reg_val(devp, AX5043_REG_PKTADDR3); - - packet_len = pktlen + maclen; - if (packet_len > sizeof(axradio_txbuffer)) - return AXRADIO_ERR_INVALID; - - /* Prepare the MAC segment of the packet.*/ - memset(axradio_txbuffer, 0, maclen); - memcpy(&axradio_txbuffer[maclen], pkt, pktlen); - if (destaddrpos != 0xff) - memcpy(&axradio_txbuffer[destaddrpos], &addr->addr, addrlen); - if (sourceaddrpos != 0xff) - memcpy(&axradio_txbuffer[sourceaddrpos], axradio_localaddr, addrlen); - if (lenmask) { - /* Calculate payload length and update the MAC of payload.*/ - uint8_t len_byte = (uint8_t)(packet_len - lenoffs) & lenmask; - axradio_txbuffer[lenpos] = (axradio_txbuffer[lenpos] & (uint8_t)~lenmask) | len_byte; - } - /*Clear radioevent flag. This indicator is set when packet is out.*/ - ax5043SPIReadRegister(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, rxbuf); - /* Clear leftover FIFO data & flags.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOSTAT, 3, rxbuf); - devp->state = AX5043_TX_LONGPREAMBLE; - - /*Code for 4-FSK mode.*/ - if ((ax5043SPIReadRegister(spip,AX5043_REG_MODULATION, (uint8_t)0x00, rxbuf) & 0x0F) == 9) { - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5), rxbuf); - /* Length including flags.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, 2, rxbuf); - /* Flag PKTSTART -> dibit sync.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, 0x01, rxbuf); - /* Dummy byte for forcing dibit sync.*/ - ax5043SPIWriteRegister(spip,AX5043_REG_FIFODATA, 0x11, rxbuf); - } - transmit_loop(devp, packet_len, axradio_txbuffer); - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - - ax5043SPIReadRegister(spip,AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, rxbuf); - while (ax5043SPIReadRegister(spip,AX5043_REG_RADIOSTATE, (uint8_t)0x00, rxbuf) != 0) { - chThdSleepMilliseconds(1); - } - - ax5043SPIWriteRegister(spip,AX5043_REG_RADIOEVENTMASK0, 0x00, rxbuf); - devp->error_code = AXRADIO_ERR_NOERROR; - return AXRADIO_ERR_NOERROR; -} - -/** - * @brief Receive loop to recieve bytes from FIFO. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[out] axradio_rxbuffer[] Pointer to array where the packet will be kept. - * - * @return Length of packet received. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t receive_loop(AX5043Driver *devp, uint8_t axradio_rxbuffer[]) { - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - uint8_t fifo_cmd; - uint8_t i; - uint8_t chunk_len; - uint8_t bytesRead = 0; - - /* Clear interrupt.*/ - ax5043SPIReadRegister(spip, AX5043_REG_RADIOEVENTREQ0, (uint8_t)0x00, rxbuf); - devp->state = AX5043_RX_LOOP; - /* Loop until FIFO not empty.*/ - while ((ax5043SPIReadRegister(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x00, rxbuf) & 0x01) != 1) { - /* FIFO read comman.*/ - fifo_cmd = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - /* Top 3 bits encode payload length.*/ - chunk_len = (fifo_cmd & 0xE0) >> 5; - /* 7 means variable length, get length byte from next read.*/ - if (chunk_len == 7) - chunk_len = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - fifo_cmd &= 0x1F; - switch (fifo_cmd) { - case AX5043_FIFOCMD_DATA: - if (chunk_len!=0){ - /* Discard the flag.*/ - ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - chunk_len = chunk_len - 1; - bytesRead = ax5043_readfifo(spip, axradio_rxbuffer, chunk_len); - } - break; - - case AX5043_FIFOCMD_RFFREQOFFS: - if (chunk_len == 3){ - devp->rf_freq_off3 = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->rf_freq_off2 = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->rf_freq_off1 = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - } - else{ - for(i=0;idropped[i] = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - case AX5043_FIFOCMD_FREQOFFS: - if (chunk_len == 2){ - devp->rf_freq_off3 = 0; - devp->rf_freq_off2 = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->rf_freq_off1 = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - } - else{ - for(i=0;idropped[i] = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - case AX5043_FIFOCMD_RSSI: - if (chunk_len == 1){ - devp->rssi = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - } - else{ - for(i=0;idropped[i] = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - devp->error_code = AXRADIO_ERR_FIFO_CHUNK; - } - } - break; - - default: - devp->error_code = AXRADIO_ERR_FIFO_CMD; - for(i=0;idropped[i] = ax5043SPIReadRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - } - } - devp->state = AX5043_RX; - } - return bytesRead; -} - -/** - * @brief Prepare for CW mode - * - * @param[in] devp pointer to the @p AX5043Driver object. - * - * @return Length of packet received. - * - * @api - * TODO return a -ve return code if there are any errors - */ -uint8_t ax5043_prepare_cw(AX5043Driver *devp){ - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV2, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV1, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FSKDEV0, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_TXRATE2, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_TXRATE1, (uint8_t)0x00, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_TXRATE0, (uint8_t)0x01, rxbuf); - - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - - /* This is not mentioned in datasheet or programming manual but is required. - * Removing this will make the transmission to transmit in low power for a few seconds - * before it reaches peak power.*/ - /* FIFO reset.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x03, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_FIFOCMD_REPEATDATA|0x60), rxbuf); - /* Preamble flag.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0xff, rxbuf); - /* Preamble.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x55, rxbuf); - /* FIFO Commit.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, rxbuf); - - ax5043_set_pwrmode(devp, AX5043_STANDBY); - devp->state = AX5043_CW; - return 0; -} - -/** - * @brief Send Morse dot and dash over the air - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] dot_dash_time time in milliseconds for transmiter to be on. - */ -void ax5043_morse_dot_dash(AX5043Driver *devp, uint16_t dot_dash_time){ - - uint8_t rxbuf[3]={0,0,0}; - SPIDriver *spip = devp->config->spip; - - ax5043_set_pwrmode(devp, AX5043_FULL_TX); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)(AX5043_FIFOCMD_REPEATDATA|0x60), rxbuf); - /* Preamble flag.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x38, rxbuf); - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0xFF, rxbuf); - /* Preamble.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFODATA, (uint8_t)0x00, rxbuf); - /* FIFO Commit.*/ - ax5043SPIWriteRegister(spip, AX5043_REG_FIFOSTAT, (uint8_t)0x04, rxbuf); - chThdSleepMilliseconds(dot_dash_time); - ax5043_set_pwrmode(devp, AX5043_STANDBY); - -} - -/** - * @brief Convert an alphabet or number to morse dot and dash - * - * @param[in] letter An alphabet or number. - * - * @return Length of packet received. - */ -const char *ax5043_ascii_to_morse(char letter){ - letter = tolower(letter); - - if (isalpha(letter)){ - return alpha[letter-'a']; - } - else if (isdigit(letter)){ - return num[letter-'0']; - } - - return SPACE; -} - -/** - * @brief Convert a message to morse code and transmit it. - * - * @param[in] devp pointer to the @p AX5043Driver object. - * @param[in] wpm words per minute. - * @param[in] beaconMessage Message to be transmitted. - * @param[in] pktlen Length of packet/beacon message. - */ -void ax5043_send_cw(AX5043Driver *devp, int wpm, char beaconMessage[], uint16_t pktlen ){ - int element; - int index = 0; - const char *morse; - - uint16_t ditLength = 1200/wpm; - uint16_t letter_space = ditLength*3; - uint16_t word_space = ditLength*7; - uint16_t element_space = ditLength; - uint16_t dash = ditLength*3; - - while (index < pktlen){ - morse = ax5043_ascii_to_morse(beaconMessage[index]); - - element = 0; - while (morse[element] != '\0'){ - switch(morse[element]){ - case '-': - ax5043_morse_dot_dash(devp, dash); - break; - case '.': - ax5043_morse_dot_dash(devp, ditLength); - break; - } - - if (morse[element] == ' '){ - chThdSleepMilliseconds(word_space); - } - else if (morse[element+1] != '\0'){ - chThdSleepMilliseconds(element_space); - } - else if (morse[element+1] == '\0'){ - chThdSleepMilliseconds(letter_space); - } - element++; - } - - index++; - } -} -/*===========================================================================*/ -/* TODO END CLEANUP */ -/*===========================================================================*/ - -#endif /* AX5043_USE_SPI */ - -/*==========================================================================*/ -/* Interface implementation. */ -/*==========================================================================*/ - -static const struct AX5043VMT vmt_device = { - (size_t)0, -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes an instance of AX5043Driver object. - * - * @param[out] devp pointer to the @p AX5043Driver object - * - * @init - */ -void ax5043ObjectInit(AX5043Driver *devp) { - devp->vmt = &vmt_device; - - devp->config = NULL; - - devp->state = AX5043_STOP; -} - -/** - * @brief Configures and activates the AX5043 Radio Driver. - * - * @param[in] devp pointer to the @p AX5043Driver object - * @param[in] config pointer to the @p AX5043Config object - * - * @api - */ -void ax5043Start(AX5043Driver *devp, const AX5043Config *config) { - osalDbgCheck((devp != NULL) && (config != NULL)); - osalDbgAssert((devp->state == AX5043_STOP) || - (devp->state == AX5043_READY), - "ax5043Start(), invalid state"); - - devp->config = config; - devp->rf_freq_off3 = 0; - devp->rf_freq_off2 = 0; - devp->rf_freq_off1 = 0; - devp->rssi = 0; - devp->error_code = 0; - devp->status_code = 0; - - ax5043_init(devp); - switch(config->ax5043_mode) { - case AX5043_MODE_RX: - ax5043_prepare_rx(devp); - break; - case AX5043_MODE_TX: - ax5043_prepare_tx(devp); - break; - case AX5043_MODE_CW: - ax5043_prepare_cw(devp); - break; - case AX5043_MODE_OFF: - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - break; - default: - ax5043_prepare_rx(devp); - } -} - -/** - * @brief Deactivates the AX5043 Radio Driver. - * - * @param[in] devp pointer to the @p AX5043Driver object - * - * @api - */ -void ax5043Stop(AX5043Driver *devp) { - ax5043_set_pwrmode(devp, AX5043_POWERDOWN); - devp->state = AX5043_OFF; - /* TODO: verify if additional driver things needs to be done.*/ - devp->state = AX5043_STOP; -} - -/** @} */ diff --git a/src/archive/app_radio/source/ax5043.h b/src/archive/app_radio/source/ax5043.h deleted file mode 100644 index ebe8211e..00000000 --- a/src/archive/app_radio/source/ax5043.h +++ /dev/null @@ -1,741 +0,0 @@ -/** - * @file ax5043.h - * @brief AX5043 Radio. - * - * @addtogroup AX5043 - * @ingroup ORESAT - * @{ - */ -#ifndef _AX5043_H_ -#define _AX5043_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Version Identification - * @{ - */ -/** - * @brief AX5043 Driver version string. - */ -#define AX5043_VERSION "1.0.0" - -/** - * @brief AX5043 Driver version major number. - */ -#define AX5043_MAJOR 1 - -/** - * @brief AX5043 Driver version minor number. - */ -#define AX5043_MINOR 0 - -/** - * @brief AX5043 Driver version patch number. - */ -#define AX5043_PATCH 0 -/** @} */ - -/** - * @name AX5043 Register Addresses - * @{ - */ -/* Status and test registers */ -#define AX5043_REG_REV 0x0 -#define AX5043_REG_SCRATCH 0x1 - -/* Power and voltage regulator */ -#define AX5043_REG_PWRMODE 0x2 -#define AX5043_REG_POWSTAT 0x3 -#define AX5043_REG_POWSTICKYSTAT 0x4 -#define AX5043_REG_POWIRQMASK 0x5 - -/* Interrupt control */ -#define AX5043_REG_IRQMASK1 0x6 -#define AX5043_REG_IRQMASK0 0x7 -#define AX5043_REG_RADIOEVENTMASK1 0x8 -#define AX5043_REG_RADIOEVENTMASK0 0x9 - -#define AX5043_REG_IRQREQUEST1 0xC -#define AX5043_REG_IRQREQUEST0 0xD -#define AX5043_REG_RADIOEVENTREQ1 0xE -#define AX5043_REG_RADIOEVENTREQ0 0xF - -/* Modulation and framing */ -#define AX5043_REG_MODULATION 0x010 -#define AX5043_REG_ENCODING 0x011 -#define AX5043_REG_FRAMING 0x012 -#define AX5043_REG_CRCINIT3 0x014 -#define AX5043_REG_CRCINIT2 0x015 -#define AX5043_REG_CRCINIT1 0x016 -#define AX5043_REG_CRCINIT0 0x017 - -/* FEC */ -#define AX5043_REG_FEC 0x018 -#define AX5043_REG_FECSYNC 0x019 -#define AX5043_REG_FECSTATUS 0x01A - -/* Status */ -#define AX5043_REG_RADIOSTATE 0x01C -#define AX5043_REG_XTALSTATUS 0x01D - -/* Pin configuration */ -#define AX5043_REG_PINSTATE 0x20 -#define AX5043_REG_PINFUNCSYSCLK 0x21 -#define AX5043_REG_PINFUNCDCLK 0x22 -#define AX5043_REG_PINFUNCDATA 0x23 -#define AX5043_REG_PINFUNCIRQ 0x24 -#define AX5043_REG_PINFUNCANTSEL 0x25 -#define AX5043_REG_PINFUNCPWRAMP 0x26 -#define AX5043_REG_PWRAMP 0x27 - -/* FIFO control */ -#define AX5043_REG_FIFOSTAT 0x28 -#define AX5043_REG_FIFODATA 0x29 -#define AX5043_REG_FIFOCOUNT1 0x2A -#define AX5043_REG_FIFOCOUNT0 0x2B -#define AX5043_REG_FIFOFREE1 0x2C -#define AX5043_REG_FIFOFREE0 0x2D -#define AX5043_REG_FIFOTHRESH1 0x2E -#define AX5043_REG_FIFOTHRESH0 0x2F - -/* Frequency Synthesizer */ -#define AX5043_REG_PLLLOOP 0x30 -#define AX5043_REG_PLLCPI 0x31 -#define AX5043_REG_PLLVCODIV 0x32 -#define AX5043_REG_PLLRANGINGA 0x33 -#define AX5043_REG_FREQA3 0x34 -#define AX5043_REG_FREQA2 0x35 -#define AX5043_REG_FREQA1 0x36 -#define AX5043_REG_FREQA0 0x37 -#define AX5043_REG_PLLLOOPBOOST 0x38 -#define AX5043_REG_PLLCPIBOOST 0x39 -#define AX5043_REG_PLLRANGINGB 0x3B -#define AX5043_REG_FREQB3 0x3C -#define AX5043_REG_FREQB2 0x3D -#define AX5043_REG_FREQB1 0x3E -#define AX5043_REG_FREQB0 0x3F - -/* RSSI */ -#define AX5043_REG_RSSI 0x40 -#define AX5043_REG_BGNDRSSI 0x41 -#define AX5043_REG_DIVERSITY 0x42 -#define AX5043_REG_AGCCOUNTER 0x43 - -/* Receiver Tracking */ -#define AX5043_REG_TRKDATARATE2 0x45 -#define AX5043_REG_TRKDATARATE1 0x46 -#define AX5043_REG_TRKDATARATE0 0x47 -#define AX5043_REG_TRKAMPL1 0x48 -#define AX5043_REG_TRKAMPL0 0x49 -#define AX5043_REG_TRKPHASE1 0x4A -#define AX5043_REG_TRKPHASE0 0x4B -#define AX5043_REG_TRKRFFREQ2 0x4D -#define AX5043_REG_TRKRFFREQ1 0x4E -#define AX5043_REG_TRKRFFREQ0 0x4F -#define AX5043_REG_TRKFREQ1 0x50 -#define AX5043_REG_TRKFREQ0 0x51 -#define AX5043_REG_TRKFSKDEMOD1 0x52 -#define AX5043_REG_TRKFSKDEMOD0 0x53 - -/* Timers */ -#define AX5043_REG_TIMER2 0x59 -#define AX5043_REG_TIMER1 0x5A -#define AX5043_REG_TIMER0 0x5B - -/* Wakeup timer */ -#define AX5043_REG_WAKEUPTIMER1 0x68 -#define AX5043_REG_WAKEUPTIMER0 0x69 -#define AX5043_REG_WAKEUP1 0x6A -#define AX5043_REG_WAKEUP0 0x6B -#define AX5043_REG_WAKEUPFREQ1 0x6C -#define AX5043_REG_WAKEUPFREQ0 0x6D -#define AX5043_REG_WAKEUPXOEARLY 0x6E - -/* PHY related registers*/ -#define AX5043_REG_IFFREQ1 0x100 -#define AX5043_REG_IFFREQ0 0x101 -#define AX5043_REG_DECIMATION 0x102 -#define AX5043_REG_RXDATARATE2 0x103 -#define AX5043_REG_RXDATARATE1 0x104 -#define AX5043_REG_RXDATARATE0 0x105 -#define AX5043_REG_MAXDROFFSET2 0x106 -#define AX5043_REG_MAXDROFFSET1 0x107 -#define AX5043_REG_MAXDROFFSET0 0x108 -#define AX5043_REG_MAXRFOFFSET2 0x109 -#define AX5043_REG_MAXRFOFFSET1 0x10A -#define AX5043_REG_MAXRFOFFSET0 0x10B -#define AX5043_REG_FSKDMAX1 0x10C -#define AX5043_REG_FSKDMAX0 0x10D -#define AX5043_REG_FSKDMIN1 0x10E -#define AX5043_REG_FSKDMIN0 0x10F -#define AX5043_REG_AFSKSPACE1 0x110 -#define AX5043_REG_AFSKSPACE0 0x111 -#define AX5043_REG_AFSKMARK1 0x112 -#define AX5043_REG_AFSKMARK0 0x113 -#define AX5043_REG_AFSKCTRL 0x114 -#define AX5043_REG_AMPLFILTER 0x115 -#define AX5043_REG_FREQUENCYLEAK 0x116 -#define AX5043_REG_RXPARAMSETS 0x117 -#define AX5043_REG_RXPARAMCURSET 0x118 - -/* Receiver Parameter Set 0 */ -#define AX5043_REG_AGCGAIN0 0x120 -#define AX5043_REG_AGCTARGET0 0x121 -#define AX5043_REG_AGCAHYST0 0x122 -#define AX5043_REG_AGCMINMAX0 0x123 -#define AX5043_REG_TIMEGAIN0 0x124 -#define AX5043_REG_DRGAIN0 0x125 -#define AX5043_REG_PHASEGAIN0 0x126 -#define AX5043_REG_FREQUENCYGAINA0 0x127 -#define AX5043_REG_FREQUENCYGAINB0 0x128 -#define AX5043_REG_FREQUENCYGAINC0 0x129 -#define AX5043_REG_FREQUENCYGAIND0 0x12A -#define AX5043_REG_AMPLITUDEGAIN0 0x12B -#define AX5043_REG_FREQDEV10 0x12C -#define AX5043_REG_FREQDEV00 0x12D -#define AX5043_REG_FOURFSK0 0x12E -#define AX5043_REG_BBOFFSRES0 0x12F - -/* Receiver Parameter Set 1 */ -#define AX5043_REG_AGCGAIN1 0x130 -#define AX5043_REG_AGCTARGET1 0x131 -#define AX5043_REG_AGCAHYST1 0x132 -#define AX5043_REG_AGCMINMAX1 0x133 -#define AX5043_REG_TIMEGAIN1 0x134 -#define AX5043_REG_DRGAIN1 0x135 -#define AX5043_REG_PHASEGAIN1 0x136 -#define AX5043_REG_FREQUENCYGAINA1 0x137 -#define AX5043_REG_FREQUENCYGAINB1 0x138 -#define AX5043_REG_FREQUENCYGAINC1 0x139 -#define AX5043_REG_FREQUENCYGAIND1 0x13A -#define AX5043_REG_AMPLITUDEGAIN1 0x13B -#define AX5043_REG_FREQDEV11 0x13C -#define AX5043_REG_FREQDEV01 0x13D -#define AX5043_REG_FOURFSK1 0x13E -#define AX5043_REG_BBOFFSRES1 0x13F - -/* Receiver Parameter Set 2 */ -#define AX5043_REG_AGCGAIN2 0x140 -#define AX5043_REG_AGCTARGET2 0x141 -#define AX5043_REG_AGCAHYST2 0x142 -#define AX5043_REG_AGCMINMAX2 0x143 -#define AX5043_REG_TIMEGAIN2 0x144 -#define AX5043_REG_DRGAIN2 0x145 -#define AX5043_REG_PHASEGAIN2 0x146 -#define AX5043_REG_FREQGAINA2 0x147 -#define AX5043_REG_FREQGAINB2 0x148 -#define AX5043_REG_FREQGAINC2 0x149 -#define AX5043_REG_FREQGAIND2 0x14A -#define AX5043_REG_AMPLGAIN2 0x14B -#define AX5043_REG_FREQDEV12 0x14C -#define AX5043_REG_FREQDEV02 0x14D -#define AX5043_REG_FOURFSK2 0x14E -#define AX5043_REG_BBOFFSRES2 0x14F - -/* Receiver Parameter Set 3 */ -#define AX5043_REG_AGCGAIN3 0x150 -#define AX5043_REG_AGCTARGET3 0x151 -#define AX5043_REG_AGCAHYST3 0x152 -#define AX5043_REG_AGCMINMAX3 0x153 -#define AX5043_REG_TIMEGAIN3 0x154 -#define AX5043_REG_DRGAIN3 0x155 -#define AX5043_REG_PHASEGAIN3 0x156 -#define AX5043_REG_FREQUENCYGAINA3 0x157 -#define AX5043_REG_FREQUENCYGAINB3 0x158 -#define AX5043_REG_FREQUENCYGAINC3 0x159 -#define AX5043_REG_FREQUENCYGAIND3 0x15A -#define AX5043_REG_AMPLITUDEGAIN3 0x15B -#define AX5043_REG_FREQDEV13 0x15C -#define AX5043_REG_FREQDEV03 0x15D -#define AX5043_REG_FOURFSK3 0x15E -#define AX5043_REG_BBOFFSRES3 0x15F - -/* Transmitter Parameters */ -#define AX5043_REG_MODCFGF 0x160 -#define AX5043_REG_FSKDEV2 0x161 -#define AX5043_REG_FSKDEV1 0x162 -#define AX5043_REG_FSKDEV0 0x163 -#define AX5043_REG_MODCFGA 0x164 -#define AX5043_REG_TXRATE2 0x165 -#define AX5043_REG_TXRATE1 0x166 -#define AX5043_REG_TXRATE0 0x167 -#define AX5043_REG_TXPWRCOEFFA1 0x168 -#define AX5043_REG_TXPWRCOEFFA0 0x169 -#define AX5043_REG_TXPWRCOEFFB1 0x16A -#define AX5043_REG_TXPWRCOEFFB0 0x16B -#define AX5043_REG_TXPWRCOEFFC1 0x16C -#define AX5043_REG_TXPWRCOEFFC0 0x16D -#define AX5043_REG_TXPWRCOEFFD1 0x16E -#define AX5043_REG_TXPWRCOEFFD0 0x16F -#define AX5043_REG_TXPWRCOEFFE1 0x170 -#define AX5043_REG_TXPWRCOEFFE0 0x171 - -/* PLL parameters */ -#define AX5043_REG_PLLVCOI 0x180 -#define AX5043_REG_PLLVCOIR 0x181 -#define AX5043_REG_PLLLOCKDET 0x182 -#define AX5043_REG_PLLRNGCLK 0x183 - -/* Crystal Oscillator */ -#define AX5043_REG_XTALCAP 0x184 - -/* Baseband */ -#define AX5043_REG_BBTUNE 0x188 -#define AX5043_REG_BBOFFSCAP 0x189 - -/* Packet Format */ -#define AX5043_REG_PKTADDRCFG 0x200 -#define AX5043_REG_PKTLENCFG 0x201 -#define AX5043_REG_PKTLENOFFSET 0x202 -#define AX5043_REG_PKTMAXLEN 0x203 -#define AX5043_REG_PKTADDR3 0x204 -#define AX5043_REG_PKTADDR2 0x205 -#define AX5043_REG_PKTADDR1 0x206 -#define AX5043_REG_PKTADDR0 0x207 -#define AX5043_REG_PKTADDRMASK3 0x208 -#define AX5043_REG_PKTADDRMASK2 0x209 -#define AX5043_REG_PKTADDRMASK1 0x20A -#define AX5043_REG_PKTADDRMASK0 0x20B - -/* Pattern Match */ -#define AX5043_REG_MATCH0PAT3 0x210 -#define AX5043_REG_MATCH0PAT2 0x211 -#define AX5043_REG_MATCH0PAT1 0x212 -#define AX5043_REG_MATCH0PAT0 0x213 -#define AX5043_REG_MATCH0LEN 0x214 -#define AX5043_REG_MATCH0MIN 0x215 -#define AX5043_REG_MATCH0MAX 0x216 -#define AX5043_REG_MATCH1PAT1 0x218 -#define AX5043_REG_MATCH1PAT0 0x219 -#define AX5043_REG_MATCH1LEN 0x21C -#define AX5043_REG_MATCH1MIN 0x21D -#define AX5043_REG_MATCH1MAX 0x21E - -/* Packet Controller */ -#define AX5043_REG_TMGTXBOOST 0x220 -#define AX5043_REG_TMGTXSETTLE 0x221 -#define AX5043_REG_TMGRXBOOST 0x223 -#define AX5043_REG_TMGRXSETTLE 0x224 -#define AX5043_REG_TMGRXOFFSACQ 0x225 -#define AX5043_REG_TMGRXCOARSEAGC 0x226 -#define AX5043_REG_TMGRXAGC 0x227 -#define AX5043_REG_TMGRXRSSI 0x228 -#define AX5043_REG_TMGRXPREAMBLE1 0x229 -#define AX5043_REG_TMGRXPREAMBLE2 0x22A -#define AX5043_REG_TMGRXPREAMBLE3 0x22B -#define AX5043_REG_RSSIREFERENCE 0x22C -#define AX5043_REG_RSSIABSTHR 0x22D -#define AX5043_REG_BGNDRSSIGAIN 0x22E -#define AX5043_REG_BGNDRSSITHR 0x22F -#define AX5043_REG_PKTCHUNKSIZE 0x230 -#define AX5043_REG_PKTMISCFLAGS 0x231 -#define AX5043_REG_PKTSTOREFLAGS 0x232 -#define AX5043_REG_PKTACCEPTFLAGS 0x233 - -/* General Purpose ADC */ -#define AX5043_REG_GPADCCTRL 0x300 -#define AX5043_REG_GPADCPERIOD 0x301 -#define AX5043_REG_GPADC13VALUE1 0x308 -#define AX5043_REG_GPADC13VALUE0 0x309 - -/* Low Power Oscillator Calibration */ -#define AX5043_REG_LPOSCCONFIG 0x310 -#define AX5043_REG_LPOSCSTATUS 0x311 -#define AX5043_REG_LPOSCKFILT1 0x312 -#define AX5043_REG_LPOSCKFILT0 0x313 -#define AX5043_REG_LPOSCREF1 0x314 -#define AX5043_REG_LPOSCREF0 0x315 -#define AX5043_REG_LPOSCFREQ1 0x316 -#define AX5043_REG_LPOSCFREQ0 0x317 -#define AX5043_REG_LPOSCPER1 0x318 -#define AX5043_REG_LPOSCPER0 0x319 - -/* DAC */ -#define AX5043_REG_DACVALUE1 0x330 -#define AX5043_REG_DACVALUE0 0x331 -#define AX5043_REG_DACCONFIG 0x332 - -/* Performance Tuning Registers */ -#define AX5043_REG_REF 0xF00 -#define AX5043_REG_0xF00 0xF00 -#define AX5043_REG_0xF0C 0xF0C -#define AX5043_REG_0xF0D 0xF0D -#define AX5043_REG_XTALOSC 0xF10 -#define AX5043_REG_XTALAMPL 0xF11 -#define AX5043_REG_0xF1C 0xF1C -#define AX5043_REG_0xF18 0xF18 -#define AX5043_REG_0xF21 0xF21 -#define AX5043_REG_0xF22 0xF22 -#define AX5043_REG_0xF23 0xF23 -#define AX5043_REG_0xF26 0xF26 -#define AX5043_REG_0xF30 0xF30 -#define AX5043_REG_0xF31 0xF31 -#define AX5043_REG_0xF32 0xF32 -#define AX5043_REG_0xF33 0xF33 -#define AX5043_REG_0xF34 0xF34 -#define AX5043_REG_0xF35 0xF35 -#define AX5043_REG_0xF44 0xF44 -#define AX5043_REG_0xF72 0xF72 -#define AX5043_REG_XTALDIV 0xF35 - -/* TODO: Clean up from here to Driver pre-compile time settings. */ -/* Not a real register. Indicator of end of registers.*/ -#define AX5043_REG_END 0xFFF -/** @} */ - -/** - * @name AX5043 Register and bit values - * - */ -/* Power modes */ -#define AX5043_RESET_BIT (1 << 7) -#define AX5043_OSC_EN_BIT (1 << 6) -#define AX5043_REF_EN_BIT (1 << 5) - -#define AX5043_POWERDOWN 0x0 -#define AX5043_DEEPSLEEP 0x1 -#define AX5043_STANDBY 0x5 -#define AX5043_FIFO_ENABLED 0x7 -#define AX5043_SYNTH_RX 0x8 -#define AX5043_FULL_RX 0x9 -#define AX5043_WOR_RX 0xB -#define AX5043_SYNTH_TX 0xC -#define AX5043_FULL_TX 0xD - -/** - * @name AX5043 FIFO Commands - * - */ -#define AX5043_FIFOCMD_NOP 0x00 -#define AX5043_FIFOCMD_DATA 0x01 -#define AX5043_FIFOCMD_REPEATDATA 0x02 -#define AX5043_FIFOCMD_TIMER 0x10 -#define AX5043_FIFOCMD_RSSI 0x11 -#define AX5043_FIFOCMD_FREQOFFS 0x12 -#define AX5043_FIFOCMD_RFFREQOFFS 0x13 -#define AX5043_FIFOCMD_DATARATE 0x14 -#define AX5043_FIFOCMD_ANTRSSI 0x15 -#define AX5043_FIFOCMD_TXCTRL 0x1C -#define AX5043_FIFOCMD_TXPWR 0x1D - -/** - * @brief FIFO commit command - */ -#define AX5043_FIFO_COMMIT_CMD (1 << 2) -#define AX5043_FIFO_PKTSTART 1 -#define AX5043_FIFO_PKTEND (1 << 1) -#define AX5043_FIFO_NOCRC (1 << 3) -#define AX5043_FIFO_RAW (1 << 4) - -#define PKTDATA_BUFLEN 260 - -/** - * @brief Error codes - */ -#define AXRADIO_ERR_NOERROR 0x00 -#define AXRADIO_ERR_NOTSUPPORTED 0x01 -#define AXRADIO_ERR_BUSY 0x02 -#define AXRADIO_ERR_TIMEOUT 0x03 -#define AXRADIO_ERR_INVALID 0x04 -#define AXRADIO_ERR_NOCHIP 0x05 -#define AXRADIO_ERR_RANGING 0x06 -#define AXRADIO_ERR_LOCKLOST 0x07 -#define AXRADIO_ERR_RETRANSMISSION 0x08 -#define AXRADIO_ERR_RESYNC 0x09 -#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a -#define AXRADIO_ERR_RECEIVESTART 0x0b -#define AXRADIO_ERR_FIFO_CHUNK 0x0c -#define AXRADIO_ERR_FIFO_CMD 0x0d -#define AXRADIO_ERR_UNEXPECTED_STATE 0x0e -#define AXRADIO_ERR_NOT_CONNECTED 0x0f -#define AXRADIO_ERR_REG_NOT_IN_CONF 0x10 -#define AXRADIO_ERR_VAL_NOT_IN_CONF 0x11 -#define AXRADIO_ERR_PLLRNG_VAL 0x12 - -/** - * @brief PHY and Framing details - */ -#define AXRADIO_PHY_PN9 0 -#define AXRADIO_PHY_NRCHANNELS 1 -#define AXRADIO_PHY_CHANFREQ 2 -#define AXRADIO_PHY_CHANPLLRNGINIT 3 -#define AXRADIO_PHY_CHANVCOIINIT 4 -#define AXRADIO_PHY_CHANPLLRNG 5 -#define AXRADIO_PHY_CHANVCOI 6 -#define AXRADIO_PHY_VCOCALIB 7 -#define AXRADIO_PHY_MAXFREQOFFSET 8 -#define AXRADIO_PHY_RSSIOFFSET 9 -#define AXRADIO_PHY_RSSIREFERENCE 10 -#define AXRADIO_PHY_CHANNELBUSY 11 -#define AXRADIO_PHY_CS_PERIOD 12 -#define AXRADIO_PHY_CS_ENABLED 13 -#define AXRADIO_PHY_LBT_RETRIES 14 -#define AXRADIO_PHY_LBT_FORCETX 15 -#define AXRADIO_PHY_PREAMBLE_WOR_LONGLEN 16 -#define AXRADIO_PHY_PREAMBLE_WOR_LEN 17 -#define AXRADIO_PHY_PREAMBLE_LONGLEN 18 -#define AXRADIO_PHY_PREAMBLE_LEN 19 -#define AXRADIO_PHY_PREAMBLE_BYTE 20 -#define AXRADIO_PHY_PREAMBLE_FLAGS 21 -#define AXRADIO_PHY_PREAMBLE_APPENDBITS 22 -#define AXRADIO_PHY_PREAMBLE_APPENDPATTERN 23 -#define AXRADIO_FRAMING_MACLEN 24 -#define AXRADIO_FRAMING_ADDRLEN 25 -#define AXRADIO_FRAMING_DESTADDRPOS 26 -#define AXRADIO_FRAMING_SOURCEADDRPOS 27 -#define AXRADIO_FRAMING_LENPOS 28 -#define AXRADIO_FRAMING_LENOFFS 29 -#define AXRADIO_FRAMING_LENMASK 30 -#define AXRADIO_FRAMING_SWCRCLEN 31 -#define AXRADIO_FRAMING_SYNCLEN 32 -#define AXRADIO_FRAMING_SYNCWORD0 33 -#define AXRADIO_FRAMING_SYNCWORD1 34 -#define AXRADIO_FRAMING_SYNCWORD2 35 -#define AXRADIO_FRAMING_SYNCWORD3 36 -#define AXRADIO_FRAMING_SYNCFLAGS 37 -#define AXRADIO_FRAMING_ENABLE_SFDCALLBACK 38 -#define AXRADIO_FRAMING_ACK_TIMEOUT 39 -#define AXRADIO_FRAMING_ACK_DELAY 40 -#define AXRADIO_FRAMING_ACK_RETRANSMISSIONS 41 -#define AXRADIO_FRAMING_ACK_SEQNRPOS 42 -#define AXRADIO_FRAMING_MINPAYLOADLEN 43 -#define AXRADIO_WOR_PERIOD 44 -#define AXRADIO_PHY_INNERFREQLOOP 45 -#define AXRADIO_PHY_END 200 - -#define SPACE " " - - -/* END TODO */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief AX5043 SPI interface switch. - * @details If set to @p TRUE the support for SPI is included. - * @note The default is @p TRUE. - */ -#if !defined(AX5043_USE_SPI) || defined(__DOXYGEN__) -#define AX5043_USE_SPI TRUE -#endif - -/** - * @brief AX5043 shared SPI switch. - * @details If set to @p TRUE the device acquires SPI bus ownership - * on each transaction. - * @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION. - */ -#if !defined(AX5043_SHARED_SPI) || defined(__DOXYGEN__) -#define AX5043_SHARED_SPI FALSE -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if AX5043_USE_SPI && !HAL_USE_SPI -#error "AX5043_USE_SPI requires HAL_USE_SPI" -#endif - -#if AX5043_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION -#error "AX5043_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name AX5043 data structures and types. - * @{ - */ -/** - * @brief Structure representing a AX5043 driver. - */ -typedef struct AX5043Driver AX5043Driver; - -/** - * @brief AX5043 registers are gouped together based on this - */ -typedef enum { - common, - tx, - rx, - rx_cont, - local_address -} ax5043_reg_group_t; - -/** - * @brief Structure containing a four byte sender X.25 address - */ -struct axradio_address { - uint8_t addr[4]; -}; - -/** - * @brief Ax5043 Register values - */ -typedef struct { - uint16_t reg; - uint8_t val; - ax5043_reg_group_t group; -} ax5043_regval_t; - -/** - * @brief Other configuration values - */ -typedef struct { - uint8_t conf_name; - uint32_t val; -} ax5043_confval_t; - -/** - * @brief Other configuration values - */ -typedef enum { - AX5043_MODE_RX, - AX5043_MODE_TX, - AX5043_MODE_CW, - AX5043_MODE_OFF, -} ax5043_mode_t; -/** - * @brief Driver state machine possible states. - */ -typedef enum { - AX5043_UNINIT, /**< Not initialized. */ - AX5043_STOP, /**< Stopped. */ - AX5043_READY, /**< Ready. */ - AX5043_BUSY, /**< Busy. */ - AX5043_IDLE, /**< Idle. */ - AX5043_RX, - AX5043_RX_LOOP, /**< In the middle of receiving packet.*/ - AX5043_TX, - AX5043_PLL_RANGE_DONE, - AX5043_OFF, - AX5043_TX_LONGPREAMBLE, - AX5043_TX_SHORTPREAMBLE, - AX5043_TX_PACKET, - AX5043_CW -} ax5043_state_t; - -/** - * @brief AX5043 configuration structure. - */ -typedef struct{ -#if (AX5043_USE_SPI) || defined(__DOXYGEN__) - /** - * @brief SPI driver associated with this AX5043. - */ - SPIDriver *spip; - /** - * @brief SPI configuration associated with this AX5043. - */ - const SPIConfig *spicfg; -#endif /* AX5043_USE_SPI */ - ioline_t irq; - ax5043_regval_t *reg_values; - ax5043_confval_t *conf_values; - ax5043_mode_t ax5043_mode; - /* TODO: probably move these to an implementation of the driver */ - mailbox_t *mb; -} AX5043Config; - -/** - * @brief @p AX5043 specific methods. - */ -#define _ax5043_methods_alone - -/** - * @brief @p AX5043 specific methods with inherited ones. - */ -#define _ax5043_methods \ - _base_object_methods - -/** - * @extends BaseObjectVMT - * - * @brief @p AX5043 virtual methods table. - */ -struct AX5043VMT { - _ax5043_methods -}; - -/** - * @brief @p AX5043Driver specific data. - */ -#define _ax5043_data \ - _base_object_data \ - /* Driver state.*/ \ - ax5043_state_t state; \ - /* Current configuration data.*/ \ - const AX5043Config *config; \ - /* Ax5043 returned values.*/ \ - uint8_t rf_freq_off1; \ - uint8_t rf_freq_off2; \ - uint8_t rf_freq_off3; \ - uint8_t rssi; \ - uint8_t dropped[250]; \ - uint8_t error_code; \ - uint8_t status_code; \ - -/** - * @brief AX5043 Radio class. - */ -struct AX5043Driver { - /** @brief Virtual Methods Table.*/ - const struct AX5043VMT *vmt; - _ax5043_data -}; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif -void ax5043ObjectInit(AX5043Driver *devp); -void ax5043Start(AX5043Driver *devp, const AX5043Config *config); -void ax5043Stop(AX5043Driver *devp); - -uint8_t ax5043_set_regs_group(AX5043Driver *devp, ax5043_reg_group_t group); -uint8_t ax5043_get_reg_val(AX5043Driver *devp, uint16_t reg_name); -uint32_t ax5043_get_conf_val(AX5043Driver *devp, uint8_t conf_name); -uint8_t ax5043_set_conf_val(AX5043Driver *devp, uint8_t conf_name, uint32_t value); -void ax5043_prepare_tx(AX5043Driver *devp); -void ax5043_prepare_rx(AX5043Driver *devp); -void ax5043_init_registers_common(AX5043Driver *devp); -uint8_t axradio_get_pllvcoi(AX5043Driver *devp); -void ax5043_init(AX5043Driver *devp); -void transmit_loop(AX5043Driver *devp, uint16_t axradio_txbuffer_len,uint8_t axradio_txbuffer[]); -uint8_t transmit_packet(AX5043Driver *devp, const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen); -uint8_t receive_loop(AX5043Driver *devp, uint8_t axradio_rxbuffer[]); - -/* TODO: Abstract these out? */ -void ax5043_morse_dot_dash(AX5043Driver *devp, uint16_t dot_dash_time); -const char *ax5043_ascii_to_morse(char letter); -void ax5043_send_cw(AX5043Driver *devp, int wpm, char beaconMessage[], uint16_t pktlen ); - -#ifdef __cplusplus -} -#endif - -#endif /* _AX5043_H_ */ - -/** @} */ diff --git a/src/archive/app_si41xx/.gitignore b/src/archive/app_si41xx/.gitignore deleted file mode 100644 index 9bf3746b..00000000 --- a/src/archive/app_si41xx/.gitignore +++ /dev/null @@ -1 +0,0 @@ -compile_commands.json diff --git a/src/archive/app_si41xx/Makefile b/src/archive/app_si41xx/Makefile deleted file mode 100644 index aa3f5e89..00000000 --- a/src/archive/app_si41xx/Makefile +++ /dev/null @@ -1,238 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO) -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = APP_SI41XX - -# Define board here -BOARD = ST_NUCLEO64_F446RE - -#Project sources -PROJ_ROOT = ../../.. -APP_ROOT = . - -# Imported source files and paths -CHIBIOS = $(PROJ_ROOT)/ChibiOS -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -#Board specific directories -CONFDIR = conf -BUILDDIR = $(APP_ROOT)/build -DEPDIR = $(APP_ROOT)/.dep -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files -include $(PROJ_SRC)/common.mk -#shell files -include $(CHIBIOS)/os/various/shell/shell.mk -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(ALLASMSRC) -ASMXSRC = $(ALLXASMSRC) - -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra -Wundef - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# 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registers,Usage: rf2 - if: Update IF registers,Usage: ifr - help: provides list of commands - ?: provides list of commands diff --git a/src/archive/app_si41xx/Si4133-notes.txt b/src/archive/app_si41xx/Si4133-notes.txt deleted file mode 100644 index 4ef17320..00000000 --- a/src/archive/app_si41xx/Si4133-notes.txt +++ /dev/null @@ -1,85 +0,0 @@ -Registers and Functionality for Si4133 family - - -Part RF1 RF2 IF ---------------------- -Si4133 X X X -Si4123 X - X -Si4122 - X X -Si4113 X X - -Si4112 - - X - - -SUMMARY OF DEFAULT VALUES FOR Si4123: -Reg # 17 0 Addr Notes --------------------------------------------------------- -0 00 0011 0000 0000 0100 0000 Main config -1 00 0000 0000 0000 0000 0001 P.D. Gain -2 00 0000 0000 0000 0011 0010 Enable outputs -3 00 0000 1001 1110 0010 0011 N for RF1 (2530) -4 00 0000 0000 0000 0000 0100 N for RF2 (0) -5 00 0000 0011 0110 1001 0101 N for IF (873) -6 00 0000 0000 0010 0000 0110 R for RF1 (32) -7 00 0000 0000 0000 0000 0111 R for RF2 (0) -8 00 0000 0000 0010 0000 1000 R for IF (32) --------------------------------------------------------- - -FYI: EXTERNAL OSC REFERENCE = 16.000 MHz - -NOTES FOR DEFAULTS: -- AUXSEL set to lock detect -- IFDIV disabled -- LPWR disabled -- AUTOPDB disabled -- AutoKp enabled -- Registers 4 and 7 for RF2 are not needed for Si4123 -- For synthesizers with RF1 and RF2 included, the selected - output is determined by the last N/R reg written. - - -REQUESTED FUNCTIONALITY: -- Breakout specific main parameter bits with defaults. - See p. 21 from datasheet for concatenation/padding. - RFPWR (1) = 0 (not used) - AUTOKP (1) = 1 (enabled) - AUTOPDB (1) = 0 (disabled) - LPWR (1) = 0 (disabled) - IFDIV (2) = 00 (no divide) - AUXSEL (2) = 11 (lock detect) - KP1 (2) = 00 (not used when AUTOKP) - KP2 (2) = 00 (not used when AUTOKP) - KPI (2) = 00 (not used when AUTOKP) - PDRB (1) = 1 (enable RF output) - PDIB (1) = 1 (enable IF output) -- Breakout specific N and R parameter bits with defaults. - See p. 21 from datasheet for concatenation/padding. - These are evaluated defaults using equations below. - NRF1 (18) = 000000100111100010 (2530) - NRF2 (17) = 000000000000000000 (0) - NIF (16) = 0000001101101001 (873) - RRF1 (13) = 0000000100000 (32) - RRF2 (13) = 0000000000000 (0) - RIF (13) = 0000000100000 (32) -- Non-register related variables with defaults (decimal values) - Note: Fouts in MHz and Pdets in kHz. - FREF (int) = 16 - FOUTRF1 (float) = 1265 - FOUTRF2 (float) = 0 - FOUTIF (float) = 436.5 - PDETRF1 (int) = 500 - PDETRF2 (int) = 0 - PDETIF (int) = 500 -- Equations for N and R: - RRF1 = FREF * 1000 / PDETRF1 - RRF2 = FREF * 1000 / PDETRF2 - RIF = FREF * 1000 / PDETIF - NRF1 = FOUTRF1 * RRF1 / FREF - NRF2 = FOUTRF2 * RRF2 / FREF - NIF = FOUTIF * RIF / FREF -- Equation Notes: - - Calculate N values only if phase detector not changed - - Calculate R first and N second if phase detector changed -- Evaluated Defaults: - - RF1 output = 1265 MHz - - RF2 output = disabled - - IF output = 436.5 MHz diff --git a/src/archive/app_si41xx/conf/chconf.h b/src/archive/app_si41xx/conf/chconf.h deleted file mode 100644 index a1b8adb8..00000000 --- a/src/archive/app_si41xx/conf/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_si41xx/conf/halconf.h b/src/archive/app_si41xx/conf/halconf.h deleted file mode 100644 index 66155382..00000000 --- a/src/archive/app_si41xx/conf/halconf.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_6_0_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the QSPI subsystem. - */ -#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) -#define HAL_USE_QSPI FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* QSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_WAIT) || defined(__DOXYGEN__) -#define QSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(QSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define QSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_si41xx/conf/mcuconf.h b/src/archive/app_si41xx/conf/mcuconf.h deleted file mode 100644 index ea2031f0..00000000 --- a/src/archive/app_si41xx/conf/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_si41xx/main.c b/src/archive/app_si41xx/main.c deleted file mode 100644 index 9592c18b..00000000 --- a/src/archive/app_si41xx/main.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/******************************************************************** - * Modification Log - * 09/05/2019 Malay Das Initial Code. - * 09/12/2019 Malay Das Added user entry via chibios shell. - ********************************************************************/ - - -/* - * Include Files - */ -#include -#include -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" -#include "util_version.h" -#include "util_numbers.h" -#include "shell.h" - -#include "si41xx.h" - - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - - -/* - * Serial Driver Configuration - */ -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - - - -/* - * Initialize the SPI drivers and configure the ax5043 chips - */ -static void app_init(void) -{ - // Start up debug output, chprintf(DEBUG_CHP,...) - sdStart(&DEBUG_SERIAL, &ser_cfg); - set_util_fwversion(&version_info); - set_util_hwversion(&version_info); - - - //Print FW/HW information - chprintf(DEBUG_CHP, "\r\nFirmware Info\r\n"); - chprintf(DEBUG_CHP, "FW HASH: %s\r\n", version_info.firmware); - chprintf(DEBUG_CHP, "STF0x UNIQUE HW ID (H,C,L):\r\n0x%x\t0x%x\t0x%x\r\n" - , version_info.hardware.id_high - , version_info.hardware.id_center - , version_info.hardware.id_low - ); - -} - - -/* - *This function bit bangs the si41xx registers with default values. - *The dafult values are set as - * RF1 output = 1265 MHz - * RF2 output = disabled - * IF output = 436.5 MHz - *The following pins are connected between M4 and si41xx chip - *LINE_SI_SCLK PAL_LINE(GPIOC, 2U) - *LINE_SI_SDATA PAL_LINE(GPIOC, 3U) - *LINE_SI_SENB PAL_LINE(GPIOC, 4U) - */ - -static void si41xx_init(void) -{ - - palSetLine(LINE_SI_SENB); - palSetLine(LINE_SI_SDATA); - palSetLine(LINE_SI_SCLK); - - si_write_reg(SI41XX_REG_MAIN_CONFIG, 0b000011000000000100); - si_write_reg(SI41XX_REG_PHASE_GAIN, 0b000000000000000000); - si_write_reg(SI41XX_REG_PWRDOWN, 0b000000000000000000); - - // RF1 and IF default for 1265 / 436.5 MHz w/ 500 kHz - si_write_reg(SI41XX_REG_RF1_NDIV, 0b000000100111100010); - si_write_reg(SI41XX_REG_RF1_RDIV, 0b000000000000100000); - si_write_reg(SI41XX_REG_IF_NDIV, 0b000000001101101001); - si_write_reg(SI41XX_REG_IF_RDIV, 0b000000000000100000); - si_write_reg(SI41XX_REG_PWRDOWN, 0b000000000000000011); - - // IF default for 808 MHz w/ 500 kHz - // si_write_reg(SI41XX_REG_IF_NDIV, 0b000000011001010000); - // si_write_reg(SI41XX_REG_IF_RDIV, 0b000000000000100000); - // si_write_reg(SI41XX_REG_PWRDOWN, 0b000000000000000010); - - palSetLine(LINE_SI_SENB); - palSetLine(LINE_SI_SDATA); - palSetLine(LINE_SI_SCLK); - -} - - -/* - * The main loop. - * Currently it does not have any utility. It keeps waiting. - */ -static void main_loop(void) -{ - - while (true) - { - chThdSleepMilliseconds(15000); - } - -} - - -/* - * shell commands for user entry. - * This lets the user update any register via the chibios shell. - * Requires register address and register value as entry. - */ -static void reg(BaseSequentialStream *sd, int argc, char *argv[]) { - - uint32_t reg_address; - uint32_t reg_value; - - if (argc < 2) { - chprintf(sd, "Usage: reg \r\n"); - chprintf(sd, "Example: reg 2 12\r\n"); - chprintf(sd, " reg 2 0xCA\r\n"); - chprintf(sd, " reg 2 0b10\r\n"); - } - - reg_address = strtoul(argv[0], NULL, 0); - reg_value = strtoul((argv[1][0] == '0' && argv[1][1] == 'b') ? argv[1]+2: argv[1], NULL, (argv[1][0] == '0' && argv[1][1] == 'b') ? 2 : 0); - - si_write_reg(reg_address, reg_value); - chprintf(sd, "INFO: Updated register %d with value 0x%x.\r\n", reg_address, reg_value); -} - - -/* - * shell commands for user entry - * This lets the user update RF1 registers via the chibios shell - * Requires frequency and phase values in KHz. - */ -static void rf1(BaseSequentialStream *sd, int argc, char *argv[]) { - - uint32_t freq; - uint32_t phase; - uint32_t ndiv; - uint32_t rdiv; - - if (argc < 2) { - chprintf(sd, "Usage: rf1 \r\n"); - return; - } - - freq = strtoul(argv[0], NULL, 10); - phase = strtoul(argv[1], NULL, 10); - - if (freq == 0) { - chprintf(sd, "ERROR: freqency cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - if (phase == 0) { - chprintf(sd, "ERROR: phase value cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - rdiv = SI41XX_FREF * 1000/phase; - ndiv = freq * rdiv / (1000*SI41XX_FREF); - - si_write_reg(SI41XX_REG_RF1_NDIV, ndiv); - si_write_reg(SI41XX_REG_RF1_RDIV, rdiv); - - chprintf(sd, "INFO: freqency set at %d Khz, phase set at %d Khz.\r\n", freq, phase); -} - - -/* - * shell commands for user entry - * This lets the user update RF2 registers via the chibios shell - * Requires frequency and phase values in KHz. This should not be used for si4123 - */ -static void rf2(BaseSequentialStream *sd, int argc, char *argv[]) { - - uint32_t freq; - uint32_t phase; - uint32_t ndiv; - uint32_t rdiv; - - if (argc < 2) { - chprintf(sd, "Usage: rf1 \r\n"); - return; - } - - freq = strtoul(argv[0], NULL, 10); - phase = strtoul(argv[1], NULL, 10); - - if (freq == 0) { - chprintf(sd, "ERROR: freqency cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - if (phase == 0) { - chprintf(sd, "ERROR: phase value cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - rdiv = SI41XX_FREF * 1000/phase; - ndiv = freq * rdiv / (1000*SI41XX_FREF); - - si_write_reg(SI41XX_REG_RF2_NDIV, ndiv); - si_write_reg(SI41XX_REG_RF2_RDIV, rdiv); - - chprintf(sd, "INFO: freqency set at %d Khz, phase set at %d Khz.\r\n", freq, phase); -} - - -/* - * shell commands for user entry - * This lets the user update IF registers via the chibios shell - * Requires frequency and phase values in KHz. - */ -static void ifr(BaseSequentialStream *sd, int argc, char *argv[]) { - - uint32_t freq; - uint32_t phase; - uint32_t ndiv; - uint32_t rdiv; - - if (argc < 2) { - chprintf(sd, "Usage: rf1 \r\n"); - return; - } - - freq = strtoul(argv[0], NULL, 10); - phase = strtoul(argv[1], NULL, 10); - - if (freq == 0) { - chprintf(sd, "ERROR: freqency cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - if (phase == 0) { - chprintf(sd, "ERROR: phase value cannot be 0. \r\nUsage: rf1 \r\n"); - return; - } - rdiv = SI41XX_FREF * 1000/phase; - ndiv = freq * rdiv / (1000*SI41XX_FREF); - - si_write_reg(SI41XX_REG_IF_NDIV, ndiv); - si_write_reg(SI41XX_REG_IF_RDIV, rdiv); - - chprintf(sd, "INFO: freqency set at %d Khz, phase set at %d Khz.\r\n", freq, phase); -} - - -/* - * shell commands for user entry - * Provides a list of comamnds and their description to Chibios shell user. - */ -static void si_help(BaseSequentialStream *sd, int argc, char *argv[]) { - - (void) argc; - (void) argv; - - chprintf(sd, "Available commands:\r\n"); - chprintf(sd, " reg: Update registers,Usage reg \r\n"); - chprintf(sd, " rf1: Update RF1 registers,Usage: rf1 \r\n"); - chprintf(sd, " rf2: Update RF2 registers,Usage: rf2 \r\n"); - chprintf(sd, " if: Update IF registers,Usage: ifr \r\n"); - chprintf(sd, " ?: provides list of commands\n\n\r\n"); -} - - -/* - * shell commands for user entry - * This is the list of shell commands defined in this program - */ -static const ShellCommand commands[] = { - {"reg", reg}, - {"rf1", rf1}, - {"rf2", rf2}, - {"if", ifr}, - {"?", si_help}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseSequentialStream *)&SD2, - commands -}; - - -/* - * Entry to our code - */ -int main(void) -{ - - halInit(); - chSysInit(); - app_init(); - - si41xx_init(); - - /* - * Shell manager initialization. - */ - shellInit(); - chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(2048), - "shell1", NORMALPRIO + 1, - shellThread, (void *)&shell_cfg1); - - main_loop(); - return 0; -} diff --git a/src/archive/app_si41xx/source/README.md b/src/archive/app_si41xx/source/README.md deleted file mode 100644 index 9250e2c8..00000000 --- a/src/archive/app_si41xx/source/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# App-specific Source - -This contains AX5043 specific files - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_si41xx/source/si41xx.c b/src/archive/app_si41xx/source/si41xx.c deleted file mode 100644 index 733a8bfa..00000000 --- a/src/archive/app_si41xx/source/si41xx.c +++ /dev/null @@ -1,62 +0,0 @@ -/*! \file ax5043.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#include -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "si41xx.h" - - - -/** - * writes to an SI4123 register. - * @param address: register address, data: Register data. - * @return void. - */ -void si_write_reg(uint8_t address, uint32_t data) -{ - int i; - uint32_t sdata; - uint32_t mask = 1 << 31; - data = (data << 14) | (address << 10); - - palClearLine(LINE_SI_SENB); - - for(i=0; i<22;i++) - { - palClearLine(LINE_SI_SCLK); - chThdSleepMicroseconds(1); - sdata = data & mask; - if(sdata > 0){ - //chprintf(DEBUG_CHP, "1"); - palSetLine(LINE_SI_SDATA); - } - else{ - //chprintf(DEBUG_CHP, "0"); - palClearLine(LINE_SI_SDATA); - } - chThdSleepMicroseconds(1); - palSetLine(LINE_SI_SCLK); - chThdSleepMicroseconds(1); - data = data <<1; - chThdSleepMicroseconds(1); - } - //chprintf(DEBUG_CHP, " \r\n"); - palSetLine(LINE_SI_SENB); - -} - - - -//!@ - diff --git a/src/archive/app_si41xx/source/si41xx.h b/src/archive/app_si41xx/source/si41xx.h deleted file mode 100644 index 6bee53fc..00000000 --- a/src/archive/app_si41xx/source/si41xx.h +++ /dev/null @@ -1,45 +0,0 @@ -/*! \file ax5043_common.h */ - - -/*! - * \addtogroup ax5043 - * * @{ - * - */ -#ifndef _AX5043_COMMON_H -#define _AX5043_COMMON_H - -#define DEBUG_SERIAL SD2 -#define DEBUG_CHP ((BaseSequentialStream *) &DEBUG_SERIAL) - -#include -#include - - - - -/****************************************************************************** - ******************** AX5043 control SPI registers *************************** - *****************************************************************************/ - -/* Status and test registers */ -#define SI41XX_REG_MAIN_CONFIG 0x0 -#define SI41XX_REG_PHASE_GAIN 0x1 -#define SI41XX_REG_PWRDOWN 0x2 -#define SI41XX_REG_RF1_NDIV 0x3 -#define SI41XX_REG_RF2_NDIV 0x4 -#define SI41XX_REG_IF_NDIV 0x5 -#define SI41XX_REG_RF1_RDIV 0x6 -#define SI41XX_REG_RF2_RDIV 0x7 -#define SI41XX_REG_IF_RDIV 0x8 - -#define SI41XX_FREF 16 - - - - -//function declaration starts here -void si_write_reg(uint8_t address, uint32_t data); - -#endif -//! @} diff --git a/src/archive/app_solardemo/Makefile b/src/archive/app_solardemo/Makefile deleted file mode 100644 index a3bc0eb4..00000000 --- a/src/archive/app_solardemo/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x200 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x200 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_solardemo - -# Target settings. -MCU = cortex-m0 -BOARD = ST_NUCLEO32_F042K6 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F042x6.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/archive/app_solardemo/cfg/chconf.h b/src/archive/app_solardemo/cfg/chconf.h deleted file mode 100644 index 6f3b51a9..00000000 --- a/src/archive/app_solardemo/cfg/chconf.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_0_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY TRUE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/archive/app_solardemo/cfg/halconf.h b/src/archive/app_solardemo/cfg/halconf.h deleted file mode 100644 index 559849b3..00000000 --- a/src/archive/app_solardemo/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/archive/app_solardemo/cfg/mcuconf.h b/src/archive/app_solardemo/cfg/mcuconf.h deleted file mode 100644 index 666f5dba..00000000 --- a/src/archive/app_solardemo/cfg/mcuconf.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 3 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_SYSCLK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_USART1SW STM32_USART1SW_HSI -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 -#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3 -#define STM32_IRQ_USART1_PRIORITY 3 -#define STM32_IRQ_USART2_PRIORITY 3 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 3 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/archive/app_solardemo/main.c b/src/archive/app_solardemo/main.c deleted file mode 100644 index 17feaab6..00000000 --- a/src/archive/app_solardemo/main.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -//=== ChibiOS header files -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -//=== Project header files -#include "oresat.h" - -#include "demo.h" - -//=== Serial configuration -static SerialConfig ser_cfg = -{ - 115200, //Baud rate - 0, // - 0, // - 0, // -}; - -/* - * I2C configuration - */ -static const I2CConfig i2cfg1 = -{ - I2C_100KHZ_TIMINGR, - 0, - 0, -}; - -uint8_t data[8]; - -static void app_init(void) { - //=== App initialization - - // Start up debug output - sdStart(&SD2, &ser_cfg); - - i2cInit(); - i2cStart(&I2CD1, &i2cfg1); - - for (uint8_t i = 0; i < 8; ++i) { - data[i] = 0; - } - - canTPDOObjectInit(CAN_PDO_1, CAN_ID_DEFAULT, 0, 0, 8, data); -} - -static void main_app(void) { - //=== Start application threads - - //Example thread creation - chThdCreateStatic(demo_measure_wa, sizeof(demo_measure_wa), NORMALPRIO, demo_measure, NULL); - - /* - * Begin main loop - */ - while (true) - { - chThdSleepMilliseconds(1000); - } -} - -int main(void) { - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - oresat_init(31); - - // Initialize and start app - app_init(); - main_app(); - - return 0; -} diff --git a/src/archive/app_solardemo/source/README.md b/src/archive/app_solardemo/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/archive/app_solardemo/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/archive/app_solardemo/source/demo.c b/src/archive/app_solardemo/source/demo.c deleted file mode 100644 index 92591760..00000000 --- a/src/archive/app_solardemo/source/demo.c +++ /dev/null @@ -1,66 +0,0 @@ -#include "demo.h" - -const uint8_t LTC2990_I2C_ADDR = 0b1001100; -static ltc2990_data monitor_data; -static solar_v1_p params; -extern uint8_t data[]; - -// Example blinker thread -THD_WORKING_AREA(demo_measure_wa, 128); -THD_FUNCTION(demo_measure, arg) { - - i2cflags_t i2c_errors = 0x0; - volatile uint8_t regval = 0xf; - - (void)arg; - chRegSetThreadName("demo_measure"); - - regval = 0xf; - - /* CONTROL Setup */ - regval = LTC2990_CONTROL_ACQ_SINGLE - | LTC2990_CONTROL_ALL_MODE_4_3 - | LTC2990_CONTROL_MODE_1_2_0; - - while (!chThdShouldTerminateX()) { - /* TRIGGER */ - regval = 0xf; - ltc2990_writereg(LTC2990_TRIGGER, regval, &i2c_errors); - chThdSleepMilliseconds(LTC2990_TRIGGER_WAIT_MS); - - regval = ltc2990_readreg(LTC2990_CONTROL, &i2c_errors); - - /* CONTROL check status */ - if(!ltc2990_conversion_done(regval)) - { - chThdSleepS(TIME_S2I(1)); - } - else - { - /* READ ALL */ - ltc2990_read_all(&monitor_data, &i2c_errors); - chSysLock(); - data[0] = monitor_data.T_INT_MSB; - data[1] = monitor_data.T_INT_LSB; - data[2] = monitor_data.VCC_MSB; - data[3] = monitor_data.VCC_LSB; - data[4] = monitor_data.V1_MSB; - data[5] = monitor_data.V1_LSB; - data[6] = monitor_data.V3_MSB; - data[7] = monitor_data.V3_LSB; - chSysUnlock(); - - /* TINT */ - ltc2990_error derror; - params.tint = ltc2990_calc_tint(&monitor_data, &derror); - /* VCC */ - params.vcc = ltc2990_calc_vcc(&monitor_data, &derror ); - /* Current */ - params.current = solar_v1_calc_current(&monitor_data, &derror); - /* External Temp */ - params.temp_ext = solar_v1_calc_temp(&monitor_data, &derror) ; - } - - chThdSleepMilliseconds(1000); - } -} diff --git a/src/archive/app_solardemo/source/demo.h b/src/archive/app_solardemo/source/demo.h deleted file mode 100644 index 5e3b1f98..00000000 --- a/src/archive/app_solardemo/source/demo.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _DEMO_H_ -#define _DEMO_H_ - -#include "ch.h" -#include "hal.h" - -#include "ltc2990.h" -#include "solar_v1.h" - -// Example blinker thread prototypes -extern THD_WORKING_AREA(demo_measure_wa, 128); -extern THD_FUNCTION(demo_measure, arg); - -#endif diff --git a/src/archive/app_solardemo/source/ltc2990.c b/src/archive/app_solardemo/source/ltc2990.c deleted file mode 100644 index cc76907d..00000000 --- a/src/archive/app_solardemo/source/ltc2990.c +++ /dev/null @@ -1,139 +0,0 @@ -/*! \file ltc2990.c - * - * API for ltc2990.c - */ - -/*! - * \defgroup ltc2990 Voltage, current and Temperature Monitor - * - * @{ - */ - -#include -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "util_numbers.h" -#include "ltc2990.h" - -extern const uint8_t LTC2990_I2C_ADDR; - -static uint8_t i2c_txbuf[LTC2990_I2C_TX_BUFSIZE]; -static uint8_t i2c_rxbuf[LTC2990_I2C_RX_BUFSIZE]; - -uint8_t ltc2990_readreg(uint8_t reg, i2cflags_t * i2c_errors) -{ - msg_t status = MSG_OK; - systime_t tmo = TIME_MS2I(4); - - i2c_txbuf[0] = reg; - i2c_rxbuf[0] = 0xff; - i2cAcquireBus(&I2CD1); - status = i2cMasterTransmitTimeout(&I2CD1, LTC2990_I2C_ADDR, i2c_txbuf, 1, i2c_rxbuf, 1, tmo); - i2cReleaseBus(&I2CD1); - - if (status != MSG_OK) - { - *i2c_errors = i2cGetErrors(&I2CD1); - } - - return(i2c_rxbuf[0]); -} - -void ltc2990_writereg(uint8_t reg, uint8_t val, i2cflags_t * i2c_errors) -{ - msg_t status = MSG_OK; - systime_t tmo = TIME_MS2I(4); - - i2c_txbuf[0] = reg; - i2c_txbuf[1] = val; - i2cAcquireBus(&I2CD1); - status = i2cMasterTransmitTimeout(&I2CD1, LTC2990_I2C_ADDR, i2c_txbuf, 2, i2c_rxbuf, 0, tmo); - i2cReleaseBus(&I2CD1); - - if (status != MSG_OK) - { - *i2c_errors = i2cGetErrors(&I2CD1); - } -} - -void ltc2990_read_all(ltc2990_data * d, i2cflags_t * i2c_errors) -{ - msg_t status = MSG_OK; - systime_t tmo = TIME_MS2I(4); - - i2c_txbuf[0] = LTC2990_STATUS; - i2cAcquireBus(&I2CD1); - status = i2cMasterTransmitTimeout(&I2CD1, LTC2990_I2C_ADDR, i2c_txbuf, 1, i2c_rxbuf, 0x10, tmo); - i2cReleaseBus(&I2CD1); - - if (status != MSG_OK) - { - *i2c_errors = i2cGetErrors(&I2CD1); - } - else - { - d->STATUS = i2c_rxbuf[0]; - d->CONTROL = i2c_rxbuf[1]; - d->TRIGGER = i2c_rxbuf[2]; - d->NA = i2c_rxbuf[3]; - d->T_INT_MSB = i2c_rxbuf[4]; - d->T_INT_LSB = i2c_rxbuf[5]; - d->V1_MSB = i2c_rxbuf[6]; - d->V1_LSB = i2c_rxbuf[7]; - d->V2_MSB = i2c_rxbuf[8]; - d->V2_LSB = i2c_rxbuf[9]; - d->V3_MSB = i2c_rxbuf[10]; - d->V3_LSB = i2c_rxbuf[11]; - d->V4_MSB = i2c_rxbuf[12]; - d->V4_LSB = i2c_rxbuf[13]; - d->VCC_MSB = i2c_rxbuf[14]; - d->VCC_LSB = i2c_rxbuf[15]; - } -} - -inline bool ltc2990_conversion_done(uint8_t statusreg) -{ - if( ((statusreg & 0xfe) & 0x1) == 0x1) - { - return false; - } - return true; -} - -/* T Internal in C */ -signed int ltc2990_calc_tint(ltc2990_data * d, ltc2990_error * error) -{ - signed int tint_C = 0; - - *error = LTC2990_DATA_INVALID; - if((0x80 & d->T_INT_MSB) != 0) - { - //clear dv bit - d->T_INT_MSB = ((~(1 << 7)) & d->T_INT_MSB); - tint_C = sign_extend_13bit((d->T_INT_MSB << 8) | d->T_INT_LSB); - *error = LTC2990_OK; - } - return(tint_C / 16); -} - -/* VCC in millivolts */ -signed int ltc2990_calc_vcc(ltc2990_data * d, ltc2990_error * error) -{ - uint16_t vcc_bits = 0; - double vcc_volts_d = 0.0; - signed int vcc_millivolts = 0; - - *error = LTC2990_DATA_INVALID; - if((0x80 & d->VCC_MSB) != 0) - { - vcc_bits = ((d->VCC_MSB << 8) | d->VCC_LSB); - vcc_volts_d = 2.5 + ((double)(vcc_bits & 0x3fff) * 0.00030518 ) ; - vcc_millivolts = (signed int)incr_rnd(vcc_volts_d * 1000, 0.1); - *error = LTC2990_OK; - } - return vcc_millivolts; -} - -//! @} diff --git a/src/archive/app_solardemo/source/ltc2990.h b/src/archive/app_solardemo/source/ltc2990.h deleted file mode 100644 index 6789917a..00000000 --- a/src/archive/app_solardemo/source/ltc2990.h +++ /dev/null @@ -1,98 +0,0 @@ -/*! \file ltc2990.h */ - -/*! - * \addtogroup ltc2990 - * * @{ - * - */ -#ifndef _LTC2990_H_ -#define _LTC2990_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "ch.h" -#include "hal.h" - -extern const uint8_t LTC2990_I2C_ADDR; - -typedef struct ltc2990data -{ - uint8_t STATUS; // 0x0 - uint8_t CONTROL; // 0x1 - uint8_t TRIGGER; // ... - uint8_t NA; - uint8_t T_INT_MSB; - uint8_t T_INT_LSB; - uint8_t V1_MSB; - uint8_t V1_LSB; - uint8_t V2_MSB; - uint8_t V2_LSB; - uint8_t V3_MSB; - uint8_t V3_LSB; - uint8_t V4_MSB; - uint8_t V4_LSB; // ... - uint8_t VCC_MSB; // 0xe - uint8_t VCC_LSB; // 0xf -} ltc2990_data; - -/* HSI Clock selected 8Mhz - see mcuconf.h Wed 03 May 2017 12:54:49 (PDT) */ -/* Ref: 26.4.10 table in Reference Manual for stm32f0 */ -typedef enum -{ - I2C_100KHZ_TIMINGR = 0x10420f13, - I2C_400KHZ_TIMINGR = 0x00310309, -} solar_i2c_cfg; - -typedef enum -{ - LTC2990_OK = 0x0, - LTC2990_DATA_INVALID = (0b1 << 0), - LTC2990_SENSOR_SHORT = (0b1 << 2), - LTC2990_SENSOR_OPEN = (0b1 << 3), -} ltc2990_error; - - -#define LTC2990_I2C_TX_BUFSIZE 4U -#define LTC2990_I2C_RX_BUFSIZE 20U - -#define LTC2990_TRIGGER_WAIT_MS 200U - -#define LTC2990_STATUS 0x00U // R Indicates BUSY State, Conversion Sta -#define LTC2990_CONTROL 0x01U // R/W Controls Mode, Single/Repeat, Celsiu -#define LTC2990_TRIGGER 0x02U // R/W Triggers a Conversion -// #define LTC2990_N/A 0x03 // Unused Address -#define LTC2990_TINT_MSB 0x04U // R Internal Temperature MSB -#define LTC2990_TINT_LSB 0x05U // R Internal Temperature LSB -#define LTC2990_V1_MSB 0x06U // R V1, V1 – V2 or TR1 MSB -#define LTC2990_V1_LSB 0x07U // R V1, V1 – V2 or TR1 LSB -#define LTC2990_V2_MSB 0x08U // R V2, V1 – V2 or TR1 MSB -#define LTC2990_V2_LSB 0x09U // R V2, V1 – V2 or TR1 LSB -#define LTC2990_V3_MSB 0x0AU // R V3, V3 – V4 or TR2 MSB -#define LTC2990_V3_LSB 0x0BU // R V3, V3 – V4 or TR2 LSB -#define LTC2990_V4_MSB 0x0CU // R V4, V3 – V4 or TR2 MSB -#define LTC2990_V4_LSB 0x0DU // R V4, V3 – V4 or TR2 LSB -#define LTC2990_VCC_MSB 0x0EU // R VCC MSB -#define LTC2990_VCC_LSB 0x0FU // R VCC LSB - -#define LTC2990_CONTROL_ACQ_SINGLE (0b1<<6) -#define LTC2990_CONTROL_ALL_MODE_4_3 (0b11<<3) -#define LTC2990_CONTROL_MODE_1_2_0 (0b001<<0) - -uint8_t ltc2990_readreg(uint8_t reg, i2cflags_t * i2c_errors); - -void ltc2990_writereg(uint8_t reg, uint8_t val, i2cflags_t * i2c_errors); -void ltc2990_read_all(ltc2990_data * d, i2cflags_t * i2c_errors); - -bool ltc2990_conversion_done(uint8_t statusreg); -signed int ltc2990_calc_tint(ltc2990_data * d, ltc2990_error * error); -signed int ltc2990_calc_vcc(ltc2990_data * d, ltc2990_error * error); - -#ifdef __cplusplus -} -#endif - -#endif -//! @} diff --git a/src/archive/app_solardemo/source/solar_v1.c b/src/archive/app_solardemo/source/solar_v1.c deleted file mode 100644 index e11715fc..00000000 --- a/src/archive/app_solardemo/source/solar_v1.c +++ /dev/null @@ -1,76 +0,0 @@ -/*! \file solar_v1.c - * - * API for solar_v1.c - */ - -/*! - * \defgroup solar_v1 Voltage, current and Temperature Monitor - * - * @{ - */ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "chprintf.h" - -#include "util_numbers.h" - -#include "ltc2990.h" - -#include "solar_v1.h" - -/* Current through Rsense in mA */ -signed int solar_v1_calc_current(ltc2990_data * d, ltc2990_error * error) -{ - uint8_t SIGN = 0; - uint16_t v_bits = 0; - double v_volts_d = 0.0; - double i_amps_d = 0.0; - signed int i_milliamps = INT_MIN; - - *error = LTC2990_DATA_INVALID; - if((0x80 & d->V1_MSB) != 0) - { - SIGN = ((d->V1_MSB & (1 << 6)) >> 6); - v_bits = ((d->V1_MSB << 8) | d->V1_LSB); - v_volts_d = (double)(v_bits & 0x3fff) * 0.00001942 ; - i_amps_d = v_volts_d / 0.18; - i_milliamps = (signed int)incr_rnd(i_amps_d * 1000, 0.1); - if(SIGN == 1) - { - i_milliamps *= -1; - } - *error = LTC2990_OK; - } - return i_milliamps; -} - -/* External Temp in C */ -signed int solar_v1_calc_temp(ltc2990_data * d, ltc2990_error * error) -{ - signed int text_C = INT_MIN; - - *error = LTC2990_DATA_INVALID; - if(((0x1 << 6) & d->V3_MSB) != 0) - { - *error = LTC2990_SENSOR_SHORT; - } - else if (((0x1 << 5) & d->V3_MSB) != 0) - { - *error = LTC2990_SENSOR_OPEN; - } - else if((0x80 & d->V3_MSB) != 0) - { - //clear dv bit - d->V3_MSB = ((~(1 << 7)) & d->V3_MSB); - text_C = sign_extend_13bit((d->V3_MSB << 8) | d->V3_LSB); - *error = LTC2990_OK; - } - return(text_C / 16); -} - - -//! @} diff --git a/src/archive/app_solardemo/source/solar_v1.h b/src/archive/app_solardemo/source/solar_v1.h deleted file mode 100644 index bceff2a4..00000000 --- a/src/archive/app_solardemo/source/solar_v1.h +++ /dev/null @@ -1,37 +0,0 @@ -/*! \file solar_v1.h */ - -/*! - * \addtogroup solar_v1 - * * @{ - * - */ -#ifndef _SOLAR_V1_H_ -#define _SOLAR_V1_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "ch.h" -#include "hal.h" - -#include "ltc2990.h" -typedef struct solar_v1_params -{ - signed int tint; - signed int vcc; - signed int current; - signed int temp_ext; -} solar_v1_p; - - -signed int solar_v1_calc_temp(ltc2990_data * d, ltc2990_error * error); -signed int solar_v1_calc_current(ltc2990_data * d, ltc2990_error * error); - -#ifdef __cplusplus -} -#endif - -#endif -//! @} diff --git a/src/archive/app_solardemo/source/util_numbers.c b/src/archive/app_solardemo/source/util_numbers.c deleted file mode 100644 index f8f07b9a..00000000 --- a/src/archive/app_solardemo/source/util_numbers.c +++ /dev/null @@ -1,65 +0,0 @@ - -/*! \file util_numbers.c - * - * Number utilities - * - * @defgroup util_numbers Numbers Utilities - * @{ - */ - - -#include "util_numbers.h" - -/* - * Given a number d - * An increment m - * 1. create y = x/m - * 2. q = int(Round y) - * 3. z = q * m - * - */ -double incr_rnd(double d, double m) -{ - - int q; - double y = 0; - double z = 0; - - y = d / m; - - q = round_nearest(y); - - z = q * m; - - return z; - -} - -/*! - * Reference - * https://graphics.stanford.edu/~seander/bithacks.html#FixedSignExtend - * - * Note: Clear bits 14->31 prior to calling. - * Warning: Untested on 64 bit integers. - * - * example - * //clear dv bit - * tint_msb = ((~(1 << 7)) & tint_msb); - * tint = sign_extend_12bit((tint_msb << 8) | tint_lsb); - * - */ -signed int sign_extend_13bit(signed int x) -{ - signed int r = 0; - struct - { - signed int x: 13; - } s; - - r = s.x = x; - - return r; -} - - -//! @} diff --git a/src/archive/app_solardemo/source/util_numbers.h b/src/archive/app_solardemo/source/util_numbers.h deleted file mode 100644 index 3a5514a1..00000000 --- a/src/archive/app_solardemo/source/util_numbers.h +++ /dev/null @@ -1,33 +0,0 @@ -/*! \file util_numbers.h - * \addtogroup util_numbers - * @{ - */ - -#ifndef UTIL_NUMBERS_H_ -#define UTIL_NUMBERS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -static inline int round_nearest(float f) -{ - return((f < 0) ? ((int)(f - 0.5f)) : ((int)(f + 0.5f))); - //if(f<0) { - //return((int)(f-0.5f)); - //} - //return (int)(f + 0.5f); -} - - -double incr_rnd(double d, double m) ; -signed int sign_extend_13bit(signed int); - -#ifdef __cplusplus -} -#endif - -#endif - -//! @} - diff --git a/src/f0/app_adcs/Makefile b/src/f0/app_adcs/Makefile index 8cf042b9..f60e5ba7 100644 --- a/src/f0/app_adcs/Makefile +++ b/src/f0/app_adcs/Makefile @@ -126,7 +126,6 @@ endif # Project specific files. include $(PROJ_SRC)/oresat.mk include $(PROJ_SRC)/bmi088.mk -include $(PROJ_SRC)/mmc5883ma.mk include $(PROJ_SRC)/mmc5983ma.mk include $(PROJ_SRC)/ltc4305.mk diff --git a/src/f4/README.md b/src/f4/README.md deleted file mode 100644 index 9c6d5a69..00000000 --- a/src/f4/README.md +++ /dev/null @@ -1,49 +0,0 @@ -# STM32F446RE - -This is the source directory for all STM32F439Zx applications. -This device contains an ARM Cortex-M4, and is also known as an M4 or F4. - -This MCU implements the main Command, Communications, and Control system -for OreSat. - -## Testing the toolchain -After having installed the required toolchain components as described in -the Prerequesites section of the main README, it is good to test that -they all function as expected. This can be done by building and flashing -the `app_blinky` application that simply blinks an LED. - -In order to accomplish this, from this directory simply execute the -following: - -``` -cd app_blinky -make -make write -``` -This should result in a clean no-error build, followed by a successful -write to the board and a flashing green LED. If this all works, -congratulations! Your toolchain is working and you can begin developing. - -## Creating an app -The template to copy for new applications is [app_template](app_template). -To create a new app, simply make a copy of the app_template directory -and name it whatever you like. From this directory: - -``` -cp -R app_template app_ -``` - -Then, open the Makefile `app_/Makefile` and edit the line `PROJECT =` to whatever name -you've chosen: - -If building for a specific board, also update the `BOARD =` line to the -board defined in the `boards` directory. -``` -PROJECT = app_ -``` - -At this point, you simply write code in source files under the `sources` -directory, include the appropriate header file in the main.c file, -and finally register your worker with the main OreSat application. - -See the doc folder for further documentation. diff --git a/src/f4/app_blinky/Makefile b/src/f4/app_blinky/Makefile deleted file mode 100644 index 71b1cd07..00000000 --- a/src/f4/app_blinky/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_blinky - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_F446RE - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Project specific files. -#include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/f4/app_blinky/README.md b/src/f4/app_blinky/README.md deleted file mode 100644 index ae8def29..00000000 --- a/src/f4/app_blinky/README.md +++ /dev/null @@ -1,87 +0,0 @@ -# Toolchain Test Application -`app_blinky` is a simple app that blinks a dev board's LED at 1Hz with a 50% duty cycle. - -To ensure you have your toolchain correctly installed and configured, -you simply need to run the following sequence of commands: - -``` -make -make write -``` - -If you see something like the following output for each, your -toolchain works: - -``` -âžœ make -Compiler Options -arm-none-eabi-gcc -c -mcpu=cortex-m0 -mthumb -Og -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -fno-common -flto -Wall -Wextra -Wundef -Wstrict-prototypes -Wa,-alms=./build/lst/ -DCORTEX_USE_FPU=FALSE -DPORT_IGNORE_GCC_VERSION_CHECK -MD -MP -MF ./.dep/build.d -I. -I./cfg -I../../../ChibiOS/os/license -I../../../ChibiOS/os/common/portability/GCC -I../../../ChibiOS/os/common/startup/ARMCMx/compilers/GCC -I../../../ChibiOS/os/common/startup/ARMCMx/devices/STM32F0xx -I../../../ChibiOS/os/common/ext/ARM/CMSIS/Core/Include -I../../../ChibiOS/os/common/ext/ST/STM32F0xx -I../../../ChibiOS/os/hal/include -I../../../ChibiOS/os/hal/ports/common/ARMCMx -I../../../ChibiOS/os/hal/ports/STM32/STM32F0xx -I../../../ChibiOS/os/hal/ports/STM32/LLD/ADCv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/CANv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/DACv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/DMAv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/EXTIv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/GPIOv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/I2Cv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/RTCv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/SPIv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/TIMv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/USARTv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/USBv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/xWDGv1 -I../../../boards/ST_NUCLEO32_F042K6 -I../../../ChibiOS/os/hal/osal/rt-nil -I../../../ChibiOS/os/rt/include -I../../../ChibiOS/os/oslib/include -I../../../ChibiOS/os/common/ports/ARMCMx -I../../../ChibiOS/os/common/ports/ARMCMx/compilers/GCC -I../../../common/include main.c -o main.o - -Compiling crt0_v6m.S -Compiling vectors.S -Compiling chcoreasm_v6m.S -Compiling crt1.c -Compiling hal.c -Compiling hal_st.c -Compiling hal_buffers.c -Compiling hal_queues.c -Compiling hal_flash.c -Compiling hal_mmcsd.c -Compiling hal_pal.c -Compiling hal_serial.c -Compiling nvic.c -Compiling stm32_isr.c -Compiling hal_lld.c -Compiling stm32_dma.c -Compiling stm32_exti.c -Compiling hal_pal_lld.c -Compiling hal_st_lld.c -Compiling hal_serial_lld.c -Compiling board.c -Compiling osal.c -Compiling chsys.c -Compiling chdebug.c -Compiling chtrace.c -Compiling chvt.c -Compiling chschd.c -Compiling chthreads.c -Compiling chregistry.c -Compiling chsem.c -Compiling chmtx.c -Compiling chcond.c -Compiling chevents.c -Compiling chmsg.c -Compiling chdynamic.c -Compiling chmboxes.c -Compiling chmemcore.c -Compiling chmempools.c -Compiling chpipes.c -Compiling chcore.c -Compiling chcore_v6m.c -Compiling main.c -Linking build/app_blinky.elf -Creating build/app_blinky.hex -Creating build/app_blinky.bin -Creating build/app_blinky.dmp - - text data bss dec hex filename - 4952 0 6144 11096 2b58 build/app_blinky.elf -Creating build/app_blinky.list - -Done - -âžœ make write -st-flash --reset --format ihex write ./build/app_blinky.hex -st-flash 1.6.1 -2020-07-30T13:29:22 INFO common.c: F09X: 32 KiB SRAM, 256 KiB flash in at least 2 KiB pages. -2020-07-30T13:29:22 INFO common.c: Attempting to write 5192 (0x1448) bytes to stm32 address: 134217728 (0x8000000) -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08000000 erased -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08000800 erased -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08001000 erased -2020-07-30T13:29:22 INFO common.c: Finished erasing 3 pages of 2048 (0x800) bytes -2020-07-30T13:29:22 INFO common.c: Starting Flash write for VL/F0/F3/F1_XL core id -2020-07-30T13:29:22 INFO flash_loader.c: Successfully loaded flash loader in sram - 3/3 pages written -2020-07-30T13:29:22 INFO common.c: Starting verification of write complete -2020-07-30T13:29:22 INFO common.c: Flash written and verified! jolly good! -``` diff --git a/src/f4/app_blinky/cfg/chconf.h b/src/f4/app_blinky/cfg/chconf.h deleted file mode 100644 index 29b34229..00000000 --- a/src/f4/app_blinky/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE TRUE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/f4/app_blinky/cfg/halconf.h b/src/f4/app_blinky/cfg/halconf.h deleted file mode 100644 index 534c4bb6..00000000 --- a/src/f4/app_blinky/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/f4/app_blinky/cfg/mcuconf.h b/src/f4/app_blinky/cfg/mcuconf.h deleted file mode 100644 index e0792bdb..00000000 --- a/src/f4/app_blinky/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/f4/app_blinky/main.c b/src/f4/app_blinky/main.c deleted file mode 100644 index 9b287051..00000000 --- a/src/f4/app_blinky/main.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" - -int main(void) -{ - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - palSetLineMode(LINE_LED,PAL_MODE_OUTPUT_PUSHPULL); - - while (true) - { - palClearLine(LINE_LED); - chThdSleepMilliseconds(500); - palSetLine(LINE_LED); - chThdSleepMilliseconds(500); - } - - return 0; -} diff --git a/src/f4/app_cantest/Makefile b/src/f4/app_cantest/Makefile deleted file mode 100644 index c00a090e..00000000 --- a/src/f4/app_cantest/Makefile +++ /dev/null @@ -1,223 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = hard -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_cantest - -# Target settings. -MCU = cortex-m4 -BOARD = ORESAT_C3_V4 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep -ODDIR := $(APP_ROOT)/od - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -ifeq ($(ORESAT),) - ORESAT = 0.5 -endif - -# generate OD.c/OD.h from oresat-configs -FW_VERSION = $(shell git describe --always) -$(shell oresat-gen-fw-files --oresat $(ORESAT) base -d $(ODDIR) -fw $(FW_VERSION) -hw $(BOARD)) -# add them -ALLCSRC += $(ODDIR)/OD.c -ALLINC += $(ODDIR) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk -include $(PROJ_SRC)/CO_master.mk -include $(PROJ_SRC)/bootloader.mk -include $(PROJ_SRC)/rtc.mk -include $(PROJ_SRC)/fs.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk -include $(CHIBIOS)/os/various/shell/shell.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F429xI.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DSHELL_ENABLE -DSHELL_CONFIG_FILE -DLFS_CONFIG=lfs_util_custom.h - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/f4/app_cantest/README.md b/src/f4/app_cantest/README.md deleted file mode 100644 index e5f134b0..00000000 --- a/src/f4/app_cantest/README.md +++ /dev/null @@ -1,18 +0,0 @@ -# OreSat C3 Firmware Application -This application implements the core C3 firmware, responsible for -interfacing with and managing all subsystems on OreSat, as well as -communicating with ground stations. This initial version simply -implements a command interface via radio, and responds with telemetry -indicating subsystem health status. - -## Directory Structure -This folder contains the root of an applications sources. It contains -several files and folders: -* [main.c](main.c): The main program file called by ChibiOS. Contains - initialization code and registers threads and functions. -* [Makefile](Makefile): The main Makefile for the application. Sources - all other build files. -* [cfg](cfg): The directory containing ChibiOS's configuration files for - this application. -* [source](source): The directory where application code is put. - Everything within this directory automatically builds. diff --git a/src/f4/app_cantest/cfg/CO_driver_custom.h b/src/f4/app_cantest/cfg/CO_driver_custom.h deleted file mode 100644 index 2e98648e..00000000 --- a/src/f4/app_cantest/cfg/CO_driver_custom.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define CO_CONFIG_NMT (CO_CONFIG_NMT_CALLBACK_CHANGE | \ - CO_CONFIG_NMT_MASTER | \ - CO_CONFIG_GLOBAL_FLAG_CALLBACK_PRE | \ - CO_CONFIG_GLOBAL_FLAG_TIMERNEXT) - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_SDO_CLI_ENABLE | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL | \ - CO_CONFIG_GLOBAL_FLAG_CALLBACK_PRE | \ - CO_CONFIG_GLOBAL_FLAG_TIMERNEXT | \ - CO_CONFIG_GLOBAL_FLAG_OD_DYNAMIC) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/f4/app_cantest/cfg/chconf.h b/src/f4/app_cantest/cfg/chconf.h deleted file mode 100644 index 53dfa662..00000000 --- a/src/f4/app_cantest/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/f4/app_cantest/cfg/halconf.h b/src/f4/app_cantest/cfg/halconf.h deleted file mode 100644 index c6c76917..00000000 --- a/src/f4/app_cantest/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS TRUE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_LINE -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/f4/app_cantest/cfg/mcuconf.h b/src/f4/app_cantest/cfg/mcuconf.h deleted file mode 100644 index 7aff5ad0..00000000 --- a/src/f4/app_cantest/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 16 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 8 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 8 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSE -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLL -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/f4/app_cantest/cfg/shellconf.h b/src/f4/app_cantest/cfg/shellconf.h deleted file mode 100644 index c31de933..00000000 --- a/src/f4/app_cantest/cfg/shellconf.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef SHELLCONF_H -#define SHELLCONF_H - -#define SHELL_MAX_ARGUMENTS 10 -#define SHELL_USE_HISTORY TRUE -#define SHELL_USE_ESC_SEQ TRUE -#define SHELL_PROMPT_STR "OreSat> " - -#endif diff --git a/src/f4/app_cantest/main.c b/src/f4/app_cantest/main.c deleted file mode 100644 index f3553a69..00000000 --- a/src/f4/app_cantest/main.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" -#include "shell.h" - -/* Project header files */ -#include "oresat.h" -#include "rtc.h" -#include "can_bootloader.h" -#ifdef SHELL_ENABLE -#include "cmd.h" -#endif - -/* -static const oresat_node_t nodes[] = { - {0x02, 0x00, 2000, "Battery 1"}, - {0x03, 0x00, 2000, "Battery 2"}, - {0x04, 0x00, 2000, "Solar Panel 1"}, - {0x05, 0x00, 2000, "Solar Panel 2"}, - {0x06, 0x00, 2000, "Solar Panel 3"}, - {0x07, 0x00, 2000, "Solar Panel 4"}, - {0x08, 0x00, 2000, "Solar Panel 5"}, - {0x09, 0x00, 2000, "Solar Panel 6"}, - {0x0A, 0x00, 2000, "Solar Panel 7"}, - {0x0B, 0x00, 2000, "Solar Panel 8"}, - {0x31, 0x18, 2000, "Protocard 1"}, - {0x32, 0x19, 2000, "Protocard 2"}, - {0x33, 0x1A, 2000, "Protocard 3"}, - {0x11, 0x1D, 2000, "Star Tracker"} -}; -*/ - -#ifdef SHELL_ENABLE -static worker_t cmd_worker; -static thread_descriptor_t cmd_desc = { - .name = "Shell", - .wbase = THD_WORKING_AREA_BASE(cmd_wa), - .wend = THD_WORKING_AREA_END(cmd_wa), - .prio = NORMALPRIO, - .funcp = cmd, - .arg = NULL -}; -#endif - -static flt_reg_t fifo1_filters[] = { - { - .scale16.id_mask[0].STID = ORESAT_BOOTLOADER_CAN_COMMAND_GET, - .scale16.id_mask[1].STID = ORESAT_BOOTLOADER_CAN_COMMAND_READ_MEMORY, - }, - { - .scale16.id_mask[0].STID = ORESAT_BOOTLOADER_CAN_COMMAND_GO, - .scale16.id_mask[1].STID = ORESAT_BOOTLOADER_CAN_COMMAND_WRITE_MEMORY, - }, - { - .scale16.id_mask[0].STID = ORESAT_BOOTLOADER_CAN_COMMAND_ERASE, - .scale16.id_mask[1].STID = CAN_BOOTLOADER_WRITE_MEMORY_RESPONSE_SID, - }, - { - .scale16.id_mask[0].STID = STM32_BOOTLOADER_CAN_ACK, - .scale16.id_mask[1].STID = STM32_BOOTLOADER_CAN_NACK, - } -}; - -static oresat_config_t oresat_conf = { - .cand = &CAND1, - .node_id = 0x01, - .bitrate = ORESAT_DEFAULT_BITRATE, - .fifo1_filters = fifo1_filters, - .filter_count = sizeof(fifo1_filters), -}; - -/** - * @brief App Initialization - */ -static void app_init(void) -{ - - /* Initialize shell worker thread */ -#ifdef SHELL_ENABLE - reg_worker(&cmd_worker, &cmd_desc, true, true); -#endif - - /* Initialize shell and start serial interface */ -#ifdef SHELL_ENABLE - shellInit(); -#endif - sdStart(&SD3, NULL); -} - -/** - * @brief Main Application - */ -int main(void) -{ - // Initialize and start - oresat_init(&oresat_conf); - app_init(); - oresat_start(); - return 0; -} diff --git a/src/f4/app_cantest/source/README.md b/src/f4/app_cantest/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/f4/app_cantest/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/f4/app_cantest/source/cmd.c b/src/f4/app_cantest/source/cmd.c deleted file mode 100644 index e8da8ec1..00000000 --- a/src/f4/app_cantest/source/cmd.c +++ /dev/null @@ -1,51 +0,0 @@ -#include -#include -#include - -#include "cmd.h" -#include "test_time.h" -#include "test_lfs.h" -#include "test_bootloader.h" -#include "chprintf.h" -#include "shell.h" - -static thread_t *shell_tp; - -/*===========================================================================*/ -/* Placeholder */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Shell */ -/*===========================================================================*/ -static const ShellCommand commands[] = { - {"time", cmd_time}, - {"lfs", cmd_lfs}, - {"bootloader", cmd_bootloader}, - {NULL, NULL} -}; - -static char histbuf[SHELL_MAX_HIST_BUFF]; - -static const ShellConfig shell_cfg = { - (BaseSequentialStream *)&SD3, - commands, - histbuf, - sizeof(histbuf), -}; - -THD_WORKING_AREA(shell_wa, 0x1000); -THD_WORKING_AREA(cmd_wa, 0x200); -THD_FUNCTION(cmd, arg) -{ - (void)arg; - - /* Start a shell */ - while (!chThdShouldTerminateX()) { - shell_tp = chThdCreateStatic(shell_wa, sizeof(shell_wa), NORMALPRIO, shellThread, (void *)&shell_cfg); - chThdWait(shell_tp); - chThdSleepMilliseconds(500); - } - - chThdExit(MSG_OK); -} diff --git a/src/f4/app_cantest/source/cmd.h b/src/f4/app_cantest/source/cmd.h deleted file mode 100644 index 86c431df..00000000 --- a/src/f4/app_cantest/source/cmd.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _CMD_H_ -#define _CMD_H_ - -#include "ch.h" -#include "hal.h" - -/* Example blinker thread prototypes */ -extern THD_WORKING_AREA(cmd_wa, 0x200); -extern THD_FUNCTION(cmd, arg); - -#endif diff --git a/src/f4/app_cantest/source/test_bootloader.c b/src/f4/app_cantest/source/test_bootloader.c deleted file mode 100644 index 075280ce..00000000 --- a/src/f4/app_cantest/source/test_bootloader.c +++ /dev/null @@ -1,32 +0,0 @@ -#include -#include -#include "test_bootloader.h" -#include "can_bootloader.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* Time */ -/*===========================================================================*/ -void cmd_bootloader(BaseSequentialStream *chp, int argc, char *argv[]) -{ - - if (argc < 1) { - goto bootloader_usage; - } - if (!strcmp(argv[0], "cmd1")) { - } else if (!strcmp(argv[0], "cmd2")) { - } else { - goto bootloader_usage; - } - - return; - -bootloader_usage: - chprintf(chp, "Usage: bootloader \r\n" - " cmd1: \r\n" - " Does blah\r\n" - " cmd2: \r\n" - " Does other blah\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_cantest/source/test_bootloader.h b/src/f4/app_cantest/source/test_bootloader.h deleted file mode 100644 index 8180792d..00000000 --- a/src/f4/app_cantest/source/test_bootloader.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TEST_BOOTLOADER_H_ -#define _TEST_BOOTLOADER_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_bootloader(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif - diff --git a/src/f4/app_cantest/source/test_lfs.c b/src/f4/app_cantest/source/test_lfs.c deleted file mode 100644 index bf035bc3..00000000 --- a/src/f4/app_cantest/source/test_lfs.c +++ /dev/null @@ -1,206 +0,0 @@ -#include -#include -#include "test_lfs.h" -#include "fs.h" - -#define BUF_SIZE 256 - -/*===========================================================================*/ -/* OreSat LFS Operations */ -/*===========================================================================*/ -void cmd_lfs(BaseSequentialStream *chp, int argc, char *argv[]) -{ - int ret; - lfs_file_t *file; - lfs_dir_t *dir; - struct lfs_info info; - char buf[BUF_SIZE]; - - if (!strcmp(argv[0], "ls") && argc > 1) { - dir = dir_open(&FSD1, argv[1]); - if (dir == NULL) { - chprintf(chp, "Error in dir_open: %d\r\n", FSD1.err); - return; - } - do { - ret = dir_read(&FSD1, dir, &info); - if (ret <= 0) { - if (ret < 0) { - chprintf(chp, "Error in dir_read: %d\r\n", ret); - } - continue; - } - if (info.type == LFS_TYPE_REG) { - chprintf(chp, "reg "); - } else if (info.type == LFS_TYPE_DIR) { - chprintf(chp, "dir "); - } else { - chprintf(chp, "? "); - } - chprintf(chp, "%8u %s\r\n", info.size, info.name); - } while (ret > 0); - ret = dir_close(&FSD1, dir); - if (ret < 0) { - chprintf(chp, "Error in dir_close: %d\r\n", ret); - return; - } - chprintf(chp, "\r\n"); - } else if (!strcmp(argv[0], "mkdir") && argc > 1) { - ret = fs_mkdir(&FSD1, argv[1]); - if (ret < 0) { - chprintf(chp, "Error in fs_mkdir: %d\r\n"); - return; - } - } else if (!strcmp(argv[0], "rm") && argc > 1) { - ret = fs_remove(&FSD1, argv[1]); - if (ret < 0) { - chprintf(chp, "Error in fs_remove: %d\r\n"); - return; - } - } else if (!strcmp(argv[0], "cat") && argc > 1) { - file = file_open(&FSD1, argv[1], LFS_O_RDONLY); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - ret = file_read(&FSD1, file, buf, BUF_SIZE - 1); - if (ret < 0) { - chprintf(chp, "Error in file_read: %d\r\n", ret); - file_close(&FSD1, file); - return; - } - buf[ret] = '\0'; - chprintf(chp, "%s\r\n", buf); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "hexdump") && argc > 1) { - file = file_open(&FSD1, argv[1], LFS_O_RDONLY); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - ret = file_read(&FSD1, file, buf, BUF_SIZE); - if (ret < 0) { - chprintf(chp, "Error in file_read: %d\r\n", ret); - file_close(&FSD1, file); - return; - } - for (int i = 0; i < ret; i++) { - if (i % 0x10 == 0) chprintf(chp, "\r\n%04X:", i); - chprintf(chp, " %02X", buf[i]); - } - chprintf(chp, "\r\n"); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "load") && argc > 1) { - uint8_t buf[BUF_SIZE] = {0}; - char line[BUF_SIZE * 2] = {0}; - char c, *p = line; - size_t count = 0; - file = file_open(&FSD1, argv[1], LFS_O_RDWR | LFS_O_CREAT | LFS_O_TRUNC); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - while (streamRead(chp, (uint8_t*)&c, 1) != 0 && c != 4) { - c = toupper(c); - - if (isdigit(c) || (c >= 'A' && c <= 'F')) { - streamPut(chp, c); - *(p++) = c; - if (p == &line[BUF_SIZE * 2]) { - for (size_t off = 0; off < BUF_SIZE; off++) { - sscanf(&line[off*2], "%2hhx", &buf[off]); - } - p = line; - ret = file_write(&FSD1, file, buf, BUF_SIZE); - if (ret < 0) { - chprintf(chp, "Error in file_write: %d\r\n", ret); - break; - } - count += ret; - } - } else if ((c == 8) || (c == 127)) { - if (p != line) { - streamPut(chp, 0x08); - streamPut(chp, 0x20); - streamPut(chp, 0x08); - p--; - } - } - } - if (p != line) { - size_t len = (p - line) / 2; - for (size_t off = 0; off < len; off++) { - sscanf(&line[off*2], "%2hhx", &buf[off]); - } - ret = file_write(&FSD1, file, buf, len); - if (ret < 0) { - chprintf(chp, "Error in file_write: %d\r\n", ret); - } else { - count += ret; - } - } - chprintf(chp, "\r\nWrote %u bytes to %s\r\n", count, argv[1]); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "mount")) { - chprintf(chp, "Attempting to mount LFS...\r\n"); - ret = fs_mount(&FSD1, false); - if (ret < 0) { - chprintf(chp, "Mount failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else if (!strcmp(argv[0], "unmount")) { - chprintf(chp, "Attempting to unmount LFS...\r\n"); - ret = fs_unmount(&FSD1); - if (ret < 0) { - chprintf(chp, "Unmount failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else if (!strcmp(argv[0], "format")) { - chprintf(chp, "Attempting to format LFS...\r\n"); - ret = fs_format(&FSD1); - if (ret < 0) { - chprintf(chp, "Format failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else { - goto lfs_usage; - } - - return; - -lfs_usage: - chprintf(chp, "Usage: lfs \r\n" - " ls: List directories\r\n" - " mkdir: Make a directory\r\n" - " rm: Delete file or directory\r\n" - " cat: Dump 255 bytes of file as string\r\n" - " hexdump: Dump 255 bytes of file as hex\r\n" - "\r\n" - " mount: Mount LFS\r\n" - " unmount: Unmount LFS\r\n" - " format: Format eMMC for LFS\r\n" - "\r\n"); - return; -} - diff --git a/src/f4/app_cantest/source/test_lfs.h b/src/f4/app_cantest/source/test_lfs.h deleted file mode 100644 index 3867f5ce..00000000 --- a/src/f4/app_cantest/source/test_lfs.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_LFS_H_ -#define _TEST_LFS_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_lfs(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_cantest/source/test_time.c b/src/f4/app_cantest/source/test_time.c deleted file mode 100644 index 08bb44d8..00000000 --- a/src/f4/app_cantest/source/test_time.c +++ /dev/null @@ -1,68 +0,0 @@ -#include -#include -#include "test_time.h" -#include "rtc.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* Time */ -/*===========================================================================*/ -void cmd_time(BaseSequentialStream *chp, int argc, char *argv[]) -{ - RTCDateTime timespec; - uint32_t msec; - time_scet_t scet; - time_utc_t utc; - if (argc < 1) { - goto time_usage; - } - if (!strcmp(argv[0], "unix")) { - if (!strcmp(argv[1], "get")) { - time_t unix_time = rtcGetTimeUnix(&msec); - char *timestr = ctime(&unix_time); - chprintf(chp, "UNIX Time: %d\r\n" - "Date: %s\r\n", - unix_time, timestr); - } else if (!strcmp(argv[1], "set") && argc > 2) { - rtcSetTimeUnix(strtoul(argv[2], NULL, 0), 0); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "scet")) { - if (!strcmp(argv[1], "get")) { - rtcGetTimeSCET(&scet); - chprintf(chp, "SCET Time: %u.%u\r\n", scet.coarse, scet.fine); - } else if (!strcmp(argv[1], "set") && argc > 3) { - scet.coarse = strtoul(argv[2], NULL, 0); - scet.fine = strtoul(argv[3], NULL, 0); - rtcSetTimeSCET(&scet); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "utc")) { - if (!strcmp(argv[1], "get")) { - rtcGetTimeUTC(&utc); - chprintf(chp, "UTC Time: Day: %u ms: %u us: %u\r\n", utc.day, utc.ms, utc.us); - } else if (!strcmp(argv[1], "set") && argc > 4) { - utc.day = strtoul(argv[2], NULL, 0); - utc.ms = strtoul(argv[3], NULL, 0); - utc.us = strtoul(argv[4], NULL, 0); - rtcSetTimeUTC(&utc); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "raw")) { - rtcGetTime(&RTCD1, ×pec); - chprintf(chp, "Year: %u Month: %u DST: %u DoW: %u Day: %u ms: %u\r\n", - timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond); - } else { - goto time_usage; - } - - return; - -time_usage: - chprintf(chp, "Usage: time unix|scet|utc|raw get|set \r\n"); - return; -} - diff --git a/src/f4/app_cantest/source/test_time.h b/src/f4/app_cantest/source/test_time.h deleted file mode 100644 index 277e16ce..00000000 --- a/src/f4/app_cantest/source/test_time.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_TIME_H_ -#define _TEST_TIME_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_time(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/Makefile b/src/f4/app_control/Makefile deleted file mode 100644 index ca05a408..00000000 --- a/src/f4/app_control/Makefile +++ /dev/null @@ -1,225 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = hard -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_control - -# Target settings. -MCU = cortex-m4 -BOARD = ORESAT_C3_V5 - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep -ODDIR := $(APP_ROOT)/od - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -ifeq ($(ORESAT),) - ORESAT = 0.5 -endif - -# generate OD.c/OD.h from oresat-configs -FW_VERSION = $(shell git describe --always) -$(shell oresat-gen-fw-files --oresat $(ORESAT) base -d $(ODDIR) -fw $(FW_VERSION) -hw $(BOARD)) -# add them -ALLCSRC += $(ODDIR)/OD.c -ALLINC += $(ODDIR) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk -include $(PROJ_SRC)/node_mgr.mk -include $(PROJ_SRC)/rtc.mk -include $(PROJ_SRC)/CO_master.mk -include $(PROJ_SRC)/fs.mk -include $(PROJ_SRC)/radio.mk -include $(PROJ_SRC)/fram.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -include $(CHIBIOS)/test/lib/test.mk -include $(CHIBIOS)/test/rt/rt_test.mk -include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk -include $(CHIBIOS)/os/various/shell/shell.mk - -# Define linker script file here -LDSCRIPT= $(PROJ_ROOT)/ld/STM32F439xI.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DSHELL_ENABLE -DSHELL_CONFIG_FILE -DFRAM_SHARED_I2C=TRUE -DMAX7310_SHARED_I2C=TRUE -DAX5043_SHARED_SPI=TRUE -DSI41XX_DEVICE=SI4112 -DUSLP_USE_SDLS=1 -DLFS_CONFIG=lfs_util_custom.h -DSTM32_FLASH_DUAL_BANK_PERMANENT=TRUE - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/f4/app_control/README.md b/src/f4/app_control/README.md deleted file mode 100644 index e5f134b0..00000000 --- a/src/f4/app_control/README.md +++ /dev/null @@ -1,18 +0,0 @@ -# OreSat C3 Firmware Application -This application implements the core C3 firmware, responsible for -interfacing with and managing all subsystems on OreSat, as well as -communicating with ground stations. This initial version simply -implements a command interface via radio, and responds with telemetry -indicating subsystem health status. - -## Directory Structure -This folder contains the root of an applications sources. It contains -several files and folders: -* [main.c](main.c): The main program file called by ChibiOS. Contains - initialization code and registers threads and functions. -* [Makefile](Makefile): The main Makefile for the application. Sources - all other build files. -* [cfg](cfg): The directory containing ChibiOS's configuration files for - this application. -* [source](source): The directory where application code is put. - Everything within this directory automatically builds. diff --git a/src/f4/app_control/cfg/CO_driver_custom.h b/src/f4/app_control/cfg/CO_driver_custom.h deleted file mode 100644 index 2e98648e..00000000 --- a/src/f4/app_control/cfg/CO_driver_custom.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define CO_CONFIG_NMT (CO_CONFIG_NMT_CALLBACK_CHANGE | \ - CO_CONFIG_NMT_MASTER | \ - CO_CONFIG_GLOBAL_FLAG_CALLBACK_PRE | \ - CO_CONFIG_GLOBAL_FLAG_TIMERNEXT) - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_SDO_CLI_ENABLE | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL | \ - CO_CONFIG_GLOBAL_FLAG_CALLBACK_PRE | \ - CO_CONFIG_GLOBAL_FLAG_TIMERNEXT | \ - CO_CONFIG_GLOBAL_FLAG_OD_DYNAMIC) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/f4/app_control/cfg/chconf.h b/src/f4/app_control/cfg/chconf.h deleted file mode 100644 index 53dfa662..00000000 --- a/src/f4/app_control/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/f4/app_control/cfg/halconf.h b/src/f4/app_control/cfg/halconf.h deleted file mode 100644 index 77a58eac..00000000 --- a/src/f4/app_control/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY TRUE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL TRUE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS TRUE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_LINE -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/f4/app_control/cfg/mcuconf.h b/src/f4/app_control/cfg/mcuconf.h deleted file mode 100644 index 709c4c46..00000000 --- a/src/f4/app_control/cfg/mcuconf.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED TRUE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 16 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 8 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 8 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSE -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSE -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLL -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 TRUE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * CRY driver system settings - */ -#define STM32_CRY_USE_CRYP1 FALSE - -#define STM32_CRY_USE_HASH1 TRUE -#define STM32_CRY_CRYP1_IRQ_PRIORITY 9 -#define STM32_CRY_HASH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_CRY_HASH1_DMA_PRIORITY 0 -#define STM32_CRY_HASH_SIZE_THRESHOLD 0 -#define STM32_CRY_HASH_DMA_ERROR_HOOK(cryp) osalSysHalt("DMA failure") - -#endif /* MCUCONF_H */ diff --git a/src/f4/app_control/cfg/shellconf.h b/src/f4/app_control/cfg/shellconf.h deleted file mode 100644 index c31de933..00000000 --- a/src/f4/app_control/cfg/shellconf.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef SHELLCONF_H -#define SHELLCONF_H - -#define SHELL_MAX_ARGUMENTS 10 -#define SHELL_USE_HISTORY TRUE -#define SHELL_USE_ESC_SEQ TRUE -#define SHELL_PROMPT_STR "OreSat> " - -#endif diff --git a/src/f4/app_control/main.c b/src/f4/app_control/main.c deleted file mode 100644 index 37ec6040..00000000 --- a/src/f4/app_control/main.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" -#include "shell.h" - -/* Project header files */ -#include "oresat.h" -#include "wdt.h" -#include "c3.h" -#include "fram.h" -#include "persist.h" -#include "fs.h" -#include "node_mgr.h" -#include "comms.h" -#include "rtc.h" -#include "CO_master.h" -#ifdef SHELL_ENABLE -#include "cli.h" -#endif - -static const oresat_node_t nodes[] = { - {0x04, 0x18, 10000, true, "Battery 0"}, - /*{0x08, 0x1D, 10000, true, "Battery 1"},*/ - {0x0C, 0x00, 10000, false, "Solar Panel 0"}, - {0x10, 0x00, 10000, false, "Solar Panel 1"}, - {0x14, 0x00, 10000, false, "Solar Panel 2"}, - {0x18, 0x00, 10000, false, "Solar Panel 3"}, - /*{0x1C, 0x00, 10000, false, "Solar Panel 4"},*/ - /*{0x20, 0x00, 10000, false, "Solar Panel 5"},*/ - /*{0x24, 0x00, 10000, false, "Solar Panel 6"},*/ - /*{0x28, 0x00, 10000, false, "Solar Panel 7"},*/ - {0x2C, 0x1C, 10000, false, "Star Tracker 0"}, - /*{0x30, 0x00, 10000, false, "Star Tracker 1"},*/ - {0x34, 0x19, 10000, false, "GPS"}, - {0x38, 0x1A, 10000, false, "ACS"}, - /*{0x3C, 0x20, 10000, false, "RWB 0"},*/ - /*{0x40, 0x21, 10000, false, "RWB 1"},*/ - /*{0x44, 0x22, 10000, false, "RWB 2"},*/ - /*{0x48, 0x23, 10000, false, "RWB 3"},*/ - {0x4C, 0x1B, 10000, false, "DxWiFi"}, - {0x50, 0x1E, 10000, false, "CFC"}, - {0, 0, 0, 0, NULL} -}; - -#ifdef SHELL_ENABLE -static worker_t cli_worker; -static thread_descriptor_t cli_desc = { - .name = "Shell", - .wbase = THD_WORKING_AREA_BASE(cli_wa), - .wend = THD_WORKING_AREA_END(cli_wa), - .prio = NORMALPRIO, - .funcp = cli, - .arg = NULL -}; -#endif -static worker_t wdt_worker; -static thread_descriptor_t wdt_desc = { - .name = "WDT", - .wbase = THD_WORKING_AREA_BASE(wdt_wa), - .wend = THD_WORKING_AREA_END(wdt_wa), - .prio = HIGHPRIO, - .funcp = wdt, - .arg = NULL -}; -static worker_t c3_worker; -static thread_descriptor_t c3_desc = { - .name = "C3", - .wbase = THD_WORKING_AREA_BASE(c3_wa), - .wend = THD_WORKING_AREA_END(c3_wa), - .prio = NORMALPRIO + 1, - .funcp = c3, - .arg = NULL -}; -static worker_t node_mgr_worker; -static thread_descriptor_t node_mgr_desc = { - .name = "Node Manager", - .wbase = THD_WORKING_AREA_BASE(node_mgr_wa), - .wend = THD_WORKING_AREA_END(node_mgr_wa), - .prio = NORMALPRIO, - .funcp = node_mgr, - .arg = (void*)&nodes -}; - -static I2CConfig i2ccfg = { - OPMODE_I2C, - 100000, - STD_DUTY_CYCLE, -}; - -static FRAMConfig framcfg = { - .i2cp = &I2CD2, - .i2ccfg = &i2ccfg, - .saddr = 0x50, -}; - -static SDCConfig sdccfg = { - .bus_width = SDC_MODE_4BIT, -}; - -static FSConfig fscfg = { - .sdcp = &SDCD1, - .sdccfg = &sdccfg, - .mmc_pwr = LINE_MMC_PWR, -}; - -static oresat_config_t oresat_conf = { - .cand = &CAND1, - .node_id = 0x01, - .bitrate = ORESAT_DEFAULT_BITRATE, -}; - -/** - * @brief App Initialization - */ -static void app_init(void) -{ -#ifdef SHELL_ENABLE - /* Initialize shell and start serial interface */ - shellInit(); - sdStart(&SD3, NULL); - /* Register shell worker thread */ - reg_worker(&cli_worker, &cli_desc, true, true); -#endif - - /* Register WDT and C3 worker thread */ - reg_worker(&wdt_worker, &wdt_desc, true, true); - reg_worker(&node_mgr_worker, &node_mgr_desc, true, true); - reg_worker(&c3_worker, &c3_desc, true, true); - start_worker(&wdt_worker); - - /* Start crypto driver */ - cryStart(&CRYD1, NULL); - - /* Initialize FRAM */ - framObjectInit(&FRAMD1); - framStart(&FRAMD1, &framcfg); - - /* Restore OD variables if available */ - persistRestoreAll(); - - /* Prepare filesystem */ - fs_init(&FSD1); - fs_start(&FSD1, &fscfg); - - /* Initialize SDO client */ - sdo_init(); - - /* Initialize and start radio systems */ - comms_init(); - comms_start(); -} - -/** - * @brief Main Application - */ -int main(void) -{ - // Initialize and start - oresat_init(&oresat_conf); - app_init(); - oresat_start(); - return 0; -} diff --git a/src/f4/app_control/source/README.md b/src/f4/app_control/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/f4/app_control/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/f4/app_control/source/beacon.c b/src/f4/app_control/source/beacon.c deleted file mode 100644 index 44436ec2..00000000 --- a/src/f4/app_control/source/beacon.c +++ /dev/null @@ -1,365 +0,0 @@ -#include "beacon.h" -#include "comms.h" -#include "CANopen.h" -#include "OD.h" -#include "ax25.h" -#include "rtc.h" -#include "crc.h" -#include "fs.h" - -/* TODO: Re-implement with OD interface */ -static const ax25_link_t ax25 = { - .dest = OD_PERSIST_APP.x6007_APRS.destCallsign, - .dest_ssid = 0, - .src = OD_PERSIST_APP.x6007_APRS.srcCallsign, - .src_ssid = 0, - .control = AX25_CTRL_UFRAME | _VAL2FLD(AX25_CTRL_U_FLD, AX25_UFRAME_UI), - .sid = AX25_PID_NONE, -}; - -static time_t unix_time; -static uint8_t bank_state; - -static const tlm_item_t tlm_aprs0[] = { - /* User-Defined APRS Start */ - { .type = TLM_MSG, .msg = "{{z" }, - /* Satellite ID */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_PERSIST_APP.x6007_APRS.satelliteID }, - /* Telemetry Version */ - { .type = TLM_VAL, .len = 1, .val = 1 }, - /* C3 State */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x6000_C3_State }, - /* Uptime */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x7000_C3_Telemetry.uptime }, - /* RTC Time */ - { .type = TLM_PTR, .len = 4, .ptr = &unix_time }, - /* MCU Temperature */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x2022_MCU_Sensors.temperature },*/ - /* MCU VREFINT */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x2022_MCU_Sensors.VREFINT },*/ - /* VBUSP Voltage */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x2022_MCU_Sensors.VBAT },*/ - /* VBUSP Current */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x2022_MCU_Sensors.VBUSP_Current },*/ - /* WDT Timeouts */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_PERSIST_STATE.x6004_persistentState.powerCycles }, - /* eMMC Usage */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7000_C3_Telemetry.emmcUsage }, - /* L-Band RX Bytes */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.lbandRX_Bytes }, - /* L-Band Valid Packets */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.lbandRX_Packets }, - /* L-Band Last RSSI */ - { .type = TLM_PTR, .len = 1, .ptr = &lband.rssi }, - /* L-Band PLL Lock TODO */ - /*{ .type = TLM_VAL, .len = 1, .val = 0 },*/ - /* UHF Temperature */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7000_C3_Telemetry.UHF_Temperature },*/ - /* UHF Forward Power */ - /*{ .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7000_C3_Telemetry.UHF_FWD_Pwr },*/ - /* UHF Reverse Power */ - /*{ .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7000_C3_Telemetry.UHF_REV_Pwr },*/ - /* UHF RX Bytes */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.UHF_RX_Bytes }, - /* UHF Valid Packets */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.UHF_RX_Packets }, - /* UHF Last RSSI */ - { .type = TLM_PTR, .len = 1, .ptr = &uhf.rssi }, - /* UHF PLL Lock TODO */ - /*{ .type = TLM_VAL, .len = 1, .val = 0 },*/ - /* FW Bank TODO */ - { .type = TLM_PTR, .len = 1, .ptr = &bank_state }, - /* EDL Sequence Count */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount }, - /* EDL Rejected Count */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_PERSIST_STATE.x6004_persistentState.EDL_RejectedCount }, - /* CAN1 Status TODO */ - /*{ .type = TLM_VAL, .len = 1, .val = 0 },*/ - /* CAN2 Status TODO */ - /*{ .type = TLM_VAL, .len = 1, .val = 0 },*/ - /* OPD Current */ - /*{ .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7000_C3_Telemetry.OPD_Current },*/ - /* OPD State TODO */ - /*{ .type = TLM_VAL, .len = 1, .val = 0 },*/ - /* Battery 0 Pack 1 vbatt */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vbattBP1 }, - /* Battery 0 Pack 1 vcell */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellBP1 }, - /* Battery 0 Pack 1 vcell Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellMaxBP1 }, - /* Battery 0 Pack 1 vcell Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellMinBP1 }, - /* Battery 0 Pack 1 vcell 1 */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcell1BP1 }, - /* Battery 0 Pack 1 vcell 2 */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcell2BP1 }, - /* Battery 0 Pack 1 vcell Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellAvgBP1 }, - /* Battery 0 Pack 1 Temperature */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureBP1 }, - /* Battery 0 Pack 1 Temperature Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureAvgBP1 }, - /* Battery 0 Pack 1 Temperature Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureMaxBP1 }, - /* Battery 0 Pack 1 Temperature Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureMinBP1 }, - /* Battery 0 Pack 1 Current */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentBP1 }, - /* Battery 0 Pack 1 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentAvgBP1 }, - /* Battery 0 Pack 1 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentMaxBP1 }, - /* Battery 0 Pack 1 Current Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentMinBP1 }, - /* Battery 0 Pack 1 State */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7001_battery.stateBP1 }, - /* Battery 0 Pack 1 Reported State Of Charge */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7001_battery.reportedStateOfChargeBP1 }, - /* Battery 0 Pack 1 Full Capacity */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.fullCapacityBP1 }, - /* Battery 0 Pack 1 Reported Capacity */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.reportedCapacityBP1 }, - /* Battery 0 Pack 2 vbatt */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vbattBP2 }, - /* Battery 0 Pack 2 vcell */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellBP2 }, - /* Battery 0 Pack 2 vcell Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellMaxBP2 }, - /* Battery 0 Pack 2 vcell Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellMinBP2 }, - /* Battery 0 Pack 2 vcell 1 */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcell1BP2 }, - /* Battery 0 Pack 2 vcell 2 */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcell2BP2 }, - /* Battery 0 Pack 2 vcell Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.vcellAvgBP2 }, - /* Battery 0 Pack 2 Temperature */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureBP2 }, - /* Battery 0 Pack 2 Temperature Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureAvgBP2 }, - /* Battery 0 Pack 2 Temperature Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureMaxBP2 }, - /* Battery 0 Pack 2 Temperature Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.temperatureMinBP2 }, - /* Battery 0 Pack 2 Current */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentBP2 }, - /* Battery 0 Pack 2 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentAvgBP2 }, - /* Battery 0 Pack 2 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentMaxBP2 }, - /* Battery 0 Pack 2 Current Min */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.currentMinBP2 }, - /* Battery 0 Pack 2 State */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7001_battery.stateBP2 }, - /* Battery 0 Pack 2 Reported State Of Charge */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7001_battery.reportedStateOfChargeBP2 }, - /* Battery 0 Pack 2 Full Capacity */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.fullCapacityBP2 }, - /* Battery 0 Pack 2 Reported Capacity */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7001_battery.reportedCapacityBP2 }, - /* Solar 0 Voltage Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.voltageAvg }, - /* Solar 0 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.currentAvg }, - /* Solar 0 Power Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.powerAvg }, - /* Solar 0 Voltage Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.voltageMax }, - /* Solar 0 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.currentMax }, - /* Solar 0 Power Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.powerMax }, - /* Solar 0 Energy */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7003_solarPanel.energy }, - /* Solar 1 Voltage Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.voltageAvg }, - /* Solar 1 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.currentAvg }, - /* Solar 1 Power Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.powerAvg }, - /* Solar 1 Voltage Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.voltageMax }, - /* Solar 1 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.currentMax }, - /* Solar 1 Power Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.powerMax }, - /* Solar 1 Energy */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7004_solarPanel.energy }, - /* Solar 2 Voltage Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.voltageAvg }, - /* Solar 2 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.currentAvg }, - /* Solar 2 Power Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.powerAvg }, - /* Solar 2 Voltage Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.voltageMax }, - /* Solar 2 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.currentMax }, - /* Solar 2 Power Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.powerMax }, - /* Solar 2 Energy */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7005_solarPanel.energy }, - /* Solar 3 Voltage Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.voltageAvg }, - /* Solar 3 Current Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.currentAvg }, - /* Solar 3 Power Avg */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.powerAvg }, - /* Solar 3 Voltage Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.voltageMax }, - /* Solar 3 Current Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.currentMax }, - /* Solar 3 Power Max */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.powerMax }, - /* Solar 3 Energy */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x7006_solarPanel.energy }, - /* Star Tracker FS Usage */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700B_starTracker.rootPartitionPercent }, - /* Star Tracker Readable Files */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700B_starTracker.freadCacheLength }, - /* Star Tracker Updater Status */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700B_starTracker.updaterStatus }, - /* Star Tracker Updates Cached */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700B_starTracker.updatesAvailable }, - /* Star Tracker Right Ascension */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700B_starTracker.rightAscension }, - /* Star Tracker Declination */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700B_starTracker.declination }, - /* Star Tracker Roll */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700B_starTracker.roll }, - /* Star Tracker Timestamp TODO */ - { .type = TLM_VAL, .len = 4, .val = 0 }, - /* GPS FS Usage */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.rootPartitionPercent }, - /* GPS Readable Files */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.freadCacheLength }, - /* GPS Updater Status */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.updaterStatus }, - /* GPS Updates Cached */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.updatesAvailable }, - /* GPS Status */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.GPS_Status }, - /* GPS Number of Satellites Locked */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700D_GPS.satellitesLocked }, - /* GPS X Pos */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.positionX }, - /* GPS Y Pos */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.positionY }, - /* GPS Z Pos */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.positionZ }, - /* GPS X Velocity */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.velocityX }, - /* GPS Y Velocity */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.velocityY }, - /* GPS Z Velocity */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x700D_GPS.velocityZ }, - /* GPS Timestamp TODO */ - { .type = TLM_VAL, .len = 4, .val = 0 }, - /* ACS Roll */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700E_ACS.gyroRoll }, - /* ACS Pitch */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700E_ACS.gyroPitch }, - /* ACS Yaw */ - { .type = TLM_PTR, .len = 2, .ptr = &OD_RAM.x700E_ACS.gyroYaw }, - /* ACS IMU Temperature */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x700E_ACS.IMU_Temp }, - /* DxWiFi FS Usage */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7013_dxwifi.rootPartitionPercent }, - /* DxWiFi Readable Files */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7013_dxwifi.freadCacheLength }, - /* DxWiFi Updater Status */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7013_dxwifi.updaterStatus }, - /* DxWiFi Updates Cached */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7013_dxwifi.updatesAvailable }, - /* DxWiFi Transmitting */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7013_dxwifi.transmitting }, -#ifdef ORESAT1 - /* CFC FS Usage */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.rootPartitionPercent }, - /* CFC Readable Files */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.freadCacheLength }, - /* CFC Updater Status */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.updaterStatus }, - /* CFC Updates Cached */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.updatesAvailable }, - /* CFC Enable */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.TEC_Enable }, - /* CFC Saturated */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.TEC_Saturated }, - /* CFC Temperature */ - { .type = TLM_PTR, .len = 1, .ptr = &OD_RAM.x7014_CFC.TEC_Temperature }, - /* CFC Captures */ - { .type = TLM_PTR, .len = 4, .ptr = &OD_RAM.x7014_CFC.TEC_Captures }, -#endif /* ORESAT1 */ -}; - -static const tlm_pkt_t aprs0 = { - .item_cnt = sizeof(tlm_aprs0) / sizeof(tlm_item_t), - .item = tlm_aprs0, -}; - -void *tlm_payload(fb_t *fb, const tlm_pkt_t *pkt) -{ - void *tlm_start = fb->tail; - size_t len, total = 0;; - uint32_t crc; - - for (unsigned int i = 0; i < pkt->item_cnt; i++) { - const tlm_item_t *item = &pkt->item[i]; - switch (item->type) { - case TLM_MSG: - len = strlen(item->msg); - memcpy(fb_put(fb, len), item->msg, len); - break; - case TLM_PTR: - len = item->len; - memcpy(fb_put(fb, len), item->ptr, len); - break; - case TLM_VAL: - len = item->len; - memcpy(fb_put(fb, len), &item->val, len); - break; - default: - return NULL; - } - total += len; - } - crc = crc32(tlm_start, total, 0); - memcpy(fb_put(fb, sizeof(crc)), &crc, sizeof(crc)); - - return tlm_start; -} - -void beacon_send(const radio_cfg_t *cfg) -{ - fb_t *fb = NULL; - while (fb == NULL) { - fb = fb_alloc(AX25_MAX_FRAME_LEN, &tx_fifo); - } - - OD_RAM.x7000_C3_Telemetry.uptime = TIME_I2S(chVTGetSystemTime()); - unix_time = rtcGetTimeUnix(NULL); - bank_state = (SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE ? 1 : 0) | ((FLASH->OPTCR & FLASH_OPTCR_BFB2 ? 1 : 0) << 1); - OD_RAM.x7000_C3_Telemetry.emmcUsage = fs_usage(&FSD1); - - fb_reserve(fb, AX25_MAX_HDR_LEN); - fb->data_ptr = tlm_payload(fb, &aprs0); - fb->mac_hdr = ax25_sdu(fb, &ax25); - - /* APRS Beacon */ - ax5043TX(cfg->devp, cfg->profile, fb->data, fb->len, fb->len, NULL, NULL, false); - fb_free(fb, &tx_fifo); - fb = NULL; -} - -THD_FUNCTION(beacon, arg) -{ - const radio_cfg_t *cfg = arg; - - while (!chThdShouldTerminateX()) { - beacon_send(cfg); - chThdSleepMilliseconds(OD_PERSIST_APP.x6003_TX_Control.beaconInterval); - } - - chThdExit(MSG_OK); -} diff --git a/src/f4/app_control/source/beacon.h b/src/f4/app_control/source/beacon.h deleted file mode 100644 index c9acd06d..00000000 --- a/src/f4/app_control/source/beacon.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef _BEACON_H_ -#define _BEACON_H_ - -#include "ch.h" -#include "hal.h" -#include "radio.h" - -typedef enum { - TLM_MSG, - TLM_PTR, - TLM_VAL, -} tlm_type_t; - -typedef struct tlm_item { - tlm_type_t type; - size_t len; - union { - char *msg; - void *ptr; - uint32_t val; - }; -} tlm_item_t; - -typedef struct tlm_pkt { - size_t item_cnt; - const tlm_item_t *item; -} tlm_pkt_t; - -#ifdef __cplusplus -extern "C" { -#endif - -void beacon_send(const radio_cfg_t *cfg); -THD_FUNCTION(beacon, arg); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/c3.c b/src/f4/app_control/source/c3.c deleted file mode 100644 index 849e0933..00000000 --- a/src/f4/app_control/source/c3.c +++ /dev/null @@ -1,337 +0,0 @@ -#include "c3.h" -#include "rtc.h" -#include "fram.h" -#include "persist.h" -#include "comms.h" -#include "deployer.h" -#include "fw.h" -#include "worker.h" -#include "CANopen.h" -#include "OD.h" - -/* TODO: Re-implement with OD interface */ - -#define CHIBIOS_EPOCH 315532800U /* ChibiOS Epoch in Unix Time */ - -/* Alarm allocations */ -#define ALARM_A 0 -#define ALARM_B 1 -#define PREDEPLOY_ALARM ALARM_A /* Predeploy timeout alarm number */ -#define TX_ENABLE_ALARM ALARM_B /* TX enable timeout alarm number */ -#define EDL_ALARM ALARM_A /* EDL timeout alarm number */ -#define RESET_ALARM ALARM_A /* Hard reset alarm number */ - -#define BAT_LEVEL_LOW 6500U -#define BAT_LEVEL_HIGH 7000U -#define BAT_LOW (OD_RAM.x7001_battery.vbattBP1 < BAT_LEVEL_LOW && OD_RAM.x7001_battery.vbattBP2 < BAT_LEVEL_LOW) - -/* Global State Variables */ -thread_t *c3_tp; -static time_t boot_time; - -/** - * @brief Alarm event callback - * - * @param[in] rtcp Pointer to @p RTCDriver instance - * @param[in] event Alarm event - * - * @notapi - */ -static void alarmcb(RTCDriver *rtcp, rtcevent_t event) -{ - chSysLockFromISR(); - switch (event) { - case RTC_EVENT_ALARM_A: - rtcSetAlarm(rtcp, ALARM_A, NULL); - chEvtSignalI(c3_tp, C3_EVENT_WAKEUP); - break; - case RTC_EVENT_ALARM_B: - rtcSetAlarm(rtcp, ALARM_B, NULL); - chEvtSignalI(c3_tp, C3_EVENT_WAKEUP); - break; - case RTC_EVENT_WAKEUP: - chEvtSignalI(c3_tp, C3_EVENT_WAKEUP); - break; - default: - break; - } - chSysUnlockFromISR(); -} - -static void c3StateSave(void) -{ - /* Do not store state in predeploy */ - if (OD_RAM.x6000_C3_State[0] == PREDEPLOY) - return; - - /* Get the current state of RTC */ - rtcGetTime(&RTCD1, (RTCDateTime*)(&OD_PERSIST_STATE.x6004_persistentState.timestamp)); - if (RTCD1.rtc->CR & RTC_CR_ALRAE) { - rtcGetAlarm(&RTCD1, ALARM_A, (RTCAlarm*)(&OD_PERSIST_STATE.x6004_persistentState.alarmA)); - } else { - OD_PERSIST_STATE.x6004_persistentState.alarmA = 0; - } - if (RTCD1.rtc->CR & RTC_CR_ALRBE) { - rtcGetAlarm(&RTCD1, ALARM_B, (RTCAlarm*)(&OD_PERSIST_STATE.x6004_persistentState.alarmB)); - } else { - OD_PERSIST_STATE.x6004_persistentState.alarmB = 0; - } - if (RTCD1.rtc->CR & RTC_CR_WUTE) { - rtcSTM32GetPeriodicWakeup(&RTCD1, (RTCWakeup*)(&OD_PERSIST_STATE.x6004_persistentState.wakeup)); - } else { - OD_PERSIST_STATE.x6004_persistentState.wakeup = 0; - } - /* Write state to FRAM */ - persistStoreGroup(&OD_PERSIST_STATE); - /* TODO: Backup/sync with external RTC */ -} - -static void c3StateRestore(void) -{ - time_t unix; - - /* Read the stored state from FRAM */ - persistRestoreGroup(&OD_PERSIST_STATE); - unix = rtcConvertDateTimeToUnix((RTCDateTime*)(&OD_PERSIST_STATE.x6004_persistentState.timestamp), NULL); - - /* TODO: Get RTC values from external RTC and reach quorum */ - if (difftime(unix, rtcGetTimeUnix(NULL)) > 0) { - /* Stored state timestamp is greater */ - rtcSetTime(&RTCD1, (RTCDateTime*)(&OD_PERSIST_STATE.x6004_persistentState.timestamp)); - } - - /* Apply state */ - if (OD_PERSIST_STATE.x6004_persistentState.alarmA != 0) { - rtcSetAlarm(&RTCD1, ALARM_A, (RTCAlarm*)(&OD_PERSIST_STATE.x6004_persistentState.alarmA)); - } - if (OD_PERSIST_STATE.x6004_persistentState.alarmB != 0) { - rtcSetAlarm(&RTCD1, ALARM_B, (RTCAlarm*)(&OD_PERSIST_STATE.x6004_persistentState.alarmB)); - } - if (OD_PERSIST_STATE.x6004_persistentState.wakeup != 0) { - rtcSTM32SetPeriodicWakeup(&RTCD1, (RTCWakeup*)(&OD_PERSIST_STATE.x6004_persistentState.wakeup)); - } -} - -bool delay_deploy(void) -{ - return (difftime(rtcGetTimeUnix(NULL), CHIBIOS_EPOCH) < OD_PERSIST_APP.x6002_deploymentControl.timeout); -} - -/* TODO: Re-enable battery monitoring using new OD interface */ -/* -CO_SDO_abortCode_t OD_BATT_CALLBACK(CO_ODF_arg_t *ODF_arg) -{ - if (!ODF_arg->reading) { - chEvtSignal(c3_tp, C3_EVENT_BAT); - } - - return CO_SDO_AB_NONE; -} -*/ - -bool bat_good(void) -{ - static bool good = true; - - if (good && BAT_LOW) { - good = false; - } else if (!good && !BAT_LOW) { - good = true; - } - - return good; -} - -bool tx_enabled(void) -{ - return (difftime(rtcGetTimeUnix(NULL), OD_PERSIST_STATE.x6004_persistentState.lastTX_Enable) < OD_PERSIST_APP.x6003_TX_Control.timeout); -} - -bool edl_enabled(void) -{ - return (difftime(rtcGetTimeUnix(NULL), OD_PERSIST_STATE.x6004_persistentState.lastEDL) < OD_PERSIST_APP.x6001_stateControl.EDL_Timeout); -} - -bool trigger_reset(void) -{ - return (difftime(rtcGetTimeUnix(NULL), boot_time) >= OD_PERSIST_APP.x6001_stateControl.resetTimeout); -} - -void set_alarm(rtcalarm_t alrm, time_t start, int days, int hours, int minutes, int seconds) -{ - RTCDateTime ref_time; - RTCAlarm alarm; - - /* Encode alarm value */ - rtcConvertUnixToDateTime(&ref_time, start, 0); - alarm.alrmr = rtcEncodeRelAlarm(&ref_time, days, hours, minutes, seconds); - - /* Set alarm */ - rtcSetAlarm(&RTCD1, alrm, &alarm); -} - -/* Main Command, Communications, and Control Thread */ -THD_WORKING_AREA(c3_wa, 0x400); -THD_FUNCTION(c3, arg) -{ - (void)arg; - - c3_tp = chThdGetSelfX(); - rtcSetCallback(&RTCD1, alarmcb); - /*CO_OD_configure(CO->SDO[0], OD_7001_battery, OD_BATT_CALLBACK, NULL, NULL, 0);*/ - - /* Restore saved state */ - c3StateRestore(); - - /* Log boot time */ - boot_time = rtcGetTimeUnix(NULL); - - /* Increment power cycles */ - OD_PERSIST_STATE.x6004_persistentState.powerCycles++; - - /* State loop */ - while (!chThdShouldTerminateX()) { - RTCWakeup wakeup; - switch (OD_RAM.x6000_C3_State[0]) { - case PREDEPLOY: - /* Check if pre-deployment timeout has occured */ - if (delay_deploy()) { - /* Must wait for pre-deployment timeout */ - set_alarm(PREDEPLOY_ALARM, CHIBIOS_EPOCH, 0, 0, 0, OD_PERSIST_APP.x6002_deploymentControl.timeout); - /* Initially enable TX */ - tx_enable(true); - chEvtWaitAny(C3_EVENT_WAKEUP | C3_EVENT_TERMINATE); - } else { - /* Enter deploy state */ - OD_RAM.x6000_C3_State[0] = DEPLOY; - } - break; - case DEPLOY: - /* Set RTC wakeup alarm for state saving */ - wakeup.wutr = (RTC_CR_WUCKSEL_2 << 16) | (OD_PERSIST_APP.x6001_stateControl.saveInterval - 1); - rtcSTM32SetPeriodicWakeup(&RTCD1, &wakeup); - - /* Initiate antenna deployment if needed */ - static uint8_t attempts = 0; - if (!OD_PERSIST_STATE.x6004_persistentState.deployed && attempts < OD_PERSIST_APP.x6002_deploymentControl.attempts) { - if (bat_good()) { - deploy_heli(OD_PERSIST_APP.x6002_deploymentControl.actuationTime); - deploy_turn(OD_PERSIST_APP.x6002_deploymentControl.actuationTime); - attempts++; - } else { - chEvtWaitAny(C3_EVENT_WAKEUP | C3_EVENT_TERMINATE | C3_EVENT_BAT); - } - } else { - /* Enter standy state */ - OD_RAM.x6000_C3_State[0] = STANDBY; - OD_PERSIST_STATE.x6004_persistentState.deployed = 1; - attempts = 0; - } - break; - case STANDBY: - beacon_enable(false); - - if (edl_enabled()) { - OD_RAM.x6000_C3_State[0] = EDL; - } else if (trigger_reset()) { - hard_reset(); - } else if (tx_enabled() && bat_good()) { - OD_RAM.x6000_C3_State[0] = BEACON; - } else { - chEvtWaitAny(C3_EVENT_WAKEUP | C3_EVENT_TERMINATE | C3_EVENT_TX | C3_EVENT_BAT | C3_EVENT_EDL); - } - break; - case BEACON: - beacon_enable(true); - - if (edl_enabled()) { - OD_RAM.x6000_C3_State[0] = EDL; - } else if (trigger_reset()) { - hard_reset(); - } else if (!tx_enabled() || !bat_good()) { - OD_RAM.x6000_C3_State[0] = STANDBY; - } else { - chEvtWaitAny(C3_EVENT_WAKEUP | C3_EVENT_TERMINATE | C3_EVENT_TX | C3_EVENT_BAT | C3_EVENT_EDL); - } - break; - case EDL: - beacon_enable(false); - - if (!edl_enabled()) { - set_alarm(RESET_ALARM, rtcGetTimeUnix(NULL), 0, 0, 0, OD_PERSIST_APP.x6001_stateControl.resetTimeout); - if (tx_enabled() && bat_good()) { - OD_RAM.x6000_C3_State[0] = BEACON; - } else { - OD_RAM.x6000_C3_State[0] = STANDBY; - } - } else { - chEvtWaitAny(C3_EVENT_WAKEUP | C3_EVENT_TERMINATE | C3_EVENT_EDL); - } - break; - default: - OD_RAM.x6000_C3_State[0] = PREDEPLOY; - break; - }; - - c3StateSave(); - } - - rtcSetCallback(&RTCD1, NULL); - rtcSTM32SetPeriodicWakeup(&RTCD1, NULL); - rtcSetAlarm(&RTCD1, 0, NULL); - rtcSetAlarm(&RTCD1, 1, NULL); - chThdExit(MSG_OK); -} - -void tx_enable(bool state) -{ - if (state) { - OD_PERSIST_STATE.x6004_persistentState.lastTX_Enable = rtcGetTimeUnix(NULL); - set_alarm(TX_ENABLE_ALARM, OD_PERSIST_STATE.x6004_persistentState.lastTX_Enable, 0, 0, 0, OD_PERSIST_APP.x6003_TX_Control.timeout); - } else { - OD_PERSIST_STATE.x6004_persistentState.lastTX_Enable = 0; - rtcSetAlarm(&RTCD1, TX_ENABLE_ALARM, NULL); - } - chEvtSignal(c3_tp, C3_EVENT_TX); -} - -void edl_enable(bool state) -{ - /* Do not enable EDL if in predeploy state */ - if (OD_RAM.x6000_C3_State[0] == PREDEPLOY) - return; - - if (state) { - OD_PERSIST_STATE.x6004_persistentState.lastEDL = rtcGetTimeUnix(NULL); - set_alarm(EDL_ALARM, OD_PERSIST_STATE.x6004_persistentState.lastEDL, 0, 0, 0, OD_PERSIST_APP.x6001_stateControl.EDL_Timeout); - } else { - OD_PERSIST_STATE.x6004_persistentState.lastEDL = 0; - rtcSetAlarm(&RTCD1, TX_ENABLE_ALARM, NULL); - } - chEvtSignal(c3_tp, C3_EVENT_EDL); -} - -void soft_reset(void) -{ - c3StateSave(); - NVIC_SystemReset(); -} - -void hard_reset(void) -{ - c3StateSave(); - stop_workers(true); - chThdSleepSeconds(60); - NVIC_SystemReset(); -} - -void factory_reset(void) -{ - chThdTerminate(c3_tp); - chEvtSignal(c3_tp, C3_EVENT_TERMINATE); - chThdWait(c3_tp); - framErase(&FRAMD1, FRAM_STATE_ADDR, FRAM_SIZE - FRAM_STATE_ADDR); - RCC->BDCR |= RCC_BDCR_BDRST; - RCC->BDCR &= ~RCC_BDCR_BDRST; - NVIC_SystemReset(); -} diff --git a/src/f4/app_control/source/c3.h b/src/f4/app_control/source/c3.h deleted file mode 100644 index 0c8f6b4a..00000000 --- a/src/f4/app_control/source/c3.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef _C3_H_ -#define _C3_H_ - -#include "ch.h" -#include "hal.h" - -#define C3_EVENT_WAKEUP EVENT_MASK(0) -#define C3_EVENT_TERMINATE EVENT_MASK(1) -#define C3_EVENT_TX EVENT_MASK(2) -#define C3_EVENT_BAT EVENT_MASK(3) -#define C3_EVENT_EDL EVENT_MASK(4) - -typedef enum { - PREDEPLOY = 'B', - DEPLOY = 'C', - STANDBY = 'D', - BEACON = 'E', - EDL = 'F' -} c3_state_t; - -typedef struct { - event_listener_t el; - event_source_t *event; - eventflags_t flags; -} c3_event_t; - -typedef struct { - c3_state_t state; - c3_state_t next_state; - eventmask_t events; -} c3_fsm_t; - -/* Main Command, Communications, and Control Thread Prototype */ -extern THD_WORKING_AREA(c3_wa, 0x400); -extern THD_FUNCTION(c3, arg); - -/* Support function prototypes */ -void tx_enable(bool state); -void edl_enable(bool state); -void soft_reset(void); -void hard_reset(void); -void factory_reset(void); - -bool delay_deploy(void); -bool bat_good(void); -bool tx_enabled(void); -bool edl_enabled(void); - -#endif diff --git a/src/f4/app_control/source/cmd.c b/src/f4/app_control/source/cmd.c deleted file mode 100644 index 87df94e9..00000000 --- a/src/f4/app_control/source/cmd.c +++ /dev/null @@ -1,137 +0,0 @@ -#include "cmd.h" -#include "c3.h" -#include "fw.h" -#include "fs.h" -#include "opd.h" -#include "rtc.h" -#include "node_mgr.h" -#include "CO_master.h" - -void cmd_process(cmd_t *cmd, fb_t *resp_fb) -{ - lfs_file_t *file; - cmd_flash_t *flash_arg; - uint32_t *key; - void *ret; - - //Add 32 bits for sequence number - ret = fb_put(resp_fb, sizeof(uint32_t)); - //Put sequence number into the response buffer - *((uint32_t*)ret) = OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount - 1; - - switch (cmd->cmd) { - case CMD_TX_CTRL: - ret = fb_put(resp_fb, 1); - tx_enable(cmd->arg[0]); - *((uint8_t*)ret) = tx_enabled(); - break; - case CMD_FW_FLASH: - ret = fb_put(resp_fb, sizeof(int)); - flash_arg = (cmd_flash_t*)cmd->arg; - *((int*)ret) = fw_flash(&EFLD1, flash_arg->filename, flash_arg->crc); - break; - case CMD_FW_BANK: - ret = fb_put(resp_fb, sizeof(int)); - *((int*)ret) = fw_set_bank(&EFLD1, cmd->arg[0]); - break; - case CMD_FW_VERIFY: - ret = fb_put(resp_fb, sizeof(uint32_t)); - *((uint32_t*)ret) = fw_verify(&EFLD1, cmd->arg[0]); - break; - case CMD_C3_SOFTRESET: - key = (uint32_t*)cmd->arg; - if (key[0] == 0x67452301U && key[1] == 0xEFCDAB89U) - soft_reset(); - break; - case CMD_C3_HARDRESET: - key = (uint32_t*)cmd->arg; - if (key[0] == 0x67452301U && key[1] == 0xEFCDAB89U) - hard_reset(); - break; - case CMD_C3_FACTORYRESET: - key = (uint32_t*)cmd->arg; - if (key[0] == 0x67452301U && key[1] == 0xEFCDAB89U) - factory_reset(); - break; - case CMD_I2C_RESET: - ret = fb_put(resp_fb, 1); - palSetLine(LINE_I2C_PWROFF); - chThdSleepMilliseconds(10); - palClearLine(LINE_I2C_PWROFF); - *((uint8_t*)ret) = 0; - break; - case CMD_FS_FORMAT: - ret = fb_put(resp_fb, sizeof(int)); - *((int*)ret) = fs_format(&FSD1); - break; - case CMD_FS_UNMOUNT: - ret = fb_put(resp_fb, sizeof(int)); - *((int*)ret) = fs_unmount(&FSD1); - break; - case CMD_FS_REMOVE: - ret = fb_put(resp_fb, sizeof(int)); - *((int*)ret) = fs_remove(&FSD1, (char*)cmd->arg); - break; - case CMD_FS_CRC: - ret = fb_put(resp_fb, sizeof(uint32_t)); - file = file_open(&FSD1, (char*)cmd->arg, LFS_O_RDONLY); - if (file == NULL) - return; - *((uint32_t*)ret) = file_crc(&FSD1, file); - file_close(&FSD1, file); - break; - case CMD_NODE_ENABLE: - ret = fb_put(resp_fb, 1); - *((int8_t *)ret) = node_enable(cmd->arg[0], cmd->arg[1]); - break; - case CMD_NODE_STATUS: - ret = fb_put(resp_fb, sizeof(CO_NMT_internalState_t)); - node_status(cmd->arg[0], ret); - break; - case CMD_OPD_SYSENABLE: - ret = fb_put(resp_fb, 1); - opd_start(); - *((uint8_t*)ret) = 0; - break; - case CMD_OPD_SYSDISABLE: - ret = fb_put(resp_fb, 1); - opd_stop(); - *((uint8_t*)ret) = 0; - break; - case CMD_OPD_SCAN: - ret = fb_put(resp_fb, 1); - opd_scan(cmd->arg[0]); - *((uint8_t*)ret) = 0; - break; - case CMD_OPD_ENABLE: - ret = fb_put(resp_fb, 1); - *((int8_t *)ret) = opd_enable(cmd->arg[0], cmd->arg[1]); - break; - case CMD_OPD_RESET: - ret = fb_put(resp_fb, 1); - *((int8_t *)ret) = opd_reset(cmd->arg[0]); - break; - case CMD_OPD_STATUS: - ret = fb_put(resp_fb, sizeof(opd_status_t)); - opd_status(cmd->arg[0], ret); - break; - case CMD_RTC_SETTIME: - ret = fb_put(resp_fb, sizeof(uint32_t)); - rtcSetTimeUnix(*((uint32_t*)cmd->arg), 0); - *((uint32_t*)ret) = rtcGetTimeUnix(NULL); - break; - case CMD_SDO_WRITE: - ret = fb_put(resp_fb, 1); - struct __attribute__((packed)) { - uint8_t node_id; - uint16_t index; - uint8_t subindex; - size_t size; - uint8_t data[]; - } *sdo_arg = (void*)cmd->arg; - sdo_transfer(SDO_CLI_WRITE, sdo_arg->node_id, sdo_arg->index, sdo_arg->subindex, sdo_arg->size, sdo_arg->size, sdo_arg->data); - *((uint8_t*)ret) = 0; - default: - break; - } -} diff --git a/src/f4/app_control/source/cmd.h b/src/f4/app_control/source/cmd.h deleted file mode 100644 index 937e19ea..00000000 --- a/src/f4/app_control/source/cmd.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef _CMD_H_ -#define _CMD_H_ - -#include "frame_buf.h" - -typedef enum { - CMD_TX_CTRL = 0, - CMD_FW_FLASH, - CMD_FW_BANK, - CMD_FW_VERIFY, - CMD_C3_SOFTRESET, - CMD_C3_HARDRESET, - CMD_C3_FACTORYRESET, - CMD_I2C_RESET, - CMD_FS_FORMAT, - CMD_FS_UNMOUNT, - CMD_FS_REMOVE, - CMD_FS_CRC, - CMD_NODE_ENABLE, - CMD_NODE_STATUS, - CMD_OPD_SYSENABLE, - CMD_OPD_SYSDISABLE, - CMD_OPD_SCAN, - CMD_OPD_ENABLE, - CMD_OPD_RESET, - CMD_OPD_STATUS, - CMD_RTC_SETTIME, - CMD_SDO_WRITE, -} cmd_code_t; - -typedef struct { - uint32_t crc; - char filename[]; -} cmd_flash_t; - -typedef struct { - cmd_code_t cmd; - uint8_t arg[]; -} cmd_t; - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_process(cmd_t *cmd, fb_t *resp_fb); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/comms.c b/src/f4/app_control/source/comms.c deleted file mode 100644 index 9bfb5dd0..00000000 --- a/src/f4/app_control/source/comms.c +++ /dev/null @@ -1,739 +0,0 @@ -#include "ch.h" -#include "hal.h" -#include "comms.h" -#include "beacon.h" -#include "c3.h" -#include "cmd.h" -#include "file_xfr.h" -#include "rtc.h" -#include "uslp.h" -#include "hmac.h" -#include "CANopen.h" -#include "OD.h" - -static inline void vc_lock(void *arg) { - mutex_t *mutex = arg; - chMtxLock(mutex); -} - -static inline void vc_unlock(void *arg) { - mutex_t *mutex = arg; - chMtxUnlock(mutex); -} - -#if (USLP_USE_SDLS == TRUE) -static const sdls_cfg_t sdls_cfg = { - .spi = 1, - .iv_len = 0, - .seq_num_len = sizeof(OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount), - .pad_len = 0, - .mac_len = 32, - .send_func = NULL, - .send_arg = NULL, - .recv_func = hmac_recv, - .recv_arg = OD_PERSIST_KEYS.x6005_cryptoKeys[0], -}; -#endif - -static const uslp_map_t map_cmd = { - .sdu = SDU_MAP_ACCESS, - .upid = UPID_MAPA_SDU, - .max_pkt_len = CMD_RESP_LEN, - .incomplete = false, - .map_recv = comms_cmd, -}; - -static const uslp_map_t map_file = { - .sdu = SDU_MAP_ACCESS, - .upid = UPID_MAPA_SDU, - .max_pkt_len = FILE_BUF_LEN + sizeof(file_xfr_t), - .incomplete = false, - .map_recv = comms_file, -}; - -static const uslp_map_t map_beacon = { - .sdu = SDU_MAP_ACCESS, - .upid = UPID_MAPA_SDU, - .max_pkt_len = 32, - .incomplete = false, - .map_recv = comms_beacon, -}; - -static const uslp_vc_t vc0 = { - .seq_ctrl_len = 0, - .expedited_len = 0, - .seq_ctrl_cnt = NULL, - .expedited_cnt = NULL, - .cop = COP_NONE, - .mapid[0] = &map_cmd, - .trunc_tf_len = USLP_MAX_LEN, - .ocf = false, -#if (USLP_USE_SDLS == TRUE) - .sdls_cfg = &sdls_cfg, -#endif -}; - -static const uslp_vc_t vc1 = { - .seq_ctrl_len = 0, - .expedited_len = 0, - .seq_ctrl_cnt = NULL, - .expedited_cnt = NULL, - .cop = COP_NONE, - .mapid[0] = &map_file, - .mapid[1] = &map_beacon, - .trunc_tf_len = USLP_MAX_LEN, - .ocf = false, -#if (USLP_USE_SDLS == TRUE) - .sdls_cfg = NULL, -#endif -}; - -/* -static MUTEX_DECL(vc2_lock); -static const uslp_vc_t vc2 = { - .seq_ctrl_len = sizeof(OD_PERSIST_STATE.x6004_persistentState.VC2_SequenceCount), - .expedited_len = sizeof(OD_PERSIST_STATE.x6004_persistentState.VC2_ExpediteCount), - .seq_ctrl_cnt = &OD_PERSIST_STATE.x6004_persistentState.VC2_SequenceCount, - .expedited_cnt = &OD_PERSIST_STATE.x6004_persistentState.VC2_ExpediteCount, - .cop = COP_1, - .mapid[0] = &map_cmd, - .mapid[1] = &map_file, - .trunc_tf_len = USLP_MAX_LEN, - .ocf = true, - .lock_arg = &vc2_lock, - .lock = vc_lock, - .unlock = vc_unlock, -#if (USLP_USE_SDLS == TRUE) - .sdls_cfg = &sdls_cfg, -#endif -}; -*/ - -const uslp_mc_t mc = { - .scid = &OD_PERSIST_APP.x6006_CCSDS.spacecraftID, - .owner = true, - .vcid[0] = &vc0, - .vcid[1] = &vc1, - /*.vcid[2] = &vc2,*/ -}; - -static const uslp_pc_t lband_pc = { - .name = "L-Band", - .tf_len = USLP_MAX_LEN, - .fecf = FECF_HW, - .fecf_len = FECF_LEN, -}; - -static const uslp_pc_t uhf_pc = { - .name = "UHF", - .tf_len = USLP_MAX_LEN, - .fecf = FECF_HW, - .fecf_len = FECF_LEN, - .phy_send = pdu_send, - .phy_send_ahead = pdu_send_ahead, - .send_arg = &tx_fifo, - .send_ahead_arg = &tx_fifo, -}; - -static const uslp_link_t edl_lband_link = { - .mc = &mc, - .pc_rx = &lband_pc, - .pc_tx = &uhf_pc, -}; - -static const uslp_link_t edl_uhf_link = { - .mc = &mc, - .pc_rx = &uhf_pc, - .pc_tx = &uhf_pc, -}; - -static const ax5043_profile_t lband_high[] = { - /* Modulation and Framing */ - {AX5043_REG_MODULATION, AX5043_MODULATION_MSK, 1}, - {AX5043_REG_ENCODING, AX5043_ENCODING_NRZI_SCRAM, 1}, - {AX5043_REG_FRAMING, _VAL2FLD(AX5043_FRAMING_FRMMODE, AX5043_FRMMODE_HDLC) | - _VAL2FLD(AX5043_FRAMING_CRCMODE, AX5043_CRCMODE_CCITT), 1}, - - /* Pin Configuration */ - {AX5043_REG_PINFUNCSYSCLK, AX5043_PFSYSCLK_OUT_XTAL_DIV1, 1}, - - /* Synthesizer */ - {AX5043_REG_PLLCPI, 0x01, 1}, - {AX5043_REG_FREQA, 0x1C900001, 4}, - - /* PHY Layer Parameters */ - /* Receiver Parameters */ - {AX5043_REG_IFFREQ, 0x170A, 2}, - {AX5043_REG_DECIMATION, 0x01, 1}, - {AX5043_REG_RXDATARATE, 0x0042AB, 3}, - {AX5043_REG_MAXDROFFSET, 0x000000, 3}, - {AX5043_REG_MAXRFOFFSET, 0x0003BE | AX5043_MAXRFOFFSET_FREQOFFSCORR, 3}, - - /* Receiver Parameter Set 0 */ - {AX5043_REG_AGCGAIN0, _VAL2FLD(AX5043_AGCGAIN_AGCDECAY, 0x08) | - _VAL2FLD(AX5043_AGCGAIN_AGCATTACK, 0x03), 1}, - {AX5043_REG_AGCTARGET0, 0x89, 1}, - {AX5043_REG_TIMEGAIN0, _VAL2FLD(AX5043_TIMEGAIN_E, 0x09) | - _VAL2FLD(AX5043_TIMEGAIN_M, 0x08), 1}, - {AX5043_REG_DRGAIN0, _VAL2FLD(AX5043_DRGAIN_E, 0x03) | - _VAL2FLD(AX5043_DRGAIN_M, 0x08), 1}, - {AX5043_REG_FREQDEV0, 0x0000, 2}, - - /* Receiver Parameter Set 1 */ - /* TODO */ - - /* Receiver Parameter Set 2 */ - /* TODO */ - - /* Receiver Parameter Set 3 */ - /* TODO */ - - /* Transmitter Parameters */ - {AX5043_REG_TXPWRCOEFFB, 0x0000, 2}, - - /* PLL Parameters */ - {AX5043_REG_PLLVCOI, _VAL2FLD(AX5043_PLLVCOI_VCOI, 0x16) | - AX5043_PLLVCOI_VCOIE, 1}, - - /* MAC Layer Parameters */ - /* Packet Format */ - {AX5043_REG_PKTADDRCFG, AX5043_PKTADDRCFG_MSBFIRST | AX5043_PKTADDRCFG_FECSYNCDIS, 1}, - {AX5043_REG_PKTLENCFG, _VAL2FLD(AX5043_PKTLENCFG_LENBITS, 0xF), 1}, - {AX5043_REG_PKTMAXLEN, 0xFF, 1}, - /*{AX5043_REG_PKTADDR, _VAL2FLD(USLP_TFPH_ID_MCID, MCID) | USLP_TFPH_ID_SRC_DST, 4},*/ - /*{AX5043_REG_PKTADDRMASK, USLP_TFPH_ID_MCID | USLP_TFPH_ID_SRC_DST, 4},*/ - - /* Pattern Match */ - - /* Packet Controller */ - {AX5043_REG_PKTCHUNKSIZE, AX5043_PKTCHUNKSIZE_240, 1}, - {AX5043_REG_PKTMISCFLAGS, AX5043_PKTMISCFLAGS_BGNDRSSI, 1}, - {AX5043_REG_PKTSTOREFLAGS, AX5043_PKTSTOREFLAGS_RSSI | AX5043_PKTSTOREFLAGS_CRCB, 1}, - {AX5043_REG_PKTACCEPTFLAGS, AX5043_PKTACCEPTFLAGS_LRGP, 1}, - - /* Performance Tuning Registers */ - {AX5043_REG_0xF00, AX5043_0xF00_DEFVAL, 1}, - {AX5043_REG_0xF08, AX5043_0xF08_DEFVAL, 1}, - {AX5043_REG_0xF0D, AX5043_0xF0D_DEFVAL, 1}, - {AX5043_REG_0xF10, AX5043_0xF10_TCXO, 1}, - {AX5043_REG_0xF11, AX5043_0xF11_TCXO, 1}, - {AX5043_REG_0xF18, 0x02, 1}, - {AX5043_REG_0xF1C, AX5043_0xF1C_DEFVAL, 1}, - {AX5043_REG_0xF21, 0x68, 1}, - {AX5043_REG_0xF22, 0xFF, 1}, - {AX5043_REG_0xF23, 0x84, 1}, - {AX5043_REG_0xF26, 0x98, 1}, - {AX5043_REG_0xF35, AX5043_0xF35_XTALDIV1, 1}, - {AX5043_REG_0xF44, 0x25, 1}, - {AX5043_REG_0xF72, AX5043_0xF72_NORAWSOFTBITS, 1}, - {0, 0, 0} -}; - -static const ax5043_profile_t lband_low[] = { - /* Modulation and Framing */ - {AX5043_REG_MODULATION, AX5043_MODULATION_FSK, 1}, - {AX5043_REG_ENCODING, AX5043_ENCODING_NRZI_SCRAM, 1}, - {AX5043_REG_FRAMING, _VAL2FLD(AX5043_FRAMING_FRMMODE, AX5043_FRMMODE_HDLC) | - _VAL2FLD(AX5043_FRAMING_CRCMODE, AX5043_CRCMODE_CCITT), 1}, - - /* Pin Configuration */ - {AX5043_REG_PINFUNCSYSCLK, AX5043_PFSYSCLK_OUT_XTAL_DIV1, 1}, - - /* Synthesizer */ - {AX5043_REG_PLLCPI, 0x01, 1}, - {AX5043_REG_FREQA, 0x1C900001, 4}, - - /* PHY Layer Parameters */ - /* Receiver Parameters */ - {AX5043_REG_IFFREQ, 0x0E78, 2}, - {AX5043_REG_DECIMATION, 0x02, 1}, - {AX5043_REG_RXDATARATE, 0x0042AB, 3}, - {AX5043_REG_MAXDROFFSET, 0x000000, 3}, - {AX5043_REG_MAXRFOFFSET, 0x0003BE | AX5043_MAXRFOFFSET_FREQOFFSCORR, 3}, - - /* Receiver Parameter Set 0 */ - {AX5043_REG_AGCGAIN0, _VAL2FLD(AX5043_AGCGAIN_AGCDECAY, 0x09) | - _VAL2FLD(AX5043_AGCGAIN_AGCATTACK, 0x03), 1}, - {AX5043_REG_AGCTARGET0, 0x89, 1}, - {AX5043_REG_TIMEGAIN0, _VAL2FLD(AX5043_TIMEGAIN_E, 0x09) | - _VAL2FLD(AX5043_TIMEGAIN_M, 0x08), 1}, - {AX5043_REG_DRGAIN0, _VAL2FLD(AX5043_DRGAIN_E, 0x03) | - _VAL2FLD(AX5043_DRGAIN_M, 0x08), 1}, - {AX5043_REG_FREQDEV0, 0x0000, 2}, - - /* Receiver Parameter Set 1 */ - /* TODO */ - - /* Receiver Parameter Set 2 */ - /* TODO */ - - /* Receiver Parameter Set 3 */ - /* TODO */ - - /* Transmitter Parameters */ - {AX5043_REG_TXPWRCOEFFB, 0x0000, 2}, - - /* PLL Parameters */ - {AX5043_REG_PLLVCOI, _VAL2FLD(AX5043_PLLVCOI_VCOI, 0x16) | - AX5043_PLLVCOI_VCOIE, 1}, - - /* MAC Layer Parameters */ - /* Packet Format */ - {AX5043_REG_PKTADDRCFG, AX5043_PKTADDRCFG_MSBFIRST | AX5043_PKTADDRCFG_FECSYNCDIS, 1}, - {AX5043_REG_PKTLENCFG, _VAL2FLD(AX5043_PKTLENCFG_LENBITS, 0xF), 1}, - {AX5043_REG_PKTMAXLEN, 0xFF, 1}, - /*{AX5043_REG_PKTADDR, _VAL2FLD(USLP_TFPH_ID_MCID, MCID) | USLP_TFPH_ID_SRC_DST, 4},*/ - /*{AX5043_REG_PKTADDRMASK, USLP_TFPH_ID_MCID | USLP_TFPH_ID_SRC_DST, 4},*/ - - /* Pattern Match */ - - /* Packet Controller */ - {AX5043_REG_PKTCHUNKSIZE, AX5043_PKTCHUNKSIZE_240, 1}, - {AX5043_REG_PKTMISCFLAGS, AX5043_PKTMISCFLAGS_BGNDRSSI, 1}, - {AX5043_REG_PKTSTOREFLAGS, AX5043_PKTSTOREFLAGS_RSSI | AX5043_PKTSTOREFLAGS_CRCB, 1}, - {AX5043_REG_PKTACCEPTFLAGS, AX5043_PKTACCEPTFLAGS_LRGP, 1}, - - /* Performance Tuning Registers */ - {AX5043_REG_0xF00, AX5043_0xF00_DEFVAL, 1}, - {AX5043_REG_0xF08, AX5043_0xF08_DEFVAL, 1}, - {AX5043_REG_0xF0D, AX5043_0xF0D_DEFVAL, 1}, - {AX5043_REG_0xF10, AX5043_0xF10_TCXO, 1}, - {AX5043_REG_0xF11, AX5043_0xF11_TCXO, 1}, - {AX5043_REG_0xF18, 0x02, 1}, - {AX5043_REG_0xF1C, AX5043_0xF1C_DEFVAL, 1}, - {AX5043_REG_0xF21, 0x68, 1}, - {AX5043_REG_0xF22, 0xFF, 1}, - {AX5043_REG_0xF23, 0x84, 1}, - {AX5043_REG_0xF26, 0x98, 1}, - {AX5043_REG_0xF35, AX5043_0xF35_XTALDIV1, 1}, - {AX5043_REG_0xF44, 0x25, 1}, - {AX5043_REG_0xF72, AX5043_0xF72_NORAWSOFTBITS, 1}, - {0, 0, 0} -}; - -static const ax5043_profile_t uhf_eng[] = { - /* Modulation and Framing */ - {AX5043_REG_MODULATION, AX5043_MODULATION_MSK, 1}, - {AX5043_REG_ENCODING, AX5043_ENCODING_NRZI_SCRAM, 1}, - {AX5043_REG_FRAMING, _VAL2FLD(AX5043_FRAMING_FRMMODE, AX5043_FRMMODE_HDLC) | - _VAL2FLD(AX5043_FRAMING_CRCMODE, AX5043_CRCMODE_CCITT), 1}, - - /* Pin Configuration */ - {AX5043_REG_PINFUNCSYSCLK, AX5043_PFSYSCLK_OUT_0, 1}, - - /* Synthesizer */ - {AX5043_REG_PLLCPI, 0x02, 1}, - {AX5043_REG_FREQA, 0x1B480001, 4}, - - /* PHY Layer Parameters */ - /* Receiver Parameters */ - {AX5043_REG_IFFREQ, 0x1058, 2}, - {AX5043_REG_DECIMATION, 0x01, 1}, - {AX5043_REG_RXDATARATE, 0x005355, 3}, - {AX5043_REG_MAXDROFFSET, 0x000000, 3}, - {AX5043_REG_MAXRFOFFSET, 0x000393 | AX5043_MAXRFOFFSET_FREQOFFSCORR, 3}, - - /* Receiver Parameter Set 0 */ - {AX5043_REG_AGCGAIN0, _VAL2FLD(AX5043_AGCGAIN_AGCDECAY, 0x08) | - _VAL2FLD(AX5043_AGCGAIN_AGCATTACK, 0x03), 1}, - {AX5043_REG_AGCTARGET0, 0x89, 1}, - {AX5043_REG_TIMEGAIN0, _VAL2FLD(AX5043_TIMEGAIN_E, 0x09) | - _VAL2FLD(AX5043_TIMEGAIN_M, 0x0A), 1}, - {AX5043_REG_DRGAIN0, _VAL2FLD(AX5043_DRGAIN_E, 0x03) | - _VAL2FLD(AX5043_DRGAIN_M, 0x0A), 1}, - {AX5043_REG_FREQDEV0, 0x0000, 2}, - - /* Receiver Parameter Set 1 */ - /* TODO */ - - /* Receiver Parameter Set 2 */ - /* TODO */ - - /* Receiver Parameter Set 3 */ - /* TODO */ - - /* Transmitter Parameters */ - {AX5043_REG_MODCFGF, AX5043_FREQSHAPE_GAUSS_BT_0_5, 1}, - {AX5043_REG_FSKDEV, 0x00624E, 3}, - {AX5043_REG_MODCFGA, AX5043_MODCFGA_TXSE | _VAL2FLD(AX5043_MODCFGA_AMPLSHAPE, AX5043_AMPLSHAPE_RAISEDCOS), 1}, - {AX5043_REG_TXRATE, 0x018937, 3}, - {AX5043_REG_TXPWRCOEFFB, 0x0FFF, 2}, - - /* PLL Parameters */ - {AX5043_REG_PLLVCOI, _VAL2FLD(AX5043_PLLVCOI_VCOI, 0x16) | - AX5043_PLLVCOI_VCOIE, 1}, - - /* MAC Layer Parameters */ - /* Packet Format */ - {AX5043_REG_PKTADDRCFG, AX5043_PKTADDRCFG_MSBFIRST | AX5043_PKTADDRCFG_FECSYNCDIS, 1}, - {AX5043_REG_PKTLENCFG, _VAL2FLD(AX5043_PKTLENCFG_LENBITS, 0xF), 1}, - {AX5043_REG_PKTMAXLEN, 0xFF, 1}, - /*{AX5043_REG_PKTADDR, _VAL2FLD(USLP_TFPH_ID_MCID, MCID) | USLP_TFPH_ID_SRC_DST, 4},*/ - /*{AX5043_REG_PKTADDRMASK, USLP_TFPH_ID_MCID | USLP_TFPH_ID_SRC_DST, 4},*/ - - /* Pattern Match */ - - /* Packet Controller */ - {AX5043_REG_PKTCHUNKSIZE, AX5043_PKTCHUNKSIZE_240, 1}, - {AX5043_REG_PKTMISCFLAGS, AX5043_PKTMISCFLAGS_BGNDRSSI, 1}, - {AX5043_REG_PKTSTOREFLAGS, AX5043_PKTSTOREFLAGS_RSSI | AX5043_PKTSTOREFLAGS_CRCB, 1}, - {AX5043_REG_PKTACCEPTFLAGS, AX5043_PKTACCEPTFLAGS_LRGP, 1}, - - /* Performance Tuning Registers */ - {AX5043_REG_0xF00, AX5043_0xF00_DEFVAL, 1}, - {AX5043_REG_0xF08, AX5043_0xF08_DEFVAL, 1}, - {AX5043_REG_0xF0D, AX5043_0xF0D_DEFVAL, 1}, - {AX5043_REG_0xF10, AX5043_0xF10_TCXO, 1}, - {AX5043_REG_0xF11, AX5043_0xF11_TCXO, 1}, - {AX5043_REG_0xF18, 0x06, 1}, - {AX5043_REG_0xF1C, AX5043_0xF1C_DEFVAL, 1}, - {AX5043_REG_0xF21, 0x68, 1}, - {AX5043_REG_0xF22, 0xFF, 1}, - {AX5043_REG_0xF23, 0x84, 1}, - {AX5043_REG_0xF26, 0x98, 1}, - {AX5043_REG_0xF35, AX5043_0xF35_XTALDIV1, 1}, - {AX5043_REG_0xF44, 0x25, 1}, - {AX5043_REG_0xF72, AX5043_0xF72_NORAWSOFTBITS, 1}, - {0, 0, 0} -}; - -static const ax5043_profile_t uhf_ax25[] = { - /* Modulation and Framing */ - {AX5043_REG_MODULATION, AX5043_MODULATION_MSK, 1}, - {AX5043_REG_ENCODING, AX5043_ENCODING_NRZI_SCRAM, 1}, - {AX5043_REG_FRAMING, _VAL2FLD(AX5043_FRAMING_FRMMODE, AX5043_FRMMODE_HDLC) | - _VAL2FLD(AX5043_FRAMING_CRCMODE, AX5043_CRCMODE_CCITT), 1}, - - /* Pin Configuration */ - {AX5043_REG_PINFUNCSYSCLK, AX5043_PFSYSCLK_OUT_0, 1}, - - /* Synthesizer */ - {AX5043_REG_PLLCPI, 0x02, 1}, - {AX5043_REG_FREQA, 0x1B480001, 4}, - - /* PHY Layer Parameters */ - /* Receiver Parameters */ - {AX5043_REG_IFFREQ, 0x01D8, 2}, - {AX5043_REG_DECIMATION, 0x11, 1}, - {AX5043_REG_RXDATARATE, 0x003106, 3}, - {AX5043_REG_MAXDROFFSET, 0x000000, 3}, - {AX5043_REG_MAXRFOFFSET, 0x000EBF | AX5043_MAXRFOFFSET_FREQOFFSCORR, 3}, - - /* Receiver Parameter Set 0 */ - {AX5043_REG_AGCGAIN0, _VAL2FLD(AX5043_AGCGAIN_AGCDECAY, 0x07) | - _VAL2FLD(AX5043_AGCGAIN_AGCATTACK, 0x04), 1}, - {AX5043_REG_AGCTARGET0, 0x89, 1}, - {AX5043_REG_TIMEGAIN0, _VAL2FLD(AX5043_TIMEGAIN_E, 0x08) | - _VAL2FLD(AX5043_TIMEGAIN_M, 0x09), 1}, - {AX5043_REG_DRGAIN0, _VAL2FLD(AX5043_DRGAIN_E, 0x04) | - _VAL2FLD(AX5043_DRGAIN_M, 0x09), 1}, - {AX5043_REG_FREQDEV0, 0x0000, 2}, - - /* Receiver Parameter Set 1 */ - /* TODO */ - - /* Receiver Parameter Set 2 */ - /* TODO */ - - /* Receiver Parameter Set 3 */ - /* TODO */ - - /* Transmitter Parameters */ - {AX5043_REG_MODCFGF, AX5043_FREQSHAPE_GAUSS_BT_0_5, 1}, - {AX5043_REG_FSKDEV, 0x0009D5, 3}, - {AX5043_REG_MODCFGA, AX5043_MODCFGA_TXSE | _VAL2FLD(AX5043_MODCFGA_AMPLSHAPE, AX5043_AMPLSHAPE_RAISEDCOS), 1}, - {AX5043_REG_TXRATE, 0x002753, 3}, - {AX5043_REG_TXPWRCOEFFB, 0x0FFF, 2}, - - /* PLL Parameters */ - {AX5043_REG_PLLVCOI, _VAL2FLD(AX5043_PLLVCOI_VCOI, 0x16) | - AX5043_PLLVCOI_VCOIE, 1}, - - /* MAC Layer Parameters */ - /* Packet Format */ - {AX5043_REG_PKTADDRCFG, AX5043_PKTADDRCFG_FECSYNCDIS, 1}, - {AX5043_REG_PKTLENCFG, _VAL2FLD(AX5043_PKTLENCFG_LENBITS, 0xF), 1}, - {AX5043_REG_PKTMAXLEN, 0xFF, 1}, - /*{AX5043_REG_PKTADDR, _VAL2FLD(USLP_TFPH_ID_MCID, MCID) | USLP_TFPH_ID_SRC_DST, 4},*/ - /*{AX5043_REG_PKTADDRMASK, USLP_TFPH_ID_MCID | USLP_TFPH_ID_SRC_DST, 4},*/ - - /* Pattern Match */ - - /* Packet Controller */ - {AX5043_REG_PKTCHUNKSIZE, AX5043_PKTCHUNKSIZE_240, 1}, - {AX5043_REG_PKTMISCFLAGS, AX5043_PKTMISCFLAGS_BGNDRSSI, 1}, - {AX5043_REG_PKTSTOREFLAGS, AX5043_PKTSTOREFLAGS_RSSI | AX5043_PKTSTOREFLAGS_CRCB, 1}, - {AX5043_REG_PKTACCEPTFLAGS, AX5043_PKTACCEPTFLAGS_LRGP, 1}, - - /* Performance Tuning Registers */ - {AX5043_REG_0xF00, AX5043_0xF00_DEFVAL, 1}, - {AX5043_REG_0xF08, AX5043_0xF08_DEFVAL, 1}, - {AX5043_REG_0xF0D, AX5043_0xF0D_DEFVAL, 1}, - {AX5043_REG_0xF10, AX5043_0xF10_TCXO, 1}, - {AX5043_REG_0xF11, AX5043_0xF11_TCXO, 1}, - {AX5043_REG_0xF18, 0x06, 1}, - {AX5043_REG_0xF1C, AX5043_0xF1C_DEFVAL, 1}, - {AX5043_REG_0xF21, 0x68, 1}, - {AX5043_REG_0xF22, 0xFF, 1}, - {AX5043_REG_0xF23, 0x84, 1}, - {AX5043_REG_0xF26, 0x98, 1}, - {AX5043_REG_0xF35, AX5043_0xF35_XTALDIV1, 1}, - {AX5043_REG_0xF44, 0x25, 1}, - {AX5043_REG_0xF72, AX5043_0xF72_NORAWSOFTBITS, 1}, - {0, 0, 0} -}; - -static const uint8_t preamble[] = { - AX5043_CHUNKCMD_TXCTRL | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 1), - AX5043_CHUNK_TXCTRL_SETPA | AX5043_CHUNK_TXCTRL_PASTATE, - AX5043_CHUNKCMD_REPEATDATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 3), - AX5043_CHUNK_REPEATDATA_RAW | AX5043_CHUNK_REPEATDATA_NOCRC, - 50, - 0x7E -}; - -static const uint8_t postamble[] = { - AX5043_CHUNKCMD_REPEATDATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 3), - AX5043_CHUNK_REPEATDATA_RAW | AX5043_CHUNK_REPEATDATA_NOCRC, - 5, - 0x7E, - AX5043_CHUNKCMD_TXCTRL | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 1), - AX5043_CHUNK_TXCTRL_SETPA -}; - -static const SPIConfig lband_spicfg = { - false, - NULL, /* Operation complete callback */ - LINE_LBAND_CS, - // SPI_CR1 - SPI_CR1_SPE | /* SPI enable */ - SPI_CR1_MSTR | /* Master */ - SPI_CR1_BR_1 | /* f_pclk/8 (f_pclk = 84MHz, so 10.5MHz) */ - SPI_CR1_SSM, - 0, -}; - -static const SPIConfig uhf_spicfg = { - false, - NULL, /* Operation complete callback */ - LINE_UHF_CS, - // SPI_CR1 - SPI_CR1_SPE | /* SPI enable */ - SPI_CR1_MSTR | /* Master */ - SPI_CR1_BR_1 | /* f_pclk/8 (f_pclk = 84MHz, so 10.5MHz) */ - SPI_CR1_SSM, - 0, -}; - -static const AX5043Config lbandcfg = { - .spip = &SPID1, - .spicfg = &lband_spicfg, - .miso = LINE_SPI1_MISO, - .irq = LINE_LBAND_IRQ, - .xtal_freq = XTAL_CLK, - .fifo = &rx_fifo, - .phy_arg = &edl_lband_link, - .profile = lband_low, -}; - -static const AX5043Config uhfcfg = { - .spip = &SPID1, - .spicfg = &uhf_spicfg, - .miso = LINE_SPI1_MISO, - .irq = LINE_UHF_IRQ, - .xtal_freq = XTAL_CLK, - .fifo = &rx_fifo, - .phy_arg = &edl_uhf_link, - .profile = uhf_eng, - .preamble = preamble, - .preamble_len = sizeof(preamble), - .postamble = postamble, - .postamble_len = sizeof(postamble), -}; - -static SI41XXConfig synthcfg = { - .sen = LINE_LO_SEN, - .sclk = LINE_LO_SCLK, - .sdata = LINE_LO_SDATA, - .ref_freq = XTAL_CLK, - .if_div = SI41XX_IFDIV_DIV1, - .if_n = 1616, - .if_r = 32, -}; - -AX5043Driver lband; -AX5043Driver uhf; -SI41XXDriver synth; - -static const radio_cfg_t lband_high_cfg = { - .devp = &lband, - .profile = lband_high, - .name = "L-Band High Data Rate Engineering", -}; - -static const radio_cfg_t lband_low_cfg = { - .devp = &lband, - .profile = lband_low, - .name = "L-Band Low Data Rate Engineering", -}; - -static const radio_cfg_t uhf_eng_cfg = { - .devp = &uhf, - .profile = uhf_eng, - .name = "UHF Engineering", -}; - -static const radio_cfg_t uhf_ax25_cfg = { - .devp = &uhf, - .profile = uhf_ax25, - .name = "UHF AX.25", -}; - -synth_dev_t synth_devices[] = { - {&synth, &synthcfg, "LO"}, - {NULL, NULL, ""}, -}; - -radio_dev_t radio_devices[] = { - {&lband, &lbandcfg, "L-Band"}, - {&uhf, &uhfcfg, "UHF"}, - {NULL, NULL, ""}, -}; - -radio_cfg_t radio_cfgs[] = { - lband_high_cfg, - lband_low_cfg, - uhf_eng_cfg, - uhf_ax25_cfg, - {NULL, NULL, ""}, -}; - -const radio_cfg_t *tx_eng = &uhf_eng_cfg; -const radio_cfg_t *tx_ax25 = &uhf_ax25_cfg; - -static thread_t *edl_tp[EDL_WORKERS] = {NULL}; -static thread_t *tx_tp = NULL; -static thread_t *beacon_tp = NULL; - -THD_FUNCTION(edl_thd, arg) -{ - (void)arg; - fb_t *fb; - size_t len; - - while (!chThdShouldTerminateX()) { - if ((fb = pdu_recv(&rx_fifo)) == NULL) - continue; - if (uslp_recv(fb->phy_arg, fb)) { - edl_enable(true); - len = fb->len; - if (fb->phy_arg == &edl_lband_link) { - OD_PERSIST_STATE.x6004_persistentState.lbandRX_Bytes += len; - OD_PERSIST_STATE.x6004_persistentState.lbandRX_Packets += 1; - } else if (fb->phy_arg == &edl_uhf_link) { - OD_PERSIST_STATE.x6004_persistentState.UHF_RX_Bytes += len; - OD_PERSIST_STATE.x6004_persistentState.UHF_RX_Packets += 1; - } - } else { - OD_PERSIST_STATE.x6004_persistentState.EDL_RejectedCount += 1; - } - fb_free(fb, &rx_fifo); - } - - chThdExit(MSG_OK); -} - -THD_FUNCTION(tx_worker, arg) -{ - const radio_cfg_t *cfg = arg; - fb_t *fb; - - while (!chThdShouldTerminateX()) { - if ((fb = pdu_recv(&tx_fifo)) == NULL) - continue; - ax5043TX(cfg->devp, cfg->profile, fb->data, fb->len, fb->len, NULL, NULL, false); - fb_free(fb, &tx_fifo); - } - - /* Free remaining frame buffers */ - while ((fb = pdu_recv(&tx_fifo)) != NULL) { - fb_free(fb, &tx_fifo); - } - - chThdExit(MSG_OK); -} - -void comms_init(void) -{ - radio_init(); -} - -void comms_start(void) -{ - radio_start(); - for (int i = 0; i < EDL_WORKERS; i++) { - edl_tp[i] = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(0x1000), "EDL Worker", NORMALPRIO, edl_thd, NULL); - } - ax5043RX(&lband, false, false); - ax5043RX(&uhf, false, false); - tx_tp = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(0x400), "TX Worker", NORMALPRIO, tx_worker, (void*)tx_eng); -} - -void comms_stop(void) -{ - /* Stop transmissions */ - beacon_enable(false); - chThdTerminate(tx_tp); - chThdWait(tx_tp); - tx_tp = NULL; - - /* Stop receiving */ - radio_stop(); - - /* Terminate receive threads */ - for (int i = 0; i < EDL_WORKERS; i++) { - chThdTerminate(edl_tp[i]); - chThdWait(edl_tp[i]); - edl_tp[i] = NULL; - } -} - -void comms_cmd(fb_t *fb, void *arg) -{ - (void)arg; - osalDbgCheck(fb != NULL); - fb_t *resp_fb = fb_alloc(CMD_RESP_ALLOC, &tx_fifo); - fb_reserve(resp_fb, USLP_MAX_HEADER_LEN + 6); /* TODO: Replace 6 with some calculation of SDLS overhead */ - cmd_process((cmd_t*)fb->data, resp_fb); - uslp_map_send(fb->phy_arg, resp_fb, 0, 0, true); -} - -void comms_file(fb_t *fb, void *arg) -{ - (void)arg; - osalDbgCheck(fb != NULL); - fb_t *resp_fb = fb_alloc(CMD_RESP_ALLOC, &tx_fifo); - fb_reserve(resp_fb, USLP_MAX_HEADER_LEN + 6); /* TODO: Replace 6 with some calculation of SDLS overhead */ - int *ret = fb_put(resp_fb, sizeof(int)); - uint32_t *crc = fb_put(resp_fb, sizeof(uint32_t)); - *ret = file_recv((file_xfr_t*)fb->data, crc); - uslp_map_send(fb->phy_arg, resp_fb, 1, 0, true); -} - -void comms_beacon(fb_t *fb, void *arg) -{ - (void)fb; - (void)arg; - beacon_send(tx_ax25); -} - -void beacon_enable(bool enable) -{ - if (enable && beacon_tp == NULL) { - beacon_tp = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(0x800), "Beacon", NORMALPRIO, beacon, (void*)tx_ax25); - } else if (!enable && beacon_tp != NULL) { - chThdTerminate(beacon_tp); - chThdWait(beacon_tp); - beacon_tp = NULL; - } -} diff --git a/src/f4/app_control/source/comms.h b/src/f4/app_control/source/comms.h deleted file mode 100644 index 158423d8..00000000 --- a/src/f4/app_control/source/comms.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _COMMS_H_ -#define _COMMS_H_ - -#include "radio.h" - -#define XTAL_CLK 16000000U -#define EDL_WORKERS 1 - -#define SCID 0x4F53U -#define MCID ((USLP_TFVN << 16) | SCID) -/* 16-bit FECF provided by AX5043 driver */ -#define FECF_LEN 2 -#define USLP_MAX_LEN (FB_MAX_LEN + FECF_LEN) -#define CMD_RESP_LEN 64 -#define CMD_RESP_ALLOC (CMD_RESP_LEN + USLP_MAX_HEADER_LEN) -#define FILE_BUF_LEN 1024 - -#ifdef __cplusplus -extern "C" { -#endif - -extern AX5043Driver lband; -extern AX5043Driver uhf; - -void comms_init(void); -void comms_start(void); -void comms_stop(void); - -void comms_cmd(fb_t *fb, void *arg); -void comms_file(fb_t *fb, void *arg); -void comms_beacon(fb_t *fb, void *arg); -void beacon_enable(bool enable); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/deployer.c b/src/f4/app_control/source/deployer.c deleted file mode 100644 index ee7b0ce0..00000000 --- a/src/f4/app_control/source/deployer.c +++ /dev/null @@ -1,25 +0,0 @@ -#include "ch.h" -#include "hal.h" -#include "deployer.h" - -void deploy_heli(uint32_t duration) -{ - palSetLine(LINE_FIRE_HELI_1); - palSetLine(LINE_FIRE_HELI_2); - chThdSleepMilliseconds(duration); - palClearLine(LINE_FIRE_HELI_1); - palClearLine(LINE_FIRE_HELI_2); - - return; -} - -void deploy_turn(uint32_t duration) -{ - palSetLine(LINE_FIRE_TURN_1); - palSetLine(LINE_FIRE_TURN_2); - chThdSleepMilliseconds(duration); - palClearLine(LINE_FIRE_TURN_1); - palClearLine(LINE_FIRE_TURN_2); - - return; -} diff --git a/src/f4/app_control/source/deployer.h b/src/f4/app_control/source/deployer.h deleted file mode 100644 index 7625582d..00000000 --- a/src/f4/app_control/source/deployer.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _DEPLOYER_H_ -#define _DEPLOYER_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void deploy_heli(uint32_t duration); -void deploy_turn(uint32_t duration); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/file_xfr.c b/src/f4/app_control/source/file_xfr.c deleted file mode 100644 index 82d984ab..00000000 --- a/src/f4/app_control/source/file_xfr.c +++ /dev/null @@ -1,29 +0,0 @@ -#include "file_xfr.h" -#include "crc.h" - -int file_recv(file_xfr_t *xfr, uint32_t *crc) -{ - char filename[9] = {0}; - lfs_file_t *file; - int ret; - - memcpy(filename, xfr->filename, 8); - file = file_open(&FSD1, filename, LFS_O_WRONLY | LFS_O_CREAT); - if (file == NULL) { - return FSD1.err; - } - - ret = file_seek(&FSD1, file, xfr->off, LFS_SEEK_SET); - if (ret < 0) - goto file_recv_fail; - - ret = file_write(&FSD1, file, xfr->data, xfr->len); - if (ret < 0) - goto file_recv_fail; - - *crc = crc32(xfr->data, xfr->len, 0); - -file_recv_fail: - file_close(&FSD1, file); - return ret; -} diff --git a/src/f4/app_control/source/file_xfr.h b/src/f4/app_control/source/file_xfr.h deleted file mode 100644 index c1c90834..00000000 --- a/src/f4/app_control/source/file_xfr.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _FILE_XFR_H_ -#define _FILE_XFR_H_ - -#include "fs.h" - -typedef struct { - char filename[8]; - uint32_t off; - uint32_t len; - uint8_t data[]; -} file_xfr_t; - -#ifdef __cplusplus -extern "C" { -#endif - -int file_recv(file_xfr_t *xfr, uint32_t *crc); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/fw.c b/src/f4/app_control/source/fw.c deleted file mode 100644 index 61b902c7..00000000 --- a/src/f4/app_control/source/fw.c +++ /dev/null @@ -1,188 +0,0 @@ -#include -#include - -#include "fw.h" -#include "fs.h" -#include "crc.h" -#include "persist.h" -#include "fram.h" - -#define FLASH_OPTKEY1 0x08192A3BU -#define FLASH_OPTKEY2 0x4C5D6E7FU -#define FLASH_BANK_OFFSET 0x100000U -#define BUF_SIZE 256 - -uint8_t buf[BUF_SIZE]; - -int fw_read(EFlashDriver *eflp, char *filename, flash_offset_t offset, size_t len) -{ - lfs_file_t *file; - int ret; - - file = file_open(&FSD1, filename, LFS_O_WRONLY | LFS_O_CREAT | LFS_O_TRUNC); - if (file == NULL) { - return FSD1.err; - } - - eflStart(&EFLD1, NULL); - while (len) { - ssize_t n = (len > BUF_SIZE ? BUF_SIZE : len); - - ret = flashRead(eflp, offset, n, buf); - if (ret != FLASH_NO_ERROR) { - break; - } - n = file_write(&FSD1, file, buf, n); - if (n < 0) { - ret = n; - break; - } - offset += n; - len -= n; - }; - eflStop(&EFLD1); - - file_close(&FSD1, file); - return ret; -} - -int fw_write(EFlashDriver *eflp, char *filename, flash_offset_t offset) -{ - lfs_file_t *file; - ssize_t n; - int ret; - - file = file_open(&FSD1, filename, LFS_O_RDONLY); - if (file == NULL) { - return FSD1.err; - } - - eflStart(&EFLD1, NULL); - while ((n = file_read(&FSD1, file, buf, BUF_SIZE)) > 0) { - ret = flashProgram(eflp, offset, n, buf); - if (ret != FLASH_NO_ERROR) { - break; - } - offset += n; - } - eflStop(&EFLD1); - if (n != 0) { - ret = n; - } - - file_close(&FSD1, file); - return ret; -} - -uint32_t fw_crc(EFlashDriver *eflp, fw_bank_t bank, size_t len) -{ - uint32_t crc = 0; - flash_offset_t offset; - offset = (((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) >> SYSCFG_MEMRMP_UFB_MODE_Pos) ^ bank ? FLASH_BANK_OFFSET : 0); - eflStart(eflp, NULL); - while (len) { - ssize_t n = len; - if (n > BUF_SIZE) { - n = BUF_SIZE; - } - - if (flashRead(eflp, offset, n, buf) != FLASH_NO_ERROR) { - break; - } - crc = crc32(buf, n, crc); - offset += n; - len -= n; - }; - eflStop(eflp); - return crc; -} - -uint32_t fw_verify(EFlashDriver *eflp, fw_bank_t bank) -{ - fw_info_t fw_info[2] = {0}; - uint32_t crc = 0; - size_t len; - - framRead(&FRAMD1, FRAM_FWINFO_ADDR, &fw_info, sizeof(fw_info)); - len = fw_info[bank].len; - if (len == 0) - return 0; - - crc = fw_crc(eflp, bank, len); - - return (crc == fw_info[bank].crc ? crc : 0); -} - -void fw_set_info(fw_info_t fw_info, fw_bank_t bank) -{ - uint16_t addr = (bank ? FRAM_FWINFO_ADDR + sizeof(fw_info_t) : FRAM_FWINFO_ADDR); - framWrite(&FRAMD1, addr, &fw_info, sizeof(fw_info_t)); -} - -int fw_flash(EFlashDriver *eflp, char *filename, uint32_t expected_crc) -{ - lfs_file_t *file; - fw_info_t fw_info = {0}; - int ret; - - /* Verify the file matches the expected CRC */ - file = file_open(&FSD1, filename, LFS_O_RDONLY); - if (file == NULL) { - return FSD1.err; - } - fw_info.crc = file_crc(&FSD1, file); - fw_info.len = file_size(&FSD1, file); - file_close(&FSD1, file); - if (FSD1.err != LFS_ERR_OK) { - return FSD1.err; - } - if (fw_info.crc != expected_crc) { - return FLASH_ERROR_VERIFY; - } - - /* Erase the offline flash bank */ - eflStart(&EFLD1, NULL); - ret = flashStartEraseAll(eflp); - if (ret != FLASH_NO_ERROR) - return ret; - /* Wait for erase operation to complete */ - ret = flashWaitErase((BaseFlash*)eflp); - if (ret != FLASH_NO_ERROR) - return ret; - eflStop(&EFLD1); - - /* Write new firmware image to offline bank */ - ret = fw_write(eflp, filename, FLASH_BANK_OFFSET); - if (ret != FLASH_NO_ERROR) - return ret; - - /* Commit new FW info to FRAM */ - fw_set_info(fw_info, !(SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE)); - - return !fw_verify(eflp, !(SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE)); -} - -int fw_set_bank(EFlashDriver *eflp, fw_bank_t bank) -{ - int ret; - - ret = flashQueryErase(eflp, NULL); - if (ret != FLASH_NO_ERROR) - return ret; - /* Unlock option byte control register */ - eflp->flash->OPTKEYR |= FLASH_OPTKEY1; - eflp->flash->OPTKEYR |= FLASH_OPTKEY2; - - /* Set bank bit appropriately */ - eflp->flash->OPTCR &= ~FLASH_OPTCR_BFB2; - eflp->flash->OPTCR |= (bank << FLASH_OPTCR_BFB2_Pos); - eflp->flash->OPTCR |= FLASH_OPTCR_OPTSTRT; - - /* Wait for operation to finish */ - while ((eflp->flash->SR & FLASH_SR_BSY) != 0); - - /* Lock option byte control register */ - eflp->flash->OPTCR |= FLASH_OPTCR_OPTLOCK; - - return ret; -} diff --git a/src/f4/app_control/source/fw.h b/src/f4/app_control/source/fw.h deleted file mode 100644 index 847d79ff..00000000 --- a/src/f4/app_control/source/fw.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef _FW_H_ -#define _FW_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - BANK_0 = 0, - BANK_1 = 1 -} fw_bank_t; - -typedef struct { - uint32_t crc; - size_t len; -} fw_info_t; - -int fw_read(EFlashDriver *eflp, char *filename, flash_offset_t offset, size_t len); -int fw_write(EFlashDriver *eflp, char *filename, flash_offset_t offset); -uint32_t fw_crc(EFlashDriver *eflp, fw_bank_t bank, size_t len); -uint32_t fw_verify(EFlashDriver *eflp, fw_bank_t bank); -void fw_set_info(fw_info_t fw_info, fw_bank_t bank); -int fw_flash(EFlashDriver *eflp, char *filename, uint32_t expected_crc); -int fw_set_bank(EFlashDriver *eflp, fw_bank_t bank); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/hmac.c b/src/f4/app_control/source/hmac.c deleted file mode 100644 index b98f0438..00000000 --- a/src/f4/app_control/source/hmac.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include "hmac.h" -#include "CANopen.h" -#include "OD.h" - -int hmac_send(void *data, size_t len, void *iv, void *seq_num, void *mac, void *arg) -{ - (void)iv; - cryerror_t err; - HMACSHA256Context ctx = {0}; - - *((uint32_t*)seq_num) = __builtin_bswap32(OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount); - - err = cryLoadHMACTransientKey(&CRYD1, 32, arg); - if (err != CRY_NOERROR) { - return err; - } - - err = cryHMACSHA256Init(&CRYD1, &ctx); - if (err != CRY_NOERROR) { - return err; - } - - err = cryHMACSHA256Update(&CRYD1, &ctx, len, data); - if (err != CRY_NOERROR) { - return err; - } - - err = cryHMACSHA256Final(&CRYD1, &ctx, mac); - if (err != CRY_NOERROR) { - return err; - } - - return 0; -} -int hmac_recv(void *data, size_t len, void *iv, void *seq_num, void *mac, void *arg) -{ - (void)iv; - cryerror_t err; - HMACSHA256Context ctx = {0}; - uint8_t hmac[32] = {0}; - uint32_t recv_seq = __builtin_bswap32(*((uint32_t*)seq_num)); - - /* Check sequence number first */ - if (recv_seq < OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount) { - return -1; - } - - /* Calculate HMAC */ - err = cryLoadHMACTransientKey(&CRYD1, 32, arg); - if (err != CRY_NOERROR) { - return err; - } - err = cryHMACSHA256Init(&CRYD1, &ctx); - if (err != CRY_NOERROR) { - return err; - } - err = cryHMACSHA256Update(&CRYD1, &ctx, len, data); - if (err != CRY_NOERROR) { - return err; - } - err = cryHMACSHA256Final(&CRYD1, &ctx, hmac); - if (err != CRY_NOERROR) { - return err; - } - - /* Compare HMAC */ - if (memcmp(hmac, mac, 32) != 0) { - return -1; - } - - /* Set new sequence number */ - OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount = recv_seq + 1; - - return 0; -} diff --git a/src/f4/app_control/source/hmac.h b/src/f4/app_control/source/hmac.h deleted file mode 100644 index 1cc9ef61..00000000 --- a/src/f4/app_control/source/hmac.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _HMAC_H_ -#define _HMAC_H_ - -#include "ch.h" -#include "hal.h" - -int hmac_send(void *data, size_t len, void *iv, void *seq_num, void *mac, void *arg); -int hmac_recv(void *data, size_t len, void *iv, void *seq_num, void *mac, void *arg); - -#endif diff --git a/src/f4/app_control/source/persist.c b/src/f4/app_control/source/persist.c deleted file mode 100644 index 0a278f6d..00000000 --- a/src/f4/app_control/source/persist.c +++ /dev/null @@ -1,94 +0,0 @@ -#include -#include "persist.h" -#include "fram.h" -#include "crc.h" -#include "CANopen.h" -#include "OD.h" - -typedef struct { - uint32_t crc; - uint8_t data[]; -} buf_t; - -typedef struct { - void *data; - size_t len; - uint16_t fram_addr; -} persist_group_t; - -persist_group_t storage[] = { - {&OD_PERSIST_KEYS, sizeof(OD_PERSIST_KEYS), FRAM_KEYS_ADDR}, - {&OD_PERSIST_STATE, sizeof(OD_PERSIST_STATE), FRAM_STATE_ADDR}, - {&OD_PERSIST_COMM, sizeof(OD_PERSIST_COMM), FRAM_COMM_ADDR}, - {&OD_PERSIST_MFR, sizeof(OD_PERSIST_MFR), FRAM_MFR_ADDR}, - {&OD_PERSIST_APP, sizeof(OD_PERSIST_APP), FRAM_APP_ADDR}, - {NULL, 0, 0} -}; - -void persistStoreGroup(void *group) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL && ptr->data != group) - ptr++; - osalDbgCheck(ptr != NULL); - - /* Checksum data and store */ - buf_t *buf = malloc(sizeof(buf_t) + ptr->len); - memcpy(buf->data, ptr->data, ptr->len); - buf->crc = crc32(buf->data, ptr->len, 0); - framWrite(&FRAMD1, ptr->fram_addr, buf, sizeof(buf) + ptr->len); - free(buf); -} - -void persistRestoreGroup(void *group) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL && ptr->data != group) - ptr++; - osalDbgCheck(ptr != NULL); - - /* Check that data is valid and restore */ - buf_t *buf = malloc(sizeof(buf_t) + ptr->len); - framRead(&FRAMD1, ptr->fram_addr, buf, sizeof(buf) + ptr->len); - if (buf->crc == crc32(buf->data, ptr->len, 0)) { - memcpy(ptr->data, buf->data, ptr->len); - } - free(buf); -} - -void persistResetGroup(void *group) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL && ptr->data != group) - ptr++; - osalDbgCheck(ptr != NULL); - - framErase(&FRAMD1, ptr->fram_addr, sizeof(buf_t) + ptr->len); -} - -void persistStoreAll(void) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL) { - persistStoreGroup(ptr->data); - ptr++; - } -} - -void persistRestoreAll(void) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL) { - persistRestoreGroup(ptr->data); - ptr++; - } -} - -void persistResetAll(void) -{ - persist_group_t *ptr = storage; - while (ptr->data != NULL) { - persistRestoreGroup(ptr->data); - ptr++; - } -} diff --git a/src/f4/app_control/source/persist.h b/src/f4/app_control/source/persist.h deleted file mode 100644 index 3b219b21..00000000 --- a/src/f4/app_control/source/persist.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef _PERSIST_H_ -#define _PERSIST_H_ - -#include "ch.h" -#include "hal.h" - -#define FRAM_FWINFO_ADDR 0x0000U -#define FRAM_KEYS_ADDR 0x0010U -#define FRAM_STATE_ADDR 0x0100U -#define FRAM_COMM_ADDR 0x0200U -#define FRAM_MFR_ADDR 0x0300U -#define FRAM_APP_ADDR 0x0400U - -void persistStoreGroup(void *group); -void persistRestoreGroup(void *group); -void persistResetGroup(void *group); -void persistStoreAll(void); -void persistRestoreAll(void); -void persistResetAll(void); - -#endif diff --git a/src/f4/app_control/source/test/cli.c b/src/f4/app_control/source/test/cli.c deleted file mode 100644 index 8ed119d8..00000000 --- a/src/f4/app_control/source/test/cli.c +++ /dev/null @@ -1,174 +0,0 @@ -#include -#include -#include -#include - -#include "cli.h" -#include "c3.h" -#include "CANopen.h" -#include "OD.h" -#include "test_fw.h" -#include "test_canopen.h" -#include "test_opd.h" -#include "test_time.h" -#include "test_fram.h" -#include "test_persist.h" -#include "test_lfs.h" -#include "test_mmc.h" -#include "test_radio.h" -#include "test_comms.h" -#include "test_deploy.h" -#include "test_crc.h" -#include "test_hmac.h" -#include "chprintf.h" -#include "shell.h" - -static thread_t *shell_tp; -extern thread_t *c3_tp; - -/*===========================================================================*/ -/* OreSat C3 State Control */ -/*===========================================================================*/ -void cmd_state(BaseSequentialStream *chp, int argc, char *argv[]) -{ - if (argc < 1) { - goto state_usage; - } - if (!strcmp(argv[0], "status")) { - chprintf(chp, "C3 State: %c\r\n", OD_RAM.x6000_C3_State[0]); - chprintf(chp, "TX Enable: %s\r\n", (tx_enabled() ? "TRUE" : "FALSE")); - chprintf(chp, "Bat Good: %s\r\n", (bat_good() ? "TRUE" : "FALSE")); - chprintf(chp, "EDL Mode: %s\r\n", (edl_enabled() ? "TRUE" : "FALSE")); - chprintf(chp, "Auth Sequence Number: %d\r\n", OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount); - chprintf(chp, "Current Bank: %d\r\n" - "Next Boot Bank: %d\r\n\r\n", - (SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE ? 1 : 0), - (FLASH->OPTCR & FLASH_OPTCR_BFB2 ? 1 : 0)); - chprintf(chp, "===RTC===\r\n" - "Date: %08X\r\n" - "Time: %08X\r\n" - "Wakeup: %08X (%s)\r\n" - "Alarm A: %08X (%s)\r\n" - "Alarm B: %08X (%s)\r\n", - RTCD1.rtc->DR, RTCD1.rtc->TR, - RTCD1.rtc->WUTR, (RTCD1.rtc->CR & RTC_CR_WUTE ? "ENABLED" : "DISABLED"), - RTCD1.rtc->ALRMAR, (RTCD1.rtc->CR & RTC_CR_ALRAE ? "ENABLED" : "DISABLED"), - RTCD1.rtc->ALRMBR, (RTCD1.rtc->CR & RTC_CR_ALRBE ? "ENABLED" : "DISABLED")); - } else if (!strcmp(argv[0], "tx") && argc > 1) { - tx_enable(argv[1][0] == 't'); - } else if (!strcmp(argv[0], "edl") && argc > 1) { - edl_enable(argv[1][0] == 't'); - } else if (!strcmp(argv[0], "keyload") && argc > 1) { - uint8_t index = strtoul(argv[1], NULL, 0); - char line[32 * 2] = {0}; - char c, *p = line; - - while (streamRead(chp, (uint8_t*)&c, 1) != 0 && c != 4) { - c = toupper(c); - - if (isdigit(c) || (c >= 'A' && c <= 'F')) { - streamPut(chp, c); - *(p++) = c; - if (p == &line[32 * 2]) { - for (size_t off = 0; off < 32; off++) { - sscanf(&line[off*2], "%2hhx", &OD_PERSIST_KEYS.x6005_cryptoKeys[index][off]); - } - break; - } - } else if ((c == 8) || (c == 127)) { - if (p != line) { - streamPut(chp, 0x08); - streamPut(chp, 0x20); - streamPut(chp, 0x08); - p--; - } - } - } - - chprintf(chp, "\r\nKEY[%u]:", index); - for (int i = 0; i < 32; i++) { - chprintf(chp, " %02X", OD_PERSIST_KEYS.x6005_cryptoKeys[index][i]); - } - chprintf(chp, "\r\n"); - } else if (!strcmp(argv[0], "i2c_cycle")) { - palSetLine(LINE_I2C_PWROFF); - chThdSleepMilliseconds(10); - palClearLine(LINE_I2C_PWROFF); - } else if (!strcmp(argv[0], "softreset")) { - soft_reset(); - } else if (!strcmp(argv[0], "hardreset")) { - hard_reset(); - } else if (!strcmp(argv[0], "factoryreset")) { - chprintf(chp, "Initiating factory reset..."); - factory_reset(); - } else { - goto state_usage; - } - - return; - -state_usage: - chprintf(chp, "Usage: state \r\n" - " status: Get current system state\r\n" - " tx : Override TX enable state\r\n" - " edl : Override EDL state\r\n" - " keyload : Load key into \r\n" - " i2c_cycle: Power cycle I2C peripheral bus\r\n" - " softreset: Soft reset C3\r\n" - " hardreset: Hard reset C3\r\n" - " factoryreset: Reset C3 to factory defaults\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* Shell */ -/*===========================================================================*/ -static const ShellCommand commands[] = { - {"fw", cmd_fw}, - {"nmt", cmd_nmt}, - {"sdo", cmd_sdo}, - {"opd", cmd_opd}, - {"node", cmd_node}, - {"mmc", cmd_mmc}, - {"time", cmd_time}, - {"lfs", cmd_lfs}, - {"radio", cmd_radio}, - {"synth", cmd_synth}, - {"rf", cmd_rf}, - {"rftest", cmd_rftest}, - {"beacon", cmd_beacon}, - {"state", cmd_state}, - {"fram", cmd_fram}, - {"persist", cmd_persist}, - {"crc", cmd_crc}, - {"hmac", cmd_hmac}, - {"deploy", cmd_deploy}, - {"edl", cmd_edl}, - {NULL, NULL} -}; - -static char histbuf[SHELL_MAX_HIST_BUFF]; - -static const ShellConfig shell_cfg = { - (BaseSequentialStream *)&SD3, - commands, - histbuf, - sizeof(histbuf), -}; - -THD_WORKING_AREA(shell_wa, 0x1000); -THD_WORKING_AREA(cli_wa, 0x100); -THD_FUNCTION(cli, arg) -{ - (void)arg; - - /* Start a shell */ - while (!chThdShouldTerminateX()) { - shell_tp = chThdCreateStatic(shell_wa, sizeof(shell_wa), NORMALPRIO, shellThread, (void *)&shell_cfg); - chThdWait(shell_tp); - chThdSleepMilliseconds(500); - } - - chThdExit(MSG_OK); -} diff --git a/src/f4/app_control/source/test/cli.h b/src/f4/app_control/source/test/cli.h deleted file mode 100644 index ffedc25b..00000000 --- a/src/f4/app_control/source/test/cli.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _CLI_H_ -#define _CLI_H_ - -#include "ch.h" -#include "hal.h" - -extern THD_WORKING_AREA(cli_wa, 0x100); -extern THD_FUNCTION(cli, arg); - -#endif diff --git a/src/f4/app_control/source/test/test_canopen.c b/src/f4/app_control/source/test/test_canopen.c deleted file mode 100644 index 1e3bea22..00000000 --- a/src/f4/app_control/source/test/test_canopen.c +++ /dev/null @@ -1,128 +0,0 @@ -#include -#include "test_canopen.h" -#include "CO_master.h" -#include "chprintf.h" - -extern CO_t *CO; - -/*===========================================================================*/ -/* Support functions */ -/*===========================================================================*/ -/* -bool sdo_file_cb(sdocli_t *sdocli, CO_SDO_return_t ret, CO_SDO_abortCode_t *abort_code, void *arg) -{ - struct cb_arg *data = arg; - ssize_t size, space; - - if (ret < 0) { - chprintf((BaseSequentialStream*)&SD3, "Error in SDO transfer. Ret: %d Abort: %X", ret, *abort_code); - return true; - } - - if (sdocli->state == SDOCLI_ST_DOWNLOAD) { - space = CO_fifo_getSpace(&sdocli->sdo_c->bufFifo); - do { - size = file_read(&FSD1, data->file, data->buf, lfs_min(space, BUF_SIZE)); - if (size < 0) { - *abort_code = CO_SDO_AB_NO_DATA; - return true; - } - CO_SDOclientDownloadBufWrite(sdocli->sdo_c, data->buf, size); - } while (size && (space -= size)); - } else if (sdocli->state == SDOCLI_ST_UPLOAD) { - if (ret == CO_SDO_RT_uploadDataBufferFull || ret == CO_SDO_RT_ok_communicationEnd) { - do { - size = CO_SDOclientUploadBufRead(sdocli->sdo_c, data->buf, BUF_SIZE); - file_write(&FSD1, data->file, data->buf, size); - } while (size); - } - } - - return false; -} -*/ - -/*===========================================================================*/ -/* OreSat CAN Bus NMT */ -/*===========================================================================*/ -void cmd_nmt(BaseSequentialStream *chp, int argc, char *argv[]) -{ - CO_ReturnError_t err; - uint8_t node_id = 0; - - if (argc < 1) { - goto nmt_usage; - } - - if (argc > 1) { - node_id = strtoul(argv[1], NULL, 0); - } - - if (!strcmp(argv[0], "op")) { - err = CO_NMT_sendCommand(CO->NMT, CO_NMT_ENTER_OPERATIONAL, node_id); - } else if (!strcmp(argv[0], "preop")) { - err = CO_NMT_sendCommand(CO->NMT, CO_NMT_ENTER_PRE_OPERATIONAL, node_id); - } else if (!strcmp(argv[0], "stop")) { - err = CO_NMT_sendCommand(CO->NMT, CO_NMT_ENTER_STOPPED, node_id); - } else if (!strcmp(argv[0], "resetcomms")) { - err = CO_NMT_sendCommand(CO->NMT, CO_NMT_RESET_COMMUNICATION, node_id); - } else if (!strcmp(argv[0], "resetnode")) { - err = CO_NMT_sendCommand(CO->NMT, CO_NMT_RESET_NODE, node_id); - } else { - goto nmt_usage; - } - if (err != CO_ERROR_NO) { - chprintf(chp, "Error executing NMT command: %d\r\n", err); - } - return; - -nmt_usage: - chprintf(chp, "Usage: nmt \r\n" - " op: Set device operational\r\n" - " preop: Set device pre-operational\r\n" - " stop: Stop device\r\n" - " resetcomms: Reset CAN communications on device\r\n" - " resetnode: Reset device\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* OreSat CAN Bus SDO Client */ -/*===========================================================================*/ -void cmd_sdo(BaseSequentialStream *chp, int argc, char *argv[]) -{ - sdocli_op_t op; - uint16_t index = 0; - uint8_t node_id = 0, subindex = 0; - size_t size = 0; - uint32_t value = 0; - - if (argc < 5) { - goto sdo_usage; - } - - if (argv[0][0] == 'w') { - op = SDO_CLI_WRITE; - } else if (argv[0][0] == 'r') { - op = SDO_CLI_READ; - } else { - goto sdo_usage; - } - node_id = strtoul(argv[1], NULL, 0); - index = strtoul(argv[2], NULL, 0); - subindex = strtoul(argv[3], NULL, 0); - size = strtoul(argv[4], NULL, 0); - if (op == SDO_CLI_WRITE) { - value = strtoul(argv[5], NULL, 0); - } - - chprintf(chp, "Initiating transfer... "); - sdo_transfer(op, node_id, index, subindex, size, size, &value); - chprintf(chp, "Started!\r\n"); - return; - -sdo_usage: - chprintf(chp, "Usage: sdo (r)ead|(w)rite [value]\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_canopen.h b/src/f4/app_control/source/test/test_canopen.h deleted file mode 100644 index 23abae9a..00000000 --- a/src/f4/app_control/source/test/test_canopen.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TEST_CANOPEN_H_ -#define _TEST_CANOPEN_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_nmt(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_sdo(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_comms.c b/src/f4/app_control/source/test/test_comms.c deleted file mode 100644 index d2147606..00000000 --- a/src/f4/app_control/source/test/test_comms.c +++ /dev/null @@ -1,398 +0,0 @@ -#include -#include -#include "test_comms.h" -#include "c3.h" -#include "cmd.h" -#include "file_xfr.h" -#include "comms.h" -#include "uslp.h" -#include "hmac.h" -#include "CANopen.h" -#include "OD.h" -#include "chprintf.h" - -#define COMMS_EVENT_LOOPBACK_RX EVENT_MASK(0) - -extern const uslp_mc_t mc; - -static fb_t *tx_fb; - -static thread_t *cli_tp; - -static uint8_t resp_buf[CMD_RESP_LEN]; -static size_t buf_len; - -static void pdu_loopback(fb_t *fb, void *arg); -static void resp_recv(fb_t *fb, void *arg); - -#if (USLP_USE_SDLS == TRUE) -static const sdls_cfg_t sdls_cfg = { - .spi = 1, - .iv_len = 0, - .seq_num_len = sizeof(OD_PERSIST_STATE.x6004_persistentState.EDL_SequenceCount), - .pad_len = 0, - .mac_len = 32, - .send_func = hmac_send, - .send_arg = OD_PERSIST_KEYS.x6005_cryptoKeys[0], - .recv_func = NULL, - .recv_arg = NULL, -}; -#endif - -static const uslp_map_t map_cmd = { - .sdu = SDU_MAP_ACCESS, - .upid = UPID_MAPA_SDU, - .max_pkt_len = CMD_RESP_LEN, - .incomplete = false, - .map_recv = resp_recv, -}; - -static const uslp_map_t map_file = { - .sdu = SDU_MAP_ACCESS, - .upid = UPID_MAPA_SDU, - .max_pkt_len = FILE_BUF_LEN + sizeof(file_xfr_t), - .incomplete = false, - .map_recv = resp_recv, -}; - -static const uslp_vc_t vc0 = { - .seq_ctrl_len = 0, - .expedited_len = 0, - .seq_ctrl_cnt = NULL, - .expedited_cnt = NULL, - .cop = COP_NONE, - .mapid[0] = &map_cmd, - .trunc_tf_len = USLP_MAX_LEN, - .ocf = false, -#if (USLP_USE_SDLS == TRUE) - .sdls_cfg = &sdls_cfg, -#endif -}; - -static const uslp_vc_t vc1 = { - .seq_ctrl_len = 0, - .expedited_len = 0, - .seq_ctrl_cnt = NULL, - .expedited_cnt = NULL, - .cop = COP_NONE, - .mapid[0] = &map_file, - .trunc_tf_len = USLP_MAX_LEN, - .ocf = false, -#if (USLP_USE_SDLS == TRUE) - .sdls_cfg = NULL, -#endif -}; - -static const uslp_mc_t loopback_mc = { - .scid = &OD_PERSIST_APP.x6006_CCSDS.spacecraftID, - .owner = false, - .vcid[0] = &vc0, - .vcid[1] = &vc1, -}; - -static const uslp_pc_t loopback_pc = { - .name = "Loopback", - .tf_len = USLP_MAX_LEN, - .fecf = FECF_SW, - .fecf_len = FECF_LEN, - .phy_send = pdu_loopback, - .phy_send_ahead = pdu_loopback, -}; - -static const uslp_link_t edl_loopback_rx_link = { - .mc = &mc, - .pc_rx = &loopback_pc, - .pc_tx = &loopback_pc, -}; - -static const uslp_link_t edl_loopback_tx_link = { - .mc = &loopback_mc, - .pc_rx = &loopback_pc, - .pc_tx = &loopback_pc, -}; - -static void pdu_loopback(fb_t *fb, void *arg) -{ - (void)arg; - if (fb == tx_fb) { - fb->phy_arg = (void*)&edl_loopback_rx_link; - pdu_send(fb, &rx_fifo); - } else { - uslp_recv(&edl_loopback_tx_link, fb); - fb_free(fb, &tx_fifo); - } -} - -static void resp_recv(fb_t *fb, void *arg) -{ - (void)arg; - osalDbgCheck(fb != NULL); - memcpy(resp_buf, fb->data, fb->len); - buf_len = fb->len; - chEvtSignal(cli_tp, COMMS_EVENT_LOOPBACK_RX); -} - -static void print_response(BaseSequentialStream *chp) -{ - if (chEvtWaitAnyTimeout(COMMS_EVENT_LOOPBACK_RX, TIME_S2I(30)) != 0) { - chprintf(chp, "Response buffer:"); - for (size_t i = 0; i < buf_len; i++) { - if (i % 0x10 == 0) chprintf(chp, "\r\n%04X:", i); - chprintf(chp, " %02X", resp_buf[i]); - } - chprintf(chp, "\r\n"); - } else { - chprintf(chp, "No response!\r\n"); - } -} - -static void send_cmd(cmd_code_t cmd_code, void *arg, size_t arg_len) -{ - cmd_t *cmd; - tx_fb = fb_alloc(CMD_RESP_ALLOC, &rx_fifo); - /* TODO: What's the 2 for? */ - fb_reserve(tx_fb, USLP_MAX_HEADER_LEN + 2 + 6); /* TODO: Replace 6 with some calculation of SDLS overhead */ - cmd = fb_put(tx_fb, sizeof(cmd_t) + arg_len); - cmd->cmd = cmd_code; - if (arg != NULL) - memcpy(cmd->arg, arg, arg_len); - uslp_map_send(&edl_loopback_tx_link, tx_fb, 0, 0, true); -} - -static int send_file_seg(BaseSequentialStream *chp, char *src, char *dest, lfs_soff_t off, lfs_size_t len) -{ - file_xfr_t *xfr; - lfs_file_t *file; - uint8_t *data; - int ret; - - file = file_open(&FSD1, src, LFS_O_RDONLY); - if (file == NULL) { - return FSD1.err; - } - ret = file_seek(&FSD1, file, off, LFS_SEEK_SET); - if (ret < 0) { - file_close(&FSD1, file); - return ret; - } - - tx_fb = fb_alloc(FB_MAX_LEN, &rx_fifo); - /* TODO: What's the 2 for? */ - fb_reserve(tx_fb, USLP_MAX_HEADER_LEN + sizeof(file_xfr_t) + 2 + 6); /* TODO: Replace 6 with some calculation of SDLS overhead */ - data = fb_put(tx_fb, len); - ret = file_read(&FSD1, file, data, len); - file_close(&FSD1, file); - if (ret < 0) { - fb_free(tx_fb, &rx_fifo); - return ret; - } - xfr = fb_push(tx_fb, sizeof(file_xfr_t)); - memcpy(xfr->filename, dest, strlen(dest) + 1); - xfr->off = off; - xfr->len = len; - chprintf(chp, "Sending %d byte block to offset %d...\r\n", len, off); - uslp_map_send(&edl_loopback_tx_link, tx_fb, 0, 1, true); - print_response(chp); - - return ret; -} - -static int send_file(BaseSequentialStream *chp, char *src, char *dest) -{ - lfs_ssize_t len; - lfs_soff_t off = 0; - lfs_file_t *file; - - if (!strcmp(src, dest)) { - return LFS_ERR_INVAL; - } - - file = file_open(&FSD1, src, LFS_O_RDONLY); - if (file == NULL) { - return FSD1.err; - } - len = file_size(&FSD1, file); - file_close(&FSD1, file); - if (len < 0) { - return FSD1.err; - } - - while (len) { - lfs_ssize_t n = (len > FILE_BUF_LEN ? FILE_BUF_LEN : len); - n = send_file_seg(chp, src, dest, off, n); - if (n < 0) { - return n; - } - off += n; - len -= n; - } - return off; -} - -/*===========================================================================*/ -/* OreSat C3 EDL */ -/*===========================================================================*/ -void cmd_edl(BaseSequentialStream *chp, int argc, char *argv[]) -{ - cli_tp = chThdGetSelfX(); - - if (argc < 1) { - goto edl_usage; - } - if (!strcmp(argv[0], "tx_enable") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_TX_CTRL, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "fw_flash") && argc > 2) { - struct { - uint32_t crc; - char filename[strlen(argv[1]) + 1]; - } arg; - arg.crc = strtoul(argv[2], NULL, 0); - memcpy(arg.filename, argv[1], strlen(argv[1]) + 1); - send_cmd(CMD_FW_FLASH, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "fw_bank") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_FW_BANK, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "fw_verify") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_FW_VERIFY, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "c3_softreset")) { - uint32_t arg[] = {0x01234567U, 0x89ABCDEFU}; - send_cmd(CMD_C3_SOFTRESET, arg, sizeof(arg)); - } else if (!strcmp(argv[0], "c3_hardreset")) { - uint32_t arg[] = {0x01234567U, 0x89ABCDEFU}; - send_cmd(CMD_C3_HARDRESET, arg, sizeof(arg)); - } else if (!strcmp(argv[0], "c3_factoryreset")) { - uint32_t arg[] = {0x01234567U, 0x89ABCDEFU}; - send_cmd(CMD_C3_FACTORYRESET, arg, sizeof(arg)); - } else if (!strcmp(argv[0], "fs_upload") && argc > 2) { - chprintf(chp, "File send result: %d\r\n", send_file(chp, argv[1], argv[2])); - } else if (!strcmp(argv[0], "fs_upload_seg") && argc > 4) { - lfs_soff_t off = strtoul(argv[3], NULL, 0); - lfs_ssize_t len = strtoul(argv[4], NULL, 0); - chprintf(chp, "File send result: %d\r\n", send_file_seg(chp, argv[1], argv[2], off, len)); - } else if (!strcmp(argv[0], "fs_format")) { - send_cmd(CMD_FS_FORMAT, NULL, 0); - print_response(chp); - } else if (!strcmp(argv[0], "fs_unmount")) { - send_cmd(CMD_FS_UNMOUNT, NULL, 0); - print_response(chp); - } else if (!strcmp(argv[0], "fs_remove") && argc > 1) { - send_cmd(CMD_FS_REMOVE, argv[1], strlen(argv[1]) + 1); - print_response(chp); - } else if (!strcmp(argv[0], "fs_crc") && argc > 1) { - send_cmd(CMD_FS_CRC, argv[1], strlen(argv[1]) + 1); - print_response(chp); - } else if (!strcmp(argv[0], "node_enable") && argc > 2) { - uint8_t arg[2]; - arg[0] = strtoul(argv[1], NULL, 0); - arg[1] = strtoul(argv[2], NULL, 0); - send_cmd(CMD_NODE_ENABLE, arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "node_status") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_NODE_STATUS, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "opd_sysenable")) { - send_cmd(CMD_OPD_SYSENABLE, NULL, 0); - print_response(chp); - } else if (!strcmp(argv[0], "opd_sysdisable")) { - send_cmd(CMD_OPD_SYSDISABLE, NULL, 0); - print_response(chp); - } else if (!strcmp(argv[0], "opd_scan") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_OPD_SCAN, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "opd_enable") && argc > 2) { - uint8_t arg[2]; - arg[0] = strtoul(argv[1], NULL, 0); - arg[1] = strtoul(argv[2], NULL, 0); - send_cmd(CMD_OPD_ENABLE, arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "opd_reset") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_OPD_RESET, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "opd_status") && argc > 1) { - uint8_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_OPD_STATUS, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "rtc_settime") && argc > 1) { - uint32_t arg = strtoul(argv[1], NULL, 0); - send_cmd(CMD_RTC_SETTIME, &arg, sizeof(arg)); - print_response(chp); - } else if (!strcmp(argv[0], "send")) { - uint8_t buf[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F - }; - edl_enable(true); - tx_fb = fb_alloc(sizeof(buf), &tx_fifo); - tx_fb->data_ptr = fb_put(tx_fb, sizeof(buf)); - memcpy(tx_fb->data_ptr, buf, sizeof(buf)); - pdu_send(tx_fb, &tx_fifo); - } else { - goto edl_usage; - } - - return; - -edl_usage: - chprintf(chp, "Usage: edl \r\n" - " tx_enable :\r\n" - " Post a TX Enable command to EDL RX queue with \r\n" - " fw_flash :\r\n" - " Post a FW Flash command to EDL RX queue\r\n" - " fw_bank :\r\n" - " Post a FW Bank command to EDL RX queue\r\n" - " fw_verify :\r\n" - " Post a FW Verify command to EDL RX queue\r\n" - " c3_softreset:\r\n" - " Post a C3 Soft Reset command to EDL RX queue\r\n" - " c3_hardreset:\r\n" - " Post a C3 Hard Reset command to EDL RX queue\r\n" - " c3_factoryreset:\r\n" - " Post a C3 Factory Reset command to EDL RX queue\r\n" - " fs_upload :\r\n" - " Upload to via EDL\r\n" - " fs_upload_seg :\r\n" - " Upload bytes starting at from to via EDL\r\n" - " fs_format:\r\n" - " Post FS Format command to EDL RX queue\r\n" - " fs_unmount:\r\n" - " Post FS Unmount command to EDL RX queue\r\n" - " fs_remove :\r\n" - " Post FS Remove command to EDL RX queue\r\n" - " fs_crc :\r\n" - " Post FS CRC command to EDL RX queue\r\n" - " node_enable :\r\n" - " Post a Node Enable command for to EDL RX queue\r\n" - " node_status :\r\n" - " Post a Node Status command for to EDL RX queue\r\n" - " opd_sysenable:\r\n" - " Post a OPD SysEnable command to EDL RX queue\r\n" - " opd_sysdisable:\r\n" - " Post a OPD SysDisable command to EDL RX queue\r\n" - " opd_scan :\r\n" - " Post a OPD Scan command for to EDL RX queue\r\n" - " opd_enable :\r\n" - " Post a OPD Enable command for to EDL RX queue\r\n" - " opd_reset :\r\n" - " Post a OPD Reset command for to EDL RX queue\r\n" - " opd_status :\r\n" - " Post a OPD Status command for to EDL RX queue\r\n" - " send:\r\n" - " Send a packet on EDL link\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_comms.h b/src/f4/app_control/source/test/test_comms.h deleted file mode 100644 index 1d8a6510..00000000 --- a/src/f4/app_control/source/test/test_comms.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TEST_COMMS_H_ -#define _TEST_COMMS_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_edl(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif - diff --git a/src/f4/app_control/source/test/test_crc.c b/src/f4/app_control/source/test/test_crc.c deleted file mode 100644 index 6a7ce433..00000000 --- a/src/f4/app_control/source/test/test_crc.c +++ /dev/null @@ -1,123 +0,0 @@ -#include -#include -#include "test_crc.h" -#include "crc.h" -#include "301/crc16-ccitt.h" -#include "fs.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* CRC Subsystem */ -/*===========================================================================*/ -void cmd_crc(BaseSequentialStream *chp, int argc, char *argv[]) -{ - if (argc < 1) { - goto crc_usage; - } - - if (!strcmp(argv[0], "check")) { - uint8_t test[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F - }; - uint32_t hw_32 = 0xFFFFFFFFU, sw_32 = 0xFFFFFFFFU; - uint32_t lfscrc= 0xFFFFFFFFU; - uint16_t hw_16 = 0xFFFFU; - uint16_t sw_16 = 0xFFFFU; - uint16_t ccitt = 0xFFFFU; - - hw_32 = crc32_hw(test, sizeof(test), hw_32); - sw_32 = crc32_sw(test, sizeof(test), sw_32); -#if (STM32_CRC_PROGRAMMABLE == TRUE) - hw_16 = crc16_ccitt_hw(test, sizeof(test), hw_16); -#endif - sw_16 = crc16_ccitt_sw(test, sizeof(test), sw_16); - ccitt = crc16_ccitt(test, sizeof(test), ccitt); - lfscrc = lfs_crc(lfscrc, test, sizeof(test)); -#if (STM32_CRC_PROGRAMMABLE == FALSE) - chprintf(chp, "CRC16_HW NOT SUPPORTED\r\n"); -#endif - chprintf(chp, "=== All At Once ===\r\n"); - chprintf(chp, "CRC32_HW: 0x%08X\r\n" - "CRC32_SW: 0x%08X\r\n" - "LFS_CRC: 0x%08X\r\n" - "CRC16_HW: 0x%04X\r\n" - "CRC16_SW: 0x%04X\r\n" - "CCITT: 0x%04X\r\n\r\n", - ~hw_32, ~sw_32, ~lfscrc, hw_16, sw_16, ccitt); - - hw_32 = sw_32 = lfscrc = 0xFFFFFFFFU; - hw_16 = sw_16 = ccitt = 0xFFFFU; - for (size_t i = 0; i < sizeof(test); i+=4) { - hw_32 = crc32_hw(&test[i], sizeof(uint32_t), hw_32); - } - for (size_t i = 0; i < sizeof(test); i+=4) { - sw_32 = crc32_sw(&test[i], sizeof(uint32_t), sw_32); - } - for (size_t i = 0; i < sizeof(test); i+=4) { - lfscrc = lfs_crc(lfscrc, &test[i], sizeof(uint32_t)); - } -#if (STM32_CRC_PROGRAMMABLE == TRUE) - for (size_t i = 0; i < sizeof(test); i+=4) { - hw_16 = crc16_ccitt_hw(&test[i], sizeof(uint32_t), hw_16); - } -#endif - for (size_t i = 0; i < sizeof(test); i+=4) { - sw_16 = crc16_ccitt_sw(&test[i], sizeof(uint32_t), sw_16); - } - for (size_t i = 0; i < sizeof(test); i+=4) { - ccitt = crc16_ccitt(&test[i], sizeof(uint32_t), ccitt); - } - chprintf(chp, "=== Word At A Time ===\r\n"); - chprintf(chp, "CRC32_HW: 0x%08X\r\n" - "CRC32_SW: 0x%08X\r\n" - "LFS_CRC: 0x%08X\r\n" - "CRC16_HW: 0x%04X\r\n" - "CRC16_SW: 0x%04X\r\n" - "CCITT: 0x%04X\r\n\r\n", - ~hw_32, ~sw_32, ~lfscrc, hw_16, sw_16, ccitt); - hw_32 = sw_32 = lfscrc = 0xFFFFFFFFU; - hw_16 = sw_16 = ccitt = 0xFFFFU; - for (size_t i = 0; i < sizeof(test); i++) { - hw_32 = crc32_hw(&test[i], 1, hw_32); - } - for (size_t i = 0; i < sizeof(test); i++) { - sw_32 = crc32_sw(&test[i], 1, sw_32); - } - for (size_t i = 0; i < sizeof(test); i++) { - lfscrc = lfs_crc(lfscrc, &test[i], 1); - } -#if (STM32_CRC_PROGRAMMABLE == TRUE) - for (size_t i = 0; i < sizeof(test); i++) { - hw_16 = crc16_ccitt_hw(&test[i], 1, hw_16); - } -#endif - for (size_t i = 0; i < sizeof(test); i++) { - sw_16 = crc16_ccitt_sw(&test[i], 1, sw_16); - } - for (size_t i = 0; i < sizeof(test); i++) { - ccitt = crc16_ccitt(&test[i], 1, ccitt); - } - chprintf(chp, "=== Byte At A Time ===\r\n"); - chprintf(chp, "CRC32_HW: 0x%08X\r\n" - "CRC32_SW: 0x%08X\r\n" - "LFS_CRC: 0x%08X\r\n" - "CRC16_HW: 0x%04X\r\n" - "CRC16_SW: 0x%04X\r\n" - "CCITT: 0x%04X\r\n\r\n", - ~hw_32, ~sw_32, ~lfscrc, hw_16, sw_16, ccitt); - } else { - goto crc_usage; - } - - return; - -crc_usage: - chprintf(chp, "Usage: crc \r\n" - " check:\r\n" - " Check consistency of CRC implementations\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_crc.h b/src/f4/app_control/source/test/test_crc.h deleted file mode 100644 index ab66a3fc..00000000 --- a/src/f4/app_control/source/test/test_crc.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_CRC_H_ -#define _TEST_CRC_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_crc(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_deploy.c b/src/f4/app_control/source/test/test_deploy.c deleted file mode 100644 index 78a947dd..00000000 --- a/src/f4/app_control/source/test/test_deploy.c +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include - -#include "test_deploy.h" -#include "chprintf.h" -#include "deployer.h" - - -/*===========================================================================*/ -/* Deployer Testing */ -/*===========================================================================*/ -void cmd_deploy(BaseSequentialStream *chp, int argc, char *argv[]) { - if (argc < 2) { - goto deploy_usage; - } - - uint32_t duration = strtoul(argv[1], NULL, 0); - - if (argv[0][0] == 'h') { - chprintf(chp, "Attempting to deploy helical antenna..."); - deploy_heli(duration); - } else if (argv[0][0] == 't') { - chprintf(chp, "Attempting to deploy turnstile antenna..."); - deploy_turn(duration); - } else { - goto deploy_usage; - } - - chprintf(chp, "Done!\r\n"); - - return; - -deploy_usage: - chprintf(chp, "Usage: deploy (h)eli|(t)urn \r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_deploy.h b/src/f4/app_control/source/test/test_deploy.h deleted file mode 100644 index 9ef77ac6..00000000 --- a/src/f4/app_control/source/test/test_deploy.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_DEPLOY_H_ -#define _TEST_DEPLOY_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_deploy(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_fram.c b/src/f4/app_control/source/test/test_fram.c deleted file mode 100644 index 027da78a..00000000 --- a/src/f4/app_control/source/test/test_fram.c +++ /dev/null @@ -1,54 +0,0 @@ -#include -#include -#include "test_fram.h" -#include "fram.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* OreSat C3 FRAM */ -/*===========================================================================*/ -void cmd_fram(BaseSequentialStream *chp, int argc, char *argv[]) -{ - if (argc < 1) { - goto fram_usage; - } - if (!strcmp(argv[0], "read") && argc > 2) { - uint16_t addr = strtoul(argv[1], NULL, 0); - size_t len = strtoul(argv[2], NULL, 0); - uint8_t *buf = calloc(len, sizeof(uint8_t)); - - framRead(&FRAMD1, addr, buf, len); - - for (uint32_t i = 0; i < len; i++) { - if (i % 0x10 == 0) chprintf(chp, "\r\n%04X:", i + addr); - chprintf(chp, " %02X", buf[i]); - } - chprintf(chp, "\r\n"); - - free(buf); - } else if (!strcmp(argv[0], "write") && argc > 3) { - chprintf(chp, "Unimplemented\r\n"); - } else if (!strcmp(argv[0], "erase") && argc > 2) { - uint16_t addr = strtoul(argv[1], NULL, 0); - size_t len = strtoul(argv[2], NULL, 0); - framErase(&FRAMD1, addr, len); - } else if (!strcmp(argv[0], "eraseall")) { - framEraseAll(&FRAMD1); - } else { - goto fram_usage; - } - - return; - -fram_usage: - chprintf(chp, "Usage: fram \r\n" - " read :\r\n" - " Read bytes starting at \r\n" - " erase :\r\n" - " Erase (set to 0) bytes starting at \r\n" - " eraseall\r\n" - " Erase (set to 0) entirety of FRAM\r\n" - "\r\n"); - return; -} - diff --git a/src/f4/app_control/source/test/test_fram.h b/src/f4/app_control/source/test/test_fram.h deleted file mode 100644 index c90fe144..00000000 --- a/src/f4/app_control/source/test/test_fram.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TEST_FRAM_H_ -#define _TEST_FRAM_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_fram(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif - diff --git a/src/f4/app_control/source/test/test_fw.c b/src/f4/app_control/source/test/test_fw.c deleted file mode 100644 index 2e836573..00000000 --- a/src/f4/app_control/source/test/test_fw.c +++ /dev/null @@ -1,194 +0,0 @@ -#include -#include -#include "test_fw.h" -#include "fw.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* Firmware control */ -/*===========================================================================*/ -void cmd_fw(BaseSequentialStream *chp, int argc, char *argv[]) -{ - - if (argc < 1) { - goto fw_usage; - } - - if (!strcmp(argv[0], "erase")) { - flash_error_t ret; - - /* Start the driver, unlocking the flash */ - eflStart(&EFLD1, NULL); - - /* Start erase operation */ - if (argc > 1) { - /* Get sector and sanity check */ - flash_sector_t sector = strtoul(argv[1], NULL, 0); - if (sector >= EFLD1.descriptor->sectors_count) { - chprintf(chp, "Invalid sector\r\n"); - goto fw_usage; - } - - /* Erase Sector */ - chprintf(chp, "Erasing sector %u... ", sector); - ret = flashStartEraseSector(&EFLD1, sector); - } else { - /* Erase Bank 2 */ - chprintf(chp, "Erasing Bank %d... ", (SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE ? BANK_0 : BANK_1)); - ret = flashStartEraseAll(&EFLD1); - } - - /* Wait for erase operation to complete */ - if (ret == FLASH_NO_ERROR) { - /* Initiated successfully, wait for completion */ - ret = flashWaitErase((BaseFlash*)&EFLD1); - } - - /* Verify completion */ - if (ret != FLASH_NO_ERROR) { - chprintf(chp, "Error with erase operation: %d\r\n", ret); - return; - } - chprintf(chp, "Done!\r\n"); - - /* Stop the driver, locking the flash */ - eflStop(&EFLD1); - } else if (!strcmp(argv[0], "verifyerase") && argc > 1) { - /* Start the driver, unlocking the flash */ - eflStart(&EFLD1, NULL); - - /* Get sector and sanity check */ - flash_sector_t sector = strtoul(argv[1], NULL, 0); - if (sector >= EFLD1.descriptor->sectors_count) { - chprintf(chp, "Invalid sector\r\n"); - goto fw_usage; - } - - /* Query for completion status and verify erase */ - chprintf(chp, "Erase query returned %d\r\n", flashQueryErase(&EFLD1, NULL)); - chprintf(chp, "Erase verify returned %d\r\n", flashVerifyErase(&EFLD1, sector)); - - /* Stop the driver, locking the flash */ - eflStop(&EFLD1); - } else if (!strcmp(argv[0], "read") && argc > 3) { - flash_offset_t offset = strtoul(argv[1], NULL, 0); - size_t len = strtoul(argv[2], NULL, 0); - int err; - - chprintf(chp, "Reading %d bytes of flash to %s starting at offset 0x%06X... ", len, argv[3], offset); - err = fw_read(&EFLD1, argv[3], offset, len); - if (err != 0) { - chprintf(chp, "Error: Return code %d\r\n", err); - return; - } - chprintf(chp, "Done!\r\n"); - } else if (!strcmp(argv[0], "write") && argc > 2) { - uint32_t offset = strtoul(argv[1], NULL, 0); - int err; - - chprintf(chp, "Writing %s to flash at offset %05X... ", argv[2], offset); - err = fw_write(&EFLD1, argv[2], offset); - if (err != 0) { - chprintf(chp, "Error: Return code %d\r\n", err); - return; - } - chprintf(chp, "Done!\r\n"); - } else if (!strcmp(argv[0], "flash") && argc > 2) { - uint32_t crc = strtoul(argv[2], NULL, 0); - int err; - - chprintf(chp, "Erasing offline bank and writing %s... ", argv[1]); - err = fw_flash(&EFLD1, argv[1], crc); - if (err != 0) { - chprintf(chp, "Error: Return code %d\r\n", err); - return; - } - chprintf(chp, "Done!\r\n"); - } else if (!strcmp(argv[0], "crc") && argc > 2) { - fw_bank_t bank; - size_t len = strtoul(argv[2], NULL, 0); - if (argv[1][0] == '0') { - bank = BANK_0; - } else if (argv[1][0] == '1') { - bank = BANK_1; - } else { - goto fw_usage; - } - - chprintf(chp, "Bank %d CRC: 0x%08X\r\n\r\n", bank, fw_crc(&EFLD1, bank, len)); - } else if (!strcmp(argv[0], "verify") && argc > 1) { - fw_bank_t bank; - uint32_t crc; - if (argv[1][0] == '0') { - bank = BANK_0; - } else if (argv[1][0] == '1') { - bank = BANK_1; - } else { - goto fw_usage; - } - - chprintf(chp, "Verifying FW in bank %d... ", bank); - crc = fw_verify(&EFLD1, bank); - chprintf(chp, "%s! CRC: 0x%08X\r\n\r\n", (crc ? "VALID" : "INVALID"), crc); - } else if (!strcmp(argv[0], "setinfo") && argc > 3) { - fw_bank_t bank; - fw_info_t fw_info; - fw_info.crc = strtoul(argv[2], NULL, 0); - fw_info.len = strtoul(argv[3], NULL, 0); - if (argv[1][0] == '0') { - bank = BANK_0; - } else if (argv[1][0] == '1') { - bank = BANK_1; - } else { - goto fw_usage; - } - - chprintf(chp, "Setting FW info for bank %d... ", bank); - fw_set_info(fw_info, bank); - chprintf(chp, "Done\r\n"); - } else if (!strcmp(argv[0], "bank") && argc > 1) { - uint32_t bank; - if (argv[1][0] == '0') { - bank = BANK_0; - } else if (argv[1][0] == '1') { - bank = BANK_1; - } else { - goto fw_usage; - } - - chprintf(chp, "Setting next boot bank to %d... ", bank); - int err = fw_set_bank(&EFLD1, bank); - if (err != FLASH_NO_ERROR) { - chprintf(chp, "Error: Return code %d\r\n\r\n", err); - return; - } - chprintf(chp, "Done!\r\n\r\n"); - } else { - goto fw_usage; - } - - return; - -fw_usage: - chprintf(chp, "Usage: fw \r\n" - " erase [sector]:\r\n" - " Erase [sector] or the offline bank if no sector provided\r\n" - " verifyerase :\r\n" - " Verify sector erased\r\n" - " read :\r\n" - " Read bytes of flash starting at into \r\n" - " write :\r\n" - " Write to flash starting at \r\n" - " flash :\r\n" - " Write to offline bank\r\n" - " crc :\r\n" - " Print CRC for assuming length \r\n" - " verify :\r\n" - " Verify firmware in against CRC\r\n" - " setinfo :\r\n" - " Set health info to and \r\n" - " bank :\r\n" - " Set flash bank to for next boot\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_fw.h b/src/f4/app_control/source/test/test_fw.h deleted file mode 100644 index a26b8803..00000000 --- a/src/f4/app_control/source/test/test_fw.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_FW_H_ -#define _TEST_FW_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_fw(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_hmac.c b/src/f4/app_control/source/test/test_hmac.c deleted file mode 100644 index 4b02131e..00000000 --- a/src/f4/app_control/source/test/test_hmac.c +++ /dev/null @@ -1,323 +0,0 @@ -#include -#include -#include - -#include "test_hmac.h" -#include "chprintf.h" - -struct TestCase { - const uint8_t *key; - const size_t keylen; - const uint8_t *data; - const size_t datalen; - const uint8_t *hmac; - const size_t hmaclen; -}; - -void testHMACSHA256(BaseSequentialStream *chp, CRYDriver *cryp, const struct TestCase * tc) { - HMACSHA256Context ctx = {0}; - - chprintf(chp, "cryLoadHMACTransientKey() ... "); - if (cryLoadHMACTransientKey(cryp, tc->keylen, tc->key) != CRY_NOERROR) { - chprintf(chp, "failed\r\n"); - return; - } else { - chprintf(chp, "good\r\n"); - } - - chprintf(chp, "cryHMACSHA256Init() ... "); - if (cryHMACSHA256Init(cryp, &ctx) != CRY_NOERROR) { - chprintf(chp, "failed\r\n"); - return; - } else { - chprintf(chp, "good\r\n"); - } - - chprintf(chp, "cryHMACSHA256Update() ... "); - if (cryHMACSHA256Update(cryp, &ctx, tc->datalen, tc->data) != CRY_NOERROR) { - chprintf(chp, "failed\r\n"); - return; - } else { - chprintf(chp, "good\r\n"); - } - - chprintf(chp, "cryHMACSHA256Final() ... "); - uint8_t out[32] = {0}; - if (cryHMACSHA256Final(cryp, &ctx, out) != CRY_NOERROR) { - chprintf(chp, "HMACFinal failed\r\n"); - return; - } else { - chprintf(chp, "good\r\n"); - } - - chprintf(chp, "HMAC result comparison ... "); - if (memcmp(out, tc->hmac, sizeof(out) < tc->hmaclen ? sizeof(out) : tc->hmaclen) != 0) { - chprintf(chp, "failed\r\n"); - chprintf(chp, "- Expect:"); - for(size_t i = 0; i < tc->hmaclen; ++i) { - chprintf(chp, " %02x", tc->hmac[i]); - } - chprintf(chp, "\r\n- Result:"); - for(size_t i = 0; i < sizeof(out); ++i) { - chprintf(chp, " %02x", out[i]); - } - chprintf(chp, "\r\n"); - } else { - chprintf(chp, "good\r\n"); - } -} - - -void cmd_hmac(BaseSequentialStream *chp, int argc, char *argv[]) -{ - (void) argc; - (void) argv; - - /* Taken from RFC 4231: Test Vectors for HMAC-SHA-256 */ - // 4.2. Test Case 1 - static const uint8_t tc1_key[] = { // 20 bytes - 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, - 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, }; - static const uint8_t tc1_data[] = { // "Hi There" - 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 }; - static const uint8_t tc1_hmac[] = { - 0xb0, 0x34, 0x4c, 0x61, 0xd8, 0xdb, 0x38, 0x53, 0x5c, 0xa8, 0xaf, 0xce, - 0xaf, 0x0b, 0xf1, 0x2b, 0x88, 0x1d, 0xc2, 0x00, 0xc9, 0x83, 0x3d, 0xa7, - 0x26, 0xe9, 0x37, 0x6c, 0x2e, 0x32, 0xcf, 0xf7 }; - static_assert(sizeof(tc1_key) == 20); - static_assert(sizeof(tc1_data) == sizeof("Hi There")-1); - osalDbgAssert(memcmp(tc1_data, "Hi There", - sizeof(tc1_data)) == 0, "TC1 data does not match expected string"); - static_assert(sizeof(tc1_hmac) == 32); - - const struct TestCase TC1 = { - .key = tc1_key, - .keylen = sizeof(tc1_key), - .data = tc1_data, - .datalen = sizeof(tc1_data), - .hmac = tc1_hmac, - .hmaclen = sizeof(tc1_hmac), - }; - - // 4.3. Test Case 2: Test with a key shorter than the length of the HMAC - // output. - static const uint8_t tc2_key[] = { 0x4a, 0x65, 0x66, 0x65 }; // "Jefe" - static const uint8_t tc2_data[] = { // "what do ya want for nothing?" - 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20, 0x79, 0x61, 0x20, 0x77, - 0x61, 0x6e, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, 0x74, 0x68, - 0x69, 0x6e, 0x67, 0x3f }; - static const uint8_t tc2_hmac[] = { - 0x5b, 0xdc, 0xc1, 0x46, 0xbf, 0x60, 0x75, 0x4e, 0x6a, 0x04, 0x24, 0x26, - 0x08, 0x95, 0x75, 0xc7, 0x5a, 0x00, 0x3f, 0x08, 0x9d, 0x27, 0x39, 0x83, - 0x9d, 0xec, 0x58, 0xb9, 0x64, 0xec, 0x38, 0x43 }; - static_assert(sizeof(tc2_key) == sizeof("Jefe")-1); - osalDbgAssert(memcmp(tc2_key, "Jefe", - sizeof(tc2_key)) == 0, "TC2 key does not match expected string"); - static_assert(sizeof(tc2_data) == sizeof("what do ya want for nothing?")-1); - osalDbgAssert(memcmp(tc2_data, "what do ya want for nothing?", - sizeof(tc2_data)) == 0, "TC2 data does not match expected string"); - static_assert(sizeof(tc2_hmac) == 32); - - const struct TestCase TC2 = { - .key = tc2_key, - .keylen = sizeof(tc2_key), - .data = tc2_data, - .datalen = sizeof(tc2_data), - .hmac = tc2_hmac, - .hmaclen = sizeof(tc2_hmac), - }; - - // 4.4. Test Case 3: Test with a combined length of key and data that is - // larger than 64 bytes (= block-size of SHA-224 and SHA-256). - static const uint8_t tc3_key[] = { // 20 bytes - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; - static const uint8_t tc3_data[] = { // 50 bytes - 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, - 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, - 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, - 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, - 0xdd, 0xdd }; - static const uint8_t tc3_hmac[] = { - 0x77, 0x3e, 0xa9, 0x1e, 0x36, 0x80, 0x0e, 0x46, 0x85, 0x4d, 0xb8, 0xeb, - 0xd0, 0x91, 0x81, 0xa7, 0x29, 0x59, 0x09, 0x8b, 0x3e, 0xf8, 0xc1, 0x22, - 0xd9, 0x63, 0x55, 0x14, 0xce, 0xd5, 0x65, 0xfe }; - static_assert(sizeof(tc3_key) == 20); - static_assert(sizeof(tc3_data) == 50); - static_assert(sizeof(tc3_hmac) == 32); - - const struct TestCase TC3 = { - .key = tc3_key, - .keylen = sizeof(tc3_key), - .data = tc3_data, - .datalen = sizeof(tc3_data), - .hmac = tc3_hmac, - .hmaclen = sizeof(tc3_hmac), - }; - - // 4.5. Test Case 4: Test with a combined length of key and data that is - // larger than 64 bytes (= block-size of SHA-224 and SHA-256). - static const uint8_t tc4_key[] = { // 25 bytes - 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, - 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, - 0x19 }; - static const uint8_t tc4_data[] = { // 50 bytes - 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, - 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, - 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, - 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, 0xcd, - 0xcd, 0xcd }; - static const uint8_t tc4_hmac[] = { - 0x82, 0x55, 0x8a, 0x38, 0x9a, 0x44, 0x3c, 0x0e, 0xa4, 0xcc, 0x81, 0x98, - 0x99, 0xf2, 0x08, 0x3a, 0x85, 0xf0, 0xfa, 0xa3, 0xe5, 0x78, 0xf8, 0x07, - 0x7a, 0x2e, 0x3f, 0xf4, 0x67, 0x29, 0x66, 0x5b }; - static_assert(sizeof(tc4_key) == 25); - static_assert(sizeof(tc4_data) == 50); - static_assert(sizeof(tc4_hmac) == 32); - - const struct TestCase TC4 = { - .key = tc4_key, - .keylen = sizeof(tc4_key), - .data = tc4_data, - .datalen = sizeof(tc4_data), - .hmac = tc4_hmac, - .hmaclen = sizeof(tc4_hmac), - }; - - // 4.6. Test Case 5: Test with a truncation of output to 128 bits. - static const uint8_t tc5_key[] = { // 20 bytes - 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, - 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }; - static const uint8_t tc5_data[] = { // "Test With Truncation" - 0x54, 0x65, 0x73, 0x74, 0x20, 0x57, 0x69, 0x74, 0x68, 0x20, 0x54, 0x72, - 0x75, 0x6e, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e }; - static const uint8_t tc5_hmac[] = { - 0xa3, 0xb6, 0x16, 0x74, 0x73, 0x10, 0x0e, 0xe0, 0x6e, 0x0c, 0x79, 0x6c, - 0x29, 0x55, 0x55, 0x2b }; - static_assert(sizeof(tc5_key) == 20); - static_assert(sizeof(tc5_data) == sizeof("Test With Truncation") - 1); - osalDbgAssert(memcmp(tc5_data, "Test With Truncation", - sizeof(tc5_data)) == 0, "TC5 data does not match expected string"); - static_assert(sizeof(tc5_hmac)*CHAR_BIT == 128); - - const struct TestCase TC5 = { - .key = tc5_key, - .keylen = sizeof(tc5_key), - .data = tc5_data, - .datalen = sizeof(tc5_data), - .hmac = tc5_hmac, - .hmaclen = sizeof(tc5_hmac), - }; - - // 4.7. Test Case 6: Test with a key larger than 128 bytes (= block-size - // of SHA-384 and SHA-512) - static const uint8_t tc6_key[] = { // 131 bytes - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; - static const uint8_t tc6_data[] = { // "Test Using Larger Than Block-Size - // Key - Hash Key First" - 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69, 0x6e, 0x67, 0x20, 0x4c, - 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, 0x20, 0x42, - 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x53, 0x69, 0x7a, 0x65, 0x20, 0x4b, 0x65, - 0x79, 0x20, 0x2d, 0x20, 0x48, 0x61, 0x73, 0x68, 0x20, 0x4b, 0x65, 0x79, - 0x20, 0x46, 0x69, 0x72, 0x73, 0x74 }; - static const uint8_t tc6_hmac[] = { - 0x60, 0xe4, 0x31, 0x59, 0x1e, 0xe0, 0xb6, 0x7f, 0x0d, 0x8a, 0x26, 0xaa, - 0xcb, 0xf5, 0xb7, 0x7f, 0x8e, 0x0b, 0xc6, 0x21, 0x37, 0x28, 0xc5, 0x14, - 0x05, 0x46, 0x04, 0x0f, 0x0e, 0xe3, 0x7f, 0x54 }; - static_assert(sizeof(tc6_key) == 131); - static_assert(sizeof(tc6_data) == sizeof("Test Using Larger Than Block-" - "Size Key - Hash Key First") - 1); - osalDbgAssert(memcmp(tc6_data, "Test Using Larger Than Block-Size Key - " - "Hash Key First", - sizeof(tc6_data)) == 0, "TC6 Data does not match expected string"); - static_assert(sizeof(tc6_hmac) == 32); - - const struct TestCase TC6 = { - .key = tc6_key, - .keylen = sizeof(tc6_key), - .data = tc6_data, - .datalen = sizeof(tc6_data), - .hmac = tc6_hmac, - .hmaclen = sizeof(tc6_hmac), - }; - - // 4.8. Test Case 7: Test with a key and data that is larger than 128 - // bytes (= block-size of SHA-384 and SHA-512). - static const uint8_t tc7_key[] = { // 131 bytes - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; - static const uint8_t tc7_data[] = { // "This is a test using a larger than - // block-size key and a larger than block-size data. The key needs to - // be hashed before being used by the HMAC algorithm." - 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x74, 0x65, - 0x73, 0x74, 0x20, 0x75, 0x73, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x20, 0x6c, - 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, 0x68, 0x61, 0x6e, 0x20, 0x62, - 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x6b, 0x65, - 0x79, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x61, 0x20, 0x6c, 0x61, 0x72, 0x67, - 0x65, 0x72, 0x20, 0x74, 0x68, 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63, - 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x64, 0x61, 0x74, 0x61, 0x2e, - 0x20, 0x54, 0x68, 0x65, 0x20, 0x6b, 0x65, 0x79, 0x20, 0x6e, 0x65, 0x65, - 0x64, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x62, 0x65, 0x20, 0x68, 0x61, 0x73, - 0x68, 0x65, 0x64, 0x20, 0x62, 0x65, 0x66, 0x6f, 0x72, 0x65, 0x20, 0x62, - 0x65, 0x69, 0x6e, 0x67, 0x20, 0x75, 0x73, 0x65, 0x64, 0x20, 0x62, 0x79, - 0x20, 0x74, 0x68, 0x65, 0x20, 0x48, 0x4d, 0x41, 0x43, 0x20, 0x61, 0x6c, - 0x67, 0x6f, 0x72, 0x69, 0x74, 0x68, 0x6d, 0x2e}; - static const uint8_t tc7_hmac[] = { - 0x9b, 0x09, 0xff, 0xa7, 0x1b, 0x94, 0x2f, 0xcb, 0x27, 0x63, 0x5f, 0xbc, - 0xd5, 0xb0, 0xe9, 0x44, 0xbf, 0xdc, 0x63, 0x64, 0x4f, 0x07, 0x13, 0x93, - 0x8a, 0x7f, 0x51, 0x53, 0x5c, 0x3a, 0x35, 0xe2 }; - - static_assert(sizeof(tc7_key) == 131); - static_assert(sizeof(tc7_data) == sizeof("This is a test using a larger " - "than block-size key and a larger than block-size data. The key needs " - "to be hashed before being used by the HMAC algorithm.") - 1); - osalDbgAssert(memcmp(tc7_data, "This is a test using a larger than block-" - "size key and a larger than block-size data. The key needs to be " - "hashed before being used by the HMAC algorithm.", - sizeof(tc7_data)) == 0, "Test 7 data does not match expected string"); - static_assert(sizeof(tc7_hmac) == 32); - - const struct TestCase TC7 = { - .key = tc7_key, - .keylen = sizeof(tc7_key), - .data = tc7_data, - .datalen = sizeof(tc7_data), - .hmac = tc7_hmac, - .hmaclen = sizeof(tc7_hmac), - }; - - chprintf(chp, "TC1\r\n"); - testHMACSHA256(chp, &CRYD1, &TC1); - chprintf(chp, "TC2\r\n"); - testHMACSHA256(chp, &CRYD1, &TC2); - chprintf(chp, "TC3\r\n"); - testHMACSHA256(chp, &CRYD1, &TC3); - chprintf(chp, "TC4\r\n"); - testHMACSHA256(chp, &CRYD1, &TC4); - chprintf(chp, "TC5\r\n"); - testHMACSHA256(chp, &CRYD1, &TC5); - chprintf(chp, "TC6\r\n"); - testHMACSHA256(chp, &CRYD1, &TC6); - chprintf(chp, "TC7\r\n"); - testHMACSHA256(chp, &CRYD1, &TC7); - chprintf(chp, "HMAC test complete\r\n"); -} diff --git a/src/f4/app_control/source/test/test_hmac.h b/src/f4/app_control/source/test/test_hmac.h deleted file mode 100644 index 39574c6a..00000000 --- a/src/f4/app_control/source/test/test_hmac.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_HMAC_H_ -#define _TEST_HMAC_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_hmac(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_lfs.c b/src/f4/app_control/source/test/test_lfs.c deleted file mode 100644 index 0686dc1c..00000000 --- a/src/f4/app_control/source/test/test_lfs.c +++ /dev/null @@ -1,221 +0,0 @@ -#include -#include -#include "test_lfs.h" -#include "fs.h" - -#define BUF_SIZE 256 - -/*===========================================================================*/ -/* OreSat LFS Operations */ -/*===========================================================================*/ -void cmd_lfs(BaseSequentialStream *chp, int argc, char *argv[]) -{ - int ret; - lfs_file_t *file; - lfs_dir_t *dir; - struct lfs_info info; - char buf[BUF_SIZE]; - - if (!strcmp(argv[0], "ls") && argc > 1) { - dir = dir_open(&FSD1, argv[1]); - if (dir == NULL) { - chprintf(chp, "Error in dir_open: %d\r\n", FSD1.err); - return; - } - do { - ret = dir_read(&FSD1, dir, &info); - if (ret <= 0) { - if (ret < 0) { - chprintf(chp, "Error in dir_read: %d\r\n", ret); - } - continue; - } - if (info.type == LFS_TYPE_REG) { - chprintf(chp, "reg "); - } else if (info.type == LFS_TYPE_DIR) { - chprintf(chp, "dir "); - } else { - chprintf(chp, "? "); - } - chprintf(chp, "%8u %s\r\n", info.size, info.name); - } while (ret > 0); - ret = dir_close(&FSD1, dir); - if (ret < 0) { - chprintf(chp, "Error in dir_close: %d\r\n", ret); - return; - } - chprintf(chp, "\r\n"); - } else if (!strcmp(argv[0], "mkdir") && argc > 1) { - ret = fs_mkdir(&FSD1, argv[1]); - if (ret < 0) { - chprintf(chp, "Error in fs_mkdir: %d\r\n"); - return; - } - } else if (!strcmp(argv[0], "rm") && argc > 1) { - ret = fs_remove(&FSD1, argv[1]); - if (ret < 0) { - chprintf(chp, "Error in fs_remove: %d\r\n"); - return; - } - } else if (!strcmp(argv[0], "crc") && argc > 1) { - file = file_open(&FSD1, argv[1], LFS_O_RDONLY); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - chprintf(chp, "CRC32: 0x%08X\r\n", file_crc(&FSD1, file)); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "cat") && argc > 1) { - file = file_open(&FSD1, argv[1], LFS_O_RDONLY); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - ret = file_read(&FSD1, file, buf, BUF_SIZE - 1); - if (ret < 0) { - chprintf(chp, "Error in file_read: %d\r\n", ret); - file_close(&FSD1, file); - return; - } - buf[ret] = '\0'; - chprintf(chp, "%s\r\n", buf); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "hexdump") && argc > 1) { - file = file_open(&FSD1, argv[1], LFS_O_RDONLY); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - ret = file_read(&FSD1, file, buf, BUF_SIZE); - if (ret < 0) { - chprintf(chp, "Error in file_read: %d\r\n", ret); - file_close(&FSD1, file); - return; - } - for (int i = 0; i < ret; i++) { - if (i % 0x10 == 0) chprintf(chp, "\r\n%04X:", i); - chprintf(chp, " %02X", buf[i]); - } - chprintf(chp, "\r\n"); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "load") && argc > 1) { - uint8_t buf[BUF_SIZE] = {0}; - char line[BUF_SIZE * 2] = {0}; - char c, *p = line; - size_t count = 0; - file = file_open(&FSD1, argv[1], LFS_O_RDWR | LFS_O_CREAT | LFS_O_TRUNC); - if (file == NULL) { - chprintf(chp, "Error in file_open: %d\r\n", FSD1.err); - return; - } - - while (streamRead(chp, (uint8_t*)&c, 1) != 0 && c != 4) { - c = toupper(c); - - if (isdigit(c) || (c >= 'A' && c <= 'F')) { - streamPut(chp, c); - *(p++) = c; - if (p == &line[BUF_SIZE * 2]) { - for (size_t off = 0; off < BUF_SIZE; off++) { - sscanf(&line[off*2], "%2hhx", &buf[off]); - } - p = line; - ret = file_write(&FSD1, file, buf, BUF_SIZE); - if (ret < 0) { - chprintf(chp, "Error in file_write: %d\r\n", ret); - break; - } - count += ret; - } - } else if ((c == 8) || (c == 127)) { - if (p != line) { - streamPut(chp, 0x08); - streamPut(chp, 0x20); - streamPut(chp, 0x08); - p--; - } - } - } - if (p != line) { - size_t len = (p - line) / 2; - for (size_t off = 0; off < len; off++) { - sscanf(&line[off*2], "%2hhx", &buf[off]); - } - ret = file_write(&FSD1, file, buf, len); - if (ret < 0) { - chprintf(chp, "Error in file_write: %d\r\n", ret); - } else { - count += ret; - } - } - chprintf(chp, "\r\nWrote %u bytes to %s\r\n", count, argv[1]); - - ret = file_close(&FSD1, file); - if (ret < 0) { - chprintf(chp, "Error in file_close: %d\r\n", ret); - return; - } - } else if (!strcmp(argv[0], "mount")) { - chprintf(chp, "Attempting to mount LFS...\r\n"); - ret = fs_mount(&FSD1, false); - if (ret < 0) { - chprintf(chp, "Mount failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else if (!strcmp(argv[0], "unmount")) { - chprintf(chp, "Attempting to unmount LFS...\r\n"); - ret = fs_unmount(&FSD1); - if (ret < 0) { - chprintf(chp, "Unmount failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else if (!strcmp(argv[0], "format")) { - chprintf(chp, "Attempting to format LFS...\r\n"); - ret = fs_format(&FSD1); - if (ret < 0) { - chprintf(chp, "Format failed: %d\r\n", ret); - return; - } - chprintf(chp, "OK\r\n"); - } else { - goto lfs_usage; - } - - return; - -lfs_usage: - chprintf(chp, "Usage: lfs \r\n" - " ls: List directories\r\n" - " mkdir: Make a directory\r\n" - " rm: Delete file or directory\r\n" - " crc: Print CRC32 of file\r\n" - " cat: Dump 255 bytes of file as string\r\n" - " hexdump: Dump 255 bytes of file as hex\r\n" - "\r\n" - " mount: Mount LFS\r\n" - " unmount: Unmount LFS\r\n" - " format: Format eMMC for LFS\r\n" - "\r\n"); - return; -} - diff --git a/src/f4/app_control/source/test/test_lfs.h b/src/f4/app_control/source/test/test_lfs.h deleted file mode 100644 index 3867f5ce..00000000 --- a/src/f4/app_control/source/test/test_lfs.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_LFS_H_ -#define _TEST_LFS_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_lfs(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_mmc.c b/src/f4/app_control/source/test/test_mmc.c deleted file mode 100644 index d86467d2..00000000 --- a/src/f4/app_control/source/test/test_mmc.c +++ /dev/null @@ -1,198 +0,0 @@ -#include - -#include "ch.h" -#include "hal.h" -#include "test_mmc.h" -#include "chprintf.h" -#include "fs.h" - -#define SDC_BURST_SIZE 16 -#define SDC (FSD1.config->sdcp) - -int mmc_enable(FSDriver *fsp); -int mmc_disable(FSDriver *fsp); - -/* Buffer for block read/write operations, note that extra bytes are - allocated in order to support unaligned operations.*/ -static uint8_t buf[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE + 4]; - -/* Additional buffer for sdcErase() test */ -static uint8_t buf2[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE ]; - -/*===========================================================================*/ -/* eMMC Testing */ -/*===========================================================================*/ -void cmd_mmc(BaseSequentialStream *chp, int argc, char *argv[]) { - systime_t start, end; - uint32_t n, startblk; - - if (argc < 1) { - chprintf(chp, "Usage: mmc \r\n" - " enable: Enable eMMC subsystem\r\n" - " disable: Disable eMMC subsystem\r\n" - "\r\n" - " testread: Test read functionality\r\n" - " testwrite: Test write functionality\r\n" - " testall: Test all functionality\r\n"); - return; - } - - if (strcmp(argv[0], "enable") == 0) { - int err; - chprintf(chp, "Enabling eMMC... "); - - /* Attempt to enable eMMC subsystem */ - err = mmc_enable(&FSD1); - if (err) { - chprintf(chp, "failed with code %d\r\n", err); - return; - } - - /* Print details of the device */ - chprintf(chp, "OK\r\n\r\nDevice Info\r\n"); - chprintf(chp, "CSD : %08X %8X %08X %08X \r\n", - SDC->csd[3], SDC->csd[2], SDC->csd[1], SDC->csd[0]); - chprintf(chp, "CID : %08X %8X %08X %08X \r\n", - SDC->cid[3], SDC->cid[2], SDC->cid[1], SDC->cid[0]); - chprintf(chp, "Capacity : %DMB\r\n", SDC->capacity / 2048); - chprintf(chp, "\r\n"); - - return; - } else if (strcmp(argv[0], "disable") == 0) { - int err; - chprintf(chp, "Disabling eMMC... "); - - /* Disable eMMC subsystem */ - err = mmc_disable(&FSD1); - if (err) { - chprintf(chp, "failed with code %d\r\n", err); - return; - } - - chprintf(chp, "OK\r\n"); - return; - } - - /* The test is performed in the middle of the flash area.*/ - startblk = (SDC->capacity / MMCSD_BLOCK_SIZE) / 2; - if ((strcmp(argv[0], "testread") == 0) || - (strcmp(argv[0], "testall") == 0)) { - - /* Single block read performance, aligned.*/ - chprintf(chp, "Single block aligned read performance: "); - start = chVTGetSystemTime(); - end = chTimeAddX(start, TIME_MS2I(1000)); - n = 0; - do { - if (blkRead(SDC, startblk, buf, 1)) { - chprintf(chp, "failed\r\n"); - return; - } - n++; - } while (chVTIsSystemTimeWithin(start, end)); - chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); - - /* Multiple sequential blocks read performance, aligned.*/ - chprintf(chp, "16 sequential blocks aligned read performance: "); - start = chVTGetSystemTime(); - end = chTimeAddX(start, TIME_MS2I(1000)); - n = 0; - do { - if (blkRead(SDC, startblk, buf, SDC_BURST_SIZE)) { - chprintf(chp, "failed\r\n"); - return; - } - n += SDC_BURST_SIZE; - } while (chVTIsSystemTimeWithin(start, end)); - chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); - -#if STM32_SDC_SDIO_UNALIGNED_SUPPORT - /* Single block read performance, unaligned.*/ - chprintf(chp, "Single block unaligned read performance: "); - start = chVTGetSystemTime(); - end = chTimeAddX(start, TIME_MS2I(1000)); - n = 0; - do { - if (blkRead(SDC, startblk, buf + 1, 1)) { - chprintf(chp, "failed\r\n"); - return; - } - n++; - } while (chVTIsSystemTimeWithin(start, end)); - chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); - - /* Multiple sequential blocks read performance, unaligned.*/ - chprintf(chp, "16 sequential blocks unaligned read performance: "); - start = chVTGetSystemTime(); - end = chTimeAddX(start, TIME_MS2I(1000)); - n = 0; - do { - if (blkRead(SDC, startblk, buf + 1, SDC_BURST_SIZE)) { - chprintf(chp, "failed\r\n"); - return; - } - n += SDC_BURST_SIZE; - } while (chVTIsSystemTimeWithin(start, end)); - chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); -#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ - } - - if ((strcmp(argv[0], "testwrite") == 0) || - (strcmp(argv[0], "testall") == 0)) { - uint8_t backup[MMCSD_BLOCK_SIZE * 2]; - - /* Backup data */ - blkRead(SDC, startblk, backup, 2); - - memset(buf, 0xAA, MMCSD_BLOCK_SIZE * 2); - chprintf(chp, "Writing..."); - if(blkWrite(SDC, startblk, buf, 2)) { - chprintf(chp, "failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - memset(buf2, 0x55, MMCSD_BLOCK_SIZE * 2); - chprintf(chp, "Reading..."); - if (blkRead(SDC, startblk, buf2, 1)) { - chprintf(chp, "failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - chprintf(chp, "Comparing..."); - if(memcmp(buf, buf2, MMCSD_BLOCK_SIZE) != 0) { - chprintf(chp, "Compare failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - for (unsigned int i = 0; i < MMCSD_BLOCK_SIZE; i++) { - buf[i] = i + 8; - } - chprintf(chp, "Writing..."); - if(blkWrite(SDC, startblk, buf, 2)) { - chprintf(chp, "failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - memset(buf2, 0, MMCSD_BLOCK_SIZE * 2); - chprintf(chp, "Reading..."); - if (blkRead(SDC, startblk, buf2, 1)) { - chprintf(chp, "failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - chprintf(chp, "Comparing..."); - if(memcmp(buf, buf2, MMCSD_BLOCK_SIZE) != 0) { - chprintf(chp, "Compare failed\r\n"); - return; - } - chprintf(chp, "OK\r\n"); - - /* Restore data */ - blkWrite(SDC, startblk, backup, 2); - } -} diff --git a/src/f4/app_control/source/test/test_mmc.h b/src/f4/app_control/source/test/test_mmc.h deleted file mode 100644 index a41e8625..00000000 --- a/src/f4/app_control/source/test/test_mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_MMC_H_ -#define _TEST_MMC_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_mmc(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_opd.c b/src/f4/app_control/source/test/test_opd.c deleted file mode 100644 index 10f0cce8..00000000 --- a/src/f4/app_control/source/test/test_opd.c +++ /dev/null @@ -1,203 +0,0 @@ -#include -#include -#include "test_opd.h" -#include "opd.h" -#include "node_mgr.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* OreSat Node Control */ -/*===========================================================================*/ -void cmd_node(BaseSequentialStream *chp, int argc, char *argv[]) -{ - static uint8_t node_id = 0; - - if (argc < 1) { - goto node_usage; - } else if (argc > 1) { - node_id = strtoul(argv[1], NULL, 0); - chprintf(chp, "Setting persistent Node ID to 0x%02X\r\n", node_id); - } - - if (node_id == 0) { - chprintf(chp, "Please specify an node address at least once (it will persist)\r\n"); - goto node_usage; - } - if (!strcmp(argv[0], "enable")) { - chprintf(chp, "Enabling Node 0x%02X: ", node_id); - if (!node_enable(node_id, true)) { - chprintf(chp, "ENABLED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "disable")) { - chprintf(chp, "Disabling Node 0x%02X: ", node_id); - if (!node_enable(node_id, false)) { - chprintf(chp, "DISABLED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "status")) { - CO_NMT_internalState_t state; - chprintf(chp, "Status of node 0x%02X: ", node_id); - switch (node_status(node_id, &state)) { - case -1: - chprintf(chp, "NOT CONNECTED\r\n"); - break; - case 0: - chprintf(chp, "DISABLED\r\n"); - break; - case 1: - chprintf(chp, "ENABLED\r\n"); - chprintf(chp, "State: %d\r\n", state); - break; - default: - chprintf(chp, "Invalid return code!\r\n"); - break; - } - } else { - goto node_usage; - } - - return; - -node_usage: - chprintf(chp, "Usage: node \r\n" - " enable: Enable managing a node\r\n" - " disable: Disable managing a node\r\n" - " status: Get Node Status\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* OreSat Power Domain Control */ -/*===========================================================================*/ -void cmd_opd(BaseSequentialStream *chp, int argc, char *argv[]) -{ - static i2caddr_t opd_addr = 0; - opd_status_t status = {0}; - - if (argc < 1) { - goto opd_usage; - } else if (argc > 1) { - opd_addr = strtoul(argv[1], NULL, 0); - chprintf(chp, "Setting persistent board address to 0x%02X\r\n", opd_addr); - } - - if (!strcmp(argv[0], "sysenable")) { - chprintf(chp, "Enabling OPD subsystem\r\n"); - opd_start(); - } else if (!strcmp(argv[0], "sysdisable")) { - chprintf(chp, "Disabling OPD subsystem\r\n"); - opd_stop(); - } else if (!strcmp(argv[0], "sysrestart")) { - chprintf(chp, "Restarting OPD subsystem\r\n"); - opd_stop(); - opd_start(); - } else if (!strcmp(argv[0], "rescan")) { - chprintf(chp, "Re-scanning OPD devices\r\n"); - opd_scan(false); - } else if (!strcmp(argv[0], "summary")) { - chprintf(chp, "Board summary:\r\n"); - for (i2caddr_t i = OPD_MIN_ADDR; i <= OPD_MAX_ADDR; i++) { - if (!opd_status(i, &status)) { - chprintf(chp, "0x%02X: CONNECTED - %s - %s\r\n", i, - (status.odr & OPD_PIN_MASK(OPD_EN) ? "ENABLED" : "DISABLED"), - (status.input & OPD_PIN_MASK(OPD_FAULT) ? "TRIPPED" : "NOT TRIPPED")); - } else { - chprintf(chp, "0x%02X: NOT CONNECTED\r\n", i); - } - } - } else { - if (opd_addr == 0) { - chprintf(chp, "Please specify an OPD address at least once (it will persist)\r\n"); - goto opd_usage; - } - if (!strcmp(argv[0], "enable")) { - chprintf(chp, "Enabling board 0x%02X: ", opd_addr); - if (!opd_enable(opd_addr, true)) { - chprintf(chp, "ENABLED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "disable")) { - chprintf(chp, "Disabling board 0x%02X: ", opd_addr); - if (!opd_enable(opd_addr, false)) { - chprintf(chp, "DISABLED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "reset")) { - chprintf(chp, "Resetting board 0x%02X: ", opd_addr); - if (!opd_reset(opd_addr)) { - chprintf(chp, "RESET\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "reinit")) { - chprintf(chp, "Attempting to reinitialize 0x%02X: ", opd_addr); - if (opd_probe(opd_addr, true)) { - chprintf(chp, "CONNECTED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "probe")) { - chprintf(chp, "Probing board 0x%02X: ", opd_addr); - if (opd_probe(opd_addr, false)) { - chprintf(chp, "CONNECTED\r\n"); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "status")) { - chprintf(chp, "Status of board 0x%02X: ", opd_addr); - if (!opd_status(opd_addr, &status)) { - chprintf(chp, "CONNECTED\r\n"); - chprintf(chp, "State: %s-%s\r\n", - (status.odr & OPD_PIN_MASK(OPD_EN) ? "ENABLED" : "DISABLED"), - (status.input & OPD_PIN_MASK(OPD_FAULT) ? "TRIPPED" : "NOT TRIPPED")); - chprintf(chp, "Raw register values:\r\n"); - chprintf(chp, "Input: %02X\r\n", status.input); - chprintf(chp, "Output: %02X\r\n", status.odr); - chprintf(chp, "Polarity: %02X\r\n", status.pol); - chprintf(chp, "Mode: %02X\r\n", status.mode); - chprintf(chp, "Timeout: %02X\r\n", status.timeout); - } else { - chprintf(chp, "NOT CONNECTED\r\n"); - } - } else if (!strcmp(argv[0], "boot")) { - int retval = opd_boot(opd_addr); - chprintf(chp, "Boot returned 0x%02X\r\n", retval); - } else if (!strcmp(argv[0], "linux_normal")) { - chprintf(chp, "Linux boot normal\r\n"); - opd_linux_recover(opd_addr, false); - } else if (!strcmp(argv[0], "linux_recover")) { - chprintf(chp, "Linux boot recovery\r\n"); - opd_linux_recover(opd_addr, true); - } else { - goto opd_usage; - } - } - - return; - -opd_usage: - chprintf(chp, "Usage: opd \r\n" - " sysenable: Enable OPD subsystem (Power On)\r\n" - " sysdisable: Disable OPD subsystem (Power Off)\r\n" - " sysrestart: Cycle power on OPD subsystem\r\n" - " rescan: Rescans devices on OPD\r\n" - " enable: Enable an OPD attached card\r\n" - " disable: Disable an OPD attached card\r\n" - " reset: Reset the circuit breaker of a card\r\n" - " reinit: Reinitialize a device\r\n" - " probe: Probe an address to see if a card responds\r\n" - " status: Report the status of a card\r\n" - " summary: Report the status of all cards\r\n" - "\r\n" - " boot: Attempt to bootstrap a card via OPD\r\n" - " linux_normal: Set linux boot pin to normal\r\n" - " linux_recover: Set linux boot pin to recovery\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_opd.h b/src/f4/app_control/source/test/test_opd.h deleted file mode 100644 index da344798..00000000 --- a/src/f4/app_control/source/test/test_opd.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _TEST_OPD_H_ -#define _TEST_OPD_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_node(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_opd(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_persist.c b/src/f4/app_control/source/test/test_persist.c deleted file mode 100644 index 25d30ad7..00000000 --- a/src/f4/app_control/source/test/test_persist.c +++ /dev/null @@ -1,60 +0,0 @@ -#include -#include -#include "CANopen.h" -#include "OD.h" -#include "test_persist.h" -#include "persist.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* OreSat C3 Persistent Storage */ -/*===========================================================================*/ -void cmd_persist(BaseSequentialStream *chp, int argc, char *argv[]) -{ - void *group = NULL; - if (argc < 2) { - goto persist_usage; - } - if (!strcmp(argv[1], "keys")) { - group = &OD_PERSIST_KEYS; - } else if (!strcmp(argv[1], "state")) { - group = &OD_PERSIST_STATE; - } else if (!strcmp(argv[1], "comm")) { - group = &OD_PERSIST_COMM; - } else if (!strcmp(argv[1], "mfr")) { - group = &OD_PERSIST_MFR; - } else if (!strcmp(argv[1], "app")) { - group = &OD_PERSIST_APP; - } else { - goto persist_usage; - } - if (!strcmp(argv[0], "store")) { - persistStoreGroup(group); - } else if (!strcmp(argv[0], "restore")) { - persistRestoreGroup(group); - } else if (!strcmp(argv[0], "reset")) { - persistResetGroup(group); - } else { - goto persist_usage; - } - - return; - -persist_usage: - chprintf(chp, "Usage: persist \r\n" - " Commands:\r\n" - " store:\r\n" - " Store OD to FRAM\r\n" - " restore:\r\n" - " Restore OD from FRAM\r\n" - " reset:\r\n" - " Reset OD in FRAM\r\n" - " Groups:\r\n" - " keys\r\n" - " state\r\n" - " comm\r\n" - " mfr\r\n" - " app\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_persist.h b/src/f4/app_control/source/test/test_persist.h deleted file mode 100644 index 834e4251..00000000 --- a/src/f4/app_control/source/test/test_persist.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_PERSIST_H_ -#define _TEST_PERSIST_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_persist(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_radio.c b/src/f4/app_control/source/test/test_radio.c deleted file mode 100644 index 8cf2b3d6..00000000 --- a/src/f4/app_control/source/test/test_radio.c +++ /dev/null @@ -1,461 +0,0 @@ -#include -#include -#include "test_radio.h" -#include "radio.h" -#include "beacon.h" -#include "chprintf.h" - -#define PA_SAMPLES 8 - -typedef struct { - adcsample_t therm; - adcsample_t fwd; - adcsample_t rev; -} pa_samples_t; - -static pa_samples_t pa_samples[PA_SAMPLES * 2]; -static pa_samples_t pa_avg = {0}; - -static void adccallback(ADCDriver *adcp) { - uint32_t start, end; - pa_samples_t pa_sum = {0}; - if (adcIsBufferComplete(adcp)) { - start = PA_SAMPLES; - end = PA_SAMPLES * 2; - } else { - start = 0; - end = PA_SAMPLES; - } - for (uint32_t i = start; i < end; i++) { - pa_sum.therm += pa_samples[i].therm; - pa_sum.fwd += pa_samples[i].fwd; - pa_sum.rev += pa_samples[i].rev; - } - pa_avg.therm = pa_sum.therm / PA_SAMPLES; - pa_avg.fwd = pa_sum.fwd / PA_SAMPLES; - pa_avg.rev = pa_sum.rev / PA_SAMPLES; -} - -static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { - (void)adcp; - (void)err; -} - -static const ADCConversionGroup pa_pwr_cfg = { - TRUE, - sizeof(pa_samples_t) / sizeof(adcsample_t), - adccallback, - adcerrorcallback, - 0, /* CR1 */ - ADC_CR2_SWSTART, /* CR2 */ - ADC_SMPR1_SMP_AN15(ADC_SAMPLE_480) | ADC_SMPR1_SMP_AN14(ADC_SAMPLE_480),/* SMPR1 */ - ADC_SMPR2_SMP_AN4(ADC_SAMPLE_480), /* SMPR2 */ - 0, /* HTR */ - 0, /* LTR */ - 0, /* SQR1 */ - 0, /* SQR2 */ - ADC_SQR3_SQ3_N(ADC_CHANNEL_IN15) | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN14) | /* SQR3 */ - ADC_SQR3_SQ1_N(ADC_CHANNEL_IN4) -}; - -extern const radio_cfg_t *tx_eng; -extern const radio_cfg_t *tx_ax25; - -/*===========================================================================*/ -/* OreSat Radio Control */ -/*===========================================================================*/ -void cmd_radio(BaseSequentialStream *chp, int argc, char *argv[]) -{ - static AX5043Driver *devp = NULL; - static const AX5043Config *cfgp = NULL; - if (argc < 1) { - goto radio_usage; - } - - if (!strcmp(argv[0], "list")) { - for (uint32_t i = 0; radio_devices[i].devp != NULL; i++) { - chprintf(chp, "%u:\t%s\r\n", i, radio_devices[i].name); - } - chprintf(chp, "\r\n"); - return; - } else if (!strcmp(argv[0], "dev") && argc > 1) { - uint32_t i, index; - /* Find max index */ - for (i = 0; radio_devices[i].devp != NULL; i++); - index = strtoul(argv[1], NULL, 0); - if (index >= i) { - chprintf(chp, "ERROR: Invalid device\r\n"); - goto radio_usage; - } - devp = radio_devices[index].devp; - cfgp = radio_devices[index].cfgp; - return; - } - - if (devp == NULL) { - chprintf(chp, "Error: Set the device via 'dev' first.\r\n"); - goto radio_usage; - } - - if (!strcmp(argv[0], "start")) { - chprintf(chp, "Starting AX5043 driver..."); - ax5043Start(devp, cfgp); - if (devp->state < AX5043_READY) { - chprintf(chp, "Error: Failed to start driver. Error code %d.\r\n", devp->error); - } else { - chprintf(chp, "OK\r\n"); - } - } else if (!strcmp(argv[0], "stop")) { - chprintf(chp, "Stopping AX5043 driver..."); - ax5043Stop(devp); - chprintf(chp, "OK\r\n"); - } else if (!strcmp(argv[0], "idle")) { - ax5043Idle(devp); - } else if (!strcmp(argv[0], "rx")) { - ax5043RX(devp, false, false); - } else if (!strcmp(argv[0], "dump")) { - chprintf(chp, "\r\n"); - for (int i = 0; i < 0x1000; i++) { - if (i % 0x20 == 0) chprintf(chp, "\r\n%03X:", i); - chprintf(chp, " %02X", ax5043ReadU8(devp, i)); - } - chprintf(chp, "\r\n"); - } else if (!strcmp(argv[0], "setfreq") && argc > 1) { - uint32_t freq = strtoul(argv[1], NULL, 0); - uint8_t vcor = (argc > 2 ? strtoul(argv[2], NULL, 0) : 0); - bool chan_b = (argc > 3 && !strcmp(argv[3], "true") ? true : false); - - if (devp->state < AX5043_READY) { - chprintf(chp, "Error: Please start the AX5043 driver first\r\n"); - goto radio_usage; - } - - chprintf(chp, "Setting Channel %s frequency to %u...", (chan_b ? "B" : "A"), freq); - ax5043SetFreq(devp, freq, vcor, chan_b); - if (devp->error != AX5043_ERR_NOERROR) { - chprintf(chp, "Error: Failed to set frequency. Error code %d.\r\n", devp->error); - } else { - chprintf(chp, "OK\r\n"); - } - } else if (!strcmp(argv[0], "getfreq")) { - chprintf(chp, "Current frequency is %u\r\n", ax5043GetFreq(devp)); - } else if (!strcmp(argv[0], "profile")) { - if (argc > 1) { - uint32_t i, index; - /* Find max index */ - for (i = 0; radio_cfgs[i].profile != NULL; i++); - index = strtoul(argv[1], NULL, 0); - if (index >= i) { - chprintf(chp, "ERROR: Invalid profile\r\n"); - goto radio_usage; - } - ax5043SetProfile(devp, radio_cfgs[index].profile); - return; - } else { - const ax5043_profile_t *profile; - profile = ax5043GetProfile(devp); - for (uint32_t i = 0; radio_cfgs[i].profile != NULL; i++) { - if (radio_cfgs[i].profile == profile) { - chprintf(chp, "Current profile is %s\r\n", radio_cfgs[i].name); - } - } - chprintf(chp, "Available profiles:\r\n"); - for (uint32_t i = 0; radio_cfgs[i].profile != NULL; i++) { - chprintf(chp, "%u:\t%s\r\n", i, radio_cfgs[i].name); - } - chprintf(chp, "\r\n"); - return; - } - } else if (!strcmp(argv[0], "rssi")) { - chprintf(chp, "AGCCOUNTER: %u\r\nRSSI: %d\r\nBGNDRSSI: %d\r\n", ax5043ReadU8(devp, AX5043_REG_AGCCOUNTER), (int8_t)ax5043ReadU8(devp, AX5043_REG_RSSI), (int8_t)ax5043ReadU8(devp, AX5043_REG_BGNDRSSI)); - } else if (!strcmp(argv[0], "read") && argc > 2) { - uint16_t reg = strtoul(argv[1], NULL, 0); - - if (devp->state < AX5043_READY) { - chprintf(chp, "Error: Please start the AX5043 driver first\r\n"); - goto radio_usage; - } - - if (!strcmp(argv[2], "u8")) { - chprintf(chp, "0x%02X\r\n", ax5043ReadU8(devp, reg)); - } else if (!strcmp(argv[2], "u16")) { - chprintf(chp, "0x%04X\r\n", ax5043ReadU16(devp, reg)); - } else if (!strcmp(argv[2], "u24")) { - chprintf(chp, "0x%06X\r\n", ax5043ReadU24(devp, reg)); - } else if (!strcmp(argv[2], "u32")) { - chprintf(chp, "0x%08X\r\n", ax5043ReadU32(devp, reg)); - } else { - goto radio_usage; - } - } else if (!strcmp(argv[0], "write") && argc > 3) { - uint16_t reg = strtoul(argv[1], NULL, 0); - - if (!strcmp(argv[3], "u8")) { - uint8_t value = strtoul(argv[2], NULL, 0); - ax5043WriteU8(devp, reg, value); - } else if (!strcmp(argv[3], "u16")) { - uint16_t value = strtoul(argv[2], NULL, 0); - ax5043WriteU16(devp, reg, value); - } else if (!strcmp(argv[3], "u24")) { - uint32_t value = strtoul(argv[2], NULL, 0); - ax5043WriteU24(devp, reg, value); - } else if (!strcmp(argv[3], "u32")) { - uint32_t value = strtoul(argv[2], NULL, 0); - ax5043WriteU32(devp, reg, value); - } else { - goto radio_usage; - } - } else { - goto radio_usage; - } - - return; - -radio_usage: - chprintf(chp, "\r\n" - "Usage: radio \r\n" - " list: List available devices\r\n" - " dev : Set the device to as shown by 'list'\r\n" - "\r\n" - " start: Start AX5043 device\r\n" - " stop: Stop AX5043 device\r\n" - " setfreq [vcor] [chan_b]:\r\n" - " Sets frequency of channel A/B to \r\n" - " Optionally provide VCOR. [chan_b] specifies channel B\r\n" - " getfreq: Get the current frequency in use\r\n" - " profile [num]:\r\n" - " Print current profile and list available profiles,\r\n" - " or set the profile to [num] if provided\r\n" - "\r\n" - " rssi: Get the current RSSI value\r\n" - "\r\n" - " read :\r\n" - " Read where is u8|u16|u24|u32\r\n" - "\r\n" - " write :\r\n" - " Write with where is u8|u16|u24|u32\r\n" - " dump: Dump all register values\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* OreSat Synthesizer Control */ -/*===========================================================================*/ -void cmd_synth(BaseSequentialStream *chp, int argc, char *argv[]) -{ - static SI41XXDriver *devp = NULL; - static SI41XXConfig *cfgp = NULL; - if (argc < 1) { - goto synth_usage; - } - - if (!strcmp(argv[0], "list")) { - for (uint32_t i = 0; synth_devices[i].devp != NULL; i++) { - chprintf(chp, "%u:\t%s\r\n", i, synth_devices[i].name); - } - chprintf(chp, "\r\n"); - return; - } else if (!strcmp(argv[0], "dev") && argc > 1) { - uint32_t i, index; - /* Find max index */ - for (i = 0; synth_devices[i].devp != NULL; i++); - index = strtoul(argv[1], NULL, 0); - if (index >= i) { - chprintf(chp, "ERROR: Invalid device\r\n"); - goto synth_usage; - } - devp = synth_devices[index].devp; - cfgp = synth_devices[index].cfgp; - return; - } - - if (devp == NULL) { - chprintf(chp, "Error: Set the device via 'dev' first.\r\n"); - goto synth_usage; - } - - if (!strcmp(argv[0], "start")) { - si41xxStart(devp, cfgp); - } else if (!strcmp(argv[0], "stop")) { - si41xxStop(devp); - } else if (!strcmp(argv[0], "reg") && argc > 2) { - uint32_t reg = strtoul(argv[1], NULL, 0); - uint32_t value = strtoul(argv[2], NULL, 0); - si41xxWriteRaw(devp, reg, value); - } else if (!strcmp(argv[0], "freq") && argc > 1) { - uint32_t freq = strtoul(argv[1], NULL, 0); - if (!si41xxSetIF(devp, freq)) { - chprintf(chp, "Failed to set frequency\r\n"); - goto synth_usage; - } - chprintf(chp, "N=%u R=%u\r\n", cfgp->if_n, cfgp->if_r); - } else if (!strcmp(argv[0], "ifdiv") && argc > 1) { - uint32_t div = strtoul(argv[1], NULL, 0); - if (!si41xxSetIFDiv(devp, div)) { - chprintf(chp, "Failed to set IF divider value\r\n"); - goto synth_usage; - } - chprintf(chp, "IFDIV=%u\r\n", cfgp->if_div); - } else if (!strcmp(argv[0], "status")) { - chprintf(chp, "PLL: %s\r\n", (palReadLine(LINE_LO_PLL) ? "NOT LOCKED" : "LOCKED")); - } else { - goto synth_usage; - } - - return; -synth_usage: - chprintf(chp, "\r\n" - "Usage: synth \r\n" - " list: List available devices\r\n" - " dev : Set the device to as shown by 'list'\r\n" - "\r\n" - " start: Start the device\r\n" - " stop: Stop the device\r\n" - " reg :\r\n" - " Write with \r\n" - "\r\n" - " freq : Sets frequency of IF output to \r\n" - " ifdiv

: Sets IF output divider to
(1,2,4,8)\r\n" - " status: Print PLL lock status\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* OreSat RF Path Control */ -/*===========================================================================*/ -void cmd_rf(BaseSequentialStream *chp, int argc, char *argv[]) -{ - if (argc < 1) { - goto rf_usage; - } - - if (!strcmp(argv[0], "pa") && argc > 1) { - if (!strcmp(argv[1], "enable")) { - palSetLine(LINE_PA_ENABLE); - } else if (!strcmp(argv[1], "disable")) { - palClearLine(LINE_PA_ENABLE); - } - } else if (!strcmp(argv[0], "lna") && argc > 1) { - if (!strcmp(argv[1], "enable")) { - palClearLine(LINE_LNA_ENABLE); - } else if (!strcmp(argv[1], "disable")) { - palSetLine(LINE_LNA_ENABLE); - } - } else if (!strcmp(argv[0], "totclear")) { - palSetLine(LINE_TOT_RESET); - chThdSleepMicroseconds(10); - palClearLine(LINE_TOT_RESET); - } else if (!strcmp(argv[0], "start")) { - adcStartConversion(&ADCD1, &pa_pwr_cfg, (adcsample_t*)pa_samples, PA_SAMPLES * 2); - } else if (!strcmp(argv[0], "stop")) { - adcStopConversion(&ADCD1); - } else if (!strcmp(argv[0], "status")) { - chprintf(chp, "PA State: %s\r\nLNA State: %s\r\nTOT State: %s\r\n" - "PA THERM AVG: %u\r\nPA FWD AVG: %u\r\nPA REV AVG: %u\r\n\r\n", - (palReadLine(LINE_PA_ENABLE) ? "ENABLED" : "DISABLED"), - (palReadLine(LINE_LNA_ENABLE) ? "DISABLED" : "ENABLED"), - (palReadLine(LINE_TOT_STATE) ? "NOT TRIPPED" : "TRIPPED"), - pa_avg.therm, pa_avg.fwd, pa_avg.rev); - } else { - goto rf_usage; - } - - return; -rf_usage: - chprintf(chp, "\r\n" - "Usage: rf \r\n" - " pa :\r\n" - " Enable or Disable the PA\r\n" - " lna :\r\n" - " Enable or Disable the LNA\r\n" - " totclear\r\n" - " Clear the Time Out Timer\r\n" - " start\r\n" - " Start a continuous measure of PA PWR and THERM\r\n" - " stop\r\n" - " Stop measure of PA PWR and THERM\r\n" - " status\r\n" - " RF path status\r\n" - "\r\n"); - return; -} - -/*===========================================================================*/ -/* OreSat RF System Test */ -/*===========================================================================*/ -static const ax5043_chunk_repeatdata_t cw = { - .header = AX5043_CHUNKCMD_REPEATDATA | _VAL2FLD(AX5043_FIFOCHUNK_SIZE, 3), - .flags = AX5043_CHUNK_REPEATDATA_UNENC | AX5043_CHUNK_REPEATDATA_NOCRC, - .repeatcnt = 0xFF, - .data = 0xFF, -}; - -size_t tx_cb(void *arg) -{ - (void)arg; - return sizeof(cw); -} - -void cmd_rftest(BaseSequentialStream *chp, int argc, char *argv[]) -{ - if (argc < 1) { - goto rftest_usage; - } - - palSetLine(LINE_LNA_ENABLE); - palSetLine(LINE_PA_ENABLE); - ax5043WriteU16(tx_eng->devp, AX5043_REG_TXPWRCOEFFB, 0); - ax5043WriteU8(tx_eng->devp, AX5043_REG_PWRAMP, 1); - - if (!strcmp(argv[0], "cw") && argc > 2) { - uint16_t txpwr = strtoul(argv[1], NULL, 0); - uint32_t cnt = strtoul(argv[2], NULL, 0); - if (cnt == 0) cnt = 1; - ax5043WriteU16(tx_eng->devp, AX5043_REG_TXPWRCOEFFB, txpwr); - adcStartConversion(&ADCD1, &pa_pwr_cfg, (adcsample_t*)pa_samples, PA_SAMPLES * 2); - ax5043TXRaw(tx_eng->devp, NULL, &cw, sizeof(cw), sizeof(cw) * cnt, tx_cb, NULL, false); - adcStopConversion(&ADCD1); - } else { - ax5043WriteU8(tx_eng->devp, AX5043_REG_PWRAMP, 0); - palClearLine(LINE_PA_ENABLE); - palClearLine(LINE_LNA_ENABLE); - goto rftest_usage; - } - - ax5043WriteU8(tx_eng->devp, AX5043_REG_PWRAMP, 0); - palClearLine(LINE_PA_ENABLE); - palClearLine(LINE_LNA_ENABLE); - return; -rftest_usage: - chprintf(chp, "\r\n" - "Usage: rftest \r\n" - " cw :\r\n" - " Transmit CW with for iterations of a CW REPEATDATA buffer\r\n" - "\r\n"); - return; -} - -void cmd_beacon(BaseSequentialStream *chp, int argc, char *argv[]) -{ - int count = 1; - if (argc > 0) { - count = strtoul(argv[0], NULL, 0); - if (count < 1 || count > 10) - goto beacon_usage; - } - - for (int i = 0; i < count; i++) { - beacon_send(tx_ax25); - if (count > 1) - chThdSleepMilliseconds(1000); - } - - return; -beacon_usage: - chprintf(chp, "\r\n" - "Usage: beacon [count]\r\n" - "\r\n"); - return; -} diff --git a/src/f4/app_control/source/test/test_radio.h b/src/f4/app_control/source/test/test_radio.h deleted file mode 100644 index ef5cfb92..00000000 --- a/src/f4/app_control/source/test/test_radio.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _TEST_RADIO_H_ -#define _TEST_RADIO_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_radio(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_synth(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_rf(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_rftest(BaseSequentialStream *chp, int argc, char *argv[]); -void cmd_beacon(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/test/test_time.c b/src/f4/app_control/source/test/test_time.c deleted file mode 100644 index 08bb44d8..00000000 --- a/src/f4/app_control/source/test/test_time.c +++ /dev/null @@ -1,68 +0,0 @@ -#include -#include -#include "test_time.h" -#include "rtc.h" -#include "chprintf.h" - -/*===========================================================================*/ -/* Time */ -/*===========================================================================*/ -void cmd_time(BaseSequentialStream *chp, int argc, char *argv[]) -{ - RTCDateTime timespec; - uint32_t msec; - time_scet_t scet; - time_utc_t utc; - if (argc < 1) { - goto time_usage; - } - if (!strcmp(argv[0], "unix")) { - if (!strcmp(argv[1], "get")) { - time_t unix_time = rtcGetTimeUnix(&msec); - char *timestr = ctime(&unix_time); - chprintf(chp, "UNIX Time: %d\r\n" - "Date: %s\r\n", - unix_time, timestr); - } else if (!strcmp(argv[1], "set") && argc > 2) { - rtcSetTimeUnix(strtoul(argv[2], NULL, 0), 0); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "scet")) { - if (!strcmp(argv[1], "get")) { - rtcGetTimeSCET(&scet); - chprintf(chp, "SCET Time: %u.%u\r\n", scet.coarse, scet.fine); - } else if (!strcmp(argv[1], "set") && argc > 3) { - scet.coarse = strtoul(argv[2], NULL, 0); - scet.fine = strtoul(argv[3], NULL, 0); - rtcSetTimeSCET(&scet); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "utc")) { - if (!strcmp(argv[1], "get")) { - rtcGetTimeUTC(&utc); - chprintf(chp, "UTC Time: Day: %u ms: %u us: %u\r\n", utc.day, utc.ms, utc.us); - } else if (!strcmp(argv[1], "set") && argc > 4) { - utc.day = strtoul(argv[2], NULL, 0); - utc.ms = strtoul(argv[3], NULL, 0); - utc.us = strtoul(argv[4], NULL, 0); - rtcSetTimeUTC(&utc); - } else { - goto time_usage; - } - } else if (!strcmp(argv[0], "raw")) { - rtcGetTime(&RTCD1, ×pec); - chprintf(chp, "Year: %u Month: %u DST: %u DoW: %u Day: %u ms: %u\r\n", - timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond); - } else { - goto time_usage; - } - - return; - -time_usage: - chprintf(chp, "Usage: time unix|scet|utc|raw get|set \r\n"); - return; -} - diff --git a/src/f4/app_control/source/test/test_time.h b/src/f4/app_control/source/test/test_time.h deleted file mode 100644 index 277e16ce..00000000 --- a/src/f4/app_control/source/test/test_time.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _TEST_TIME_H_ -#define _TEST_TIME_H_ - -#include "ch.h" -#include "hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void cmd_time(BaseSequentialStream *chp, int argc, char *argv[]); - -#ifdef __cplusplus -} -#endif /*__cplusplus*/ -#endif diff --git a/src/f4/app_control/source/wdt.c b/src/f4/app_control/source/wdt.c deleted file mode 100644 index 2aa2c6b7..00000000 --- a/src/f4/app_control/source/wdt.c +++ /dev/null @@ -1,21 +0,0 @@ -#include "wdt.h" - -/* Watchdog Timer Thread */ -THD_WORKING_AREA(wdt_wa, 0x40); -THD_FUNCTION(wdt, arg) -{ - (void)arg; - - while (!chThdShouldTerminateX()) { - palToggleLine(LINE_WDT); - if (!palReadLine(LINE_TOT_STATE)) { - palSetLine(LINE_TOT_RESET); - chThdSleepMilliseconds(10); - palClearLine(LINE_TOT_RESET); - } - chThdSleepMilliseconds(250); - } - - palClearLine(LINE_WDT); - chThdExit(MSG_OK); -} diff --git a/src/f4/app_control/source/wdt.h b/src/f4/app_control/source/wdt.h deleted file mode 100644 index 20c7c211..00000000 --- a/src/f4/app_control/source/wdt.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _WDT_H_ -#define _WDT_H_ - -#include "ch.h" -#include "hal.h" - -/* Watchdog Timer Thread Prototypes */ -extern THD_WORKING_AREA(wdt_wa, 0x40); -extern THD_FUNCTION(wdt, arg); - -#endif diff --git a/src/f4/app_control/stm32f42x_43x_efl.patch b/src/f4/app_control/stm32f42x_43x_efl.patch deleted file mode 100644 index 6e3243df..00000000 --- a/src/f4/app_control/stm32f42x_43x_efl.patch +++ /dev/null @@ -1,263 +0,0 @@ -diff --git os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c -index bfaf5dff0..b8a6bdf9d 100644 ---- os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c -+++ os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c -@@ -48,6 +48,10 @@ - #define FLASH_SR_OPERR FLASH_SR_SOP - #endif - -+#if !defined(STM32_FLASH_DUAL_BANK_PERMANENT) -+#define STM32_FLASH_DUAL_BANK_PERMANENT FALSE -+#endif -+ - /*===========================================================================*/ - /* Driver exported variables. */ - /*===========================================================================*/ -@@ -137,6 +141,134 @@ static const efl_lld_size_t efl_lld_flash_sizes[] = { - .desc = efl_lld_size2 - } - }; -+#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ -+ defined(__DOXYGEN__) -+ -+/* Sector table for 1M device in SBM. */ -+static const flash_sector_descriptor_t efl_lld_sect_1m_sbm[STM32_FLASH_SECTORS_TOTAL_1M_SBM] = { -+ { 0, 16384}, /* Sector 0. */ -+ { 1 * 16384, 16384}, /* Sector 1. */ -+ { 2 * 16384, 16384}, /* Sector 2. */ -+ { 3 * 16384, 16384}, /* Sector 3. */ -+ { 4 * 16384, 65536}, /* Sector 4. */ -+ { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ -+ { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ -+ { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ -+ { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ -+ { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ -+ { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072} /* Sector 11. */ -+}; -+ -+/* Sector table for 1M device in DBM. */ -+static const flash_sector_descriptor_t efl_lld_sect_1m_dbm[STM32_FLASH_SECTORS_TOTAL_1M_DBM] = { -+ { 0, 16384}, /* Sector 0. */ -+ { 1 * 16384, 16384}, /* Sector 1. */ -+ { 2 * 16384, 16384}, /* Sector 2. */ -+ { 3 * 16384, 16384}, /* Sector 3. */ -+ { 4 * 16384, 65536}, /* Sector 4. */ -+ { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ -+ { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ -+ { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 0}, /* Invalid. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 12. */ -+ { 5 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 13. */ -+ { 6 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 14. */ -+ { 7 * 16384 + 1 * 65536 + 3 * 131072, 16384}, /* Sector 15. */ -+ { 8 * 16384 + 1 * 65536 + 3 * 131072, 65536}, /* Sector 16. */ -+ { 8 * 16384 + 2 * 65536 + 3 * 131072, 131072}, /* Sector 17. */ -+ { 8 * 16384 + 2 * 65536 + 4 * 131072, 131072}, /* Sector 18. */ -+ { 8 * 16384 + 2 * 65536 + 5 * 131072, 131072} /* Sector 19. */ -+}; -+ -+/* Sector table for 2M device banks. */ -+static const flash_sector_descriptor_t efl_lld_sect_2m[STM32_FLASH_SECTORS_TOTAL_2M] = { -+ { 0, 16384}, /* Sector 0. */ -+ { 1 * 16384, 16384}, /* Sector 1. */ -+ { 2 * 16384, 16384}, /* Sector 2. */ -+ { 3 * 16384, 16384}, /* Sector 3. */ -+ { 4 * 16384, 65536}, /* Sector 4. */ -+ { 4 * 16384 + 1 * 65536, 131072}, /* Sector 5. */ -+ { 4 * 16384 + 1 * 65536 + 1 * 131072, 131072}, /* Sector 6. */ -+ { 4 * 16384 + 1 * 65536 + 2 * 131072, 131072}, /* Sector 7. */ -+ { 4 * 16384 + 1 * 65536 + 3 * 131072, 131072}, /* Sector 8. */ -+ { 4 * 16384 + 1 * 65536 + 4 * 131072, 131072}, /* Sector 9. */ -+ { 4 * 16384 + 1 * 65536 + 5 * 131072, 131072}, /* Sector 10. */ -+ { 4 * 16384 + 1 * 65536 + 6 * 131072, 131072}, /* Sector 11. */ -+ { 4 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 12. */ -+ { 5 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 13. */ -+ { 6 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 14. */ -+ { 7 * 16384 + 1 * 65536 + 7 * 131072, 16384}, /* Sector 15. */ -+ { 8 * 16384 + 1 * 65536 + 7 * 131072, 65536}, /* Sector 16. */ -+ { 8 * 16384 + 2 * 65536 + 7 * 131072, 131072}, /* Sector 17. */ -+ { 8 * 16384 + 2 * 65536 + 8 * 131072, 131072}, /* Sector 18. */ -+ { 8 * 16384 + 2 * 65536 + 9 * 131072, 131072}, /* Sector 19. */ -+ { 8 * 16384 + 2 * 65536 + 10 * 131072, 131072}, /* Sector 20. */ -+ { 8 * 16384 + 2 * 65536 + 11 * 131072, 131072}, /* Sector 21. */ -+ { 8 * 16384 + 2 * 65536 + 12 * 131072, 131072}, /* Sector 22. */ -+ { 8 * 16384 + 2 * 65536 + 13 * 131072, 131072} /* Sector 23. */ -+}; -+ -+/* The descriptors for 1M device. */ -+static const flash_descriptor_t efl_lld_size_1m[STM32_FLASH_NUMBER_OF_BANKS] = { -+ { /* Bank 1 (SBM) organisation. */ -+ .attributes = FLASH_ATTR_ERASED_IS_ONE | -+ FLASH_ATTR_MEMORY_MAPPED, -+ .page_size = STM32_FLASH_LINE_SIZE, -+ .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_SBM, -+ .sectors = efl_lld_sect_1m_sbm, -+ .sectors_size = 0, -+ .address = (uint8_t *)FLASH_BASE, -+ .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE -+ }, -+ { /* Bank 1 & 2 (DBM) organisation. */ -+ .attributes = FLASH_ATTR_ERASED_IS_ONE | -+ FLASH_ATTR_MEMORY_MAPPED, -+ .page_size = STM32_FLASH_LINE_SIZE, -+ .sectors_count = STM32_FLASH_SECTORS_TOTAL_1M_DBM, -+ .sectors = efl_lld_sect_1m_dbm, -+ .sectors_size = 0, -+ .address = (uint8_t *)FLASH_BASE, -+ .size = STM32_FLASH_SIZE_1M * STM32_FLASH_SIZE_SCALE -+ } -+}; -+ -+/* The descriptors for 2M device. */ -+static const flash_descriptor_t efl_lld_size_2m[STM32_FLASH_NUMBER_OF_BANKS] = { -+ { /* Dual bank organisation. */ -+ .attributes = FLASH_ATTR_ERASED_IS_ONE | -+ FLASH_ATTR_MEMORY_MAPPED, -+ .page_size = STM32_FLASH_LINE_SIZE, -+ .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, -+ .sectors = efl_lld_sect_2m, -+ .sectors_size = 0, -+ .address = (uint8_t *)FLASH_BASE, -+ .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE -+ }, -+ { /* Dual bank organisation. */ -+ .attributes = FLASH_ATTR_ERASED_IS_ONE | -+ FLASH_ATTR_MEMORY_MAPPED, -+ .page_size = STM32_FLASH_LINE_SIZE, -+ .sectors_count = STM32_FLASH_SECTORS_TOTAL_2M, -+ .sectors = efl_lld_sect_2m, -+ .sectors_size = 0, -+ .address = (uint8_t *)FLASH_BASE, -+ .size = STM32_FLASH_SIZE_2M * STM32_FLASH_SIZE_SCALE -+ } -+}; -+ -+/* Table describing possible flash sizes and descriptors for this device. */ -+static const efl_lld_size_t efl_lld_flash_sizes[] = { -+ { -+ .desc = efl_lld_size_1m -+ }, -+ { -+ .desc = efl_lld_size_2m -+ } -+}; - #else - #error "This EFL driver does not support the selected device" - #endif -@@ -190,7 +322,7 @@ static inline size_t stm32_flash_get_size(void) { - static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { - - #if STM32_FLASH_NUMBER_OF_BANKS > 1 -- return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U); -+ return ((eflp->flash->OPTCR & FLASH_OPTCR_DB1M) != 0U || STM32_FLASH_DUAL_BANK_PERMANENT); - #endif - (void)eflp; - return false; -@@ -460,9 +592,10 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - - /** - * @brief Starts a whole-device erase operation. -- * @note This function only erases bank 2 if it is present. Bank 1 is not -- * allowed since it is normally where the primary program is located. -- * Sectors on bank 1 can be individually erased. -+ * @note This function only erases the unused bank if in dual bank mode. The -+ * currently in use bank is not allowed since it is normally where the -+ * currently running program is executing from. -+ * Sectors on the in-use bank can be individually erased. - * - * @param[in] ip pointer to a @p EFlashDriver instance - * @return An error code. -@@ -484,7 +617,7 @@ flash_error_t efl_lld_start_erase_all(void *instance) { - return FLASH_BUSY_ERASING; - } - --#if defined(FLASH_CR_MER1) -+#if defined(FLASH_CR_MER2) - /* If dual bank is active then mass erase bank2. */ - if (stm32_flash_dual_bank(devp)) { - -@@ -494,7 +627,15 @@ flash_error_t efl_lld_start_erase_all(void *instance) { - /* Clearing error status bits.*/ - stm32_flash_clear_status(devp); - -- devp->flash->CR |= FLASH_CR_MER1; -+ /* Erase the currently unused bank, based on Flash Bank Mode */ -+ if ((SYSCFG->MEMRMP & SYSCFG_MEMRMP_UFB_MODE) != 0U) { -+ /* Bank 2 in use, erase Bank 1 */ -+ devp->flash->CR |= FLASH_CR_MER; -+ } -+ else { -+ /* Bank 1 in use, erase Bank 2 */ -+ devp->flash->CR |= FLASH_CR_MER2; -+ } - devp->flash->CR |= FLASH_CR_STRT; - return FLASH_NO_ERROR; - } -@@ -545,6 +686,17 @@ flash_error_t efl_lld_start_erase_sector(void *instance, - devp->flash->CR &= ~FLASH_CR_SNB; - devp->flash->CR &= ~FLASH_CR_PSIZE; - -+#if defined(FLASH_CR_MER2) -+ /* Adjust sector value for dual-bank devices -+ * For STM32F42x_43x devices (dual-bank), FLASH_CR_SNB values jump to 0b10000 -+ * for sectors 12 and up. -+ */ -+ if (sector >= 12) { -+ sector -= 12; -+ sector |= 0x10U; -+ } -+#endif -+ - /* Set sector and parallelism. */ - devp->flash->CR |= (sector << FLASH_CR_SNB_Pos) | - (STM32_FLASH_PSIZE << FLASH_CR_PSIZE_Pos); -@@ -582,8 +734,8 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { - - /* Disabling the various erase control bits.*/ - devp->flash->CR &= ~(FLASH_CR_MER | --#if defined(FLASH_CR_MER1) -- FLASH_CR_MER1 | -+#if defined(FLASH_CR_MER2) -+ FLASH_CR_MER2 | - #endif - FLASH_CR_SER); - -diff --git os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h -index 21614b461..40ee5e346 100644 ---- os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h -+++ os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h -@@ -67,6 +67,30 @@ - #define STM32_FLASH2_SIZE 1024U - #define STM32_FLASH1_SECTORS_TOTAL 16 - #define STM32_FLASH2_SECTORS_TOTAL 12 -+ -+#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ -+ defined(__DOXYGEN__) -+ -+/* Flash size register. */ -+#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22 -+#define STM32_FLASH_SIZE_SCALE 1024U -+ -+/* -+ * Device flash size is: -+ * 1M for STM32F4x7/4x9 suffix G devices -+ * 2M for STM32F4x7/4x9 suffix I devices. -+ * -+ * For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors. -+ * For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank. -+ * -+ * For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank. -+ */ -+#define STM32_FLASH_NUMBER_OF_BANKS 2 -+#define STM32_FLASH_SIZE_1M 1024U -+#define STM32_FLASH_SIZE_2M 2048U -+#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12 -+#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20 -+#define STM32_FLASH_SECTORS_TOTAL_2M 24 - #else - #error "This EFL driver does not support the selected device" - #endif diff --git a/src/f4/app_control/stm32f439_hmacsha256.patch b/src/f4/app_control/stm32f439_hmacsha256.patch deleted file mode 100644 index 467afc39..00000000 --- a/src/f4/app_control/stm32f439_hmacsha256.patch +++ /dev/null @@ -1,332 +0,0 @@ -diff --git a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c -index 1d83e199b..322d172c1 100644 ---- a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c -+++ b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c -@@ -361,6 +361,8 @@ void cry_lld_init(void) { - #endif - - #if STM32_CRY_USE_HASH1 -+ CRYD1.hmac_keyp = NULL; -+ CRYD1.hmac_keylen = 0; - #if STM32_CRY_HASH_SIZE_THRESHOLD != 0 - CRYD1.hash_tr = NULL; - CRYD1.hash_dma = NULL; -@@ -451,6 +453,7 @@ void cry_lld_start(CRYDriver *cryp) { - #endif - } - -+#if STM32_CRY_USE_CRYP1 - /* Resetting trasient key data.*/ - cryp->cryp_ktype = cryp_key_none; - cryp->cryp_ksize = 0U; -@@ -463,7 +466,6 @@ void cry_lld_start(CRYDriver *cryp) { - cryp->cryp_k[6] = 0U; - cryp->cryp_k[7] = 0U; - --#if STM32_CRY_USE_CRYP1 - /* CRYP setup.*/ - CRYP->CR = CRYP_CR_DATATYPE_1; - CRYP->DMACR = CRYP_DMACR_DIEN | CRYP_DMACR_DOEN; -@@ -1711,7 +1713,8 @@ cryerror_t cry_lld_SHA512_final(CRYDriver *cryp, SHA512Context *sha512ctxp, - /** - * @brief Initializes the HMAC transient key. - * @note It is the underlying implementation to decide which key sizes are -- * allowable. -+ * allowable. The key must not be moved, freed, or fall out of scope -+ * until the relevent HMAC*_final() function has been called. - * - * @param[in] cryp pointer to the @p CRYDriver object - * @param[in] size key size in bytes -@@ -1727,14 +1730,66 @@ cryerror_t cry_lld_SHA512_final(CRYDriver *cryp, SHA512Context *sha512ctxp, - cryerror_t cry_lld_hmac_loadkey(CRYDriver *cryp, - size_t size, - const uint8_t *keyp) { -- -- (void)cryp; -- (void)size; -- (void)keyp; -+ /* The HASH peripheral doesn't really match up to this API so this gets a -+ * little awkward. The described use is loadkey() -> init() -> update() -> -+ * final() but the key can only be loaded after the configuration in init(). -+ * At the same time init() needs to know the length of the key and so -+ * init() -> loadkey() does not work. Finally, the key needs to be loaded -+ * again, after update() and before final(), but final() feeds the last word -+ * of data into HASH so update() -> loadkey() -> final() is out as well. -+ * -+ * This is the least worst option that I could come up with, doing an -+ * allocation and copying the secret around seemed less desirable. The -+ * downside being users must ensure that the key has not been moved, freed, -+ * or fallen out of scope until final() is called. -+ */ -+ cryp->hmac_keyp = keyp; -+ cryp->hmac_keylen = size; - - return CRY_NOERROR; - } - -+/** -+ * @brief Actually loads a key into the HASH peripheral. -+ * @note The hardware will pad to extend or hash to shorten to -+ * ensure the actual key is the right size -+ * -+ * @param[in] cryp pointer to the @p CRYDriver object -+ * @param[in] size key size in bytes -+ * @param[in] keyp pointer to the key data -+ * -+ * @notapi -+ */ -+ -+static void hmac_loadkey(CRYDriver *cryp, size_t size, const uint8_t *keyp) { -+ /* The API accepts bytes but HASH only takes words so special handling is -+ * needed for the end word */ -+ uint32_t words = size / sizeof(uint32_t); -+ uint32_t bytes = size % sizeof(uint32_t); -+ uint32_t end = 0; -+ switch (bytes) { -+ case 3: -+ end = keyp[size-1] << 16 | keyp[size-2] << 8 | keyp[size-3]; -+ break; -+ case 2: -+ end = keyp[size-1] << 8 | keyp[size-2]; -+ break; -+ case 1: -+ end = keyp[size-1]; -+ break; -+ default: -+ break; -+ } -+ cry_lld_hash_push(cryp, words, (const uint32_t *)keyp); -+ if (bytes) { -+ HASH->DIN = end; -+ } -+ /* It is not possible to configure NBLW and set DCAL at the same time. -+ * Additinally NBLW is not reset by HASH_CR_INIT and so must always be set */ -+ HASH->STR = (8 * bytes) & HASH_STR_NBLW; -+ HASH->STR = HASH_STR_DCAL; -+} -+ - /** - * @brief Hash initialization using HMAC_SHA256. - * -@@ -1752,11 +1807,25 @@ cryerror_t cry_lld_hmac_loadkey(CRYDriver *cryp, - */ - cryerror_t cry_lld_HMACSHA256_init(CRYDriver *cryp, - HMACSHA256Context *hmacsha256ctxp) { -+ hmacsha256ctxp->last_data = 0; -+ hmacsha256ctxp->last_size = 0; - -- (void)cryp; -- (void)hmacsha256ctxp; -+ if (!cryp->hmac_keyp || !cryp->hmac_keylen) { -+ return CRY_ERR_OP_FAILURE; -+ } - -- return CRY_ERR_INV_ALGO; -+ //FIXME: DMA -+ /* SHA256 | HMAC | LE Byte data */ -+ uint32_t cr = HASH_CR_ALGO_1 | HASH_CR_ALGO_0 | HASH_CR_MODE | HASH_CR_DATATYPE_1; -+ if (cryp->hmac_keylen > 64) { -+ /* Can only be set when the INIT bit is also set */ -+ cr |= HASH_CR_LKEY; -+ } -+ HASH->CR = cr | HASH_CR_INIT; -+ -+ /* Load the "inner" key */ -+ hmac_loadkey(cryp, cryp->hmac_keylen, cryp->hmac_keyp); -+ return CRY_NOERROR; - } - - /** -@@ -1779,13 +1848,31 @@ cryerror_t cry_lld_HMACSHA256_update(CRYDriver *cryp, - HMACSHA256Context *hmacsha256ctxp, - size_t size, - const uint8_t *in) { -+ /* This HW is unable to hash blocks that are not a multiple of 4 bytes -+ except for the last block in the stream which is handled in the -+ "final" function. */ -+ if (hmacsha256ctxp->last_size) { -+ return CRY_ERR_OP_FAILURE; -+ } - -- (void)cryp; -- (void)hmacsha256ctxp; -- (void)size; -- (void)in; -+ /* Any unaligned data is deferred to the "final" function. */ -+ hmacsha256ctxp->last_size = size % sizeof(uint32_t); -+ switch (hmacsha256ctxp->last_size) { -+ case 3: -+ hmacsha256ctxp->last_data = in[size-1] << 16 | in[size-2] << 8 | in[size-3]; -+ break; -+ case 2: -+ hmacsha256ctxp->last_data = in[size-1] << 8 | in[size-2]; -+ break; -+ case 1: -+ hmacsha256ctxp->last_data = in[size-1]; -+ break; -+ default: -+ break; -+ } - -- return CRY_ERR_INV_ALGO; -+ cry_lld_hash_push(cryp, size / sizeof(uint32_t), (const uint32_t *)in); -+ return CRY_NOERROR; - } - - /** -@@ -1806,12 +1893,34 @@ cryerror_t cry_lld_HMACSHA256_update(CRYDriver *cryp, - cryerror_t cry_lld_HMACSHA256_final(CRYDriver *cryp, - HMACSHA256Context *hmacsha256ctxp, - uint8_t *out) { -+ if (hmacsha256ctxp->last_size) { -+ HASH->DIN = hmacsha256ctxp->last_data; -+ } -+ /* It is not possible to configure NBLW and set DCAL at the same time. -+ * Additinally NBLW is not reset by HASH_CR_INIT and so must always be set */ -+ HASH->STR = (8 * hmacsha256ctxp->last_size) & HASH_STR_NBLW; -+ HASH->STR = HASH_STR_DCAL; -+ /* Wait for calculation result */ -+ while (HASH->SR & HASH_SR_BUSY) {} - -- (void)cryp; -- (void)hmacsha256ctxp; -- (void)out; -+ /* Feed in the "outer" key (which should be the same as the inner key) */ -+ hmac_loadkey(cryp, cryp->hmac_keylen, cryp->hmac_keyp); - -- return CRY_ERR_INV_ALGO; -+ uint32_t digest[8]; -+ /* Reading digest.*/ -+ digest[0] = __REV(HASH_DIGEST->HR[0]); -+ digest[1] = __REV(HASH_DIGEST->HR[1]); -+ digest[2] = __REV(HASH_DIGEST->HR[2]); -+ digest[3] = __REV(HASH_DIGEST->HR[3]); -+ digest[4] = __REV(HASH_DIGEST->HR[4]); -+ digest[5] = __REV(HASH_DIGEST->HR[5]); -+ digest[6] = __REV(HASH_DIGEST->HR[6]); -+ digest[7] = __REV(HASH_DIGEST->HR[7]); -+ memcpy(out, digest, sizeof(digest)); -+ -+ cryp->hmac_keyp = NULL; -+ cryp->hmac_keylen = 0; -+ return CRY_NOERROR; - } - #endif - -diff --git a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.h b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.h -index 257d39624..55f263df7 100644 ---- a/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.h -+++ b/os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.h -@@ -195,17 +195,20 @@ - #endif /* !STM32_DMA_SUPPORTS_DMAMUX */ - - /* DMA priority check.*/ --#if !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_CRYP1_IN_DMA_PRIORITY) -+#if STM32_CRY_USE_CRYP1 && \ -+ !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_CRYP1_IN_DMA_PRIORITY) - #error "Invalid DMA priority assigned to CRYP1_IN" - #endif - - /* DMA priority check.*/ --#if !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_CRYP1_OUT_DMA_PRIORITY) -+#if STM32_CRY_USE_CRYP1 && \ -+ !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_CRYP1_OUT_DMA_PRIORITY) - #error "Invalid DMA priority assigned to CRYP1_OUT" - #endif - - /* DMA priority check.*/ --#if !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_HASH1_DMA_PRIORITY) -+#if STM32_CRY_USE_HASH1 && \ -+ !STM32_DMA_IS_VALID_PRIORITY(STM32_CRY_HASH1_DMA_PRIORITY) - #error "Invalid DMA priority assigned to HASH1" - #endif - -@@ -335,6 +338,14 @@ struct CRYDriver { - #endif /* STM32_CRY_CRYP_SIZE_THRESHOLD != 0 */ - #endif /* STM32_CRY_USE_CRYP1 == TRUE */ - #if (STM32_CRY_USE_HASH1 == TRUE) || defined (__DOXYGEN__) -+ /** -+ * @brief Pointer to HMAC transient key -+ */ -+ const uint8_t *hmac_keyp; -+ /** -+ * #brief Length of the key pointed to by hmac_keyp -+ */ -+ size_t hmac_keylen; - #if (STM32_CRY_HASH_SIZE_THRESHOLD != 0) || defined (__DOXYGEN__) - /** - * @brief Thread reference for hash operations. -@@ -387,7 +398,14 @@ typedef struct { - * @brief Type of a HMAC_SHA256 context. - */ - typedef struct { -- uint32_t dummy; -+ /** -+ * @brief Last data to be hashed on finalization. -+ */ -+ uint32_t last_data; -+ /** -+ * @brief Size, in bits, of the last data. -+ */ -+ uint32_t last_size; - } HMACSHA256Context; - #endif - -diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h -index cc401ce05..ec445db3e 100644 ---- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h -+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h -@@ -1596,6 +1596,34 @@ - #define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST) - /** @} */ - -+/** -+ * @name HASH peripheral specific RCC operations -+ * @{ -+ */ -+/** -+ * @brief Enables the HASH peripheral clock. -+ * -+ * @param[in] lp low power enable flag -+ * -+ * @api -+ */ -+#define rccEnableHASH(lp) rccEnableAHB2(RCC_AHB2ENR_HASHEN, lp) -+ -+/** -+ * @brief Disables the HASH peripheral clock. -+ * -+ * @api -+ */ -+#define rccDisableHASH() rccDisableAHB2(RCC_AHB2ENR_HASHEN) -+ -+/** -+ * @brief Resets the HASH peripheral. -+ * -+ * @api -+ */ -+#define rccResetHASH() rccResetAHB2(RCC_AHB2RSTR_HASHRST) -+/** @} */ -+ - /** - * @name FSMC peripherals specific RCC operations - * @{ -diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h -index 5072ce744..267b313b4 100644 ---- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h -+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h -@@ -1219,6 +1219,14 @@ - #define STM32_HAS_CRC TRUE - #define STM32_CRC_PROGRAMMABLE FALSE - -+/* CRY attributes.*/ -+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(__DOXYGEN__) -+#define STM32_HAS_HASH1 TRUE -+#define STM32_HASH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -+#define STM32_HASH1_DMA_CHN 0x20000000 -+ -+#endif -+ - #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ - - /*===========================================================================*/ diff --git a/src/f4/app_devboard/Makefile b/src/f4/app_devboard/Makefile deleted file mode 100644 index 6fdd0d1e..00000000 --- a/src/f4/app_devboard/Makefile +++ /dev/null @@ -1,217 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_devboard - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_F446RE - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep -ODDIR := $(APP_ROOT)/od - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -ifeq ($(ORESAT),) - ORESAT = 0.5 -endif - -# generate OD.c/OD.h from oresat-configs -FW_VERSION = $(shell git describe --always) -$(shell oresat-gen-fw-files --oresat $(ORESAT) base -d $(ODDIR) -fw $(FW_VERSION) -hw $(BOARD)) -# add them -ALLCSRC += $(ODDIR)/OD.c -ALLINC += $(ODDIR) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(PROJ_ROOT)/ld/STM32F446xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/f4/app_devboard/README.md b/src/f4/app_devboard/README.md deleted file mode 100644 index 1df5134b..00000000 --- a/src/f4/app_devboard/README.md +++ /dev/null @@ -1,12 +0,0 @@ -# Application Main Directory -## Directory Structure -This folder contains the root of an applications sources. It contains -several files and folders: -* [main.c](main.c): The main program file called by ChibiOS. Contains - initialization code and registers threads and functions. -* [Makefile](Makefile): The main Makefile for the application. Sources - all other build files. -* [cfg](cfg): The directory containing ChibiOS's configuration files for - this application. -* [source](source): The directory where application code is put. - Everything within this directory automatically builds. diff --git a/src/f4/app_devboard/cfg/CO_driver_custom.h b/src/f4/app_devboard/cfg/CO_driver_custom.h deleted file mode 100644 index d1a11777..00000000 --- a/src/f4/app_devboard/cfg/CO_driver_custom.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define CO_CONFIG_SDO_CLI (CO_CONFIG_SDO_CLI_ENABLE | \ - CO_CONFIG_SDO_CLI_SEGMENTED | \ - CO_CONFIG_SDO_CLI_BLOCK | \ - CO_CONFIG_SDO_CLI_LOCAL | \ - CO_CONFIG_FLAG_CALLBACK_PRE | \ - CO_CONFIG_FLAG_TIMERNEXT | \ - CO_CONFIG_FLAG_OD_DYNAMIC) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/f4/app_devboard/cfg/chconf.h b/src/f4/app_devboard/cfg/chconf.h deleted file mode 100644 index 29b34229..00000000 --- a/src/f4/app_devboard/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE TRUE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/f4/app_devboard/cfg/halconf.h b/src/f4/app_devboard/cfg/halconf.h deleted file mode 100644 index 5d81faa8..00000000 --- a/src/f4/app_devboard/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/f4/app_devboard/cfg/mcuconf.h b/src/f4/app_devboard/cfg/mcuconf.h deleted file mode 100644 index 50d24450..00000000 --- a/src/f4/app_devboard/cfg/mcuconf.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F4xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 360 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SM_VALUE 4 -#define STM32_PLLI2SR_VALUE 4 -#define STM32_PLLI2SP_VALUE 4 -#define STM32_PLLI2SQ_VALUE 4 -#define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 4 -#define STM32_PLLSAIP_VALUE 8 -#define STM32_PLLSAIQ_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_SAI1SEL STM32_SAI2SEL_PLLR -#define STM32_SAI2SEL STM32_SAI2SEL_PLLR -#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#endif /* MCUCONF_H */ diff --git a/src/f4/app_devboard/main.c b/src/f4/app_devboard/main.c deleted file mode 100644 index a0818a85..00000000 --- a/src/f4/app_devboard/main.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" - -/* Project header files */ -#include "oresat.h" -#include "blink.h" - -static worker_t worker1; -static thread_descriptor_t worker1_desc = { - .name = "Example blinky thread", - .wbase = THD_WORKING_AREA_BASE(blink_wa), - .wend = THD_WORKING_AREA_END(blink_wa), - .prio = NORMALPRIO, - .funcp = blink, - .arg = NULL -}; - -static oresat_config_t oresat_conf = { - .cand = &CAND1, - .node_id = ORESAT_DEFAULT_ID, - .bitrate = ORESAT_DEFAULT_BITRATE, -}; - -/** - * @brief App Initialization - */ -static void app_init(void) -{ - /* App initialization */ - reg_worker(&worker1, &worker1_desc, false, true); - - /* Start up debug output */ - sdStart(&SD2, NULL); -} - -/** - * @brief Main Application - */ -int main(void) -{ - // Initialize and start - oresat_init(&oresat_conf); - app_init(); - oresat_start(); - return 0; -} diff --git a/src/f4/app_devboard/source/README.md b/src/f4/app_devboard/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/f4/app_devboard/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/f4/app_devboard/source/blink.c b/src/f4/app_devboard/source/blink.c deleted file mode 100644 index 93010401..00000000 --- a/src/f4/app_devboard/source/blink.c +++ /dev/null @@ -1,18 +0,0 @@ -#include "blink.h" - -/* Example blinker thread */ -THD_WORKING_AREA(blink_wa, 0x40); -THD_FUNCTION(blink, arg) -{ - (void)arg; - - palSetLineMode(LINE_LED,PAL_MODE_OUTPUT_PUSHPULL); - - while (!chThdShouldTerminateX()) { - palToggleLine(LINE_LED); - chThdSleepMilliseconds(500); - } - - palClearLine(LINE_LED); - chThdExit(MSG_OK); -} diff --git a/src/f4/app_devboard/source/blink.h b/src/f4/app_devboard/source/blink.h deleted file mode 100644 index c9178eb2..00000000 --- a/src/f4/app_devboard/source/blink.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _BLINK_H_ -#define _BLINK_H_ - -#include "ch.h" -#include "hal.h" - -/* Example blinker thread prototypes */ -extern THD_WORKING_AREA(blink_wa, 0x40); -extern THD_FUNCTION(blink, arg); - -#endif diff --git a/src/l4/README.md b/src/l4/README.md deleted file mode 100644 index 54cf4959..00000000 --- a/src/l4/README.md +++ /dev/null @@ -1,49 +0,0 @@ -# STM32L452RE - -This is the source directory for all STM32L452RE applications. -This device contains an ARM Cortex-M4, and is also known as an L4. - -This MCU typically implements higher power OreSat subsystems, -such as Reaction Wheels and Magnetorquers. - -## Testing the toolchain -After having installed the required toolchain components as described in -the Prerequesites section of the main README, it is good to test that -they all function as expected. This can be done by building and flashing -the `app_blinky` application that simply blinks an LED. - -In order to accomplish this, from this directory simply execute the -following: - -``` -cd app_blinky -make -make write -``` -This should result in a clean no-error build, followed by a successful -write to the board and a flashing green LED. If this all works, -congratulations! Your toolchain is working and you can begin developing. - -## Creating an app -The template to copy for new applications is [app_template](app_template). -To create a new app, simply make a copy of the app_template directory -and name it whatever you like. From this directory: - -``` -cp -R app_template app_ -``` - -Then, open the Makefile `app_/Makefile` and edit the line `PROJECT =` to whatever name -you've chosen: - -If building for a specific board, also update the `BOARD =` line to the -board defined in the `boards` directory. -``` -PROJECT = app_ -``` - -At this point, you simply write code in source files under the `sources` -directory, include the appropriate header file in the main.c file, -and finally register your worker with the main OreSat application. - -See the doc folder for further documentation. diff --git a/src/l4/app_blinky/Makefile b/src/l4/app_blinky/Makefile deleted file mode 100644 index 15872963..00000000 --- a/src/l4/app_blinky/Makefile +++ /dev/null @@ -1,202 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_blinky - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_L452RE_P - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32L452xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/l4/app_blinky/README.md b/src/l4/app_blinky/README.md deleted file mode 100644 index ae8def29..00000000 --- a/src/l4/app_blinky/README.md +++ /dev/null @@ -1,87 +0,0 @@ -# Toolchain Test Application -`app_blinky` is a simple app that blinks a dev board's LED at 1Hz with a 50% duty cycle. - -To ensure you have your toolchain correctly installed and configured, -you simply need to run the following sequence of commands: - -``` -make -make write -``` - -If you see something like the following output for each, your -toolchain works: - -``` -âžœ make -Compiler Options -arm-none-eabi-gcc -c -mcpu=cortex-m0 -mthumb -Og -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -fno-common -flto -Wall -Wextra -Wundef -Wstrict-prototypes -Wa,-alms=./build/lst/ -DCORTEX_USE_FPU=FALSE -DPORT_IGNORE_GCC_VERSION_CHECK -MD -MP -MF ./.dep/build.d -I. -I./cfg -I../../../ChibiOS/os/license -I../../../ChibiOS/os/common/portability/GCC -I../../../ChibiOS/os/common/startup/ARMCMx/compilers/GCC -I../../../ChibiOS/os/common/startup/ARMCMx/devices/STM32F0xx -I../../../ChibiOS/os/common/ext/ARM/CMSIS/Core/Include -I../../../ChibiOS/os/common/ext/ST/STM32F0xx -I../../../ChibiOS/os/hal/include -I../../../ChibiOS/os/hal/ports/common/ARMCMx -I../../../ChibiOS/os/hal/ports/STM32/STM32F0xx -I../../../ChibiOS/os/hal/ports/STM32/LLD/ADCv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/CANv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/DACv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/DMAv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/EXTIv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/GPIOv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/I2Cv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/RTCv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/SPIv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/TIMv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/USARTv2 -I../../../ChibiOS/os/hal/ports/STM32/LLD/USBv1 -I../../../ChibiOS/os/hal/ports/STM32/LLD/xWDGv1 -I../../../boards/ST_NUCLEO32_F042K6 -I../../../ChibiOS/os/hal/osal/rt-nil -I../../../ChibiOS/os/rt/include -I../../../ChibiOS/os/oslib/include -I../../../ChibiOS/os/common/ports/ARMCMx -I../../../ChibiOS/os/common/ports/ARMCMx/compilers/GCC -I../../../common/include main.c -o main.o - -Compiling crt0_v6m.S -Compiling vectors.S -Compiling chcoreasm_v6m.S -Compiling crt1.c -Compiling hal.c -Compiling hal_st.c -Compiling hal_buffers.c -Compiling hal_queues.c -Compiling hal_flash.c -Compiling hal_mmcsd.c -Compiling hal_pal.c -Compiling hal_serial.c -Compiling nvic.c -Compiling stm32_isr.c -Compiling hal_lld.c -Compiling stm32_dma.c -Compiling stm32_exti.c -Compiling hal_pal_lld.c -Compiling hal_st_lld.c -Compiling hal_serial_lld.c -Compiling board.c -Compiling osal.c -Compiling chsys.c -Compiling chdebug.c -Compiling chtrace.c -Compiling chvt.c -Compiling chschd.c -Compiling chthreads.c -Compiling chregistry.c -Compiling chsem.c -Compiling chmtx.c -Compiling chcond.c -Compiling chevents.c -Compiling chmsg.c -Compiling chdynamic.c -Compiling chmboxes.c -Compiling chmemcore.c -Compiling chmempools.c -Compiling chpipes.c -Compiling chcore.c -Compiling chcore_v6m.c -Compiling main.c -Linking build/app_blinky.elf -Creating build/app_blinky.hex -Creating build/app_blinky.bin -Creating build/app_blinky.dmp - - text data bss dec hex filename - 4952 0 6144 11096 2b58 build/app_blinky.elf -Creating build/app_blinky.list - -Done - -âžœ make write -st-flash --reset --format ihex write ./build/app_blinky.hex -st-flash 1.6.1 -2020-07-30T13:29:22 INFO common.c: F09X: 32 KiB SRAM, 256 KiB flash in at least 2 KiB pages. -2020-07-30T13:29:22 INFO common.c: Attempting to write 5192 (0x1448) bytes to stm32 address: 134217728 (0x8000000) -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08000000 erased -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08000800 erased -2020-07-30T13:29:22 INFO common.c: Flash page at addr: 0x08001000 erased -2020-07-30T13:29:22 INFO common.c: Finished erasing 3 pages of 2048 (0x800) bytes -2020-07-30T13:29:22 INFO common.c: Starting Flash write for VL/F0/F3/F1_XL core id -2020-07-30T13:29:22 INFO flash_loader.c: Successfully loaded flash loader in sram - 3/3 pages written -2020-07-30T13:29:22 INFO common.c: Starting verification of write complete -2020-07-30T13:29:22 INFO common.c: Flash written and verified! jolly good! -``` diff --git a/src/l4/app_blinky/cfg/chconf.h b/src/l4/app_blinky/cfg/chconf.h deleted file mode 100644 index 6bf327ae..00000000 --- a/src/l4/app_blinky/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE TRUE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/l4/app_blinky/cfg/halconf.h b/src/l4/app_blinky/cfg/halconf.h deleted file mode 100644 index 534c4bb6..00000000 --- a/src/l4/app_blinky/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/l4/app_blinky/cfg/mcuconf.h b/src/l4/app_blinky/cfg/mcuconf.h deleted file mode 100644 index 10eb53d4..00000000 --- a/src/l4/app_blinky/cfg/mcuconf.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#ifndef MCUCONF_H -#define MCUCONF_H - -#define STM32L4xx_MCUCONF -#define STM32L452_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_VOS STM32_VOS_RANGE1 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI16_ENABLED FALSE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED TRUE -#define STM32_MSIPLL_ENABLED TRUE -#define STM32_MSIRANGE STM32_MSIRANGE_4M -#define STM32_MSISRANGE STM32_MSISRANGE_4M -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_MSI -#define STM32_PLLM_VALUE 1 -#define STM32_PLLN_VALUE 80 -#define STM32_PLLPDIV_VALUE 0 -#define STM32_PLLP_VALUE 7 -#define STM32_PLLQ_VALUE 6 -#define STM32_PLLR_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_STOPWUCK STM32_STOPWUCK_MSI -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 72 -#define STM32_PLLSAI1PDIV_VALUE 6 -#define STM32_PLLSAI1P_VALUE 7 -#define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 6 - -/* - * Peripherals clock sources. - */ -#define STM32_USART1SEL STM32_USART1SEL_SYSCLK -#define STM32_USART2SEL STM32_USART2SEL_SYSCLK -#define STM32_USART3SEL STM32_USART3SEL_SYSCLK -#define STM32_UART4SEL STM32_UART4SEL_SYSCLK -#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK -#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK -#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK -#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK -#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 -#define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 -#define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI1635_38_PRIORITY 6 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_22_PRIORITY 15 - -#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 -#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 -#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 -#define STM32_IRQ_TIM1_CC_PRIORITY 7 -#define STM32_IRQ_TIM2_PRIORITY 7 -#define STM32_IRQ_TIM3_PRIORITY 7 -#define STM32_IRQ_TIM6_PRIORITY 7 - -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_LPUART1_PRIORITY 12 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM15 FALSE -#define STM32_GPT_USE_TIM16 FALSE - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_USE_I2C4 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C4_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C4_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_USE_TIM16 FALSE - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM15 FALSE -#define STM32_PWM_USE_TIM16 FALSE - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_USE_SDMMC1 FALSE -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 -#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 -#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 -#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_LPUART1 TRUE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_LPUART1_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * TRNG driver system settings. - */ -#define STM32_TRNG_USE_RNG1 FALSE - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * WSPI driver system settings. - */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) - -#endif /* MCUCONF_H */ diff --git a/src/l4/app_blinky/main.c b/src/l4/app_blinky/main.c deleted file mode 100644 index c5a48d2a..00000000 --- a/src/l4/app_blinky/main.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" - -int main(void) -{ - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - while (true) - { - palClearLine(LINE_LED); - chThdSleepMilliseconds(500); - palSetLine(LINE_LED); - chThdSleepMilliseconds(500); - } - - return 0; -} diff --git a/src/l4/app_devboard/Makefile b/src/l4/app_devboard/Makefile deleted file mode 100644 index 61f98e20..00000000 --- a/src/l4/app_devboard/Makefile +++ /dev/null @@ -1,217 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_devboard - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_L452RE_P - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep -ODDIR := $(APP_ROOT)/od - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -ifeq ($(ORESAT),) - ORESAT = 0.5 -endif - -# generate OD.c/OD.h from oresat-configs -FW_VERSION = $(shell git describe --always) -$(shell oresat-gen-fw-files --oresat $(ORESAT) base -d $(ODDIR) -fw $(FW_VERSION) -hw $(BOARD)) -# add them -ALLCSRC += $(ODDIR)/OD.c -ALLINC += $(ODDIR) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(PROJ_ROOT)/ld/STM32L452xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/l4/app_devboard/README.md b/src/l4/app_devboard/README.md deleted file mode 100644 index 1df5134b..00000000 --- a/src/l4/app_devboard/README.md +++ /dev/null @@ -1,12 +0,0 @@ -# Application Main Directory -## Directory Structure -This folder contains the root of an applications sources. It contains -several files and folders: -* [main.c](main.c): The main program file called by ChibiOS. Contains - initialization code and registers threads and functions. -* [Makefile](Makefile): The main Makefile for the application. Sources - all other build files. -* [cfg](cfg): The directory containing ChibiOS's configuration files for - this application. -* [source](source): The directory where application code is put. - Everything within this directory automatically builds. diff --git a/src/l4/app_devboard/cfg/CO_driver_custom.h b/src/l4/app_devboard/cfg/CO_driver_custom.h deleted file mode 100644 index 4d72b881..00000000 --- a/src/l4/app_devboard/cfg/CO_driver_custom.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/l4/app_devboard/cfg/chconf.h b/src/l4/app_devboard/cfg/chconf.h deleted file mode 100644 index 29b34229..00000000 --- a/src/l4/app_devboard/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE TRUE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/l4/app_devboard/cfg/halconf.h b/src/l4/app_devboard/cfg/halconf.h deleted file mode 100644 index 5d81faa8..00000000 --- a/src/l4/app_devboard/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/l4/app_devboard/cfg/mcuconf.h b/src/l4/app_devboard/cfg/mcuconf.h deleted file mode 100644 index 10774df3..00000000 --- a/src/l4/app_devboard/cfg/mcuconf.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#ifndef MCUCONF_H -#define MCUCONF_H - -#define STM32L4xx_MCUCONF -#define STM32L452_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_VOS STM32_VOS_RANGE1 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI16_ENABLED FALSE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED TRUE -#define STM32_MSIPLL_ENABLED TRUE -#define STM32_MSIRANGE STM32_MSIRANGE_4M -#define STM32_MSISRANGE STM32_MSISRANGE_4M -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_MSI -#define STM32_PLLM_VALUE 1 -#define STM32_PLLN_VALUE 80 -#define STM32_PLLPDIV_VALUE 0 -#define STM32_PLLP_VALUE 7 -#define STM32_PLLQ_VALUE 6 -#define STM32_PLLR_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_STOPWUCK STM32_STOPWUCK_MSI -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 72 -#define STM32_PLLSAI1PDIV_VALUE 6 -#define STM32_PLLSAI1P_VALUE 7 -#define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 6 - -/* - * Peripherals clock sources. - */ -#define STM32_USART1SEL STM32_USART1SEL_SYSCLK -#define STM32_USART2SEL STM32_USART2SEL_SYSCLK -#define STM32_USART3SEL STM32_USART3SEL_SYSCLK -#define STM32_UART4SEL STM32_UART4SEL_SYSCLK -#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK -#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK -#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK -#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK -#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 -#define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 -#define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI1635_38_PRIORITY 6 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_22_PRIORITY 15 - -#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 -#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 -#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 -#define STM32_IRQ_TIM1_CC_PRIORITY 7 -#define STM32_IRQ_TIM2_PRIORITY 7 -#define STM32_IRQ_TIM3_PRIORITY 7 -#define STM32_IRQ_TIM6_PRIORITY 7 - -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_LPUART1_PRIORITY 12 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM15 FALSE -#define STM32_GPT_USE_TIM16 FALSE - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_USE_I2C4 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C4_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C4_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_USE_TIM16 FALSE - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM15 FALSE -#define STM32_PWM_USE_TIM16 FALSE - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_USE_SDMMC1 FALSE -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 -#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 -#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 -#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_LPUART1 TRUE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_LPUART1_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * TRNG driver system settings. - */ -#define STM32_TRNG_USE_RNG1 FALSE - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * WSPI driver system settings. - */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) - -#endif /* MCUCONF_H */ diff --git a/src/l4/app_devboard/main.c b/src/l4/app_devboard/main.c deleted file mode 100644 index eca517c2..00000000 --- a/src/l4/app_devboard/main.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" - -/* Project header files */ -#include "oresat.h" -#include "blink.h" - -static worker_t worker1; -static thread_descriptor_t worker1_desc = { - .name = "Example blinky thread", - .wbase = THD_WORKING_AREA_BASE(blink_wa), - .wend = THD_WORKING_AREA_END(blink_wa), - .prio = NORMALPRIO, - .funcp = blink, - .arg = NULL -}; - -static oresat_config_t oresat_conf = { - .cand = &CAND1, - .node_id = ORESAT_DEFAULT_ID, - .bitrate = ORESAT_DEFAULT_BITRATE, -}; - -/** - * @brief App Initialization - */ -static void app_init(void) -{ - /* App initialization */ - reg_worker(&worker1, &worker1_desc, false, true); - - /* Start up debug output */ - sdStart(&LPSD1, NULL); -} - -/** - * @brief Main Application - */ -int main(void) -{ - // Initialize and start - oresat_init(&oresat_conf); - app_init(); - oresat_start(); - return 0; -} diff --git a/src/l4/app_devboard/od/app.eds b/src/l4/app_devboard/od/app.eds deleted file mode 100644 index 116bbad9..00000000 --- a/src/l4/app_devboard/od/app.eds +++ /dev/null @@ -1,4863 +0,0 @@ -[FileInfo] -FileName=app.eds -FileVersion=0 -FileRevision=1 -EDSVersion=4.0 -Description=OreSat Template Application Object Dictionary -CreationTime=02:51PM -CreationDate=08-12-2019 -CreatedBy=Miles Simpson -ModificationTime=11:45AM -ModificationDate=04-25-2021 -ModifiedBy= - -[DeviceInfo] -VendorName=Portland State Aerospace Society -VendorNumber=0 -ProductName=OreSat Template -ProductNumber=0 -RevisionNumber=0 -OrderCode= -BaudRate_10=1 -BaudRate_20=1 -BaudRate_50=1 -BaudRate_125=1 -BaudRate_250=1 -BaudRate_500=1 -BaudRate_800=1 -BaudRate_1000=1 -SimpleBootUpMaster=0 -SimpleBootUpSlave=0 -Granularity=0 -DynamicChannelsSupported=0 -GroupMessaging=0 -NrOfRXPDO=16 -NrOfTXPDO=16 -LSS_Supported=0 - -[DummyUsage] -Dummy0000=1 -Dummy0001=1 -Dummy0002=1 -Dummy0003=1 -Dummy0004=1 -Dummy0005=1 -Dummy0006=1 -Dummy0007=1 - -[Comments] -Lines=0 - -[MandatoryObjects] -SupportedObjects=3 -1=0x1000 -2=0x1001 -3=0x1018 - -[1000] -ParameterName=Device type -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1001] -ParameterName=Error register -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0x00 -PDOMapping=1 - -[1018] -ParameterName=Identity -ObjectType=0x09 -;StorageLocation=ROM -SubNumber=5 - -[1018sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1018sub1] -ParameterName=Vendor-ID -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub2] -ParameterName=Product code -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub3] -ParameterName=Revision number -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub4] -ParameterName=Serial number -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[OptionalObjects] -SupportedObjects=82 -1=0x1002 -2=0x1003 -3=0x1005 -4=0x1006 -5=0x1007 -6=0x1008 -7=0x1009 -8=0x100A -9=0x1010 -10=0x1011 -11=0x1014 -12=0x1015 -13=0x1016 -14=0x1017 -15=0x1019 -16=0x1029 -17=0x1200 -18=0x1400 -19=0x1401 -20=0x1402 -21=0x1403 -22=0x1404 -23=0x1405 -24=0x1406 -25=0x1407 -26=0x1408 -27=0x1409 -28=0x140A -29=0x140B -30=0x140C -31=0x140D -32=0x140E -33=0x140F -34=0x1600 -35=0x1601 -36=0x1602 -37=0x1603 -38=0x1604 -39=0x1605 -40=0x1606 -41=0x1607 -42=0x1608 -43=0x1609 -44=0x160A -45=0x160B -46=0x160C -47=0x160D -48=0x160E -49=0x160F -50=0x1800 -51=0x1801 -52=0x1802 -53=0x1803 -54=0x1804 -55=0x1805 -56=0x1806 -57=0x1807 -58=0x1808 -59=0x1809 -60=0x180A -61=0x180B -62=0x180C -63=0x180D -64=0x180E -65=0x180F -66=0x1A00 -67=0x1A01 -68=0x1A02 -69=0x1A03 -70=0x1A04 -71=0x1A05 -72=0x1A06 -73=0x1A07 -74=0x1A08 -75=0x1A09 -76=0x1A0A -77=0x1A0B -78=0x1A0C -79=0x1A0D -80=0x1A0E -81=0x1A0F -82=0x1F80 - -[1002] -ParameterName=Manufacturer status register -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[1003] -ParameterName=Pre-defined error field -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=9 - -[1003sub0] -ParameterName=Number of errors -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1003sub1] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub2] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub3] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub4] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub5] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub6] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub7] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub8] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1005] -ParameterName=COB-ID SYNC message -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000080 - -[1006] -ParameterName=Communication cycle period -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0 - -[1007] -ParameterName=Synchronous window length -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0 - -[1008] -ParameterName=Manufacturer device name -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=OreSat Node - -[1009] -ParameterName=Manufacturer hardware version -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=0.0 - -[100A] -ParameterName=Manufacturer software version -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=0.0.0 - -[1010] -ParameterName=Store parameters -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=5 - -[1010sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1010sub1] -ParameterName=Save all parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub2] -ParameterName=Save communication parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub3] -ParameterName=Save application parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub4] -ParameterName=Save manufacturer defined parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011] -ParameterName=Restore default parameters -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=5 - -[1011sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1011sub1] -ParameterName=Restore all default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub2] -ParameterName=Restore communication default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub3] -ParameterName=Restore application default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub4] -ParameterName=Restore manufacturer defined default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1014] -ParameterName=COB-ID EMCY -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80+$NODEID - -[1015] -ParameterName=Inhibit time EMCY -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1016] -ParameterName=Consumer heartbeat time -ObjectType=0x08 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1016sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1016sub1] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub2] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub3] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub4] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub5] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub6] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub7] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub8] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1017] -ParameterName=Producer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=1000 - -[1019] -ParameterName=Synchronous counter overflow value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1029] -ParameterName=Error behavior -ObjectType=0x08 -;StorageLocation=ROM -SubNumber=7 - -[1029sub0] -ParameterName=max sub-index -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=const -DefaultValue=0x06 - -[1029sub1] -ParameterName=Communication -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub2] -ParameterName=Communication other -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub3] -ParameterName=Communication passive -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub4] -ParameterName=Generic -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub5] -ParameterName=Device profile -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub6] -ParameterName=Manufacturer specific -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1200] -ParameterName=SDO server parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1200sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1200sub1] -ParameterName=COB-ID client to server -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000000 -PDOMapping=1 - -[1200sub2] -ParameterName=COB-ID server to client -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000000 -PDOMapping=1 - -[1200sub3] -ParameterName=Node-ID of the SDO client -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1400] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1400sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1400sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1400sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1400sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1401] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1401sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1401sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1401sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1401sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1402] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1402sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1402sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[1402sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1402sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1403] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1403sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1403sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[1403sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1403sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1404] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1404sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1404sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1404sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1404sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1405] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1405sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1405sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1405sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1405sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1406] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1406sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1406sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[1406sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1406sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1407] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1407sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1407sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[1407sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1407sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1408] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1408sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1408sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1408sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1408sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1409] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1409sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1409sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1409sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1409sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140A] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Asub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Asub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[140Asub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Asub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140B] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Bsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Bsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[140Bsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Bsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140C] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Csub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Csub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[140Csub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Csub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140D] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Dsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Dsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[140Dsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Dsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140E] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Esub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Esub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[140Esub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Esub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140F] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Fsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Fsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[140Fsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Fsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1600] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1600sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1600sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1601sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1601sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1602sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1602sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1603sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1603sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1604sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1604sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1605sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1605sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1606sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1606sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1607sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1607sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1608sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1608sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1609sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1609sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160A] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Asub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Asub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160B] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Bsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Bsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160C] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Csub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Csub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160D] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Dsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Dsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160E] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Esub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Esub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160F] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Fsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Fsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1800] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1800sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1800sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1800sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1800sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1800sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1800sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1801] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1801sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1801sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1801sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1801sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1801sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1801sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1802] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1802sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1802sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[1802sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1802sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1802sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1802sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1803] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1803sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1803sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[1803sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1803sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1803sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1803sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1804] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1804sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1804sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1804sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1804sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1804sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1804sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1805] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1805sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1805sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1805sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1805sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1805sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1805sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1806] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1806sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1806sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[1806sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1806sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1806sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1806sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1807] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1807sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1807sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[1807sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1807sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1807sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1807sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1808] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1808sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1808sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1808sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1808sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1808sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1808sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1809] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1809sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1809sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1809sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1809sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1809sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1809sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180A] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Asub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Asub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[180Asub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Asub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Asub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Asub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180B] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Bsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Bsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[180Bsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Bsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Bsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Bsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180C] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Csub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Csub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[180Csub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Csub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Csub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Csub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180D] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Dsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Dsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[180Dsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Dsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Dsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Dsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180E] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Esub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Esub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[180Esub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Esub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Esub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Esub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180F] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Fsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Fsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[180Fsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Fsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Fsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Fsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1A00] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A00sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A00sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A01sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A01sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A02sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A02sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A03sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A03sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A04sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A04sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A05sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A05sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A06sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A06sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A07sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A07sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A08sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A08sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A09sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A09sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0A] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Asub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Asub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0B] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Bsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Bsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0C] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Csub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Csub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0D] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Dsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Dsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0E] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Esub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Esub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0F] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Fsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Fsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1F80] -ParameterName=NMTStartup -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000008 - -[ManufacturerObjects] -SupportedObjects=7 -1=0x2000 -2=0x2010 -3=0x2011 -4=0x2020 -5=0x2021 -6=0x2022 -7=0x2100 - -[2000] -ParameterName=BUS Management -ObjectType=0x09 -;StorageLocation=PERSIST_MFR -SubNumber=5 - -[2000sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[2000sub1] -ParameterName=Bdefault -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub2] -ParameterName=Ttoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub3] -ParameterName=Ntoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub4] -ParameterName=Ctoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2010] -ParameterName=SCET -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x001B -AccessType=rw -DefaultValue=0 -PDOMapping=1 - -[2011] -ParameterName=UTC -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x001B -AccessType=rw -DefaultValue=0 -PDOMapping=1 - -[2020] -ParameterName=MCU Unique Device ID -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=4 - -[2020sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[2020sub1] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2020sub2] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2020sub3] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2021] -ParameterName=MCU Calibration -ObjectType=0x09 -;StorageLocation=RAM -SubNumber=4 - -[2021sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[2021sub1] -ParameterName=TS_CAL1 -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2021sub2] -ParameterName=TS_CAL2 -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2021sub3] -ParameterName=VREFINT_CAL -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2022] -ParameterName=MCU Sensors -ObjectType=0x09 -;StorageLocation=RAM -SubNumber=9 - -[2022sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[2022sub1] -ParameterName=Temperature -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0002 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub2] -ParameterName=VREFINT -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub3] -ParameterName=VBAT -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub4] -ParameterName=VBUSP Current -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub5] -ParameterName=Temperature (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub6] -ParameterName=VREFINT (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub7] -ParameterName=VBAT (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub8] -ParameterName=VBUSP Current (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2100] -ParameterName=Error Status Bits -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x000A -AccessType=ro -DefaultValue=00 00 00 00 00 00 00 00 00 00 - diff --git a/src/l4/app_devboard/source/README.md b/src/l4/app_devboard/source/README.md deleted file mode 100644 index b6bc7530..00000000 --- a/src/l4/app_devboard/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/l4/app_devboard/source/blink.c b/src/l4/app_devboard/source/blink.c deleted file mode 100644 index 93010401..00000000 --- a/src/l4/app_devboard/source/blink.c +++ /dev/null @@ -1,18 +0,0 @@ -#include "blink.h" - -/* Example blinker thread */ -THD_WORKING_AREA(blink_wa, 0x40); -THD_FUNCTION(blink, arg) -{ - (void)arg; - - palSetLineMode(LINE_LED,PAL_MODE_OUTPUT_PUSHPULL); - - while (!chThdShouldTerminateX()) { - palToggleLine(LINE_LED); - chThdSleepMilliseconds(500); - } - - palClearLine(LINE_LED); - chThdExit(MSG_OK); -} diff --git a/src/l4/app_devboard/source/blink.h b/src/l4/app_devboard/source/blink.h deleted file mode 100644 index c9178eb2..00000000 --- a/src/l4/app_devboard/source/blink.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _BLINK_H_ -#define _BLINK_H_ - -#include "ch.h" -#include "hal.h" - -/* Example blinker thread prototypes */ -extern THD_WORKING_AREA(blink_wa, 0x40); -extern THD_FUNCTION(blink, arg); - -#endif diff --git a/src/l4/app_devboard_cpp/Makefile b/src/l4/app_devboard_cpp/Makefile deleted file mode 100644 index 6b3f8672..00000000 --- a/src/l4/app_devboard_cpp/Makefile +++ /dev/null @@ -1,217 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -std=gnu++11 -fno-exceptions -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = no -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = app_devboard_cpp - -# Target settings. -MCU = cortex-m4 -BOARD = ST_NUCLEO64_L452RE_P - -#Project sources. -PROJ_ROOT = ../../.. -APP_ROOT = . -PROJ_SRC = $(PROJ_ROOT)/common -PROJ_INC = $(PROJ_SRC)/include -TOOLCHAIN = $(PROJ_ROOT)/toolchain -ODDIR := $(APP_ROOT)/od - -# Imported source files and paths. -CHIBIOS := $(PROJ_ROOT)/ext/ChibiOS -CONFDIR := $(APP_ROOT)/cfg -BUILDDIR := $(APP_ROOT)/build -DEPDIR := $(APP_ROOT)/.dep - -#Board specific directories. -BOARDDIR = $(PROJ_ROOT)/boards/$(BOARD) - -ifeq ($(ORESAT),) - ORESAT = 0.5 -endif - -# generate OD.c/OD.h from oresat-configs -FW_VERSION = $(shell git describe --always) -$(shell oresat-gen-fw-files --oresat $(ORESAT) base -d $(ODDIR) -fw $(FW_VERSION) -hw $(BOARD)) -# add them -ALLCSRC += $(ODDIR)/OD.c -ALLINC += $(ODDIR) - -# Project specific files. -include $(PROJ_SRC)/oresat.mk - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk -include $(BOARDDIR)/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk -include $(CHIBIOS)/os/hal/lib/streams/streams.mk - -# Define linker script file here -LDSCRIPT= $(PROJ_ROOT)/ld/STM32L452xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) \ - $(TESTSRC) - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) \ - main.cpp - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = $(PROJ_INC) - -# List the user directory to look for the libraries here -ULIBDIR = $(PROJ_SRC) - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk -include $(TOOLCHAIN)/toolchain.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## diff --git a/src/l4/app_devboard_cpp/README.md b/src/l4/app_devboard_cpp/README.md deleted file mode 100644 index 1df5134b..00000000 --- a/src/l4/app_devboard_cpp/README.md +++ /dev/null @@ -1,12 +0,0 @@ -# Application Main Directory -## Directory Structure -This folder contains the root of an applications sources. It contains -several files and folders: -* [main.c](main.c): The main program file called by ChibiOS. Contains - initialization code and registers threads and functions. -* [Makefile](Makefile): The main Makefile for the application. Sources - all other build files. -* [cfg](cfg): The directory containing ChibiOS's configuration files for - this application. -* [source](source): The directory where application code is put. - Everything within this directory automatically builds. diff --git a/src/l4/app_devboard_cpp/cfg/CO_driver_custom.h b/src/l4/app_devboard_cpp/cfg/CO_driver_custom.h deleted file mode 100644 index 4d72b881..00000000 --- a/src/l4/app_devboard_cpp/cfg/CO_driver_custom.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef CO_DRIVER_CUSTOM_H -#define CO_DRIVER_CUSTOM_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* CO_DRIVER_CUSTOM_H */ diff --git a/src/l4/app_devboard_cpp/cfg/chconf.h b/src/l4/app_devboard_cpp/cfg/chconf.h deleted file mode 100644 index 29b34229..00000000 --- a/src/l4/app_devboard_cpp/cfg/chconf.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file rt/templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 -#endif - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 -#endif - -/** - * @brief Time intervals data size. - * @note Allowed values are 16, 32 or 64 bits. - */ -#if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 -#endif - -/** - * @brief Time types data size. - * @note Allowed values are 16 or 32 bits. - */ -#if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 -#endif - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE -#endif - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE -#endif - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name OSLIB options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Objects FIFOs APIs. - * @details If enabled then the objects FIFOs APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE -#endif - -/** - * @brief Pipes APIs. - * @details If enabled then the pipes APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE -#endif - -/** - * @brief Objects Caches APIs. - * @details If enabled then the objects caches APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES TRUE -#endif - -/** - * @brief Delegate threads APIs. - * @details If enabled then the delegate threads APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES TRUE -#endif - -/** - * @brief Jobs Queues APIs. - * @details If enabled then the jobs queues APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Objects factory options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Objects Factory APIs. - * @details If enabled then the objects factory APIs are included in the - * kernel. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE -#endif - -/** - * @brief Maximum length for object names. - * @details If the specified length is zero then the name is stored by - * pointer but this could have unintended side effects. - */ -#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 -#endif - -/** - * @brief Enables the registry of generic objects. - */ -#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE -#endif - -/** - * @brief Enables factory for generic buffers. - */ -#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE -#endif - -/** - * @brief Enables factory for semaphores. - */ -#if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE -#endif - -/** - * @brief Enables factory for mailboxes. - */ -#if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE -#endif - -/** - * @brief Enables factory for objects FIFOs. - */ -#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE -#endif - -/** - * @brief Enables factory for Pipes. - */ -#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS TRUE -#endif - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL -#endif - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System structure extension. - * @details User fields added to the end of the @p ch_system_t structure. - */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief System initialization hook. - * @details User initialization code added to the @p chSysInit() function - * just before interrupts are enabled globally. - */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p _thread_init() function. - * - * @note It is invoked from within @p _thread_init() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#if !defined(CORTEX_ENABLE_WFI_IDLE) -#define CORTEX_ENABLE_WFI_IDLE TRUE -#endif - -#endif /* CHCONF_H */ - -/** @} */ diff --git a/src/l4/app_devboard_cpp/cfg/halconf.h b/src/l4/app_devboard_cpp/cfg/halconf.h deleted file mode 100644 index 1b285cb2..00000000 --- a/src/l4/app_devboard_cpp/cfg/halconf.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN TRUE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* HALCONF_H */ - -/** @} */ diff --git a/src/l4/app_devboard_cpp/cfg/mcuconf.h b/src/l4/app_devboard_cpp/cfg/mcuconf.h deleted file mode 100644 index 10774df3..00000000 --- a/src/l4/app_devboard_cpp/cfg/mcuconf.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32L4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#ifndef MCUCONF_H -#define MCUCONF_H - -#define STM32L4xx_MCUCONF -#define STM32L452_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_VOS STM32_VOS_RANGE1 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI16_ENABLED FALSE -#define STM32_HSI48_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED TRUE -#define STM32_MSIPLL_ENABLED TRUE -#define STM32_MSIRANGE STM32_MSIRANGE_4M -#define STM32_MSISRANGE STM32_MSISRANGE_4M -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_MSI -#define STM32_PLLM_VALUE 1 -#define STM32_PLLN_VALUE 80 -#define STM32_PLLPDIV_VALUE 0 -#define STM32_PLLP_VALUE 7 -#define STM32_PLLQ_VALUE 6 -#define STM32_PLLR_VALUE 4 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_STOPWUCK STM32_STOPWUCK_MSI -#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 72 -#define STM32_PLLSAI1PDIV_VALUE 6 -#define STM32_PLLSAI1P_VALUE 7 -#define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 6 - -/* - * Peripherals clock sources. - */ -#define STM32_USART1SEL STM32_USART1SEL_SYSCLK -#define STM32_USART2SEL STM32_USART2SEL_SYSCLK -#define STM32_USART3SEL STM32_USART3SEL_SYSCLK -#define STM32_UART4SEL STM32_UART4SEL_SYSCLK -#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK -#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK -#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK -#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK -#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 -#define STM32_SAI1SEL STM32_SAI1SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 -#define STM32_ADCSEL STM32_ADCSEL_SYSCLK -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI1635_38_PRIORITY 6 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_22_PRIORITY 15 - -#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 -#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 -#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 -#define STM32_IRQ_TIM1_CC_PRIORITY 7 -#define STM32_IRQ_TIM2_PRIORITY 7 -#define STM32_IRQ_TIM3_PRIORITY 7 -#define STM32_IRQ_TIM6_PRIORITY 7 - -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_LPUART1_PRIORITY 12 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM15 FALSE -#define STM32_GPT_USE_TIM16 FALSE - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_USE_I2C4 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C4_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C4_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_USE_TIM16 FALSE - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM15 FALSE -#define STM32_PWM_USE_TIM16 FALSE - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_USE_SDMMC1 FALSE -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 -#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 -#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 -#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_LPUART1 TRUE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_LPUART1_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * TRNG driver system settings. - */ -#define STM32_TRNG_USE_RNG1 FALSE - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * WSPI driver system settings. - */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) - -#endif /* MCUCONF_H */ diff --git a/src/l4/app_devboard_cpp/main.cpp b/src/l4/app_devboard_cpp/main.cpp deleted file mode 100644 index eca517c2..00000000 --- a/src/l4/app_devboard_cpp/main.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* ChibiOS header files */ -#include "ch.h" -#include "hal.h" - -/* Project header files */ -#include "oresat.h" -#include "blink.h" - -static worker_t worker1; -static thread_descriptor_t worker1_desc = { - .name = "Example blinky thread", - .wbase = THD_WORKING_AREA_BASE(blink_wa), - .wend = THD_WORKING_AREA_END(blink_wa), - .prio = NORMALPRIO, - .funcp = blink, - .arg = NULL -}; - -static oresat_config_t oresat_conf = { - .cand = &CAND1, - .node_id = ORESAT_DEFAULT_ID, - .bitrate = ORESAT_DEFAULT_BITRATE, -}; - -/** - * @brief App Initialization - */ -static void app_init(void) -{ - /* App initialization */ - reg_worker(&worker1, &worker1_desc, false, true); - - /* Start up debug output */ - sdStart(&LPSD1, NULL); -} - -/** - * @brief Main Application - */ -int main(void) -{ - // Initialize and start - oresat_init(&oresat_conf); - app_init(); - oresat_start(); - return 0; -} diff --git a/src/l4/app_devboard_cpp/od/app.eds b/src/l4/app_devboard_cpp/od/app.eds deleted file mode 100644 index 116bbad9..00000000 --- a/src/l4/app_devboard_cpp/od/app.eds +++ /dev/null @@ -1,4863 +0,0 @@ -[FileInfo] -FileName=app.eds -FileVersion=0 -FileRevision=1 -EDSVersion=4.0 -Description=OreSat Template Application Object Dictionary -CreationTime=02:51PM -CreationDate=08-12-2019 -CreatedBy=Miles Simpson -ModificationTime=11:45AM -ModificationDate=04-25-2021 -ModifiedBy= - -[DeviceInfo] -VendorName=Portland State Aerospace Society -VendorNumber=0 -ProductName=OreSat Template -ProductNumber=0 -RevisionNumber=0 -OrderCode= -BaudRate_10=1 -BaudRate_20=1 -BaudRate_50=1 -BaudRate_125=1 -BaudRate_250=1 -BaudRate_500=1 -BaudRate_800=1 -BaudRate_1000=1 -SimpleBootUpMaster=0 -SimpleBootUpSlave=0 -Granularity=0 -DynamicChannelsSupported=0 -GroupMessaging=0 -NrOfRXPDO=16 -NrOfTXPDO=16 -LSS_Supported=0 - -[DummyUsage] -Dummy0000=1 -Dummy0001=1 -Dummy0002=1 -Dummy0003=1 -Dummy0004=1 -Dummy0005=1 -Dummy0006=1 -Dummy0007=1 - -[Comments] -Lines=0 - -[MandatoryObjects] -SupportedObjects=3 -1=0x1000 -2=0x1001 -3=0x1018 - -[1000] -ParameterName=Device type -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1001] -ParameterName=Error register -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0x00 -PDOMapping=1 - -[1018] -ParameterName=Identity -ObjectType=0x09 -;StorageLocation=ROM -SubNumber=5 - -[1018sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1018sub1] -ParameterName=Vendor-ID -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub2] -ParameterName=Product code -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub3] -ParameterName=Revision number -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1018sub4] -ParameterName=Serial number -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[OptionalObjects] -SupportedObjects=82 -1=0x1002 -2=0x1003 -3=0x1005 -4=0x1006 -5=0x1007 -6=0x1008 -7=0x1009 -8=0x100A -9=0x1010 -10=0x1011 -11=0x1014 -12=0x1015 -13=0x1016 -14=0x1017 -15=0x1019 -16=0x1029 -17=0x1200 -18=0x1400 -19=0x1401 -20=0x1402 -21=0x1403 -22=0x1404 -23=0x1405 -24=0x1406 -25=0x1407 -26=0x1408 -27=0x1409 -28=0x140A -29=0x140B -30=0x140C -31=0x140D -32=0x140E -33=0x140F -34=0x1600 -35=0x1601 -36=0x1602 -37=0x1603 -38=0x1604 -39=0x1605 -40=0x1606 -41=0x1607 -42=0x1608 -43=0x1609 -44=0x160A -45=0x160B -46=0x160C -47=0x160D -48=0x160E -49=0x160F -50=0x1800 -51=0x1801 -52=0x1802 -53=0x1803 -54=0x1804 -55=0x1805 -56=0x1806 -57=0x1807 -58=0x1808 -59=0x1809 -60=0x180A -61=0x180B -62=0x180C -63=0x180D -64=0x180E -65=0x180F -66=0x1A00 -67=0x1A01 -68=0x1A02 -69=0x1A03 -70=0x1A04 -71=0x1A05 -72=0x1A06 -73=0x1A07 -74=0x1A08 -75=0x1A09 -76=0x1A0A -77=0x1A0B -78=0x1A0C -79=0x1A0D -80=0x1A0E -81=0x1A0F -82=0x1F80 - -[1002] -ParameterName=Manufacturer status register -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[1003] -ParameterName=Pre-defined error field -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=9 - -[1003sub0] -ParameterName=Number of errors -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1003sub1] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub2] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub3] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub4] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub5] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub6] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub7] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1003sub8] -ParameterName=Standard error field -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0x00000000 - -[1005] -ParameterName=COB-ID SYNC message -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000080 - -[1006] -ParameterName=Communication cycle period -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0 - -[1007] -ParameterName=Synchronous window length -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0 - -[1008] -ParameterName=Manufacturer device name -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=OreSat Node - -[1009] -ParameterName=Manufacturer hardware version -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=0.0 - -[100A] -ParameterName=Manufacturer software version -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0009 -AccessType=ro -DefaultValue=0.0.0 - -[1010] -ParameterName=Store parameters -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=5 - -[1010sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1010sub1] -ParameterName=Save all parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub2] -ParameterName=Save communication parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub3] -ParameterName=Save application parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1010sub4] -ParameterName=Save manufacturer defined parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011] -ParameterName=Restore default parameters -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=5 - -[1011sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[1011sub1] -ParameterName=Restore all default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub2] -ParameterName=Restore communication default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub3] -ParameterName=Restore application default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1011sub4] -ParameterName=Restore manufacturer defined default parameters -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000001 - -[1014] -ParameterName=COB-ID EMCY -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80+$NODEID - -[1015] -ParameterName=Inhibit time EMCY -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1016] -ParameterName=Consumer heartbeat time -ObjectType=0x08 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1016sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1016sub1] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub2] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub3] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub4] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub5] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub6] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub7] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1016sub8] -ParameterName=Consumer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1017] -ParameterName=Producer heartbeat time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=1000 - -[1019] -ParameterName=Synchronous counter overflow value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1029] -ParameterName=Error behavior -ObjectType=0x08 -;StorageLocation=ROM -SubNumber=7 - -[1029sub0] -ParameterName=max sub-index -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=const -DefaultValue=0x06 - -[1029sub1] -ParameterName=Communication -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub2] -ParameterName=Communication other -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub3] -ParameterName=Communication passive -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub4] -ParameterName=Generic -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub5] -ParameterName=Device profile -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1029sub6] -ParameterName=Manufacturer specific -ObjectType=0x07 -;StorageLocation=ROM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1200] -ParameterName=SDO server parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1200sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1200sub1] -ParameterName=COB-ID client to server -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000000 -PDOMapping=1 - -[1200sub2] -ParameterName=COB-ID server to client -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000000 -PDOMapping=1 - -[1200sub3] -ParameterName=Node-ID of the SDO client -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0x01 - -[1400] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1400sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1400sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1400sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1400sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1401] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1401sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1401sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1401sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1401sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1402] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1402sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1402sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[1402sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1402sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1403] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1403sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1403sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[1403sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1403sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1404] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1404sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1404sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1404sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1404sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1405] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1405sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1405sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1405sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1405sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1406] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1406sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1406sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[1406sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1406sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1407] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1407sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1407sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[1407sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1407sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1408] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1408sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1408sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[1408sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1408sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1409] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[1409sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[1409sub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[1409sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1409sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140A] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Asub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Asub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[140Asub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Asub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140B] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Bsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Bsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[140Bsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Bsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140C] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Csub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Csub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000200+$NODEID - -[140Csub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Csub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140D] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Dsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Dsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000300+$NODEID - -[140Dsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Dsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140E] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Esub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Esub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000400+$NODEID - -[140Esub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Esub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[140F] -ParameterName=RPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=4 - -[140Fsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[140Fsub1] -ParameterName=COB-ID used by RPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x80000500+$NODEID - -[140Fsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[140Fsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1600] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1600sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1600sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1600sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1601sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1601sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1601sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1602sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1602sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1602sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1603sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1603sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1603sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1604sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1604sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1604sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1605sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1605sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1605sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1606sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1606sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1606sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1607sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1607sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1607sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1608sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1608sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1608sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1609sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1609sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1609sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160A] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Asub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Asub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Asub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160B] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Bsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Bsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Bsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160C] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Csub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Csub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Csub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160D] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Dsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Dsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Dsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160E] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Esub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Esub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Esub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160F] -ParameterName=RPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[160Fsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[160Fsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[160Fsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1800] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1800sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1800sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1800sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1800sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1800sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1800sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1801] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1801sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1801sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1801sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1801sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1801sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1801sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1802] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1802sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1802sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[1802sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1802sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1802sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1802sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1803] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1803sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1803sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[1803sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1803sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1803sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1803sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1804] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1804sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1804sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1804sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1804sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1804sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1804sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1805] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1805sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1805sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1805sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1805sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1805sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1805sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1806] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1806sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1806sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[1806sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1806sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1806sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1806sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1807] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1807sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1807sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[1807sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1807sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1807sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1807sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1808] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1808sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1808sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[1808sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1808sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1808sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1808sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1809] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[1809sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[1809sub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[1809sub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[1809sub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1809sub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[1809sub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180A] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Asub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Asub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[180Asub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Asub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Asub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Asub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180B] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Bsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Bsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[180Bsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Bsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Bsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Bsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180C] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Csub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Csub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000180+$NODEID - -[180Csub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Csub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Csub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Csub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180D] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Dsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Dsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000280+$NODEID - -[180Dsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Dsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Dsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Dsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180E] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Esub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Esub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000380+$NODEID - -[180Esub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Esub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Esub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Esub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[180F] -ParameterName=TPDO communication parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=6 - -[180Fsub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x05 - -[180Fsub1] -ParameterName=COB-ID used by TPDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0xC0000480+$NODEID - -[180Fsub2] -ParameterName=Transmission type -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=254 - -[180Fsub3] -ParameterName=Inhibit time -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Fsub5] -ParameterName=Event timer -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0006 -AccessType=rw -DefaultValue=0 - -[180Fsub6] -ParameterName=SYNC start value -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[1A00] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A00sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A00sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A00sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A01sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A01sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A01sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A02sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A02sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A02sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A03sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A03sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A03sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A04sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A04sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A04sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A05sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A05sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A05sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A06sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A06sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A06sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A07sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A07sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A07sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A08sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A08sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A08sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A09sub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A09sub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A09sub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0A] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Asub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Asub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Asub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0B] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Bsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Bsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Bsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0C] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Csub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Csub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Csub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0D] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Dsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Dsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Dsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0E] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Esub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Esub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Esub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0F] -ParameterName=TPDO mapping parameter -ObjectType=0x09 -;StorageLocation=PERSIST_COMM -SubNumber=9 - -[1A0Fsub0] -ParameterName=Number of mapped application objects in PDO -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[1A0Fsub1] -ParameterName=Application object 1 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub2] -ParameterName=Application object 2 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub3] -ParameterName=Application object 3 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub4] -ParameterName=Application object 4 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub5] -ParameterName=Application object 5 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub6] -ParameterName=Application object 6 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub7] -ParameterName=Application object 7 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1A0Fsub8] -ParameterName=Application object 8 -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000000 - -[1F80] -ParameterName=NMTStartup -ObjectType=0x07 -;StorageLocation=PERSIST_COMM -DataType=0x0007 -AccessType=rw -DefaultValue=0x00000008 - -[ManufacturerObjects] -SupportedObjects=7 -1=0x2000 -2=0x2010 -3=0x2011 -4=0x2020 -5=0x2021 -6=0x2022 -7=0x2100 - -[2000] -ParameterName=BUS Management -ObjectType=0x09 -;StorageLocation=PERSIST_MFR -SubNumber=5 - -[2000sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=const -DefaultValue=0x04 - -[2000sub1] -ParameterName=Bdefault -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub2] -ParameterName=Ttoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub3] -ParameterName=Ntoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2000sub4] -ParameterName=Ctoggle -ObjectType=0x07 -;StorageLocation=PERSIST_MFR -DataType=0x0005 -AccessType=rw -DefaultValue=0 - -[2010] -ParameterName=SCET -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x001B -AccessType=rw -DefaultValue=0 -PDOMapping=1 - -[2011] -ParameterName=UTC -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x001B -AccessType=rw -DefaultValue=0 -PDOMapping=1 - -[2020] -ParameterName=MCU Unique Device ID -ObjectType=0x08 -;StorageLocation=RAM -SubNumber=4 - -[2020sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[2020sub1] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2020sub2] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2020sub3] -ParameterName=UID -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0007 -AccessType=ro -DefaultValue=0 - -[2021] -ParameterName=MCU Calibration -ObjectType=0x09 -;StorageLocation=RAM -SubNumber=4 - -[2021sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x03 - -[2021sub1] -ParameterName=TS_CAL1 -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2021sub2] -ParameterName=TS_CAL2 -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2021sub3] -ParameterName=VREFINT_CAL -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 - -[2022] -ParameterName=MCU Sensors -ObjectType=0x09 -;StorageLocation=RAM -SubNumber=9 - -[2022sub0] -ParameterName=Highest sub-index supported -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=const -DefaultValue=0x08 - -[2022sub1] -ParameterName=Temperature -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0002 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub2] -ParameterName=VREFINT -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub3] -ParameterName=VBAT -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub4] -ParameterName=VBUSP Current -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0005 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub5] -ParameterName=Temperature (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub6] -ParameterName=VREFINT (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub7] -ParameterName=VBAT (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2022sub8] -ParameterName=VBUSP Current (Raw) -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x0006 -AccessType=ro -DefaultValue=0 -PDOMapping=1 - -[2100] -ParameterName=Error Status Bits -ObjectType=0x07 -;StorageLocation=RAM -DataType=0x000A -AccessType=ro -DefaultValue=00 00 00 00 00 00 00 00 00 00 - diff --git a/src/l4/app_devboard_cpp/source/README.md b/src/l4/app_devboard_cpp/source/README.md deleted file mode 100644 index a38d5d9b..00000000 --- a/src/l4/app_devboard_cpp/source/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# App-specific Source - -Put any .h or .c files (besides main.c) you want to compile with your app in here. They will automatically build when you run make. - -If you don't want them to build, move them to another directory or the app's top level directory to effectively "disable" them. diff --git a/src/l4/app_devboard_cpp/source/blink.cpp b/src/l4/app_devboard_cpp/source/blink.cpp deleted file mode 100644 index 93010401..00000000 --- a/src/l4/app_devboard_cpp/source/blink.cpp +++ /dev/null @@ -1,18 +0,0 @@ -#include "blink.h" - -/* Example blinker thread */ -THD_WORKING_AREA(blink_wa, 0x40); -THD_FUNCTION(blink, arg) -{ - (void)arg; - - palSetLineMode(LINE_LED,PAL_MODE_OUTPUT_PUSHPULL); - - while (!chThdShouldTerminateX()) { - palToggleLine(LINE_LED); - chThdSleepMilliseconds(500); - } - - palClearLine(LINE_LED); - chThdExit(MSG_OK); -} diff --git a/src/l4/app_devboard_cpp/source/blink.h b/src/l4/app_devboard_cpp/source/blink.h deleted file mode 100644 index c9178eb2..00000000 --- a/src/l4/app_devboard_cpp/source/blink.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _BLINK_H_ -#define _BLINK_H_ - -#include "ch.h" -#include "hal.h" - -/* Example blinker thread prototypes */ -extern THD_WORKING_AREA(blink_wa, 0x40); -extern THD_FUNCTION(blink, arg); - -#endif

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