diff --git a/.doctrees/api.doctree b/.doctrees/api.doctree index 21e1a0a7c..142ce374b 100644 Binary files a/.doctrees/api.doctree and b/.doctrees/api.doctree differ diff --git a/.doctrees/auto_graph.doctree b/.doctrees/auto_graph.doctree index 9e765d2d8..e3366e611 100644 Binary files a/.doctrees/auto_graph.doctree and b/.doctrees/auto_graph.doctree differ diff --git a/.doctrees/current-graph.doctree b/.doctrees/current-graph.doctree index e678de0e6..1e4e4c480 100644 Binary files a/.doctrees/current-graph.doctree and b/.doctrees/current-graph.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 1e21cf8b7..c05911b53 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/_sources/auto_graph.rst.txt b/_sources/auto_graph.rst.txt index 2d072c51d..f22b2c784 100644 --- a/_sources/auto_graph.rst.txt +++ b/_sources/auto_graph.rst.txt @@ -6,9 +6,9 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] - WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] Forwarder_write["write"] Forwarder_read["read"] @@ -19,13 +19,13 @@ WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -37,8 +37,8 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] @@ -52,32 +52,32 @@ end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] - CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_target_pred_req["target_pred_req"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_clear["clear"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] + BasicFifo2_clear["clear"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end end subgraph ICache["icache ICache"] + ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_accept_res["accept_res"] - ICache_MemRead["MemRead"] ICache_ICache1["ICache"] ICache_flush["flush"] - ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -105,30 +105,30 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] - ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_read["read"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] BasicFifo3_peek["peek"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_stall_exception["stall_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage0["Fetch_Stage0"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -136,9 +136,9 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] + Serializer_write["write"] Serializer_clean["clean"] Serializer_read["read"] - Serializer_write["write"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -172,9 +172,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_clean["clean"] - Pipe1_read["read"] Pipe1_write["write"] + Pipe1_read["read"] + Pipe1_clean["clean"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -184,22 +184,22 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_perf["perf"] - RegisterFile_write["write"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_write["write"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -217,11 +217,11 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_perf["perf"] ReorderBuffer_retire["retire"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_put["put"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] @@ -229,8 +229,8 @@ HwExpHistogram3__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -238,12 +238,12 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -253,8 +253,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -272,30 +272,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_get_result["get_result"] - RSFuncBlock_update["update"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_insert["insert"] RS_RS["RS"] - RS_select["select"] RS_RS1["RS"] RS_RS2["RS"] - RS_take["take"] - RS_insert["insert"] - RS_RS3["RS"] + RS_perf["perf"] + RS_select["select"] RS_update["update"] + RS_RS3["RS"] RS_RS4["RS"] - RS_perf["perf"] + RS_take["take"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read["read"] AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -320,8 +320,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -331,8 +331,8 @@ JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -344,8 +344,8 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -355,20 +355,20 @@ ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_write["write"] @@ -408,25 +408,25 @@ end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_insert["insert"] + RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] RSFuncBlock1_update["update"] - RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] FifoRS_select["select"] FifoRS_insert["insert"] - FifoRS_perf["perf"] FifoRS_take["take"] FifoRS_update["update"] + FifoRS_FifoRS["FifoRS"] + FifoRS_perf["perf"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_read["read"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -436,19 +436,19 @@ subgraph LSUDummy["func_unit_0 LSUDummy"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_issue["issue"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_issue["issue"] LSUDummy_accept_cond0["accept_cond0"] - LSUDummy_accept["accept"] LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_accept["accept"] subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] subgraph BasicFifo9["args_fifo BasicFifo"] BasicFifo9_read["read"] BasicFifo9_write["write"] @@ -459,16 +459,16 @@ Forwarder6_write["write"] end subgraph FIFO6["results_noop FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph FIFO8["issued_noop FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end end subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] @@ -477,8 +477,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -488,13 +488,13 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_update["update"] CSRUnit_insert["insert"] - CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit1["CSRUnit"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_CSRUnit1["CSRUnit"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -547,13 +547,13 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_read["_fu_read"] AliasedCSR__fu_write["_fu_write"] + AliasedCSR__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_write["_internal_fu_write"] CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -565,9 +565,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] - CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] + CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -579,10 +579,10 @@ end end subgraph CSRRegister8["mepc CSRRegister"] - CSRRegister8_write["write"] CSRRegister8_read["read"] - CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8__internal_fu_write["_internal_fu_write"] + CSRRegister8_write["write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -597,17 +597,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister9["register_low CSRRegister"] + CSRRegister9_read["read"] CSRRegister9_write["write"] CSRRegister9__internal_fu_read["_internal_fu_read"] - CSRRegister9_read["read"] subgraph MethodMap19["fu_read_map MethodMap"] MethodMap19_method["method"] end end subgraph CSRRegister10["register_high CSRRegister"] + CSRRegister10_read["read"] CSRRegister10_write["write"] CSRRegister10__internal_fu_read["_internal_fu_read"] - CSRRegister10_read["read"] subgraph MethodMap21["fu_read_map MethodMap"] MethodMap21_method["method"] end @@ -616,17 +616,17 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister11["register_low CSRRegister"] - CSRRegister11_write["write"] CSRRegister11__internal_fu_read["_internal_fu_read"] + CSRRegister11_write["write"] CSRRegister11_read["read"] subgraph MethodMap23["fu_read_map MethodMap"] MethodMap23_method["method"] end end subgraph CSRRegister12["register_high CSRRegister"] + CSRRegister12_write["write"] CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_read["read"] - CSRRegister12_write["write"] subgraph MethodMap25["fu_read_map MethodMap"] MethodMap25_method["method"] end @@ -635,16 +635,16 @@ end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_entry["entry"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_mret["mret"] + InternalInterruptController_entry["entry"] subgraph CSRRegister13["mstatus_mie CSRRegister"] CSRRegister13_read["read"] - CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_write["write"] CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -656,10 +656,10 @@ end end subgraph CSRRegister14["mstatus_mpie CSRRegister"] + CSRRegister14_write["write"] + CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14_read["read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -684,9 +684,9 @@ end end subgraph CSRRegister16["mie CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] - CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16_read["read"] + CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] end @@ -698,11 +698,11 @@ end end subgraph CSRRegister17["mip CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17_read["read"] CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_read["read"] CSRRegister17_read_comb["read_comb"] CSRRegister17__internal_fu_write["_internal_fu_write"] + CSRRegister17_write["write"] subgraph MethodMap34["fu_write_map MethodMap"] MethodMap34_method["method"] end @@ -723,8 +723,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -737,8 +737,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -777,20 +777,20 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_precommit["precommit"] + Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_precommit["precommit"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] - CSRRegister18_read["read"] CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18_read["read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -808,8 +808,8 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__stop["_stop"] FIFOLatencyMeasurer2__start["_start"] + FIFOLatencyMeasurer2__stop["_stop"] subgraph HwExpHistogram9["histogram HwExpHistogram"] HwExpHistogram9__add["_add"] end @@ -822,27 +822,27 @@ end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond1["ConnectTrans_accept_cond0_accept_cond1"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond1["ConnectTrans_accept_cond0_accept_cond1"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] end end Core_InitFreeRFFifo --> BasicFifo5_write - Retirement_Retirement --> BasicFifo5_write - TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write - TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write + Retirement_Retirement3 --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write + TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify @@ -901,31 +901,31 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister11_write CSRRegister12_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister12_write + CSRRegister13_read --> InternalInterruptController_InternalInterruptController CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 - CSRRegister16_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister17_read --> InternalInterruptController_InternalInterruptController1 - CSRRegister17_read_comb --> InternalInterruptController_InternalInterruptController - InternalInterruptController_InternalInterruptController --> CSRRegister17_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write - InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write - CSRRegister14_read --> InternalInterruptController_InternalInterruptController2 + CSRRegister16_read --> InternalInterruptController_InternalInterruptController + CSRRegister17_read --> InternalInterruptController_InternalInterruptController + CSRRegister17_read_comb --> InternalInterruptController_InternalInterruptController2 + InternalInterruptController_InternalInterruptController2 --> CSRRegister17_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write + InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write + CSRRegister14_read --> InternalInterruptController_InternalInterruptController1 MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write + FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection2 - FIFO10_read --> RSSelection_RSSelection1 - RSFuncBlock_select --> RSSelection_RSSelection - RS_select --> RSSelection_RSSelection + RSFuncBlock_select --> RSSelection_RSSelection1 + RS_select --> RSSelection_RSSelection1 + RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write - RSSelection_RSSelection1 --> FIFO11_write - RSFuncBlock1_select --> RSSelection_RSSelection2 - FifoRS_select --> RSSelection_RSSelection2 - RSSelection_RSSelection1 <--> CSRUnit_select + RSFuncBlock1_select --> RSSelection_RSSelection + FifoRS_select --> RSSelection_RSSelection + RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -967,7 +967,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add - RS_RS2 --> WakeupSelect_WakeupSelect + RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -999,17 +999,17 @@ WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr - RS_RS4 --> WakeupSelect3_WakeupSelect + RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> BasicFifo6_write - TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write + TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write - RS_RS3 --> WakeupSelect4_WakeupSelect + RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -1032,36 +1032,36 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add - Forwarder6_read --> LSUDummy_LSUDummy + Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_issue_cond2_LSUDummy - Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy - LSUDummy_LSUDummy --> FIFO6_write + Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy + LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_issue_cond2_LSUDummy --> FIFO6_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write TransactionManager_issue_cond1_LSUDummy --> FIFO6_write - LSUDummy_LSUDummy --> FIFO8_write + TransactionManager_issue_cond0_LSUDummy --> FIFO6_write + LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_issue_cond2_LSUDummy --> FIFO8_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write TransactionManager_issue_cond1_LSUDummy --> FIFO8_write - Retirement_precommit --> LSUDummy_LSUDummy1 + TransactionManager_issue_cond0_LSUDummy --> FIFO8_write + Retirement_precommit --> LSUDummy_LSUDummy Retirement_precommit --> CSRUnit_CSRUnit - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - ReorderBuffer_peek --> LSUDummy_LSUDummy1 + Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + ReorderBuffer_peek --> LSUDummy_LSUDummy ReorderBuffer_peek --> CSRUnit_CSRUnit ReorderBuffer_peek --> Retirement_Retirement2 - ReorderBuffer_peek --> Retirement_Retirement - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + ReorderBuffer_peek --> Retirement_Retirement3 + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 + ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement - ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement + ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -1149,165 +1149,165 @@ Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans ExceptionCauseRegister_get --> Retirement_Retirement2 - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement - ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire - TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire - Retirement_Retirement <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop - FIFO1_read --> Retirement_Retirement - FIFO1_read --> TransactionManager_Retirement_cond1_Retirement - FIFO1_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram3__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add - CoreInstructionCounter_decrement --> Retirement_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement - CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement - RRAT_peek --> Retirement_Retirement - RRAT_peek --> TransactionManager_Retirement_cond1_Retirement - Retirement_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free - TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free - Retirement_Retirement --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop - TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop - AsyncMemoryBank_read --> Retirement_Retirement - AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement - AsyncMemoryBank_read --> TransactionManager_Retirement_cond0_Retirement - Retirement_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add - TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add - Retirement_Retirement --> FRAT_rename - TransactionManager_ROBAllocation_Renaming --> FRAT_rename - TransactionManager_Retirement_cond1_Retirement --> FRAT_rename - Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop - FIFO12_read --> Retirement_Retirement1 - Retirement_Retirement1 --> HwExpHistogram9__add - CSRRegister7_read --> Retirement_Retirement1 - Retirement_Retirement1 --> FetchUnit_resume_from_exception - Retirement_Retirement1 <--> ExceptionCauseRegister_clear - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> Forwarder7_write - TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 - TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSUDummy_accept_cond0 - LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 - WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - Serializer1_Serializer --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 - Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSURequester_accept_cond1 - WishboneMasterAdapter1_get_read_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - Serializer1_Serializer3 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 - TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 - TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 - TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue - TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue - TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue - TransactionManager_issue_cond2_LSUDummy --> BasicFifo9_write - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write - TransactionManager_issue_cond1_LSUDummy --> BasicFifo9_write - TransactionManager_issue_cond2_LSUDummy --> FIFO7_write - TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write - TransactionManager_issue_cond1_LSUDummy --> FIFO7_write - TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 - FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 - FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 - TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation - Connect_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put - TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start - TransactionManager_ROBAllocation_Renaming --> FIFO1_write - TransactionManager_ROBAllocation_Renaming --> FIFO10_write - TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming - FIFO9_read --> TransactionManager_ROBAllocation_Renaming - TransactionManager_ROBAllocation_Renaming --> Connect_write - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 + ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire + TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire + Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop + FIFO1_read --> Retirement_Retirement3 + FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 + FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add + CoreInstructionCounter_decrement --> Retirement_Retirement3 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 + CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 + RRAT_peek --> Retirement_Retirement3 + RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free + TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free + Retirement_Retirement3 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop + TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop + AsyncMemoryBank_read --> Retirement_Retirement3 + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 + AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 + Retirement_Retirement3 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add + TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add + Retirement_Retirement3 --> FRAT_rename + TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename + TransactionManager_Renaming_ROBAllocation --> FRAT_rename + Retirement_Retirement <--> FIFOLatencyMeasurer2__stop + FIFO12_read --> Retirement_Retirement + Retirement_Retirement --> HwExpHistogram9__add + CSRRegister7_read --> Retirement_Retirement + Retirement_Retirement --> FetchUnit_resume_from_exception + Retirement_Retirement <--> ExceptionCauseRegister_clear + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 + TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start + TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write + TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 + InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write + TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry + TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit + TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment + CSRRegister18_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister18_write + CSRRegister19_read --> TransactionManager_Retirement_Retirement_cond0 + TransactionManager_Retirement_Retirement_cond0 --> CSRRegister19_write + TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release - Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode + Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr - TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 - TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 - TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write - TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 - TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write - TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write - TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request - TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 - TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 - TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start - TransactionManager_Retirement_cond1_Retirement --> FIFO12_write - TransactionManager_Retirement_cond0_Retirement --> FIFO12_write - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement - InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write - TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write - TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry - TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr + TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 + TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 + TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue + TransactionManager_issue_cond2_LSUDummy --> BasicFifo9_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo9_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write + TransactionManager_issue_cond2_LSUDummy --> FIFO7_write + TransactionManager_issue_cond1_LSUDummy --> FIFO7_write + TransactionManager_issue_cond0_LSUDummy --> FIFO7_write + TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 + TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer2 - TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 - TransactionManager_Retirement_cond0_Retirement --> RRAT_commit - TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment - CSRRegister18_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister18_write - CSRRegister19_read --> TransactionManager_Retirement_cond0_Retirement - TransactionManager_Retirement_cond0_Retirement --> CSRRegister19_write - TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write + TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write + TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request + TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request + TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans + TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> Forwarder7_write + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write + TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans + TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSUDummy_accept_cond0 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 + LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSURequester_accept_cond1 + WishboneMasterAdapter1_get_read_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + Serializer1_Serializer1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 + Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming + FIFO9_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> Connect_write + TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation + Connect_read --> TransactionManager_Renaming_ROBAllocation + TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put + TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start + TransactionManager_Renaming_ROBAllocation --> FIFO1_write + TransactionManager_Renaming_ROBAllocation --> FIFO10_write + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 + TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 + WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + Serializer1_Serializer --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret + TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 + FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans + FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans + TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 + TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write + TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 diff --git a/api.html b/api.html index 2a15fd57e..d02d3d58a 100644 --- a/api.html +++ b/api.html @@ -271,7 +271,7 @@

transactron

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-07-17. + Last updated on 12:18 2024-08-11.

diff --git a/assumptions.html b/assumptions.html index 94b9094fa..ebaa38b97 100644 --- a/assumptions.html +++ b/assumptions.html @@ -104,7 +104,7 @@

List of assumptions made during development

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-07-17. + Last updated on 12:18 2024-08-11.

diff --git a/auto_graph.html b/auto_graph.html index 63b4b2dd4..510b3964a 100644 --- a/auto_graph.html +++ b/auto_graph.html @@ -85,9 +85,9 @@ subgraph Core["core Core"] Core_InitFreeRFFifo["InitFreeRFFifo"] subgraph WishboneMaster["wb_master_instr WishboneMaster"] + WishboneMaster_result["result"] WishboneMaster_WishboneMaster["WishboneMaster"] WishboneMaster_request["request"] - WishboneMaster_result["result"] subgraph Forwarder["result Forwarder"] Forwarder_write["write"] Forwarder_read["read"] @@ -98,13 +98,13 @@ WishboneMaster1_result["result"] WishboneMaster1_request["request"] subgraph Forwarder1["result Forwarder"] - Forwarder1_write["write"] Forwarder1_read["read"] + Forwarder1_write["write"] end end subgraph WishboneMasterAdapter["bus_master_instr_adapter WishboneMasterAdapter"] - WishboneMasterAdapter_get_read_response["get_read_response"] WishboneMasterAdapter_request_read["request_read"] + WishboneMasterAdapter_get_read_response["get_read_response"] subgraph Serializer["bus_serializer Serializer"] Serializer_Serializer["Serializer"] Serializer_Serializer1["Serializer"] @@ -116,8 +116,8 @@ end subgraph WishboneMasterAdapter1["bus_master_data_adapter WishboneMasterAdapter"] WishboneMasterAdapter1_get_read_response["get_read_response"] - WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_get_write_response["get_write_response"] + WishboneMasterAdapter1_request_write["request_write"] WishboneMasterAdapter1_request_read["request_read"] subgraph Serializer1["bus_serializer Serializer"] Serializer1_Serializer["Serializer"] @@ -131,32 +131,32 @@ end end subgraph CoreFrontend["frontend CoreFrontend"] - CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] - CoreFrontend_target_pred_req["target_pred_req"] CoreFrontend_stall["stall"] CoreFrontend_target_pred_resp["target_pred_resp"] + CoreFrontend_DiscardBranchVerify["DiscardBranchVerify"] + CoreFrontend_target_pred_req["target_pred_req"] subgraph BasicFifo2["instr_buffer BasicFifo"] - BasicFifo2_clear["clear"] - BasicFifo2_read["read"] BasicFifo2_write["write"] + BasicFifo2_read["read"] + BasicFifo2_clear["clear"] end subgraph SimpleCommonBusCacheRefiller["icache_refiller SimpleCommonBusCacheRefiller"] + SimpleCommonBusCacheRefiller_start_refill["start_refill"] + SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller["SimpleCommonBusCacheRefiller"] SimpleCommonBusCacheRefiller_SimpleCommonBusCacheRefiller1["SimpleCommonBusCacheRefiller"] - SimpleCommonBusCacheRefiller_accept_refill["accept_refill"] - SimpleCommonBusCacheRefiller_start_refill["start_refill"] subgraph Forwarder2["resp_fwd Forwarder"] Forwarder2_read["read"] Forwarder2_write["write"] end end subgraph ICache["icache ICache"] + ICache_MemRead["MemRead"] + ICache_issue_req["issue_req"] ICache_ICache["ICache"] ICache_accept_res["accept_res"] - ICache_MemRead["MemRead"] ICache_ICache1["ICache"] ICache_flush["flush"] - ICache_issue_req["issue_req"] subgraph HwCounter["perf_loads HwCounter"] HwCounter__incr["_incr"] end @@ -184,30 +184,30 @@ end end subgraph ArgumentsToResultsZipper["req_zipper ArgumentsToResultsZipper"] - ArgumentsToResultsZipper_peek_arg["peek_arg"] - ArgumentsToResultsZipper_read["read"] - ArgumentsToResultsZipper_write_results["write_results"] ArgumentsToResultsZipper_write_args["write_args"] + ArgumentsToResultsZipper_write_results["write_results"] + ArgumentsToResultsZipper_read["read"] + ArgumentsToResultsZipper_peek_arg["peek_arg"] subgraph BasicFifo3["fifo BasicFifo"] BasicFifo3_write["write"] BasicFifo3_read["read"] BasicFifo3_peek["peek"] end subgraph Forwarder3["forwarder Forwarder"] - Forwarder3_write["write"] Forwarder3_read["read"] + Forwarder3_write["write"] end end end subgraph FetchUnit["fetch FetchUnit"] - FetchUnit_Fetch_Stage1["Fetch_Stage1"] - FetchUnit_resume_from_unsafe["resume_from_unsafe"] - FetchUnit_stall_exception["stall_exception"] - FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_Fetch_Stage2["Fetch_Stage2"] + FetchUnit_stall_exception["stall_exception"] + FetchUnit_resume_from_unsafe["resume_from_unsafe"] + FetchUnit_Fetch_Stage0["Fetch_Stage0"] FetchUnit_Fetch_Stage2_cond0["Fetch_Stage2_cond0"] + FetchUnit_Fetch_Stage2_cond1["Fetch_Stage2_cond1"] FetchUnit_resume_from_exception["resume_from_exception"] - FetchUnit_Fetch_Stage0["Fetch_Stage0"] + FetchUnit_Fetch_Stage1["Fetch_Stage1"] subgraph TaggedCounter["perf_fetch_utilization TaggedCounter"] TaggedCounter__incr["_incr"] end @@ -215,9 +215,9 @@ HwCounter5__incr["_incr"] end subgraph Serializer["serializer Serializer"] + Serializer_write["write"] Serializer_clean["clean"] Serializer_read["read"] - Serializer_write["write"] end subgraph ConnectTrans["serializer_connector ConnectTrans"] ConnectTrans_ConnectTrans["ConnectTrans"] @@ -251,9 +251,9 @@ end end subgraph Pipe1["decode_pipe Pipe"] - Pipe1_clean["clean"] - Pipe1_read["read"] Pipe1_write["write"] + Pipe1_read["read"] + Pipe1_clean["clean"] end subgraph DecodeStage["decode DecodeStage"] DecodeStage_DecodeStage["DecodeStage"] @@ -263,22 +263,22 @@ end end subgraph BasicFifo5["free_rf_fifo BasicFifo"] - BasicFifo5_write["write"] BasicFifo5_read["read"] + BasicFifo5_write["write"] end subgraph FRAT["FRAT FRAT"] FRAT_rename["rename"] end subgraph RRAT["RRAT RRAT"] - RRAT_commit["commit"] RRAT_peek["peek"] + RRAT_commit["commit"] end subgraph RegisterFile["RF RegisterFile"] - RegisterFile_read1["read1"] RegisterFile_perf["perf"] - RegisterFile_write["write"] RegisterFile_read2["read2"] + RegisterFile_read1["read1"] RegisterFile_free["free"] + RegisterFile_write["write"] subgraph TaggedLatencyMeasurer["perf_rf_valid_time TaggedLatencyMeasurer"] TaggedLatencyMeasurer__start["_start"] TaggedLatencyMeasurer__stop["_stop"] @@ -296,11 +296,11 @@ end subgraph ReorderBuffer["ROB ReorderBuffer"] ReorderBuffer_mark_done["mark_done"] - ReorderBuffer_put["put"] + ReorderBuffer_get_indices["get_indices"] ReorderBuffer_perf["perf"] ReorderBuffer_retire["retire"] ReorderBuffer_peek["peek"] - ReorderBuffer_get_indices["get_indices"] + ReorderBuffer_put["put"] subgraph FIFOLatencyMeasurer1["perf_rob_wait_time FIFOLatencyMeasurer"] FIFOLatencyMeasurer1__stop["_stop"] FIFOLatencyMeasurer1__start["_start"] @@ -308,8 +308,8 @@ HwExpHistogram3__add["_add"] end subgraph FIFO1["fifo FIFO"] - FIFO1_write["write"] FIFO1_read["read"] + FIFO1_write["write"] end end subgraph HwExpHistogram4["perf_rob_size HwExpHistogram"] @@ -317,12 +317,12 @@ end end subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"] - ExceptionCauseRegister_report["report"] ExceptionCauseRegister_clear["clear"] ExceptionCauseRegister_get["get"] + ExceptionCauseRegister_report["report"] subgraph BasicFifo6["fu_report_fifo BasicFifo"] - BasicFifo6_read["read"] BasicFifo6_write["write"] + BasicFifo6_read["read"] end subgraph ConnectTrans1["report_connector ConnectTrans"] ConnectTrans1_ConnectTrans["ConnectTrans"] @@ -332,8 +332,8 @@ subgraph Collector["result_collector Collector"] Collector_method["method"] subgraph Forwarder4["forwarder Forwarder"] - Forwarder4_write["write"] Forwarder4_read["read"] + Forwarder4_write["write"] end subgraph ManyToOneConnectTrans["connect ManyToOneConnectTrans"] subgraph ConnectTrans2["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -351,30 +351,30 @@ MethodProduct_method["method"] end subgraph RSFuncBlock["rs_block_0 RSFuncBlock"] - RSFuncBlock_get_result["get_result"] - RSFuncBlock_update["update"] RSFuncBlock_select["select"] + RSFuncBlock_update["update"] RSFuncBlock_insert["insert"] + RSFuncBlock_get_result["get_result"] subgraph RS["rs RS"] + RS_insert["insert"] RS_RS["RS"] - RS_select["select"] RS_RS1["RS"] RS_RS2["RS"] - RS_take["take"] - RS_insert["insert"] - RS_RS3["RS"] + RS_perf["perf"] + RS_select["select"] RS_update["update"] + RS_RS3["RS"] RS_RS4["RS"] - RS_perf["perf"] + RS_take["take"] subgraph TaggedLatencyMeasurer1["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer1__stop["_stop"] TaggedLatencyMeasurer1__start["_start"] + TaggedLatencyMeasurer1__stop["_stop"] subgraph HwExpHistogram5["histogram HwExpHistogram"] HwExpHistogram5__add["_add"] end subgraph AsyncMemoryBank1["slots AsyncMemoryBank"] - AsyncMemoryBank1_read["read"] AsyncMemoryBank1_write["write"] + AsyncMemoryBank1_read["read"] end end subgraph HwExpHistogram6["perf_num_full HwExpHistogram"] @@ -399,8 +399,8 @@ ShiftFuncUnit_accept["accept"] ShiftFuncUnit_issue["issue"] subgraph FIFO3["fifo FIFO"] - FIFO3_write["write"] FIFO3_read["read"] + FIFO3_write["write"] end end subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"] @@ -410,8 +410,8 @@ JumpBranchFuncUnit_accept["accept"] JumpBranchFuncUnit_issue["issue"] subgraph FIFO4["fifo_branch_resolved FIFO"] - FIFO4_read["read"] FIFO4_write["write"] + FIFO4_read["read"] end subgraph TaggedCounter5["perf_instr TaggedCounter"] TaggedCounter5__incr["_incr"] @@ -423,8 +423,8 @@ HwCounter8__incr["_incr"] end subgraph BasicFifo7["instr_fifo BasicFifo"] - BasicFifo7_read["read"] BasicFifo7_write["write"] + BasicFifo7_read["read"] end end subgraph WakeupSelect2["wakeup_select_2 WakeupSelect"] @@ -434,20 +434,20 @@ ExceptionFuncUnit_issue["issue"] ExceptionFuncUnit_accept["accept"] subgraph FIFO5["fifo FIFO"] - FIFO5_write["write"] FIFO5_read["read"] + FIFO5_write["write"] end end subgraph WakeupSelect3["wakeup_select_3 WakeupSelect"] WakeupSelect3_WakeupSelect["WakeupSelect"] end subgraph PrivilegedFuncUnit["func_unit_4 PrivilegedFuncUnit"] - PrivilegedFuncUnit_accept["accept"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] - PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_cond1"] PrivilegedFuncUnit_issue["issue"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_cond3"] + PrivilegedFuncUnit_accept["accept"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_cond2"] + PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_cond0"] PrivilegedFuncUnit_PrivilegedFuncUnit["PrivilegedFuncUnit"] subgraph BasicFifo8["fetch_resume_fifo BasicFifo"] BasicFifo8_write["write"] @@ -487,25 +487,25 @@ end subgraph RSFuncBlock1["rs_block_1 RSFuncBlock"] RSFuncBlock1_insert["insert"] + RSFuncBlock1_select["select"] RSFuncBlock1_get_result["get_result"] RSFuncBlock1_update["update"] - RSFuncBlock1_select["select"] subgraph FifoRS["rs FifoRS"] - FifoRS_FifoRS["FifoRS"] FifoRS_select["select"] FifoRS_insert["insert"] - FifoRS_perf["perf"] FifoRS_take["take"] FifoRS_update["update"] + FifoRS_FifoRS["FifoRS"] + FifoRS_perf["perf"] subgraph TaggedLatencyMeasurer2["perf_rs_wait_time TaggedLatencyMeasurer"] - TaggedLatencyMeasurer2__start["_start"] TaggedLatencyMeasurer2__stop["_stop"] + TaggedLatencyMeasurer2__start["_start"] subgraph HwExpHistogram7["histogram HwExpHistogram"] HwExpHistogram7__add["_add"] end subgraph AsyncMemoryBank2["slots AsyncMemoryBank"] - AsyncMemoryBank2_read["read"] AsyncMemoryBank2_write["write"] + AsyncMemoryBank2_read["read"] end end subgraph HwExpHistogram8["perf_num_full HwExpHistogram"] @@ -515,19 +515,19 @@ subgraph LSUDummy["func_unit_0 LSUDummy"] LSUDummy_LSUDummy["LSUDummy"] LSUDummy_accept_cond1["accept_cond1"] - LSUDummy_issue["issue"] LSUDummy_LSUDummy1["LSUDummy"] + LSUDummy_issue["issue"] LSUDummy_accept_cond0["accept_cond0"] - LSUDummy_accept["accept"] LSUDummy_LSUDummy2["LSUDummy"] + LSUDummy_accept["accept"] subgraph LSURequester["requester LSURequester"] - LSURequester_accept["accept"] LSURequester_issue["issue"] - LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond1["accept_cond1"] - LSURequester_issue_cond0["issue_cond0"] LSURequester_issue_cond1["issue_cond1"] + LSURequester_issue_cond2["issue_cond2"] LSURequester_accept_cond0["accept_cond0"] + LSURequester_issue_cond0["issue_cond0"] + LSURequester_accept["accept"] subgraph BasicFifo9["args_fifo BasicFifo"] BasicFifo9_read["read"] BasicFifo9_write["write"] @@ -538,16 +538,16 @@ Forwarder6_write["write"] end subgraph FIFO6["results_noop FIFO"] - FIFO6_read["read"] FIFO6_write["write"] + FIFO6_read["read"] end subgraph FIFO7["issued FIFO"] - FIFO7_read["read"] FIFO7_write["write"] + FIFO7_read["read"] end subgraph FIFO8["issued_noop FIFO"] - FIFO8_read["read"] FIFO8_write["write"] + FIFO8_read["read"] end end subgraph WakeupSelect5["wakeup_select_0 WakeupSelect"] @@ -556,8 +556,8 @@ subgraph Collector2["collector Collector"] Collector2_method["method"] subgraph Forwarder7["forwarder Forwarder"] - Forwarder7_read["read"] Forwarder7_write["write"] + Forwarder7_read["read"] end subgraph ManyToOneConnectTrans2["connect ManyToOneConnectTrans"] subgraph ConnectTrans10["ManyToOneConnectTrans_input_0 ConnectTrans"] @@ -567,13 +567,13 @@ end end subgraph CSRUnit["rs_block_2 CSRUnit"] - CSRUnit_select["select"] CSRUnit_CSRUnit["CSRUnit"] + CSRUnit_get_result["get_result"] CSRUnit_update["update"] CSRUnit_insert["insert"] - CSRUnit_get_result["get_result"] - CSRUnit_CSRUnit1["CSRUnit"] CSRUnit_fetch_resume["fetch_resume"] + CSRUnit_select["select"] + CSRUnit_CSRUnit1["CSRUnit"] end end subgraph ResultAnnouncement["announcement ResultAnnouncement"] @@ -626,13 +626,13 @@ end end subgraph AliasedCSR["mstatus AliasedCSR"] - AliasedCSR__fu_read["_fu_read"] AliasedCSR__fu_write["_fu_write"] + AliasedCSR__fu_read["_fu_read"] end subgraph CSRRegister6["mcause CSRRegister"] - CSRRegister6__internal_fu_write["_internal_fu_write"] CSRRegister6__internal_fu_read["_internal_fu_read"] CSRRegister6_write["write"] + CSRRegister6__internal_fu_write["_internal_fu_write"] subgraph MethodMap12["fu_write_map MethodMap"] MethodMap12_method["method"] end @@ -644,9 +644,9 @@ end end subgraph CSRRegister7["mtvec CSRRegister"] - CSRRegister7__internal_fu_write["_internal_fu_write"] - CSRRegister7_read["read"] CSRRegister7__internal_fu_read["_internal_fu_read"] + CSRRegister7_read["read"] + CSRRegister7__internal_fu_write["_internal_fu_write"] subgraph MethodMap14["fu_write_map MethodMap"] MethodMap14_method["method"] end @@ -658,10 +658,10 @@ end end subgraph CSRRegister8["mepc CSRRegister"] - CSRRegister8_write["write"] CSRRegister8_read["read"] - CSRRegister8__internal_fu_write["_internal_fu_write"] CSRRegister8__internal_fu_read["_internal_fu_read"] + CSRRegister8__internal_fu_write["_internal_fu_write"] + CSRRegister8_write["write"] subgraph MethodMap16["fu_write_map MethodMap"] MethodMap16_method["method"] end @@ -676,17 +676,17 @@ subgraph DoubleCounterCSR["csr_cycle DoubleCounterCSR"] DoubleCounterCSR_increment["increment"] subgraph CSRRegister9["register_low CSRRegister"] + CSRRegister9_read["read"] CSRRegister9_write["write"] CSRRegister9__internal_fu_read["_internal_fu_read"] - CSRRegister9_read["read"] subgraph MethodMap19["fu_read_map MethodMap"] MethodMap19_method["method"] end end subgraph CSRRegister10["register_high CSRRegister"] + CSRRegister10_read["read"] CSRRegister10_write["write"] CSRRegister10__internal_fu_read["_internal_fu_read"] - CSRRegister10_read["read"] subgraph MethodMap21["fu_read_map MethodMap"] MethodMap21_method["method"] end @@ -695,17 +695,17 @@ subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"] DoubleCounterCSR1_increment["increment"] subgraph CSRRegister11["register_low CSRRegister"] - CSRRegister11_write["write"] CSRRegister11__internal_fu_read["_internal_fu_read"] + CSRRegister11_write["write"] CSRRegister11_read["read"] subgraph MethodMap23["fu_read_map MethodMap"] MethodMap23_method["method"] end end subgraph CSRRegister12["register_high CSRRegister"] + CSRRegister12_write["write"] CSRRegister12__internal_fu_read["_internal_fu_read"] CSRRegister12_read["read"] - CSRRegister12_write["write"] subgraph MethodMap25["fu_read_map MethodMap"] MethodMap25_method["method"] end @@ -714,16 +714,16 @@ end subgraph InternalInterruptController["interrupt_controller InternalInterruptController"] InternalInterruptController_InternalInterruptController["InternalInterruptController"] - InternalInterruptController_entry["entry"] - InternalInterruptController_mret["mret"] InternalInterruptController_InternalInterruptController1["InternalInterruptController"] InternalInterruptController_InternalInterruptController2["InternalInterruptController"] InternalInterruptController_interrupt_cause["interrupt_cause"] + InternalInterruptController_mret["mret"] + InternalInterruptController_entry["entry"] subgraph CSRRegister13["mstatus_mie CSRRegister"] CSRRegister13_read["read"] - CSRRegister13__internal_fu_write["_internal_fu_write"] CSRRegister13_write["write"] CSRRegister13__internal_fu_read["_internal_fu_read"] + CSRRegister13__internal_fu_write["_internal_fu_write"] subgraph MethodMap26["fu_write_map MethodMap"] MethodMap26_method["method"] end @@ -735,10 +735,10 @@ end end subgraph CSRRegister14["mstatus_mpie CSRRegister"] + CSRRegister14_write["write"] + CSRRegister14__internal_fu_read["_internal_fu_read"] CSRRegister14_read["read"] CSRRegister14__internal_fu_write["_internal_fu_write"] - CSRRegister14__internal_fu_read["_internal_fu_read"] - CSRRegister14_write["write"] subgraph MethodMap28["fu_write_map MethodMap"] MethodMap28_method["method"] end @@ -763,9 +763,9 @@ end end subgraph CSRRegister16["mie CSRRegister"] - CSRRegister16__internal_fu_read["_internal_fu_read"] - CSRRegister16__internal_fu_write["_internal_fu_write"] CSRRegister16_read["read"] + CSRRegister16__internal_fu_write["_internal_fu_write"] + CSRRegister16__internal_fu_read["_internal_fu_read"] subgraph MethodMap32["fu_write_map MethodMap"] MethodMap32_method["method"] end @@ -777,11 +777,11 @@ end end subgraph CSRRegister17["mip CSRRegister"] - CSRRegister17_write["write"] - CSRRegister17_read["read"] CSRRegister17__internal_fu_read["_internal_fu_read"] + CSRRegister17_read["read"] CSRRegister17_read_comb["read_comb"] CSRRegister17__internal_fu_write["_internal_fu_write"] + CSRRegister17_write["write"] subgraph MethodMap34["fu_write_map MethodMap"] MethodMap34_method["method"] end @@ -802,8 +802,8 @@ end subgraph Scheduler["scheduler Scheduler"] subgraph FIFO9["alloc_rename_buf FIFO"] - FIFO9_write["write"] FIFO9_read["read"] + FIFO9_write["write"] end subgraph RegAllocation["reg_alloc RegAllocation"] RegAllocation_RegAllocation["RegAllocation"] @@ -816,8 +816,8 @@ Renaming_Renaming["Renaming"] end subgraph FIFO10["reg_alloc_out_buf FIFO"] - FIFO10_read["read"] FIFO10_write["write"] + FIFO10_read["read"] end subgraph ROBAllocation["rob_alloc ROBAllocation"] ROBAllocation_ROBAllocation["ROBAllocation"] @@ -856,20 +856,20 @@ ConnectTrans13_ConnectTrans["ConnectTrans"] end subgraph Retirement["retirement Retirement"] + Retirement_Retirement_cond1["Retirement_cond1"] + Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement["Retirement"] + Retirement_precommit["precommit"] + Retirement_core_state["core_state"] Retirement_Retirement1["Retirement"] - Retirement_Retirement_cond0["Retirement_cond0"] Retirement_Retirement2["Retirement"] Retirement_Retirement3["Retirement"] - Retirement_core_state["core_state"] - Retirement_Retirement_cond1["Retirement_cond1"] - Retirement_precommit["precommit"] subgraph DoubleCounterCSR2["instret_csr DoubleCounterCSR"] DoubleCounterCSR2_increment["increment"] subgraph CSRRegister18["register_low CSRRegister"] - CSRRegister18_read["read"] CSRRegister18__internal_fu_read["_internal_fu_read"] CSRRegister18_write["write"] + CSRRegister18_read["read"] subgraph MethodMap37["fu_read_map MethodMap"] MethodMap37_method["method"] end @@ -887,8 +887,8 @@ HwCounter9__incr["_incr"] end subgraph FIFOLatencyMeasurer2["perf_trap_latency FIFOLatencyMeasurer"] - FIFOLatencyMeasurer2__stop["_stop"] FIFOLatencyMeasurer2__start["_start"] + FIFOLatencyMeasurer2__stop["_stop"] subgraph HwExpHistogram9["histogram HwExpHistogram"] HwExpHistogram9__add["_add"] end @@ -901,27 +901,27 @@ end end subgraph TransactionManager["transaction_manager TransactionManager"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond1["ConnectTrans_accept_cond0_accept_cond1"] - TransactionManager_Retirement_cond0_Retirement["Retirement_cond0_Retirement"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1["PrivilegedFuncUnit_PrivilegedFuncUnit_cond1"] - TransactionManager_Retirement_cond1_Retirement["Retirement_cond1_Retirement"] - TransactionManager_ConnectTrans_accept_cond1["ConnectTrans_accept_cond1"] - TransactionManager_LSUDummy_issue_cond0["LSUDummy_issue_cond0"] + TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] + TransactionManager_Retirement_Retirement_cond0["Retirement_Retirement_cond0"] + TransactionManager_accept_cond1_ConnectTrans["accept_cond1_ConnectTrans"] TransactionManager_issue_cond1_LSUDummy["issue_cond1_LSUDummy"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3["PrivilegedFuncUnit_PrivilegedFuncUnit_cond3"] - TransactionManager_ROBAllocation_Renaming["ROBAllocation_Renaming"] + TransactionManager_issue_cond0_LSUDummy["issue_cond0_LSUDummy"] TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2["Fetch_Stage2_cond1_Fetch_Stage2"] - TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2["Fetch_Stage2_cond0_Fetch_Stage2"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_ConnectTrans_accept_cond0_accept_cond1["ConnectTrans_accept_cond0_accept_cond1"] TransactionManager_issue_cond2_LSUDummy["issue_cond2_LSUDummy"] - TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2["PrivilegedFuncUnit_PrivilegedFuncUnit_cond2"] TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0["PrivilegedFuncUnit_PrivilegedFuncUnit_cond0"] - TransactionManager_ConnectTrans_accept_cond0_accept_cond0["ConnectTrans_accept_cond0_accept_cond0"] + TransactionManager_Retirement_Retirement_cond1["Retirement_Retirement_cond1"] + TransactionManager_Renaming_ROBAllocation["Renaming_ROBAllocation"] end end Core_InitFreeRFFifo --> BasicFifo5_write -Retirement_Retirement --> BasicFifo5_write -TransactionManager_Retirement_cond1_Retirement --> BasicFifo5_write -TransactionManager_Retirement_cond0_Retirement --> BasicFifo5_write +Retirement_Retirement3 --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond0 --> BasicFifo5_write +TransactionManager_Retirement_Retirement_cond1 --> BasicFifo5_write WishboneMaster_WishboneMaster --> Forwarder_write WishboneMaster1_WishboneMaster --> Forwarder1_write FIFO4_read --> CoreFrontend_DiscardBranchVerify @@ -980,31 +980,31 @@ GenericCSRRegisters_GenericCSRRegisters --> CSRRegister11_write CSRRegister12_read --> GenericCSRRegisters_GenericCSRRegisters GenericCSRRegisters_GenericCSRRegisters --> CSRRegister12_write +CSRRegister13_read --> InternalInterruptController_InternalInterruptController CSRRegister13_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister13_read --> InternalInterruptController_InternalInterruptController2 -CSRRegister16_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister17_read --> InternalInterruptController_InternalInterruptController1 -CSRRegister17_read_comb --> InternalInterruptController_InternalInterruptController -InternalInterruptController_InternalInterruptController --> CSRRegister17_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister13_write -InternalInterruptController_InternalInterruptController2 --> CSRRegister14_write -CSRRegister14_read --> InternalInterruptController_InternalInterruptController2 +CSRRegister16_read --> InternalInterruptController_InternalInterruptController +CSRRegister17_read --> InternalInterruptController_InternalInterruptController +CSRRegister17_read_comb --> InternalInterruptController_InternalInterruptController2 +InternalInterruptController_InternalInterruptController2 --> CSRRegister17_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister13_write +InternalInterruptController_InternalInterruptController1 --> CSRRegister14_write +CSRRegister14_read --> InternalInterruptController_InternalInterruptController1 MethodProduct1_method --> RegAllocation_RegAllocation Pipe1_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation <--> CoreInstructionCounter_increment BasicFifo5_read --> RegAllocation_RegAllocation RegAllocation_RegAllocation --> FIFO9_write +FIFO10_read --> RSSelection_RSSelection1 FIFO10_read --> RSSelection_RSSelection FIFO10_read --> RSSelection_RSSelection2 -FIFO10_read --> RSSelection_RSSelection1 -RSFuncBlock_select --> RSSelection_RSSelection -RS_select --> RSSelection_RSSelection +RSFuncBlock_select --> RSSelection_RSSelection1 +RS_select --> RSSelection_RSSelection1 +RSSelection_RSSelection1 --> FIFO11_write RSSelection_RSSelection --> FIFO11_write RSSelection_RSSelection2 --> FIFO11_write -RSSelection_RSSelection1 --> FIFO11_write -RSFuncBlock1_select --> RSSelection_RSSelection2 -FifoRS_select --> RSSelection_RSSelection2 -RSSelection_RSSelection1 <--> CSRUnit_select +RSFuncBlock1_select --> RSSelection_RSSelection +FifoRS_select --> RSSelection_RSSelection +RSSelection_RSSelection2 <--> CSRUnit_select FIFO11_read --> RSInsertion_RSInsertion RegisterFile_read1 --> RSInsertion_RSInsertion RegisterFile_read2 --> RSInsertion_RSInsertion @@ -1046,7 +1046,7 @@ ResultAnnouncement_ResultAnnouncement --> FifoRS_update ResultAnnouncement_ResultAnnouncement --> CSRUnit_update RS_perf --> HwExpHistogram6__add -RS_RS2 --> WakeupSelect_WakeupSelect +RS_RS4 --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect_WakeupSelect RS_take --> WakeupSelect1_WakeupSelect RS_take --> WakeupSelect2_WakeupSelect @@ -1078,17 +1078,17 @@ WakeupSelect2_WakeupSelect <--> CoreFrontend_target_pred_req WakeupSelect2_WakeupSelect --> BasicFifo7_write WakeupSelect2_WakeupSelect --> TaggedCounter5__incr -RS_RS4 --> WakeupSelect3_WakeupSelect +RS_RS3 --> WakeupSelect3_WakeupSelect WakeupSelect3_WakeupSelect --> ExceptionFuncUnit_issue WakeupSelect3_WakeupSelect --> BasicFifo6_write ConnectTrans7_ConnectTrans --> BasicFifo6_write ConnectTrans9_ConnectTrans --> BasicFifo6_write ConnectTrans4_ConnectTrans --> BasicFifo6_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> BasicFifo6_write -TransactionManager_ConnectTrans_accept_cond1 --> BasicFifo6_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> BasicFifo6_write +TransactionManager_accept_cond1_ConnectTrans --> BasicFifo6_write WakeupSelect3_WakeupSelect --> FIFO5_write -RS_RS3 --> WakeupSelect4_WakeupSelect +RS_RS2 --> WakeupSelect4_WakeupSelect WakeupSelect4_WakeupSelect --> PrivilegedFuncUnit_issue ConnectTrans5_ConnectTrans --> Forwarder5_write ConnectTrans6_ConnectTrans --> Forwarder5_write @@ -1111,36 +1111,36 @@ CSRRegister8_read --> ConnectTrans9_ConnectTrans ConnectTrans9_ConnectTrans --> BasicFifo8_write FifoRS_perf --> HwExpHistogram8__add -Forwarder6_read --> LSUDummy_LSUDummy +Forwarder6_read --> LSUDummy_LSUDummy1 Forwarder6_read --> TransactionManager_issue_cond2_LSUDummy -Forwarder6_read --> TransactionManager_LSUDummy_issue_cond0 Forwarder6_read --> TransactionManager_issue_cond1_LSUDummy -LSUDummy_LSUDummy --> FIFO6_write +Forwarder6_read --> TransactionManager_issue_cond0_LSUDummy +LSUDummy_LSUDummy1 --> FIFO6_write WakeupSelect5_WakeupSelect --> FIFO6_write TransactionManager_issue_cond2_LSUDummy --> FIFO6_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO6_write TransactionManager_issue_cond1_LSUDummy --> FIFO6_write -LSUDummy_LSUDummy --> FIFO8_write +TransactionManager_issue_cond0_LSUDummy --> FIFO6_write +LSUDummy_LSUDummy1 --> FIFO8_write WakeupSelect5_WakeupSelect --> FIFO8_write TransactionManager_issue_cond2_LSUDummy --> FIFO8_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO8_write TransactionManager_issue_cond1_LSUDummy --> FIFO8_write -Retirement_precommit --> LSUDummy_LSUDummy1 +TransactionManager_issue_cond0_LSUDummy --> FIFO8_write +Retirement_precommit --> LSUDummy_LSUDummy Retirement_precommit --> CSRUnit_CSRUnit -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -ReorderBuffer_peek --> LSUDummy_LSUDummy1 +Retirement_precommit --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +ReorderBuffer_peek --> LSUDummy_LSUDummy ReorderBuffer_peek --> CSRUnit_CSRUnit ReorderBuffer_peek --> Retirement_Retirement2 -ReorderBuffer_peek --> Retirement_Retirement -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +ReorderBuffer_peek --> Retirement_Retirement3 +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond0 +ReorderBuffer_peek --> TransactionManager_Retirement_Retirement_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -ReorderBuffer_peek --> TransactionManager_Retirement_cond1_Retirement -ReorderBuffer_peek --> TransactionManager_Retirement_cond0_Retirement +ReorderBuffer_peek --> TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 FifoRS_FifoRS --> WakeupSelect5_WakeupSelect FifoRS_take --> WakeupSelect5_WakeupSelect WakeupSelect5_WakeupSelect --> TaggedLatencyMeasurer2__stop @@ -1228,168 +1228,168 @@ Forwarder7_read --> ConnectTrans3_ConnectTrans CSRUnit_get_result --> ConnectTrans4_ConnectTrans ExceptionCauseRegister_get --> Retirement_Retirement2 -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond1_Retirement -ExceptionCauseRegister_get --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond1_Retirement <--> ReorderBuffer_retire -TransactionManager_Retirement_cond0_Retirement <--> ReorderBuffer_retire -Retirement_Retirement <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer1__stop -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer1__stop -FIFO1_read --> Retirement_Retirement -FIFO1_read --> TransactionManager_Retirement_cond1_Retirement -FIFO1_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram3__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram3__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram3__add -CoreInstructionCounter_decrement --> Retirement_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond1_Retirement -CoreInstructionCounter_decrement --> TransactionManager_Retirement_cond0_Retirement -RRAT_peek --> Retirement_Retirement -RRAT_peek --> TransactionManager_Retirement_cond1_Retirement -Retirement_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond1_Retirement --> RegisterFile_free -TransactionManager_Retirement_cond0_Retirement --> RegisterFile_free -Retirement_Retirement --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond1_Retirement --> TaggedLatencyMeasurer__stop -TransactionManager_Retirement_cond0_Retirement --> TaggedLatencyMeasurer__stop -AsyncMemoryBank_read --> Retirement_Retirement -AsyncMemoryBank_read --> TransactionManager_Retirement_cond1_Retirement -AsyncMemoryBank_read --> TransactionManager_Retirement_cond0_Retirement -Retirement_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond1_Retirement --> HwExpHistogram1__add -TransactionManager_Retirement_cond0_Retirement --> HwExpHistogram1__add -Retirement_Retirement --> FRAT_rename -TransactionManager_ROBAllocation_Renaming --> FRAT_rename -TransactionManager_Retirement_cond1_Retirement --> FRAT_rename -Retirement_Retirement1 <--> FIFOLatencyMeasurer2__stop -FIFO12_read --> Retirement_Retirement1 -Retirement_Retirement1 --> HwExpHistogram9__add -CSRRegister7_read --> Retirement_Retirement1 -Retirement_Retirement1 --> FetchUnit_resume_from_exception -Retirement_Retirement1 <--> ExceptionCauseRegister_clear -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond1 <--> ConnectTrans10_ConnectTrans -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> Forwarder7_write -TransactionManager_ConnectTrans_accept_cond1 --> Forwarder7_write -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond1 -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 -TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSUDummy_accept_cond0 -LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 -WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -Serializer1_Serializer --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 -Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSURequester_accept_cond1 -WishboneMasterAdapter1_get_read_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -Serializer1_Serializer3 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 -TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 -TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 -TransactionManager_LSUDummy_issue_cond0 <--> LSUDummy_LSUDummy2 -TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 -TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue -TransactionManager_LSUDummy_issue_cond0 --> LSURequester_issue -TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue -TransactionManager_issue_cond2_LSUDummy --> BasicFifo9_write -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo9_write -TransactionManager_issue_cond1_LSUDummy --> BasicFifo9_write -TransactionManager_issue_cond2_LSUDummy --> FIFO7_write -TransactionManager_LSUDummy_issue_cond0 --> FIFO7_write -TransactionManager_issue_cond1_LSUDummy --> FIFO7_write -TransactionManager_ConnectTrans_accept_cond1 <--> LSUDummy_accept_cond1 -FIFO6_read --> TransactionManager_ConnectTrans_accept_cond1 -FIFO8_read --> TransactionManager_ConnectTrans_accept_cond1 -TransactionManager_ROBAllocation_Renaming <--> ROBAllocation_ROBAllocation -Connect_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> ReorderBuffer_put -TransactionManager_ROBAllocation_Renaming <--> FIFOLatencyMeasurer1__start -TransactionManager_ROBAllocation_Renaming --> FIFO1_write -TransactionManager_ROBAllocation_Renaming --> FIFO10_write -TransactionManager_ROBAllocation_Renaming <--> Renaming_Renaming -FIFO9_read --> TransactionManager_ROBAllocation_Renaming -TransactionManager_ROBAllocation_Renaming --> Connect_write -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond0 +ExceptionCauseRegister_get --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond0 <--> ReorderBuffer_retire +TransactionManager_Retirement_Retirement_cond1 <--> ReorderBuffer_retire +Retirement_Retirement3 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer1__stop +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer1__stop +FIFO1_read --> Retirement_Retirement3 +FIFO1_read --> TransactionManager_Retirement_Retirement_cond0 +FIFO1_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram3__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram3__add +CoreInstructionCounter_decrement --> Retirement_Retirement3 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond0 +CoreInstructionCounter_decrement --> TransactionManager_Retirement_Retirement_cond1 +RRAT_peek --> Retirement_Retirement3 +RRAT_peek --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond0 --> RegisterFile_free +TransactionManager_Retirement_Retirement_cond1 --> RegisterFile_free +Retirement_Retirement3 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond0 --> TaggedLatencyMeasurer__stop +TransactionManager_Retirement_Retirement_cond1 --> TaggedLatencyMeasurer__stop +AsyncMemoryBank_read --> Retirement_Retirement3 +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond0 +AsyncMemoryBank_read --> TransactionManager_Retirement_Retirement_cond1 +Retirement_Retirement3 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond0 --> HwExpHistogram1__add +TransactionManager_Retirement_Retirement_cond1 --> HwExpHistogram1__add +Retirement_Retirement3 --> FRAT_rename +TransactionManager_Retirement_Retirement_cond1 --> FRAT_rename +TransactionManager_Renaming_ROBAllocation --> FRAT_rename +Retirement_Retirement <--> FIFOLatencyMeasurer2__stop +FIFO12_read --> Retirement_Retirement +Retirement_Retirement --> HwExpHistogram9__add +CSRRegister7_read --> Retirement_Retirement +Retirement_Retirement --> FetchUnit_resume_from_exception +Retirement_Retirement <--> ExceptionCauseRegister_clear +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 --> TaggedCounter6__incr TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 --> TaggedCounter6__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 --> TaggedCounter6__incr +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement1 +TransactionManager_Retirement_Retirement_cond0 <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_Retirement_cond1 <--> FIFOLatencyMeasurer2__start +TransactionManager_Retirement_Retirement_cond0 --> FIFO12_write +TransactionManager_Retirement_Retirement_cond1 --> FIFO12_write +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond0 +InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_Retirement_cond1 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister6_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister6_write +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond1 --> CSRRegister8_write +TransactionManager_Retirement_Retirement_cond0 <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond1 <--> InternalInterruptController_entry +TransactionManager_Retirement_Retirement_cond0 <--> Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> RRAT_commit +TransactionManager_Retirement_Retirement_cond0 <--> DoubleCounterCSR2_increment +CSRRegister18_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister18_write +CSRRegister19_read --> TransactionManager_Retirement_Retirement_cond0 +TransactionManager_Retirement_Retirement_cond0 --> CSRRegister19_write +TransactionManager_Retirement_Retirement_cond0 <--> HwCounter9__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr +TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> Semaphore_release -Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> Semaphore_release Pipe_read --> TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode +Pipe_read --> TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Predecoder_predecode -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> Predecoder_predecode TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> PredictionChecker_check -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> PredictionChecker_check TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter1__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter1__incr TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter2__incr -TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter2__incr TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter3__incr -TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond3 -TransactionManager_LSUDummy_issue_cond0 <--> LSURequester_issue_cond0 -TransactionManager_LSUDummy_issue_cond0 --> WishboneMasterAdapter1_request_write -TransactionManager_LSUDummy_issue_cond0 --> Serializer1_Serializer1 -TransactionManager_LSUDummy_issue_cond0 --> BasicFifo1_write -TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write -TransactionManager_LSUDummy_issue_cond0 --> WishboneMaster1_request -TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement_cond1 -TransactionManager_Retirement_cond1_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement3 -TransactionManager_Retirement_cond1_Retirement <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_cond0_Retirement <--> FIFOLatencyMeasurer2__start -TransactionManager_Retirement_cond1_Retirement --> FIFO12_write -TransactionManager_Retirement_cond0_Retirement --> FIFO12_write -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond1_Retirement -InternalInterruptController_interrupt_cause --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond1_Retirement --> CSRRegister6_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister6_write -TransactionManager_Retirement_cond1_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond0_Retirement --> CSRRegister8_write -TransactionManager_Retirement_cond1_Retirement <--> InternalInterruptController_entry -TransactionManager_Retirement_cond0_Retirement <--> InternalInterruptController_entry +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 --> TaggedCounter3__incr +TransactionManager_issue_cond2_LSUDummy <--> LSURequester_issue_cond2 +TransactionManager_issue_cond2_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond1_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond0_LSUDummy <--> LSUDummy_LSUDummy2 +TransactionManager_issue_cond2_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond1_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond0_LSUDummy --> LSURequester_issue +TransactionManager_issue_cond2_LSUDummy --> BasicFifo9_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo9_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo9_write +TransactionManager_issue_cond2_LSUDummy --> FIFO7_write +TransactionManager_issue_cond1_LSUDummy --> FIFO7_write +TransactionManager_issue_cond0_LSUDummy --> FIFO7_write +TransactionManager_Retirement_Retirement_cond1 <--> Retirement_Retirement_cond1 +TransactionManager_Fetch_Stage2_cond1_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond1 TransactionManager_issue_cond1_LSUDummy <--> LSURequester_issue_cond1 TransactionManager_issue_cond1_LSUDummy --> WishboneMasterAdapter1_request_read TransactionManager_issue_cond1_LSUDummy --> Serializer1_Serializer2 -TransactionManager_Retirement_cond0_Retirement <--> Retirement_Retirement_cond0 -TransactionManager_Retirement_cond0_Retirement --> RRAT_commit -TransactionManager_Retirement_cond0_Retirement <--> DoubleCounterCSR2_increment -CSRRegister18_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister18_write -CSRRegister19_read --> TransactionManager_Retirement_cond0_Retirement -TransactionManager_Retirement_cond0_Retirement --> CSRRegister19_write -TransactionManager_Retirement_cond0_Retirement <--> HwCounter9__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> FetchUnit_Fetch_Stage2_cond0 -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 <--> HwCounter5__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> TaggedCounter__incr -TransactionManager_Fetch_Stage2_cond0_Fetch_Stage2 --> Serializer_write +TransactionManager_issue_cond1_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond0_LSUDummy --> BasicFifo1_write +TransactionManager_issue_cond1_LSUDummy --> WishboneMaster1_request +TransactionManager_issue_cond0_LSUDummy --> WishboneMaster1_request +TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> ConnectTrans10_ConnectTrans +TransactionManager_accept_cond1_ConnectTrans <--> ConnectTrans10_ConnectTrans +TransactionManager_ConnectTrans_accept_cond0_accept_cond1 --> Forwarder7_write +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 --> Forwarder7_write +TransactionManager_accept_cond1_ConnectTrans --> Forwarder7_write +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +LSUDummy_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +LSUDummy_accept --> TransactionManager_accept_cond1_ConnectTrans +TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSUDummy_accept_cond0 +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSUDummy_accept_cond0 +LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +LSURequester_accept --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +BasicFifo9_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +FIFO7_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_ConnectTrans_accept_cond0_accept_cond1 <--> LSURequester_accept_cond1 +WishboneMasterAdapter1_get_read_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +Serializer1_Serializer1 --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +BasicFifo1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +WishboneMaster1_result --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond1 +Forwarder1_read --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_Renaming_ROBAllocation <--> Renaming_Renaming +FIFO9_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> Connect_write +TransactionManager_Renaming_ROBAllocation <--> ROBAllocation_ROBAllocation +Connect_read --> TransactionManager_Renaming_ROBAllocation +TransactionManager_Renaming_ROBAllocation --> ReorderBuffer_put +TransactionManager_Renaming_ROBAllocation <--> FIFOLatencyMeasurer1__start +TransactionManager_Renaming_ROBAllocation --> FIFO1_write +TransactionManager_Renaming_ROBAllocation --> FIFO10_write +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond1 <--> ICache_flush +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond2 +TransactionManager_ConnectTrans_accept_cond0_accept_cond0 <--> LSURequester_accept_cond0 +WishboneMasterAdapter1_get_write_response --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +Serializer1_Serializer --> TransactionManager_ConnectTrans_accept_cond0_accept_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 +TransactionManager_PrivilegedFuncUnit_PrivilegedFuncUnit_cond0 <--> InternalInterruptController_mret +TransactionManager_accept_cond1_ConnectTrans <--> LSUDummy_accept_cond1 +FIFO6_read --> TransactionManager_accept_cond1_ConnectTrans +FIFO8_read --> TransactionManager_accept_cond1_ConnectTrans +TransactionManager_issue_cond0_LSUDummy <--> LSURequester_issue_cond0 +TransactionManager_issue_cond0_LSUDummy --> WishboneMasterAdapter1_request_write +TransactionManager_issue_cond0_LSUDummy --> Serializer1_Serializer3 @@ -1400,7 +1400,7 @@

© Copyright Kuźnia Rdzeni, 2024. - Last updated on 14:02 2024-07-17. + Last updated on 12:18 2024-08-11.

diff --git a/components/icache.html b/components/icache.html index 81017b38a..7db8284b9 100644 --- a/components/icache.html +++ b/components/icache.html @@ -131,7 +131,7 @@

Address mapping example

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diff --git a/coreblocks.arch.html b/coreblocks.arch.html index ee8d2665a..2d34b4e2e 100644 --- a/coreblocks.arch.html +++ b/coreblocks.arch.html @@ -3776,7 +3776,7 @@

Submodules

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diff --git a/coreblocks.backend.html b/coreblocks.backend.html index 15abea1be..20ae8fe03 100644 --- a/coreblocks.backend.html +++ b/coreblocks.backend.html @@ -165,7 +165,7 @@

Submodules

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diff --git a/coreblocks.cache.html b/coreblocks.cache.html index b260f8569..8e73a81ef 100644 --- a/coreblocks.cache.html +++ b/coreblocks.cache.html @@ -241,7 +241,7 @@

Submodules

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diff --git a/coreblocks.core_structs.html b/coreblocks.core_structs.html index 8f45f1f8c..c48ff23da 100644 --- a/coreblocks.core_structs.html +++ b/coreblocks.core_structs.html @@ -157,7 +157,7 @@

Submodules

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diff --git a/coreblocks.frontend.decoder.html b/coreblocks.frontend.decoder.html index ffdfdbab2..b8cd6e897 100644 --- a/coreblocks.frontend.decoder.html +++ b/coreblocks.frontend.decoder.html @@ -313,7 +313,7 @@

Submodules

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diff --git a/coreblocks.frontend.fetch.html b/coreblocks.frontend.fetch.html index 07593d8d0..dfb501113 100644 --- a/coreblocks.frontend.fetch.html +++ b/coreblocks.frontend.fetch.html @@ -210,7 +210,7 @@

Submodules

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diff --git a/coreblocks.frontend.html b/coreblocks.frontend.html index c154fda68..b1e64c319 100644 --- a/coreblocks.frontend.html +++ b/coreblocks.frontend.html @@ -187,7 +187,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.html b/coreblocks.func_blocks.fu.html index 8764f6111..f6728bff6 100644 --- a/coreblocks.func_blocks.fu.html +++ b/coreblocks.func_blocks.fu.html @@ -886,7 +886,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.lsu.html b/coreblocks.func_blocks.fu.lsu.html index 40bb83f23..4ee52a0a1 100644 --- a/coreblocks.func_blocks.fu.lsu.html +++ b/coreblocks.func_blocks.fu.lsu.html @@ -290,7 +290,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.fu.unsigned_multiplication.html b/coreblocks.func_blocks.fu.unsigned_multiplication.html index 4ece26eab..1c7f542a2 100644 --- a/coreblocks.func_blocks.fu.unsigned_multiplication.html +++ b/coreblocks.func_blocks.fu.unsigned_multiplication.html @@ -260,7 +260,7 @@

Submodules

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diff --git a/coreblocks.func_blocks.html b/coreblocks.func_blocks.html index 1b5d5038f..30289e3b7 100644 --- a/coreblocks.func_blocks.html +++ b/coreblocks.func_blocks.html @@ -150,7 +150,7 @@

Subpackages

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diff --git a/coreblocks.func_blocks.interface.html b/coreblocks.func_blocks.interface.html index aea5e916c..c9663da12 100644 --- a/coreblocks.func_blocks.interface.html +++ b/coreblocks.func_blocks.interface.html @@ -164,7 +164,7 @@

Submodules

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diff --git a/coreblocks.html b/coreblocks.html index 2839dc398..65979d070 100644 --- a/coreblocks.html +++ b/coreblocks.html @@ -268,7 +268,7 @@

Submodules

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diff --git a/coreblocks.params.html b/coreblocks.params.html index 6bada4bc1..6490311cf 100644 --- a/coreblocks.params.html +++ b/coreblocks.params.html @@ -781,7 +781,7 @@

Submodules

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diff --git a/coreblocks.peripherals.html b/coreblocks.peripherals.html index b28989e4b..689542941 100644 --- a/coreblocks.peripherals.html +++ b/coreblocks.peripherals.html @@ -746,7 +746,7 @@

Submodules

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diff --git a/coreblocks.priv.csr.html b/coreblocks.priv.csr.html index 5c95973d9..8a760855b 100644 --- a/coreblocks.priv.csr.html +++ b/coreblocks.priv.csr.html @@ -301,7 +301,7 @@

Submodules

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diff --git a/coreblocks.priv.html b/coreblocks.priv.html index c420edc43..9be32f7d5 100644 --- a/coreblocks.priv.html +++ b/coreblocks.priv.html @@ -124,7 +124,7 @@

Subpackages

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diff --git a/coreblocks.priv.traps.html b/coreblocks.priv.traps.html index 229858154..eb863fd7e 100644 --- a/coreblocks.priv.traps.html +++ b/coreblocks.priv.traps.html @@ -205,7 +205,7 @@

Submodules

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diff --git a/coreblocks.scheduler.html b/coreblocks.scheduler.html index 451c4de06..60a262e02 100644 --- a/coreblocks.scheduler.html +++ b/coreblocks.scheduler.html @@ -191,7 +191,7 @@

Submodules

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diff --git a/current-graph.html b/current-graph.html index 577c1e080..49596d603 100644 --- a/current-graph.html +++ b/current-graph.html @@ -91,9 +91,9 @@

Full transaction-method graph

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diff --git a/development-environment.html b/development-environment.html index b807a79af..942edd6f8 100644 --- a/development-environment.html +++ b/development-environment.html @@ -209,7 +209,7 @@

tprof.py

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diff --git a/genindex.html b/genindex.html index 6ba60e9dc..ade6ff5a9 100644 --- a/genindex.html +++ b/genindex.html @@ -4731,7 +4731,7 @@

Z

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diff --git a/home.html b/home.html index e28dff023..262fc3290 100644 --- a/home.html +++ b/home.html @@ -129,7 +129,7 @@

Documentation

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diff --git a/index.html b/index.html index eff6222b5..f128dc973 100644 --- a/index.html +++ b/index.html @@ -229,7 +229,7 @@

Coreblocks

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diff --git a/miscellany/exceptions-summary.html b/miscellany/exceptions-summary.html index 53dfe49a3..8369bb4e4 100644 --- a/miscellany/exceptions-summary.html +++ b/miscellany/exceptions-summary.html @@ -271,7 +271,7 @@

Summary

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diff --git a/modules-coreblocks.html b/modules-coreblocks.html index 3fbdd5cc6..a6096e2dc 100644 --- a/modules-coreblocks.html +++ b/modules-coreblocks.html @@ -179,7 +179,7 @@

coreblocks

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diff --git a/modules-transactron.html b/modules-transactron.html index 927ec385d..3e2093f14 100644 --- a/modules-transactron.html +++ b/modules-transactron.html @@ -162,7 +162,7 @@

transactron

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diff --git a/problem-checklist.html b/problem-checklist.html index 029eaa064..ad9692b12 100644 --- a/problem-checklist.html +++ b/problem-checklist.html @@ -105,7 +105,7 @@

Problem checklist

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diff --git a/py-modindex.html b/py-modindex.html index 72cbd0c02..b0a32f298 100644 --- a/py-modindex.html +++ b/py-modindex.html @@ -708,7 +708,7 @@

Python Module Index

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diff --git a/scheduler/overview.html b/scheduler/overview.html index d9f311a3c..5a891d19b 100644 --- a/scheduler/overview.html +++ b/scheduler/overview.html @@ -146,7 +146,7 @@

More detailed description of each block

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diff --git a/search.html b/search.html index f82f491fe..fdf50df96 100644 --- a/search.html +++ b/search.html @@ -101,7 +101,7 @@

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diff --git a/shared-structs/implementation/rs-impl.html b/shared-structs/implementation/rs-impl.html index 3044f616b..f546e369c 100644 --- a/shared-structs/implementation/rs-impl.html +++ b/shared-structs/implementation/rs-impl.html @@ -252,7 +252,7 @@

Read and clean row

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diff --git a/shared-structs/rs.html b/shared-structs/rs.html index 0aced1ccb..139215b1e 100644 --- a/shared-structs/rs.html +++ b/shared-structs/rs.html @@ -222,7 +222,7 @@

External interface signals

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diff --git a/synthesis/synthesis.html b/synthesis/synthesis.html index d17c9d9c9..53cda0820 100644 --- a/synthesis/synthesis.html +++ b/synthesis/synthesis.html @@ -266,7 +266,7 @@

Regression tests manual execution

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diff --git a/transactions.html b/transactions.html index f9db2dcbe..f96d6833f 100644 --- a/transactions.html +++ b/transactions.html @@ -409,7 +409,7 @@

Transaction and method nesting

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diff --git a/transactron.core.html b/transactron.core.html index ded9bb94e..60148987b 100644 --- a/transactron.core.html +++ b/transactron.core.html @@ -899,7 +899,7 @@

Submodules

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diff --git a/transactron.html b/transactron.html index f4a72c275..d2a37142d 100644 --- a/transactron.html +++ b/transactron.html @@ -752,7 +752,7 @@

Submodules

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diff --git a/transactron.lib.html b/transactron.lib.html index 5cb1adf13..fbddb82ae 100644 --- a/transactron.lib.html +++ b/transactron.lib.html @@ -2238,7 +2238,7 @@

Submodules

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diff --git a/transactron.testing.html b/transactron.testing.html index ef19d5e6b..84a7a294f 100644 --- a/transactron.testing.html +++ b/transactron.testing.html @@ -471,7 +471,7 @@

Submodules

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diff --git a/transactron.utils.amaranth_ext.html b/transactron.utils.amaranth_ext.html index 97e530272..3c311efce 100644 --- a/transactron.utils.amaranth_ext.html +++ b/transactron.utils.amaranth_ext.html @@ -478,7 +478,7 @@

Submodules

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diff --git a/transactron.utils.html b/transactron.utils.html index 61850aa9c..a656b5575 100644 --- a/transactron.utils.html +++ b/transactron.utils.html @@ -813,7 +813,7 @@

Submodules

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