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This was build with ./test_ulx3s_target.py --build --device=LFE5U-85F --cpu-type=picorv32 --cpu-variant=standard --csr-csv=build/csr.csv --ecppack-compress
A single byte write to address 0x0c appears to work:
However a single byte read from address 0x0c never asserts STB or CYC
For comparison, this is a single byte read from address 0x0c using the vexriscv CPU:
The text was updated successfully, but these errors were encountered:
I have added a 8 bit wishbone peripheral as follows:
This was build with
./test_ulx3s_target.py --build --device=LFE5U-85F --cpu-type=picorv32 --cpu-variant=standard --csr-csv=build/csr.csv --ecppack-compress
A single byte write to address 0x0c appears to work:
However a single byte read from address 0x0c never asserts STB or CYC
For comparison, this is a single byte read from address 0x0c using the vexriscv CPU:
The text was updated successfully, but these errors were encountered: