gfmpw-1 dv issues

[piotro888]

I tried to setup dv testbenches for gfmpw-1c tag accordingly to mpw-* (after fixing pin assignments) tests and found two issues:

1. There is a problem with interacting with simple_por on caravel. Changing VDD pin state in verilog testbech doesn't change its state inside caravel module (where this signal is happens to be a constant 1). This causes simple_por to keep waiting for @(posedge VDD) forever and keep resetting caravel. Simple workaround for this problem is to change @(posedge VDD) to some constant delay.

2. More problematic issue is that caravel turns its wb_rst_i pin to undefined state (and all other pins few cycles later) at fixed time of around ~700us (with 12.5ns clock) into testbench. This time doesn't depend on any external event or interaction with design. I found that it shifts in time only when instruction count of caravel .c program changes - so it probably is some internal caravel problem. It breaks even on default user_proj_example design (without la interactions, only output pins). The only thing that I do in .c file is setting gpio pin modes. I tried to trace this signal, but could not found the reason for this behavior. I can provide more details if needed. This problem is critical, because it breaks possibility of testing larger designs, where shorter tests are not possible. What's important - this problem only happens on GL level, on RTL everything works fine.

[piotro888]

Second problem will be fixed with PR efabless/caravel_mgmt_soc_litex#133 and efabless/caravel_mgmt_soc_gf180mcu#26