cpu0.map.rpt

Analysis & Synthesis report for cpu0
Thu May 30 23:40:51 2024
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |cpu0|timer:inst28|state
  8. User-Specified and Inferred Latches
  9. Logic Cells Representing Combinational Loops
 10. General Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: asynram:inst3
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu May 30 23:40:51 2024    ;
; Quartus II Version          ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name               ; cpu0                                     ;
; Top-level Entity Name       ; cpu0                                     ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 1,177                                    ;
; Total pins                  ; 19                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option                                                         ; Setting            ; Default Value      ;
+----------------------------------------------------------------+--------------------+--------------------+
; Device                                                         ; EP1C12Q240C8       ;                    ;
; Top-level entity name                                          ; cpu0               ; cpu0               ;
; Family name                                                    ; Cyclone            ; Stratix            ;
; Use smart compilation                                          ; Off                ; Off                ;
; Restructure Multiplexers                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                            ; Off                ; Off                ;
; Preserve fewer node names                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                      ; Off                ; Off                ;
; Verilog Version                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                       ; Auto               ; Auto               ;
; Safe State Machine                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                              ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                     ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                 ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                        ; On                 ; On                 ;
; Parallel Synthesis                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                             ; On                 ; On                 ;
; Power-Up Don't Care                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                 ; Off                ; Off                ;
; Optimization Technique                                         ; Balanced           ; Balanced           ;
; Carry Chain Length                                             ; 70                 ; 70                 ;
; Auto Carry Chains                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                          ; Off                ; Off                ;
; Auto ROM Replacement                                           ; On                 ; On                 ;
; Auto RAM Replacement                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                  ; On                 ; On                 ;
; Strict RAM Replacement                                         ; Off                ; Off                ;
; Allow Synchronous Control Signals                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                              ; Off                ; Off                ;
; Auto Resource Sharing                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                  ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing            ; On                 ; On                 ;
; Maximum Number of M512 Memory Blocks                           ; -1                 ; -1                 ;
; Maximum Number of M4K/M9K Memory Blocks                        ; -1                 ; -1                 ;
; Maximum Number of M-RAM/M144K Memory Blocks                    ; -1                 ; -1                 ;
; Ignore translate_off and synthesis_off directives              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                             ; Off                ; Off                ;
; Synchronization Register Chain Length                          ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                         ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+
; mux_4_to_1.vhd                   ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/mux_4_to_1.vhd     ;
; decoder_2_to_4.vhd               ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/decoder_2_to_4.vhd ;
; asynram.vhd                      ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/asynram.vhd        ;
; regfile.vhd                      ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/regfile.vhd        ;
; cpu0.bdf                         ; yes             ; User Block Diagram/Schematic File  ; D:/下载/CPU8bit-main/CPU8bit-main/cpu0.bdf           ;
; alu.vhd                          ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/alu.vhd            ;
; ar.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/ar.vhd             ;
; bus_mux.vhd                      ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/bus_mux.vhd        ;
; controller.vhd                   ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/controller.vhd     ;
; flag_reg.vhd                     ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/flag_reg.vhd       ;
; ir.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/ir.vhd             ;
; pc.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/pc.vhd             ;
; reg.vhd                          ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/reg.vhd            ;
; reg_out.vhd                      ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/reg_out.vhd        ;
; reg_testa.vhd                    ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/reg_testa.vhd      ;
; t1.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/t1.vhd             ;
; t2.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/t2.vhd             ;
; t3.vhd                           ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/t3.vhd             ;
; timer.vhd                        ; yes             ; User VHDL File                     ; D:/下载/CPU8bit-main/CPU8bit-main/timer.vhd          ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+---------------------------------------------+----------------+
; Resource                                    ; Usage          ;
+---------------------------------------------+----------------+
; Total logic elements                        ; 1177           ;
;     -- Combinational with no register       ; 1104           ;
;     -- Register only                        ; 58             ;
;     -- Combinational with a register        ; 15             ;
;                                             ;                ;
; Logic element usage by number of LUT inputs ;                ;
;     -- 4 input functions                    ; 555            ;
;     -- 3 input functions                    ; 548            ;
;     -- 2 input functions                    ; 15             ;
;     -- 1 input functions                    ; 0              ;
;     -- 0 input functions                    ; 1              ;
;                                             ;                ;
; Logic elements by mode                      ;                ;
;     -- normal mode                          ; 1177           ;
;     -- arithmetic mode                      ; 0              ;
;     -- qfbk mode                            ; 0              ;
;     -- register cascade mode                ; 0              ;
;     -- synchronous clear/load mode          ; 7              ;
;     -- asynchronous clear/load mode         ; 73             ;
;                                             ;                ;
; Total registers                             ; 73             ;
; I/O pins                                    ; 19             ;
; Maximum fan-out node                        ; ar:inst19|q[4] ;
; Maximum fan-out                             ; 150            ;
; Total fan-out                               ; 4183           ;
; Average fan-out                             ; 3.50           ;
+---------------------------------------------+----------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                      ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                            ; Library Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
; |cpu0                              ; 1177 (333)  ; 73           ; 0           ; 19   ; 0            ; 1104 (333)   ; 58 (0)            ; 15 (0)           ; 0 (0)           ; 0 (0)      ; |cpu0                                          ; work         ;
;    |alu:inst|                      ; 36 (18)     ; 0            ; 0           ; 0    ; 0            ; 36 (18)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst                                 ; work         ;
;       |adder8bit:f_add|            ; 18 (2)      ; 0            ; 0           ; 0    ; 0            ; 18 (2)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add                 ; work         ;
;          |fa:\f1_7:1:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:1:fm   ; work         ;
;          |fa:\f1_7:2:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:2:fm   ; work         ;
;          |fa:\f1_7:3:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:3:fm   ; work         ;
;          |fa:\f1_7:4:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:4:fm   ; work         ;
;          |fa:\f1_7:5:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:5:fm   ; work         ;
;          |fa:\f1_7:6:fm|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:6:fm   ; work         ;
;          |fa:\f1_7:7:fm|           ; 3 (3)       ; 0            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:\f1_7:7:fm   ; work         ;
;          |fa:f0|                   ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|alu:inst|adder8bit:f_add|fa:f0           ; work         ;
;    |ar:inst19|                     ; 7 (7)       ; 7            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 0 (0)           ; 0 (0)      ; |cpu0|ar:inst19                                ; work         ;
;    |asynram:inst3|                 ; 540 (540)   ; 0            ; 0           ; 0    ; 0            ; 540 (540)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|asynram:inst3                            ; work         ;
;    |bus_mux:inst15|                ; 60 (60)     ; 0            ; 0           ; 0    ; 0            ; 60 (60)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|bus_mux:inst15                           ; work         ;
;    |controller:inst9|              ; 67 (67)     ; 0            ; 0           ; 0    ; 0            ; 67 (67)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|controller:inst9                         ; work         ;
;    |flag_reg:inst2|                ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |cpu0|flag_reg:inst2                           ; work         ;
;    |ir:inst25|                     ; 9 (9)       ; 8            ; 0           ; 0    ; 0            ; 1 (1)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|ir:inst25                                ; work         ;
;    |pc:inst18|                     ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|pc:inst18                                ; work         ;
;    |reg_out:inst6|                 ; 60 (60)     ; 0            ; 0           ; 0    ; 0            ; 60 (60)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|reg_out:inst6                            ; work         ;
;    |reg_testa:inst8|               ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |cpu0|reg_testa:inst8                          ; work         ;
;    |regfile:inst4|                 ; 36 (0)      ; 32           ; 0           ; 0    ; 0            ; 4 (0)        ; 32 (0)            ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4                            ; work         ;
;       |decoder_2_to_4:des_decoder| ; 3 (3)       ; 0            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4|decoder_2_to_4:des_decoder ; work         ;
;       |reg:Areg00|                 ; 9 (9)       ; 8            ; 0           ; 0    ; 0            ; 1 (1)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4|reg:Areg00                 ; work         ;
;       |reg:Areg01|                 ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4|reg:Areg01                 ; work         ;
;       |reg:Areg02|                 ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4|reg:Areg02                 ; work         ;
;       |reg:Areg03|                 ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cpu0|regfile:inst4|reg:Areg03                 ; work         ;
;    |timer:inst28|                  ; 9 (9)       ; 6            ; 0           ; 0    ; 0            ; 3 (3)        ; 2 (2)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |cpu0|timer:inst28                             ; work         ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+----------------------------------------------------------------------------+
; State Machine - |cpu0|timer:inst28|state                                   ;
+----------+----------+----------+----------+----------+----------+----------+
; Name     ; state.s5 ; state.s4 ; state.s3 ; state.s2 ; state.s1 ; state.s0 ;
+----------+----------+----------+----------+----------+----------+----------+
; state.s0 ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ;
; state.s1 ; 0        ; 0        ; 0        ; 0        ; 1        ; 1        ;
; state.s2 ; 0        ; 0        ; 0        ; 1        ; 0        ; 1        ;
; state.s3 ; 0        ; 0        ; 1        ; 0        ; 0        ; 1        ;
; state.s4 ; 0        ; 1        ; 0        ; 0        ; 0        ; 1        ;
; state.s5 ; 1        ; 0        ; 0        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+----------+----------+


+-------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                         ;
+------------------------------------------------------+-----------------------------+------------------------+
; Latch Name                                           ; Latch Enable Signal         ; Free of Timing Hazards ;
+------------------------------------------------------+-----------------------------+------------------------+
; controller:inst9|wr                                  ; controller:inst9|Mux17      ; yes                    ;
; controller:inst9|alu_in_sel[1]                       ; controller:inst9|Mux31      ; yes                    ;
; controller:inst9|alu_in_sel[2]                       ; controller:inst9|Mux34      ; yes                    ;
; controller:inst9|dest_reg[0]                         ; controller:inst9|Mux54      ; yes                    ;
; controller:inst9|dest_reg[1]                         ; controller:inst9|Mux54      ; yes                    ;
; controller:inst9|alu_func[1]                         ; controller:inst9|Mux38      ; yes                    ;
; controller:inst9|alu_func[0]                         ; controller:inst9|Mux38      ; yes                    ;
; controller:inst9|alu_func[2]                         ; controller:inst9|Mux38      ; yes                    ;
; controller:inst9|alu_in_sel[0]                       ; controller:inst9|Mux31      ; yes                    ;
; controller:inst9|sour_reg[0]                         ; controller:inst9|Mux54      ; yes                    ;
; controller:inst9|sour_reg[1]                         ; controller:inst9|Mux54      ; yes                    ;
; controller:inst9|sst[1]                              ; controller:inst9|Mux38      ; yes                    ;
; controller:inst9|sst[0]                              ; controller:inst9|Mux38      ; yes                    ;
; controller:inst9|rec[1]                              ; controller:inst9|Mux15      ; yes                    ;
; controller:inst9|rec[0]                              ; controller:inst9|Mux15      ; yes                    ;
; controller:inst9|sci[1]                              ; controller:inst9|Mux48      ; yes                    ;
; controller:inst9|sci[0]                              ; controller:inst9|Mux48      ; yes                    ;
; asynram:inst3|ram[49][1]                             ; asynram:inst3|ram[49][7]~15 ; yes                    ;
; asynram:inst3|ram[50][1]                             ; asynram:inst3|ram[50][7]~14 ; yes                    ;
; asynram:inst3|ram[48][1]                             ; asynram:inst3|ram[48][7]~16 ; yes                    ;
; asynram:inst3|ram[51][1]                             ; asynram:inst3|ram[51][7]~13 ; yes                    ;
; asynram:inst3|ram[21][1]                             ; asynram:inst3|ram[21][7]~43 ; yes                    ;
; asynram:inst3|ram[22][1]                             ; asynram:inst3|ram[22][7]~42 ; yes                    ;
; asynram:inst3|ram[20][1]                             ; asynram:inst3|ram[20][7]~44 ; yes                    ;
; asynram:inst3|ram[23][1]                             ; asynram:inst3|ram[23][7]~41 ; yes                    ;
; asynram:inst3|ram[17][1]                             ; asynram:inst3|ram[17][7]~47 ; yes                    ;
; asynram:inst3|ram[18][1]                             ; asynram:inst3|ram[18][7]~46 ; yes                    ;
; asynram:inst3|ram[16][1]                             ; asynram:inst3|ram[16][7]~48 ; yes                    ;
; asynram:inst3|ram[19][1]                             ; asynram:inst3|ram[19][7]~45 ; yes                    ;
; asynram:inst3|ram[53][1]                             ; asynram:inst3|ram[53][7]~11 ; yes                    ;
; asynram:inst3|ram[54][1]                             ; asynram:inst3|ram[54][7]~10 ; yes                    ;
; asynram:inst3|ram[52][1]                             ; asynram:inst3|ram[52][7]~12 ; yes                    ;
; asynram:inst3|ram[55][1]                             ; asynram:inst3|ram[55][7]~9  ; yes                    ;
; asynram:inst3|ram[37][1]                             ; asynram:inst3|ram[37][7]~27 ; yes                    ;
; asynram:inst3|ram[35][1]                             ; asynram:inst3|ram[35][7]~29 ; yes                    ;
; asynram:inst3|ram[33][1]                             ; asynram:inst3|ram[33][7]~31 ; yes                    ;
; asynram:inst3|ram[39][1]                             ; asynram:inst3|ram[39][7]~25 ; yes                    ;
; asynram:inst3|ram[64][1]                             ; asynram:inst3|ram[64][6]~0  ; yes                    ;
; asynram:inst3|ram[7][1]                              ; asynram:inst3|ram[7][7]~57  ; yes                    ;
; asynram:inst3|ram[34][1]                             ; asynram:inst3|ram[34][7]~30 ; yes                    ;
; asynram:inst3|ram[36][1]                             ; asynram:inst3|ram[36][7]~28 ; yes                    ;
; asynram:inst3|ram[32][1]                             ; asynram:inst3|ram[32][7]~32 ; yes                    ;
; asynram:inst3|ram[38][1]                             ; asynram:inst3|ram[38][7]~26 ; yes                    ;
; asynram:inst3|ram[28][1]                             ; asynram:inst3|ram[28][7]~36 ; yes                    ;
; asynram:inst3|ram[26][1]                             ; asynram:inst3|ram[26][7]~38 ; yes                    ;
; asynram:inst3|ram[24][1]                             ; asynram:inst3|ram[24][7]~40 ; yes                    ;
; asynram:inst3|ram[30][1]                             ; asynram:inst3|ram[30][7]~34 ; yes                    ;
; asynram:inst3|ram[44][1]                             ; asynram:inst3|ram[44][7]~20 ; yes                    ;
; asynram:inst3|ram[42][1]                             ; asynram:inst3|ram[42][7]~22 ; yes                    ;
; asynram:inst3|ram[40][1]                             ; asynram:inst3|ram[40][7]~24 ; yes                    ;
; asynram:inst3|ram[46][1]                             ; asynram:inst3|ram[46][7]~18 ; yes                    ;
; asynram:inst3|ram[12][1]                             ; asynram:inst3|ram[12][7]~52 ; yes                    ;
; asynram:inst3|ram[10][1]                             ; asynram:inst3|ram[10][7]~54 ; yes                    ;
; asynram:inst3|ram[8][1]                              ; asynram:inst3|ram[8][7]~56  ; yes                    ;
; asynram:inst3|ram[14][1]                             ; asynram:inst3|ram[14][7]~50 ; yes                    ;
; asynram:inst3|ram[58][1]                             ; asynram:inst3|ram[58][7]~6  ; yes                    ;
; asynram:inst3|ram[60][1]                             ; asynram:inst3|ram[60][7]~4  ; yes                    ;
; asynram:inst3|ram[56][1]                             ; asynram:inst3|ram[56][7]~8  ; yes                    ;
; asynram:inst3|ram[62][1]                             ; asynram:inst3|ram[62][7]~2  ; yes                    ;
; asynram:inst3|ram[27][1]                             ; asynram:inst3|ram[27][7]~37 ; yes                    ;
; asynram:inst3|ram[29][1]                             ; asynram:inst3|ram[29][7]~35 ; yes                    ;
; asynram:inst3|ram[25][1]                             ; asynram:inst3|ram[25][7]~39 ; yes                    ;
; asynram:inst3|ram[31][1]                             ; asynram:inst3|ram[31][7]~33 ; yes                    ;
; asynram:inst3|ram[45][1]                             ; asynram:inst3|ram[45][7]~19 ; yes                    ;
; asynram:inst3|ram[43][1]                             ; asynram:inst3|ram[43][7]~21 ; yes                    ;
; asynram:inst3|ram[41][1]                             ; asynram:inst3|ram[41][7]~23 ; yes                    ;
; asynram:inst3|ram[47][1]                             ; asynram:inst3|ram[47][7]~17 ; yes                    ;
; asynram:inst3|ram[13][1]                             ; asynram:inst3|ram[13][7]~51 ; yes                    ;
; asynram:inst3|ram[11][1]                             ; asynram:inst3|ram[11][7]~53 ; yes                    ;
; asynram:inst3|ram[9][1]                              ; asynram:inst3|ram[9][7]~55  ; yes                    ;
; asynram:inst3|ram[15][1]                             ; asynram:inst3|ram[15][7]~49 ; yes                    ;
; asynram:inst3|ram[59][1]                             ; asynram:inst3|ram[59][7]~5  ; yes                    ;
; asynram:inst3|ram[61][1]                             ; asynram:inst3|ram[61][7]~3  ; yes                    ;
; asynram:inst3|ram[57][1]                             ; asynram:inst3|ram[57][7]~7  ; yes                    ;
; asynram:inst3|ram[63][1]                             ; asynram:inst3|ram[63][7]~1  ; yes                    ;
; asynram:inst3|ram[37][2]                             ; asynram:inst3|ram[37][7]~27 ; yes                    ;
; asynram:inst3|ram[35][2]                             ; asynram:inst3|ram[35][7]~29 ; yes                    ;
; asynram:inst3|ram[33][2]                             ; asynram:inst3|ram[33][7]~31 ; yes                    ;
; asynram:inst3|ram[39][2]                             ; asynram:inst3|ram[39][7]~25 ; yes                    ;
; asynram:inst3|ram[49][2]                             ; asynram:inst3|ram[49][7]~15 ; yes                    ;
; asynram:inst3|ram[52][2]                             ; asynram:inst3|ram[52][7]~12 ; yes                    ;
; asynram:inst3|ram[48][2]                             ; asynram:inst3|ram[48][7]~16 ; yes                    ;
; asynram:inst3|ram[53][2]                             ; asynram:inst3|ram[53][7]~11 ; yes                    ;
; asynram:inst3|ram[19][2]                             ; asynram:inst3|ram[19][7]~45 ; yes                    ;
; asynram:inst3|ram[22][2]                             ; asynram:inst3|ram[22][7]~42 ; yes                    ;
; asynram:inst3|ram[18][2]                             ; asynram:inst3|ram[18][7]~46 ; yes                    ;
; asynram:inst3|ram[23][2]                             ; asynram:inst3|ram[23][7]~41 ; yes                    ;
; asynram:inst3|ram[17][2]                             ; asynram:inst3|ram[17][7]~47 ; yes                    ;
; asynram:inst3|ram[20][2]                             ; asynram:inst3|ram[20][7]~44 ; yes                    ;
; asynram:inst3|ram[16][2]                             ; asynram:inst3|ram[16][7]~48 ; yes                    ;
; asynram:inst3|ram[21][2]                             ; asynram:inst3|ram[21][7]~43 ; yes                    ;
; asynram:inst3|ram[51][2]                             ; asynram:inst3|ram[51][7]~13 ; yes                    ;
; asynram:inst3|ram[54][2]                             ; asynram:inst3|ram[54][7]~10 ; yes                    ;
; asynram:inst3|ram[50][2]                             ; asynram:inst3|ram[50][7]~14 ; yes                    ;
; asynram:inst3|ram[55][2]                             ; asynram:inst3|ram[55][7]~9  ; yes                    ;
; asynram:inst3|ram[64][2]                             ; asynram:inst3|ram[64][6]~0  ; yes                    ;
; asynram:inst3|ram[7][2]                              ; asynram:inst3|ram[7][7]~57  ; yes                    ;
; asynram:inst3|ram[34][2]                             ; asynram:inst3|ram[34][7]~30 ; yes                    ;
; asynram:inst3|ram[36][2]                             ; asynram:inst3|ram[36][7]~28 ; yes                    ;
; asynram:inst3|ram[32][2]                             ; asynram:inst3|ram[32][7]~32 ; yes                    ;
; Number of user-specified and inferred latches = 481  ;                             ;                        ;
+------------------------------------------------------+-----------------------------+------------------------+
Table restricted to first 100 entries. Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-------------------------------------------------------------+
; Logic Cells Representing Combinational Loops                ;
+--------------------------------------------------------+----+
; Logic Cell Name                                        ;    ;
+--------------------------------------------------------+----+
; bus_mux:inst15|Mux8~0                                  ;    ;
; alu:inst|b_in[6]~16                                    ;    ;
; alu:inst|b_in[5]~17                                    ;    ;
; alu:inst|b_in[4]~18                                    ;    ;
; alu:inst|b_in[3]~19                                    ;    ;
; alu:inst|b_in[2]~20                                    ;    ;
; alu:inst|b_in[1]~21                                    ;    ;
; alu:inst|b_in[0]~22                                    ;    ;
; gdfx_temp0[6]~1                                        ;    ;
; gdfx_temp0[5]~2                                        ;    ;
; gdfx_temp0[4]~3                                        ;    ;
; gdfx_temp0[3]~4                                        ;    ;
; gdfx_temp0[2]~5                                        ;    ;
; gdfx_temp0[1]~6                                        ;    ;
; gdfx_temp0[0]~7                                        ;    ;
; gdfx_temp0[7]~0                                        ;    ;
; controller:inst9|en_reg                                ;    ;
; controller:inst9|en_pc                                 ;    ;
; Number of logic cells representing combinational loops ; 18 ;
+--------------------------------------------------------+----+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 73    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 7     ;
; Number of registers using Asynchronous Clear ; 73    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 58    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |cpu0|ar:inst19|q[6]         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |cpu0|controller:inst9|Mux33 ;
; 8:1                ; 8 bits    ; 40 LEs        ; 24 LEs               ; 16 LEs                 ; No         ; |cpu0|alu:inst|Mux2          ;
; 6:1                ; 5 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |cpu0|bus_mux:inst15|Mux1    ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |cpu0|alu:inst|b_in[7]       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |cpu0|controller:inst9|Mux49 ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |cpu0|controller:inst9|Mux55 ;
; 10:1               ; 3 bits    ; 18 LEs        ; 12 LEs               ; 6 LEs                  ; No         ; |cpu0|bus_mux:inst15|Mux7    ;
; 10:1               ; 8 bits    ; 48 LEs        ; 40 LEs               ; 8 LEs                  ; No         ; |cpu0|bus_mux:inst15|Mux13   ;
; 14:1               ; 8 bits    ; 72 LEs        ; 64 LEs               ; 8 LEs                  ; No         ; |cpu0|reg_out:inst6|Mux25    ;
; 80:1               ; 8 bits    ; 424 LEs       ; 352 LEs              ; 72 LEs                 ; No         ; |cpu0|gdfx_temp0[5]          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: asynram:inst3 ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type                              ;
+----------------+-------+-----------------------------------+
; ram_width      ; 8     ; Signed Integer                    ;
; adr_width      ; 8     ; Signed Integer                    ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Thu May 30 23:40:48 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu0 -c cpu0
Info: Found 2 design units, including 1 entities, in source file mux_4_to_1.vhd
    Info: Found design unit 1: mux_4_to_1-behavioral
    Info: Found entity 1: mux_4_to_1
Info: Found 2 design units, including 1 entities, in source file decoder_2_to_4.vhd
    Info: Found design unit 1: decoder_2_to_4-behavioral
    Info: Found entity 1: decoder_2_to_4
Info: Found 2 design units, including 1 entities, in source file asynram.vhd
    Info: Found design unit 1: asynram-rtl
    Info: Found entity 1: asynram
Info: Found 2 design units, including 1 entities, in source file regfile.vhd
    Info: Found design unit 1: regfile-struct
    Info: Found entity 1: regfile
Info: Found 1 design units, including 1 entities, in source file cpu0.bdf
    Info: Found entity 1: cpu0
Info: Found 6 design units, including 3 entities, in source file alu.vhd
    Info: Found design unit 1: alu-behavioral
    Info: Found design unit 2: adder8bit-structure
    Info: Found design unit 3: fa-b_fa
    Info: Found entity 1: alu
    Info: Found entity 2: adder8bit
    Info: Found entity 3: fa
Info: Found 2 design units, including 1 entities, in source file ar.vhd
    Info: Found design unit 1: ar-behave
    Info: Found entity 1: ar
Info: Found 2 design units, including 1 entities, in source file bus_dir.vhd
    Info: Found design unit 1: bus_dir-behave
    Info: Found entity 1: bus_dir
Info: Found 2 design units, including 1 entities, in source file bus_mux.vhd
    Info: Found design unit 1: bus_mux-behave
    Info: Found entity 1: bus_mux
Info: Found 2 design units, including 1 entities, in source file controller.vhd
    Info: Found design unit 1: controller-behave
    Info: Found entity 1: controller
Info: Found 2 design units, including 1 entities, in source file flag_reg.vhd
    Info: Found design unit 1: flag_reg-behave
    Info: Found entity 1: flag_reg
Info: Found 2 design units, including 1 entities, in source file ir.vhd
    Info: Found design unit 1: ir-behave
    Info: Found entity 1: ir
Info: Found 2 design units, including 1 entities, in source file pc.vhd
    Info: Found design unit 1: pc-behave
    Info: Found entity 1: pc
Info: Found 2 design units, including 1 entities, in source file reg.vhd
    Info: Found design unit 1: reg-behave
    Info: Found entity 1: reg
Info: Found 2 design units, including 1 entities, in source file reg_mux.vhd
    Info: Found design unit 1: reg_mux-behave
    Info: Found entity 1: reg_mux
Info: Found 2 design units, including 1 entities, in source file reg_out.vhd
    Info: Found design unit 1: reg_out-behave
    Info: Found entity 1: reg_out
Info: Found 2 design units, including 1 entities, in source file reg_test.vhd
    Info: Found design unit 1: reg_test-behave
    Info: Found entity 1: reg_test
Info: Found 2 design units, including 1 entities, in source file reg_testa.vhd
    Info: Found design unit 1: reg_testa-behave
    Info: Found entity 1: reg_testa
Info: Found 2 design units, including 1 entities, in source file t1.vhd
    Info: Found design unit 1: t1-behave
    Info: Found entity 1: t1
Info: Found 2 design units, including 1 entities, in source file t2.vhd
    Info: Found design unit 1: t2-behave
    Info: Found entity 1: t2
Info: Found 2 design units, including 1 entities, in source file t3.vhd
    Info: Found design unit 1: t3-behave
    Info: Found entity 1: t3
Info: Found 2 design units, including 1 entities, in source file timer.vhd
    Info: Found design unit 1: timer-behave
    Info: Found entity 1: timer
Info: Elaborating entity "cpu0" for the top level hierarchy
Info: Elaborating entity "controller" for hierarchy "controller:inst9"
Warning (10036): Verilog HDL or VHDL warning at controller.vhd(18): object "temp2" assigned a value but never read
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "dest_reg", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "sour_reg", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "offset", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "sci", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "sst", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "alu_out_sel", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "alu_in_sel", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "alu_func", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "wr", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at controller.vhd(17): inferring latch(es) for signal or variable "rec", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "rec[0]" at controller.vhd(17)
Info (10041): Inferred latch for "rec[1]" at controller.vhd(17)
Info (10041): Inferred latch for "wr" at controller.vhd(17)
Info (10041): Inferred latch for "alu_func[0]" at controller.vhd(17)
Info (10041): Inferred latch for "alu_func[1]" at controller.vhd(17)
Info (10041): Inferred latch for "alu_func[2]" at controller.vhd(17)
Info (10041): Inferred latch for "alu_in_sel[0]" at controller.vhd(17)
Info (10041): Inferred latch for "alu_in_sel[1]" at controller.vhd(17)
Info (10041): Inferred latch for "alu_in_sel[2]" at controller.vhd(17)
Info (10041): Inferred latch for "sst[0]" at controller.vhd(17)
Info (10041): Inferred latch for "sst[1]" at controller.vhd(17)
Info (10041): Inferred latch for "sci[0]" at controller.vhd(17)
Info (10041): Inferred latch for "sci[1]" at controller.vhd(17)
Info (10041): Inferred latch for "offset[0]" at controller.vhd(17)
Info (10041): Inferred latch for "offset[1]" at controller.vhd(17)
Info (10041): Inferred latch for "offset[2]" at controller.vhd(17)
Info (10041): Inferred latch for "offset[3]" at controller.vhd(17)
Info (10041): Inferred latch for "sour_reg[0]" at controller.vhd(17)
Info (10041): Inferred latch for "sour_reg[1]" at controller.vhd(17)
Info (10041): Inferred latch for "dest_reg[0]" at controller.vhd(17)
Info (10041): Inferred latch for "dest_reg[1]" at controller.vhd(17)
Info: Elaborating entity "flag_reg" for hierarchy "flag_reg:inst2"
Info: Elaborating entity "alu" for hierarchy "alu:inst"
Warning (10492): VHDL Process Statement warning at alu.vhd(60): signal "a_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(60): signal "b_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(62): signal "a_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(62): signal "b_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(64): signal "a_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(66): signal "a_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(66): signal "b_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at alu.vhd(68): signal "result_add8" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "adder8bit" for hierarchy "alu:inst|adder8bit:f_add"
Info: Elaborating entity "fa" for hierarchy "alu:inst|adder8bit:f_add|fa:f0"
Info: Elaborating entity "t1" for hierarchy "t1:inst31"
Info: Elaborating entity "bus_mux" for hierarchy "bus_mux:inst15"
Info: Elaborating entity "t3" for hierarchy "t3:inst21"
Info: Elaborating entity "asynram" for hierarchy "asynram:inst3"
Warning (10492): VHDL Process Statement warning at asynram.vhd(29): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at asynram.vhd(20): inferring latch(es) for signal or variable "ram", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "ram[64][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[64][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[63][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[62][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[61][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[60][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[59][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[58][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[57][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[56][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[55][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[54][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[53][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[52][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[51][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[50][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[49][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[48][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[47][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[46][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[45][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[44][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[43][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[42][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[41][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[40][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[39][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[38][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[37][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[36][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[35][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[34][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[33][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[32][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[31][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[30][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[29][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[28][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[27][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[26][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[25][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[24][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[23][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[22][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[21][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[20][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[19][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[18][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[17][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[16][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[15][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[14][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[13][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[12][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[11][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[10][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[9][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[8][0]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][7]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][6]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][5]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][4]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][3]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][2]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][1]" at asynram.vhd(20)
Info (10041): Inferred latch for "ram[7][0]" at asynram.vhd(20)
Info: Elaborating entity "ar" for hierarchy "ar:inst19"
Info: Elaborating entity "pc" for hierarchy "pc:inst18"
Info: Elaborating entity "regfile" for hierarchy "regfile:inst4"
Info: Elaborating entity "reg" for hierarchy "regfile:inst4|reg:Areg00"
Info: Elaborating entity "decoder_2_to_4" for hierarchy "regfile:inst4|decoder_2_to_4:des_decoder"
Info: Elaborating entity "mux_4_to_1" for hierarchy "regfile:inst4|mux_4_to_1:muxA"
Info: Elaborating entity "t2" for hierarchy "t2:inst5"
Info: Elaborating entity "ir" for hierarchy "ir:inst25"
Info: Elaborating entity "timer" for hierarchy "timer:inst28"
Info: Elaborating entity "reg_out" for hierarchy "reg_out:inst6"
Warning (10036): Verilog HDL or VHDL warning at reg_out.vhd(18): object "temp" assigned a value but never read
Warning (10631): VHDL Process Statement warning at reg_out.vhd(17): inferring latch(es) for signal or variable "reg_data1", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "reg_data1[0]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[1]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[2]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[3]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[4]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[5]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[6]" at reg_out.vhd(17)
Info (10041): Inferred latch for "reg_data1[7]" at reg_out.vhd(17)
Info: Elaborating entity "reg_testa" for hierarchy "reg_testa:inst8"
Warning: Tri-state node(s) do not directly drive top-level pin(s)
    Warning: Converted tri-state node "gdfx_temp0[7]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[6]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[5]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[4]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[3]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[2]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[1]" into a selector
    Warning: Converted tri-state node "gdfx_temp0[0]" into a selector
Info: Duplicate LATCH primitives merged into single LATCH primitive
    Info: Duplicate LATCH primitive "controller:inst9|sst[0]" merged with LATCH primitive "controller:inst9|sst[1]"
Warning: Latch controller:inst9|wr has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Warning: Latch controller:inst9|alu_in_sel[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|alu_in_sel[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|dest_reg[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|dest_reg[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|alu_func[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Warning: Latch controller:inst9|alu_func[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Warning: Latch controller:inst9|alu_func[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ir:inst25|q[7]
Warning: Latch controller:inst9|alu_in_sel[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ir:inst25|q[5]
Warning: Latch controller:inst9|sour_reg[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|sour_reg[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|sst[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Warning: Latch controller:inst9|rec[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Warning: Latch controller:inst9|rec[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|output~1
Warning: Latch controller:inst9|sci[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ir:inst25|q[7]
Warning: Latch controller:inst9|sci[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal timer:inst28|WideOr1
Info: Implemented 1196 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 13 output pins
    Info: Implemented 1177 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings
    Info: Peak virtual memory: 255 megabytes
    Info: Processing ended: Thu May 30 23:40:51 2024
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02