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Tetris_mapped.v
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Tetris_mapped.v
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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : K-2015.06-SP5-6
// Date : Mon Dec 2 12:34:41 2019
/////////////////////////////////////////////////////////////
module Input_Controller ( clk, reset, button_data_in, nes_reset,
button_data_out );
output [3:0] button_data_out;
input clk, reset, button_data_in;
output nes_reset;
wire button_lock, N407, N408, N409, N410, N411, N412, N413, N414, N415,
N416, N417, N418, N419, N420, N421, N422, N423, N424, N425, n145,
n146, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42,
n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56,
n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98,
n99, n100, n101, n102, n103, n104;
wire [18:0] slow_clk_counter;
DFFQX1 \slow_clk_counter_reg[0] ( .D(N407), .CLK(clk), .Q(
slow_clk_counter[0]) );
DFFQX1 \slow_clk_counter_reg[1] ( .D(N408), .CLK(clk), .Q(
slow_clk_counter[1]) );
DFFQX1 \slow_clk_counter_reg[2] ( .D(N409), .CLK(clk), .Q(
slow_clk_counter[2]) );
DFFQX1 \slow_clk_counter_reg[3] ( .D(N410), .CLK(clk), .Q(
slow_clk_counter[3]) );
DFFQX1 \slow_clk_counter_reg[4] ( .D(N411), .CLK(clk), .Q(
slow_clk_counter[4]) );
DFFQX1 \slow_clk_counter_reg[5] ( .D(N412), .CLK(clk), .Q(
slow_clk_counter[5]) );
DFFQX1 \slow_clk_counter_reg[6] ( .D(N413), .CLK(clk), .Q(
slow_clk_counter[6]) );
DFFQX1 \slow_clk_counter_reg[7] ( .D(N414), .CLK(clk), .Q(
slow_clk_counter[7]) );
DFFQX1 \slow_clk_counter_reg[8] ( .D(N415), .CLK(clk), .Q(
slow_clk_counter[8]) );
DFFQX1 \slow_clk_counter_reg[9] ( .D(N416), .CLK(clk), .Q(
slow_clk_counter[9]) );
DFFQX1 \slow_clk_counter_reg[10] ( .D(N417), .CLK(clk), .Q(
slow_clk_counter[10]) );
DFFQX1 \slow_clk_counter_reg[11] ( .D(N418), .CLK(clk), .Q(
slow_clk_counter[11]) );
DFFQX1 \slow_clk_counter_reg[12] ( .D(N419), .CLK(clk), .Q(
slow_clk_counter[12]) );
DFFQX1 \slow_clk_counter_reg[13] ( .D(N420), .CLK(clk), .Q(
slow_clk_counter[13]) );
DFFQX1 \slow_clk_counter_reg[14] ( .D(N421), .CLK(clk), .Q(
slow_clk_counter[14]) );
DFFQX1 \slow_clk_counter_reg[15] ( .D(N422), .CLK(clk), .Q(
slow_clk_counter[15]) );
DFFQX1 \slow_clk_counter_reg[16] ( .D(N423), .CLK(clk), .Q(
slow_clk_counter[16]) );
DFFQX1 \slow_clk_counter_reg[17] ( .D(N424), .CLK(clk), .Q(
slow_clk_counter[17]) );
DFFQX1 \slow_clk_counter_reg[18] ( .D(N425), .CLK(clk), .Q(
slow_clk_counter[18]) );
DFFQX1 button_lock_reg ( .D(n146), .CLK(clk), .Q(button_lock) );
DFFQX1 nes_reset_reg ( .D(n145), .CLK(clk), .Q(nes_reset) );
INVX1 U3 ( .A(n8), .Z(n12) );
INVX1 U4 ( .A(slow_clk_counter[0]), .Z(N407) );
NAND2X1 U5 ( .A(slow_clk_counter[1]), .B(slow_clk_counter[0]), .Z(n8) );
NOR2X1 U6 ( .A(slow_clk_counter[1]), .B(slow_clk_counter[0]), .Z(n44) );
NOR2X1 U7 ( .A(n12), .B(n44), .Z(N408) );
NAND3X1 U8 ( .A(slow_clk_counter[8]), .B(slow_clk_counter[9]), .C(
slow_clk_counter[3]), .Z(n58) );
NAND3X1 U9 ( .A(slow_clk_counter[18]), .B(slow_clk_counter[17]), .C(
slow_clk_counter[11]), .Z(n3) );
INVX1 U10 ( .A(slow_clk_counter[12]), .Z(n82) );
INVX1 U11 ( .A(slow_clk_counter[4]), .Z(n70) );
NOR2X1 U12 ( .A(n82), .B(n70), .Z(n76) );
INVX1 U13 ( .A(slow_clk_counter[10]), .Z(n67) );
INVX1 U14 ( .A(slow_clk_counter[5]), .Z(n84) );
NAND3X1 U15 ( .A(n67), .B(slow_clk_counter[7]), .C(n84), .Z(n1) );
NOR2X1 U16 ( .A(slow_clk_counter[6]), .B(n1), .Z(n73) );
NAND3X1 U17 ( .A(n76), .B(slow_clk_counter[14]), .C(n73), .Z(n2) );
NOR2X1 U18 ( .A(n3), .B(n2), .Z(n6) );
NOR2X1 U19 ( .A(slow_clk_counter[2]), .B(n8), .Z(n5) );
OR2X1 U20 ( .A(slow_clk_counter[16]), .B(slow_clk_counter[15]), .Z(n4) );
NOR2X1 U21 ( .A(slow_clk_counter[13]), .B(n4), .Z(n101) );
NAND3X1 U22 ( .A(n6), .B(n5), .C(n101), .Z(n7) );
NOR2X1 U23 ( .A(n58), .B(n7), .Z(n41) );
NOR2X1 U24 ( .A(n41), .B(slow_clk_counter[2]), .Z(n9) );
MUX2X1 U25 ( .A(n9), .B(slow_clk_counter[2]), .S(n8), .Z(N409) );
INVX1 U26 ( .A(slow_clk_counter[3]), .Z(n72) );
NAND2X1 U27 ( .A(slow_clk_counter[2]), .B(n12), .Z(n10) );
MUX2X1 U28 ( .A(slow_clk_counter[3]), .B(n72), .S(n10), .Z(n11) );
NOR2X1 U29 ( .A(n41), .B(n11), .Z(N410) );
NAND3X1 U30 ( .A(slow_clk_counter[3]), .B(slow_clk_counter[2]), .C(n12), .Z(
n14) );
MUX2X1 U31 ( .A(slow_clk_counter[4]), .B(n70), .S(n14), .Z(n13) );
NOR2X1 U32 ( .A(n41), .B(n13), .Z(N411) );
NOR2X1 U33 ( .A(n70), .B(n14), .Z(n15) );
MUX2X1 U34 ( .A(slow_clk_counter[5]), .B(n84), .S(n15), .Z(N412) );
INVX1 U35 ( .A(slow_clk_counter[6]), .Z(n17) );
NAND2X1 U36 ( .A(slow_clk_counter[5]), .B(n15), .Z(n16) );
MUX2X1 U37 ( .A(n17), .B(slow_clk_counter[6]), .S(n16), .Z(N413) );
INVX1 U38 ( .A(slow_clk_counter[7]), .Z(n18) );
NOR2X1 U39 ( .A(n17), .B(n16), .Z(n20) );
MUX2X1 U40 ( .A(n18), .B(slow_clk_counter[7]), .S(n20), .Z(n19) );
NOR2X1 U41 ( .A(n41), .B(n19), .Z(N414) );
INVX1 U42 ( .A(slow_clk_counter[8]), .Z(n50) );
NAND2X1 U43 ( .A(slow_clk_counter[7]), .B(n20), .Z(n22) );
MUX2X1 U44 ( .A(slow_clk_counter[8]), .B(n50), .S(n22), .Z(n21) );
NOR2X1 U45 ( .A(n41), .B(n21), .Z(N415) );
INVX1 U46 ( .A(slow_clk_counter[9]), .Z(n77) );
NOR2X1 U47 ( .A(n50), .B(n22), .Z(n24) );
MUX2X1 U48 ( .A(n77), .B(slow_clk_counter[9]), .S(n24), .Z(n23) );
NOR2X1 U49 ( .A(n41), .B(n23), .Z(N416) );
NAND2X1 U50 ( .A(slow_clk_counter[9]), .B(n24), .Z(n25) );
MUX2X1 U51 ( .A(n67), .B(slow_clk_counter[10]), .S(n25), .Z(N417) );
INVX1 U52 ( .A(slow_clk_counter[11]), .Z(n64) );
NOR2X1 U53 ( .A(n67), .B(n25), .Z(n27) );
MUX2X1 U54 ( .A(n64), .B(slow_clk_counter[11]), .S(n27), .Z(n26) );
NOR2X1 U55 ( .A(n41), .B(n26), .Z(N418) );
NAND2X1 U56 ( .A(slow_clk_counter[11]), .B(n27), .Z(n29) );
MUX2X1 U57 ( .A(slow_clk_counter[12]), .B(n82), .S(n29), .Z(n28) );
NOR2X1 U58 ( .A(n41), .B(n28), .Z(N419) );
NOR2X1 U59 ( .A(n82), .B(n29), .Z(n30) );
XOR2X1 U60 ( .A(slow_clk_counter[13]), .B(n30), .Z(N420) );
INVX1 U61 ( .A(slow_clk_counter[14]), .Z(n33) );
NAND2X1 U62 ( .A(slow_clk_counter[13]), .B(n30), .Z(n32) );
MUX2X1 U63 ( .A(slow_clk_counter[14]), .B(n33), .S(n32), .Z(n31) );
NOR2X1 U64 ( .A(n41), .B(n31), .Z(N421) );
NOR2X1 U65 ( .A(n33), .B(n32), .Z(n34) );
XOR2X1 U66 ( .A(slow_clk_counter[15]), .B(n34), .Z(N422) );
INVX1 U67 ( .A(slow_clk_counter[16]), .Z(n36) );
NAND2X1 U68 ( .A(slow_clk_counter[15]), .B(n34), .Z(n35) );
MUX2X1 U69 ( .A(n36), .B(slow_clk_counter[16]), .S(n35), .Z(N423) );
INVX1 U70 ( .A(slow_clk_counter[17]), .Z(n43) );
NOR2X1 U71 ( .A(n36), .B(n35), .Z(n38) );
MUX2X1 U72 ( .A(n43), .B(slow_clk_counter[17]), .S(n38), .Z(n37) );
NOR2X1 U73 ( .A(n41), .B(n37), .Z(N424) );
INVX1 U74 ( .A(slow_clk_counter[18]), .Z(n42) );
NAND2X1 U75 ( .A(slow_clk_counter[17]), .B(n38), .Z(n39) );
MUX2X1 U76 ( .A(slow_clk_counter[18]), .B(n42), .S(n39), .Z(n40) );
NOR2X1 U77 ( .A(n41), .B(n40), .Z(N425) );
NAND2X1 U78 ( .A(button_lock), .B(n41), .Z(n97) );
INVX1 U79 ( .A(reset), .Z(n102) );
NAND2X1 U80 ( .A(slow_clk_counter[11]), .B(n82), .Z(n47) );
NAND3X1 U81 ( .A(n44), .B(n43), .C(n42), .Z(n45) );
NOR2X1 U82 ( .A(slow_clk_counter[14]), .B(n45), .Z(n46) );
NAND2X1 U83 ( .A(slow_clk_counter[2]), .B(n46), .Z(n63) );
NOR2X1 U84 ( .A(n47), .B(n63), .Z(n51) );
NOR2X1 U85 ( .A(slow_clk_counter[4]), .B(n77), .Z(n81) );
NAND3X1 U86 ( .A(n50), .B(n81), .C(slow_clk_counter[3]), .Z(n48) );
NOR2X1 U87 ( .A(button_data_in), .B(n48), .Z(n49) );
NAND3X1 U88 ( .A(n73), .B(n51), .C(n49), .Z(n98) );
NAND3X1 U89 ( .A(n50), .B(n77), .C(n72), .Z(n54) );
NOR2X1 U90 ( .A(slow_clk_counter[6]), .B(slow_clk_counter[7]), .Z(n52) );
AND2X1 U91 ( .A(slow_clk_counter[5]), .B(n51), .Z(n55) );
NAND3X1 U92 ( .A(n52), .B(n55), .C(slow_clk_counter[4]), .Z(n57) );
NOR2X1 U93 ( .A(n54), .B(n57), .Z(n62) );
NAND2X1 U94 ( .A(slow_clk_counter[6]), .B(slow_clk_counter[7]), .Z(n53) );
NOR2X1 U95 ( .A(n54), .B(n53), .Z(n56) );
NAND3X1 U96 ( .A(n56), .B(n55), .C(n70), .Z(n60) );
OR2X1 U97 ( .A(n58), .B(n57), .Z(n59) );
NAND2X1 U98 ( .A(n60), .B(n59), .Z(n61) );
MUX2X1 U99 ( .A(n62), .B(n61), .S(slow_clk_counter[10]), .Z(n91) );
INVX1 U100 ( .A(n63), .Z(n65) );
NAND3X1 U101 ( .A(slow_clk_counter[8]), .B(n65), .C(n64), .Z(n75) );
NAND3X1 U102 ( .A(slow_clk_counter[7]), .B(slow_clk_counter[6]), .C(
slow_clk_counter[3]), .Z(n66) );
NOR2X1 U103 ( .A(n75), .B(n66), .Z(n86) );
INVX1 U104 ( .A(n86), .Z(n69) );
NAND3X1 U105 ( .A(slow_clk_counter[5]), .B(slow_clk_counter[12]), .C(n67),
.Z(n68) );
NOR2X1 U106 ( .A(n69), .B(n68), .Z(n71) );
NAND2X1 U107 ( .A(n71), .B(n70), .Z(n79) );
NAND2X1 U108 ( .A(n73), .B(n72), .Z(n74) );
NOR2X1 U109 ( .A(n75), .B(n74), .Z(n80) );
NAND2X1 U110 ( .A(n76), .B(n80), .Z(n78) );
MUX2X1 U111 ( .A(n79), .B(n78), .S(n77), .Z(n89) );
NAND3X1 U112 ( .A(n81), .B(n80), .C(n82), .Z(n88) );
NAND3X1 U113 ( .A(slow_clk_counter[10]), .B(slow_clk_counter[4]), .C(n82),
.Z(n83) );
NOR2X1 U114 ( .A(slow_clk_counter[9]), .B(n83), .Z(n85) );
NAND3X1 U115 ( .A(n86), .B(n85), .C(n84), .Z(n87) );
NAND3X1 U116 ( .A(n89), .B(n88), .C(n87), .Z(n90) );
NOR2X1 U117 ( .A(n91), .B(n90), .Z(n92) );
OR2X1 U118 ( .A(button_data_in), .B(n92), .Z(n93) );
INVX1 U119 ( .A(button_lock), .Z(n99) );
NAND3X1 U120 ( .A(n98), .B(n93), .C(n99), .Z(n94) );
AND2X1 U121 ( .A(n94), .B(n101), .Z(n95) );
NOR2X1 U122 ( .A(reset), .B(n95), .Z(n96) );
MUX2X1 U123 ( .A(n97), .B(button_lock), .S(n96), .Z(n146) );
INVX1 U124 ( .A(n98), .Z(n100) );
NAND3X1 U125 ( .A(n101), .B(n100), .C(n99), .Z(n104) );
NAND2X1 U126 ( .A(nes_reset), .B(n102), .Z(n103) );
NAND2X1 U127 ( .A(n104), .B(n103), .Z(n145) );
endmodule
module Piece_Placer ( en, clk, rst, placed, we, addr, data, reg_1_addr,
reg_2_addr, reg_3_addr, reg_4_addr );
output [7:0] addr;
output [7:0] data;
output [7:0] reg_1_addr;
output [7:0] reg_2_addr;
output [7:0] reg_3_addr;
output [7:0] reg_4_addr;
input en, clk, rst;
output placed, we;
wire N32, N33, N34, N35, piece_gen, \block[11][2] , \block[11][0] ,
\block[10][2] , \block[10][1] , \block[10][0] , \block[9][2] ,
\block[9][1] , \block[9][0] , \block[8][2] , \block[7][2] ,
\block[7][1] , \block[7][0] , \block[6][2] , \block[6][1] ,
\block[6][0] , \block[4][2] , \block[4][1] , \block[4][0] ,
\block[3][2] , \block[3][1] , \block[3][0] , \block[0][0] , N133,
N134, N135, N136, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183;
wire [3:0] lfsr;
DFFQX1 \lfsr_reg[0] ( .D(N32), .CLK(clk), .Q(lfsr[0]) );
DFFQX1 \lfsr_reg[3] ( .D(N35), .CLK(clk), .Q(lfsr[3]) );
DFFQX1 \lfsr_reg[2] ( .D(N34), .CLK(clk), .Q(lfsr[2]) );
DFFQX1 \lfsr_reg[1] ( .D(N33), .CLK(clk), .Q(lfsr[1]) );
DFFQX1 piece_gen_reg ( .D(n262), .CLK(clk), .Q(piece_gen) );
DFFQX1 \reg_4_addr_reg[7] ( .D(n261), .CLK(clk), .Q(reg_4_addr[7]) );
DFFQX1 \reg_4_addr_reg[6] ( .D(n260), .CLK(clk), .Q(reg_4_addr[6]) );
DFFQX1 \reg_4_addr_reg[0] ( .D(n259), .CLK(clk), .Q(reg_4_addr[0]) );
DFFQX1 \reg_4_addr_reg[1] ( .D(n258), .CLK(clk), .Q(reg_4_addr[1]) );
DFFQX1 \reg_4_addr_reg[3] ( .D(n257), .CLK(clk), .Q(reg_4_addr[3]) );
DFFQX1 \reg_4_addr_reg[4] ( .D(n256), .CLK(clk), .Q(reg_4_addr[4]) );
DFFQX1 \reg_4_addr_reg[5] ( .D(n255), .CLK(clk), .Q(reg_4_addr[5]) );
DFFQX1 \block_reg[11][2] ( .D(n254), .CLK(clk), .Q(\block[11][2] ) );
DFFQX1 \block_reg[11][0] ( .D(n253), .CLK(clk), .Q(\block[11][0] ) );
DFFQX1 \block_reg[10][2] ( .D(n252), .CLK(clk), .Q(\block[10][2] ) );
DFFQX1 \block_reg[10][1] ( .D(n251), .CLK(clk), .Q(\block[10][1] ) );
DFFQX1 \block_reg[10][0] ( .D(n250), .CLK(clk), .Q(\block[10][0] ) );
DFFQX1 \block_reg[9][2] ( .D(n249), .CLK(clk), .Q(\block[9][2] ) );
DFFQX1 \block_reg[9][1] ( .D(n248), .CLK(clk), .Q(\block[9][1] ) );
DFFQX1 \block_reg[9][0] ( .D(n247), .CLK(clk), .Q(\block[9][0] ) );
DFFQX1 \block_reg[8][2] ( .D(n246), .CLK(clk), .Q(\block[8][2] ) );
DFFQX1 \block_reg[7][2] ( .D(n245), .CLK(clk), .Q(\block[7][2] ) );
DFFQX1 \block_reg[7][1] ( .D(n244), .CLK(clk), .Q(\block[7][1] ) );
DFFQX1 \block_reg[7][0] ( .D(n243), .CLK(clk), .Q(\block[7][0] ) );
DFFQX1 \block_reg[6][2] ( .D(n242), .CLK(clk), .Q(\block[6][2] ) );
DFFQX1 \block_reg[6][1] ( .D(n241), .CLK(clk), .Q(\block[6][1] ) );
DFFQX1 \block_reg[6][0] ( .D(n240), .CLK(clk), .Q(\block[6][0] ) );
DFFQX1 \block_reg[4][2] ( .D(n239), .CLK(clk), .Q(\block[4][2] ) );
DFFQX1 \block_reg[4][1] ( .D(n238), .CLK(clk), .Q(\block[4][1] ) );
DFFQX1 \block_reg[4][0] ( .D(n237), .CLK(clk), .Q(\block[4][0] ) );
DFFQX1 \block_reg[3][2] ( .D(n236), .CLK(clk), .Q(\block[3][2] ) );
DFFQX1 \block_reg[3][1] ( .D(n235), .CLK(clk), .Q(\block[3][1] ) );
DFFQX1 \block_reg[3][0] ( .D(n234), .CLK(clk), .Q(\block[3][0] ) );
DFFQX1 \block_reg[0][0] ( .D(n233), .CLK(clk), .Q(\block[0][0] ) );
DFFQX1 \reg_1_addr_reg[7] ( .D(n232), .CLK(clk), .Q(reg_1_addr[7]) );
DFFQX1 \reg_1_addr_reg[6] ( .D(n231), .CLK(clk), .Q(reg_1_addr[6]) );
DFFQX1 \reg_1_addr_reg[5] ( .D(n230), .CLK(clk), .Q(reg_1_addr[5]) );
DFFQX1 \reg_1_addr_reg[4] ( .D(n229), .CLK(clk), .Q(reg_1_addr[4]) );
DFFQX1 \reg_1_addr_reg[2] ( .D(n228), .CLK(clk), .Q(reg_1_addr[2]) );
DFFQX1 \reg_1_addr_reg[1] ( .D(n227), .CLK(clk), .Q(reg_1_addr[1]) );
DFFQX1 \reg_1_addr_reg[0] ( .D(n226), .CLK(clk), .Q(reg_1_addr[0]) );
DFFQX1 \reg_2_addr_reg[7] ( .D(n225), .CLK(clk), .Q(reg_2_addr[7]) );
DFFQX1 \reg_2_addr_reg[6] ( .D(n224), .CLK(clk), .Q(reg_2_addr[6]) );
DFFQX1 \reg_2_addr_reg[5] ( .D(n223), .CLK(clk), .Q(reg_2_addr[5]) );
DFFQX1 \reg_2_addr_reg[4] ( .D(n222), .CLK(clk), .Q(reg_2_addr[4]) );
DFFQX1 \reg_2_addr_reg[3] ( .D(n221), .CLK(clk), .Q(reg_2_addr[3]) );
DFFQX1 \reg_2_addr_reg[2] ( .D(n220), .CLK(clk), .Q(reg_2_addr[2]) );
DFFQX1 \reg_2_addr_reg[1] ( .D(n219), .CLK(clk), .Q(reg_2_addr[1]) );
DFFQX1 \reg_2_addr_reg[0] ( .D(n218), .CLK(clk), .Q(reg_2_addr[0]) );
DFFQX1 \reg_3_addr_reg[7] ( .D(n217), .CLK(clk), .Q(reg_3_addr[7]) );
DFFQX1 \reg_3_addr_reg[6] ( .D(n216), .CLK(clk), .Q(reg_3_addr[6]) );
DFFQX1 \reg_3_addr_reg[5] ( .D(n215), .CLK(clk), .Q(reg_3_addr[5]) );
DFFQX1 \reg_3_addr_reg[4] ( .D(n214), .CLK(clk), .Q(reg_3_addr[4]) );
DFFQX1 \reg_3_addr_reg[3] ( .D(n213), .CLK(clk), .Q(reg_3_addr[3]) );
DFFQX1 \reg_3_addr_reg[2] ( .D(n212), .CLK(clk), .Q(reg_3_addr[2]) );
DFFQX1 \reg_3_addr_reg[1] ( .D(n211), .CLK(clk), .Q(reg_3_addr[1]) );
DFFQX1 \reg_3_addr_reg[0] ( .D(n210), .CLK(clk), .Q(reg_3_addr[0]) );
DFFQX1 \box_number_reg[0] ( .D(n209), .CLK(clk), .Q(N133) );
DFFQX1 \box_number_reg[3] ( .D(n198), .CLK(clk), .Q(N136) );
DFFQX1 \box_number_reg[1] ( .D(n200), .CLK(clk), .Q(N134) );
DFFQX1 \box_number_reg[2] ( .D(n199), .CLK(clk), .Q(N135) );
DFFQX1 \data_reg[0] ( .D(n208), .CLK(clk), .Q(data[0]) );
DFFQX1 \data_reg[1] ( .D(n207), .CLK(clk), .Q(data[1]) );
DFFQX1 \data_reg[2] ( .D(n206), .CLK(clk), .Q(data[2]) );
DFFQX1 placed_reg ( .D(n197), .CLK(clk), .Q(placed) );
DFFQX1 we_reg ( .D(n196), .CLK(clk), .Q(we) );
DFFQX1 \addr_reg[7] ( .D(n195), .CLK(clk), .Q(addr[7]) );
DFFQX1 \addr_reg[6] ( .D(n194), .CLK(clk), .Q(addr[6]) );
DFFQX1 \addr_reg[5] ( .D(n193), .CLK(clk), .Q(addr[5]) );
DFFQX1 \addr_reg[4] ( .D(n192), .CLK(clk), .Q(addr[4]) );
DFFQX1 \addr_reg[3] ( .D(n191), .CLK(clk), .Q(addr[3]) );
DFFQX1 \addr_reg[2] ( .D(n190), .CLK(clk), .Q(addr[2]) );
DFFQX1 \addr_reg[1] ( .D(n189), .CLK(clk), .Q(addr[1]) );
DFFQX1 \addr_reg[0] ( .D(n188), .CLK(clk), .Q(addr[0]) );
INVX1 U3 ( .A(n160), .Z(n169) );
INVX1 U4 ( .A(n50), .Z(n74) );
INVX1 U5 ( .A(n91), .Z(n31) );
INVX1 U6 ( .A(n92), .Z(n70) );
INVX1 U7 ( .A(rst), .Z(n183) );
INVX1 U8 ( .A(lfsr[1]), .Z(n22) );
NAND2X1 U9 ( .A(n183), .B(n22), .Z(N32) );
INVX1 U10 ( .A(lfsr[0]), .Z(n23) );
INVX1 U11 ( .A(lfsr[2]), .Z(n37) );
XOR2X1 U12 ( .A(n23), .B(n37), .Z(n59) );
INVX1 U13 ( .A(lfsr[3]), .Z(n2) );
XOR2X1 U14 ( .A(n59), .B(n2), .Z(n1) );
NOR2X1 U15 ( .A(rst), .B(n1), .Z(N35) );
NOR2X1 U16 ( .A(rst), .B(n2), .Z(N34) );
NOR2X1 U17 ( .A(rst), .B(n37), .Z(N33) );
NAND2X1 U18 ( .A(en), .B(piece_gen), .Z(n181) );
INVX1 U19 ( .A(n181), .Z(n174) );
NAND2X1 U20 ( .A(n183), .B(n174), .Z(n153) );
NOR2X1 U21 ( .A(n23), .B(n37), .Z(n3) );
NAND2X1 U22 ( .A(n3), .B(lfsr[1]), .Z(n5) );
INVX1 U23 ( .A(piece_gen), .Z(n4) );
NAND3X1 U24 ( .A(en), .B(n183), .C(n4), .Z(n8) );
INVX1 U25 ( .A(n8), .Z(n84) );
NAND2X1 U26 ( .A(n5), .B(n84), .Z(n79) );
NAND2X1 U27 ( .A(n153), .B(n79), .Z(n262) );
INVX1 U28 ( .A(n153), .Z(n138) );
NAND2X1 U29 ( .A(n138), .B(reg_4_addr[7]), .Z(n6) );
NAND2X1 U30 ( .A(n6), .B(n79), .Z(n261) );
NAND2X1 U31 ( .A(n138), .B(reg_4_addr[6]), .Z(n7) );
NAND2X1 U32 ( .A(n7), .B(n79), .Z(n260) );
NAND2X1 U33 ( .A(n138), .B(reg_4_addr[0]), .Z(n9) );
NOR2X1 U34 ( .A(n8), .B(lfsr[1]), .Z(n50) );
NAND2X1 U35 ( .A(n23), .B(n50), .Z(n88) );
NAND2X1 U36 ( .A(n9), .B(n88), .Z(n259) );
NAND2X1 U37 ( .A(n138), .B(reg_4_addr[1]), .Z(n11) );
NAND2X1 U38 ( .A(lfsr[1]), .B(n84), .Z(n10) );
NOR2X1 U39 ( .A(n10), .B(lfsr[0]), .Z(n92) );
INVX1 U40 ( .A(n10), .Z(n30) );
NAND2X1 U41 ( .A(n37), .B(n30), .Z(n94) );
INVX1 U42 ( .A(n94), .Z(n26) );
NOR2X1 U43 ( .A(lfsr[0]), .B(lfsr[2]), .Z(n85) );
NOR2X1 U44 ( .A(n85), .B(n74), .Z(n69) );
NOR2X1 U45 ( .A(n26), .B(n69), .Z(n57) );
NAND3X1 U46 ( .A(n11), .B(n70), .C(n57), .Z(n258) );
NAND2X1 U47 ( .A(n138), .B(reg_4_addr[3]), .Z(n12) );
NAND2X1 U48 ( .A(n12), .B(n79), .Z(n257) );
NAND2X1 U49 ( .A(n138), .B(reg_4_addr[4]), .Z(n13) );
NAND2X1 U50 ( .A(n13), .B(n79), .Z(n256) );
NAND2X1 U51 ( .A(n138), .B(reg_4_addr[5]), .Z(n14) );
NAND2X1 U52 ( .A(n14), .B(n79), .Z(n255) );
NAND2X1 U53 ( .A(\block[11][2] ), .B(n138), .Z(n15) );
OR2X1 U54 ( .A(n37), .B(n88), .Z(n33) );
NAND2X1 U55 ( .A(n15), .B(n33), .Z(n254) );
NAND2X1 U56 ( .A(\block[11][0] ), .B(n138), .Z(n16) );
NAND2X1 U57 ( .A(n16), .B(n33), .Z(n253) );
NAND2X1 U58 ( .A(\block[10][2] ), .B(n138), .Z(n17) );
NAND2X1 U59 ( .A(n30), .B(n59), .Z(n82) );
NAND2X1 U60 ( .A(lfsr[2]), .B(n50), .Z(n28) );
NAND3X1 U61 ( .A(n17), .B(n82), .C(n28), .Z(n252) );
NAND2X1 U62 ( .A(\block[10][1] ), .B(n138), .Z(n18) );
NOR2X1 U63 ( .A(n23), .B(n74), .Z(n91) );
NAND3X1 U64 ( .A(n18), .B(n70), .C(n31), .Z(n251) );
NAND2X1 U65 ( .A(\block[10][0] ), .B(n138), .Z(n19) );
NAND2X1 U66 ( .A(n23), .B(n84), .Z(n72) );
OR2X1 U67 ( .A(n37), .B(n72), .Z(n35) );
NAND3X1 U68 ( .A(n19), .B(n70), .C(n35), .Z(n250) );
NAND2X1 U69 ( .A(\block[9][2] ), .B(n138), .Z(n20) );
NAND2X1 U70 ( .A(lfsr[2]), .B(n91), .Z(n42) );
NAND3X1 U71 ( .A(n20), .B(n82), .C(n42), .Z(n249) );
NAND2X1 U72 ( .A(\block[9][1] ), .B(n138), .Z(n21) );
NAND2X1 U73 ( .A(n92), .B(lfsr[2]), .Z(n46) );
NAND3X1 U74 ( .A(n21), .B(n31), .C(n46), .Z(n248) );
XOR2X1 U75 ( .A(lfsr[2]), .B(n22), .Z(n24) );
NAND3X1 U76 ( .A(n24), .B(n84), .C(n23), .Z(n48) );
NAND2X1 U77 ( .A(n138), .B(\block[9][0] ), .Z(n25) );
NAND2X1 U78 ( .A(n48), .B(n25), .Z(n247) );
NAND2X1 U79 ( .A(\block[8][2] ), .B(n138), .Z(n27) );
NAND2X1 U80 ( .A(lfsr[0]), .B(n26), .Z(n67) );
NAND2X1 U81 ( .A(n27), .B(n67), .Z(n246) );
NAND2X1 U82 ( .A(\block[7][2] ), .B(n138), .Z(n29) );
NAND3X1 U83 ( .A(n29), .B(n28), .C(n67), .Z(n245) );
NAND2X1 U84 ( .A(\block[7][1] ), .B(n138), .Z(n32) );
NAND2X1 U85 ( .A(n30), .B(n85), .Z(n89) );
NAND3X1 U86 ( .A(n32), .B(n31), .C(n89), .Z(n244) );
NAND2X1 U87 ( .A(\block[7][0] ), .B(n138), .Z(n34) );
NAND3X1 U88 ( .A(n34), .B(n33), .C(n89), .Z(n243) );
NAND2X1 U89 ( .A(\block[6][2] ), .B(n138), .Z(n36) );
NAND2X1 U90 ( .A(n36), .B(n35), .Z(n242) );
NAND2X1 U91 ( .A(\block[6][1] ), .B(n138), .Z(n39) );
NAND2X1 U92 ( .A(n91), .B(n37), .Z(n38) );
NAND3X1 U93 ( .A(n39), .B(n70), .C(n38), .Z(n241) );
NAND2X1 U94 ( .A(\block[6][0] ), .B(n138), .Z(n40) );
NAND2X1 U95 ( .A(n40), .B(n72), .Z(n240) );
NAND2X1 U96 ( .A(\block[4][2] ), .B(n138), .Z(n41) );
NAND2X1 U97 ( .A(n41), .B(n42), .Z(n239) );
NAND2X1 U98 ( .A(\block[4][1] ), .B(n138), .Z(n43) );
NAND3X1 U99 ( .A(n43), .B(n42), .C(n89), .Z(n238) );
NAND2X1 U100 ( .A(\block[4][0] ), .B(n138), .Z(n44) );
NAND2X1 U101 ( .A(n44), .B(n89), .Z(n237) );
NAND2X1 U102 ( .A(\block[3][2] ), .B(n138), .Z(n45) );
NAND2X1 U103 ( .A(n45), .B(n46), .Z(n236) );
NAND2X1 U104 ( .A(\block[3][1] ), .B(n138), .Z(n47) );
NAND2X1 U105 ( .A(n47), .B(n46), .Z(n235) );
NAND2X1 U106 ( .A(\block[3][0] ), .B(n138), .Z(n49) );
NAND2X1 U107 ( .A(n49), .B(n48), .Z(n234) );
NAND2X1 U108 ( .A(n85), .B(n50), .Z(n52) );
NAND2X1 U109 ( .A(\block[0][0] ), .B(n138), .Z(n51) );
NAND2X1 U110 ( .A(n52), .B(n51), .Z(n233) );
NAND2X1 U111 ( .A(n138), .B(reg_1_addr[7]), .Z(n53) );
NAND2X1 U112 ( .A(n53), .B(n79), .Z(n232) );
NAND2X1 U113 ( .A(n138), .B(reg_1_addr[6]), .Z(n54) );
NAND2X1 U114 ( .A(n54), .B(n79), .Z(n231) );
NAND2X1 U115 ( .A(n138), .B(reg_1_addr[5]), .Z(n55) );
NAND2X1 U116 ( .A(n55), .B(n79), .Z(n230) );
NAND2X1 U117 ( .A(n138), .B(reg_1_addr[4]), .Z(n56) );
NAND2X1 U118 ( .A(n56), .B(n79), .Z(n229) );
NAND2X1 U119 ( .A(reg_1_addr[2]), .B(n138), .Z(n58) );
NAND2X1 U120 ( .A(n58), .B(n57), .Z(n228) );
NAND2X1 U121 ( .A(n59), .B(n84), .Z(n61) );
NAND2X1 U122 ( .A(reg_1_addr[1]), .B(n138), .Z(n60) );
NAND2X1 U123 ( .A(n61), .B(n60), .Z(n227) );
NAND2X1 U124 ( .A(n138), .B(reg_1_addr[0]), .Z(n62) );
NAND2X1 U125 ( .A(n62), .B(n82), .Z(n226) );
NAND2X1 U126 ( .A(n138), .B(reg_2_addr[7]), .Z(n63) );
NAND2X1 U127 ( .A(n63), .B(n79), .Z(n225) );
NAND2X1 U128 ( .A(n138), .B(reg_2_addr[6]), .Z(n64) );
NAND2X1 U129 ( .A(n64), .B(n79), .Z(n224) );
NAND2X1 U130 ( .A(n138), .B(reg_2_addr[5]), .Z(n65) );
NAND2X1 U131 ( .A(n65), .B(n79), .Z(n223) );
NAND2X1 U132 ( .A(n138), .B(reg_2_addr[4]), .Z(n66) );
NAND2X1 U133 ( .A(n66), .B(n79), .Z(n222) );
NAND2X1 U134 ( .A(n138), .B(reg_2_addr[3]), .Z(n68) );
NAND2X1 U135 ( .A(n68), .B(n67), .Z(n221) );
NAND2X1 U136 ( .A(n138), .B(reg_2_addr[2]), .Z(n71) );
INVX1 U137 ( .A(n69), .Z(n81) );
NAND3X1 U138 ( .A(n71), .B(n81), .C(n70), .Z(n220) );
NAND2X1 U139 ( .A(n138), .B(reg_2_addr[1]), .Z(n73) );
NAND3X1 U140 ( .A(n73), .B(n72), .C(n74), .Z(n219) );
NAND2X1 U141 ( .A(n138), .B(reg_2_addr[0]), .Z(n75) );
NAND2X1 U142 ( .A(n75), .B(n74), .Z(n218) );
NAND2X1 U143 ( .A(n138), .B(reg_3_addr[7]), .Z(n76) );
NAND2X1 U144 ( .A(n76), .B(n79), .Z(n217) );
NAND2X1 U145 ( .A(n138), .B(reg_3_addr[6]), .Z(n77) );
NAND2X1 U146 ( .A(n77), .B(n79), .Z(n216) );
NAND2X1 U147 ( .A(n138), .B(reg_3_addr[5]), .Z(n78) );
NAND2X1 U148 ( .A(n78), .B(n79), .Z(n215) );
NAND2X1 U149 ( .A(n138), .B(reg_3_addr[4]), .Z(n80) );
NAND2X1 U150 ( .A(n80), .B(n79), .Z(n214) );
NAND2X1 U151 ( .A(n138), .B(reg_3_addr[3]), .Z(n83) );
NAND3X1 U152 ( .A(n83), .B(n82), .C(n81), .Z(n213) );
NAND2X1 U153 ( .A(n85), .B(n84), .Z(n87) );
NAND2X1 U154 ( .A(reg_3_addr[2]), .B(n138), .Z(n86) );
NAND2X1 U155 ( .A(n87), .B(n86), .Z(n212) );
NAND2X1 U156 ( .A(n138), .B(reg_3_addr[1]), .Z(n90) );
NAND3X1 U157 ( .A(n90), .B(n89), .C(n88), .Z(n211) );
NAND2X1 U158 ( .A(n138), .B(reg_3_addr[0]), .Z(n95) );
NOR2X1 U159 ( .A(n92), .B(n91), .Z(n93) );
NAND3X1 U160 ( .A(n95), .B(n94), .C(n93), .Z(n210) );
NOR2X1 U161 ( .A(rst), .B(n174), .Z(n176) );
INVX1 U162 ( .A(N135), .Z(n104) );
INVX1 U163 ( .A(N136), .Z(n128) );
NOR2X1 U164 ( .A(n104), .B(n128), .Z(n96) );
NOR2X1 U165 ( .A(n153), .B(n96), .Z(n160) );
INVX1 U166 ( .A(N133), .Z(n148) );
MUX2X1 U167 ( .A(n176), .B(n160), .S(n148), .Z(n209) );
NAND2X1 U168 ( .A(n176), .B(data[0]), .Z(n115) );
INVX1 U169 ( .A(N134), .Z(n154) );
MUX2X1 U170 ( .A(\block[11][0] ), .B(\block[9][0] ), .S(n154), .Z(n98) );
AND2X1 U171 ( .A(\block[3][0] ), .B(N134), .Z(n97) );
MUX2X1 U172 ( .A(n98), .B(n97), .S(n128), .Z(n99) );
NAND2X1 U173 ( .A(N133), .B(n99), .Z(n102) );
NAND2X1 U174 ( .A(n148), .B(n154), .Z(n105) );
INVX1 U175 ( .A(n105), .Z(n166) );
NAND3X1 U176 ( .A(n166), .B(\block[0][0] ), .C(n128), .Z(n101) );
NAND2X1 U177 ( .A(n148), .B(N134), .Z(n107) );
INVX1 U178 ( .A(n107), .Z(n139) );
NAND3X1 U179 ( .A(N136), .B(n139), .C(\block[10][0] ), .Z(n100) );
NAND3X1 U180 ( .A(n102), .B(n101), .C(n100), .Z(n103) );
NAND2X1 U181 ( .A(n104), .B(n103), .Z(n112) );
NAND2X1 U182 ( .A(N133), .B(N134), .Z(n152) );
NAND2X1 U183 ( .A(N135), .B(n128), .Z(n106) );
NOR2X1 U184 ( .A(n152), .B(n106), .Z(n161) );
NAND2X1 U185 ( .A(n161), .B(\block[7][0] ), .Z(n111) );
NOR2X1 U186 ( .A(n105), .B(n106), .Z(n130) );
NAND2X1 U187 ( .A(\block[4][0] ), .B(n130), .Z(n109) );
NOR2X1 U188 ( .A(n107), .B(n106), .Z(n131) );
NAND2X1 U189 ( .A(\block[6][0] ), .B(n131), .Z(n108) );
AND2X1 U190 ( .A(n109), .B(n108), .Z(n110) );
NAND3X1 U191 ( .A(n112), .B(n111), .C(n110), .Z(n113) );
NAND2X1 U192 ( .A(n138), .B(n113), .Z(n114) );
NAND2X1 U193 ( .A(n115), .B(n114), .Z(n208) );
NAND2X1 U194 ( .A(n176), .B(data[1]), .Z(n127) );
NAND2X1 U195 ( .A(n138), .B(N136), .Z(n177) );
NOR2X1 U196 ( .A(n177), .B(N135), .Z(n159) );
NAND2X1 U197 ( .A(n139), .B(\block[10][1] ), .Z(n117) );
NAND3X1 U198 ( .A(N133), .B(\block[9][1] ), .C(n154), .Z(n116) );
NAND2X1 U199 ( .A(n117), .B(n116), .Z(n118) );
NAND2X1 U200 ( .A(n159), .B(n118), .Z(n126) );
NAND2X1 U201 ( .A(n161), .B(\block[7][1] ), .Z(n123) );
NAND2X1 U202 ( .A(\block[4][1] ), .B(n130), .Z(n120) );
NAND2X1 U203 ( .A(\block[6][1] ), .B(n131), .Z(n119) );
AND2X1 U204 ( .A(n120), .B(n119), .Z(n122) );
NOR2X1 U205 ( .A(N135), .B(n152), .Z(n129) );
NAND3X1 U206 ( .A(n129), .B(\block[3][1] ), .C(n128), .Z(n121) );
NAND3X1 U207 ( .A(n123), .B(n122), .C(n121), .Z(n124) );
NAND2X1 U208 ( .A(n124), .B(n138), .Z(n125) );
NAND3X1 U209 ( .A(n127), .B(n126), .C(n125), .Z(n207) );
NAND2X1 U210 ( .A(n161), .B(\block[7][2] ), .Z(n136) );
NAND3X1 U211 ( .A(n129), .B(\block[3][2] ), .C(n128), .Z(n135) );
NAND2X1 U212 ( .A(\block[4][2] ), .B(n130), .Z(n133) );
NAND2X1 U213 ( .A(\block[6][2] ), .B(n131), .Z(n132) );
AND2X1 U214 ( .A(n133), .B(n132), .Z(n134) );
NAND3X1 U215 ( .A(n136), .B(n135), .C(n134), .Z(n137) );
NAND2X1 U216 ( .A(n138), .B(n137), .Z(n147) );
NAND2X1 U217 ( .A(n176), .B(data[2]), .Z(n146) );
NAND2X1 U218 ( .A(n139), .B(\block[10][2] ), .Z(n143) );
NAND2X1 U219 ( .A(n166), .B(\block[8][2] ), .Z(n142) );
MUX2X1 U220 ( .A(\block[11][2] ), .B(\block[9][2] ), .S(n154), .Z(n140) );
NAND2X1 U221 ( .A(N133), .B(n140), .Z(n141) );
NAND3X1 U222 ( .A(n143), .B(n142), .C(n141), .Z(n144) );
NAND2X1 U223 ( .A(n159), .B(n144), .Z(n145) );
NAND3X1 U224 ( .A(n147), .B(n146), .C(n145), .Z(n206) );
NOR2X1 U225 ( .A(n148), .B(n169), .Z(n151) );
NOR2X1 U226 ( .A(N133), .B(n169), .Z(n149) );
NOR2X1 U227 ( .A(n176), .B(n149), .Z(n155) );
INVX1 U228 ( .A(n155), .Z(n150) );
MUX2X1 U229 ( .A(n151), .B(n150), .S(N134), .Z(n200) );
NOR2X1 U230 ( .A(n153), .B(n152), .Z(n157) );
NAND2X1 U231 ( .A(n160), .B(n154), .Z(n156) );
NAND2X1 U232 ( .A(n156), .B(n155), .Z(n158) );
MUX2X1 U233 ( .A(n157), .B(n158), .S(N135), .Z(n199) );
NAND2X1 U234 ( .A(N136), .B(n158), .Z(n164) );
INVX1 U235 ( .A(n159), .Z(n163) );
NAND2X1 U236 ( .A(n161), .B(n160), .Z(n162) );
NAND3X1 U237 ( .A(n164), .B(n163), .C(n162), .Z(n198) );
NAND2X1 U238 ( .A(n176), .B(placed), .Z(n168) );
INVX1 U239 ( .A(n177), .Z(n165) );
NAND3X1 U240 ( .A(N135), .B(n166), .C(n165), .Z(n167) );
NAND2X1 U241 ( .A(n168), .B(n167), .Z(n197) );
NAND2X1 U242 ( .A(n176), .B(we), .Z(n170) );
NAND2X1 U243 ( .A(n170), .B(n169), .Z(n196) );
NOR2X1 U244 ( .A(n174), .B(addr[7]), .Z(n171) );
NOR2X1 U245 ( .A(rst), .B(n171), .Z(n195) );
NOR2X1 U246 ( .A(n174), .B(addr[6]), .Z(n172) );
NOR2X1 U247 ( .A(rst), .B(n172), .Z(n194) );
NOR2X1 U248 ( .A(n174), .B(addr[5]), .Z(n173) );
NOR2X1 U249 ( .A(rst), .B(n173), .Z(n193) );
NOR2X1 U250 ( .A(n174), .B(addr[4]), .Z(n175) );
NOR2X1 U251 ( .A(rst), .B(n175), .Z(n192) );
NAND2X1 U252 ( .A(n176), .B(addr[3]), .Z(n178) );
NAND2X1 U253 ( .A(n178), .B(n177), .Z(n191) );
MUX2X1 U254 ( .A(N135), .B(addr[2]), .S(n181), .Z(n179) );
AND2X1 U255 ( .A(n183), .B(n179), .Z(n190) );
MUX2X1 U256 ( .A(N134), .B(addr[1]), .S(n181), .Z(n180) );
AND2X1 U257 ( .A(n183), .B(n180), .Z(n189) );
MUX2X1 U258 ( .A(N133), .B(addr[0]), .S(n181), .Z(n182) );
AND2X1 U259 ( .A(n183), .B(n182), .Z(n188) );
endmodule
module Line_Clearer ( en, clk, rst, data_in, cleared, we, addr, data_out );
input [7:0] data_in;
output [7:0] addr;
output [7:0] data_out;
input en, clk, rst;
output cleared, we;
wire check_line, clear_line, line_cleared, N443, N445, N446, N447, N448,
advance_line, N748, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n396, n397, n398, n399, n400, n401, n402, n404, n405,
n406, n407, n408, n409, n410, n411, n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248,
n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270,
n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n395, n403, n412, n413, n414, n415, n416,
n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438,
n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501;
wire [7:0] check_addr;
wire [7:0] shift_addr;
wire [7:0] current_shift_line;
wire [5:0] clear_state;
wire [7:0] data;
wire [3:0] addr_cnt;
wire [7:0] current_line;
wire [3:0] block_count;
wire [3:0] check_block_number;
wire [4:0] line_iterator;
DFFQX1 \line_iterator_reg[0] ( .D(n411), .CLK(clk), .Q(line_iterator[0]) );
DFFQX1 \line_iterator_reg[4] ( .D(n410), .CLK(clk), .Q(line_iterator[4]) );
DFFQX1 \line_iterator_reg[3] ( .D(n407), .CLK(clk), .Q(line_iterator[3]) );
DFFQX1 \line_iterator_reg[2] ( .D(n406), .CLK(clk), .Q(line_iterator[2]) );
DFFQX1 \line_iterator_reg[1] ( .D(n405), .CLK(clk), .Q(line_iterator[1]) );
DFFQX1 \current_line_reg[0] ( .D(n404), .CLK(clk), .Q(N748) );
DFFQX1 \current_line_reg[2] ( .D(n402), .CLK(clk), .Q(current_line[2]) );
DFFQX1 \current_line_reg[3] ( .D(n401), .CLK(clk), .Q(current_line[3]) );
DFFQX1 \current_line_reg[4] ( .D(n400), .CLK(clk), .Q(current_line[4]) );
DFFQX1 \current_line_reg[5] ( .D(n399), .CLK(clk), .Q(current_line[5]) );
DFFQX1 \current_line_reg[6] ( .D(n398), .CLK(clk), .Q(current_line[6]) );
DFFQX1 \current_line_reg[7] ( .D(n397), .CLK(clk), .Q(current_line[7]) );
DFFQX1 \current_shift_line_reg[7] ( .D(n388), .CLK(clk), .Q(
current_shift_line[7]) );
DFFQX1 line_cleared_reg ( .D(n359), .CLK(clk), .Q(line_cleared) );
DFFQX1 \check_block_number_reg[0] ( .D(n357), .CLK(clk), .Q(
check_block_number[0]) );
DFFQX1 \check_block_number_reg[1] ( .D(n356), .CLK(clk), .Q(
check_block_number[1]) );
DFFQX1 \check_block_number_reg[2] ( .D(n355), .CLK(clk), .Q(
check_block_number[2]) );
DFFQX1 \check_block_number_reg[3] ( .D(n354), .CLK(clk), .Q(
check_block_number[3]) );
DFFQX1 \block_count_reg[2] ( .D(n342), .CLK(clk), .Q(block_count[2]) );
DFFQX1 \block_count_reg[3] ( .D(n345), .CLK(clk), .Q(block_count[3]) );
DFFQX1 advance_line_reg ( .D(n408), .CLK(clk), .Q(advance_line) );
DFFQX1 check_line_reg ( .D(n409), .CLK(clk), .Q(check_line) );
DFFQX1 clear_line_reg ( .D(n396), .CLK(clk), .Q(clear_line) );
DFFQX1 \clear_state_reg[0] ( .D(N443), .CLK(clk), .Q(clear_state[0]) );
DFFQX1 \clear_state_reg[1] ( .D(n501), .CLK(clk), .Q(clear_state[1]) );
DFFQX1 \clear_state_reg[2] ( .D(N445), .CLK(clk), .Q(clear_state[2]) );
DFFQX1 \clear_state_reg[3] ( .D(N446), .CLK(clk), .Q(clear_state[3]) );
DFFQX1 \clear_state_reg[4] ( .D(N447), .CLK(clk), .Q(clear_state[4]) );
DFFQX1 \clear_state_reg[5] ( .D(N448), .CLK(clk), .Q(clear_state[5]) );
DFFQX1 \current_shift_line_reg[0] ( .D(n394), .CLK(clk), .Q(
current_shift_line[0]) );
DFFQX1 \current_shift_line_reg[2] ( .D(n393), .CLK(clk), .Q(
current_shift_line[2]) );
DFFQX1 \current_shift_line_reg[3] ( .D(n392), .CLK(clk), .Q(
current_shift_line[3]) );
DFFQX1 \current_shift_line_reg[4] ( .D(n391), .CLK(clk), .Q(
current_shift_line[4]) );
DFFQX1 \current_shift_line_reg[5] ( .D(n390), .CLK(clk), .Q(
current_shift_line[5]) );
DFFQX1 \current_shift_line_reg[6] ( .D(n389), .CLK(clk), .Q(
current_shift_line[6]) );
DFFQX1 \shift_addr_reg[0] ( .D(n383), .CLK(clk), .Q(shift_addr[0]) );
DFFQX1 \shift_addr_reg[1] ( .D(n382), .CLK(clk), .Q(shift_addr[1]) );
DFFQX1 \shift_addr_reg[2] ( .D(n381), .CLK(clk), .Q(shift_addr[2]) );
DFFQX1 \shift_addr_reg[3] ( .D(n380), .CLK(clk), .Q(shift_addr[3]) );
DFFQX1 \shift_addr_reg[4] ( .D(n379), .CLK(clk), .Q(shift_addr[4]) );
DFFQX1 \shift_addr_reg[5] ( .D(n378), .CLK(clk), .Q(shift_addr[5]) );
DFFQX1 \shift_addr_reg[6] ( .D(n377), .CLK(clk), .Q(shift_addr[6]) );
DFFQX1 \shift_addr_reg[7] ( .D(n376), .CLK(clk), .Q(shift_addr[7]) );
DFFQX1 \addr_cnt_reg[0] ( .D(n387), .CLK(clk), .Q(addr_cnt[0]) );
DFFQX1 \addr_cnt_reg[1] ( .D(n386), .CLK(clk), .Q(addr_cnt[1]) );
DFFQX1 \addr_cnt_reg[2] ( .D(n385), .CLK(clk), .Q(addr_cnt[2]) );
DFFQX1 \addr_cnt_reg[3] ( .D(n384), .CLK(clk), .Q(addr_cnt[3]) );
DFFQX1 \data_reg[0] ( .D(n375), .CLK(clk), .Q(data[0]) );
DFFQX1 \data_out_reg[0] ( .D(n367), .CLK(clk), .Q(data_out[0]) );
DFFQX1 \data_reg[1] ( .D(n374), .CLK(clk), .Q(data[1]) );
DFFQX1 \data_out_reg[1] ( .D(n366), .CLK(clk), .Q(data_out[1]) );
DFFQX1 \data_reg[2] ( .D(n373), .CLK(clk), .Q(data[2]) );
DFFQX1 \data_out_reg[2] ( .D(n365), .CLK(clk), .Q(data_out[2]) );
DFFQX1 \data_reg[3] ( .D(n372), .CLK(clk), .Q(data[3]) );
DFFQX1 \data_out_reg[3] ( .D(n364), .CLK(clk), .Q(data_out[3]) );
DFFQX1 \data_reg[4] ( .D(n371), .CLK(clk), .Q(data[4]) );
DFFQX1 \data_out_reg[4] ( .D(n363), .CLK(clk), .Q(data_out[4]) );
DFFQX1 \data_reg[5] ( .D(n370), .CLK(clk), .Q(data[5]) );
DFFQX1 \data_out_reg[5] ( .D(n362), .CLK(clk), .Q(data_out[5]) );
DFFQX1 \data_reg[6] ( .D(n369), .CLK(clk), .Q(data[6]) );
DFFQX1 \data_out_reg[6] ( .D(n361), .CLK(clk), .Q(data_out[6]) );
DFFQX1 \data_reg[7] ( .D(n368), .CLK(clk), .Q(data[7]) );
DFFQX1 \data_out_reg[7] ( .D(n360), .CLK(clk), .Q(data_out[7]) );
DFFQX1 we_reg ( .D(n358), .CLK(clk), .Q(we) );
DFFQX1 \check_addr_reg[0] ( .D(n352), .CLK(clk), .Q(check_addr[0]) );
DFFQX1 \check_addr_reg[1] ( .D(n351), .CLK(clk), .Q(check_addr[1]) );
DFFQX1 \check_addr_reg[2] ( .D(n350), .CLK(clk), .Q(check_addr[2]) );
DFFQX1 \check_addr_reg[3] ( .D(n349), .CLK(clk), .Q(check_addr[3]) );
DFFQX1 \check_addr_reg[4] ( .D(n348), .CLK(clk), .Q(check_addr[4]) );
DFFQX1 \check_addr_reg[5] ( .D(n347), .CLK(clk), .Q(check_addr[5]) );
DFFQX1 \check_addr_reg[6] ( .D(n346), .CLK(clk), .Q(check_addr[6]) );
DFFQX1 \block_count_reg[0] ( .D(n344), .CLK(clk), .Q(block_count[0]) );
DFFQX1 \block_count_reg[1] ( .D(n343), .CLK(clk), .Q(block_count[1]) );
DFFQX1 \check_addr_reg[7] ( .D(n353), .CLK(clk), .Q(check_addr[7]) );
DFFQX1 cleared_reg ( .D(n341), .CLK(clk), .Q(cleared) );
INVX1 U3 ( .A(n257), .Z(n259) );
INVX1 U4 ( .A(n313), .Z(n163) );
INVX1 U5 ( .A(n117), .Z(n49) );
INVX1 U6 ( .A(n74), .Z(n334) );
INVX1 U7 ( .A(n177), .Z(n168) );
INVX1 U8 ( .A(n499), .Z(n59) );
INVX1 U9 ( .A(n133), .Z(n148) );
INVX1 U10 ( .A(rst), .Z(n53) );
INVX1 U11 ( .A(n419), .Z(n195) );
INVX1 U12 ( .A(n307), .Z(n213) );
INVX1 U13 ( .A(n190), .Z(n182) );
INVX1 U14 ( .A(n156), .Z(n111) );
INVX1 U15 ( .A(n122), .Z(n149) );
INVX1 U16 ( .A(n89), .Z(n90) );
NAND2X1 U17 ( .A(clear_line), .B(n53), .Z(n206) );
INVX1 U18 ( .A(clear_state[4]), .Z(n68) );
INVX1 U19 ( .A(clear_state[2]), .Z(n2) );
INVX1 U20 ( .A(clear_state[3]), .Z(n1) );
NAND3X1 U21 ( .A(n68), .B(n2), .C(n1), .Z(n3) );
NOR2X1 U22 ( .A(clear_state[5]), .B(n3), .Z(n14) );
INVX1 U23 ( .A(n14), .Z(n6) );
NOR2X1 U24 ( .A(clear_state[1]), .B(clear_state[0]), .Z(n5) );
NAND2X1 U25 ( .A(clear_state[4]), .B(clear_state[5]), .Z(n4) );
NAND3X1 U26 ( .A(n6), .B(n5), .C(n4), .Z(n74) );
NOR2X1 U27 ( .A(n206), .B(n74), .Z(n419) );
INVX1 U28 ( .A(clear_state[0]), .Z(n72) );
NAND2X1 U29 ( .A(clear_state[2]), .B(clear_state[3]), .Z(n67) );
NOR2X1 U30 ( .A(n72), .B(n67), .Z(n8) );
INVX1 U31 ( .A(clear_state[5]), .Z(n12) );
NOR2X1 U32 ( .A(clear_state[1]), .B(n12), .Z(n7) );
NAND3X1 U33 ( .A(n8), .B(n7), .C(n68), .Z(n9) );
INVX1 U34 ( .A(n9), .Z(n164) );
NOR2X1 U35 ( .A(n334), .B(n164), .Z(n426) );
INVX1 U36 ( .A(clear_state[1]), .Z(n71) );
NOR2X1 U37 ( .A(n71), .B(n67), .Z(n10) );
NOR2X1 U38 ( .A(clear_state[4]), .B(n10), .Z(n11) );
NOR2X1 U39 ( .A(n12), .B(n11), .Z(n13) );
NOR2X1 U40 ( .A(n206), .B(n13), .Z(n314) );
NAND3X1 U41 ( .A(n14), .B(n71), .C(n72), .Z(n160) );
AND2X1 U42 ( .A(n314), .B(n160), .Z(n422) );
NAND2X1 U43 ( .A(n426), .B(n422), .Z(n34) );
MUX2X1 U44 ( .A(n195), .B(n34), .S(addr_cnt[0]), .Z(n15) );
INVX1 U45 ( .A(n15), .Z(n387) );
NAND2X1 U46 ( .A(check_line), .B(n53), .Z(n117) );
NOR2X1 U47 ( .A(check_block_number[1]), .B(check_block_number[3]), .Z(n16)
);
MUX2X1 U48 ( .A(n16), .B(check_block_number[3]), .S(check_block_number[2]),
.Z(n45) );
NOR2X1 U49 ( .A(n117), .B(n45), .Z(n26) );
NOR2X1 U50 ( .A(data_in[6]), .B(data_in[7]), .Z(n21) );
NOR2X1 U51 ( .A(data_in[1]), .B(data_in[0]), .Z(n18) );
NOR2X1 U52 ( .A(data_in[3]), .B(data_in[2]), .Z(n17) );
AND2X1 U53 ( .A(n18), .B(n17), .Z(n20) );
NOR2X1 U54 ( .A(data_in[5]), .B(data_in[4]), .Z(n19) );
NAND3X1 U55 ( .A(n21), .B(n20), .C(n19), .Z(n28) );
NAND2X1 U56 ( .A(n26), .B(n28), .Z(n31) );
INVX1 U57 ( .A(n31), .Z(n492) );
AND2X1 U58 ( .A(block_count[0]), .B(n492), .Z(n494) );
NAND2X1 U59 ( .A(block_count[1]), .B(n494), .Z(n484) );
MUX2X1 U60 ( .A(check_block_number[0]), .B(check_block_number[2]), .S(
check_block_number[3]), .Z(n24) );
INVX1 U61 ( .A(check_block_number[1]), .Z(n23) );
NAND2X1 U62 ( .A(check_block_number[2]), .B(check_block_number[0]), .Z(n22)
);
NAND3X1 U63 ( .A(n24), .B(n23), .C(n22), .Z(n25) );
NOR2X1 U64 ( .A(n117), .B(n25), .Z(n38) );
INVX1 U65 ( .A(n26), .Z(n27) );
NOR2X1 U66 ( .A(n28), .B(n27), .Z(n29) );
NOR2X1 U67 ( .A(n38), .B(n29), .Z(n490) );
OR2X1 U68 ( .A(block_count[0]), .B(n31), .Z(n30) );
NAND2X1 U69 ( .A(n490), .B(n30), .Z(n493) );
NOR2X1 U70 ( .A(n31), .B(block_count[1]), .Z(n32) );
NOR2X1 U71 ( .A(n493), .B(n32), .Z(n486) );
MUX2X1 U72 ( .A(n484), .B(n486), .S(block_count[2]), .Z(n33) );
INVX1 U73 ( .A(n33), .Z(n342) );
NAND3X1 U74 ( .A(addr_cnt[1]), .B(addr_cnt[0]), .C(n419), .Z(n200) );
INVX1 U75 ( .A(addr_cnt[0]), .Z(n226) );
NAND2X1 U76 ( .A(n419), .B(n226), .Z(n35) );
NAND2X1 U77 ( .A(n35), .B(n34), .Z(n196) );
NOR2X1 U78 ( .A(n195), .B(addr_cnt[1]), .Z(n36) );
NOR2X1 U79 ( .A(n196), .B(n36), .Z(n199) );
MUX2X1 U80 ( .A(n200), .B(n199), .S(addr_cnt[2]), .Z(n37) );
INVX1 U81 ( .A(n37), .Z(n385) );
NOR2X1 U82 ( .A(check_block_number[2]), .B(check_block_number[3]), .Z(n47)
);
NAND2X1 U83 ( .A(check_block_number[0]), .B(n47), .Z(n44) );
NAND2X1 U84 ( .A(n38), .B(n44), .Z(n462) );
NOR2X1 U85 ( .A(block_count[2]), .B(clear_line), .Z(n41) );
INVX1 U86 ( .A(block_count[1]), .Z(n39) );
NOR2X1 U87 ( .A(block_count[0]), .B(n39), .Z(n40) );
NAND3X1 U88 ( .A(n41), .B(n40), .C(block_count[3]), .Z(n156) );
NOR2X1 U89 ( .A(n462), .B(n156), .Z(n43) );
INVX1 U90 ( .A(clear_line), .Z(n100) );
OR2X1 U91 ( .A(line_cleared), .B(n100), .Z(n112) );
NOR2X1 U92 ( .A(n462), .B(n112), .Z(n42) );
NOR2X1 U93 ( .A(n43), .B(n42), .Z(n433) );
NAND2X1 U94 ( .A(n45), .B(n44), .Z(n46) );
NAND2X1 U95 ( .A(n46), .B(n49), .Z(n91) );
NOR2X1 U96 ( .A(check_block_number[1]), .B(check_block_number[0]), .Z(n51)
);
AND2X1 U97 ( .A(n51), .B(n47), .Z(n48) );
NAND2X1 U98 ( .A(n49), .B(n48), .Z(n440) );
NAND3X1 U99 ( .A(n462), .B(n91), .C(n440), .Z(n50) );
NAND2X1 U100 ( .A(n433), .B(n50), .Z(n435) );
INVX1 U101 ( .A(n435), .Z(n431) );
NAND2X1 U102 ( .A(check_block_number[1]), .B(check_block_number[0]), .Z(n430) );
INVX1 U103 ( .A(n51), .Z(n113) );
NAND3X1 U104 ( .A(n431), .B(n430), .C(n113), .Z(n52) );
INVX1 U105 ( .A(n52), .Z(n356) );
NAND2X1 U106 ( .A(en), .B(n53), .Z(n499) );
NOR2X1 U107 ( .A(line_iterator[1]), .B(line_iterator[0]), .Z(n56) );
NOR2X1 U108 ( .A(line_iterator[3]), .B(line_iterator[2]), .Z(n54) );
MUX2X1 U109 ( .A(line_iterator[4]), .B(n56), .S(n54), .Z(n58) );
INVX1 U110 ( .A(line_iterator[3]), .Z(n55) );
NAND3X1 U111 ( .A(n56), .B(line_iterator[4]), .C(n55), .Z(n57) );
NAND2X1 U112 ( .A(n58), .B(n57), .Z(n60) );
NAND2X1 U113 ( .A(n59), .B(n60), .Z(n133) );
NAND2X1 U114 ( .A(n148), .B(advance_line), .Z(n152) );
OR2X1 U115 ( .A(advance_line), .B(n133), .Z(n109) );
NOR2X1 U116 ( .A(line_iterator[1]), .B(line_iterator[3]), .Z(n495) );
NOR2X1 U117 ( .A(n499), .B(n60), .Z(n108) );
NOR2X1 U118 ( .A(line_iterator[4]), .B(line_iterator[2]), .Z(n61) );
INVX1 U119 ( .A(line_iterator[0]), .Z(n127) );
NAND3X1 U120 ( .A(n61), .B(n495), .C(n127), .Z(n102) );
NAND3X1 U121 ( .A(n495), .B(n108), .C(n102), .Z(n132) );
NAND2X1 U122 ( .A(n109), .B(n132), .Z(n122) );
MUX2X1 U123 ( .A(n152), .B(n149), .S(current_line[2]), .Z(n62) );
INVX1 U124 ( .A(n62), .Z(n402) );
NOR2X1 U125 ( .A(current_shift_line[6]), .B(current_shift_line[7]), .Z(n63)
);
INVX1 U126 ( .A(current_shift_line[5]), .Z(n297) );
NAND2X1 U127 ( .A(n63), .B(n297), .Z(n66) );
NOR2X1 U128 ( .A(current_shift_line[3]), .B(current_shift_line[2]), .Z(n169)
);
INVX1 U129 ( .A(current_shift_line[0]), .Z(n225) );
NOR2X1 U130 ( .A(current_shift_line[4]), .B(n225), .Z(n64) );
NAND2X1 U131 ( .A(n169), .B(n64), .Z(n65) );
NOR2X1 U132 ( .A(n66), .B(n65), .Z(n313) );
NAND2X1 U133 ( .A(n164), .B(n313), .Z(n423) );
NAND2X1 U134 ( .A(n68), .B(n67), .Z(n69) );
NAND2X1 U135 ( .A(clear_state[5]), .B(n69), .Z(n73) );
NAND2X1 U136 ( .A(n73), .B(clear_state[0]), .Z(n203) );
NAND2X1 U137 ( .A(n423), .B(n203), .Z(n89) );
XOR2X1 U138 ( .A(n89), .B(clear_state[1]), .Z(n70) );
AND2X1 U139 ( .A(n70), .B(n314), .Z(n501) );
NOR2X1 U140 ( .A(n71), .B(n203), .Z(n315) );
NAND3X1 U141 ( .A(clear_state[1]), .B(n73), .C(n72), .Z(n205) );
NAND3X1 U142 ( .A(n205), .B(n74), .C(n203), .Z(n77) );
NAND2X1 U143 ( .A(n77), .B(clear_state[2]), .Z(n75) );
NAND2X1 U144 ( .A(n423), .B(n75), .Z(n87) );
AND2X1 U145 ( .A(n315), .B(n87), .Z(n85) );
NAND2X1 U146 ( .A(n77), .B(clear_state[3]), .Z(n76) );
NAND2X1 U147 ( .A(n423), .B(n76), .Z(n84) );
AND2X1 U148 ( .A(n85), .B(n84), .Z(n82) );
AND2X1 U149 ( .A(n82), .B(clear_state[4]), .Z(n80) );
NAND2X1 U150 ( .A(n77), .B(clear_state[5]), .Z(n78) );
NAND2X1 U151 ( .A(n423), .B(n78), .Z(n79) );
XOR2X1 U152 ( .A(n80), .B(n79), .Z(n81) );
AND2X1 U153 ( .A(n81), .B(n314), .Z(N448) );
XOR2X1 U154 ( .A(n82), .B(clear_state[4]), .Z(n83) );
AND2X1 U155 ( .A(n83), .B(n314), .Z(N447) );
XOR2X1 U156 ( .A(n85), .B(n84), .Z(n86) );
AND2X1 U157 ( .A(n86), .B(n314), .Z(N446) );
XOR2X1 U158 ( .A(n315), .B(n87), .Z(n88) );
AND2X1 U159 ( .A(n88), .B(n314), .Z(N445) );
AND2X1 U160 ( .A(n90), .B(n314), .Z(N443) );
INVX1 U161 ( .A(check_addr[0]), .Z(n449) );
NOR2X1 U162 ( .A(n449), .B(n91), .Z(n92) );
INVX1 U163 ( .A(n91), .Z(n468) );
NAND2X1 U164 ( .A(n468), .B(n449), .Z(n451) );
NAND2X1 U165 ( .A(n462), .B(n451), .Z(n453) );
MUX2X1 U166 ( .A(n92), .B(n453), .S(check_addr[1]), .Z(n351) );
AND2X1 U167 ( .A(check_addr[0]), .B(check_line), .Z(n93) );
MUX2X1 U168 ( .A(shift_addr[0]), .B(n93), .S(n100), .Z(addr[0]) );
AND2X1 U169 ( .A(check_addr[1]), .B(check_line), .Z(n94) );
MUX2X1 U170 ( .A(shift_addr[1]), .B(n94), .S(n100), .Z(addr[1]) );
AND2X1 U171 ( .A(check_addr[2]), .B(check_line), .Z(n95) );
MUX2X1 U172 ( .A(shift_addr[2]), .B(n95), .S(n100), .Z(addr[2]) );
AND2X1 U173 ( .A(check_addr[3]), .B(check_line), .Z(n96) );
MUX2X1 U174 ( .A(shift_addr[3]), .B(n96), .S(n100), .Z(addr[3]) );
AND2X1 U175 ( .A(check_addr[4]), .B(check_line), .Z(n97) );
MUX2X1 U176 ( .A(shift_addr[4]), .B(n97), .S(n100), .Z(addr[4]) );
AND2X1 U177 ( .A(check_addr[5]), .B(check_line), .Z(n98) );
MUX2X1 U178 ( .A(shift_addr[5]), .B(n98), .S(n100), .Z(addr[5]) );
AND2X1 U179 ( .A(check_addr[6]), .B(check_line), .Z(n99) );
MUX2X1 U180 ( .A(shift_addr[6]), .B(n99), .S(n100), .Z(addr[6]) );
AND2X1 U181 ( .A(check_addr[7]), .B(check_line), .Z(n101) );
MUX2X1 U182 ( .A(shift_addr[7]), .B(n101), .S(n100), .Z(addr[7]) );
OR2X1 U183 ( .A(n499), .B(n102), .Z(n136) );
NAND2X1 U184 ( .A(n152), .B(n136), .Z(n104) );
MUX2X1 U185 ( .A(n104), .B(n122), .S(line_iterator[0]), .Z(n411) );
INVX1 U186 ( .A(line_iterator[2]), .Z(n497) );
NAND2X1 U187 ( .A(line_iterator[1]), .B(line_iterator[0]), .Z(n121) );
OR2X1 U188 ( .A(n497), .B(n121), .Z(n105) );
NAND2X1 U189 ( .A(n104), .B(n105), .Z(n103) );
NAND2X1 U190 ( .A(n149), .B(n103), .Z(n119) );
NAND2X1 U191 ( .A(line_iterator[4]), .B(n119), .Z(n107) );
INVX1 U192 ( .A(n104), .Z(n128) );
NOR2X1 U193 ( .A(n128), .B(n105), .Z(n120) );
NAND2X1 U194 ( .A(line_iterator[3]), .B(n120), .Z(n106) );
NAND2X1 U195 ( .A(n107), .B(n106), .Z(n410) );
NAND2X1 U196 ( .A(n108), .B(check_line), .Z(n110) );
NAND2X1 U197 ( .A(n110), .B(n109), .Z(n409) );
NOR2X1 U198 ( .A(n111), .B(n462), .Z(n118) );
NAND2X1 U199 ( .A(check_block_number[2]), .B(check_block_number[3]), .Z(n115) );
NOR2X1 U200 ( .A(n113), .B(n112), .Z(n114) );
NOR2X1 U201 ( .A(n115), .B(n114), .Z(n116) );
NOR2X1 U202 ( .A(n117), .B(n116), .Z(n157) );
MUX2X1 U203 ( .A(n118), .B(advance_line), .S(n157), .Z(n408) );
MUX2X1 U204 ( .A(n120), .B(n119), .S(line_iterator[3]), .Z(n407) );
NOR2X1 U205 ( .A(n128), .B(n121), .Z(n126) );
NOR2X1 U206 ( .A(line_iterator[0]), .B(n128), .Z(n123) );
NOR2X1 U207 ( .A(n123), .B(n122), .Z(n129) );
OR2X1 U208 ( .A(line_iterator[1]), .B(n128), .Z(n124) );
NAND2X1 U209 ( .A(n129), .B(n124), .Z(n125) );
MUX2X1 U210 ( .A(n126), .B(n125), .S(line_iterator[2]), .Z(n406) );
NOR2X1 U211 ( .A(n128), .B(n127), .Z(n131) );
INVX1 U212 ( .A(n129), .Z(n130) );
MUX2X1 U213 ( .A(n131), .B(n130), .S(line_iterator[1]), .Z(n405) );
NAND2X1 U214 ( .A(n133), .B(n132), .Z(n134) );
NAND2X1 U215 ( .A(n134), .B(N748), .Z(n135) );
NAND2X1 U216 ( .A(n136), .B(n135), .Z(n404) );
NOR2X1 U217 ( .A(current_line[2]), .B(n152), .Z(n139) );
NAND2X1 U218 ( .A(current_line[2]), .B(n148), .Z(n137) );
NAND2X1 U219 ( .A(n137), .B(n149), .Z(n138) );
MUX2X1 U220 ( .A(n139), .B(n138), .S(current_line[3]), .Z(n401) );
INVX1 U221 ( .A(current_line[4]), .Z(n142) );
NOR2X1 U222 ( .A(current_line[3]), .B(current_line[2]), .Z(n141) );
NOR2X1 U223 ( .A(n142), .B(n141), .Z(n147) );
INVX1 U224 ( .A(n147), .Z(n144) );
NAND2X1 U225 ( .A(n148), .B(n144), .Z(n140) );
NAND2X1 U226 ( .A(n140), .B(n149), .Z(n145) );
NOR2X1 U227 ( .A(n141), .B(n152), .Z(n143) );
MUX2X1 U228 ( .A(n145), .B(n143), .S(n142), .Z(n400) );
NOR2X1 U229 ( .A(n152), .B(n144), .Z(n146) );
MUX2X1 U230 ( .A(n146), .B(n145), .S(current_line[5]), .Z(n399) );
AND2X1 U231 ( .A(n146), .B(current_line[5]), .Z(n151) );
NAND3X1 U232 ( .A(n147), .B(current_line[5]), .C(current_line[6]), .Z(n153)
);
NAND2X1 U233 ( .A(n148), .B(n153), .Z(n150) );
NAND2X1 U234 ( .A(n150), .B(n149), .Z(n154) );
MUX2X1 U235 ( .A(n151), .B(n154), .S(current_line[6]), .Z(n398) );
NOR2X1 U236 ( .A(n153), .B(n152), .Z(n155) );
MUX2X1 U237 ( .A(n155), .B(n154), .S(current_line[7]), .Z(n397) );
OR2X1 U238 ( .A(n156), .B(n462), .Z(n159) );
NAND2X1 U239 ( .A(n157), .B(clear_line), .Z(n158) );
NAND2X1 U240 ( .A(n159), .B(n158), .Z(n396) );
NOR2X1 U241 ( .A(n206), .B(n160), .Z(n191) );
NAND2X1 U242 ( .A(N748), .B(n191), .Z(n162) );
NAND2X1 U243 ( .A(n422), .B(current_shift_line[0]), .Z(n161) );
NAND2X1 U244 ( .A(n162), .B(n161), .Z(n394) );
NAND2X1 U245 ( .A(n191), .B(current_line[2]), .Z(n167) );
INVX1 U246 ( .A(n206), .Z(n312) );
AND2X1 U247 ( .A(n312), .B(n164), .Z(n425) );
NAND2X1 U248 ( .A(n164), .B(n163), .Z(n165) );
NAND2X1 U249 ( .A(n165), .B(n422), .Z(n170) );
NAND2X1 U250 ( .A(n425), .B(n170), .Z(n190) );
MUX2X1 U251 ( .A(n190), .B(n170), .S(current_shift_line[2]), .Z(n166) );
NAND2X1 U252 ( .A(n167), .B(n166), .Z(n393) );
NAND2X1 U253 ( .A(current_shift_line[3]), .B(current_shift_line[2]), .Z(n177) );
NOR2X1 U254 ( .A(n169), .B(n168), .Z(n251) );
NAND2X1 U255 ( .A(n182), .B(n251), .Z(n173) );
NAND2X1 U256 ( .A(current_line[3]), .B(n191), .Z(n172) );
INVX1 U257 ( .A(n170), .Z(n186) );
NAND2X1 U258 ( .A(current_shift_line[3]), .B(n186), .Z(n171) );
NAND3X1 U259 ( .A(n173), .B(n172), .C(n171), .Z(n392) );
NAND2X1 U260 ( .A(n186), .B(current_shift_line[4]), .Z(n176) );
INVX1 U261 ( .A(current_shift_line[4]), .Z(n286) );
MUX2X1 U262 ( .A(current_shift_line[4]), .B(n286), .S(n177), .Z(n254) );
NAND2X1 U263 ( .A(n182), .B(n254), .Z(n175) );
NAND2X1 U264 ( .A(current_line[4]), .B(n191), .Z(n174) );
NAND3X1 U265 ( .A(n176), .B(n175), .C(n174), .Z(n391) );
NAND2X1 U266 ( .A(n186), .B(current_shift_line[5]), .Z(n180) );
NAND2X1 U267 ( .A(n286), .B(n177), .Z(n181) );
MUX2X1 U268 ( .A(current_shift_line[5]), .B(n297), .S(n181), .Z(n270) );
OR2X1 U269 ( .A(n270), .B(n190), .Z(n179) );
NAND2X1 U270 ( .A(current_line[5]), .B(n191), .Z(n178) );
NAND3X1 U271 ( .A(n180), .B(n179), .C(n178), .Z(n390) );
NAND2X1 U272 ( .A(n186), .B(current_shift_line[6]), .Z(n185) );
INVX1 U273 ( .A(current_shift_line[6]), .Z(n300) );