- Make
current_state
value accessible. - Call / return
using the stackusing generic variables. - Support for include files / packages/ modules.
- Multiple instantiations of included files.
- Make it possible to access state (block) encodings directly for better call / return support.
- Inlineable blocks rather than callable blocks.
- Proper parsing of instruction statements, rather than simply expecting correct Verilog syntax as at the moment.
- Detect multiple writes to the same variable in a single state.
- Detect reading from and writing to the same variable in a single state.
- Infrastructure to break up blocks into sequences of atomic operations.
- Marking of parallelisable statements
- Infrastructure to coalesce atomised blocks based on tunable parameters.
- Be able to specify a cost for each operator, and coalesce blocks until they contain the maximum allowable cost per block (per cycle)
- Detecting and unrolling loops
- Stack example
- Finish the AXI example
- Mini RISCV registers and instructions. RV32UI Only.