From 5fc3eb3de3ec2eae3200025bc00ded27bcdcf13f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=2E=20Efe=20=C3=87etin?= Date: Fri, 4 Oct 2024 08:21:30 +0300 Subject: [PATCH] rockchip-rk3588-current: update kernel to 6.11 (#7326) * rockchip-rk3588-edge: rebase patches * rockchip-rk3588-edge: derive HDMI RX patch from 6.10 pathces * rockchip-rk3588-current: update kernel to 6.11 * rockchip-rk3588-current: derive recent patches from 6.10 --- .../kernel/linux-rockchip-rk3588-6.10.config | 10975 ---------------- .../kernel/linux-rockchip-rk3588-6.11.config | 33 +- config/sources/families/rockchip-rk3588.conf | 2 +- .../0000.patching_config.yaml | 47 - .../0001-general-add-overlay-support.patch | 69 - .../0010-fix-clk-divisions.patch | 142 - .../0011-irqchip-fix-its-timeout-issue.patch | 214 - ...3588-Add-Thermal-and-CpuFreq-Support.patch | 758 -- .../0024-RK3588-Add-Crypto-Support.patch | 2328 ---- .../0025-RK3588-Add-HW-RNG-Support.patch | 663 - ...588-Add-VPU121-H.264-Decoder-Support.patch | 311 - .../0027-RK3588-Add-rkvdec2-Support-v3.patch | 3746 ------ ...Initialize-h264-frame_mbs_only_flag-.patch | 43 - ...nopsys-designware-hdmi-rx-controller.patch | 3921 ------ ...-rockchip-Add-HDMI0-bridge-to-rk3588.patch | 81 - ...ip-Enable-HDMI0-PHY-clk-provider-on-.patch | 26 - ...p-samsung-hdptx-Add-FRL-EARC-support.patch | 549 - ...hip-samsung-hdptx-Add-clock-provider.patch | 222 - ...2-Improve-display-modes-handling-on-.patch | 679 - ...64-dts-rockchip-rk3588-add-RGA2-node.patch | 34 - ...itial-support-for-DW-HDMI-Controller.patch | 6616 ---------- ...-bridge-synopsys-Fix-HDMI-Controller.patch | 25 - ...ckchip-vop2-add-clocks-reset-support.patch | 190 - .../0801-wireless-add-bcm43752.patch | 74 - .../0802-wireless-add-clk-property.patch | 51 - ...b-Slow-down-emmc-to-hs200-and-add-ts.patch | 37 - ...d-rock-5b-arm64-dts-enable-spi-flash.patch | 52 - ...dts-rockchip-Enable-HDMI0-on-rock-5b.patch | 67 - ...-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch | 41 - ...5-board-rock5b-automatic-fan-control.patch | 68 - .../1020-Add-HDMI-and-VOP2-to-Rock-5A.patch | 57 - ...rm64-dts-enable-gpu-node-for-rock-5a.patch | 36 - ...dd-missing-nodes-to-Orange-Pi-5-Plus.patch | 322 - ...ip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch | 39 - ...hip-Add-HDMI-support-to-ArmSoM-Sige7.patch | 74 - ...ip-Add-ap6275p-wireless-support-to-A.patch | 39 - .../1040-board-khadas-edge2-add-nodes.patch | 359 - .../1041-board-khadas-edge2-mcu.patch | 441 - ...dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch | 38 - ...ts-rockchip-Split-pcie30x1m1-pinctrl.patch | 47 - ...ip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch | 30 - ...ckchip-Enable-GPU-node-on-Turing-RK1.patch | 31 - ...ip-Enable-automatic-fan-control-on-t.patch | 63 - ...ip-Add-missing-hym8563-clock-frequen.patch | 26 - .../dt/rk3588-bananapi-m7.dts | 10 - .../dt/rk3588-hinlink-h88k.dts | 858 -- .../dt/rk3588-mixtile-blade3.dts | 712 - .../dt/rk3588-nanopc-cm3588-nas.dts | 1436 -- .../dt/rk3588s-nanopi-r6c.dts | 19 - .../dt/rk3588s-nanopi-r6s.dts | 865 -- .../dt/rk3588s-orangepi-5.dts | 814 -- .../dt/rk3588s-orangepi-5b.dts | 48 - .../dt/rk3588s-rock-5c.dts | 825 -- .../dt/rk3588s-youyeetoo-r1.dts | 861 -- .../rockchip-rk3588-6.10/overlay/Makefile | 48 - .../overlay/rockchip-rk3588-fanctrl.dtso | 11 - .../overlay/rockchip-rk3588-hdmirx.dtso | 20 - .../overlay/rockchip-rk3588-i2c8-m2.dtso | 14 - .../overlay/rockchip-rk3588-pwm0-m0.dtso | 14 - .../overlay/rockchip-rk3588-pwm0-m1.dtso | 13 - .../overlay/rockchip-rk3588-pwm0-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm1-m0.dtso | 14 - .../overlay/rockchip-rk3588-pwm1-m1.dtso | 13 - .../overlay/rockchip-rk3588-pwm1-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm10-m0.dtso | 13 - .../overlay/rockchip-rk3588-pwm11-m0.dtso | 13 - .../overlay/rockchip-rk3588-pwm11-m1.dtso | 21 - .../overlay/rockchip-rk3588-pwm12-m0.dtso | 13 - .../overlay/rockchip-rk3588-pwm13-m0.dtso | 13 - .../overlay/rockchip-rk3588-pwm13-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm14-m0.dtso | 14 - .../overlay/rockchip-rk3588-pwm14-m1.dtso | 14 - .../overlay/rockchip-rk3588-pwm14-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm15-m0.dtso | 21 - .../overlay/rockchip-rk3588-pwm15-m1.dtso | 13 - .../overlay/rockchip-rk3588-pwm15-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm15-m3.dtso | 21 - .../overlay/rockchip-rk3588-pwm2-m1.dtso | 21 - .../overlay/rockchip-rk3588-pwm3-m0.dtso | 13 - .../overlay/rockchip-rk3588-pwm3-m1.dtso | 21 - .../overlay/rockchip-rk3588-pwm3-m2.dtso | 13 - .../overlay/rockchip-rk3588-pwm3-m3.dtso | 13 - .../overlay/rockchip-rk3588-pwm5-m2.dtso | 21 - .../overlay/rockchip-rk3588-pwm6-m0.dtso | 21 - .../overlay/rockchip-rk3588-pwm6-m2.dtso | 21 - .../overlay/rockchip-rk3588-pwm7-m0.dtso | 21 - .../overlay/rockchip-rk3588-pwm7-m3.dtso | 21 - .../overlay/rockchip-rk3588-pwm8-m0.dtso | 21 - .../overlay/rockchip-rk3588-sata1.dtso | 20 - .../overlay/rockchip-rk3588-sata2.dtso | 20 - .../overlay/rockchip-rk3588-uart1-m1.dtso | 13 - .../overlay/rockchip-rk3588-uart3-m1.dtso | 13 - .../overlay/rockchip-rk3588-uart4-m2.dtso | 13 - .../overlay/rockchip-rk3588-uart6-m1.dtso | 13 - .../overlay/rockchip-rk3588-uart7-m2.dtso | 13 - .../overlay/rockchip-rk3588-uart8-m1.dtso | 13 - .../rk3588-rock-5b_dts_add_rfkill-bt.patch | 31 - ...nopsys-designware-hdmi-rx-controller.patch | 150 + ...s-rockchip-nanopct6-lts-and-fixes-v6.patch | 1127 +- .../rockchip-rk3588-6.11/overlay/Makefile | 3 +- .../rockchip-rk3588-rkvenc-overlay.dtso | 0 101 files changed, 1165 insertions(+), 40953 deletions(-) delete mode 100644 config/kernel/linux-rockchip-rk3588-6.10.config delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0000.patching_config.yaml delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0001-general-add-overlay-support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0010-fix-clk-divisions.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0011-irqchip-fix-its-timeout-issue.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0024-RK3588-Add-Crypto-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0025-RK3588-Add-HW-RNG-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0170-drm-rockchip-vop2-add-clocks-reset-support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0801-wireless-add-bcm43752.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/0802-wireless-add-clk-property.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1015-board-rock5b-automatic-fan-control.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1040-board-khadas-edge2-add-nodes.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1041-board-khadas-edge2-mcu.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-bananapi-m7.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-hinlink-h88k.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-mixtile-blade3.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-nanopc-cm3588-nas.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6c.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6s.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5b.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-rock-5c.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-youyeetoo-r1.dts delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/Makefile delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-fanctrl.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-i2c8-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm10-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm12-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m3.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm2-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m3.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm5-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m3.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm8-m0.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart1-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart3-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart4-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart6-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart7-m2.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart8-m1.dtso delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch rename patch/kernel/archive/{rockchip-rk3588-6.10 => rockchip-rk3588-6.11}/overlay/rockchip-rk3588-rkvenc-overlay.dtso (100%) diff --git a/config/kernel/linux-rockchip-rk3588-6.10.config b/config/kernel/linux-rockchip-rk3588-6.10.config deleted file mode 100644 index d801774faf9b..000000000000 --- a/config/kernel/linux-rockchip-rk3588-6.10.config +++ /dev/null @@ -1,10975 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.10.5 Kernel Configuration -# -CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 13.2.0-23ubuntu4) 13.2.0" -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=130200 -CONFIG_CLANG_VERSION=0 -CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=24200 -CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=24200 -CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y -CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y -CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y -CONFIG_PAHOLE_VERSION=125 -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_TABLE_SORT=y -CONFIG_THREAD_INFO_IN_TASK=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_COMPILE_TEST is not set -# CONFIG_WERROR is not set -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_WATCH_QUEUE is not set -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y -CONFIG_AUDIT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_INJECTION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_SIM=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -# end of IRQ subsystem - -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_TIME_KUNIT_TEST=m -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -# end of Timers subsystem - -CONFIG_BPF=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y - -# -# BPF subsystem -# -CONFIG_BPF_SYSCALL=y -CONFIG_BPF_JIT=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_JIT_DEFAULT_ON=y -# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set -# CONFIG_BPF_PRELOAD is not set -CONFIG_BPF_LSM=y -# end of BPF subsystem - -CONFIG_PREEMPT_BUILD=y -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_PREEMPT_COUNT=y -CONFIG_PREEMPTION=y -# CONFIG_PREEMPT_DYNAMIC is not set -CONFIG_SCHED_CORE=y - -# -# CPU/Task time and stats accounting -# -CONFIG_TICK_CPU_ACCOUNTING=y -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_SCHED_AVG_IRQ=y -CONFIG_SCHED_HW_PRESSURE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_PSI is not set -# end of CPU/Task time and stats accounting - -CONFIG_CPU_ISOLATION=y - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -CONFIG_PREEMPT_RCU=y -# CONFIG_RCU_EXPERT is not set -CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_NEED_TASKS_RCU=y -CONFIG_TASKS_RCU=y -CONFIG_TASKS_TRACE_RCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y -# end of RCU Subsystem - -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_IKHEADERS=m -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -# CONFIG_PRINTK_INDEX is not set -CONFIG_GENERIC_SCHED_CLOCK=y - -# -# Scheduler features -# -# CONFIG_UCLAMP_TASK is not set -# end of Scheduler features - -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y -CONFIG_CC_HAS_INT128=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_GCC10_NO_ARRAY_BOUNDS=y -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_GCC_NO_STRINGOP_OVERFLOW=y -CONFIG_CC_NO_STRINGOP_OVERFLOW=y -CONFIG_ARCH_SUPPORTS_INT128=y -CONFIG_NUMA_BALANCING=y -CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y -CONFIG_SLAB_OBJ_EXT=y -CONFIG_CGROUPS=y -CONFIG_PAGE_COUNTER=y -# CONFIG_CGROUP_FAVOR_DYNMODS is not set -CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_WRITEBACK=y -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_SCHED_MM_CID=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_MISC=y -# CONFIG_CGROUP_DEBUG is not set -CONFIG_SOCK_CGROUP_DATA=y -CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_TIME_NS=y -CONFIG_IPC_NS=y -CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y -CONFIG_BOOT_CONFIG=y -# CONFIG_BOOT_CONFIG_FORCE is not set -# CONFIG_BOOT_CONFIG_EMBED is not set -CONFIG_INITRAMFS_PRESERVE_MTIME=y -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_LD_ORPHAN_WARN=y -CONFIG_LD_ORPHAN_WARN_LEVEL="warn" -CONFIG_SYSCTL=y -CONFIG_HAVE_UID16=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -# CONFIG_SGETMASK_SYSCALL is not set -CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y -CONFIG_POSIX_TIMERS=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -# CONFIG_BASE_SMALL is not set -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_IO_URING=y -CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -# CONFIG_DEBUG_RSEQ is not set -CONFIG_CACHESTAT_SYSCALL=y -# CONFIG_PC104 is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_SELFTEST is not set -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_GUEST_PERF_EVENTS=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# end of Kernel Performance Events And Counters - -CONFIG_SYSTEM_DATA_VERIFICATION=y -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y - -# -# Kexec and crash features -# -CONFIG_KEXEC_CORE=y -CONFIG_HAVE_IMA_KEXEC=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -# CONFIG_KEXEC_SIG is not set -# CONFIG_CRASH_DUMP is not set -# end of Kexec and crash features -# end of General setup - -CONFIG_ARM64=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_64BIT=y -CONFIG_MMU=y -CONFIG_ARM64_CONT_PTE_SHIFT=4 -CONFIG_ARM64_CONT_PMD_SHIFT=4 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SMP=y -CONFIG_KERNEL_MODE_NEON=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y - -# -# Platform selection -# -# CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AIROHA is not set -# CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_ALPINE is not set -# CONFIG_ARCH_APPLE is not set -# CONFIG_ARCH_BCM is not set -# CONFIG_ARCH_BERLIN is not set -# CONFIG_ARCH_BITMAIN is not set -# CONFIG_ARCH_EXYNOS is not set -# CONFIG_ARCH_SPARX5 is not set -# CONFIG_ARCH_K3 is not set -# CONFIG_ARCH_LG1K is not set -# CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_KEEMBAY is not set -# CONFIG_ARCH_MEDIATEK is not set -# CONFIG_ARCH_MESON is not set -# CONFIG_ARCH_MVEBU is not set -# CONFIG_ARCH_NXP is not set -# CONFIG_ARCH_MA35 is not set -# CONFIG_ARCH_NPCM is not set -# CONFIG_ARCH_PENSANDO is not set -# CONFIG_ARCH_QCOM is not set -# CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_RENESAS is not set -CONFIG_ARCH_ROCKCHIP=y -# CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_INTEL_SOCFPGA is not set -# CONFIG_ARCH_STM32 is not set -# CONFIG_ARCH_SYNQUACER is not set -# CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_SPRD is not set -# CONFIG_ARCH_THUNDER is not set -# CONFIG_ARCH_THUNDER2 is not set -# CONFIG_ARCH_UNIPHIER is not set -# CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_VISCONTI is not set -# CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZYNQMP is not set -# end of Platform selection - -# -# Kernel Features -# - -# -# ARM errata workarounds via the alternatives framework -# -CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_834220=y -CONFIG_ARM64_ERRATUM_1742098=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_ERRATUM_2441007=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y -CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_2658417=y -CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y -CONFIG_ARM64_ERRATUM_2054223=y -CONFIG_ARM64_ERRATUM_2067961=y -CONFIG_ARM64_ERRATUM_2441009=y -CONFIG_ARM64_ERRATUM_2457168=y -CONFIG_ARM64_ERRATUM_2645198=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y -CONFIG_ARM64_ERRATUM_2966298=y -CONFIG_ARM64_ERRATUM_3117295=y -CONFIG_ARM64_ERRATUM_3194386=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23144=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y -CONFIG_ROCKCHIP_ERRATUM_3588001=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y -# end of ARM errata workarounds via the alternatives framework - -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_16K_PAGES is not set -# CONFIG_ARM64_64K_PAGES is not set -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -# CONFIG_ARM64_VA_BITS_52 is not set -CONFIG_ARM64_VA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PA_BITS=48 -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_CLUSTER=y -CONFIG_SCHED_SMT=y -CONFIG_NR_CPUS=256 -CONFIG_HOTPLUG_CPU=y -CONFIG_NUMA=y -CONFIG_NODES_SHIFT=4 -# CONFIG_HZ_100 is not set -# CONFIG_HZ_250 is not set -CONFIG_HZ_300=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=300 -CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HW_PERF_EVENTS=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_TIME_ACCOUNTING=y -CONFIG_ARCH_SUPPORTS_KEXEC=y -CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y -CONFIG_ARCH_SELECTS_KEXEC_FILE=y -CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y -CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y -CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y -CONFIG_TRANS_TABLE=y -CONFIG_XEN_DOM0=y -CONFIG_XEN=y -CONFIG_ARCH_FORCE_MAX_ORDER=10 -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_COMPAT=y -CONFIG_KUSER_HELPERS=y -CONFIG_COMPAT_ALIGNMENT_FIXUPS=y -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y - -# -# ARMv8.1 architectural features -# -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y -CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y -# end of ARMv8.1 architectural features - -# -# ARMv8.2 architectural features -# -CONFIG_AS_HAS_ARMV8_2=y -CONFIG_AS_HAS_SHA3=y -# CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_CNP=y -# end of ARMv8.2 architectural features - -# -# ARMv8.3 architectural features -# -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y -CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y -CONFIG_AS_HAS_ARMV8_3=y -CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y -CONFIG_AS_HAS_LDAPR=y -# end of ARMv8.3 architectural features - -# -# ARMv8.4 architectural features -# -CONFIG_ARM64_AMU_EXTN=y -CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y -# end of ARMv8.4 architectural features - -# -# ARMv8.5 architectural features -# -CONFIG_AS_HAS_ARMV8_5=y -CONFIG_ARM64_BTI=y -CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y -# end of ARMv8.5 architectural features - -# -# ARMv8.7 architectural features -# -CONFIG_ARM64_EPAN=y -# end of ARMv8.7 architectural features - -CONFIG_ARM64_SVE=y -CONFIG_ARM64_SME=y -CONFIG_ARM64_PSEUDO_NMI=y -# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set -CONFIG_RELOCATABLE=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_ARM64_CONTPTE=y -# end of Kernel Features - -# -# Boot options -# -# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set -CONFIG_CMDLINE="" -CONFIG_EFI_STUB=y -CONFIG_EFI=y -CONFIG_DMI=y -# end of Boot options - -# -# Power management options -# -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_HIBERNATION_COMP_LZO=y -# CONFIG_HIBERNATION_COMP_LZ4 is not set -CONFIG_HIBERNATION_DEF_COMP="lzo" -CONFIG_PM_STD_PARTITION="" -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -# CONFIG_PM_AUTOSLEEP is not set -# CONFIG_PM_USERSPACE_AUTOSLEEP is not set -# CONFIG_PM_WAKELOCKS is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_CPU_PM=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# end of Power management options - -# -# CPU Power Management -# - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DT_IDLE_GENPD=y - -# -# ARM CPU Idle Drivers -# -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -# end of ARM CPU Idle Drivers -# end of CPU Idle - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - -# -# CPU frequency scaling drivers -# -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -# CONFIG_ARM_SCMI_CPUFREQ is not set -# CONFIG_ACPI_CPPC_CPUFREQ is not set -# end of CPU Frequency scaling -# end of CPU Power Management - -CONFIG_ARCH_SUPPORTS_ACPI=y -CONFIG_ACPI=y -CONFIG_ACPI_GENERIC_GSI=y -CONFIG_ACPI_CCA_REQUIRED=y -CONFIG_ACPI_TABLE_LIB=y -CONFIG_ACPI_THERMAL_LIB=y -# CONFIG_ACPI_DEBUGGER is not set -CONFIG_ACPI_SPCR_TABLE=y -# CONFIG_ACPI_FPDT is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_AC=m -CONFIG_ACPI_BATTERY=m -CONFIG_ACPI_BUTTON=m -# CONFIG_ACPI_TINY_POWER_BUTTON is not set -CONFIG_ACPI_VIDEO=m -CONFIG_ACPI_FAN=m -# CONFIG_ACPI_TAD is not set -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_MCFG=y -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_IPMI=m -CONFIG_ACPI_THERMAL=m -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ACPI_TABLE_UPGRADE=y -# CONFIG_ACPI_DEBUG is not set -CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_HED=y -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y -CONFIG_ACPI_NHLT=y -CONFIG_ACPI_NUMA=y -CONFIG_ACPI_HMAT=y -CONFIG_HAVE_ACPI_APEI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -# CONFIG_ACPI_APEI_PCIEAER is not set -CONFIG_ACPI_APEI_SEA=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_ACPI_APEI_EINJ_CXL=y -# CONFIG_ACPI_APEI_ERST_DEBUG is not set -CONFIG_ACPI_WATCHDOG=y -CONFIG_ACPI_CONFIGFS=m -# CONFIG_ACPI_PFRUT is not set -CONFIG_ACPI_IORT=y -CONFIG_ACPI_GTDT=y -# CONFIG_ACPI_AGDI is not set -CONFIG_ACPI_APMT=y -CONFIG_ACPI_PPTT=y -CONFIG_ACPI_PCC=y -# CONFIG_ACPI_FFH is not set -CONFIG_PMIC_OPREGION=y -CONFIG_ACPI_VIOT=y -CONFIG_ACPI_PRMT=y -CONFIG_KVM_COMMON=y -CONFIG_HAVE_KVM_IRQCHIP=y -CONFIG_HAVE_KVM_IRQ_ROUTING=y -CONFIG_HAVE_KVM_DIRTY_RING=y -CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y -CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y -CONFIG_KVM_MMIO=y -CONFIG_HAVE_KVM_MSI=y -CONFIG_HAVE_KVM_READONLY_MEM=y -CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y -CONFIG_KVM_VFIO=y -CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y -CONFIG_HAVE_KVM_IRQ_BYPASS=y -CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y -CONFIG_KVM_XFER_TO_GUEST_WORK=y -CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y -CONFIG_KVM_GENERIC_MMU_NOTIFIER=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -# CONFIG_NVHE_EL2_DEBUG is not set -CONFIG_CPU_MITIGATIONS=y - -# -# General architecture-dependent options -# -CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y -CONFIG_HOTPLUG_CORE_SYNC=y -CONFIG_HOTPLUG_CORE_SYNC_DEAD=y -CONFIG_KPROBES=y -CONFIG_JUMP_LABEL=y -# CONFIG_STATIC_KEYS_SELFTEST is not set -CONFIG_UPROBES=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_KRETPROBES=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -CONFIG_HAVE_NMI=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_KEEPINITRD=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_RUST=y -CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_PERF_EVENTS_NMI=y -CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_MMU_GATHER_TABLE_FREE=y -CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_HAVE_ARCH_SECCOMP=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SECCOMP_CACHE_DEBUG is not set -CONFIG_HAVE_ARCH_STACKLEAK=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y -# CONFIG_SHADOW_CALL_STACK is not set -CONFIG_ARCH_SUPPORTS_LTO_CLANG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y -CONFIG_LTO_NONE=y -CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING_USER=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOVE_PUD=y -CONFIG_HAVE_MOVE_PMD=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_HUGE_VMALLOC=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_WANT_PMD_MKWRITE=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_ARCH_WANTS_EXECMEM_LATE=y -CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_HAVE_PAGE_SIZE_4KB=y -CONFIG_PAGE_SIZE_4KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SHIFT=12 -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_VMAP_STACK=y -CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y -CONFIG_RANDOMIZE_KSTACK_OFFSET=y -# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -# CONFIG_LOCK_EVENT_COUNTS is not set -CONFIG_ARCH_HAS_RELR=y -CONFIG_HAVE_PREEMPT_DYNAMIC=y -CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y -CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y -CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y -CONFIG_ARCH_HAS_HW_PTE_YOUNG=y -CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# end of GCOV-based kernel profiling - -CONFIG_HAVE_GCC_PLUGINS=y -CONFIG_FUNCTION_ALIGNMENT_4B=y -CONFIG_FUNCTION_ALIGNMENT=4 -# end of General architecture-dependent options - -CONFIG_RT_MUTEXES=y -CONFIG_MODULES=y -# CONFIG_MODULE_DEBUG is not set -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set -CONFIG_MODVERSIONS=y -CONFIG_ASM_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -CONFIG_MODPROBE_PATH="/sbin/modprobe" -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLOCK_LEGACY_AUTOLOAD=y -CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_CGROUP_PUNT_BIO=y -CONFIG_BLK_DEV_BSG_COMMON=y -CONFIG_BLK_ICQ=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_WRITE_MOUNTED=y -CONFIG_BLK_DEV_ZONED=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_WBT=y -CONFIG_BLK_WBT_MQ=y -CONFIG_BLK_CGROUP_IOLATENCY=y -# CONFIG_BLK_CGROUP_FC_APPID is not set -# CONFIG_BLK_CGROUP_IOCOST is not set -# CONFIG_BLK_CGROUP_IOPRIO is not set -CONFIG_BLK_DEBUG_FS=y -CONFIG_BLK_SED_OPAL=y -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -CONFIG_OSF_PARTITION=y -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -# CONFIG_LDM_DEBUG is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_CMDLINE_PARTITION=y -# end of Partition Types - -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_HOLDER_DEPRECATED=y -CONFIG_BLK_MQ_STACKING=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_IOSCHED_BFQ=y -CONFIG_BFQ_GROUP_IOSCHED=y -# CONFIG_BFQ_CGROUP_DEBUG is not set -# end of IO Schedulers - -CONFIG_PREEMPT_NOTIFIERS=y -CONFIG_PADATA=y -CONFIG_ASN1=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -CONFIG_FREEZER=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_HAVE_ELF_PROT=y -CONFIG_ARCH_USE_GNU_PROPERTY=y -CONFIG_ELFCORE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_BINFMT_SCRIPT=y -CONFIG_BINFMT_MISC=m -CONFIG_COREDUMP=y -# end of Executable file formats - -# -# Memory Management options -# -CONFIG_ZPOOL=y -CONFIG_SWAP=y -CONFIG_ZSWAP=y -CONFIG_ZSWAP_DEFAULT_ON=y -# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" -CONFIG_ZBUD=y -CONFIG_Z3FOLD=y -CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_ZSMALLOC_CHAIN_SIZE=8 - -# -# Slab allocator options -# -CONFIG_SLUB=y -# CONFIG_SLUB_TINY is not set -CONFIG_SLAB_MERGE_DEFAULT=y -CONFIG_SLAB_FREELIST_RANDOM=y -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SLUB_STATS is not set -CONFIG_SLUB_CPU_PARTIAL=y -# CONFIG_RANDOM_KMALLOC_CACHES is not set -# end of Slab allocator options - -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_GUP_FAST=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -# CONFIG_MEMORY_HOTPLUG is not set -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_MEMORY_BALLOON=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_COMPACTION=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_PAGE_REPORTING=y -CONFIG_MIGRATION=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_PCP_BATCH_SCALE_MAX=5 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_MMU_NOTIFIER=y -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_MEMORY_FAILURE=y -# CONFIG_HWPOISON_INJECT is not set -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_TRANSPARENT_HUGEPAGE=y -# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set -CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y -# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set -CONFIG_THP_SWAP=y -# CONFIG_READ_ONLY_THP_FOR_FS is not set -CONFIG_PGTABLE_HAS_HUGE_LEAVES=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_CMA=y -# CONFIG_CMA_DEBUGFS is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_CMA_AREAS=7 -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -CONFIG_PAGE_IDLE_FLAG=y -CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_ARCH_HAS_ZONE_DMA_SET=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y -CONFIG_GET_FREE_REGION=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_USES_PG_ARCH_X=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_PERCPU_STATS=y -# CONFIG_GUP_TEST is not set -# CONFIG_DMAPOOL_TEST is not set -CONFIG_ARCH_HAS_PTE_SPECIAL=y -CONFIG_MAPPING_DIRTY_HELPERS=y -CONFIG_MEMFD_CREATE=y -CONFIG_SECRETMEM=y -# CONFIG_ANON_VMA_NAME is not set -# CONFIG_USERFAULTFD is not set -CONFIG_LRU_GEN=y -# CONFIG_LRU_GEN_ENABLED is not set -# CONFIG_LRU_GEN_STATS is not set -CONFIG_LRU_GEN_WALKS_MMU=y -CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y -CONFIG_PER_VMA_LOCK=y -CONFIG_LOCK_MM_AND_FIND_VMA=y -CONFIG_IOMMU_MM_DATA=y -CONFIG_EXECMEM=y - -# -# Data Access Monitoring -# -# CONFIG_DAMON is not set -# end of Data Access Monitoring -# end of Memory Management options - -CONFIG_NET=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_NET_INGRESS=y -CONFIG_NET_EGRESS=y -CONFIG_NET_XGRESS=y -CONFIG_NET_REDIRECT=y -CONFIG_SKB_DECRYPTED=y -CONFIG_SKB_EXTENSIONS=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX=y -CONFIG_AF_UNIX_OOB=y -CONFIG_UNIX_DIAG=m -CONFIG_TLS=m -CONFIG_TLS_DEVICE=y -# CONFIG_TLS_TOE is not set -CONFIG_XFRM=y -CONFIG_XFRM_OFFLOAD=y -CONFIG_XFRM_ALGO=m -CONFIG_XFRM_USER=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XFRM_STATISTICS=y -CONFIG_XFRM_AH=m -CONFIG_XFRM_ESP=m -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y -CONFIG_XDP_SOCKETS=y -# CONFIG_XDP_SOCKETS_DIAG is not set -CONFIG_NET_HANDSHAKE=y -# CONFIG_NET_HANDSHAKE_KUNIT_TEST is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_ROUTE_CLASSID=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IP_TUNNEL=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE_COMMON=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_NET_IPVTI=m -CONFIG_NET_UDP_TUNNEL=m -CONFIG_NET_FOU=m -CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -# CONFIG_INET_ESPINTCP is not set -CONFIG_INET_IPCOMP=m -CONFIG_INET_TABLE_PERTURB_ORDER=16 -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_INET_DIAG_DESTROY=y -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_CDG=m -CONFIG_TCP_CONG_BBR=m -# CONFIG_DEFAULT_CUBIC is not set -CONFIG_DEFAULT_RENO=y -CONFIG_DEFAULT_TCP_CONG="reno" -CONFIG_TCP_SIGPOOL=y -# CONFIG_TCP_AO is not set -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -# CONFIG_INET6_ESPINTCP is not set -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_ILA=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_GRE=m -CONFIG_IPV6_FOU=m -CONFIG_IPV6_FOU_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_IPV6_SEG6_LWTUNNEL=y -CONFIG_IPV6_SEG6_HMAC=y -CONFIG_IPV6_SEG6_BPF=y -# CONFIG_IPV6_RPL_LWTUNNEL is not set -# CONFIG_IPV6_IOAM6_LWTUNNEL is not set -CONFIG_NETLABEL=y -# CONFIG_MPTCP is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=m - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_EGRESS=y -CONFIG_NETFILTER_SKIP_EGRESS=y -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_FAMILY_BRIDGE=y -CONFIG_NETFILTER_FAMILY_ARP=y -CONFIG_NETFILTER_BPF_LINK=y -CONFIG_NETFILTER_NETLINK_HOOK=m -CONFIG_NETFILTER_NETLINK_ACCT=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_NETLINK_OSF=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_SYSLOG=m -CONFIG_NETFILTER_CONNCOUNT=m -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_PROCFS=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_LABELS=y -CONFIG_NF_CONNTRACK_OVS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_GRE=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_BROADCAST=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_SIP=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_NAT_MASQUERADE=y -CONFIG_NF_NAT_OVS=y -CONFIG_NETFILTER_SYNPROXY=m -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_CONNLIMIT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_TUNNEL=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_REJECT_INET=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_XFRM=m -CONFIG_NFT_SOCKET=m -CONFIG_NFT_OSF=m -CONFIG_NFT_TPROXY=m -CONFIG_NFT_SYNPROXY=m -CONFIG_NF_DUP_NETDEV=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NFT_REJECT_NETDEV=m -CONFIG_NF_FLOW_TABLE_INET=m -CONFIG_NF_FLOW_TABLE=m -CONFIG_NF_FLOW_TABLE_PROCFS=y -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XTABLES_COMPAT=y - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_CONNMARK=m -CONFIG_NETFILTER_XT_SET=m - -# -# Xtables targets -# -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_CT=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HL=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_NETMAP=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m - -# -# Xtables matches -# -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ECN=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_L2TP=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# end of Core Netfilter Configuration - -CONFIG_IP_SET=m -CONFIG_IP_SET_MAX=256 -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_IPMAC=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_MH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_TWOS=m - -# -# IPVS SH scheduler -# -CONFIG_IP_VS_SH_TAB_BITS=8 - -# -# IPVS MH scheduler -# -CONFIG_IP_VS_MH_TAB_INDEX=12 - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_NFCT=y -CONFIG_IP_VS_PE_SIP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_IP_NF_IPTABLES_LEGACY=m -CONFIG_NF_SOCKET_IPV4=m -CONFIG_NF_TPROXY_IPV4=m -CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_REJECT_IPV4=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_DUP_IPV4=m -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_NF_REJECT_IPV4=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_NFT_COMPAT_ARP=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -# end of IP: Netfilter Configuration - -# -# IPv6: Netfilter Configuration -# -CONFIG_IP6_NF_IPTABLES_LEGACY=m -CONFIG_NF_SOCKET_IPV6=m -CONFIG_NF_TPROXY_IPV6=m -CONFIG_NF_TABLES_IPV6=y -CONFIG_NFT_REJECT_IPV6=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_DUP_IPV6=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_IP6_NF_TARGET_NPT=m -# end of IPv6: Netfilter Configuration - -CONFIG_NF_DEFRAG_IPV6=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_META=m -CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_CONNTRACK_BRIDGE=m -CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_TFRC_LIB=y -# end of DCCP CCIDs Configuration - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -# end of DCCP Kernel Hacking - -CONFIG_IP_SCTP=m -CONFIG_SCTP_DBG_OBJCNT=y -CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y -# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set -# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set -CONFIG_SCTP_COOKIE_HMAC_MD5=y -CONFIG_SCTP_COOKIE_HMAC_SHA1=y -CONFIG_INET_SCTP_DIAG=m -CONFIG_RDS=m -CONFIG_RDS_TCP=m -# CONFIG_RDS_DEBUG is not set -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_UDP=y -CONFIG_TIPC_CRYPTO=y -CONFIG_TIPC_DIAG=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_CLIP_NO_ICMP=y -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_ATM_BR2684_IPFILTER=y -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_STP=y -CONFIG_GARP=y -CONFIG_MRP=y -CONFIG_BRIDGE=m -CONFIG_BRIDGE_IGMP_SNOOPING=y -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_BRIDGE_MRP=y -# CONFIG_BRIDGE_CFM is not set -CONFIG_NET_DSA=m -CONFIG_NET_DSA_TAG_NONE=m -CONFIG_NET_DSA_TAG_AR9331=m -CONFIG_NET_DSA_TAG_BRCM_COMMON=m -CONFIG_NET_DSA_TAG_BRCM=m -CONFIG_NET_DSA_TAG_BRCM_LEGACY=m -CONFIG_NET_DSA_TAG_BRCM_PREPEND=m -CONFIG_NET_DSA_TAG_HELLCREEK=m -CONFIG_NET_DSA_TAG_GSWIP=m -CONFIG_NET_DSA_TAG_DSA_COMMON=m -CONFIG_NET_DSA_TAG_DSA=m -CONFIG_NET_DSA_TAG_EDSA=m -CONFIG_NET_DSA_TAG_MTK=m -CONFIG_NET_DSA_TAG_KSZ=m -CONFIG_NET_DSA_TAG_OCELOT=m -CONFIG_NET_DSA_TAG_OCELOT_8021Q=m -CONFIG_NET_DSA_TAG_QCA=m -CONFIG_NET_DSA_TAG_RTL4_A=m -CONFIG_NET_DSA_TAG_RTL8_4=m -CONFIG_NET_DSA_TAG_RZN1_A5PSW=m -CONFIG_NET_DSA_TAG_LAN9303=m -CONFIG_NET_DSA_TAG_SJA1105=m -CONFIG_NET_DSA_TAG_TRAILER=m -CONFIG_NET_DSA_TAG_XRS700X=m -CONFIG_VLAN_8021Q=y -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_LLC=y -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_6LOWPAN=m -# CONFIG_6LOWPAN_DEBUGFS is not set -CONFIG_6LOWPAN_NHC=m -CONFIG_6LOWPAN_NHC_DEST=m -CONFIG_6LOWPAN_NHC_FRAGMENT=m -CONFIG_6LOWPAN_NHC_HOP=m -CONFIG_6LOWPAN_NHC_IPV6=m -CONFIG_6LOWPAN_NHC_MOBILITY=m -CONFIG_6LOWPAN_NHC_ROUTING=m -CONFIG_6LOWPAN_NHC_UDP=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -CONFIG_IEEE802154=m -CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y -CONFIG_IEEE802154_SOCKET=m -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_MAC802154=m -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_MQPRIO_LIB=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_SKBPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_CAKE=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_FQ_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_ETS=m -CONFIG_NET_SCH_DEFAULT=y -# CONFIG_DEFAULT_FQ is not set -# CONFIG_DEFAULT_CODEL is not set -# CONFIG_DEFAULT_FQ_CODEL is not set -# CONFIG_DEFAULT_FQ_PIE is not set -# CONFIG_DEFAULT_SFQ is not set -CONFIG_DEFAULT_PFIFO_FAST=y -CONFIG_DEFAULT_NET_SCH="pfifo_fast" - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_CANID=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_EMATCH_IPT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_MPLS=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_CTINFO=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m -CONFIG_NET_ACT_CT=m -CONFIG_NET_ACT_GATE=m -CONFIG_NET_IFE_SKBMARK=m -CONFIG_NET_IFE_SKBPRIO=m -CONFIG_NET_IFE_SKBTCINDEX=m -# CONFIG_NET_TC_SKB_EXT is not set -CONFIG_NET_SCH_FIFO=y -CONFIG_DCB=y -CONFIG_DNS_RESOLVER=y -CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_BATMAN_V=y -CONFIG_BATMAN_ADV_BLA=y -CONFIG_BATMAN_ADV_DAT=y -CONFIG_BATMAN_ADV_NC=y -CONFIG_BATMAN_ADV_MCAST=y -CONFIG_BATMAN_ADV_DEBUG=y -CONFIG_BATMAN_ADV_TRACING=y -CONFIG_OPENVSWITCH=m -CONFIG_OPENVSWITCH_GRE=m -CONFIG_OPENVSWITCH_VXLAN=m -CONFIG_OPENVSWITCH_GENEVE=m -CONFIG_VSOCKETS=m -CONFIG_VSOCKETS_DIAG=m -CONFIG_VSOCKETS_LOOPBACK=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS_COMMON=m -CONFIG_NETLINK_DIAG=m -CONFIG_MPLS=y -CONFIG_NET_MPLS_GSO=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m -CONFIG_NET_NSH=m -CONFIG_HSR=m -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_L3_MASTER_DEV=y -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set -CONFIG_PCPU_DEV_REFCNT=y -CONFIG_MAX_SKB_FRAGS=17 -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_XPS=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_CGROUP_NET_CLASSID=y -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -CONFIG_BPF_STREAM_PARSER=y -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -CONFIG_NET_PKTGEN=m -CONFIG_NET_DROP_MONITOR=m -# end of Network testing -# end of Networking options - -CONFIG_HAMRADIO=y - -# -# Packet Radio protocols -# -CONFIG_AX25=m -CONFIG_AX25_DAMA_SLAVE=y -CONFIG_NETROM=m -CONFIG_ROSE=m - -# -# AX.25 network device drivers -# -CONFIG_MKISS=m -CONFIG_6PACK=m -CONFIG_BPQETHER=m -CONFIG_BAYCOM_SER_FDX=m -CONFIG_BAYCOM_SER_HDX=m -CONFIG_YAM=m -# end of AX.25 network device drivers - -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_GW=m -CONFIG_CAN_J1939=m -# CONFIG_CAN_ISOTP is not set -CONFIG_BT=m -CONFIG_BT_BREDR=y -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_LE=y -CONFIG_BT_LE_L2CAP_ECRED=y -CONFIG_BT_6LOWPAN=m -CONFIG_BT_LEDS=y -# CONFIG_BT_MSFTEXT is not set -CONFIG_BT_AOSPEXT=y -# CONFIG_BT_DEBUGFS is not set -# CONFIG_BT_SELFTEST is not set - -# -# Bluetooth device drivers -# -CONFIG_BT_INTEL=m -CONFIG_BT_BCM=m -CONFIG_BT_RTL=m -CONFIG_BT_QCA=m -CONFIG_BT_MTK=m -CONFIG_BT_HCIBTUSB=m -# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set -CONFIG_BT_HCIBTUSB_POLL_SYNC=y -CONFIG_BT_HCIBTUSB_BCM=y -CONFIG_BT_HCIBTUSB_MTK=y -CONFIG_BT_HCIBTUSB_RTL=y -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_SERDEV=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_3WIRE=y -CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_RTL=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_AG6XX=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_HCIBCM203X=m -# CONFIG_BT_HCIBCM4377 is not set -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_BT_ATH3K=m -CONFIG_BT_MTKSDIO=m -CONFIG_BT_MTKUART=m -CONFIG_BT_HCIRSI=m -CONFIG_BT_VIRTIO=m -# CONFIG_BT_NXPUART is not set -# CONFIG_BT_INTEL_PCIE is not set -# end of Bluetooth device drivers - -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_IPV6 is not set -# CONFIG_AF_RXRPC_INJECT_LOSS is not set -# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -# CONFIG_RXPERF is not set -# CONFIG_AF_KCM is not set -CONFIG_STREAM_PARSER=y -# CONFIG_MCTP is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_CERTIFICATION_ONUS is not set -CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y -CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_CFG80211_CRDA_SUPPORT=y -CONFIG_CFG80211_WEXT=y -CONFIG_CFG80211_WEXT_EXPORT=y -# CONFIG_CFG80211_KUNIT_TEST is not set -CONFIG_LIB80211=m -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_HAS_RC=y -CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" -# CONFIG_MAC80211_KUNIT_TEST is not set -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_MESSAGE_TRACING is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=m -CONFIG_NET_9P_FD=m -CONFIG_NET_9P_VIRTIO=m -CONFIG_NET_9P_XEN=m -# CONFIG_NET_9P_DEBUG is not set -CONFIG_CAIF=m -# CONFIG_CAIF_DEBUG is not set -CONFIG_CAIF_NETDEV=m -CONFIG_CAIF_USB=m -CONFIG_CEPH_LIB=m -# CONFIG_CEPH_LIB_PRETTYDEBUG is not set -CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_SPI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_SHDLC=y - -# -# Near Field Communication (NFC) devices -# -CONFIG_NFC_TRF7970A=m -CONFIG_NFC_SIM=m -CONFIG_NFC_PORT100=m -CONFIG_NFC_VIRTUAL_NCI=m -CONFIG_NFC_FDP=m -CONFIG_NFC_FDP_I2C=m -CONFIG_NFC_PN544=m -CONFIG_NFC_PN544_I2C=m -CONFIG_NFC_PN533=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_PN533_I2C=m -CONFIG_NFC_PN532_UART=m -CONFIG_NFC_MICROREAD=m -CONFIG_NFC_MICROREAD_I2C=m -CONFIG_NFC_MRVL=m -CONFIG_NFC_MRVL_USB=m -CONFIG_NFC_MRVL_UART=m -CONFIG_NFC_MRVL_I2C=m -CONFIG_NFC_MRVL_SPI=m -CONFIG_NFC_ST21NFCA=m -CONFIG_NFC_ST21NFCA_I2C=m -CONFIG_NFC_ST_NCI=m -CONFIG_NFC_ST_NCI_I2C=m -CONFIG_NFC_ST_NCI_SPI=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_NXP_NCI_I2C=m -CONFIG_NFC_S3FWRN5=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_NFC_S3FWRN82_UART=m -CONFIG_NFC_ST95HF=m -# end of Near Field Communication (NFC) devices - -CONFIG_PSAMPLE=m -CONFIG_NET_IFE=m -CONFIG_LWTUNNEL=y -CONFIG_LWTUNNEL_BPF=y -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_SOCK_VALIDATE_XMIT=y -CONFIG_NET_IEEE8021Q_HELPERS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -CONFIG_NET_DEVLINK=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_FAILOVER=y -CONFIG_ETHTOOL_NETLINK=y -# CONFIG_NETDEV_ADDR_LIST_TEST is not set -# CONFIG_NET_TEST is not set - -# -# Device Drivers -# -CONFIG_ARM_AMBA=y -CONFIG_HAVE_PCI=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_SYSCALL=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_PCIEAER=y -CONFIG_PCIEAER_INJECT=m -CONFIG_PCIEAER_CXL=y -CONFIG_PCIE_ECRC=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -CONFIG_PCIE_PME=y -# CONFIG_PCIE_DPC is not set -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -CONFIG_PCI_STUB=y -# CONFIG_PCI_PF_STUB is not set -CONFIG_PCI_ATS=y -CONFIG_PCI_DOE=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -CONFIG_PCI_LABEL=y -# CONFIG_PCI_DYNAMIC_OF_NODES is not set -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA is not set -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set - -# -# PCI controller drivers -# -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -# CONFIG_PCI_FTPCI100 is not set -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -# CONFIG_PCIE_HISI_ERR is not set -# CONFIG_PCIE_MICROCHIP_HOST is not set -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCIE_ROCKCHIP_EP=y -CONFIG_PCI_XGENE=y -CONFIG_PCI_XGENE_MSI=y -# CONFIG_PCIE_XILINX is not set - -# -# Cadence-based PCIe controllers -# -# CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCIE_CADENCE_PLAT_EP is not set -# end of Cadence-based PCIe controllers - -# -# DesignWare-based PCIe controllers -# -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_DW_EP=y -# CONFIG_PCIE_AL is not set -# CONFIG_PCI_MESON is not set -CONFIG_PCI_HISI=y -# CONFIG_PCIE_KIRIN is not set -CONFIG_PCIE_DW_PLAT=y -CONFIG_PCIE_DW_PLAT_HOST=y -CONFIG_PCIE_DW_PLAT_EP=y -CONFIG_PCIE_ROCKCHIP_DW_HOST=y -# end of DesignWare-based PCIe controllers - -# -# Mobiveil-based PCIe controllers -# -# end of Mobiveil-based PCIe controllers -# end of PCI controller drivers - -# -# PCI Endpoint -# -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_PCI_EPF_NTB=m -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - -CONFIG_CXL_BUS=m -CONFIG_CXL_PCI=m -# CONFIG_CXL_MEM_RAW_COMMANDS is not set -CONFIG_CXL_ACPI=m -CONFIG_CXL_MEM=m -CONFIG_CXL_PORT=m -CONFIG_CXL_SUSPEND=y -CONFIG_CXL_REGION=y -# CONFIG_CXL_REGION_INVALIDATION_TEST is not set -# CONFIG_PCCARD is not set -# CONFIG_RAPIDIO is not set - -# -# Generic Driver Options -# -CONFIG_AUXILIARY_BUS=y -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_DEVTMPFS_SAFE is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Firmware loader -# -CONFIG_FW_LOADER=y -CONFIG_FW_LOADER_DEBUG=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set -# CONFIG_FW_LOADER_COMPRESS is not set -CONFIG_FW_CACHE=y -CONFIG_FW_UPLOAD=y -# end of Firmware loader - -CONFIG_WANT_DEV_COREDUMP=y -CONFIG_ALLOW_DEV_COREDUMP=y -CONFIG_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -CONFIG_HMEM_REPORTING=y -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -# CONFIG_DM_KUNIT_TEST is not set -# CONFIG_DRIVER_PE_KUNIT_TEST is not set -CONFIG_SYS_HYPERVISOR=y -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_SOC_BUS=y -CONFIG_REGMAP=y -# CONFIG_REGMAP_KUNIT is not set -# CONFIG_REGMAP_BUILD is not set -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SLIMBUS=m -CONFIG_REGMAP_SPI=m -CONFIG_REGMAP_SPMI=m -CONFIG_REGMAP_W1=m -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_SOUNDWIRE=m -CONFIG_REGMAP_SOUNDWIRE_MBQ=m -CONFIG_REGMAP_SCCB=m -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_ARCH_NUMA=y -# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set -# end of Generic Driver Options - -# -# Bus devices -# -CONFIG_ARM_CCI=y -CONFIG_ARM_CCI400_COMMON=y -# CONFIG_MOXTET is not set -CONFIG_VEXPRESS_CONFIG=y -CONFIG_MHI_BUS=m -# CONFIG_MHI_BUS_DEBUG is not set -CONFIG_MHI_BUS_PCI_GENERIC=m -# CONFIG_MHI_BUS_EP is not set -# end of Bus devices - -# -# Cache Drivers -# -# end of Cache Drivers - -CONFIG_CONNECTOR=m - -# -# Firmware Drivers -# - -# -# ARM System Control and Management Interface Protocol -# -CONFIG_ARM_SCMI_PROTOCOL=y -# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set -CONFIG_ARM_SCMI_HAVE_TRANSPORT=y -CONFIG_ARM_SCMI_HAVE_SHMEM=y -CONFIG_ARM_SCMI_HAVE_MSG=y -CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y -CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y -CONFIG_ARM_SCMI_TRANSPORT_SMC=y -# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set -CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y -CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y -# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set -CONFIG_ARM_SCMI_POWER_CONTROL=m -# end of ARM System Control and Management Interface Protocol - -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SDE_INTERFACE=y -# CONFIG_FIRMWARE_MEMMAP is not set -CONFIG_DMIID=y -CONFIG_DMI_SYSFS=y -CONFIG_ISCSI_IBFT=y -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_SYSFB=y -CONFIG_SYSFB_SIMPLEFB=y -CONFIG_ARM_FFA_TRANSPORT=m -CONFIG_ARM_FFA_SMCCC=y -CONFIG_FW_CS_DSP=m -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_ESRT=y -CONFIG_EFI_VARS_PSTORE=y -CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -CONFIG_EFI_SOFT_RESERVE=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB=y -# CONFIG_EFI_ZBOOT is not set -CONFIG_EFI_ARMSTUB_DTB_LOADER=y -CONFIG_EFI_BOOTLOADER_CONTROL=m -CONFIG_EFI_CAPSULE_LOADER=m -CONFIG_EFI_TEST=m -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_EFI_DISABLE_PCI_DMA=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y -# CONFIG_EFI_DISABLE_RUNTIME is not set -# CONFIG_EFI_COCO_SECRET is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_UEFI_CPER=y -CONFIG_UEFI_CPER_ARM=y -# CONFIG_TEE_STMM_EFI is not set -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_PSCI_CHECKER=y - -# -# Qualcomm firmware drivers -# -# end of Qualcomm firmware drivers - -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - -CONFIG_GNSS=m -CONFIG_GNSS_SERIAL=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_GNSS_SIRF_SERIAL=m -CONFIG_GNSS_UBX_SERIAL=m -# CONFIG_GNSS_USB is not set -CONFIG_MTD=y -# CONFIG_MTD_TESTS is not set - -# -# Partition parsers -# -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_AFS_PARTS=m -# CONFIG_MTD_REDBOOT_PARTS is not set -# end of Partition parsers - -# -# User Modules And Translation Layers -# -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y - -# -# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. -# -CONFIG_FTL=m -CONFIG_NFTL=m -CONFIG_NFTL_RW=y -CONFIG_INFTL=m -CONFIG_RFD_FTL=m -CONFIG_SSFDC=m -CONFIG_SM_FTL=m -# CONFIG_MTD_OOPS is not set -# CONFIG_MTD_PSTORE is not set -CONFIG_MTD_SWAP=m -# CONFIG_MTD_PARTITIONED_MASTER is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# end of RAM/ROM/Flash chip drivers - -# -# Mapping drivers for chip access -# -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -CONFIG_MTD_PHYSMAP_OF=y -# CONFIG_MTD_PHYSMAP_VERSATILE is not set -# CONFIG_MTD_PHYSMAP_GEMINI is not set -CONFIG_MTD_PHYSMAP_GPIO_ADDR=y -CONFIG_MTD_PCI=m -# CONFIG_MTD_PLATRAM is not set -# end of Mapping drivers for chip access - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -CONFIG_MTD_DATAFLASH=y -# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set -# CONFIG_MTD_DATAFLASH_OTP is not set -# CONFIG_MTD_MCHP23K256 is not set -CONFIG_MTD_MCHP48L640=m -CONFIG_MTD_SST25L=y -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOCG3 is not set -# end of Self-contained MTD device drivers - -# -# NAND -# -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_ONENAND=m -# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set -# CONFIG_MTD_ONENAND_GENERIC is not set -# CONFIG_MTD_ONENAND_OTP is not set -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -CONFIG_MTD_RAW_NAND=y - -# -# Raw/parallel NAND flash controllers -# -CONFIG_MTD_NAND_DENALI=y -# CONFIG_MTD_NAND_DENALI_PCI is not set -CONFIG_MTD_NAND_DENALI_DT=y -# CONFIG_MTD_NAND_CAFE is not set -# CONFIG_MTD_NAND_BRCMNAND is not set -# CONFIG_MTD_NAND_MXIC is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_NAND_CADENCE is not set -# CONFIG_MTD_NAND_ARASAN is not set -# CONFIG_MTD_NAND_INTEL_LGM is not set -CONFIG_MTD_NAND_ROCKCHIP=m - -# -# Misc -# -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_RICOH is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_SPI_NAND=m - -# -# ECC engine support -# -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set -# CONFIG_MTD_NAND_ECC_SW_BCH is not set -CONFIG_MTD_NAND_ECC_MXIC=y -# end of ECC engine support -# end of NAND - -# -# LPDDR & LPDDR2 PCM memory drivers -# -# CONFIG_MTD_LPDDR is not set -# end of LPDDR & LPDDR2 PCM memory drivers - -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set -CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y -# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UBI_BLOCK is not set -# CONFIG_MTD_UBI_NVMEM is not set -CONFIG_MTD_HYPERBUS=m -CONFIG_DTC=y -CONFIG_OF=y -# CONFIG_OF_UNITTEST is not set -# CONFIG_OF_KUNIT_TEST is not set -CONFIG_OF_FLATTREE=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_KOBJ=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OF_RESOLVE=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_NUMA=y -# CONFIG_PARPORT is not set -CONFIG_PNP=y -CONFIG_PNP_DEBUG_MESSAGES=y - -# -# Protocols -# -CONFIG_PNPACPI=y -CONFIG_BLK_DEV=y -CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_CDROM=y -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -CONFIG_ZRAM=m -CONFIG_ZRAM_DEF_COMP_LZORLE=y -# CONFIG_ZRAM_DEF_COMP_ZSTD is not set -# CONFIG_ZRAM_DEF_COMP_LZ4 is not set -# CONFIG_ZRAM_DEF_COMP_LZO is not set -# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set -# CONFIG_ZRAM_DEF_COMP_842 is not set -CONFIG_ZRAM_DEF_COMP="lzo-rle" -CONFIG_ZRAM_WRITEBACK=y -# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set -# CONFIG_ZRAM_MEMORY_TRACKING is not set -# CONFIG_ZRAM_MULTI_COMP is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -CONFIG_BLK_DEV_DRBD=m -# CONFIG_DRBD_FAULT_INJECTION is not set -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_ATA_OVER_ETH=m -CONFIG_XEN_BLKDEV_FRONTEND=m -CONFIG_XEN_BLKDEV_BACKEND=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_RBD=m -CONFIG_BLK_DEV_UBLK=m -CONFIG_BLKDEV_UBLK_LEGACY_OPCODES=y - -# -# NVME Support -# -CONFIG_NVME_KEYRING=m -CONFIG_NVME_AUTH=y -CONFIG_NVME_CORE=y -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -# CONFIG_NVME_VERBOSE_ERRORS is not set -CONFIG_NVME_HWMON=y -CONFIG_NVME_FABRICS=m -CONFIG_NVME_FC=m -CONFIG_NVME_TCP=m -CONFIG_NVME_TCP_TLS=y -CONFIG_NVME_HOST_AUTH=y -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_PASSTHRU=y -CONFIG_NVME_TARGET_LOOP=m -CONFIG_NVME_TARGET_FC=m -CONFIG_NVME_TARGET_FCLOOP=m -CONFIG_NVME_TARGET_TCP=m -CONFIG_NVME_TARGET_TCP_TLS=y -CONFIG_NVME_TARGET_AUTH=y -# end of NVME Support - -# -# Misc devices -# -CONFIG_AD525X_DPOT=m -CONFIG_AD525X_DPOT_I2C=m -CONFIG_AD525X_DPOT_SPI=m -# CONFIG_DUMMY_IRQ is not set -CONFIG_PHANTOM=m -CONFIG_TIFM_CORE=m -CONFIG_TIFM_7XX1=m -# CONFIG_ICS932S401 is not set -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_HI6421V600_IRQ=m -# CONFIG_HP_ILO is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_LATTICE_ECP3_CONFIG is not set -CONFIG_SRAM=y -CONFIG_DW_XDATA_PCIE=m -# CONFIG_PCI_ENDPOINT_TEST is not set -CONFIG_XILINX_SDFEC=m -CONFIG_MISC_RTSX=m -# CONFIG_HISI_HIKEY_USB is not set -# CONFIG_OPEN_DICE is not set -CONFIG_VCPU_STALL_DETECTOR=m -# CONFIG_NSM is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_EEPROM_MAX6875=m -CONFIG_EEPROM_93CX6=m -# CONFIG_EEPROM_93XX46 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -CONFIG_EEPROM_EE1004=m -# end of EEPROM support - -CONFIG_CB710_CORE=m -# CONFIG_CB710_DEBUG is not set -CONFIG_CB710_DEBUG_ASSUMPTIONS=y - -# -# Texas Instruments shared transport line discipline -# -# CONFIG_TI_ST is not set -# end of Texas Instruments shared transport line discipline - -# CONFIG_SENSORS_LIS3_I2C is not set -CONFIG_ALTERA_STAPL=m -# CONFIG_VMWARE_VMCI is not set -CONFIG_GENWQE=m -CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 -CONFIG_ECHO=m -CONFIG_BCM_VK=m -# CONFIG_BCM_VK_TTY is not set -CONFIG_MISC_ALCOR_PCI=m -CONFIG_MISC_RTSX_PCI=m -CONFIG_MISC_RTSX_USB=m -CONFIG_UACCE=m -# CONFIG_PVPANIC is not set -CONFIG_GP_PCI1XXXX=m -# end of Misc devices - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -CONFIG_RAID_ATTRS=m -CONFIG_SCSI_COMMON=y -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y -# CONFIG_SCSI_LIB_KUNIT_TEST is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -CONFIG_BLK_DEV_BSG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_ENCLOSURE=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -# CONFIG_SCSI_PROTO_TEST is not set - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SRP_ATTRS=m -# end of SCSI Transports - -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -CONFIG_ISCSI_BOOT_SYSFS=y -# CONFIG_SCSI_CXGB3_ISCSI is not set -# CONFIG_SCSI_CXGB4_ISCSI is not set -CONFIG_SCSI_BNX2_ISCSI=m -CONFIG_SCSI_BNX2X_FCOE=m -CONFIG_BE2ISCSI=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -CONFIG_SCSI_HPSA=m -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_3W_SAS is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_HISI_SAS is not set -CONFIG_SCSI_MVSAS=m -# CONFIG_SCSI_MVSAS_DEBUG is not set -CONFIG_SCSI_MVSAS_TASKLET=y -CONFIG_SCSI_MVUMI=m -# CONFIG_SCSI_ADVANSYS is not set -CONFIG_SCSI_ARCMSR=m -CONFIG_SCSI_ESAS2R=m -CONFIG_MEGARAID_NEWGEN=y -CONFIG_MEGARAID_MM=m -CONFIG_MEGARAID_MAILBOX=m -CONFIG_MEGARAID_LEGACY=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_MPT2SAS_MAX_SGE=128 -CONFIG_SCSI_MPT3SAS_MAX_SGE=128 -# CONFIG_SCSI_MPT2SAS is not set -CONFIG_SCSI_MPI3MR=m -# CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_HPTIOP is not set -CONFIG_SCSI_BUSLOGIC=m -CONFIG_SCSI_FLASHPOINT=y -# CONFIG_SCSI_MYRB is not set -# CONFIG_SCSI_MYRS is not set -# CONFIG_XEN_SCSI_FRONTEND is not set -CONFIG_LIBFC=m -CONFIG_LIBFCOE=m -CONFIG_FCOE=m -CONFIG_SCSI_SNIC=m -# CONFIG_SCSI_SNIC_DEBUG_FS is not set -CONFIG_SCSI_DMX3191D=m -# CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_IPS is not set -CONFIG_SCSI_INITIO=m -CONFIG_SCSI_INIA100=m -CONFIG_SCSI_STEX=m -CONFIG_SCSI_SYM53C8XX_2=m -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -CONFIG_SCSI_SYM53C8XX_MMIO=y -CONFIG_SCSI_IPR=m -CONFIG_SCSI_IPR_TRACE=y -CONFIG_SCSI_IPR_DUMP=y -CONFIG_SCSI_QLOGIC_1280=m -CONFIG_SCSI_QLA_FC=m -CONFIG_TCM_QLA2XXX=m -# CONFIG_TCM_QLA2XXX_DEBUG is not set -CONFIG_SCSI_QLA_ISCSI=m -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_EFCT is not set -CONFIG_SCSI_DC395x=m -CONFIG_SCSI_AM53C974=m -CONFIG_SCSI_WD719X=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_PMCRAID=m -# CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_BFA_FC is not set -CONFIG_SCSI_VIRTIO=y -CONFIG_SCSI_CHELSIO_FCOE=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -# end of SCSI device support - -CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_PATA_TIMINGS=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_ATA_ACPI=y -# CONFIG_SATA_ZPODD is not set -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# -CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_DWC=y -CONFIG_AHCI_CEVA=y -CONFIG_SATA_INIC162X=m -CONFIG_SATA_ACARD_AHCI=m -CONFIG_SATA_SIL24=y -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -CONFIG_PDC_ADMA=m -CONFIG_SATA_QSTOR=m -CONFIG_SATA_SX4=m -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# -CONFIG_ATA_PIIX=y -# CONFIG_SATA_DWC is not set -CONFIG_SATA_MV=m -CONFIG_SATA_NV=m -CONFIG_SATA_PROMISE=m -CONFIG_SATA_SIL=m -CONFIG_SATA_SIS=m -CONFIG_SATA_SVW=m -CONFIG_SATA_ULI=m -CONFIG_SATA_VIA=m -CONFIG_SATA_VITESSE=m - -# -# PATA SFF controllers with BMDMA -# -CONFIG_PATA_ALI=m -CONFIG_PATA_AMD=m -CONFIG_PATA_ARTOP=m -CONFIG_PATA_ATIIXP=m -CONFIG_PATA_ATP867X=m -CONFIG_PATA_CMD64X=m -CONFIG_PATA_CYPRESS=m -CONFIG_PATA_EFAR=m -CONFIG_PATA_HPT366=m -CONFIG_PATA_HPT37X=m -CONFIG_PATA_HPT3X2N=m -CONFIG_PATA_HPT3X3=m -# CONFIG_PATA_HPT3X3_DMA is not set -CONFIG_PATA_IT8213=m -CONFIG_PATA_IT821X=m -CONFIG_PATA_JMICRON=m -CONFIG_PATA_MARVELL=m -CONFIG_PATA_NETCELL=m -CONFIG_PATA_NINJA32=m -CONFIG_PATA_NS87415=m -CONFIG_PATA_OLDPIIX=m -CONFIG_PATA_OPTIDMA=m -CONFIG_PATA_PDC2027X=m -CONFIG_PATA_PDC_OLD=m -# CONFIG_PATA_RADISYS is not set -CONFIG_PATA_RDC=m -CONFIG_PATA_SCH=m -CONFIG_PATA_SERVERWORKS=m -CONFIG_PATA_SIL680=m -CONFIG_PATA_SIS=m -CONFIG_PATA_TOSHIBA=m -CONFIG_PATA_TRIFLEX=m -CONFIG_PATA_VIA=m -CONFIG_PATA_WINBOND=m - -# -# PIO-only SFF controllers -# -CONFIG_PATA_CMD640_PCI=m -CONFIG_PATA_MPIIX=m -CONFIG_PATA_NS87410=m -CONFIG_PATA_OPTI=m -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -CONFIG_PATA_ACPI=m -CONFIG_ATA_GENERIC=y -# CONFIG_PATA_LEGACY is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_AUTODETECT=y -CONFIG_MD_BITMAP_FILE=y -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_CLUSTER=m -CONFIG_BCACHE=m -# CONFIG_BCACHE_DEBUG is not set -# CONFIG_BCACHE_ASYNC_REGISTRATION is not set -CONFIG_BLK_DEV_DM_BUILTIN=y -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_BUFIO=m -# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set -CONFIG_DM_BIO_PRISON=m -CONFIG_DM_PERSISTENT_DATA=m -CONFIG_DM_UNSTRIPED=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m -CONFIG_DM_CACHE=m -CONFIG_DM_CACHE_SMQ=m -CONFIG_DM_WRITECACHE=m -# CONFIG_DM_EBS is not set -CONFIG_DM_ERA=m -CONFIG_DM_CLONE=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -# CONFIG_DM_MULTIPATH_HST is not set -CONFIG_DM_MULTIPATH_IOA=m -CONFIG_DM_DELAY=m -CONFIG_DM_DUST=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m -# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set -CONFIG_DM_VERITY_FEC=y -CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m -CONFIG_DM_ZONED=m -CONFIG_DM_AUDIT=y -# CONFIG_DM_VDO is not set -CONFIG_TARGET_CORE=m -CONFIG_TCM_IBLOCK=m -CONFIG_TCM_FILEIO=m -CONFIG_TCM_PSCSI=m -CONFIG_TCM_USER2=m -CONFIG_LOOPBACK_TARGET=m -CONFIG_TCM_FC=m -CONFIG_ISCSI_TARGET=m -# CONFIG_REMOTE_TARGET is not set -CONFIG_FUSION=y -CONFIG_FUSION_SPI=m -CONFIG_FUSION_FC=m -CONFIG_FUSION_SAS=m -CONFIG_FUSION_MAX_SGE=128 -CONFIG_FUSION_CTL=m -CONFIG_FUSION_LAN=m -# CONFIG_FUSION_LOGGING is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -CONFIG_FIREWIRE_NOSY=m -# end of IEEE 1394 (FireWire) support - -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -# CONFIG_WIREGUARD_DEBUG is not set -CONFIG_EQUALIZER=m -CONFIG_NET_FC=y -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN_L3S=y -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_BAREUDP=m -CONFIG_GTP=m -# CONFIG_PFCP is not set -CONFIG_AMT=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=y -CONFIG_NETCONSOLE_DYNAMIC=y -# CONFIG_NETCONSOLE_EXTENDED_LOG is not set -CONFIG_NETPOLL=y -CONFIG_NET_POLL_CONTROLLER=y -CONFIG_TUN=m -CONFIG_TAP=m -CONFIG_TUN_VNET_CROSS_LE=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=m -CONFIG_NLMON=m -# CONFIG_NETKIT is not set -CONFIG_NET_VRF=m -CONFIG_MHI_NET=m -# CONFIG_ARCNET is not set -CONFIG_ATM_DRIVERS=y -CONFIG_ATM_DUMMY=m -CONFIG_ATM_TCP=m -CONFIG_ATM_LANAI=m -CONFIG_ATM_ENI=m -# CONFIG_ATM_ENI_DEBUG is not set -# CONFIG_ATM_ENI_TUNE_BURST is not set -CONFIG_ATM_NICSTAR=m -# CONFIG_ATM_NICSTAR_USE_SUNI is not set -# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set -CONFIG_ATM_IDT77252=m -# CONFIG_ATM_IDT77252_DEBUG is not set -# CONFIG_ATM_IDT77252_RCV_ALL is not set -CONFIG_ATM_IDT77252_USE_SUNI=y -CONFIG_ATM_IA=m -# CONFIG_ATM_IA_DEBUG is not set -CONFIG_ATM_FORE200E=m -# CONFIG_ATM_FORE200E_USE_TASKLET is not set -CONFIG_ATM_FORE200E_TX_RETRY=16 -CONFIG_ATM_FORE200E_DEBUG=0 -CONFIG_ATM_HE=m -# CONFIG_ATM_HE_USE_SUNI is not set -CONFIG_ATM_SOLOS=m -CONFIG_CAIF_DRIVERS=y -CONFIG_CAIF_TTY=m -CONFIG_CAIF_VIRTIO=m - -# -# Distributed Switch Architecture drivers -# -CONFIG_B53=m -CONFIG_B53_SPI_DRIVER=m -CONFIG_B53_MDIO_DRIVER=m -CONFIG_B53_MMAP_DRIVER=m -CONFIG_B53_SRAB_DRIVER=m -CONFIG_B53_SERDES=m -CONFIG_NET_DSA_BCM_SF2=m -CONFIG_NET_DSA_LOOP=m -CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m -CONFIG_NET_DSA_LANTIQ_GSWIP=m -CONFIG_NET_DSA_MT7530=m -CONFIG_NET_DSA_MT7530_MDIO=m -CONFIG_NET_DSA_MT7530_MMIO=m -CONFIG_NET_DSA_MV88E6060=m -CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m -CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m -# CONFIG_NET_DSA_MICROCHIP_KSZ_PTP is not set -CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m -CONFIG_NET_DSA_MV88E6XXX=m -# CONFIG_NET_DSA_MV88E6XXX_PTP is not set -# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set -# CONFIG_NET_DSA_MSCC_SEVILLE is not set -CONFIG_NET_DSA_AR9331=m -CONFIG_NET_DSA_QCA8K=m -# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set -CONFIG_NET_DSA_SJA1105=m -# CONFIG_NET_DSA_SJA1105_PTP is not set -CONFIG_NET_DSA_XRS700X=m -CONFIG_NET_DSA_XRS700X_I2C=m -CONFIG_NET_DSA_XRS700X_MDIO=m -CONFIG_NET_DSA_REALTEK=m -# CONFIG_NET_DSA_REALTEK_MDIO is not set -# CONFIG_NET_DSA_REALTEK_SMI is not set -CONFIG_NET_DSA_SMSC_LAN9303=m -CONFIG_NET_DSA_SMSC_LAN9303_I2C=m -CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m -CONFIG_NET_DSA_VITESSE_VSC73XX=m -CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m -CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m -# end of Distributed Switch Architecture drivers - -CONFIG_ETHERNET=y -CONFIG_MDIO=m -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -CONFIG_ET131X=m -CONFIG_NET_VENDOR_ALACRITECH=y -# CONFIG_SLICOSS is not set -CONFIG_NET_VENDOR_ALTEON=y -CONFIG_ACENIC=m -# CONFIG_ACENIC_OMIT_TIGON_I is not set -CONFIG_ALTERA_TSE=m -CONFIG_NET_VENDOR_AMAZON=y -# CONFIG_ENA_ETHERNET is not set -CONFIG_NET_VENDOR_AMD=y -CONFIG_AMD8111_ETH=m -CONFIG_PCNET32=m -CONFIG_AMD_XGBE=m -# CONFIG_AMD_XGBE_DCB is not set -# CONFIG_PDS_CORE is not set -CONFIG_NET_VENDOR_AQUANTIA=y -CONFIG_AQTION=m -CONFIG_NET_VENDOR_ARC=y -# CONFIG_EMAC_ROCKCHIP is not set -CONFIG_NET_VENDOR_ASIX=y -# CONFIG_SPI_AX88796C is not set -CONFIG_NET_VENDOR_ATHEROS=y -CONFIG_ATL2=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -CONFIG_NET_VENDOR_BROADCOM=y -CONFIG_B44=m -CONFIG_B44_PCI_AUTOSELECT=y -CONFIG_B44_PCICORE_AUTOSELECT=y -CONFIG_B44_PCI=y -CONFIG_BCMGENET=m -CONFIG_BNX2=m -CONFIG_CNIC=m -CONFIG_TIGON3=m -CONFIG_TIGON3_HWMON=y -CONFIG_BNX2X=m -CONFIG_BNX2X_SRIOV=y -CONFIG_SYSTEMPORT=m -CONFIG_BNXT=m -CONFIG_BNXT_SRIOV=y -CONFIG_BNXT_FLOWER_OFFLOAD=y -# CONFIG_BNXT_DCB is not set -CONFIG_BNXT_HWMON=y -CONFIG_NET_VENDOR_CADENCE=y -CONFIG_MACB=y -CONFIG_MACB_USE_HWSTAMP=y -# CONFIG_MACB_PCI is not set -CONFIG_NET_VENDOR_CAVIUM=y -CONFIG_THUNDER_NIC_PF=y -# CONFIG_THUNDER_NIC_VF is not set -CONFIG_THUNDER_NIC_BGX=y -CONFIG_THUNDER_NIC_RGX=y -CONFIG_CAVIUM_PTP=y -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -CONFIG_NET_VENDOR_CORTINA=y -# CONFIG_GEMINI_ETHERNET is not set -CONFIG_NET_VENDOR_DAVICOM=y -# CONFIG_DM9051 is not set -CONFIG_DNET=m -CONFIG_NET_VENDOR_DEC=y -# CONFIG_NET_TULIP is not set -CONFIG_NET_VENDOR_DLINK=y -CONFIG_DL2K=m -CONFIG_SUNDANCE=m -# CONFIG_SUNDANCE_MMIO is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_ENGLEDER=y -# CONFIG_TSNEP is not set -CONFIG_NET_VENDOR_EZCHIP=y -# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_FUNGIBLE=y -# CONFIG_FUN_ETH is not set -CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set -CONFIG_NET_VENDOR_HISILICON=y -CONFIG_HIX5HD2_GMAC=y -# CONFIG_HISI_FEMAC is not set -# CONFIG_HIP04_ETH is not set -CONFIG_HNS_MDIO=y -CONFIG_HNS=y -CONFIG_HNS_DSAF=y -CONFIG_HNS_ENET=y -CONFIG_HNS3=y -CONFIG_HNS3_HCLGE=y -# CONFIG_HNS3_DCB is not set -# CONFIG_HNS3_HCLGEVF is not set -CONFIG_HNS3_ENET=y -CONFIG_NET_VENDOR_HUAWEI=y -# CONFIG_HINIC is not set -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y -CONFIG_LIBETH=m -CONFIG_LIBIE=m -CONFIG_E100=m -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_IGB=m -CONFIG_IGB_HWMON=y -CONFIG_IGBVF=m -CONFIG_IXGBE=m -CONFIG_IXGBE_HWMON=y -CONFIG_IXGBE_DCB=y -CONFIG_IXGBE_IPSEC=y -CONFIG_IXGBEVF=m -CONFIG_IXGBEVF_IPSEC=y -CONFIG_I40E=m -# CONFIG_I40E_DCB is not set -CONFIG_IAVF=m -CONFIG_I40EVF=m -# CONFIG_ICE is not set -CONFIG_FM10K=m -# CONFIG_IGC is not set -# CONFIG_IDPF is not set -CONFIG_JME=m -CONFIG_NET_VENDOR_ADI=y -CONFIG_ADIN1110=m -CONFIG_NET_VENDOR_LITEX=y -CONFIG_LITEX_LITEETH=m -CONFIG_NET_VENDOR_MARVELL=y -CONFIG_MVMDIO=m -CONFIG_SKGE=m -# CONFIG_SKGE_DEBUG is not set -CONFIG_SKGE_GENESIS=y -CONFIG_SKY2=m -# CONFIG_SKY2_DEBUG is not set -CONFIG_OCTEONTX2_MBOX=m -# CONFIG_OCTEONTX2_AF is not set -CONFIG_OCTEONTX2_PF=m -CONFIG_OCTEONTX2_VF=m -# CONFIG_OCTEON_EP is not set -# CONFIG_OCTEON_EP_VF is not set -# CONFIG_PRESTERA is not set -CONFIG_NET_VENDOR_MELLANOX=y -CONFIG_MLX4_EN=m -CONFIG_MLX4_EN_DCB=y -CONFIG_MLX4_CORE=m -CONFIG_MLX4_DEBUG=y -CONFIG_MLX4_CORE_GEN2=y -CONFIG_MLX5_CORE=m -# CONFIG_MLX5_FPGA is not set -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_EN_ARFS=y -CONFIG_MLX5_EN_RXNFC=y -CONFIG_MLX5_MPFS=y -CONFIG_MLX5_ESWITCH=y -CONFIG_MLX5_BRIDGE=y -CONFIG_MLX5_CORE_EN_DCB=y -# CONFIG_MLX5_CORE_IPOIB is not set -# CONFIG_MLX5_MACSEC is not set -# CONFIG_MLX5_EN_IPSEC is not set -# CONFIG_MLX5_EN_TLS is not set -CONFIG_MLX5_SW_STEERING=y -# CONFIG_MLX5_SF is not set -# CONFIG_MLX5_DPLL is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLXFW is not set -CONFIG_MLXBF_GIGE=m -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_KSZ884X_PCI=m -CONFIG_NET_VENDOR_MICROCHIP=y -CONFIG_ENC28J60=m -CONFIG_ENC28J60_WRITEVERIFY=y -# CONFIG_ENCX24J600 is not set -# CONFIG_LAN743X is not set -# CONFIG_LAN966X_SWITCH is not set -# CONFIG_VCAP is not set -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_MSCC_OCELOT_SWITCH_LIB=m -CONFIG_MSCC_OCELOT_SWITCH=m -CONFIG_NET_VENDOR_MICROSOFT=y -CONFIG_NET_VENDOR_MYRI=y -CONFIG_MYRI10GE=m -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_NATSEMI=y -CONFIG_NATSEMI=m -CONFIG_NS83820=m -CONFIG_NET_VENDOR_NETERION=y -# CONFIG_S2IO is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP is not set -CONFIG_NET_VENDOR_8390=y -CONFIG_NE2K_PCI=m -CONFIG_NET_VENDOR_NVIDIA=y -CONFIG_FORCEDETH=m -CONFIG_NET_VENDOR_OKI=y -CONFIG_ETHOC=m -CONFIG_NET_VENDOR_PACKET_ENGINES=y -CONFIG_HAMACHI=m -CONFIG_YELLOWFIN=m -CONFIG_NET_VENDOR_PENSANDO=y -CONFIG_IONIC=m -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_BROCADE=y -CONFIG_BNA=m -CONFIG_NET_VENDOR_QUALCOMM=y -CONFIG_QCA7000=m -# CONFIG_QCA7000_SPI is not set -CONFIG_QCA7000_UART=m -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_REALTEK=y -CONFIG_8139CP=m -CONFIG_8139TOO=m -CONFIG_8139TOO_PIO=y -CONFIG_8139TOO_TUNE_TWISTER=y -CONFIG_8139TOO_8129=y -CONFIG_8139_OLD_RX_RESET=y -CONFIG_R8169=m -CONFIG_R8169_LEDS=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_ROCKER=m -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -# CONFIG_SFC_SIENA is not set -CONFIG_NET_VENDOR_SMSC=y -CONFIG_SMC91X=y -# CONFIG_EPIC100 is not set -CONFIG_SMSC911X=y -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_STMICRO=y -CONFIG_STMMAC_ETH=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_STMMAC_PLATFORM=y -# CONFIG_DWMAC_DWC_QOS_ETH is not set -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -# CONFIG_DWMAC_INTEL_PLAT is not set -# CONFIG_STMMAC_PCI is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_NET_VENDOR_TEHUTI=y -CONFIG_TEHUTI=m -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VERTEXCOM=y -# CONFIG_MSE102X is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WANGXUN=y -CONFIG_LIBWX=m -CONFIG_NGBE=m -# CONFIG_TXGBE is not set -CONFIG_NET_VENDOR_WIZNET=y -# CONFIG_WIZNET_W5100 is not set -# CONFIG_WIZNET_W5300 is not set -CONFIG_NET_VENDOR_XILINX=y -CONFIG_XILINX_EMACLITE=m -CONFIG_XILINX_LL_TEMAC=m -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PHYLINK=y -CONFIG_PHYLIB=y -CONFIG_SWPHY=y -CONFIG_LED_TRIGGER_PHY=y -CONFIG_PHYLIB_LEDS=y -CONFIG_FIXED_PHY=y -CONFIG_SFP=m - -# -# MII PHY device drivers -# -# CONFIG_AIR_EN8811H_PHY is not set -CONFIG_AMD_PHY=m -CONFIG_ADIN_PHY=m -CONFIG_ADIN1100_PHY=m -CONFIG_AQUANTIA_PHY=m -CONFIG_AX88796B_PHY=m -CONFIG_BROADCOM_PHY=m -# CONFIG_BCM54140_PHY is not set -CONFIG_BCM7XXX_PHY=m -CONFIG_BCM84881_PHY=m -CONFIG_BCM87XX_PHY=m -CONFIG_BCM_NET_PHYLIB=m -CONFIG_BCM_NET_PHYPTP=m -CONFIG_CICADA_PHY=m -# CONFIG_CORTINA_PHY is not set -CONFIG_DAVICOM_PHY=m -CONFIG_ICPLUS_PHY=m -CONFIG_LXT_PHY=m -# CONFIG_INTEL_XWAY_PHY is not set -CONFIG_LSI_ET1011C_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -# CONFIG_MARVELL_88Q2XXX_PHY is not set -CONFIG_MARVELL_88X2222_PHY=m -CONFIG_MAXLINEAR_GPHY=m -CONFIG_MEDIATEK_GE_PHY=m -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MICREL_PHY=y -# CONFIG_MICROCHIP_T1S_PHY is not set -CONFIG_MICROCHIP_PHY=m -CONFIG_MICROCHIP_T1_PHY=m -CONFIG_MICROSEMI_PHY=m -CONFIG_MOTORCOMM_PHY=y -CONFIG_NATIONAL_PHY=m -# CONFIG_NXP_CBTX_PHY is not set -CONFIG_NXP_C45_TJA11XX_PHY=m -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_NCN26000_PHY is not set -CONFIG_QCOM_NET_PHYLIB=m -CONFIG_AT803X_PHY=m -# CONFIG_QCA83XX_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA807X_PHY is not set -CONFIG_QSEMI_PHY=m -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -CONFIG_ROCKCHIP_PHY=y -CONFIG_SMSC_PHY=m -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -CONFIG_DP83TC811_PHY=m -CONFIG_DP83848_PHY=m -# CONFIG_DP83867_PHY is not set -CONFIG_DP83869_PHY=m -CONFIG_DP83TD510_PHY=m -# CONFIG_DP83TG720_PHY is not set -CONFIG_VITESSE_PHY=m -# CONFIG_XILINX_GMII2RGMII is not set -# CONFIG_MICREL_KS8995MA is not set -CONFIG_PSE_CONTROLLER=y -CONFIG_PSE_REGULATOR=m -# CONFIG_PSE_PD692X0 is not set -# CONFIG_PSE_TPS23881 is not set -CONFIG_CAN_DEV=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_NETLINK=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_RX_OFFLOAD=y -# CONFIG_CAN_CAN327 is not set -# CONFIG_CAN_FLEXCAN is not set -CONFIG_CAN_GRCAN=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_XILINXCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_PLATFORM=m -# CONFIG_CAN_CTUCANFD_PCI is not set -# CONFIG_CAN_CTUCANFD_PLATFORM is not set -# CONFIG_CAN_ESD_402_PCI is not set -# CONFIG_CAN_IFI_CANFD is not set -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCIEC=y -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m - -# -# CAN SPI interfaces -# -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -# CONFIG_CAN_MCP251XFD_SANITY is not set -# end of CAN SPI interfaces - -# -# CAN USB interfaces -# -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB=m -CONFIG_CAN_ETAS_ES58X=m -# CONFIG_CAN_F81604 is not set -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -# end of CAN USB interfaces - -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_FWNODE_MDIO=y -CONFIG_OF_MDIO=y -CONFIG_ACPI_MDIO=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BCM_UNIMAC=m -CONFIG_MDIO_CAVIUM=y -CONFIG_MDIO_GPIO=m -# CONFIG_MDIO_HISI_FEMAC is not set -CONFIG_MDIO_I2C=m -CONFIG_MDIO_MVUSB=m -CONFIG_MDIO_MSCC_MIIM=m -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_IPQ4019 is not set -CONFIG_MDIO_IPQ8064=m -CONFIG_MDIO_REGMAP=m -CONFIG_MDIO_THUNDER=y - -# -# MDIO Multiplexers -# -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=m -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y - -# -# PCS device drivers -# -CONFIG_PCS_XPCS=y -CONFIG_PCS_LYNX=m -CONFIG_PCS_MTK_LYNXI=m -# end of PCS device drivers - -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOATM=m -CONFIG_PPPOE=m -# CONFIG_PPPOE_HASH_BITS_1 is not set -# CONFIG_PPPOE_HASH_BITS_2 is not set -CONFIG_PPPOE_HASH_BITS_4=y -# CONFIG_PPPOE_HASH_BITS_8 is not set -CONFIG_PPPOE_HASH_BITS=4 -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLHC=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_CDC_NCM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_CDC_SUBSET_ENABLE=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=m -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -CONFIG_USB_NET_AQC111=m -CONFIG_USB_RTL8153_ECM=m -CONFIG_WLAN=y -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_ADM8211=m -CONFIG_ATH_COMMON=m -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -CONFIG_ATH5K=m -# CONFIG_ATH5K_DEBUG is not set -# CONFIG_ATH5K_TRACER is not set -CONFIG_ATH5K_PCI=y -CONFIG_ATH9K_HW=m -CONFIG_ATH9K_COMMON=m -CONFIG_ATH9K_BTCOEX_SUPPORT=y -CONFIG_ATH9K=m -CONFIG_ATH9K_PCI=y -CONFIG_ATH9K_AHB=y -CONFIG_ATH9K_DYNACK=y -CONFIG_ATH9K_WOW=y -CONFIG_ATH9K_RFKILL=y -CONFIG_ATH9K_CHANNEL_CONTEXT=y -CONFIG_ATH9K_PCOEM=y -CONFIG_ATH9K_PCI_NO_EEPROM=m -CONFIG_ATH9K_HTC=m -# CONFIG_ATH9K_HTC_DEBUGFS is not set -CONFIG_ATH9K_HWRNG=y -CONFIG_CARL9170=m -CONFIG_CARL9170_LEDS=y -CONFIG_CARL9170_WPC=y -CONFIG_CARL9170_HWRNG=y -CONFIG_ATH6KL=m -CONFIG_ATH6KL_SDIO=m -CONFIG_ATH6KL_USB=m -# CONFIG_ATH6KL_DEBUG is not set -# CONFIG_ATH6KL_TRACING is not set -CONFIG_AR5523=m -CONFIG_WIL6210=m -CONFIG_WIL6210_ISR_COR=y -# CONFIG_WIL6210_TRACING is not set -# CONFIG_WIL6210_DEBUGFS is not set -CONFIG_ATH10K=m -CONFIG_ATH10K_CE=y -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_AHB=y -CONFIG_ATH10K_SDIO=m -CONFIG_ATH10K_USB=m -# CONFIG_ATH10K_DEBUG is not set -# CONFIG_ATH10K_DEBUGFS is not set -# CONFIG_ATH10K_TRACING is not set -CONFIG_WCN36XX=m -# CONFIG_WCN36XX_DEBUGFS is not set -CONFIG_ATH11K=m -CONFIG_ATH11K_AHB=m -# CONFIG_ATH11K_PCI is not set -# CONFIG_ATH11K_DEBUG is not set -# CONFIG_ATH11K_TRACING is not set -# CONFIG_ATH12K is not set -CONFIG_WLAN_VENDOR_ATMEL=y -CONFIG_AT76C50X_USB=m -CONFIG_WLAN_VENDOR_BROADCOM=y -CONFIG_B43=m -CONFIG_B43_BCMA=y -CONFIG_B43_SSB=y -CONFIG_B43_BUSES_BCMA_AND_SSB=y -# CONFIG_B43_BUSES_BCMA is not set -# CONFIG_B43_BUSES_SSB is not set -CONFIG_B43_PCI_AUTOSELECT=y -CONFIG_B43_PCICORE_AUTOSELECT=y -CONFIG_B43_SDIO=y -CONFIG_B43_BCMA_PIO=y -CONFIG_B43_PIO=y -CONFIG_B43_PHY_G=y -CONFIG_B43_PHY_N=y -CONFIG_B43_PHY_LP=y -CONFIG_B43_PHY_HT=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -CONFIG_B43LEGACY=m -CONFIG_B43LEGACY_PCI_AUTOSELECT=y -CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y -CONFIG_B43LEGACY_LEDS=y -CONFIG_B43LEGACY_HWRNG=y -# CONFIG_B43LEGACY_DEBUG is not set -CONFIG_B43LEGACY_DMA=y -CONFIG_B43LEGACY_PIO=y -CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y -# CONFIG_B43LEGACY_DMA_MODE is not set -# CONFIG_B43LEGACY_PIO_MODE is not set -CONFIG_BRCMUTIL=m -CONFIG_BRCMSMAC=m -CONFIG_BRCMSMAC_LEDS=y -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_PROTO_BCDC=y -CONFIG_BRCMFMAC_PROTO_MSGBUF=y -CONFIG_BRCMFMAC_SDIO=y -CONFIG_BRCMFMAC_USB=y -CONFIG_BRCMFMAC_PCIE=y -CONFIG_BRCM_TRACING=y -# CONFIG_BRCMDBG is not set -CONFIG_WLAN_VENDOR_INTEL=y -CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -# CONFIG_IPW2100_DEBUG is not set -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_RADIOTAP=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -# CONFIG_IPW2200_DEBUG is not set -CONFIG_LIBIPW=m -# CONFIG_LIBIPW_DEBUG is not set -CONFIG_IWLEGACY=m -CONFIG_IWL4965=m -CONFIG_IWL3945=m - -# -# iwl3945 / iwl4965 Debugging Options -# -# CONFIG_IWLEGACY_DEBUG is not set -# end of iwl3945 / iwl4965 Debugging Options - -CONFIG_IWLWIFI=m -CONFIG_IWLWIFI_LEDS=y -CONFIG_IWLDVM=m -CONFIG_IWLMVM=m -CONFIG_IWLWIFI_OPMODE_MODULAR=y - -# -# Debugging Options -# -# CONFIG_IWLWIFI_DEBUG is not set -CONFIG_IWLWIFI_DEVICE_TRACING=y -# end of Debugging Options - -CONFIG_WLAN_VENDOR_INTERSIL=y -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_PCI is not set -CONFIG_P54_SPI=m -CONFIG_P54_SPI_DEFAULT_EEPROM=y -CONFIG_P54_LEDS=y -CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_LIBERTAS_MESH=y -CONFIG_LIBERTAS_THINFIRM=m -# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set -CONFIG_LIBERTAS_THINFIRM_USB=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_MWIFIEX_USB=m -CONFIG_MWL8K=m -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_MT7601U=m -CONFIG_MT76_CORE=m -CONFIG_MT76_LEDS=y -CONFIG_MT76_USB=m -CONFIG_MT76_SDIO=m -CONFIG_MT76x02_LIB=m -CONFIG_MT76x02_USB=m -CONFIG_MT76_CONNAC_LIB=m -CONFIG_MT792x_LIB=m -CONFIG_MT792x_USB=m -CONFIG_MT76x0_COMMON=m -CONFIG_MT76x0U=m -CONFIG_MT76x0E=m -CONFIG_MT76x2_COMMON=m -CONFIG_MT76x2E=m -CONFIG_MT76x2U=m -CONFIG_MT7603E=m -CONFIG_MT7615_COMMON=m -CONFIG_MT7615E=m -CONFIG_MT7663_USB_SDIO_COMMON=m -CONFIG_MT7663U=m -CONFIG_MT7663S=m -CONFIG_MT7915E=m -CONFIG_MT7921_COMMON=m -CONFIG_MT7921E=m -CONFIG_MT7921S=m -CONFIG_MT7921U=m -CONFIG_MT7996E=m -CONFIG_MT7925_COMMON=m -CONFIG_MT7925E=m -CONFIG_MT7925U=m -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WILC1000=m -CONFIG_WILC1000_SDIO=m -CONFIG_WILC1000_SPI=m -# CONFIG_WILC1000_HW_OOB_INTR is not set -CONFIG_WLAN_VENDOR_PURELIFI=y -# CONFIG_PLFXLC is not set -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_RT2X00=m -CONFIG_RT2400PCI=m -CONFIG_RT2500PCI=m -CONFIG_RT61PCI=m -CONFIG_RT2800PCI=m -CONFIG_RT2800PCI_RT33XX=y -CONFIG_RT2800PCI_RT35XX=y -CONFIG_RT2800PCI_RT53XX=y -CONFIG_RT2800PCI_RT3290=y -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT33XX=y -CONFIG_RT2800USB_RT35XX=y -CONFIG_RT2800USB_RT3573=y -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_RT55XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RT2800_LIB=m -CONFIG_RT2800_LIB_MMIO=m -CONFIG_RT2X00_LIB_MMIO=m -CONFIG_RT2X00_LIB_PCI=m -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -CONFIG_RTL_CARDS=m -CONFIG_RTL8192CE=m -CONFIG_RTL8192SE=m -CONFIG_RTL8192DE=m -CONFIG_RTL8723AE=m -CONFIG_RTL8723BE=m -CONFIG_RTL8188EE=m -CONFIG_RTL8192EE=m -CONFIG_RTL8821AE=m -CONFIG_RTL8192CU=m -CONFIG_RTLWIFI=m -CONFIG_RTLWIFI_PCI=m -CONFIG_RTLWIFI_USB=m -# CONFIG_RTLWIFI_DEBUG is not set -CONFIG_RTL8192C_COMMON=m -CONFIG_RTL8192D_COMMON=m -CONFIG_RTL8723_COMMON=m -CONFIG_RTLBTCOEXIST=m -CONFIG_RTL8XXXU=m -# CONFIG_RTL8XXXU_UNTESTED is not set -CONFIG_RTW88=m -CONFIG_RTW88_CORE=m -CONFIG_RTW88_PCI=m -CONFIG_RTW88_USB=m -CONFIG_RTW88_8822B=m -CONFIG_RTW88_8822C=m -CONFIG_RTW88_8723X=m -CONFIG_RTW88_8723D=m -CONFIG_RTW88_8821C=m -CONFIG_RTW88_8822BE=m -# CONFIG_RTW88_8822BS is not set -CONFIG_RTW88_8822BU=m -CONFIG_RTW88_8822CE=m -# CONFIG_RTW88_8822CS is not set -CONFIG_RTW88_8822CU=m -CONFIG_RTW88_8723DE=m -# CONFIG_RTW88_8723DS is not set -# CONFIG_RTW88_8723CS is not set -CONFIG_RTW88_8723DU=m -CONFIG_RTW88_8821CE=m -# CONFIG_RTW88_8821CS is not set -CONFIG_RTW88_8821CU=m -# CONFIG_RTW88_DEBUG is not set -# CONFIG_RTW88_DEBUGFS is not set -CONFIG_RTW89=m -CONFIG_RTW89_CORE=m -CONFIG_RTW89_PCI=m -CONFIG_RTW89_8851B=m -CONFIG_RTW89_8852A=m -CONFIG_RTW89_8852B=m -CONFIG_RTW89_8852C=m -CONFIG_RTW89_8851BE=m -CONFIG_RTW89_8852AE=m -CONFIG_RTW89_8852BE=m -CONFIG_RTW89_8852CE=m -# CONFIG_RTW89_8922AE is not set -# CONFIG_RTW89_DEBUGMSG is not set -# CONFIG_RTW89_DEBUGFS is not set -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_RSI_91X=m -# CONFIG_RSI_DEBUGFS is not set -CONFIG_RSI_SDIO=m -CONFIG_RSI_USB=m -CONFIG_RSI_COEX=y -CONFIG_WLAN_VENDOR_SILABS=y -CONFIG_WFX=m -CONFIG_WLAN_VENDOR_ST=y -CONFIG_CW1200=m -CONFIG_CW1200_WLAN_SDIO=m -CONFIG_CW1200_WLAN_SPI=m -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL12XX=m -CONFIG_WL18XX=m -CONFIG_WLCORE=m -CONFIG_WLCORE_SPI=m -CONFIG_WLCORE_SDIO=m -# CONFIG_RTL8723DS is not set -# CONFIG_RTL8822BU is not set -# CONFIG_RTL8821CU is not set -# CONFIG_88XXAU is not set -# CONFIG_RTL8192EU is not set -# CONFIG_RTL8189FS is not set -# CONFIG_RTL8189ES is not set -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set -CONFIG_WLAN_VENDOR_QUANTENNA=y -CONFIG_QTNFMAC=m -CONFIG_QTNFMAC_PCIE=m -CONFIG_MAC80211_HWSIM=m -CONFIG_VIRT_WIFI=m -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -# CONFIG_HDLC_CISCO is not set -# CONFIG_HDLC_FR is not set -# CONFIG_HDLC_PPP is not set -# CONFIG_HDLC_X25 is not set -# CONFIG_FRAMER is not set -# CONFIG_PCI200SYN is not set -# CONFIG_WANXL is not set -# CONFIG_PC300TOO is not set -# CONFIG_FARSYNC is not set -# CONFIG_LAPBETHER is not set -CONFIG_IEEE802154_DRIVERS=m -CONFIG_IEEE802154_FAKELB=m -CONFIG_IEEE802154_AT86RF230=m -CONFIG_IEEE802154_MRF24J40=m -CONFIG_IEEE802154_CC2520=m -CONFIG_IEEE802154_ATUSB=m -CONFIG_IEEE802154_ADF7242=m -CONFIG_IEEE802154_CA8210=m -# CONFIG_IEEE802154_CA8210_DEBUGFS is not set -CONFIG_IEEE802154_MCR20A=m -CONFIG_IEEE802154_HWSIM=m - -# -# Wireless WAN -# -CONFIG_WWAN=m -CONFIG_WWAN_DEBUGFS=y -CONFIG_WWAN_HWSIM=m -CONFIG_MHI_WWAN_CTRL=m -CONFIG_MHI_WWAN_MBIM=m -CONFIG_RPMSG_WWAN_CTRL=m -CONFIG_IOSM=m -CONFIG_MTK_T7XX=m -# end of Wireless WAN - -CONFIG_XEN_NETDEV_FRONTEND=m -CONFIG_XEN_NETDEV_BACKEND=m -CONFIG_VMXNET3=m -CONFIG_FUJITSU_ES=m -CONFIG_NETDEVSIM=m -CONFIG_NET_FAILOVER=y -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=m -CONFIG_INPUT_SPARSEKMAP=m -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_VIVALDIFMAP=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -# CONFIG_INPUT_KUNIT_TEST is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ADC=m -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -CONFIG_KEYBOARD_QT1050=m -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_GPIO_POLLED=m -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_PINEPHONE is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_CROS_EC=y -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_BCM is not set -# CONFIG_KEYBOARD_CYPRESS_SF is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -CONFIG_MOUSE_PS2_SMBUS=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADC=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=m -CONFIG_JOYSTICK_IFORCE_232=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_JOYSTICK_PSXPAD_SPI_FF=y -CONFIG_JOYSTICK_PXRC=m -CONFIG_JOYSTICK_QWIIC=m -CONFIG_JOYSTICK_FSIA6B=m -CONFIG_JOYSTICK_SENSEHAT=m -# CONFIG_JOYSTICK_SEESAW is not set -CONFIG_INPUT_TABLET=y -# CONFIG_TABLET_USB_ACECAD is not set -# CONFIG_TABLET_USB_AIPTEK is not set -# CONFIG_TABLET_USB_HANWANG is not set -# CONFIG_TABLET_USB_KBTAB is not set -# CONFIG_TABLET_USB_PEGASUS is not set -# CONFIG_TABLET_SERIAL_WACOM4 is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m -CONFIG_TOUCHSCREEN_AD7877=m -CONFIG_TOUCHSCREEN_AD7879=m -CONFIG_TOUCHSCREEN_AD7879_I2C=m -CONFIG_TOUCHSCREEN_AD7879_SPI=m -CONFIG_TOUCHSCREEN_ADC=m -CONFIG_TOUCHSCREEN_AR1021_I2C=m -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y -CONFIG_TOUCHSCREEN_AUO_PIXCIR=m -CONFIG_TOUCHSCREEN_BU21013=m -CONFIG_TOUCHSCREEN_BU21029=m -CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m -CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m -CONFIG_TOUCHSCREEN_CY8CTMA140=m -CONFIG_TOUCHSCREEN_CY8CTMG110=m -CONFIG_TOUCHSCREEN_CYTTSP_CORE=m -CONFIG_TOUCHSCREEN_CYTTSP_I2C=m -CONFIG_TOUCHSCREEN_CYTTSP_SPI=m -CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m -CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m -CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m -# CONFIG_TOUCHSCREEN_CYTTSP5 is not set -CONFIG_TOUCHSCREEN_DYNAPRO=m -CONFIG_TOUCHSCREEN_HAMPSHIRE=m -CONFIG_TOUCHSCREEN_EETI=m -CONFIG_TOUCHSCREEN_EGALAX=m -CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m -CONFIG_TOUCHSCREEN_EXC3000=m -CONFIG_TOUCHSCREEN_FUJITSU=m -CONFIG_TOUCHSCREEN_GOODIX=m -# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set -# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set -CONFIG_TOUCHSCREEN_HIDEEP=m -CONFIG_TOUCHSCREEN_HYCON_HY46XX=m -# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set -CONFIG_TOUCHSCREEN_ILI210X=m -CONFIG_TOUCHSCREEN_ILITEK=m -CONFIG_TOUCHSCREEN_S6SY761=m -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_TOUCHSCREEN_EKTF2127=m -CONFIG_TOUCHSCREEN_ELAN=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_WACOM_W8001=m -CONFIG_TOUCHSCREEN_WACOM_I2C=m -CONFIG_TOUCHSCREEN_MAX11801=m -CONFIG_TOUCHSCREEN_MCS5000=m -CONFIG_TOUCHSCREEN_MMS114=m -CONFIG_TOUCHSCREEN_MELFAS_MIP4=m -CONFIG_TOUCHSCREEN_MSG2638=m -CONFIG_TOUCHSCREEN_MTOUCH=m -# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set -CONFIG_TOUCHSCREEN_IMAGIS=m -CONFIG_TOUCHSCREEN_IMX6UL_TSC=m -CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -CONFIG_TOUCHSCREEN_PIXCIR=m -CONFIG_TOUCHSCREEN_WDT87XX_I2C=m -CONFIG_TOUCHSCREEN_WM97XX=m -CONFIG_TOUCHSCREEN_WM9705=y -CONFIG_TOUCHSCREEN_WM9712=y -CONFIG_TOUCHSCREEN_WM9713=y -CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -CONFIG_TOUCHSCREEN_USB_EGALAX=y -CONFIG_TOUCHSCREEN_USB_PANJIT=y -CONFIG_TOUCHSCREEN_USB_3M=y -CONFIG_TOUCHSCREEN_USB_ITM=y -CONFIG_TOUCHSCREEN_USB_ETURBO=y -CONFIG_TOUCHSCREEN_USB_GUNZE=y -CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y -CONFIG_TOUCHSCREEN_USB_IRTOUCH=y -CONFIG_TOUCHSCREEN_USB_IDEALTEK=y -CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y -CONFIG_TOUCHSCREEN_USB_GOTOP=y -CONFIG_TOUCHSCREEN_USB_JASTEC=y -CONFIG_TOUCHSCREEN_USB_ELO=y -CONFIG_TOUCHSCREEN_USB_E2I=y -CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y -CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y -CONFIG_TOUCHSCREEN_USB_NEXIO=y -CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y -CONFIG_TOUCHSCREEN_TOUCHIT213=m -CONFIG_TOUCHSCREEN_TSC_SERIO=m -CONFIG_TOUCHSCREEN_TSC200X_CORE=m -CONFIG_TOUCHSCREEN_TSC2004=m -CONFIG_TOUCHSCREEN_TSC2005=m -CONFIG_TOUCHSCREEN_TSC2007=m -CONFIG_TOUCHSCREEN_TSC2007_IIO=y -CONFIG_TOUCHSCREEN_RM_TS=m -CONFIG_TOUCHSCREEN_SILEAD=m -CONFIG_TOUCHSCREEN_SIS_I2C=m -CONFIG_TOUCHSCREEN_ST1232=m -CONFIG_TOUCHSCREEN_STMFTS=m -CONFIG_TOUCHSCREEN_SUR40=m -CONFIG_TOUCHSCREEN_SURFACE3_SPI=m -CONFIG_TOUCHSCREEN_SX8654=m -CONFIG_TOUCHSCREEN_TPS6507X=m -CONFIG_TOUCHSCREEN_ZET6223=m -CONFIG_TOUCHSCREEN_ZFORCE=m -CONFIG_TOUCHSCREEN_COLIBRI_VF50=m -CONFIG_TOUCHSCREEN_ROHM_BU21023=m -CONFIG_TOUCHSCREEN_IQS5XX=m -# CONFIG_TOUCHSCREEN_IQS7211 is not set -CONFIG_TOUCHSCREEN_ZINITIX=m -# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -# CONFIG_INPUT_BMA150 is not set -# CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_MMA8450 is not set -CONFIG_INPUT_GPIO_BEEPER=m -CONFIG_INPUT_GPIO_DECODER=m -CONFIG_INPUT_GPIO_VIBRA=m -CONFIG_INPUT_ATI_REMOTE2=m -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_KXTJ9 is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -# CONFIG_INPUT_REGULATOR_HAPTIC is not set -CONFIG_INPUT_UINPUT=m -# CONFIG_INPUT_PCF8574 is not set -# CONFIG_INPUT_PWM_BEEPER is not set -# CONFIG_INPUT_PWM_VIBRA is not set -CONFIG_INPUT_RK805_PWRKEY=m -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -CONFIG_INPUT_DA7280_HAPTICS=m -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_IBM_PANEL is not set -# CONFIG_INPUT_IMS_PCU is not set -# CONFIG_INPUT_IQS269A is not set -CONFIG_INPUT_IQS626A=m -CONFIG_INPUT_IQS7222=m -# CONFIG_INPUT_CMA3000 is not set -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INPUT_SOC_BUTTON_ARRAY=m -# CONFIG_INPUT_DRV260X_HAPTICS is not set -# CONFIG_INPUT_DRV2665_HAPTICS is not set -# CONFIG_INPUT_DRV2667_HAPTICS is not set -CONFIG_RMI4_CORE=m -CONFIG_RMI4_I2C=m -CONFIG_RMI4_SPI=m -CONFIG_RMI4_SMB=m -CONFIG_RMI4_F03=y -CONFIG_RMI4_F03_SERIO=m -CONFIG_RMI4_2D_SENSOR=y -CONFIG_RMI4_F11=y -CONFIG_RMI4_F12=y -CONFIG_RMI4_F30=y -CONFIG_RMI4_F34=y -CONFIG_RMI4_F3A=y -CONFIG_RMI4_F54=y -CONFIG_RMI4_F55=y - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_AMBAKMI=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m -CONFIG_SERIO_ALTERA_PS2=m -# CONFIG_SERIO_PS2MULT is not set -CONFIG_SERIO_ARC_PS2=m -# CONFIG_SERIO_APBPS2 is not set -# CONFIG_SERIO_GPIO_PS2 is not set -# CONFIG_USERIO is not set -CONFIG_GAMEPORT=m -# CONFIG_GAMEPORT_EMU10K1 is not set -# CONFIG_GAMEPORT_FM801 is not set -# end of Hardware I/O ports -# end of Input device support - -# -# Character devices -# -CONFIG_TTY=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_LEGACY_TIOCSTI=y -CONFIG_LDISC_AUTOLOAD=y - -# -# Serial drivers -# -CONFIG_SERIAL_EARLYCON=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIAL_8250_16550A_VARIANTS=y -CONFIG_SERIAL_8250_FINTEK=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCILIB=y -CONFIG_SERIAL_8250_PCI=m -CONFIG_SERIAL_8250_EXAR=m -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_RUNTIME_UARTS=8 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_PCI1XXXX is not set -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_DW=y -# CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_PERICOM=y -CONFIG_SERIAL_OF_PLATFORM=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_AMBA_PL010=y -CONFIG_SERIAL_AMBA_PL010_CONSOLE=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_MAX310X is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_JSM=m -CONFIG_SERIAL_SIFIVE=m -CONFIG_SERIAL_SCCNXP=y -CONFIG_SERIAL_SCCNXP_CONSOLE=y -# CONFIG_SERIAL_SC16IS7XX is not set -CONFIG_SERIAL_ALTERA_JTAGUART=m -CONFIG_SERIAL_ALTERA_UART=m -CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 -CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_ARC=m -CONFIG_SERIAL_ARC_NR_PORTS=1 -CONFIG_SERIAL_RP2=m -CONFIG_SERIAL_RP2_NR_UARTS=32 -CONFIG_SERIAL_FSL_LPUART=m -CONFIG_SERIAL_FSL_LINFLEXUART=m -CONFIG_SERIAL_CONEXANT_DIGICOLOR=m -CONFIG_SERIAL_SPRD=m -CONFIG_SERIAL_LITEUART=m -CONFIG_SERIAL_LITEUART_MAX_PORTS=1 -# end of Serial drivers - -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_MOXA_INTELLIO=m -CONFIG_MOXA_SMARTIO=m -CONFIG_N_HDLC=m -CONFIG_N_GSM=m -CONFIG_NOZOMI=m -CONFIG_NULL_TTY=m -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -# CONFIG_HVC_DCC is not set -CONFIG_RPMSG_TTY=m -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -# CONFIG_TTY_PRINTK is not set -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DMI_DECODE=y -CONFIG_IPMI_PLAT_DATA=y -# CONFIG_IPMI_PANIC_EVENT is not set -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -# CONFIG_IPMI_SSIF is not set -CONFIG_IPMI_IPMB=m -# CONFIG_IPMI_WATCHDOG is not set -# CONFIG_IPMI_POWEROFF is not set -# CONFIG_SSIF_IPMI_BMC is not set -# CONFIG_IPMB_DEVICE_INTERFACE is not set -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=m -# CONFIG_HW_RANDOM_BA431 is not set -CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_OPTEE=m -# CONFIG_HW_RANDOM_CCTRNG is not set -# CONFIG_HW_RANDOM_XIPHERA is not set -CONFIG_HW_RANDOM_ROCKCHIP=m -CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m -CONFIG_HW_RANDOM_CN10K=y -# CONFIG_APPLICOM is not set -CONFIG_DEVMEM=y -CONFIG_DEVPORT=y -CONFIG_TCG_TPM=y -# CONFIG_TCG_TPM2_HMAC is not set -CONFIG_HW_RANDOM_TPM=y -# CONFIG_TCG_TIS is not set -# CONFIG_TCG_TIS_SPI is not set -# CONFIG_TCG_TIS_I2C is not set -CONFIG_TCG_TIS_I2C_CR50=m -# CONFIG_TCG_TIS_I2C_ATMEL is not set -CONFIG_TCG_TIS_I2C_INFINEON=y -# CONFIG_TCG_TIS_I2C_NUVOTON is not set -# CONFIG_TCG_ATMEL is not set -# CONFIG_TCG_INFINEON is not set -# CONFIG_TCG_XEN is not set -CONFIG_TCG_CRB=y -# CONFIG_TCG_VTPM_PROXY is not set -# CONFIG_TCG_FTPM_TEE is not set -# CONFIG_TCG_TIS_ST33ZP24_I2C is not set -# CONFIG_TCG_TIS_ST33ZP24_SPI is not set -CONFIG_XILLYBUS_CLASS=m -# CONFIG_XILLYBUS is not set -CONFIG_XILLYUSB=m -# end of Character devices - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y - -# -# Multiplexer I2C Chip support -# -CONFIG_I2C_ARB_GPIO_CHALLENGE=m -CONFIG_I2C_MUX_GPIO=m -CONFIG_I2C_MUX_GPMUX=m -CONFIG_I2C_MUX_LTC4306=m -CONFIG_I2C_MUX_PCA9541=m -CONFIG_I2C_MUX_PCA954x=m -CONFIG_I2C_MUX_PINCTRL=m -CONFIG_I2C_MUX_REG=m -CONFIG_I2C_DEMUX_PINCTRL=m -CONFIG_I2C_MUX_MLXCPLD=m -# end of Multiplexer I2C Chip support - -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_SMBUS=m -CONFIG_I2C_ALGOBIT=m -CONFIG_I2C_ALGOPCA=m - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -CONFIG_I2C_CCGX_UCSI=m -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_AMD_MP2 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_ZHAOXIN is not set - -# -# ACPI drivers -# -CONFIG_I2C_SCMI=m - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -CONFIG_I2C_CADENCE=m -CONFIG_I2C_CBUS_GPIO=m -CONFIG_I2C_DESIGNWARE_CORE=y -# CONFIG_I2C_DESIGNWARE_SLAVE is not set -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_I2C_EMEV2=m -CONFIG_I2C_GPIO=m -CONFIG_I2C_GPIO_FAULT_INJECTOR=y -CONFIG_I2C_HISI=m -# CONFIG_I2C_NOMADIK is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_PCA_PLATFORM=m -CONFIG_I2C_RK3X=y -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_THUNDERX is not set -CONFIG_I2C_XILINX=m - -# -# External I2C/SMBus adapter drivers -# -CONFIG_I2C_DIOLAN_U2C=m -CONFIG_I2C_CP2615=m -CONFIG_I2C_PCI1XXXX=m -CONFIG_I2C_ROBOTFUZZ_OSIF=m -CONFIG_I2C_TAOS_EVM=m -CONFIG_I2C_TINY_USB=m - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_MLXCPLD is not set -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_I2C_VIRTIO=m -# end of I2C Hardware Bus support - -CONFIG_I2C_STUB=m -CONFIG_I2C_SLAVE=y -CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_I2C_SLAVE_TESTUNIT=m -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# end of I2C support - -CONFIG_I3C=m -CONFIG_CDNS_I3C_MASTER=m -CONFIG_DW_I3C_MASTER=m -CONFIG_SVC_I3C_MASTER=m -CONFIG_MIPI_I3C_HCI=m -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_ALTERA=m -CONFIG_SPI_ALTERA_CORE=m -CONFIG_SPI_AXI_SPI_ENGINE=m -CONFIG_SPI_BITBANG=m -CONFIG_SPI_CADENCE=m -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_SPI_CADENCE_XSPI=m -CONFIG_SPI_DESIGNWARE=m -# CONFIG_SPI_DW_DMA is not set -CONFIG_SPI_DW_PCI=m -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_HISI_KUNPENG=m -CONFIG_SPI_HISI_SFC_V3XX=m -CONFIG_SPI_GPIO=m -CONFIG_SPI_FSL_LIB=m -CONFIG_SPI_FSL_SPI=m -CONFIG_SPI_MICROCHIP_CORE=m -CONFIG_SPI_MICROCHIP_CORE_QSPI=m -CONFIG_SPI_OC_TINY=m -# CONFIG_SPI_PCI1XXXX is not set -CONFIG_SPI_PL022=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_ROCKCHIP_SFC=y -# CONFIG_SPI_SC18IS602 is not set -# CONFIG_SPI_SIFIVE is not set -# CONFIG_SPI_SN_F_OSPI is not set -CONFIG_SPI_MXIC=m -# CONFIG_SPI_THUNDERX is not set -# CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_XILINX is not set -# CONFIG_SPI_ZYNQMP_GQSPI is not set -# CONFIG_SPI_AMD is not set - -# -# SPI Multiplexer support -# -CONFIG_SPI_MUX=m - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=m -CONFIG_SPI_LOOPBACK_TEST=m -CONFIG_SPI_TLE62X0=m -CONFIG_SPI_SLAVE=y -CONFIG_SPI_SLAVE_TIME=m -CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m -CONFIG_SPI_DYNAMIC=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_HSI is not set -CONFIG_PPS=y -# CONFIG_PPS_DEBUG is not set - -# -# PPS clients support -# -# CONFIG_PPS_CLIENT_KTIMER is not set -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_GPIO=m - -# -# PPS generators support -# - -# -# PTP clock support -# -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_DP83640_PHY=m -CONFIG_PTP_1588_CLOCK_INES=m -CONFIG_PTP_1588_CLOCK_KVM=m -CONFIG_PTP_1588_CLOCK_IDT82P33=m -CONFIG_PTP_1588_CLOCK_IDTCM=m -# CONFIG_PTP_1588_CLOCK_FC3W is not set -# CONFIG_PTP_1588_CLOCK_MOCK is not set -CONFIG_PTP_1588_CLOCK_OCP=m -# end of PTP clock support - -CONFIG_PINCTRL=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_PINMUX=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_PINCONF=y -CONFIG_GENERIC_PINCONF=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_CY8C95X0=m -# CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set -# CONFIG_PINCTRL_OCELOT is not set -CONFIG_PINCTRL_RK805=m -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SCMI is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_STMFX=m -CONFIG_PINCTRL_SX150X=y - -# -# Renesas pinctrl drivers -# -# end of Renesas pinctrl drivers - -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_FASTPATH_LIMIT=512 -CONFIG_OF_GPIO=y -CONFIG_GPIO_ACPI=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_OF_GPIO_MM_GPIOCHIP=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_CDEV_V1=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_REGMAP=m -CONFIG_GPIO_MAX730X=m -CONFIG_GPIO_IDIO_16=m - -# -# Memory mapped GPIO drivers -# -CONFIG_GPIO_74XX_MMIO=m -CONFIG_GPIO_ALTERA=m -# CONFIG_GPIO_AMDPT is not set -CONFIG_GPIO_CADENCE=m -CONFIG_GPIO_DWAPB=m -CONFIG_GPIO_EXAR=m -# CONFIG_GPIO_FTGPIO010 is not set -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_GRGPIO=m -CONFIG_GPIO_HISI=m -CONFIG_GPIO_HLWD=m -CONFIG_GPIO_LOGICVC=m -CONFIG_GPIO_MB86S7X=m -CONFIG_GPIO_PL061=y -CONFIG_GPIO_ROCKCHIP=y -# CONFIG_GPIO_SIFIVE is not set -CONFIG_GPIO_SYSCON=y -CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XILINX=y -CONFIG_GPIO_AMD_FCH=m -# end of Memory mapped GPIO drivers - -# -# I2C GPIO expanders -# -CONFIG_GPIO_ADNP=m -# CONFIG_GPIO_FXL6408 is not set -# CONFIG_GPIO_DS4520 is not set -CONFIG_GPIO_GW_PLD=m -CONFIG_GPIO_MAX7300=m -CONFIG_GPIO_MAX732X=m -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_PCA9570=m -CONFIG_GPIO_PCF857X=m -CONFIG_GPIO_TPIC2810=m -# end of I2C GPIO expanders - -# -# MFD GPIO expanders -# -# CONFIG_GPIO_CROS_EC is not set -# end of MFD GPIO expanders - -# -# PCI GPIO expanders -# -CONFIG_GPIO_PCI_IDIO_16=m -CONFIG_GPIO_PCIE_IDIO_24=m -CONFIG_GPIO_RDC321X=m -# end of PCI GPIO expanders - -# -# SPI GPIO expanders -# -CONFIG_GPIO_74X164=m -CONFIG_GPIO_MAX3191X=m -CONFIG_GPIO_MAX7301=m -CONFIG_GPIO_MC33880=m -CONFIG_GPIO_PISOSR=m -CONFIG_GPIO_XRA1403=m -# end of SPI GPIO expanders - -# -# USB GPIO expanders -# -# end of USB GPIO expanders - -# -# Virtual GPIO drivers -# -CONFIG_GPIO_AGGREGATOR=m -# CONFIG_GPIO_LATCH is not set -CONFIG_GPIO_MOCKUP=m -CONFIG_GPIO_VIRTIO=m -# CONFIG_GPIO_SIM is not set -# end of Virtual GPIO drivers - -CONFIG_W1=m -CONFIG_W1_CON=y - -# -# 1-wire Bus Masters -# -# CONFIG_W1_MASTER_AMD_AXI is not set -CONFIG_W1_MASTER_MATROX=m -CONFIG_W1_MASTER_DS2490=m -CONFIG_W1_MASTER_DS2482=m -CONFIG_W1_MASTER_GPIO=m -CONFIG_W1_MASTER_SGI=m -# CONFIG_W1_MASTER_UART is not set -# end of 1-wire Bus Masters - -# -# 1-wire Slaves -# -CONFIG_W1_SLAVE_THERM=m -CONFIG_W1_SLAVE_SMEM=m -CONFIG_W1_SLAVE_DS2405=m -CONFIG_W1_SLAVE_DS2408=m -CONFIG_W1_SLAVE_DS2408_READBACK=y -CONFIG_W1_SLAVE_DS2413=m -CONFIG_W1_SLAVE_DS2406=m -CONFIG_W1_SLAVE_DS2423=m -CONFIG_W1_SLAVE_DS2805=m -CONFIG_W1_SLAVE_DS2430=m -CONFIG_W1_SLAVE_DS2431=m -CONFIG_W1_SLAVE_DS2433=m -# CONFIG_W1_SLAVE_DS2433_CRC is not set -CONFIG_W1_SLAVE_DS2438=m -CONFIG_W1_SLAVE_DS250X=m -CONFIG_W1_SLAVE_DS2780=m -CONFIG_W1_SLAVE_DS2781=m -CONFIG_W1_SLAVE_DS28E04=m -CONFIG_W1_SLAVE_DS28E17=m -# end of 1-wire Slaves - -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -# CONFIG_POWER_RESET_LTC2952 is not set -CONFIG_POWER_RESET_REGULATOR=y -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_REBOOT_MODE=y -CONFIG_SYSCON_REBOOT_MODE=y -# CONFIG_NVMEM_REBOOT_MODE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_GENERIC_ADC_BATTERY=m -# CONFIG_IP5XXX_POWER is not set -# CONFIG_TEST_POWER is not set -CONFIG_CHARGER_ADP5061=m -CONFIG_BATTERY_CW2015=m -CONFIG_BATTERY_DS2760=m -CONFIG_BATTERY_DS2780=m -CONFIG_BATTERY_DS2781=m -CONFIG_BATTERY_DS2782=m -# CONFIG_BATTERY_SAMSUNG_SDI is not set -CONFIG_BATTERY_SBS=m -CONFIG_CHARGER_SBS=m -CONFIG_MANAGER_SBS=m -CONFIG_BATTERY_BQ27XXX=m -CONFIG_BATTERY_BQ27XXX_I2C=m -CONFIG_BATTERY_BQ27XXX_HDQ=m -# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set -CONFIG_BATTERY_MAX17040=m -CONFIG_BATTERY_MAX17042=m -CONFIG_BATTERY_MAX1721X=m -CONFIG_CHARGER_ISP1704=m -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -CONFIG_CHARGER_GPIO=m -# CONFIG_CHARGER_MANAGER is not set -CONFIG_CHARGER_LT3651=m -CONFIG_CHARGER_LTC4162L=m -CONFIG_CHARGER_DETECTOR_MAX14656=m -# CONFIG_CHARGER_MAX77976 is not set -# CONFIG_CHARGER_MT6370 is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_BQ24190 is not set -# CONFIG_CHARGER_BQ24257 is not set -# CONFIG_CHARGER_BQ24735 is not set -# CONFIG_CHARGER_BQ2515X is not set -# CONFIG_CHARGER_BQ25890 is not set -# CONFIG_CHARGER_BQ25980 is not set -CONFIG_CHARGER_BQ256XX=m -# CONFIG_CHARGER_RK817 is not set -CONFIG_CHARGER_SMB347=m -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -CONFIG_BATTERY_GOLDFISH=m -CONFIG_BATTERY_RT5033=m -# CONFIG_CHARGER_RT9455 is not set -# CONFIG_CHARGER_RT9467 is not set -# CONFIG_CHARGER_RT9471 is not set -# CONFIG_CHARGER_CROS_USBPD is not set -CONFIG_CHARGER_CROS_PCHG=m -CONFIG_CHARGER_UCS1002=m -# CONFIG_CHARGER_BD99954 is not set -# CONFIG_BATTERY_UG3105 is not set -# CONFIG_FUEL_GAUGE_MM8013 is not set -CONFIG_HWMON=y -CONFIG_HWMON_VID=m -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -CONFIG_SENSORS_AD7314=m -CONFIG_SENSORS_AD7414=m -CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM1177=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ADT7X10=m -CONFIG_SENSORS_ADT7310=m -CONFIG_SENSORS_ADT7410=m -CONFIG_SENSORS_ADT7411=m -CONFIG_SENSORS_ADT7462=m -CONFIG_SENSORS_ADT7470=m -CONFIG_SENSORS_ADT7475=m -CONFIG_SENSORS_AHT10=m -CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m -CONFIG_SENSORS_AS370=m -CONFIG_SENSORS_ASC7621=m -# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set -CONFIG_SENSORS_AXI_FAN_CONTROL=m -CONFIG_SENSORS_ARM_SCMI=m -CONFIG_SENSORS_ARM_SCPI=m -CONFIG_SENSORS_ATXP1=m -# CONFIG_SENSORS_CHIPCAP2 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -CONFIG_SENSORS_CORSAIR_PSU=m -CONFIG_SENSORS_DRIVETEMP=m -CONFIG_SENSORS_DS620=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_I5K_AMB=m -CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_F71882FG=m -CONFIG_SENSORS_F75375S=m -CONFIG_SENSORS_FTSTEUTATES=m -# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_G760A=m -CONFIG_SENSORS_G762=m -CONFIG_SENSORS_GPIO_FAN=m -CONFIG_SENSORS_HIH6130=m -# CONFIG_SENSORS_HS3001 is not set -CONFIG_SENSORS_IBMAEM=m -CONFIG_SENSORS_IBMPEX=m -CONFIG_SENSORS_IIO_HWMON=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_JC42=m -# CONFIG_SENSORS_POWERZ is not set -CONFIG_SENSORS_POWR1220=m -CONFIG_SENSORS_LINEAGE=m -CONFIG_SENSORS_LTC2945=m -CONFIG_SENSORS_LTC2947=m -CONFIG_SENSORS_LTC2947_I2C=m -CONFIG_SENSORS_LTC2947_SPI=m -CONFIG_SENSORS_LTC2990=m -# CONFIG_SENSORS_LTC2991 is not set -CONFIG_SENSORS_LTC2992=m -CONFIG_SENSORS_LTC4151=m -CONFIG_SENSORS_LTC4215=m -CONFIG_SENSORS_LTC4222=m -CONFIG_SENSORS_LTC4245=m -CONFIG_SENSORS_LTC4260=m -CONFIG_SENSORS_LTC4261=m -# CONFIG_SENSORS_LTC4282 is not set -CONFIG_SENSORS_MAX1111=m -CONFIG_SENSORS_MAX127=m -CONFIG_SENSORS_MAX16065=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_MAX1668=m -CONFIG_SENSORS_MAX197=m -CONFIG_SENSORS_MAX31722=m -CONFIG_SENSORS_MAX31730=m -CONFIG_SENSORS_MAX31760=m -# CONFIG_MAX31827 is not set -CONFIG_SENSORS_MAX6620=m -CONFIG_SENSORS_MAX6621=m -CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6650=m -CONFIG_SENSORS_MAX6697=m -CONFIG_SENSORS_MAX31790=m -# CONFIG_SENSORS_MC34VR500 is not set -CONFIG_SENSORS_MCP3021=m -CONFIG_SENSORS_TC654=m -CONFIG_SENSORS_TPS23861=m -# CONFIG_SENSORS_MR75203 is not set -CONFIG_SENSORS_ADCXX=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_LM93=m -CONFIG_SENSORS_LM95234=m -CONFIG_SENSORS_LM95241=m -CONFIG_SENSORS_LM95245=m -CONFIG_SENSORS_PC87360=m -CONFIG_SENSORS_PC87427=m -CONFIG_SENSORS_NTC_THERMISTOR=m -CONFIG_SENSORS_NCT6683=m -CONFIG_SENSORS_NCT6775_CORE=m -CONFIG_SENSORS_NCT6775=m -CONFIG_SENSORS_NCT6775_I2C=m -CONFIG_SENSORS_NCT7802=m -CONFIG_SENSORS_NCT7904=m -CONFIG_SENSORS_NPCM7XX=m -CONFIG_SENSORS_NZXT_KRAKEN2=m -# CONFIG_SENSORS_NZXT_KRAKEN3 is not set -# CONFIG_SENSORS_NZXT_SMART2 is not set -CONFIG_SENSORS_OCC_P8_I2C=m -CONFIG_SENSORS_OCC=m -CONFIG_SENSORS_PCF8591=m -CONFIG_PMBUS=m -CONFIG_SENSORS_PMBUS=m -# CONFIG_SENSORS_ACBEL_FSG032 is not set -# CONFIG_SENSORS_ADM1266 is not set -CONFIG_SENSORS_ADM1275=m -# CONFIG_SENSORS_ADP1050 is not set -CONFIG_SENSORS_BEL_PFE=m -CONFIG_SENSORS_BPA_RS600=m -# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set -CONFIG_SENSORS_FSP_3Y=m -CONFIG_SENSORS_IBM_CFFPS=m -CONFIG_SENSORS_DPS920AB=m -CONFIG_SENSORS_INSPUR_IPSPS=m -CONFIG_SENSORS_IR35221=m -CONFIG_SENSORS_IR36021=m -CONFIG_SENSORS_IR38064=m -# CONFIG_SENSORS_IR38064_REGULATOR is not set -CONFIG_SENSORS_IRPS5401=m -CONFIG_SENSORS_ISL68137=m -CONFIG_SENSORS_LM25066=m -# CONFIG_SENSORS_LM25066_REGULATOR is not set -CONFIG_SENSORS_LT7182S=m -CONFIG_SENSORS_LTC2978=m -CONFIG_SENSORS_LTC2978_REGULATOR=y -CONFIG_SENSORS_LTC3815=m -# CONFIG_SENSORS_LTC4286 is not set -CONFIG_SENSORS_MAX15301=m -CONFIG_SENSORS_MAX16064=m -CONFIG_SENSORS_MAX16601=m -CONFIG_SENSORS_MAX20730=m -CONFIG_SENSORS_MAX20751=m -CONFIG_SENSORS_MAX31785=m -CONFIG_SENSORS_MAX34440=m -CONFIG_SENSORS_MAX8688=m -# CONFIG_SENSORS_MP2856 is not set -CONFIG_SENSORS_MP2888=m -# CONFIG_SENSORS_MP2975 is not set -# CONFIG_SENSORS_MP5023 is not set -# CONFIG_SENSORS_MP5990 is not set -# CONFIG_SENSORS_MPQ7932 is not set -# CONFIG_SENSORS_MPQ8785 is not set -CONFIG_SENSORS_PIM4328=m -# CONFIG_SENSORS_PLI1209BC is not set -CONFIG_SENSORS_PM6764TR=m -CONFIG_SENSORS_PXE1610=m -CONFIG_SENSORS_Q54SJ108A2=m -CONFIG_SENSORS_STPDDC60=m -# CONFIG_SENSORS_TDA38640 is not set -CONFIG_SENSORS_TPS40422=m -CONFIG_SENSORS_TPS53679=m -CONFIG_SENSORS_TPS546D24=m -CONFIG_SENSORS_UCD9000=m -CONFIG_SENSORS_UCD9200=m -# CONFIG_SENSORS_XDP710 is not set -CONFIG_SENSORS_XDPE152=m -CONFIG_SENSORS_XDPE122=m -# CONFIG_SENSORS_XDPE122_REGULATOR is not set -CONFIG_SENSORS_ZL6100=m -# CONFIG_SENSORS_PT5161L is not set -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_SBTSI=m -CONFIG_SENSORS_SBRMI=m -CONFIG_SENSORS_SHT15=m -CONFIG_SENSORS_SHT21=m -CONFIG_SENSORS_SHT3x=m -CONFIG_SENSORS_SHT4x=m -CONFIG_SENSORS_SHTC1=m -CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_DME1737=m -CONFIG_SENSORS_EMC1403=m -CONFIG_SENSORS_EMC2103=m -CONFIG_SENSORS_EMC2305=m -CONFIG_SENSORS_EMC6W201=m -CONFIG_SENSORS_SMSC47M1=m -CONFIG_SENSORS_SMSC47M192=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_SCH56XX_COMMON=m -CONFIG_SENSORS_SCH5627=m -CONFIG_SENSORS_SCH5636=m -CONFIG_SENSORS_STTS751=m -CONFIG_SENSORS_ADC128D818=m -CONFIG_SENSORS_ADS7828=m -CONFIG_SENSORS_ADS7871=m -CONFIG_SENSORS_AMC6821=m -CONFIG_SENSORS_INA209=m -CONFIG_SENSORS_INA2XX=m -# CONFIG_SENSORS_INA238 is not set -CONFIG_SENSORS_INA3221=m -CONFIG_SENSORS_TC74=m -CONFIG_SENSORS_THMC50=m -CONFIG_SENSORS_TMP102=m -CONFIG_SENSORS_TMP103=m -CONFIG_SENSORS_TMP108=m -CONFIG_SENSORS_TMP401=m -CONFIG_SENSORS_TMP421=m -# CONFIG_SENSORS_TMP464 is not set -CONFIG_SENSORS_TMP513=m -CONFIG_SENSORS_VEXPRESS=m -CONFIG_SENSORS_VIA686A=m -CONFIG_SENSORS_VT1211=m -CONFIG_SENSORS_VT8231=m -CONFIG_SENSORS_W83773G=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83795=m -# CONFIG_SENSORS_W83795_FANCTRL is not set -CONFIG_SENSORS_W83L785TS=m -CONFIG_SENSORS_W83L786NG=m -CONFIG_SENSORS_W83627HF=m -CONFIG_SENSORS_W83627EHF=m -CONFIG_SENSORS_XGENE=m - -# -# ACPI drivers -# -CONFIG_SENSORS_ACPI_POWER=m -CONFIG_THERMAL=y -# CONFIG_THERMAL_NETLINK is not set -CONFIG_THERMAL_STATISTICS=y -# CONFIG_THERMAL_DEBUGFS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_FREQ_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_MMIO=m -CONFIG_ROCKCHIP_THERMAL=y -# CONFIG_GENERIC_ADC_THERMAL is not set -CONFIG_KHADAS_MCU_FAN_THERMAL=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -CONFIG_WATCHDOG_SYSFS=y -# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set - -# -# Watchdog Pretimeout Governors -# -# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set - -# -# Watchdog Device Drivers -# -CONFIG_SOFT_WATCHDOG=m -# CONFIG_CROS_EC_WATCHDOG is not set -CONFIG_GPIO_WATCHDOG=m -CONFIG_WDAT_WDT=m -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_XILINX_WINDOW_WATCHDOG is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -# CONFIG_CADENCE_WATCHDOG is not set -CONFIG_DW_WATCHDOG=y -# CONFIG_MAX63XX_WATCHDOG is not set -CONFIG_ARM_SMC_WATCHDOG=y -# CONFIG_ALIM7101_WDT is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_HP_WATCHDOG is not set -# CONFIG_MEN_A21_WDT is not set -# CONFIG_XEN_WDT is not set - -# -# PCI-based Watchdog Cards -# -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m - -# -# USB-based Watchdog Cards -# -CONFIG_USBPCWATCHDOG=m -CONFIG_SSB_POSSIBLE=y -CONFIG_SSB=m -CONFIG_SSB_SPROM=y -CONFIG_SSB_BLOCKIO=y -CONFIG_SSB_PCIHOST_POSSIBLE=y -CONFIG_SSB_PCIHOST=y -CONFIG_SSB_B43_PCI_BRIDGE=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -CONFIG_SSB_SDIOHOST=y -CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y -CONFIG_SSB_DRIVER_PCICORE=y -CONFIG_SSB_DRIVER_GPIO=y -CONFIG_BCMA_POSSIBLE=y -CONFIG_BCMA=m -CONFIG_BCMA_BLOCKIO=y -CONFIG_BCMA_HOST_PCI_POSSIBLE=y -CONFIG_BCMA_HOST_PCI=y -CONFIG_BCMA_HOST_SOC=y -CONFIG_BCMA_DRIVER_PCI=y -CONFIG_BCMA_SFLASH=y -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_BCMA_DEBUG=y - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_AS3711 is not set -# CONFIG_MFD_SMPRO is not set -# CONFIG_MFD_AS3722 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_AAT2870_CORE is not set -# CONFIG_MFD_ATMEL_FLEXCOM is not set -# CONFIG_MFD_ATMEL_HLCDC is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set -CONFIG_MFD_CROS_EC_DEV=y -# CONFIG_MFD_CS42L43_I2C is not set -# CONFIG_MFD_CS42L43_SDW is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_MFD_MAX5970 is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_SPI is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_GATEWORKS_GSC is not set -# CONFIG_MFD_MC13XXX_SPI is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_MFD_HI6421_PMIC is not set -# CONFIG_MFD_HI6421_SPMI is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77541 is not set -# CONFIG_MFD_MAX77620 is not set -# CONFIG_MFD_MAX77650 is not set -# CONFIG_MFD_MAX77686 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77714 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set -CONFIG_MFD_MT6370=m -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -CONFIG_MFD_OCELOT=m -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_CPCAP is not set -# CONFIG_MFD_VIPERBOARD is not set -CONFIG_MFD_NTXEC=m -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_SY7636A is not set -CONFIG_MFD_RDC321X=m -# CONFIG_MFD_RT4831 is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RT5120 is not set -# CONFIG_MFD_RC5T583 is not set -CONFIG_MFD_RK8XX=m -CONFIG_MFD_RK8XX_I2C=m -CONFIG_MFD_RK8XX_SPI=m -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -CONFIG_MFD_SIMPLE_MFD_I2C=m -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_STMPE is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS65010 is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TI_LP87565 is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MFD_TPS65219 is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65910 is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS65912_SPI is not set -# CONFIG_MFD_TPS6594_I2C is not set -# CONFIG_MFD_TPS6594_SPI is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -CONFIG_MFD_WL1273_CORE=m -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_LOCHNAGAR is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM831X_SPI is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD71828 is not set -# CONFIG_MFD_ROHM_BD957XMUF is not set -# CONFIG_MFD_STPMIC1 is not set -CONFIG_MFD_STMFX=m -# CONFIG_MFD_WCD934X is not set -# CONFIG_MFD_ATC260X_I2C is not set -CONFIG_MFD_KHADAS_MCU=m -# CONFIG_MFD_QCOM_PM8008 is not set -CONFIG_MFD_VEXPRESS_SYSREG=y -# CONFIG_RAVE_SP_CORE is not set -# CONFIG_MFD_INTEL_M10_BMC_SPI is not set -CONFIG_MFD_RSMU_I2C=m -CONFIG_MFD_RSMU_SPI=m -# end of Multifunction device drivers - -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_88PG86X is not set -CONFIG_REGULATOR_ACT8865=y -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ARM_SCMI is not set -# CONFIG_REGULATOR_AW37503 is not set -# CONFIG_REGULATOR_CROS_EC is not set -# CONFIG_REGULATOR_DA9121 is not set -# CONFIG_REGULATOR_DA9210 is not set -# CONFIG_REGULATOR_DA9211 is not set -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FAN53880=m -CONFIG_REGULATOR_GPIO=y -# CONFIG_REGULATOR_ISL9305 is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_LP3972 is not set -# CONFIG_REGULATOR_LP872X is not set -# CONFIG_REGULATOR_LP8755 is not set -# CONFIG_REGULATOR_LTC3589 is not set -# CONFIG_REGULATOR_LTC3676 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX77503 is not set -# CONFIG_REGULATOR_MAX77857 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -CONFIG_REGULATOR_MAX8893=m -# CONFIG_REGULATOR_MAX8952 is not set -CONFIG_REGULATOR_MAX8973=y -# CONFIG_REGULATOR_MAX20086 is not set -# CONFIG_REGULATOR_MAX20411 is not set -# CONFIG_REGULATOR_MAX77826 is not set -CONFIG_REGULATOR_MCP16502=m -CONFIG_REGULATOR_MP5416=m -CONFIG_REGULATOR_MP8859=m -CONFIG_REGULATOR_MP886X=m -CONFIG_REGULATOR_MPQ7920=m -# CONFIG_REGULATOR_MT6311 is not set -CONFIG_REGULATOR_MT6315=m -CONFIG_REGULATOR_MT6370=m -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PF8X00=m -CONFIG_REGULATOR_PFUZE100=m -# CONFIG_REGULATOR_PV88060 is not set -# CONFIG_REGULATOR_PV88080 is not set -# CONFIG_REGULATOR_PV88090 is not set -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_SPMI=y -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -# CONFIG_REGULATOR_RAA215300 is not set -# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set -CONFIG_REGULATOR_RK808=m -# CONFIG_REGULATOR_RT4801 is not set -# CONFIG_REGULATOR_RT4803 is not set -# CONFIG_REGULATOR_RT5190A is not set -# CONFIG_REGULATOR_RT5739 is not set -CONFIG_REGULATOR_RT5759=m -CONFIG_REGULATOR_RT6160=m -# CONFIG_REGULATOR_RT6190 is not set -CONFIG_REGULATOR_RT6245=m -CONFIG_REGULATOR_RTQ2134=m -# CONFIG_REGULATOR_RTMV20 is not set -CONFIG_REGULATOR_RTQ6752=m -# CONFIG_REGULATOR_RTQ2208 is not set -CONFIG_REGULATOR_SLG51000=m -# CONFIG_REGULATOR_SY8106A is not set -CONFIG_REGULATOR_SY8824X=m -# CONFIG_REGULATOR_SY8827N is not set -# CONFIG_REGULATOR_TPS51632 is not set -# CONFIG_REGULATOR_TPS62360 is not set -# CONFIG_REGULATOR_TPS6286X is not set -# CONFIG_REGULATOR_TPS6287X is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_REGULATOR_TPS65132 is not set -# CONFIG_REGULATOR_TPS6524X is not set -CONFIG_REGULATOR_VCTRL=m -CONFIG_REGULATOR_VEXPRESS=m -# CONFIG_REGULATOR_QCOM_LABIBB is not set -CONFIG_RC_CORE=m -CONFIG_LIRC=y -CONFIG_RC_MAP=m -CONFIG_RC_DECODERS=y -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m -CONFIG_IR_NEC_DECODER=m -CONFIG_IR_RC5_DECODER=m -CONFIG_IR_RC6_DECODER=m -CONFIG_IR_RCMM_DECODER=m -CONFIG_IR_SANYO_DECODER=m -CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_SONY_DECODER=m -CONFIG_IR_XMP_DECODER=m -CONFIG_RC_DEVICES=y -CONFIG_IR_ENE=m -CONFIG_IR_FINTEK=m -CONFIG_IR_GPIO_CIR=m -CONFIG_IR_GPIO_TX=m -CONFIG_IR_HIX5HD2=m -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_IMON=m -CONFIG_IR_IMON_RAW=m -CONFIG_IR_ITE_CIR=m -CONFIG_IR_MCEUSB=m -CONFIG_IR_NUVOTON=m -CONFIG_IR_PWM_TX=m -CONFIG_IR_REDRAT3=m -CONFIG_IR_SERIAL=m -CONFIG_IR_SERIAL_TRANSMITTER=y -CONFIG_IR_SPI=m -CONFIG_IR_STREAMZAP=m -CONFIG_IR_TOY=m -CONFIG_IR_TTUSBIR=m -CONFIG_RC_ATI_REMOTE=m -CONFIG_RC_LOOPBACK=m -CONFIG_RC_XBOX_DVD=m -CONFIG_CEC_CORE=m -CONFIG_CEC_NOTIFIER=y -CONFIG_CEC_PIN=y - -# -# CEC support -# -# CONFIG_MEDIA_CEC_RC is not set -CONFIG_CEC_PIN_ERROR_INJ=y -CONFIG_MEDIA_CEC_SUPPORT=y -CONFIG_CEC_CH7322=m -CONFIG_CEC_CROS_EC=m -CONFIG_CEC_GPIO=m -CONFIG_USB_PULSE8_CEC=m -CONFIG_USB_RAINSHADOW_CEC=m -# end of CEC support - -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_SUPPORT_FILTER=y -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y - -# -# Media device types -# -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_TEST_SUPPORT=y -# end of Media device types - -CONFIG_VIDEO_DEV=m -CONFIG_MEDIA_CONTROLLER=y -CONFIG_DVB_CORE=m - -# -# Video4Linux options -# -CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -# CONFIG_VIDEO_ADV_DEBUG is not set -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_VIDEO_TUNER=m -CONFIG_V4L2_H264=m -CONFIG_V4L2_VP9=m -CONFIG_V4L2_MEM2MEM_DEV=m -CONFIG_V4L2_FLASH_LED_CLASS=m -CONFIG_V4L2_FWNODE=m -CONFIG_V4L2_ASYNC=m -CONFIG_V4L2_CCI=m -CONFIG_V4L2_CCI_I2C=m -# end of Video4Linux options - -# -# Media controller options -# -CONFIG_MEDIA_CONTROLLER_DVB=y -# end of Media controller options - -# -# Digital TV options -# -CONFIG_DVB_MMAP=y -CONFIG_DVB_NET=y -CONFIG_DVB_MAX_ADAPTERS=16 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y -# CONFIG_DVB_ULE_DEBUG is not set -# end of Digital TV options - -# -# Media drivers -# - -# -# Drivers filtered as selected at 'Filter media drivers' -# - -# -# Media drivers -# -CONFIG_MEDIA_USB_SUPPORT=y - -# -# Webcam devices -# -CONFIG_USB_GSPCA=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_GL860=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y - -# -# Analog TV USB devices -# -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_GO7007_USB=m -CONFIG_VIDEO_GO7007_LOADER=m -CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_STK1160=m - -# -# Analog/digital TV USB devices -# -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_AU0828_V4L2=y -CONFIG_VIDEO_AU0828_RC=y -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_RC=y -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m - -# -# Digital TV USB devices -# -CONFIG_DVB_AS102=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_CXUSB=m -# CONFIG_DVB_USB_CXUSB_ANALOG is not set -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_DIB3000MC=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_VP7045=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m - -# -# Webcam, TV (analog/digital) USB devices -# -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=m - -# -# Software defined radio USB devices -# -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -CONFIG_MEDIA_PCI_SUPPORT=y - -# -# Media capture support -# -# CONFIG_VIDEO_MGB4 is not set -CONFIG_VIDEO_SOLO6X10=m -# CONFIG_VIDEO_TW5864 is not set -CONFIG_VIDEO_TW68=m -# CONFIG_VIDEO_TW686X is not set -CONFIG_VIDEO_ZORAN=m -# CONFIG_VIDEO_ZORAN_DC30 is not set -# CONFIG_VIDEO_ZORAN_ZR36060 is not set - -# -# Media capture/analog TV support -# -CONFIG_VIDEO_DT3155=m -CONFIG_VIDEO_IVTV=m -CONFIG_VIDEO_IVTV_ALSA=m -CONFIG_VIDEO_FB_IVTV=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_MXB=m - -# -# Media capture/analog/hybrid TV support -# -CONFIG_VIDEO_BT848=m -CONFIG_DVB_BT8XX=m -CONFIG_VIDEO_CX18=m -CONFIG_VIDEO_CX18_ALSA=m -CONFIG_VIDEO_CX23885=m -CONFIG_MEDIA_ALTERA_CI=m -CONFIG_VIDEO_CX25821=m -CONFIG_VIDEO_CX25821_ALSA=m -CONFIG_VIDEO_CX88=m -CONFIG_VIDEO_CX88_ALSA=m -CONFIG_VIDEO_CX88_BLACKBIRD=m -CONFIG_VIDEO_CX88_DVB=m -CONFIG_VIDEO_CX88_ENABLE_VP3054=y -CONFIG_VIDEO_CX88_VP3054=m -CONFIG_VIDEO_CX88_MPEG=m -CONFIG_VIDEO_SAA7134=m -CONFIG_VIDEO_SAA7134_ALSA=m -CONFIG_VIDEO_SAA7134_RC=y -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_SAA7134_GO7007=m -CONFIG_VIDEO_SAA7164=m - -# -# Media digital TV PCI Adapters -# -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set -CONFIG_DVB_DDBRIDGE=m -# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set -CONFIG_DVB_DM1105=m -CONFIG_MANTIS_CORE=m -CONFIG_DVB_MANTIS=m -CONFIG_DVB_HOPPER=m -# CONFIG_DVB_NETUP_UNIDVB is not set -CONFIG_DVB_NGENE=m -CONFIG_DVB_PLUTO2=m -CONFIG_DVB_PT1=m -CONFIG_DVB_PT3=m -CONFIG_DVB_SMIPCIE=m -CONFIG_DVB_BUDGET_CORE=m -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_CI=m -CONFIG_DVB_BUDGET_AV=m -# CONFIG_IPU_BRIDGE is not set -CONFIG_RADIO_ADAPTERS=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_SAA7706H=m -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_RADIO_SI4713=m -CONFIG_RADIO_TEA575X=m -CONFIG_RADIO_TEA5764=m -CONFIG_RADIO_TEF6862=m -CONFIG_RADIO_WL1273=m -CONFIG_USB_DSBR=m -CONFIG_USB_KEENE=m -CONFIG_USB_MA901=m -CONFIG_USB_MR800=m -CONFIG_USB_RAREMONO=m -CONFIG_RADIO_SI470X=m -CONFIG_USB_SI470X=m -CONFIG_I2C_SI470X=m -CONFIG_USB_SI4713=m -CONFIG_PLATFORM_SI4713=m -CONFIG_I2C_SI4713=m -CONFIG_MEDIA_PLATFORM_DRIVERS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_DVB_PLATFORM_DRIVERS=y -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -CONFIG_VIDEO_MUX=m - -# -# Allegro DVT media platform drivers -# - -# -# Amlogic media platform drivers -# - -# -# Amphion drivers -# - -# -# Aspeed media platform drivers -# - -# -# Atmel media platform drivers -# - -# -# Cadence media platform drivers -# -CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_CADENCE_CSI2TX=m - -# -# Chips&Media media platform drivers -# - -# -# Intel media platform drivers -# - -# -# Marvell media platform drivers -# -CONFIG_VIDEO_CAFE_CCIC=m - -# -# Mediatek media platform drivers -# - -# -# Microchip Technology, Inc. media platform drivers -# - -# -# Nuvoton media platform drivers -# - -# -# NVidia media platform drivers -# - -# -# NXP media platform drivers -# - -# -# Qualcomm media platform drivers -# - -# -# Renesas media platform drivers -# - -# -# Rockchip media platform drivers -# -CONFIG_VIDEO_ROCKCHIP_RGA=m -CONFIG_VIDEO_ROCKCHIP_ISP1=m - -# -# Samsung media platform drivers -# - -# -# STMicroelectronics media platform drivers -# - -# -# Sunxi media platform drivers -# -CONFIG_VIDEO_SYNOPSYS_HDMIRX=m -CONFIG_HDMIRX_LOAD_DEFAULT_EDID=y - -# -# Texas Instruments drivers -# - -# -# Verisilicon media platform drivers -# -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_ROCKCHIP=y - -# -# VIA media platform drivers -# - -# -# Xilinx media platform drivers -# -CONFIG_VIDEO_XILINX=m -CONFIG_VIDEO_XILINX_CSI2RXSS=m -CONFIG_VIDEO_XILINX_TPG=m -CONFIG_VIDEO_XILINX_VTC=m - -# -# MMC/SDIO DVB adapters -# -CONFIG_SMS_SDIO_DRV=m -CONFIG_V4L_TEST_DRIVERS=y -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m -CONFIG_VIDEO_VIMC=m -CONFIG_VIDEO_VIVID=m -CONFIG_VIDEO_VIVID_CEC=y -CONFIG_VIDEO_VIVID_MAX_DEVS=64 -# CONFIG_VIDEO_VISL is not set -CONFIG_DVB_TEST_DRIVERS=y -CONFIG_DVB_VIDTV=m -CONFIG_MEDIA_COMMON_OPTIONS=y - -# -# common driver options -# -CONFIG_CYPRESS_FIRMWARE=m -CONFIG_TTPCI_EEPROM=m -CONFIG_UVC_COMMON=m -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_VIDEO_SAA7146=m -CONFIG_VIDEO_SAA7146_VV=m -CONFIG_SMS_SIANO_MDTV=m -CONFIG_SMS_SIANO_RC=y -# CONFIG_SMS_SIANO_DEBUGFS is not set -CONFIG_VIDEO_V4L2_TPG=m -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_V4L2=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m -CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEOBUF2_DMA_SG=m -CONFIG_VIDEOBUF2_DVB=m -# end of Media drivers - -# -# Media ancillary drivers -# -CONFIG_MEDIA_ATTACH=y - -# -# IR I2C driver auto-selected by 'Autoselect ancillary drivers' -# -CONFIG_VIDEO_IR_I2C=m -CONFIG_VIDEO_CAMERA_SENSOR=y -CONFIG_VIDEO_APTINA_PLL=m -CONFIG_VIDEO_CCS_PLL=m -# CONFIG_VIDEO_ALVIUM_CSI2 is not set -# CONFIG_VIDEO_AR0521 is not set -# CONFIG_VIDEO_GC0308 is not set -# CONFIG_VIDEO_GC2145 is not set -CONFIG_VIDEO_HI556=m -CONFIG_VIDEO_HI846=m -# CONFIG_VIDEO_HI847 is not set -CONFIG_VIDEO_IMX208=m -CONFIG_VIDEO_IMX214=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_IMX258=m -CONFIG_VIDEO_IMX274=m -CONFIG_VIDEO_IMX290=m -# CONFIG_VIDEO_IMX296 is not set -CONFIG_VIDEO_IMX319=m -CONFIG_VIDEO_IMX334=m -CONFIG_VIDEO_IMX335=m -CONFIG_VIDEO_IMX355=m -CONFIG_VIDEO_IMX412=m -# CONFIG_VIDEO_IMX415 is not set -CONFIG_VIDEO_MAX9271_LIB=m -CONFIG_VIDEO_MT9M001=m -CONFIG_VIDEO_MT9M111=m -# CONFIG_VIDEO_MT9M114 is not set -CONFIG_VIDEO_MT9P031=m -CONFIG_VIDEO_MT9T112=m -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V032=m -CONFIG_VIDEO_MT9V111=m -# CONFIG_VIDEO_OG01A1B is not set -# CONFIG_VIDEO_OV01A10 is not set -CONFIG_VIDEO_OV02A10=m -# CONFIG_VIDEO_OV08D10 is not set -# CONFIG_VIDEO_OV08X40 is not set -CONFIG_VIDEO_OV13858=m -CONFIG_VIDEO_OV13B10=m -CONFIG_VIDEO_OV2640=m -CONFIG_VIDEO_OV2659=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV2685=m -CONFIG_VIDEO_OV2740=m -# CONFIG_VIDEO_OV4689 is not set -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_OV5647=m -CONFIG_VIDEO_OV5648=m -CONFIG_VIDEO_OV5670=m -CONFIG_VIDEO_OV5675=m -# CONFIG_VIDEO_OV5693 is not set -CONFIG_VIDEO_OV5695=m -# CONFIG_VIDEO_OV64A40 is not set -CONFIG_VIDEO_OV6650=m -CONFIG_VIDEO_OV7251=m -CONFIG_VIDEO_OV7640=m -CONFIG_VIDEO_OV7670=m -CONFIG_VIDEO_OV772X=m -CONFIG_VIDEO_OV7740=m -CONFIG_VIDEO_OV8856=m -# CONFIG_VIDEO_OV8858 is not set -CONFIG_VIDEO_OV8865=m -CONFIG_VIDEO_OV9282=m -CONFIG_VIDEO_OV9640=m -CONFIG_VIDEO_OV9650=m -CONFIG_VIDEO_OV9734=m -CONFIG_VIDEO_RDACM20=m -CONFIG_VIDEO_RDACM21=m -CONFIG_VIDEO_RJ54N1=m -CONFIG_VIDEO_S5C73M3=m -CONFIG_VIDEO_S5K5BAF=m -CONFIG_VIDEO_S5K6A3=m -# CONFIG_VIDEO_ST_VGXY61 is not set -CONFIG_VIDEO_CCS=m -CONFIG_VIDEO_ET8EK8=m - -# -# Camera ISPs -# -# CONFIG_VIDEO_THP7312 is not set -# end of Camera ISPs - -# -# Lens drivers -# -CONFIG_VIDEO_AD5820=m -CONFIG_VIDEO_AK7375=m -CONFIG_VIDEO_DW9714=m -# CONFIG_VIDEO_DW9719 is not set -CONFIG_VIDEO_DW9768=m -CONFIG_VIDEO_DW9807_VCM=m -# end of Lens drivers - -# -# Flash devices -# -CONFIG_VIDEO_ADP1653=m -CONFIG_VIDEO_LM3560=m -CONFIG_VIDEO_LM3646=m -# end of Flash devices - -# -# Audio decoders, processors and mixers -# -CONFIG_VIDEO_CS3308=m -CONFIG_VIDEO_CS5345=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_SONY_BTF_MPX=m -# CONFIG_VIDEO_TDA1997X is not set -CONFIG_VIDEO_TDA7432=m -CONFIG_VIDEO_TDA9840=m -CONFIG_VIDEO_TEA6415C=m -CONFIG_VIDEO_TEA6420=m -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_TVAUDIO=m -CONFIG_VIDEO_UDA1342=m -CONFIG_VIDEO_VP27SMPX=m -CONFIG_VIDEO_WM8739=m -CONFIG_VIDEO_WM8775=m -# end of Audio decoders, processors and mixers - -# -# RDS decoders -# -CONFIG_VIDEO_SAA6588=m -# end of RDS decoders - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_ADV7183 is not set -# CONFIG_VIDEO_ADV748X is not set -# CONFIG_VIDEO_ADV7604 is not set -# CONFIG_VIDEO_ADV7842 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_ISL7998X is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_MAX9286 is not set -# CONFIG_VIDEO_ML86V7667 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_TC358743 is not set -# CONFIG_VIDEO_TC358746 is not set -# CONFIG_VIDEO_TVP514X is not set -CONFIG_VIDEO_TVP5150=m -# CONFIG_VIDEO_TVP7002 is not set -CONFIG_VIDEO_TW2804=m -# CONFIG_VIDEO_TW9900 is not set -CONFIG_VIDEO_TW9903=m -CONFIG_VIDEO_TW9906=m -# CONFIG_VIDEO_TW9910 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_SAA717X=m -CONFIG_VIDEO_CX25840=m -# end of Video decoders - -# -# Video encoders -# -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_ADV7343 is not set -# CONFIG_VIDEO_ADV7393 is not set -# CONFIG_VIDEO_AK881X is not set -CONFIG_VIDEO_SAA7127=m -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_THS8200 is not set -# end of Video encoders - -# -# Video improvement chips -# -CONFIG_VIDEO_UPD64031A=m -CONFIG_VIDEO_UPD64083=m -# end of Video improvement chips - -# -# Audio/Video compression chips -# -CONFIG_VIDEO_SAA6752HS=m -# end of Audio/Video compression chips - -# -# SDR tuner chips -# -# CONFIG_SDR_MAX2175 is not set -# end of SDR tuner chips - -# -# Miscellaneous helper chips -# -# CONFIG_VIDEO_I2C is not set -CONFIG_VIDEO_M52790=m -# CONFIG_VIDEO_ST_MIPID02 is not set -# CONFIG_VIDEO_THS7303 is not set -# end of Miscellaneous helper chips - -# -# Video serializers and deserializers -# -# CONFIG_VIDEO_DS90UB913 is not set -# CONFIG_VIDEO_DS90UB953 is not set -# CONFIG_VIDEO_DS90UB960 is not set -# end of Video serializers and deserializers - -# -# Media SPI Adapters -# -CONFIG_CXD2880_SPI_DRV=m -CONFIG_VIDEO_GS1662=m -# end of Media SPI Adapters - -CONFIG_MEDIA_TUNER=m - -# -# Customize TV tuners -# -CONFIG_MEDIA_TUNER_E4000=m -CONFIG_MEDIA_TUNER_FC0011=m -CONFIG_MEDIA_TUNER_FC0012=m -CONFIG_MEDIA_TUNER_FC0013=m -CONFIG_MEDIA_TUNER_FC2580=m -CONFIG_MEDIA_TUNER_IT913X=m -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MSI001=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2063=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MXL301RF=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_QM1D1B0004=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_R820T=m -CONFIG_MEDIA_TUNER_SI2157=m -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_MEDIA_TUNER_TDA18218=m -CONFIG_MEDIA_TUNER_TDA18250=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_TUA9001=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC4000=m -CONFIG_MEDIA_TUNER_XC5000=m -# end of Customize TV tuners - -# -# Customise DVB Frontends -# - -# -# Multistandard (satellite) frontends -# -CONFIG_DVB_M88DS3103=m -CONFIG_DVB_MXL5XX=m -CONFIG_DVB_STB0899=m -CONFIG_DVB_STB6100=m -CONFIG_DVB_STV090x=m -CONFIG_DVB_STV0910=m -CONFIG_DVB_STV6110x=m -CONFIG_DVB_STV6111=m - -# -# Multistandard (cable + terrestrial) frontends -# -CONFIG_DVB_DRXK=m -CONFIG_DVB_MN88472=m -CONFIG_DVB_MN88473=m -CONFIG_DVB_SI2165=m -CONFIG_DVB_TDA18271C2DD=m - -# -# DVB-S (satellite) frontends -# -CONFIG_DVB_CX24110=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_CX24117=m -CONFIG_DVB_CX24120=m -CONFIG_DVB_CX24123=m -CONFIG_DVB_DS3000=m -CONFIG_DVB_MB86A16=m -CONFIG_DVB_MT312=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_STV0900=m -CONFIG_DVB_STV6110=m -CONFIG_DVB_TDA10071=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA8261=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_TS2020=m -CONFIG_DVB_TUA6100=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_VES1X93=m -CONFIG_DVB_ZL10036=m -CONFIG_DVB_ZL10039=m - -# -# DVB-T (terrestrial) frontends -# -CONFIG_DVB_AF9013=m -CONFIG_DVB_AS102_FE=m -CONFIG_DVB_CX22700=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_CXD2820R=m -CONFIG_DVB_CXD2841ER=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -# CONFIG_DVB_DIB9000 is not set -CONFIG_DVB_DRXD=m -CONFIG_DVB_EC100=m -CONFIG_DVB_GP8PSK_FE=m -CONFIG_DVB_L64781=m -CONFIG_DVB_MT352=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_RTL2830=m -CONFIG_DVB_RTL2832=m -CONFIG_DVB_RTL2832_SDR=m -# CONFIG_DVB_S5H1432 is not set -CONFIG_DVB_SI2168=m -CONFIG_DVB_SP887X=m -CONFIG_DVB_STV0367=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_ZD1301_DEMOD=m -CONFIG_DVB_ZL10353=m -# CONFIG_DVB_CXD2880 is not set - -# -# DVB-C (cable) frontends -# -CONFIG_DVB_STV0297=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_VES1820=m - -# -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -# -CONFIG_DVB_AU8522=m -CONFIG_DVB_AU8522_DTV=m -CONFIG_DVB_AU8522_V4L=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LG2160=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_LGDT3306A=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_MXL692=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m - -# -# ISDB-T (terrestrial) frontends -# -CONFIG_DVB_DIB8000=m -CONFIG_DVB_MB86A20S=m -CONFIG_DVB_S921=m - -# -# ISDB-S (satellite) & ISDB-T (terrestrial) frontends -# -# CONFIG_DVB_MN88443X is not set -CONFIG_DVB_TC90522=m - -# -# Digital terrestrial only tuners/PLL -# -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_TUNER_DIB0090=m - -# -# SEC control devices for DVB-S -# -CONFIG_DVB_A8293=m -CONFIG_DVB_AF9033=m -# CONFIG_DVB_ASCOT2E is not set -CONFIG_DVB_ATBM8830=m -# CONFIG_DVB_HELENE is not set -# CONFIG_DVB_HORUS3A is not set -CONFIG_DVB_ISL6405=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_ISL6423=m -CONFIG_DVB_IX2505V=m -# CONFIG_DVB_LGS8GL5 is not set -CONFIG_DVB_LGS8GXX=m -CONFIG_DVB_LNBH25=m -# CONFIG_DVB_LNBH29 is not set -CONFIG_DVB_LNBP21=m -CONFIG_DVB_LNBP22=m -CONFIG_DVB_M88RS2000=m -CONFIG_DVB_TDA665x=m -CONFIG_DVB_DRX39XYJ=m - -# -# Common Interface (EN50221) controller drivers -# -CONFIG_DVB_CXD2099=m -CONFIG_DVB_SP2=m -# end of Customise DVB Frontends - -# -# Tools to develop new frontends -# -CONFIG_DVB_DUMMY_FE=m -# end of Media ancillary drivers - -# -# Graphics support -# -CONFIG_APERTURE_HELPERS=y -CONFIG_SCREEN_INFO=y -CONFIG_VIDEO=y -# CONFIG_AUXDISPLAY is not set -CONFIG_DRM=m -CONFIG_DRM_MIPI_DBI=m -CONFIG_DRM_MIPI_DSI=y -# CONFIG_DRM_DEBUG_MM is not set -CONFIG_DRM_KUNIT_TEST_HELPERS=m -CONFIG_DRM_KUNIT_TEST=m -CONFIG_DRM_KMS_HELPER=m -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -# CONFIG_DRM_DEBUG_MODESET_LOCK is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_DISPLAY_HELPER=m -CONFIG_DRM_DISPLAY_DP_AUX_BUS=m -# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set -# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set -CONFIG_DRM_DISPLAY_DP_HELPER=y -CONFIG_DRM_DISPLAY_HDCP_HELPER=y -CONFIG_DRM_DISPLAY_HDMI_HELPER=y -CONFIG_DRM_TTM=m -CONFIG_DRM_EXEC=m -CONFIG_DRM_GPUVM=m -CONFIG_DRM_BUDDY=m -CONFIG_DRM_VRAM_HELPER=m -CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_GEM_DMA_HELPER=m -CONFIG_DRM_GEM_SHMEM_HELPER=m -CONFIG_DRM_SCHED=m - -# -# I2C encoder or helper chips -# -CONFIG_DRM_I2C_CH7006=m -CONFIG_DRM_I2C_SIL164=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_I2C_NXP_TDA9950=m -# end of I2C encoder or helper chips - -# -# ARM devices -# -CONFIG_DRM_HDLCD=m -CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y -# CONFIG_DRM_MALI_DISPLAY is not set -CONFIG_DRM_KOMEDA=m -# end of ARM devices - -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_XE is not set -CONFIG_DRM_VGEM=m -# CONFIG_DRM_VKMS is not set -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_VOP=y -CONFIG_ROCKCHIP_VOP2=y -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_ROCKCHIP_RGB=y -CONFIG_ROCKCHIP_RK3066_HDMI=y -CONFIG_DRM_VMWGFX=m -CONFIG_DRM_UDL=m -CONFIG_DRM_AST=m -CONFIG_DRM_MGAG200=m -CONFIG_DRM_QXL=m -CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_VIRTIO_GPU_KMS=y -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -CONFIG_DRM_PANEL_ABT_Y030XX067A=m -CONFIG_DRM_PANEL_ARM_VERSATILE=m -# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set -# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set -CONFIG_DRM_PANEL_BOE_HIMAX8279D=m -# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -# CONFIG_DRM_PANEL_EBBG_FT8719 is not set -CONFIG_DRM_PANEL_ELIDA_KD35T133=m -CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m -CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m -CONFIG_DRM_PANEL_DSI_CM=m -CONFIG_DRM_PANEL_LVDS=m -# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set -# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set -CONFIG_DRM_PANEL_ILITEK_IL9322=m -CONFIG_DRM_PANEL_ILITEK_ILI9341=m -# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set -CONFIG_DRM_PANEL_ILITEK_ILI9881C=m -# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set -CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m -CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m -# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set -# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set -CONFIG_DRM_PANEL_JDI_LT070ME05000=m -# CONFIG_DRM_PANEL_JDI_R63452 is not set -CONFIG_DRM_PANEL_KHADAS_TS050=m -CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m -# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m -CONFIG_DRM_PANEL_LG_LB035Q02=m -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_LG_SW43408 is not set -# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set -CONFIG_DRM_PANEL_NEC_NL8048HL11=m -# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set -CONFIG_DRM_PANEL_NEWVISION_NV3052C=m -CONFIG_DRM_PANEL_NOVATEK_NT35510=m -CONFIG_DRM_PANEL_NOVATEK_NT35560=m -# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set -CONFIG_DRM_PANEL_NOVATEK_NT36672A=m -# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set -CONFIG_DRM_PANEL_NOVATEK_NT39016=m -CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m -# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set -CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m -# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set -CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_RAYDIUM_RM68200=m -# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set -# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set -CONFIG_DRM_PANEL_RONBO_RB070D30=m -CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m -CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m -CONFIG_DRM_PANEL_SAMSUNG_DB7430=m -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set -CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m -CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m -# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set -CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m -CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m -# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m -CONFIG_DRM_PANEL_SEIKO_43WVF1G=m -CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m -CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m -CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m -CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m -CONFIG_DRM_PANEL_SITRONIX_ST7701=m -# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -CONFIG_DRM_PANEL_SONY_ACX565AKM=m -# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set -# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set -# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set -CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_SIMPLE=m -# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set -CONFIG_DRM_PANEL_TDO_TL070WSH30=m -CONFIG_DRM_PANEL_TPO_TD028TTEC1=m -CONFIG_DRM_PANEL_TPO_TD043MTEA1=m -CONFIG_DRM_PANEL_TPO_TPG110=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set -# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set -# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m -CONFIG_DRM_PANEL_XINPENG_XPP055C272=m -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -CONFIG_DRM_CHIPONE_ICN6211=m -CONFIG_DRM_CHRONTEL_CH7033=m -CONFIG_DRM_CROS_EC_ANX7688=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_ITE_IT6505=m -CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_LONTIUM_LT9211=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_LONTIUM_LT9611UXC=m -CONFIG_DRM_ITE_IT66121=m -CONFIG_DRM_LVDS_CODEC=m -# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set -CONFIG_DRM_NWL_MIPI_DSI=m -# CONFIG_DRM_NXP_PTN3460 is not set -# CONFIG_DRM_PARADE_PS8622 is not set -CONFIG_DRM_PARADE_PS8640=m -# CONFIG_DRM_SAMSUNG_DSIM is not set -# CONFIG_DRM_SIL_SII8620 is not set -CONFIG_DRM_SII902X=m -CONFIG_DRM_SII9234=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -# CONFIG_DRM_TOSHIBA_TC358762 is not set -CONFIG_DRM_TOSHIBA_TC358764=m -# CONFIG_DRM_TOSHIBA_TC358767 is not set -CONFIG_DRM_TOSHIBA_TC358768=m -# CONFIG_DRM_TOSHIBA_TC358775 is not set -# CONFIG_DRM_TI_DLPC3433 is not set -# CONFIG_DRM_TI_TFP410 is not set -CONFIG_DRM_TI_SN65DSI83=m -# CONFIG_DRM_TI_SN65DSI86 is not set -CONFIG_DRM_TI_TPD12S015=m -CONFIG_DRM_ANALOGIX_ANX6345=m -CONFIG_DRM_ANALOGIX_ANX78XX=m -CONFIG_DRM_ANALOGIX_DP=m -# CONFIG_DRM_ANALOGIX_ANX7625 is not set -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_I2C_ADV7511_CEC=y -CONFIG_DRM_CDNS_DSI=m -CONFIG_DRM_CDNS_DSI_J721E=y -# CONFIG_DRM_CDNS_MHDP8546 is not set -CONFIG_DRM_DW_HDMI=m -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_I2S_AUDIO=m -# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_DW_MIPI_DSI=m -# end of Display Interface Bridges - -CONFIG_DRM_ETNAVIV=m -CONFIG_DRM_ETNAVIV_THERMAL=y -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_LOGICVC=m -# CONFIG_DRM_ARCPGU is not set -CONFIG_DRM_BOCHS=m -# CONFIG_DRM_CIRRUS_QEMU is not set -CONFIG_DRM_GM12U320=m -CONFIG_DRM_PANEL_MIPI_DBI=m -CONFIG_DRM_SIMPLEDRM=m -CONFIG_TINYDRM_HX8357D=m -# CONFIG_TINYDRM_ILI9163 is not set -CONFIG_TINYDRM_ILI9225=m -CONFIG_TINYDRM_ILI9341=m -CONFIG_TINYDRM_ILI9486=m -CONFIG_TINYDRM_MI0283QT=m -CONFIG_TINYDRM_REPAPER=m -CONFIG_TINYDRM_ST7586=m -CONFIG_TINYDRM_ST7735R=m -CONFIG_DRM_PL111=m -CONFIG_DRM_XEN=y -CONFIG_DRM_XEN_FRONTEND=m -CONFIG_DRM_LIMA=m -CONFIG_DRM_PANFROST=m -CONFIG_DRM_PANTHOR=m -CONFIG_DRM_TIDSS=m -CONFIG_DRM_GUD=m -CONFIG_DRM_SSD130X=m -CONFIG_DRM_SSD130X_I2C=m -CONFIG_DRM_SSD130X_SPI=m -# CONFIG_DRM_POWERVR is not set -CONFIG_DRM_EXPORT_FOR_TESTS=y -CONFIG_DRM_LIB_RANDOM=y -# CONFIG_DRM_WERROR is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y - -# -# Frame buffer Devices -# -CONFIG_FB=y -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -CONFIG_FB_UVESA=m -CONFIG_FB_EFI=y -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -CONFIG_FB_UDL=m -# CONFIG_FB_IBM_GXT4500 is not set -CONFIG_FB_VIRTUAL=m -CONFIG_XEN_FBDEV_FRONTEND=y -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -CONFIG_FB_SIMPLE=m -CONFIG_FB_SSD1307=m -# CONFIG_FB_SM712 is not set -CONFIG_FB_CORE=y -CONFIG_FB_NOTIFY=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_DEVICE=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYSMEM_FOPS=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_IOMEM_FOPS=y -CONFIG_FB_IOMEM_HELPERS=y -CONFIG_FB_SYSMEM_HELPERS=y -CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y -CONFIG_FB_BACKLIGHT=m -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -# end of Frame buffer Devices - -# -# Backlight & LCD device support -# -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_L4F00242T03 is not set -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_ILI922X is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -CONFIG_LCD_PLATFORM=m -# CONFIG_LCD_AMS369FG06 is not set -# CONFIG_LCD_LMS501KF03 is not set -# CONFIG_LCD_HX8357 is not set -CONFIG_LCD_OTM3225A=m -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_KTD253 is not set -# CONFIG_BACKLIGHT_KTD2801 is not set -# CONFIG_BACKLIGHT_KTZ8866 is not set -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_MT6370=m -CONFIG_BACKLIGHT_QCOM_WLED=m -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3630A is not set -# CONFIG_BACKLIGHT_LM3639 is not set -CONFIG_BACKLIGHT_LP855X=y -# CONFIG_BACKLIGHT_MP3309C is not set -CONFIG_BACKLIGHT_GPIO=m -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -CONFIG_BACKLIGHT_LED=m -# end of Backlight & LCD device support - -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_HDMI=y - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# end of Console display driver support - -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# end of Graphics support - -# CONFIG_DRM_ACCEL is not set -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_PCM_ELD=y -CONFIG_SND_PCM_IEC958=y -CONFIG_SND_DMAENGINE_PCM=m -CONFIG_SND_HWDEP=m -CONFIG_SND_SEQ_DEVICE=m -CONFIG_SND_RAWMIDI=m -# CONFIG_SND_CORE_TEST is not set -CONFIG_SND_COMPRESS_OFFLOAD=m -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_OSSEMUL is not set -CONFIG_SND_PCM_TIMER=y -# CONFIG_SND_HRTIMER is not set -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_MAX_CARDS=32 -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_PROC_FS=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -CONFIG_SND_CTL_FAST_LOOKUP=y -# CONFIG_SND_DEBUG is not set -CONFIG_SND_CTL_INPUT_VALIDATION=y -CONFIG_SND_VMASTER=y -CONFIG_SND_CTL_LED=m -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_SEQ_MIDI_EVENT=m -CONFIG_SND_SEQ_MIDI=m -CONFIG_SND_SEQ_MIDI_EMUL=m -CONFIG_SND_SEQ_VIRMIDI=m -# CONFIG_SND_SEQ_UMP is not set -CONFIG_SND_MPU401_UART=m -CONFIG_SND_OPL3_LIB=m -CONFIG_SND_OPL3_LIB_SEQ=m -CONFIG_SND_VX_LIB=m -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_DRIVERS=y -CONFIG_SND_DUMMY=m -CONFIG_SND_ALOOP=m -# CONFIG_SND_PCMTEST is not set -CONFIG_SND_VIRMIDI=m -CONFIG_SND_MTPAV=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_SERIAL_GENERIC=m -CONFIG_SND_MPU401=m -CONFIG_SND_AC97_POWER_SAVE=y -CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 -CONFIG_SND_PCI=y -CONFIG_SND_AD1889=m -CONFIG_SND_ALS300=m -CONFIG_SND_ALI5451=m -CONFIG_SND_ATIIXP=m -CONFIG_SND_ATIIXP_MODEM=m -CONFIG_SND_AU8810=m -CONFIG_SND_AU8820=m -CONFIG_SND_AU8830=m -CONFIG_SND_AW2=m -CONFIG_SND_AZT3328=m -CONFIG_SND_BT87X=m -CONFIG_SND_BT87X_OVERCLOCK=y -CONFIG_SND_CA0106=m -CONFIG_SND_CMIPCI=m -CONFIG_SND_OXYGEN_LIB=m -CONFIG_SND_OXYGEN=m -CONFIG_SND_CS4281=m -CONFIG_SND_CS46XX=m -CONFIG_SND_CS46XX_NEW_DSP=y -CONFIG_SND_CTXFI=m -CONFIG_SND_DARLA20=m -CONFIG_SND_GINA20=m -CONFIG_SND_LAYLA20=m -CONFIG_SND_DARLA24=m -CONFIG_SND_GINA24=m -CONFIG_SND_LAYLA24=m -CONFIG_SND_MONA=m -CONFIG_SND_MIA=m -CONFIG_SND_ECHO3G=m -CONFIG_SND_INDIGO=m -CONFIG_SND_INDIGOIO=m -CONFIG_SND_INDIGODJ=m -CONFIG_SND_INDIGOIOX=m -CONFIG_SND_INDIGODJX=m -CONFIG_SND_EMU10K1=m -CONFIG_SND_EMU10K1_SEQ=m -CONFIG_SND_EMU10K1X=m -CONFIG_SND_ENS1370=m -CONFIG_SND_ENS1371=m -CONFIG_SND_ES1938=m -CONFIG_SND_ES1968=m -CONFIG_SND_ES1968_INPUT=y -CONFIG_SND_ES1968_RADIO=y -CONFIG_SND_FM801=m -CONFIG_SND_FM801_TEA575X_BOOL=y -CONFIG_SND_HDSP=m -CONFIG_SND_HDSPM=m -CONFIG_SND_ICE1712=m -CONFIG_SND_ICE1724=m -CONFIG_SND_INTEL8X0=m -CONFIG_SND_INTEL8X0M=m -CONFIG_SND_KORG1212=m -CONFIG_SND_LOLA=m -CONFIG_SND_LX6464ES=m -CONFIG_SND_MAESTRO3=m -CONFIG_SND_MAESTRO3_INPUT=y -CONFIG_SND_MIXART=m -CONFIG_SND_NM256=m -CONFIG_SND_PCXHR=m -CONFIG_SND_RIPTIDE=m -CONFIG_SND_RME32=m -CONFIG_SND_RME96=m -CONFIG_SND_RME9652=m -CONFIG_SND_SONICVIBES=m -CONFIG_SND_TRIDENT=m -CONFIG_SND_VIA82XX=m -CONFIG_SND_VIA82XX_MODEM=m -CONFIG_SND_VIRTUOSO=m -CONFIG_SND_VX222=m -CONFIG_SND_YMFPCI=m - -# -# HD-Audio -# -CONFIG_SND_HDA=m -CONFIG_SND_HDA_GENERIC_LEDS=y -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_HDA_HWDEP=y -CONFIG_SND_HDA_RECONFIG=y -CONFIG_SND_HDA_INPUT_BEEP=y -CONFIG_SND_HDA_INPUT_BEEP_MODE=1 -CONFIG_SND_HDA_PATCH_LOADER=y -# CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST is not set -CONFIG_SND_HDA_SCODEC_CS35L41=m -CONFIG_SND_HDA_CS_DSP_CONTROLS=m -CONFIG_SND_HDA_SCODEC_COMPONENT=m -CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m -CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m -# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set -# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set -# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set -CONFIG_SND_HDA_CODEC_REALTEK=m -CONFIG_SND_HDA_CODEC_ANALOG=m -CONFIG_SND_HDA_CODEC_SIGMATEL=m -CONFIG_SND_HDA_CODEC_VIA=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_HDA_CODEC_CIRRUS=m -CONFIG_SND_HDA_CODEC_CS8409=m -CONFIG_SND_HDA_CODEC_CONEXANT=m -CONFIG_SND_HDA_CODEC_CA0110=m -CONFIG_SND_HDA_CODEC_CA0132=m -CONFIG_SND_HDA_CODEC_CA0132_DSP=y -CONFIG_SND_HDA_CODEC_CMEDIA=m -CONFIG_SND_HDA_CODEC_SI3054=m -CONFIG_SND_HDA_GENERIC=m -CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 -CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y -# CONFIG_SND_HDA_CTL_DEV_ID is not set -# end of HD-Audio - -CONFIG_SND_HDA_CORE=m -CONFIG_SND_HDA_DSP_LOADER=y -CONFIG_SND_HDA_EXT_CORE=m -CONFIG_SND_HDA_PREALLOC_SIZE=64 -CONFIG_SND_INTEL_NHLT=y -CONFIG_SND_INTEL_DSP_CONFIG=m -CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=m -# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set -CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_LINE6=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_COMPRESS=y -# CONFIG_SND_SOC_TOPOLOGY_BUILD is not set -# CONFIG_SND_SOC_CARD_KUNIT_TEST is not set -CONFIG_SND_SOC_UTILS_KUNIT_TEST=m -CONFIG_SND_SOC_ACPI=m -CONFIG_SND_SOC_ADI=m -CONFIG_SND_SOC_ADI_AXI_I2S=m -CONFIG_SND_SOC_ADI_AXI_SPDIF=m -CONFIG_SND_SOC_AMD_ACP=m -CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m -CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m -CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m -# CONFIG_SND_AMD_ACP_CONFIG is not set -CONFIG_SND_ATMEL_SOC=m -CONFIG_SND_SOC_MIKROE_PROTO=m -CONFIG_SND_BCM63XX_I2S_WHISTLER=m -CONFIG_SND_DESIGNWARE_I2S=m -CONFIG_SND_DESIGNWARE_PCM=y - -# -# SoC Audio for Freescale CPUs -# - -# -# Common SoC Audio options for Freescale CPUs: -# -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_MQS=m -CONFIG_SND_SOC_FSL_AUDMIX=m -CONFIG_SND_SOC_FSL_SSI=m -CONFIG_SND_SOC_FSL_SPDIF=m -CONFIG_SND_SOC_FSL_ESAI=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_SOC_FSL_XCVR=m -CONFIG_SND_SOC_FSL_UTILS=m -CONFIG_SND_SOC_FSL_RPMSG=m -CONFIG_SND_SOC_IMX_AUDMUX=m -# end of SoC Audio for Freescale CPUs - -# CONFIG_SND_SOC_CHV3_I2S is not set -CONFIG_SND_I2S_HI6210_I2S=m -CONFIG_SND_SOC_IMG=y -CONFIG_SND_SOC_IMG_I2S_IN=m -CONFIG_SND_SOC_IMG_I2S_OUT=m -CONFIG_SND_SOC_IMG_PARALLEL_OUT=m -CONFIG_SND_SOC_IMG_SPDIF_IN=m -CONFIG_SND_SOC_IMG_SPDIF_OUT=m -CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m -CONFIG_SND_SOC_MTK_BTCVSD=m -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_I2S=m -CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m -CONFIG_SND_SOC_ROCKCHIP_PDM=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_MAX98090=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m -CONFIG_SND_SOC_SOF_TOPLEVEL=y -CONFIG_SND_SOC_SOF_PCI=m -CONFIG_SND_SOC_SOF_ACPI=m -CONFIG_SND_SOC_SOF_OF=m -CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y -# CONFIG_SND_SOC_SOF_MTK_TOPLEVEL is not set - -# -# STMicroelectronics STM32 SOC audio support -# -# end of STMicroelectronics STM32 SOC audio support - -CONFIG_SND_SOC_XILINX_I2S=m -CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m -CONFIG_SND_SOC_XILINX_SPDIF=m -CONFIG_SND_SOC_XTFPGA_I2S=m -CONFIG_SND_SOC_I2C_AND_SPI=m - -# -# CODEC drivers -# -CONFIG_SND_SOC_WM_ADSP=m -CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_ADAU_UTILS=m -CONFIG_SND_SOC_ADAU1372=m -CONFIG_SND_SOC_ADAU1372_I2C=m -CONFIG_SND_SOC_ADAU1372_SPI=m -CONFIG_SND_SOC_ADAU1701=m -CONFIG_SND_SOC_ADAU17X1=m -CONFIG_SND_SOC_ADAU1761=m -CONFIG_SND_SOC_ADAU1761_I2C=m -CONFIG_SND_SOC_ADAU1761_SPI=m -CONFIG_SND_SOC_ADAU7002=m -CONFIG_SND_SOC_ADAU7118=m -CONFIG_SND_SOC_ADAU7118_HW=m -CONFIG_SND_SOC_ADAU7118_I2C=m -CONFIG_SND_SOC_AK4104=m -CONFIG_SND_SOC_AK4118=m -CONFIG_SND_SOC_AK4375=m -CONFIG_SND_SOC_AK4458=m -CONFIG_SND_SOC_AK4554=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_AK4642=m -CONFIG_SND_SOC_AK5386=m -CONFIG_SND_SOC_AK5558=m -CONFIG_SND_SOC_ALC5623=m -# CONFIG_SND_SOC_AUDIO_IIO_AUX is not set -CONFIG_SND_SOC_AW8738=m -# CONFIG_SND_SOC_AW88395 is not set -# CONFIG_SND_SOC_AW88261 is not set -# CONFIG_SND_SOC_AW87390 is not set -# CONFIG_SND_SOC_AW88399 is not set -CONFIG_SND_SOC_BD28623=m -CONFIG_SND_SOC_BT_SCO=m -# CONFIG_SND_SOC_CHV3_CODEC is not set -CONFIG_SND_SOC_CROS_EC_CODEC=m -CONFIG_SND_SOC_CS_AMP_LIB=m -# CONFIG_SND_SOC_CS_AMP_LIB_TEST is not set -CONFIG_SND_SOC_CS35L32=m -CONFIG_SND_SOC_CS35L33=m -CONFIG_SND_SOC_CS35L34=m -CONFIG_SND_SOC_CS35L35=m -CONFIG_SND_SOC_CS35L36=m -CONFIG_SND_SOC_CS35L41_LIB=m -CONFIG_SND_SOC_CS35L41=m -CONFIG_SND_SOC_CS35L41_SPI=m -CONFIG_SND_SOC_CS35L41_I2C=m -CONFIG_SND_SOC_CS35L45=m -CONFIG_SND_SOC_CS35L45_SPI=m -CONFIG_SND_SOC_CS35L45_I2C=m -# CONFIG_SND_SOC_CS35L56_I2C is not set -# CONFIG_SND_SOC_CS35L56_SPI is not set -# CONFIG_SND_SOC_CS35L56_SDW is not set -CONFIG_SND_SOC_CS42L42_CORE=m -CONFIG_SND_SOC_CS42L42=m -# CONFIG_SND_SOC_CS42L42_SDW is not set -CONFIG_SND_SOC_CS42L51=m -CONFIG_SND_SOC_CS42L51_I2C=m -CONFIG_SND_SOC_CS42L52=m -CONFIG_SND_SOC_CS42L56=m -CONFIG_SND_SOC_CS42L73=m -CONFIG_SND_SOC_CS42L83=m -CONFIG_SND_SOC_CS4234=m -CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4270=m -CONFIG_SND_SOC_CS4271=m -CONFIG_SND_SOC_CS4271_I2C=m -CONFIG_SND_SOC_CS4271_SPI=m -CONFIG_SND_SOC_CS42XX8=m -CONFIG_SND_SOC_CS42XX8_I2C=m -CONFIG_SND_SOC_CS43130=m -CONFIG_SND_SOC_CS4341=m -CONFIG_SND_SOC_CS4349=m -CONFIG_SND_SOC_CS53L30=m -CONFIG_SND_SOC_CX2072X=m -CONFIG_SND_SOC_DA7213=m -CONFIG_SND_SOC_DA7219=m -CONFIG_SND_SOC_DMIC=m -CONFIG_SND_SOC_HDMI_CODEC=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_ES8316=m -CONFIG_SND_SOC_ES8326=m -CONFIG_SND_SOC_ES8328=m -CONFIG_SND_SOC_ES8328_I2C=m -CONFIG_SND_SOC_ES8328_SPI=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_HDA=m -CONFIG_SND_SOC_ICS43432=m -# CONFIG_SND_SOC_IDT821034 is not set -CONFIG_SND_SOC_INNO_RK3036=m -CONFIG_SND_SOC_MAX98088=m -CONFIG_SND_SOC_MAX98090=m -CONFIG_SND_SOC_MAX98357A=m -CONFIG_SND_SOC_MAX98504=m -CONFIG_SND_SOC_MAX9867=m -CONFIG_SND_SOC_MAX98927=m -CONFIG_SND_SOC_MAX98520=m -# CONFIG_SND_SOC_MAX98363 is not set -CONFIG_SND_SOC_MAX98373=m -CONFIG_SND_SOC_MAX98373_I2C=m -CONFIG_SND_SOC_MAX98373_SDW=m -# CONFIG_SND_SOC_MAX98388 is not set -CONFIG_SND_SOC_MAX98390=m -CONFIG_SND_SOC_MAX98396=m -CONFIG_SND_SOC_MAX9860=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM1681=m -CONFIG_SND_SOC_PCM1789=m -CONFIG_SND_SOC_PCM1789_I2C=m -CONFIG_SND_SOC_PCM179X=m -CONFIG_SND_SOC_PCM179X_I2C=m -CONFIG_SND_SOC_PCM179X_SPI=m -CONFIG_SND_SOC_PCM186X=m -CONFIG_SND_SOC_PCM186X_I2C=m -CONFIG_SND_SOC_PCM186X_SPI=m -CONFIG_SND_SOC_PCM3060=m -CONFIG_SND_SOC_PCM3060_I2C=m -CONFIG_SND_SOC_PCM3060_SPI=m -CONFIG_SND_SOC_PCM3168A=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_PCM3168A_SPI=m -CONFIG_SND_SOC_PCM5102A=m -CONFIG_SND_SOC_PCM512x=m -CONFIG_SND_SOC_PCM512x_I2C=m -CONFIG_SND_SOC_PCM512x_SPI=m -# CONFIG_SND_SOC_PCM6240 is not set -# CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3308 is not set -CONFIG_SND_SOC_RK3328=m -# CONFIG_SND_SOC_RK817 is not set -CONFIG_SND_SOC_RL6231=m -# CONFIG_SND_SOC_RT1017_SDCA_SDW is not set -CONFIG_SND_SOC_RT1308_SDW=m -CONFIG_SND_SOC_RT1316_SDW=m -# CONFIG_SND_SOC_RT1318_SDW is not set -CONFIG_SND_SOC_RT5514=m -CONFIG_SND_SOC_RT5514_SPI=m -CONFIG_SND_SOC_RT5616=m -CONFIG_SND_SOC_RT5631=m -CONFIG_SND_SOC_RT5640=m -CONFIG_SND_SOC_RT5645=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_RT5682=m -CONFIG_SND_SOC_RT5682_I2C=m -CONFIG_SND_SOC_RT5682_SDW=m -CONFIG_SND_SOC_RT700=m -CONFIG_SND_SOC_RT700_SDW=m -CONFIG_SND_SOC_RT711=m -CONFIG_SND_SOC_RT711_SDW=m -CONFIG_SND_SOC_RT711_SDCA_SDW=m -# CONFIG_SND_SOC_RT712_SDCA_SDW is not set -# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set -# CONFIG_SND_SOC_RT722_SDCA_SDW is not set -CONFIG_SND_SOC_RT715=m -CONFIG_SND_SOC_RT715_SDW=m -CONFIG_SND_SOC_RT715_SDCA_SDW=m -# CONFIG_SND_SOC_RT9120 is not set -# CONFIG_SND_SOC_RTQ9128 is not set -# CONFIG_SND_SOC_SDW_MOCKUP is not set -CONFIG_SND_SOC_SGTL5000=m -CONFIG_SND_SOC_SIGMADSP=m -CONFIG_SND_SOC_SIGMADSP_I2C=m -CONFIG_SND_SOC_SIGMADSP_REGMAP=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -# CONFIG_SND_SOC_SMA1303 is not set -CONFIG_SND_SOC_SPDIF=m -CONFIG_SND_SOC_SRC4XXX_I2C=m -CONFIG_SND_SOC_SRC4XXX=m -CONFIG_SND_SOC_SSM2305=m -CONFIG_SND_SOC_SSM2518=m -CONFIG_SND_SOC_SSM2602=m -CONFIG_SND_SOC_SSM2602_SPI=m -CONFIG_SND_SOC_SSM2602_I2C=m -# CONFIG_SND_SOC_SSM3515 is not set -CONFIG_SND_SOC_SSM4567=m -CONFIG_SND_SOC_STA32X=m -CONFIG_SND_SOC_STA350=m -CONFIG_SND_SOC_STI_SAS=m -CONFIG_SND_SOC_TAS2552=m -CONFIG_SND_SOC_TAS2562=m -CONFIG_SND_SOC_TAS2764=m -CONFIG_SND_SOC_TAS2770=m -CONFIG_SND_SOC_TAS2780=m -# CONFIG_SND_SOC_TAS2781_I2C is not set -CONFIG_SND_SOC_TAS5086=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TAS5720=m -CONFIG_SND_SOC_TAS5805M=m -CONFIG_SND_SOC_TAS6424=m -CONFIG_SND_SOC_TDA7419=m -CONFIG_SND_SOC_TFA9879=m -CONFIG_SND_SOC_TFA989X=m -CONFIG_SND_SOC_TLV320ADC3XXX=m -CONFIG_SND_SOC_TLV320AIC23=m -CONFIG_SND_SOC_TLV320AIC23_I2C=m -CONFIG_SND_SOC_TLV320AIC23_SPI=m -CONFIG_SND_SOC_TLV320AIC31XX=m -CONFIG_SND_SOC_TLV320AIC32X4=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_TLV320AIC32X4_SPI=m -CONFIG_SND_SOC_TLV320AIC3X=m -CONFIG_SND_SOC_TLV320AIC3X_I2C=m -CONFIG_SND_SOC_TLV320AIC3X_SPI=m -CONFIG_SND_SOC_TLV320ADCX140=m -CONFIG_SND_SOC_TS3A227E=m -CONFIG_SND_SOC_TSCS42XX=m -CONFIG_SND_SOC_TSCS454=m -CONFIG_SND_SOC_UDA1334=m -CONFIG_SND_SOC_WCD_CLASSH=m -CONFIG_SND_SOC_WCD9335=m -CONFIG_SND_SOC_WCD_MBHC=m -CONFIG_SND_SOC_WCD938X=m -CONFIG_SND_SOC_WCD938X_SDW=m -# CONFIG_SND_SOC_WCD939X_SDW is not set -CONFIG_SND_SOC_WM8510=m -CONFIG_SND_SOC_WM8523=m -CONFIG_SND_SOC_WM8524=m -CONFIG_SND_SOC_WM8580=m -CONFIG_SND_SOC_WM8711=m -CONFIG_SND_SOC_WM8728=m -CONFIG_SND_SOC_WM8731=m -CONFIG_SND_SOC_WM8731_I2C=m -CONFIG_SND_SOC_WM8731_SPI=m -CONFIG_SND_SOC_WM8737=m -CONFIG_SND_SOC_WM8741=m -CONFIG_SND_SOC_WM8750=m -CONFIG_SND_SOC_WM8753=m -CONFIG_SND_SOC_WM8770=m -CONFIG_SND_SOC_WM8776=m -CONFIG_SND_SOC_WM8782=m -CONFIG_SND_SOC_WM8804=m -CONFIG_SND_SOC_WM8804_I2C=m -CONFIG_SND_SOC_WM8804_SPI=m -CONFIG_SND_SOC_WM8903=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8940=m -CONFIG_SND_SOC_WM8960=m -# CONFIG_SND_SOC_WM8961 is not set -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8974=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WM8985=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_WSA883X=m -# CONFIG_SND_SOC_WSA884X is not set -CONFIG_SND_SOC_ZL38060=m -CONFIG_SND_SOC_MAX9759=m -CONFIG_SND_SOC_MT6351=m -CONFIG_SND_SOC_MT6358=m -CONFIG_SND_SOC_MT6660=m -CONFIG_SND_SOC_NAU8315=m -CONFIG_SND_SOC_NAU8540=m -CONFIG_SND_SOC_NAU8810=m -CONFIG_SND_SOC_NAU8821=m -CONFIG_SND_SOC_NAU8822=m -CONFIG_SND_SOC_NAU8824=m -CONFIG_SND_SOC_TPA6130A2=m -CONFIG_SND_SOC_LPASS_MACRO_COMMON=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SOC_LPASS_RX_MACRO=m -CONFIG_SND_SOC_LPASS_TX_MACRO=m -# end of CODEC drivers - -CONFIG_SND_SIMPLE_CARD_UTILS=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD2=m -CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m -CONFIG_SND_TEST_COMPONENT=m -CONFIG_SND_SYNTH_EMUX=m -CONFIG_SND_XEN_FRONTEND=m -CONFIG_SND_VIRTIO=m -CONFIG_AC97_BUS=m -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HIDRAW=y -CONFIG_UHID=m -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=m -CONFIG_HID_ACCUTOUCH=m -CONFIG_HID_ACRUX=m -CONFIG_HID_ACRUX_FF=y -CONFIG_HID_APPLE=m -CONFIG_HID_APPLEIR=m -CONFIG_HID_ASUS=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=m -CONFIG_HID_BETOP_FF=m -CONFIG_HID_BIGBEN_FF=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CORSAIR=m -CONFIG_HID_COUGAR=m -CONFIG_HID_MACALLY=m -CONFIG_HID_PRODIKEYS=m -CONFIG_HID_CMEDIA=m -CONFIG_HID_CP2112=m -CONFIG_HID_CREATIVE_SB0540=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EMS_FF=m -CONFIG_HID_ELAN=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -# CONFIG_HID_EVISION is not set -CONFIG_HID_EZKEY=m -CONFIG_HID_FT260=m -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_GLORIOUS=m -CONFIG_HID_HOLTEK=m -CONFIG_HOLTEK_FF=y -CONFIG_HID_VIVALDI_COMMON=m -CONFIG_HID_GOOGLE_HAMMER=m -# CONFIG_HID_GOOGLE_STADIA_FF is not set -CONFIG_HID_VIVALDI=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_VIEWSONIC=m -CONFIG_HID_VRC2=m -CONFIG_HID_XIAOMI=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_ITE=m -CONFIG_HID_JABRA=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LCPOWER=m -CONFIG_HID_LED=m -CONFIG_HID_LENOVO=m -# CONFIG_HID_LETSKETCH is not set -CONFIG_HID_LOGITECH=m -CONFIG_HID_LOGITECH_DJ=m -CONFIG_HID_LOGITECH_HIDPP=m -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_LOGIG940_FF=y -CONFIG_LOGIWHEELS_FF=y -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_MALTRON=m -CONFIG_HID_MAYFLASH=m -CONFIG_HID_MEGAWORLD_FF=m -CONFIG_HID_REDRAGON=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NINTENDO=m -# CONFIG_NINTENDO_FF is not set -CONFIG_HID_NTI=m -CONFIG_HID_NTRIG=m -# CONFIG_HID_NVIDIA_SHIELD is not set -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_PANTHERLORD_FF=y -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PICOLCD_CIR=y -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PXRC=m -# CONFIG_HID_RAZER is not set -CONFIG_HID_PRIMAX=m -CONFIG_HID_RETRODE=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SEMITEK=m -# CONFIG_HID_SIGMAMICRO is not set -CONFIG_HID_SONY=m -CONFIG_SONY_FF=y -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEAM=m -# CONFIG_STEAM_FF is not set -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_GREENASIA_FF=y -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_SMARTJOYPLUS_FF=y -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_TOPRE=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_THRUSTMASTER_FF=y -CONFIG_HID_UDRAW_PS3=m -CONFIG_HID_U2FZERO=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -# CONFIG_HID_WINWING is not set -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_ZEROPLUS_FF=y -CONFIG_HID_ZYDACRON=m -CONFIG_HID_SENSOR_HUB=m -CONFIG_HID_SENSOR_CUSTOM_SENSOR=m -CONFIG_HID_ALPS=m -# CONFIG_HID_MCP2200 is not set -CONFIG_HID_MCP2221=m -# CONFIG_HID_KUNIT_TEST is not set -# end of Special HID drivers - -# -# HID-BPF support -# -# end of HID-BPF support - -# -# USB HID support -# -CONFIG_USB_HID=y -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -# end of USB HID support - -CONFIG_I2C_HID=y -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_I2C_HID_OF_ELAN=m -CONFIG_I2C_HID_OF_GOODIX=m -CONFIG_I2C_HID_CORE=m -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -CONFIG_USB_LED_TRIG=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_CONN_GPIO=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB=y -CONFIG_USB_PCI=y -# CONFIG_USB_PCI_AMD is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -CONFIG_USB_OTG_FSM=m -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_AUTOSUSPEND_DELAY=2 -CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 -CONFIG_USB_MON=m - -# -# USB Host Controller Drivers -# -CONFIG_USB_C67X00_HCD=m -CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DBGCAP is not set -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PCI_RENESAS is not set -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y -CONFIG_USB_EHCI_FSL=m -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OXU210HP_HCD=m -CONFIG_USB_ISP116X_HCD=m -CONFIG_USB_MAX3421_HCD=m -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=m -CONFIG_USB_SL811_HCD=m -CONFIG_USB_SL811_HCD_ISO=y -CONFIG_USB_R8A66597_HCD=m -CONFIG_USB_HCD_BCMA=m -CONFIG_USB_HCD_SSB=m -CONFIG_USB_HCD_TEST_MODE=y -# CONFIG_USB_XEN_HCD is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_REALTEK_AUTOPM=y -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m - -# -# USB Imaging devices -# -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_VHCI_HC_PORTS=8 -CONFIG_USBIP_VHCI_NR_HCS=1 -CONFIG_USBIP_HOST=m -CONFIG_USBIP_VUDC=m -# CONFIG_USBIP_DEBUG is not set - -# -# USB dual-mode controller drivers -# -CONFIG_USB_CDNS_SUPPORT=m -CONFIG_USB_CDNS_HOST=y -CONFIG_USB_CDNS3=m -# CONFIG_USB_CDNS3_GADGET is not set -# CONFIG_USB_CDNS3_HOST is not set -CONFIG_USB_CDNS3_PCI_WRAP=m -CONFIG_USB_CDNSP_PCI=m -CONFIG_USB_CDNSP_GADGET=y -CONFIG_USB_CDNSP_HOST=y -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_DUAL_ROLE=y - -# -# Platform Glue Layer -# - -# -# MUSB DMA mode -# -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_ULPI=y -# CONFIG_USB_DWC3_HOST is not set -# CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_DUAL_ROLE=y - -# -# Platform Glue Driver Support -# -CONFIG_USB_DWC3_PCI=y -CONFIG_USB_DWC3_HAPS=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_DWC2=y -# CONFIG_USB_DWC2_HOST is not set - -# -# Gadget/Dual-role mode requires USB Gadget support to be enabled -# -# CONFIG_USB_DWC2_PERIPHERAL is not set -CONFIG_USB_DWC2_DUAL_ROLE=y -CONFIG_USB_DWC2_PCI=m -# CONFIG_USB_DWC2_DEBUG is not set -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_CHIPIDEA_PCI=y -CONFIG_USB_CHIPIDEA_MSM=y -CONFIG_USB_CHIPIDEA_NPCM=y -CONFIG_USB_CHIPIDEA_IMX=y -CONFIG_USB_CHIPIDEA_GENERIC=y -CONFIG_USB_CHIPIDEA_TEGRA=y -CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HCD=y -CONFIG_USB_ISP1761_UDC=y -# CONFIG_USB_ISP1760_HOST_ROLE is not set -# CONFIG_USB_ISP1760_GADGET_ROLE is not set -CONFIG_USB_ISP1760_DUAL_ROLE=y - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_F81232=m -CONFIG_USB_SERIAL_F8153X=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_METRO=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MXUPORT=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_WWAN=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_WISHBONE=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_XR=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_APPLE_MFI_FASTCHARGE=m -# CONFIG_USB_LJCA is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_EZUSB_FX2=m -CONFIG_USB_HUB_USB251XB=m -CONFIG_USB_HSIC_USB3503=y -CONFIG_USB_HSIC_USB4604=m -CONFIG_USB_LINK_LAYER_TEST=m -CONFIG_USB_CHAOSKEY=m -# CONFIG_USB_ONBOARD_DEV is not set -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m - -# -# USB Physical Layer drivers -# -CONFIG_USB_PHY=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_ISP1301=m -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_VIEWPORT=y -# end of USB Physical Layer drivers - -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 -CONFIG_U_SERIAL_CONSOLE=y - -# -# USB Peripheral Controller -# -CONFIG_USB_GR_UDC=m -CONFIG_USB_R8A66597=m -CONFIG_USB_PXA27X=m -CONFIG_USB_MV_UDC=m -CONFIG_USB_MV_U3D=m -CONFIG_USB_SNP_CORE=m -CONFIG_USB_SNP_UDC_PLAT=m -CONFIG_USB_M66592=m -CONFIG_USB_BDC_UDC=m -CONFIG_USB_AMD5536UDC=m -CONFIG_USB_NET2272=m -# CONFIG_USB_NET2272_DMA is not set -CONFIG_USB_NET2280=m -CONFIG_USB_GOKU=m -CONFIG_USB_EG20T=m -CONFIG_USB_GADGET_XILINX=m -CONFIG_USB_MAX3420_UDC=m -# CONFIG_USB_CDNS2_UDC is not set -CONFIG_USB_DUMMY_HCD=m -# end of USB Peripheral Controller - -CONFIG_USB_LIBCOMPOSITE=m -CONFIG_USB_F_ACM=m -CONFIG_USB_F_SS_LB=m -CONFIG_USB_U_SERIAL=m -CONFIG_USB_U_ETHER=m -CONFIG_USB_U_AUDIO=m -CONFIG_USB_F_SERIAL=m -CONFIG_USB_F_OBEX=m -CONFIG_USB_F_NCM=m -CONFIG_USB_F_ECM=m -CONFIG_USB_F_PHONET=m -CONFIG_USB_F_EEM=m -CONFIG_USB_F_SUBSET=m -CONFIG_USB_F_RNDIS=m -CONFIG_USB_F_MASS_STORAGE=m -CONFIG_USB_F_FS=m -CONFIG_USB_F_UAC1=m -CONFIG_USB_F_UAC1_LEGACY=m -CONFIG_USB_F_UAC2=m -CONFIG_USB_F_UVC=m -CONFIG_USB_F_MIDI=m -CONFIG_USB_F_HID=m -CONFIG_USB_F_PRINTER=m -CONFIG_USB_F_TCM=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -# CONFIG_USB_CONFIGFS_PHONET is not set -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -# CONFIG_USB_CONFIGFS_F_MIDI2 is not set -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_CONFIGFS_F_TCM=y - -# -# USB Gadget precomposed configurations -# -CONFIG_USB_ZERO=m -# CONFIG_USB_ZERO_HNPTEST is not set -CONFIG_USB_AUDIO=m -CONFIG_GADGET_UAC1=y -# CONFIG_GADGET_UAC1_LEGACY is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_ETH_EEM=y -CONFIG_USB_G_NCM=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_FUNCTIONFS_ETH=y -CONFIG_USB_FUNCTIONFS_RNDIS=y -CONFIG_USB_FUNCTIONFS_GENERIC=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_GADGET_TARGET=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_NOKIA=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_MULTI=m -CONFIG_USB_G_MULTI_RNDIS=y -CONFIG_USB_G_MULTI_CDC=y -CONFIG_USB_G_HID=m -# CONFIG_USB_G_DBGP is not set -CONFIG_USB_G_WEBCAM=m -CONFIG_USB_RAW_GADGET=m -# end of USB Gadget precomposed configurations - -CONFIG_TYPEC=y -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_RT1711H=m -CONFIG_TYPEC_TCPCI_MT6370=m -CONFIG_TYPEC_TCPCI_MAXIM=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_UCSI=m -CONFIG_UCSI_CCG=m -CONFIG_UCSI_ACPI=m -CONFIG_UCSI_STM32G0=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_TYPEC_ANX7411=m -CONFIG_TYPEC_RT1719=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_STUSB160X=m -CONFIG_TYPEC_WUSB3801=m - -# -# USB Type-C Multiplexer/DeMultiplexer Switch support -# -CONFIG_TYPEC_MUX_FSA4480=m -# CONFIG_TYPEC_MUX_GPIO_SBU is not set -CONFIG_TYPEC_MUX_PI3USB30532=m -# CONFIG_TYPEC_MUX_IT5205 is not set -# CONFIG_TYPEC_MUX_NB7VPQ904M is not set -# CONFIG_TYPEC_MUX_PTN36502 is not set -# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set -# end of USB Type-C Multiplexer/DeMultiplexer Switch support - -# -# USB Type-C Alternate Mode drivers -# -CONFIG_TYPEC_DP_ALTMODE=m -CONFIG_TYPEC_NVIDIA_ALTMODE=m -# end of USB Type-C Alternate Mode drivers - -CONFIG_USB_ROLE_SWITCH=y -CONFIG_MMC=y -CONFIG_PWRSEQ_EMMC=y -CONFIG_PWRSEQ_SD8787=m -CONFIG_PWRSEQ_SIMPLE=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_SDIO_UART=m -CONFIG_MMC_TEST=y - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_STM32_SDMMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_AT91=m -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_SDHCI_MILBEAUT=m -CONFIG_MMC_ALCOR=m -CONFIG_MMC_TIFM_SD=m -CONFIG_MMC_SPI=y -# CONFIG_MMC_CB710 is not set -CONFIG_MMC_VIA_SDMMC=m -CONFIG_MMC_DW=y -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_BLUEFIELD=m -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -# CONFIG_MMC_DW_HI3798MV200 is not set -CONFIG_MMC_DW_K3=y -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -CONFIG_MMC_USDHI6ROL0=m -CONFIG_MMC_REALTEK_PCI=m -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_CQHCI=y -CONFIG_MMC_HSQ=m -# CONFIG_MMC_TOSHIBA_PCI is not set -CONFIG_MMC_MTK=m -CONFIG_MMC_SDHCI_XENON=y -# CONFIG_MMC_LITEX is not set -CONFIG_SCSI_UFSHCD=y -# CONFIG_SCSI_UFS_BSG is not set -CONFIG_SCSI_UFS_HWMON=y -CONFIG_SCSI_UFSHCD_PCI=m -# CONFIG_SCSI_UFS_DWC_TC_PCI is not set -CONFIG_SCSI_UFSHCD_PLATFORM=y -# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set -# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_CLASS_MULTICOLOR=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set - -# -# LED drivers -# -CONFIG_LEDS_AN30259A=m -# CONFIG_LEDS_AW200XX is not set -# CONFIG_LEDS_AW2013 is not set -# CONFIG_LEDS_BCM6328 is not set -# CONFIG_LEDS_BCM6358 is not set -CONFIG_LEDS_CR0014114=m -CONFIG_LEDS_EL15203000=m -# CONFIG_LEDS_LM3530 is not set -CONFIG_LEDS_LM3532=m -# CONFIG_LEDS_LM3642 is not set -CONFIG_LEDS_LM3692X=m -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP8860 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_PCA995X is not set -# CONFIG_LEDS_DAC124S085 is not set -CONFIG_LEDS_PWM=m -CONFIG_LEDS_REGULATOR=m -# CONFIG_LEDS_BD2606MVV is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_IS31FL319X is not set -# CONFIG_LEDS_IS31FL32XX is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_MLXREG=m -CONFIG_LEDS_USER=y -CONFIG_LEDS_SPI_BYTE=m -CONFIG_LEDS_TI_LMU_COMMON=m -CONFIG_LEDS_LM3697=m - -# -# Flash and Torch LED drivers -# -# CONFIG_LEDS_AAT1290 is not set -# CONFIG_LEDS_AS3645A is not set -# CONFIG_LEDS_KTD2692 is not set -# CONFIG_LEDS_LM3601X is not set -# CONFIG_LEDS_MT6370_FLASH is not set -# CONFIG_LEDS_RT4505 is not set -# CONFIG_LEDS_RT8515 is not set -# CONFIG_LEDS_SGM3140 is not set - -# -# RGB LED drivers -# - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_ONESHOT=m -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_MTD=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ACTIVITY=y -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y - -# -# iptables trigger is under Netfilter config (LED target) -# -CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=m -CONFIG_LEDS_TRIGGER_PATTERN=m -CONFIG_LEDS_TRIGGER_TTY=m - -# -# Simple LED drivers -# -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_SUPPORT=y -CONFIG_EDAC=y -CONFIG_EDAC_LEGACY_SYSFS=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_GHES=y -# CONFIG_EDAC_THUNDERX is not set -# CONFIG_EDAC_XGENE is not set -CONFIG_EDAC_DMC520=m -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_LIB_KUNIT_TEST=m -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -CONFIG_RTC_DRV_HYM8563=y -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_MAX31335 is not set -# CONFIG_RTC_DRV_NCT3018Y is not set -CONFIG_RTC_DRV_RK808=m -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_ISL12026 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8111 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T93 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1302 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6916 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_MCP795 is not set -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set -# CONFIG_RTC_DRV_RX6110 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_EFI is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -CONFIG_RTC_DRV_OPTEE=m -# CONFIG_RTC_DRV_ZYNQMP is not set -# CONFIG_RTC_DRV_CROS_EC is not set -# CONFIG_RTC_DRV_NTXEC is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_PL030 is not set -# CONFIG_RTC_DRV_PL031 is not set -# CONFIG_RTC_DRV_CADENCE is not set -# CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_R7301 is not set - -# -# HID Sensor RTC drivers -# -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_GOLDFISH is not set -CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DMA_ACPI=y -CONFIG_DMA_OF=y -CONFIG_ALTERA_MSGDMA=m -# CONFIG_AMBA_PL08X is not set -CONFIG_BCM_SBA_RAID=m -CONFIG_DW_AXI_DMAC=m -CONFIG_FSL_EDMA=y -CONFIG_FSL_QDMA=m -# CONFIG_INTEL_IDMA64 is not set -CONFIG_MV_XOR_V2=y -CONFIG_PL330_DMA=y -CONFIG_PLX_DMA=m -# CONFIG_XILINX_DMA is not set -# CONFIG_XILINX_XDMA is not set -# CONFIG_XILINX_ZYNQMP_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_HIDMA=y -CONFIG_DW_DMAC_CORE=m -CONFIG_DW_DMAC=m -CONFIG_DW_DMAC_PCI=m -CONFIG_DW_EDMA=m -CONFIG_DW_EDMA_PCIE=m -CONFIG_SF_PDMA=m - -# -# DMA Clients -# -CONFIG_ASYNC_TX_DMA=y -# CONFIG_DMATEST is not set -CONFIG_DMA_ENGINE_RAID=y - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -CONFIG_UDMABUF=y -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_DEBUG is not set -CONFIG_DMABUF_SELFTESTS=m -CONFIG_DMABUF_HEAPS=y -CONFIG_DMABUF_SYSFS_STATS=y -CONFIG_DMABUF_HEAPS_SYSTEM=y -CONFIG_DMABUF_HEAPS_CMA=y -# end of DMABUF options - -CONFIG_UIO=m -CONFIG_UIO_CIF=m -# CONFIG_UIO_PDRV_GENIRQ is not set -# CONFIG_UIO_DMEM_GENIRQ is not set -CONFIG_UIO_AEC=m -CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m -# CONFIG_UIO_NETX is not set -# CONFIG_UIO_MF624 is not set -CONFIG_VFIO=y -CONFIG_VFIO_GROUP=y -CONFIG_VFIO_CONTAINER=y -CONFIG_VFIO_IOMMU_TYPE1=y -# CONFIG_VFIO_NOIOMMU is not set -CONFIG_VFIO_VIRQFD=y -# CONFIG_VFIO_DEBUGFS is not set - -# -# VFIO support for PCI devices -# -CONFIG_VFIO_PCI_CORE=y -CONFIG_VFIO_PCI_MMAP=y -CONFIG_VFIO_PCI_INTX=y -CONFIG_VFIO_PCI=y -CONFIG_MLX5_VFIO_PCI=m -# CONFIG_HISI_ACC_VFIO_PCI is not set -# CONFIG_NVGRACE_GPU_VFIO_PCI is not set -# end of VFIO support for PCI devices - -# -# VFIO support for platform devices -# -# CONFIG_VFIO_PLATFORM is not set -# CONFIG_VFIO_AMBA is not set -# end of VFIO support for platform devices - -CONFIG_IRQ_BYPASS_MANAGER=y -CONFIG_VIRT_DRIVERS=y -CONFIG_VMGENID=y -CONFIG_NITRO_ENCLAVES=m -CONFIG_VIRTIO_ANCHOR=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_PCI_LIB=y -CONFIG_VIRTIO_PCI_LIB_LEGACY=y -CONFIG_VIRTIO_MENU=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_VIRTIO_VDPA=m -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_INPUT=m -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_DMA_SHARED_BUFFER=m -# CONFIG_VIRTIO_DEBUG is not set -CONFIG_VDPA=m -CONFIG_VDPA_SIM=m -CONFIG_VDPA_SIM_NET=m -CONFIG_VDPA_SIM_BLOCK=m -CONFIG_VDPA_USER=m -CONFIG_IFCVF=m -CONFIG_MLX5_VDPA=y -CONFIG_MLX5_VDPA_NET=m -# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set -CONFIG_VP_VDPA=m -# CONFIG_SNET_VDPA is not set -CONFIG_VHOST_IOTLB=m -CONFIG_VHOST_RING=m -CONFIG_VHOST_TASK=y -CONFIG_VHOST=m -CONFIG_VHOST_MENU=y -CONFIG_VHOST_NET=m -CONFIG_VHOST_SCSI=m -# CONFIG_VHOST_VSOCK is not set -CONFIG_VHOST_VDPA=m -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set - -# -# Microsoft Hyper-V guest support -# -# CONFIG_HYPERV is not set -# end of Microsoft Hyper-V guest support - -# -# Xen driver support -# -CONFIG_XEN_BALLOON=y -CONFIG_XEN_SCRUB_PAGES_DEFAULT=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_BACKEND=y -CONFIG_XENFS=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_SYS_HYPERVISOR=y -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -# CONFIG_XEN_GRANT_DMA_ALLOC is not set -CONFIG_SWIOTLB_XEN=y -CONFIG_XEN_PCI_STUB=y -CONFIG_XEN_PCIDEV_STUB=m -# CONFIG_XEN_PVCALLS_FRONTEND is not set -# CONFIG_XEN_PVCALLS_BACKEND is not set -CONFIG_XEN_SCSI_BACKEND=m -CONFIG_XEN_PRIVCMD=y -CONFIG_XEN_EFI=y -CONFIG_XEN_AUTO_XLATE=y -CONFIG_XEN_FRONT_PGDIR_SHBUF=m -# CONFIG_XEN_VIRTIO is not set -# end of Xen driver support - -# CONFIG_GREYBUS is not set -# CONFIG_COMEDI is not set -CONFIG_STAGING=y -CONFIG_RTLLIB=m -CONFIG_RTLLIB_CRYPTO_CCMP=m -CONFIG_RTLLIB_CRYPTO_TKIP=m -CONFIG_RTLLIB_CRYPTO_WEP=m -CONFIG_RTL8192E=m -CONFIG_RTL8723BS=m -CONFIG_R8712U=m -CONFIG_RTS5208=m -CONFIG_VT6655=m -CONFIG_VT6656=m - -# -# IIO staging drivers -# - -# -# Accelerometers -# -# CONFIG_ADIS16203 is not set -# CONFIG_ADIS16240 is not set -# end of Accelerometers - -# -# Analog to digital converters -# -# CONFIG_AD7816 is not set -# end of Analog to digital converters - -# -# Analog digital bi-direction converters -# -# CONFIG_ADT7316 is not set -# end of Analog digital bi-direction converters - -# -# Direct Digital Synthesis -# -CONFIG_AD9832=m -CONFIG_AD9834=m -# end of Direct Digital Synthesis - -# -# Network Analyzer, Impedance Converters -# -# CONFIG_AD5933 is not set -# end of Network Analyzer, Impedance Converters -# end of IIO staging drivers - -CONFIG_FB_SM750=m -CONFIG_STAGING_MEDIA=y -CONFIG_DVB_AV7110_IR=y -CONFIG_DVB_AV7110=m -CONFIG_DVB_AV7110_OSD=y -# CONFIG_DVB_BUDGET_PATCH is not set -CONFIG_DVB_SP8870=m -# CONFIG_VIDEO_MAX96712 is not set -CONFIG_VIDEO_ROCKCHIP_VDEC=m -CONFIG_VIDEO_ROCKCHIP_VDEC2=m - -# -# StarFive media platform drivers -# -CONFIG_STAGING_MEDIA_DEPRECATED=y - -# -# Atmel media platform drivers -# -# CONFIG_LTE_GDM724X is not set -CONFIG_FB_TFT=m -CONFIG_FB_TFT_AGM1264K_FL=m -CONFIG_FB_TFT_BD663474=m -CONFIG_FB_TFT_HX8340BN=m -CONFIG_FB_TFT_HX8347D=m -CONFIG_FB_TFT_HX8353D=m -CONFIG_FB_TFT_HX8357D=m -CONFIG_FB_TFT_ILI9163=m -CONFIG_FB_TFT_ILI9320=m -CONFIG_FB_TFT_ILI9325=m -CONFIG_FB_TFT_ILI9340=m -CONFIG_FB_TFT_ILI9341=m -CONFIG_FB_TFT_ILI9481=m -CONFIG_FB_TFT_ILI9486=m -CONFIG_FB_TFT_PCD8544=m -CONFIG_FB_TFT_RA8875=m -CONFIG_FB_TFT_S6D02A1=m -CONFIG_FB_TFT_S6D1121=m -CONFIG_FB_TFT_SEPS525=m -CONFIG_FB_TFT_SH1106=m -CONFIG_FB_TFT_SSD1289=m -CONFIG_FB_TFT_SSD1305=m -CONFIG_FB_TFT_SSD1306=m -CONFIG_FB_TFT_SSD1331=m -CONFIG_FB_TFT_SSD1351=m -CONFIG_FB_TFT_ST7735R=m -CONFIG_FB_TFT_ST7789V=m -CONFIG_FB_TFT_TINYLCD=m -CONFIG_FB_TFT_TLS8204=m -CONFIG_FB_TFT_UC1611=m -CONFIG_FB_TFT_UC1701=m -CONFIG_FB_TFT_UPD161704=m -# CONFIG_MOST_COMPONENTS is not set -# CONFIG_KS7010 is not set -# CONFIG_XIL_AXIS_FIFO is not set -CONFIG_FIELDBUS_DEV=m -CONFIG_HMS_ANYBUSS_BUS=m -# CONFIG_ARCX_ANYBUS_CONTROLLER is not set -# CONFIG_HMS_PROFINET is not set -# CONFIG_VME_BUS is not set -# CONFIG_RTL8723CS is not set -# CONFIG_GOLDFISH is not set -CONFIG_CHROME_PLATFORMS=y -CONFIG_CHROMEOS_ACPI=m -# CONFIG_CHROMEOS_TBMC is not set -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -# CONFIG_CROS_EC_RPMSG is not set -CONFIG_CROS_EC_SPI=y -# CONFIG_CROS_EC_UART is not set -CONFIG_CROS_EC_PROTO=y -# CONFIG_CROS_KBD_LED_BACKLIGHT is not set -CONFIG_CROS_EC_CHARDEV=y -CONFIG_CROS_EC_LIGHTBAR=y -CONFIG_CROS_EC_VBC=y -CONFIG_CROS_EC_DEBUGFS=y -CONFIG_CROS_EC_SENSORHUB=y -CONFIG_CROS_EC_SYSFS=y -CONFIG_CROS_EC_TYPEC=m -# CONFIG_CROS_HPS_I2C is not set -CONFIG_CROS_USBPD_NOTIFY=y -# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set -CONFIG_CROS_TYPEC_SWITCH=m -# CONFIG_CROS_KUNIT_EC_PROTO_TEST is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_GPE is not set -# CONFIG_SURFACE_HOTPLUG is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -# CONFIG_SURFACE_AGGREGATOR is not set -CONFIG_ARM64_PLATFORM_DEVICES=y -# CONFIG_EC_ACER_ASPIRE1 is not set -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y - -# -# Clock driver for ARM Reference designs -# -# CONFIG_CLK_ICST is not set -# CONFIG_CLK_SP810 is not set -# CONFIG_CLK_VEXPRESS_OSC is not set -# end of Clock driver for ARM Reference designs - -# CONFIG_LMK04832 is not set -# CONFIG_COMMON_CLK_MAX9485 is not set -CONFIG_COMMON_CLK_RK808=m -CONFIG_COMMON_CLK_SCMI=y -# CONFIG_COMMON_CLK_SCPI is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI514 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_SI570 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CDCE925 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_COMMON_CLK_AXI_CLKGEN is not set -# CONFIG_COMMON_CLK_XGENE is not set -CONFIG_COMMON_CLK_PWM=y -# CONFIG_COMMON_CLK_RS9_PCIE is not set -# CONFIG_COMMON_CLK_SI521XX is not set -# CONFIG_COMMON_CLK_VC3 is not set -# CONFIG_COMMON_CLK_VC5 is not set -# CONFIG_COMMON_CLK_VC7 is not set -# CONFIG_COMMON_CLK_FIXED_MMIO is not set -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y -CONFIG_CLK_RK3588=y -# CONFIG_XILINX_VCU is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set -# CONFIG_CLK_KUNIT_TEST is not set -# CONFIG_CLK_GATE_KUNIT_TEST is not set -# CONFIG_CLK_FD_KUNIT_TEST is not set -# CONFIG_HWSPINLOCK is not set - -# -# Clock Source drivers -# -CONFIG_TIMER_OF=y -CONFIG_TIMER_ACPI=y -CONFIG_TIMER_PROBE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_FSL_ERRATUM_A008585=y -CONFIG_HISILICON_ERRATUM_161010101=y -CONFIG_ARM64_ERRATUM_858921=y -# end of Clock Source drivers - -CONFIG_MAILBOX=y -CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=m -# CONFIG_ARM_MHU_V3 is not set -CONFIG_PLATFORM_MHU=y -# CONFIG_PL320_MBOX is not set -CONFIG_ROCKCHIP_MBOX=y -CONFIG_PCC=y -# CONFIG_ALTERA_MBOX is not set -# CONFIG_MAILBOX_TEST is not set -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_API=y -CONFIG_IOMMUFD_DRIVER=y -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_DART is not set -# end of Generic IOMMU Pagetable Support - -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_OF_IOMMU=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_SVA=y -CONFIG_IOMMU_IOPF=y -# CONFIG_IOMMUFD is not set -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ARM_SMMU=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -CONFIG_ARM_SMMU_V3=y -CONFIG_ARM_SMMU_V3_SVA=y -# CONFIG_ARM_SMMU_V3_KUNIT_TEST is not set -CONFIG_VIRTIO_IOMMU=m - -# -# Remoteproc drivers -# -CONFIG_REMOTEPROC=y -# CONFIG_REMOTEPROC_CDEV is not set -# end of Remoteproc drivers - -# -# Rpmsg drivers -# -CONFIG_RPMSG=y -# CONFIG_RPMSG_CHAR is not set -# CONFIG_RPMSG_CTRL is not set -CONFIG_RPMSG_NS=m -CONFIG_RPMSG_QCOM_GLINK=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -# CONFIG_RPMSG_VIRTIO is not set -# end of Rpmsg drivers - -CONFIG_SOUNDWIRE=m - -# -# SoundWire Devices -# -# CONFIG_SOUNDWIRE_AMD is not set -# CONFIG_SOUNDWIRE_INTEL is not set -CONFIG_SOUNDWIRE_QCOM=m - -# -# SOC (System On Chip) specific Drivers -# - -# -# Amlogic SoC drivers -# -# end of Amlogic SoC drivers - -# -# Broadcom SoC drivers -# -# end of Broadcom SoC drivers - -# -# NXP/Freescale QorIQ SoC drivers -# -# CONFIG_QUICC_ENGINE is not set -# CONFIG_FSL_RCPM is not set -# end of NXP/Freescale QorIQ SoC drivers - -# -# fujitsu SoC drivers -# -# CONFIG_A64FX_DIAG is not set -# end of fujitsu SoC drivers - -# -# i.MX SoC drivers -# -# end of i.MX SoC drivers - -# -# Enable LiteX SoC Builder specific drivers -# -CONFIG_LITEX=y -CONFIG_LITEX_SOC_CONTROLLER=m -# end of Enable LiteX SoC Builder specific drivers - -# CONFIG_WPCM450_SOC is not set - -# -# Qualcomm SoC drivers -# -# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set -# CONFIG_QCOM_PMIC_GLINK is not set -CONFIG_QCOM_QMI_HELPERS=m -# CONFIG_QCOM_PBS is not set -# end of Qualcomm SoC drivers - -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_SOC_TI=y - -# -# Xilinx SoC drivers -# -# end of Xilinx SoC drivers -# end of SOC (System On Chip) specific Drivers - -# -# PM Domains -# - -# -# Amlogic PM Domains -# -# end of Amlogic PM Domains - -CONFIG_ARM_SCMI_PERF_DOMAIN=y -CONFIG_ARM_SCMI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y - -# -# Broadcom PM Domains -# -# end of Broadcom PM Domains - -# -# i.MX PM Domains -# -# end of i.MX PM Domains - -# -# Qualcomm PM Domains -# -# end of Qualcomm PM Domains - -CONFIG_ROCKCHIP_PM_DOMAINS=y -# end of PM Domains - -CONFIG_PM_DEVFREQ=y - -# -# DEVFREQ Governors -# -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=m -CONFIG_DEVFREQ_GOV_POWERSAVE=m -CONFIG_DEVFREQ_GOV_USERSPACE=m -CONFIG_DEVFREQ_GOV_PASSIVE=m - -# -# DEVFREQ Drivers -# -CONFIG_ARM_RK3399_DMC_DEVFREQ=y -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y -CONFIG_EXTCON=y - -# -# Extcon Device Drivers -# -CONFIG_EXTCON_ADC_JACK=m -# CONFIG_EXTCON_FSA9480 is not set -CONFIG_EXTCON_GPIO=y -# CONFIG_EXTCON_MAX3355 is not set -CONFIG_EXTCON_PTN5150=m -# CONFIG_EXTCON_RT8973A is not set -# CONFIG_EXTCON_SM5502 is not set -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_EXTCON_USBC_TUSB320=m -CONFIG_MEMORY=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_BUFFER_CB=m -# CONFIG_IIO_BUFFER_DMA is not set -# CONFIG_IIO_BUFFER_DMAENGINE is not set -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_IIO_CONFIGFS=m -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_IIO_TRIGGERED_EVENT=m - -# -# Accelerometers -# -CONFIG_ADIS16201=m -CONFIG_ADIS16209=m -CONFIG_ADXL313=m -CONFIG_ADXL313_I2C=m -CONFIG_ADXL313_SPI=m -CONFIG_ADXL345=m -CONFIG_ADXL345_I2C=m -CONFIG_ADXL345_SPI=m -CONFIG_ADXL355=m -CONFIG_ADXL355_I2C=m -CONFIG_ADXL355_SPI=m -CONFIG_ADXL367=m -CONFIG_ADXL367_SPI=m -CONFIG_ADXL367_I2C=m -CONFIG_ADXL372=m -CONFIG_ADXL372_SPI=m -CONFIG_ADXL372_I2C=m -CONFIG_BMA180=m -CONFIG_BMA220=m -CONFIG_BMA400=m -CONFIG_BMA400_I2C=m -CONFIG_BMA400_SPI=m -CONFIG_BMC150_ACCEL=m -CONFIG_BMC150_ACCEL_I2C=m -CONFIG_BMC150_ACCEL_SPI=m -CONFIG_BMI088_ACCEL=m -CONFIG_BMI088_ACCEL_I2C=m -CONFIG_BMI088_ACCEL_SPI=m -CONFIG_DA280=m -CONFIG_DA311=m -CONFIG_DMARD06=m -CONFIG_DMARD09=m -CONFIG_DMARD10=m -CONFIG_FXLS8962AF=m -CONFIG_FXLS8962AF_I2C=m -CONFIG_FXLS8962AF_SPI=m -CONFIG_HID_SENSOR_ACCEL_3D=m -CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m -CONFIG_IIO_ST_ACCEL_3AXIS=m -CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m -CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m -# CONFIG_IIO_KX022A_SPI is not set -# CONFIG_IIO_KX022A_I2C is not set -CONFIG_KXSD9=m -CONFIG_KXSD9_SPI=m -CONFIG_KXSD9_I2C=m -CONFIG_KXCJK1013=m -CONFIG_MC3230=m -CONFIG_MMA7455=m -CONFIG_MMA7455_I2C=m -CONFIG_MMA7455_SPI=m -CONFIG_MMA7660=m -CONFIG_MMA8452=m -CONFIG_MMA9551_CORE=m -CONFIG_MMA9551=m -CONFIG_MMA9553=m -# CONFIG_MSA311 is not set -CONFIG_MXC4005=m -CONFIG_MXC6255=m -CONFIG_SCA3000=m -CONFIG_SCA3300=m -CONFIG_STK8312=m -CONFIG_STK8BA50=m -# end of Accelerometers - -# -# Analog to digital converters -# -CONFIG_AD_SIGMA_DELTA=m -# CONFIG_AD4130 is not set -CONFIG_AD7091R=m -CONFIG_AD7091R5=m -# CONFIG_AD7091R8 is not set -CONFIG_AD7124=m -# CONFIG_AD7173 is not set -# CONFIG_AD7192 is not set -CONFIG_AD7266=m -# CONFIG_AD7280 is not set -CONFIG_AD7291=m -CONFIG_AD7292=m -CONFIG_AD7298=m -CONFIG_AD7476=m -CONFIG_AD7606=m -CONFIG_AD7606_IFACE_PARALLEL=m -CONFIG_AD7606_IFACE_SPI=m -CONFIG_AD7766=m -CONFIG_AD7768_1=m -# CONFIG_AD7780 is not set -CONFIG_AD7791=m -CONFIG_AD7793=m -CONFIG_AD7887=m -CONFIG_AD7923=m -# CONFIG_AD7944 is not set -CONFIG_AD7949=m -CONFIG_AD799X=m -# CONFIG_AD9467 is not set -# CONFIG_ADI_AXI_ADC is not set -# CONFIG_CC10001_ADC is not set -# CONFIG_ENVELOPE_DETECTOR is not set -# CONFIG_HI8435 is not set -# CONFIG_HX711 is not set -# CONFIG_INA2XX_ADC is not set -# CONFIG_LTC2309 is not set -# CONFIG_LTC2471 is not set -# CONFIG_LTC2485 is not set -CONFIG_LTC2496=m -# CONFIG_LTC2497 is not set -# CONFIG_MAX1027 is not set -# CONFIG_MAX11100 is not set -# CONFIG_MAX1118 is not set -CONFIG_MAX11205=m -# CONFIG_MAX11410 is not set -# CONFIG_MAX1241 is not set -CONFIG_MAX1363=m -# CONFIG_MAX34408 is not set -CONFIG_MAX9611=m -CONFIG_MCP320X=m -CONFIG_MCP3422=m -# CONFIG_MCP3564 is not set -CONFIG_MCP3911=m -# CONFIG_MEDIATEK_MT6370_ADC is not set -# CONFIG_NAU7802 is not set -# CONFIG_PAC1934 is not set -# CONFIG_QCOM_SPMI_IADC is not set -# CONFIG_QCOM_SPMI_VADC is not set -# CONFIG_QCOM_SPMI_ADC5 is not set -CONFIG_ROCKCHIP_SARADC=y -CONFIG_RICHTEK_RTQ6056=m -# CONFIG_SD_ADC_MODULATOR is not set -CONFIG_TI_ADC081C=m -CONFIG_TI_ADC0832=m -CONFIG_TI_ADC084S021=m -CONFIG_TI_ADC12138=m -CONFIG_TI_ADC108S102=m -CONFIG_TI_ADC128S052=m -CONFIG_TI_ADC161S626=m -CONFIG_TI_ADS1015=m -# CONFIG_TI_ADS7924 is not set -# CONFIG_TI_ADS1100 is not set -# CONFIG_TI_ADS1298 is not set -CONFIG_TI_ADS7950=m -CONFIG_TI_ADS8344=m -CONFIG_TI_ADS8688=m -CONFIG_TI_ADS124S08=m -CONFIG_TI_ADS131E08=m -# CONFIG_TI_LMP92064 is not set -# CONFIG_TI_TLC4541 is not set -CONFIG_TI_TSC2046=m -# CONFIG_VF610_ADC is not set -CONFIG_XILINX_XADC=m -# end of Analog to digital converters - -# -# Analog to digital and digital to analog converters -# -# CONFIG_AD74115 is not set -# CONFIG_AD74413R is not set -# end of Analog to digital and digital to analog converters - -# -# Analog Front Ends -# -# CONFIG_IIO_RESCALE is not set -# end of Analog Front Ends - -# -# Amplifiers -# -# CONFIG_AD8366 is not set -# CONFIG_ADA4250 is not set -CONFIG_HMC425=m -# end of Amplifiers - -# -# Capacitance to digital converters -# -# CONFIG_AD7150 is not set -# CONFIG_AD7746 is not set -# end of Capacitance to digital converters - -# -# Chemical Sensors -# -# CONFIG_AOSONG_AGS02MA is not set -# CONFIG_ATLAS_PH_SENSOR is not set -# CONFIG_ATLAS_EZO_SENSOR is not set -CONFIG_BME680=m -CONFIG_BME680_I2C=m -CONFIG_BME680_SPI=m -# CONFIG_CCS811 is not set -# CONFIG_IAQCORE is not set -CONFIG_PMS7003=m -# CONFIG_SCD30_CORE is not set -CONFIG_SCD4X=m -CONFIG_SENSIRION_SGP30=m -CONFIG_SENSIRION_SGP40=m -CONFIG_SPS30=m -CONFIG_SPS30_I2C=m -CONFIG_SPS30_SERIAL=m -CONFIG_SENSEAIR_SUNRISE_CO2=m -# CONFIG_VZ89X is not set -# end of Chemical Sensors - -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -# CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE is not set - -# -# Hid Sensor IIO Common -# -CONFIG_HID_SENSOR_IIO_COMMON=m -CONFIG_HID_SENSOR_IIO_TRIGGER=m -# end of Hid Sensor IIO Common - -CONFIG_IIO_MS_SENSORS_I2C=m - -# -# IIO SCMI Sensors -# -CONFIG_IIO_SCMI=m -# end of IIO SCMI Sensors - -# -# SSP Sensor Common -# -# CONFIG_IIO_SSP_SENSORHUB is not set -# end of SSP Sensor Common - -CONFIG_IIO_ST_SENSORS_I2C=m -CONFIG_IIO_ST_SENSORS_SPI=m -CONFIG_IIO_ST_SENSORS_CORE=m - -# -# Digital to analog converters -# -# CONFIG_AD3552R is not set -# CONFIG_AD5064 is not set -# CONFIG_AD5360 is not set -# CONFIG_AD5380 is not set -# CONFIG_AD5421 is not set -# CONFIG_AD5446 is not set -# CONFIG_AD5449 is not set -# CONFIG_AD5592R is not set -# CONFIG_AD5593R is not set -# CONFIG_AD5504 is not set -# CONFIG_AD5624R_SPI is not set -# CONFIG_AD9739A is not set -# CONFIG_ADI_AXI_DAC is not set -# CONFIG_LTC2688 is not set -CONFIG_AD5686=m -CONFIG_AD5686_SPI=m -CONFIG_AD5696_I2C=m -# CONFIG_AD5755 is not set -CONFIG_AD5758=m -# CONFIG_AD5761 is not set -# CONFIG_AD5764 is not set -CONFIG_AD5766=m -CONFIG_AD5770R=m -# CONFIG_AD5791 is not set -# CONFIG_AD7293 is not set -# CONFIG_AD7303 is not set -# CONFIG_AD8801 is not set -# CONFIG_DPOT_DAC is not set -# CONFIG_DS4424 is not set -CONFIG_LTC1660=m -# CONFIG_LTC2632 is not set -# CONFIG_M62332 is not set -# CONFIG_MAX517 is not set -# CONFIG_MAX5522 is not set -# CONFIG_MAX5821 is not set -# CONFIG_MCP4725 is not set -# CONFIG_MCP4728 is not set -# CONFIG_MCP4821 is not set -# CONFIG_MCP4922 is not set -# CONFIG_TI_DAC082S085 is not set -CONFIG_TI_DAC5571=m -CONFIG_TI_DAC7311=m -CONFIG_TI_DAC7612=m -# CONFIG_VF610_DAC is not set -# end of Digital to analog converters - -# -# IIO dummy driver -# -CONFIG_IIO_SIMPLE_DUMMY=m -# CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set -# CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set -# end of IIO dummy driver - -# -# Filters -# -# CONFIG_ADMV8818 is not set -# end of Filters - -# -# Frequency Synthesizers DDS/PLL -# - -# -# Clock Generator/Distribution -# -CONFIG_AD9523=m -# end of Clock Generator/Distribution - -# -# Phase-Locked Loop (PLL) frequency synthesizers -# -# CONFIG_ADF4350 is not set -CONFIG_ADF4371=m -# CONFIG_ADF4377 is not set -# CONFIG_ADMFM2000 is not set -# CONFIG_ADMV1013 is not set -# CONFIG_ADMV1014 is not set -# CONFIG_ADMV4420 is not set -CONFIG_ADRF6780=m -# end of Phase-Locked Loop (PLL) frequency synthesizers -# end of Frequency Synthesizers DDS/PLL - -# -# Digital gyroscope sensors -# -CONFIG_ADIS16080=m -CONFIG_ADIS16130=m -CONFIG_ADIS16136=m -CONFIG_ADIS16260=m -# CONFIG_ADXRS290 is not set -CONFIG_ADXRS450=m -CONFIG_BMG160=m -CONFIG_BMG160_I2C=m -CONFIG_BMG160_SPI=m -CONFIG_FXAS21002C=m -CONFIG_FXAS21002C_I2C=m -CONFIG_FXAS21002C_SPI=m -CONFIG_HID_SENSOR_GYRO_3D=m -CONFIG_MPU3050=m -CONFIG_MPU3050_I2C=m -CONFIG_IIO_ST_GYRO_3AXIS=m -CONFIG_IIO_ST_GYRO_I2C_3AXIS=m -CONFIG_IIO_ST_GYRO_SPI_3AXIS=m -CONFIG_ITG3200=m -# end of Digital gyroscope sensors - -# -# Health Sensors -# - -# -# Heart Rate Monitors -# -CONFIG_AFE4403=m -CONFIG_AFE4404=m -CONFIG_MAX30100=m -CONFIG_MAX30102=m -# end of Heart Rate Monitors -# end of Health Sensors - -# -# Humidity sensors -# -CONFIG_AM2315=m -CONFIG_DHT11=m -CONFIG_HDC100X=m -# CONFIG_HDC2010 is not set -# CONFIG_HDC3020 is not set -CONFIG_HID_SENSOR_HUMIDITY=m -CONFIG_HTS221=m -CONFIG_HTS221_I2C=m -CONFIG_HTS221_SPI=m -CONFIG_HTU21=m -CONFIG_SI7005=m -CONFIG_SI7020=m -# end of Humidity sensors - -# -# Inertial measurement units -# -# CONFIG_ADIS16400 is not set -CONFIG_ADIS16460=m -# CONFIG_ADIS16475 is not set -# CONFIG_ADIS16480 is not set -# CONFIG_BMI160_I2C is not set -# CONFIG_BMI160_SPI is not set -# CONFIG_BMI323_I2C is not set -# CONFIG_BMI323_SPI is not set -# CONFIG_BOSCH_BNO055_SERIAL is not set -# CONFIG_BOSCH_BNO055_I2C is not set -CONFIG_FXOS8700=m -CONFIG_FXOS8700_I2C=m -CONFIG_FXOS8700_SPI=m -# CONFIG_KMX61 is not set -# CONFIG_INV_ICM42600_I2C is not set -# CONFIG_INV_ICM42600_SPI is not set -# CONFIG_INV_MPU6050_I2C is not set -# CONFIG_INV_MPU6050_SPI is not set -# CONFIG_IIO_ST_LSM6DSX is not set -CONFIG_IIO_ST_LSM9DS0=m -CONFIG_IIO_ST_LSM9DS0_I2C=m -CONFIG_IIO_ST_LSM9DS0_SPI=m -# end of Inertial measurement units - -CONFIG_IIO_ADIS_LIB=m -CONFIG_IIO_ADIS_LIB_BUFFER=y - -# -# Light sensors -# -CONFIG_ACPI_ALS=m -CONFIG_ADJD_S311=m -CONFIG_ADUX1020=m -CONFIG_AL3010=m -CONFIG_AL3320A=m -CONFIG_APDS9300=m -# CONFIG_APDS9306 is not set -CONFIG_APDS9960=m -# CONFIG_AS73211 is not set -CONFIG_BH1750=m -CONFIG_BH1780=m -CONFIG_CM32181=m -CONFIG_CM3232=m -CONFIG_CM3323=m -CONFIG_CM3605=m -CONFIG_CM36651=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_GP2AP002=m -CONFIG_GP2AP020A00F=m -CONFIG_SENSORS_ISL29018=m -CONFIG_SENSORS_ISL29028=m -CONFIG_ISL29125=m -# CONFIG_ISL76682 is not set -CONFIG_HID_SENSOR_ALS=m -CONFIG_HID_SENSOR_PROX=m -CONFIG_JSA1212=m -# CONFIG_ROHM_BU27008 is not set -# CONFIG_ROHM_BU27034 is not set -CONFIG_RPR0521=m -# CONFIG_LTR390 is not set -CONFIG_LTR501=m -# CONFIG_LTRF216A is not set -CONFIG_LV0104CS=m -CONFIG_MAX44000=m -CONFIG_MAX44009=m -CONFIG_NOA1305=m -CONFIG_OPT3001=m -# CONFIG_OPT4001 is not set -CONFIG_PA12203001=m -CONFIG_SI1133=m -CONFIG_SI1145=m -CONFIG_STK3310=m -CONFIG_ST_UVIS25=m -CONFIG_ST_UVIS25_I2C=m -CONFIG_ST_UVIS25_SPI=m -CONFIG_TCS3414=m -CONFIG_TCS3472=m -CONFIG_SENSORS_TSL2563=m -CONFIG_TSL2583=m -CONFIG_TSL2591=m -CONFIG_TSL2772=m -CONFIG_TSL4531=m -CONFIG_US5182D=m -CONFIG_VCNL4000=m -CONFIG_VCNL4035=m -CONFIG_VEML6030=m -CONFIG_VEML6070=m -# CONFIG_VEML6075 is not set -CONFIG_VL6180=m -CONFIG_ZOPT2201=m -# end of Light sensors - -# -# Magnetometer sensors -# -# CONFIG_AF8133J is not set -CONFIG_AK8974=m -CONFIG_AK8975=m -CONFIG_AK09911=m -CONFIG_BMC150_MAGN=m -CONFIG_BMC150_MAGN_I2C=m -CONFIG_BMC150_MAGN_SPI=m -CONFIG_MAG3110=m -CONFIG_HID_SENSOR_MAGNETOMETER_3D=m -CONFIG_MMC35240=m -CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_ST_MAGN_I2C_3AXIS=m -CONFIG_IIO_ST_MAGN_SPI_3AXIS=m -CONFIG_SENSORS_HMC5843=m -CONFIG_SENSORS_HMC5843_I2C=m -CONFIG_SENSORS_HMC5843_SPI=m -CONFIG_SENSORS_RM3100=m -CONFIG_SENSORS_RM3100_I2C=m -CONFIG_SENSORS_RM3100_SPI=m -# CONFIG_TI_TMAG5273 is not set -CONFIG_YAMAHA_YAS530=m -# end of Magnetometer sensors - -# -# Multiplexers -# -# CONFIG_IIO_MUX is not set -# end of Multiplexers - -# -# Inclinometer sensors -# -CONFIG_HID_SENSOR_INCLINOMETER_3D=m -CONFIG_HID_SENSOR_DEVICE_ROTATION=m -# end of Inclinometer sensors - -# CONFIG_IIO_GTS_KUNIT_TEST is not set -CONFIG_IIO_FORMAT_KUNIT_TEST=m - -# -# Triggers - standalone -# -CONFIG_IIO_HRTIMER_TRIGGER=m -CONFIG_IIO_INTERRUPT_TRIGGER=m -CONFIG_IIO_TIGHTLOOP_TRIGGER=m -CONFIG_IIO_SYSFS_TRIGGER=m -# end of Triggers - standalone - -# -# Linear and angular position sensors -# -CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m -# end of Linear and angular position sensors - -# -# Digital potentiometers -# -CONFIG_AD5110=m -CONFIG_AD5272=m -CONFIG_DS1803=m -CONFIG_MAX5432=m -# CONFIG_MAX5481 is not set -# CONFIG_MAX5487 is not set -CONFIG_MCP4018=m -# CONFIG_MCP4131 is not set -# CONFIG_MCP4531 is not set -CONFIG_MCP41010=m -# CONFIG_TPL0102 is not set -# CONFIG_X9250 is not set -# end of Digital potentiometers - -# -# Digital potentiostats -# -# CONFIG_LMP91000 is not set -# end of Digital potentiostats - -# -# Pressure sensors -# -# CONFIG_ABP060MG is not set -# CONFIG_ROHM_BM1390 is not set -CONFIG_BMP280=m -CONFIG_BMP280_I2C=m -CONFIG_BMP280_SPI=m -# CONFIG_IIO_CROS_EC_BARO is not set -CONFIG_DLHL60D=m -CONFIG_DPS310=m -CONFIG_HID_SENSOR_PRESS=m -# CONFIG_HP03 is not set -# CONFIG_HSC030PA is not set -CONFIG_ICP10100=m -# CONFIG_MPL115_I2C is not set -# CONFIG_MPL115_SPI is not set -CONFIG_MPL3115=m -# CONFIG_MPRLS0025PA is not set -# CONFIG_MS5611 is not set -# CONFIG_MS5637 is not set -# CONFIG_IIO_ST_PRESS is not set -# CONFIG_T5403 is not set -# CONFIG_HP206C is not set -# CONFIG_ZPA2326 is not set -# end of Pressure sensors - -# -# Lightning sensors -# -# CONFIG_AS3935 is not set -# end of Lightning sensors - -# -# Proximity and distance sensors -# -CONFIG_CROS_EC_MKBP_PROXIMITY=m -# CONFIG_IRSD200 is not set -CONFIG_ISL29501=m -# CONFIG_LIDAR_LITE_V2 is not set -CONFIG_MB1232=m -CONFIG_PING=m -# CONFIG_RFD77402 is not set -# CONFIG_SRF04 is not set -# CONFIG_SX9310 is not set -# CONFIG_SX9324 is not set -# CONFIG_SX9360 is not set -# CONFIG_SX9500 is not set -# CONFIG_SRF08 is not set -# CONFIG_VCNL3020 is not set -CONFIG_VL53L0X_I2C=m -# end of Proximity and distance sensors - -# -# Resolver to digital converters -# -# CONFIG_AD2S90 is not set -# CONFIG_AD2S1200 is not set -# CONFIG_AD2S1210 is not set -# end of Resolver to digital converters - -# -# Temperature sensors -# -CONFIG_LTC2983=m -CONFIG_MAXIM_THERMOCOUPLE=m -CONFIG_HID_SENSOR_TEMP=m -CONFIG_MLX90614=m -CONFIG_MLX90632=m -# CONFIG_MLX90635 is not set -CONFIG_TMP006=m -CONFIG_TMP007=m -CONFIG_TMP117=m -CONFIG_TSYS01=m -CONFIG_TSYS02D=m -# CONFIG_MAX30208 is not set -CONFIG_MAX31856=m -CONFIG_MAX31865=m -# CONFIG_MCP9600 is not set -# end of Temperature sensors - -# CONFIG_NTB is not set -CONFIG_PWM=y -# CONFIG_PWM_DEBUG is not set -CONFIG_PWM_ATMEL_TCB=m -CONFIG_PWM_CLK=m -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_DWC_CORE=m -CONFIG_PWM_DWC=m -# CONFIG_PWM_FSL_FTM is not set -CONFIG_PWM_NTXEC=m -# CONFIG_PWM_PCA9685 is not set -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_XILINX=m - -# -# IRQ chip support -# -CONFIG_IRQCHIP=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_MAX_NR=1 -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_AL_FIC is not set -# CONFIG_XILINX_INTC is not set -CONFIG_PARTITION_PERCPU=y -# end of IRQ chip support - -# CONFIG_IPACK_BUS is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_GPIO is not set -CONFIG_RESET_SCMI=y -# CONFIG_RESET_SIMPLE is not set -# CONFIG_RESET_TI_SYSCON is not set -CONFIG_RESET_TI_TPS380X=m - -# -# PHY Subsystem -# -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PHY_MIPI_DPHY=y -CONFIG_PHY_CAN_TRANSCEIVER=m - -# -# PHY drivers for Broadcom platforms -# -CONFIG_BCM_KONA_USB2_PHY=m -# end of PHY drivers for Broadcom platforms - -CONFIG_PHY_CADENCE_TORRENT=m -CONFIG_PHY_CADENCE_DPHY=m -# CONFIG_PHY_CADENCE_DPHY_RX is not set -CONFIG_PHY_CADENCE_SIERRA=m -# CONFIG_PHY_CADENCE_SALVO is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_LAN966X_SERDES is not set -# CONFIG_PHY_CPCAP_USB is not set -CONFIG_PHY_MAPPHONE_MDM6600=m -# CONFIG_PHY_OCELOT_SERDES is not set -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_HSIC=y -CONFIG_PHY_ROCKCHIP_DP=y -CONFIG_PHY_ROCKCHIP_DPHY_RX0=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=y -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y -CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PHY_ROCKCHIP_USBDP=y -CONFIG_PHY_SAMSUNG_USB2=y -# CONFIG_PHY_TUSB1210 is not set -# end of PHY Subsystem - -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -CONFIG_ARM_CCI_PMU=y -CONFIG_ARM_CCI400_PMU=y -CONFIG_ARM_CCI5xx_PMU=y -CONFIG_ARM_CCN=y -# CONFIG_ARM_CMN is not set -CONFIG_ARM_PMU=y -CONFIG_ARM_PMU_ACPI=y -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_ARM_PMUV3=y -# CONFIG_ARM_DSU_PMU is not set -# CONFIG_ARM_SPE_PMU is not set -CONFIG_ARM_DMC620_PMU=m -CONFIG_ALIBABA_UNCORE_DRW_PMU=m -CONFIG_HISI_PMU=y -# CONFIG_HISI_PCIE_PMU is not set -CONFIG_HNS3_PMU=m -# CONFIG_DWC_PCIE_PMU is not set -# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set -CONFIG_CXL_PMU=m -# end of Performance monitor support - -CONFIG_RAS=y -# CONFIG_USB4 is not set - -# -# Android -# -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_BINDERFS=y -CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder,anbox-binder,anbox-hwbinder,anbox-vndbinder" -# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set -# end of Android - -# CONFIG_LIBNVDIMM is not set -CONFIG_DAX=y -CONFIG_DEV_DAX=m -CONFIG_DEV_DAX_HMEM=m -CONFIG_DEV_DAX_CXL=m -CONFIG_DEV_DAX_HMEM_DEVICES=y -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_NVMEM_LAYOUTS=y - -# -# Layout Types -# -# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set -# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set -# end of Layout Types - -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_ROCKCHIP_EFUSE=m -CONFIG_NVMEM_ROCKCHIP_OTP=m -CONFIG_NVMEM_SPMI_SDAM=m -CONFIG_NVMEM_U_BOOT_ENV=m - -# -# HW tracing support -# -# CONFIG_STM is not set -# CONFIG_INTEL_TH is not set -CONFIG_HISI_PTT=m -# end of HW tracing support - -CONFIG_FPGA=y -# CONFIG_ALTERA_PR_IP_CORE is not set -# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set -# CONFIG_FPGA_MGR_ALTERA_CVP is not set -# CONFIG_FPGA_MGR_XILINX_SELECTMAP is not set -# CONFIG_FPGA_MGR_XILINX_SPI is not set -# CONFIG_FPGA_MGR_ICE40_SPI is not set -# CONFIG_FPGA_MGR_MACHXO2_SPI is not set -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -# CONFIG_XILINX_PR_DECOUPLER is not set -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -# CONFIG_FPGA_DFL is not set -CONFIG_FPGA_MGR_MICROCHIP_SPI=m -# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set -# CONFIG_FSI is not set -CONFIG_TEE=y -CONFIG_OPTEE=y -# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set -# CONFIG_ARM_TSTEE is not set -CONFIG_MULTIPLEXER=y - -# -# Multiplexer drivers -# -CONFIG_MUX_ADG792A=m -CONFIG_MUX_ADGS1408=m -CONFIG_MUX_GPIO=m -CONFIG_MUX_MMIO=m -# end of Multiplexer drivers - -CONFIG_PM_OPP=y -# CONFIG_SIOX is not set -CONFIG_SLIMBUS=m -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_INTERCONNECT=y -CONFIG_COUNTER=m -CONFIG_INTERRUPT_CNT=m -CONFIG_MOST=m -# CONFIG_MOST_USB_HDM is not set -# CONFIG_MOST_CDEV is not set -CONFIG_MOST_SND=m -# CONFIG_PECI is not set -# CONFIG_HTE is not set -# CONFIG_CDX_BUS is not set -CONFIG_DPLL=y -# end of Device Drivers - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_STACK=y -CONFIG_BUFFER_HEAD=y -CONFIG_LEGACY_DIRECT_IO=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_EXT4_KUNIT_TESTS=m -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=m -CONFIG_XFS_SUPPORT_V4=y -CONFIG_XFS_SUPPORT_ASCII_CI=y -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -# CONFIG_XFS_ONLINE_SCRUB is not set -# CONFIG_XFS_WARN is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set -# CONFIG_BTRFS_DEBUG is not set -# CONFIG_BTRFS_ASSERT is not set -# CONFIG_BTRFS_FS_REF_VERIFY is not set -CONFIG_NILFS2_FS=m -CONFIG_F2FS_FS=y -CONFIG_F2FS_STAT_FS=y -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_FS_POSIX_ACL=y -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_CHECK_FS=y -# CONFIG_F2FS_FAULT_INJECTION is not set -CONFIG_F2FS_FS_COMPRESSION=y -CONFIG_F2FS_FS_LZO=y -CONFIG_F2FS_FS_LZORLE=y -CONFIG_F2FS_FS_LZ4=y -CONFIG_F2FS_FS_LZ4HC=y -CONFIG_F2FS_FS_ZSTD=y -CONFIG_F2FS_IOSTAT=y -# CONFIG_F2FS_UNFAIR_RWSEM is not set -CONFIG_BCACHEFS_FS=m -CONFIG_BCACHEFS_QUOTA=y -CONFIG_BCACHEFS_ERASURE_CODING=y -CONFIG_BCACHEFS_POSIX_ACL=y -# CONFIG_BCACHEFS_DEBUG is not set -# CONFIG_BCACHEFS_TESTS is not set -# CONFIG_BCACHEFS_LOCK_TIME_STATS is not set -# CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set -CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y -# CONFIG_MEAN_AND_VARIANCE_UNIT_TEST is not set -CONFIG_ZONEFS_FS=m -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -CONFIG_EXPORTFS_BLOCK_OPS=y -CONFIG_FILE_LOCKING=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_ALGS=y -CONFIG_FS_VERITY=y -CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=m -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_QUOTACTL=y -CONFIG_AUTOFS_FS=m -CONFIG_FUSE_FS=y -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=m -CONFIG_FUSE_PASSTHROUGH=y -CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_INDEX is not set -CONFIG_OVERLAY_FS_XINO_AUTO=y -# CONFIG_OVERLAY_FS_METACOPY is not set -# CONFIG_OVERLAY_FS_DEBUG is not set - -# -# Caches -# -CONFIG_NETFS_SUPPORT=m -CONFIG_NETFS_STATS=y -CONFIG_FSCACHE=y -CONFIG_FSCACHE_STATS=y -# CONFIG_FSCACHE_DEBUG is not set -CONFIG_CACHEFILES=m -# CONFIG_CACHEFILES_DEBUG is not set -# CONFIG_CACHEFILES_ERROR_INJECTION is not set -# CONFIG_CACHEFILES_ONDEMAND is not set -# end of Caches - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=936 -CONFIG_FAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_FAT_KUNIT_TEST is not set -CONFIG_EXFAT_FS=y -CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS3_FS=y -# CONFIG_NTFS3_64BIT_CLUSTER is not set -CONFIG_NTFS3_LZX_XPRESS=y -CONFIG_NTFS3_FS_POSIX_ACL=y -CONFIG_NTFS_FS=y -# end of DOS/FAT/EXFAT/NT Filesystems - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -# CONFIG_PROC_KCORE is not set -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_CHILDREN=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -# CONFIG_TMPFS_INODE64 is not set -# CONFIG_TMPFS_QUOTA is not set -CONFIG_ARCH_SUPPORTS_HUGETLBFS=y -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y -# end of Pseudo filesystems - -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ORANGEFS_FS=m -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=m -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UBIFS_FS_ZSTD=y -# CONFIG_UBIFS_ATIME_SUPPORT is not set -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_SECURITY=y -# CONFIG_UBIFS_FS_AUTHENTICATION is not set -CONFIG_CRAMFS=m -CONFIG_CRAMFS_BLOCKDEV=y -CONFIG_CRAMFS_MTD=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set -CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set -# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_ZSTD=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_SQUASHFS_EMBEDDED=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_QNX6FS_FS=m -# CONFIG_QNX6FS_DEBUG is not set -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_PSTORE=y -CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_COMPRESS=y -# CONFIG_PSTORE_CONSOLE is not set -# CONFIG_PSTORE_PMSG is not set -CONFIG_PSTORE_RAM=m -CONFIG_PSTORE_ZONE=m -CONFIG_PSTORE_BLK=m -CONFIG_PSTORE_BLK_BLKDEV="" -CONFIG_PSTORE_BLK_KMSG_SIZE=64 -CONFIG_PSTORE_BLK_MAX_REASON=2 -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -CONFIG_UFS_FS_WRITE=y -# CONFIG_UFS_DEBUG is not set -CONFIG_EROFS_FS=m -# CONFIG_EROFS_FS_DEBUG is not set -CONFIG_EROFS_FS_XATTR=y -CONFIG_EROFS_FS_POSIX_ACL=y -CONFIG_EROFS_FS_SECURITY=y -# CONFIG_EROFS_FS_ZIP is not set -# CONFIG_EROFS_FS_ONDEMAND is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V2=m -CONFIG_NFS_V3=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_SWAP=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_PNFS_FILE_LAYOUT=m -CONFIG_PNFS_BLOCK=m -CONFIG_PNFS_FLEXFILE_LAYOUT=m -CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" -CONFIG_NFS_V4_1_MIGRATION=y -CONFIG_NFS_V4_SECURITY_LABEL=y -CONFIG_NFS_FSCACHE=y -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DEBUG=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_NFS_V4_2_READ_PLUS=y -CONFIG_NFSD=m -# CONFIG_NFSD_V2 is not set -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_PNFS=y -CONFIG_NFSD_BLOCKLAYOUT=y -CONFIG_NFSD_SCSILAYOUT=y -CONFIG_NFSD_FLEXFILELAYOUT=y -# CONFIG_NFSD_V4_2_INTER_SSC is not set -CONFIG_NFSD_V4_SECURITY_LABEL=y -# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set -CONFIG_GRACE_PERIOD=m -CONFIG_LOCKD=m -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_NFS_V4_2_SSC_HELPER=y -CONFIG_SUNRPC=m -CONFIG_SUNRPC_GSS=m -CONFIG_SUNRPC_BACKCHANNEL=y -CONFIG_SUNRPC_SWAP=y -CONFIG_RPCSEC_GSS_KRB5=m -CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y -# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set -# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set -# CONFIG_RPCSEC_GSS_KRB5_KUNIT_TEST is not set -CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FSCACHE=y -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CEPH_FS_SECURITY_LABEL=y -CONFIG_CIFS=m -CONFIG_CIFS_STATS2=y -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -CONFIG_CIFS_DFS_UPCALL=y -# CONFIG_CIFS_SWN_UPCALL is not set -CONFIG_CIFS_FSCACHE=y -CONFIG_SMB_SERVER=m -CONFIG_SMB_SERVER_SMBDIRECT=y -CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y -CONFIG_SMB_SERVER_KERBEROS5=y -CONFIG_SMBFS=m -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_AFS_FSCACHE=y -# CONFIG_AFS_DEBUG_CURSOR is not set -CONFIG_9P_FS=m -CONFIG_9P_FSCACHE=y -CONFIG_9P_FS_POSIX_ACL=y -CONFIG_9P_FS_SECURITY=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_NLS_UTF8=m -CONFIG_NLS_UCS2_UTILS=m -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set -CONFIG_UNICODE=y -# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set -CONFIG_IO_WQ=y -# end of File systems - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_REQUEST_CACHE=y -CONFIG_PERSISTENT_KEYRINGS=y -CONFIG_TRUSTED_KEYS=y -CONFIG_HAVE_TRUSTED_KEYS=y -CONFIG_TRUSTED_KEYS_TPM=y -CONFIG_TRUSTED_KEYS_TEE=y -CONFIG_ENCRYPTED_KEYS=y -# CONFIG_USER_DECRYPTED_DATA is not set -CONFIG_KEY_DH_OPERATIONS=y -CONFIG_SECURITY_DMESG_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITYFS=y -CONFIG_SECURITY_NETWORK=y -CONFIG_SECURITY_NETWORK_XFRM=y -CONFIG_SECURITY_PATH=y -CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_HARDENED_USERCOPY=y -CONFIG_FORTIFY_SOURCE=y -# CONFIG_STATIC_USERMODEHELPER is not set -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y -CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 -CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 -# CONFIG_SECURITY_SELINUX_DEBUG is not set -CONFIG_SECURITY_SMACK=y -# CONFIG_SECURITY_SMACK_BRINGUP is not set -CONFIG_SECURITY_SMACK_NETFILTER=y -CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y -CONFIG_SECURITY_TOMOYO=y -CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 -CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 -# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set -CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" -CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" -# CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set -CONFIG_SECURITY_APPARMOR=y -# CONFIG_SECURITY_APPARMOR_DEBUG is not set -CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y -CONFIG_SECURITY_APPARMOR_HASH=y -CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y -CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y -CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y -# CONFIG_SECURITY_APPARMOR_KUNIT_TEST is not set -# CONFIG_SECURITY_LOADPIN is not set -CONFIG_SECURITY_YAMA=y -CONFIG_SECURITY_SAFESETID=y -# CONFIG_SECURITY_LOCKDOWN_LSM is not set -# CONFIG_SECURITY_LANDLOCK is not set -CONFIG_INTEGRITY=y -CONFIG_INTEGRITY_SIGNATURE=y -CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -CONFIG_INTEGRITY_TRUSTED_KEYRING=y -CONFIG_INTEGRITY_PLATFORM_KEYRING=y -# CONFIG_INTEGRITY_MACHINE_KEYRING is not set -CONFIG_LOAD_UEFI_KEYS=y -CONFIG_INTEGRITY_AUDIT=y -CONFIG_IMA=y -# CONFIG_IMA_KEXEC is not set -CONFIG_IMA_MEASURE_PCR_IDX=10 -CONFIG_IMA_LSM_RULES=y -CONFIG_IMA_NG_TEMPLATE=y -# CONFIG_IMA_SIG_TEMPLATE is not set -CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" -CONFIG_IMA_DEFAULT_HASH_SHA1=y -# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set -# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set -CONFIG_IMA_DEFAULT_HASH="sha1" -# CONFIG_IMA_WRITE_POLICY is not set -# CONFIG_IMA_READ_POLICY is not set -CONFIG_IMA_APPRAISE=y -# CONFIG_IMA_ARCH_POLICY is not set -# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set -CONFIG_IMA_APPRAISE_BOOTPARAM=y -# CONFIG_IMA_APPRAISE_MODSIG is not set -# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set -# CONFIG_IMA_BLACKLIST_KEYRING is not set -# CONFIG_IMA_LOAD_X509 is not set -CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y -CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -# CONFIG_IMA_DISABLE_HTABLE is not set -CONFIG_EVM=y -CONFIG_EVM_ATTR_FSUUID=y -CONFIG_EVM_EXTRA_SMACK_XATTRS=y -# CONFIG_EVM_ADD_XATTRS is not set -# CONFIG_EVM_LOAD_X509 is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_APPARMOR=y -# CONFIG_DEFAULT_SECURITY_DAC is not set -CONFIG_LSM="lockdown,yama,integrity,apparmor" - -# -# Kernel hardening options -# - -# -# Memory initialization -# -CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y -CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_STACK_ALL_PATTERN is not set -# CONFIG_INIT_STACK_ALL_ZERO is not set -CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y -# CONFIG_ZERO_CALL_USED_REGS is not set -# end of Memory initialization - -# -# Hardening of kernel data structures -# -# CONFIG_LIST_HARDENED is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# end of Hardening of kernel data structures - -CONFIG_RANDSTRUCT_NONE=y -# end of Kernel hardening options -# end of Security options - -CONFIG_XOR_BLOCKS=y -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y -CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SIG=y -CONFIG_CRYPTO_SIG2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_KPP=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ENGINE=m -# end of Crypto core or helper - -# -# Public-key cryptography -# -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_DH=y -CONFIG_CRYPTO_DH_RFC7919_GROUPS=y -CONFIG_CRYPTO_ECC=m -CONFIG_CRYPTO_ECDH=m -CONFIG_CRYPTO_ECDSA=m -CONFIG_CRYPTO_ECRDSA=m -# CONFIG_CRYPTO_SM2 is not set -CONFIG_CRYPTO_CURVE25519=m -# end of Public-key cryptography - -# -# Block ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_AES_TI=m -CONFIG_CRYPTO_ANUBIS=m -# CONFIG_CRYPTO_ARIA is not set -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_BLOWFISH_COMMON=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST_COMMON=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_SM4=m -CONFIG_CRYPTO_SM4_GENERIC=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -# end of Block ciphers - -# -# Length-preserving ciphers and modes -# -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_CHACHA20=m -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_HCTR2 is not set -CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_NHPOLY1305=y -# end of Length-preserving ciphers and modes - -# -# AEAD (authenticated encryption with associated data) ciphers -# -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_AEGIS128_SIMD=y -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_GENIV=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=m -CONFIG_CRYPTO_ESSIV=m -# end of AEAD (authenticated encryption with associated data) ciphers - -# -# Hashes, digests, and MACs -# -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_GHASH=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_POLY1305=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SM3=m -CONFIG_CRYPTO_SM3_GENERIC=m -CONFIG_CRYPTO_STREEBOG=m -CONFIG_CRYPTO_VMAC=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_XXHASH=y -# end of Hashes, digests, and MACs - -# -# CRCs (cyclic redundancy checks) -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRC64_ROCKSOFT=y -# end of CRCs (cyclic redundancy checks) - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_842=m -CONFIG_CRYPTO_LZ4=m -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ZSTD=y -# end of Compression - -# -# Random number generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_DRBG_HMAC=y -# CONFIG_CRYPTO_DRBG_HASH is not set -# CONFIG_CRYPTO_DRBG_CTR is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 -CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 -CONFIG_CRYPTO_JITTERENTROPY_OSR=1 -CONFIG_CRYPTO_KDF800108_CTR=y -# end of Random number generation - -# -# Userspace interface -# -CONFIG_CRYPTO_USER_API=m -CONFIG_CRYPTO_USER_API_HASH=m -CONFIG_CRYPTO_USER_API_SKCIPHER=m -CONFIG_CRYPTO_USER_API_RNG=m -# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set -CONFIG_CRYPTO_USER_API_AEAD=m -CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y -# end of Userspace interface - -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_NHPOLY1305_NEON=y -CONFIG_CRYPTO_CHACHA20_NEON=y - -# -# Accelerated Cryptographic Algorithms for CPU (arm64) -# -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_POLY1305_NEON=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -# CONFIG_CRYPTO_SM3_NEON is not set -CONFIG_CRYPTO_SM3_ARM64_CE=m -# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_AES_ARM64_BS=y -CONFIG_CRYPTO_SM4_ARM64_CE=m -# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set -# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -# end of Accelerated Cryptographic Algorithms for CPU (arm64) - -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_DEV_ATMEL_I2C=m -CONFIG_CRYPTO_DEV_ATMEL_ECC=m -CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m -# CONFIG_CRYPTO_DEV_CCP is not set -CONFIG_CRYPTO_DEV_NITROX=m -CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set -# CONFIG_CRYPTO_DEV_QAT_C62X is not set -# CONFIG_CRYPTO_DEV_QAT_4XXX is not set -# CONFIG_CRYPTO_DEV_QAT_420XX is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set -# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m -CONFIG_CRYPTO_DEV_ROCKCHIP=m -# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set -CONFIG_CRYPTO_DEV_ROCKCHIP2=m -# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set -CONFIG_CRYPTO_DEV_VIRTIO=m -CONFIG_CRYPTO_DEV_SAFEXCEL=m -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_QM=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_HISI_TRNG=m -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_X509_CERTIFICATE_PARSER=y -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set -CONFIG_PKCS7_MESSAGE_PARSER=y -CONFIG_PKCS7_TEST_KEY=m -CONFIG_SIGNED_PE_FILE_VERIFICATION=y -# CONFIG_FIPS_SIGNATURE_SELFTEST is not set - -# -# Certificates for signature checking -# -CONFIG_SYSTEM_TRUSTED_KEYRING=y -CONFIG_SYSTEM_TRUSTED_KEYS="" -CONFIG_SYSTEM_EXTRA_CERTIFICATE=y -CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 -CONFIG_SECONDARY_TRUSTED_KEYRING=y -# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set -CONFIG_SYSTEM_BLACKLIST_KEYRING=y -CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" -# CONFIG_SYSTEM_REVOCATION_LIST is not set -# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set -# end of Certificates for signature checking - -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_RAID6_PQ=y -CONFIG_RAID6_PQ_BENCHMARK=y -CONFIG_LINEAR_RANGES=y -CONFIG_PACKING=y -CONFIG_BITREVERSE=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_CORDIC=m -CONFIG_PRIME_NUMBERS=m -CONFIG_RATIONAL=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_USE_SYM_ANNOTATIONS=y -CONFIG_INDIRECT_PIO=y -# CONFIG_TRACE_MMIO_ACCESS is not set - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -# end of Crypto library routines - -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC64_ROCKSOFT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -CONFIG_CRC64=y -CONFIG_CRC4=m -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_CRC8=m -CONFIG_XXHASH=y -CONFIG_AUDIT_GENERIC=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_AUDIT_COMPAT_GENERIC=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_842_COMPRESS=m -CONFIG_842_DECOMPRESS=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=y -CONFIG_LZ4HC_COMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_MICROLZMA=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_TEST=m -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=m -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC16=y -CONFIG_REED_SOLOMON_DEC16=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_BTREE=y -CONFIG_INTERVAL_TREE=y -CONFIG_XARRAY_MULTI=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_CLOSURES=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y -CONFIG_NEED_SG_DMA_FLAGS=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_DMA_DECLARE_COHERENT=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y -CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_SWIOTLB=y -# CONFIG_SWIOTLB_DYNAMIC is not set -CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_RESTRICTED_POOL=y -CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_COHERENT_POOL=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_CMA=y -# CONFIG_DMA_NUMA_CMA is not set - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=384 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_DMA_MAP_BENCHMARK is not set -CONFIG_SGL_ALLOC=y -CONFIG_CHECK_SIGNATURE=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_GLOB=y -CONFIG_GLOB_SELFTEST=m -CONFIG_NLATTR=y -CONFIG_LRU_CACHE=m -CONFIG_CLZ_TAB=y -CONFIG_IRQ_POLL=y -CONFIG_MPILIB=y -CONFIG_SIGNATURE=y -CONFIG_DIMLIB=y -CONFIG_LIBFDT=y -CONFIG_OID_REGISTRY=y -CONFIG_UCS2_STRING=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_VDSO_TIME_NS=y -CONFIG_FONT_SUPPORT=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -CONFIG_FONT_ACORN_8x8=y -# CONFIG_FONT_MINI_4x6 is not set -CONFIG_FONT_6x10=y -# CONFIG_FONT_10x18 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -CONFIG_FONT_TER16x32=y -# CONFIG_FONT_6x8 is not set -CONFIG_SG_SPLIT=y -CONFIG_SG_POOL=y -CONFIG_MEMREGION=y -CONFIG_ARCH_STACKWALK=y -CONFIG_STACKDEPOT=y -CONFIG_STACKDEPOT_MAX_FRAMES=64 -CONFIG_SBITMAP=y -# CONFIG_LWQ_TEST is not set -# end of Library routines - -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_ASN1_ENCODER=y -CONFIG_POLYNOMIAL=m -CONFIG_FIRMWARE_TABLE=y - -# -# Kernel hacking -# - -# -# printk and dmesg options -# -CONFIG_PRINTK_TIME=y -# CONFIG_PRINTK_CALLER is not set -# CONFIG_STACKTRACE_BUILD_ID is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DYNAMIC_DEBUG_CORE=y -CONFIG_SYMBOLIC_ERRNAME=y -CONFIG_DEBUG_BUGVERBOSE=y -# end of printk and dmesg options - -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - -# -# Compile-time checks and compiler options -# -CONFIG_AS_HAS_NON_CONST_ULEB128=y -CONFIG_DEBUG_INFO_NONE=y -# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_DEBUG_INFO_DWARF5 is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_FRAME_POINTER=y -# CONFIG_VMLINUX_MAP is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# end of Compile-time checks and compiler options - -# -# Generic Kernel Debugging Instruments -# -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN=y -# CONFIG_UBSAN is not set -CONFIG_HAVE_ARCH_KCSAN=y -CONFIG_HAVE_KCSAN_COMPILER=y -# CONFIG_KCSAN is not set -# end of Generic Kernel Debugging Instruments - -# -# Networking Debugging -# -# CONFIG_NET_DEV_REFCNT_TRACKER is not set -# CONFIG_NET_NS_REFCNT_TRACKER is not set -# CONFIG_DEBUG_NET is not set -# end of Networking Debugging - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_TABLE_CHECK is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set -# CONFIG_DEBUG_RODATA_TEST is not set -CONFIG_ARCH_HAS_DEBUG_WX=y -# CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y -# CONFIG_PTDUMP_DEBUGFS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_PER_VMA_LOCK_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SHRINKER_DEBUG is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_SCHED_STACK_END_CHECK is not set -CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_VM_PGTABLE is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_MEM_ALLOC_PROFILING is not set -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y -CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y -CONFIG_HAVE_ARCH_KASAN_VMALLOC=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_CC_HAS_KASAN_SW_TAGS=y -CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y -# CONFIG_KASAN is not set -CONFIG_HAVE_ARCH_KFENCE=y -# CONFIG_KFENCE is not set -# end of Memory Debugging - -# CONFIG_DEBUG_SHIRQ is not set - -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_SOFTLOCKUP_DETECTOR is not set -CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y -# CONFIG_HARDLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set -CONFIG_TEST_LOCKUP=m -# end of Debug Oops, Lockups and Hangs - -# -# Scheduler Debugging -# -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_INFO=y -# CONFIG_SCHEDSTATS is not set -# end of Scheduler Debugging - -# CONFIG_DEBUG_TIMEKEEPING is not set -# CONFIG_DEBUG_PREEMPT is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_RWSEMS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_SCF_TORTURE_TEST is not set -# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -# end of Lock Debugging (spinlocks, mutexes, etc...) - -# CONFIG_DEBUG_IRQFLAGS is not set -CONFIG_STACKTRACE=y -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set - -# -# Debug kernel data structures -# -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CLOSURES is not set -# CONFIG_DEBUG_MAPLE_TREE is not set -# end of Debug kernel data structures - -# -# RCU Debugging -# -# CONFIG_RCU_SCALE_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 -# CONFIG_RCU_CPU_STALL_CPUTIME is not set -CONFIG_RCU_TRACE=y -# CONFIG_RCU_EQS_DEBUG is not set -# end of RCU Debugging - -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_DEBUG_CGROUP_REF is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_HWLAT_TRACER is not set -# CONFIG_OSNOISE_TRACER is not set -# CONFIG_TIMERLAT_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_TRACER_SNAPSHOT is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_KPROBE_EVENTS=y -CONFIG_UPROBE_EVENTS=y -CONFIG_BPF_EVENTS=y -CONFIG_DYNAMIC_EVENTS=y -CONFIG_PROBE_EVENTS=y -# CONFIG_BPF_KPROBE_OVERRIDE is not set -# CONFIG_SYNTH_EVENTS is not set -# CONFIG_USER_EVENTS is not set -# CONFIG_HIST_TRIGGERS is not set -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_RV is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y -CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_IO_STRICT_DEVMEM is not set - -# -# arm64 Debugging -# -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_ARM64_RELOC_TEST is not set -# CONFIG_CORESIGHT is not set -# end of arm64 Debugging - -# -# Kernel Testing and Coverage -# -CONFIG_KUNIT=m -# CONFIG_KUNIT_DEBUGFS is not set -# CONFIG_KUNIT_TEST is not set -# CONFIG_KUNIT_EXAMPLE_TEST is not set -# CONFIG_KUNIT_ALL_TESTS is not set -# CONFIG_KUNIT_DEFAULT_ENABLED is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set -CONFIG_RUNTIME_TESTING_MENU=y -# CONFIG_TEST_DHRY is not set -# CONFIG_LKDTM is not set -# CONFIG_CPUMASK_KUNIT_TEST is not set -# CONFIG_TEST_LIST_SORT is not set -CONFIG_TEST_MIN_HEAP=m -# CONFIG_TEST_SORT is not set -CONFIG_TEST_DIV64=m -# CONFIG_TEST_IOV_ITER is not set -# CONFIG_KPROBES_SANITY_TEST is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_TEST_REF_TRACKER is not set -# CONFIG_RBTREE_TEST is not set -CONFIG_REED_SOLOMON_TEST=m -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -CONFIG_ASYNC_RAID6_TEST=m -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_STRING_KUNIT_TEST is not set -# CONFIG_STRING_HELPERS_KUNIT_TEST is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -CONFIG_TEST_SCANF=m -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_UUID is not set -CONFIG_TEST_XARRAY=m -# CONFIG_TEST_MAPLE_TREE is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_IDA is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_BITOPS is not set -CONFIG_TEST_VMALLOC=m -# CONFIG_TEST_USER_COPY is not set -CONFIG_TEST_BPF=m -CONFIG_TEST_BLACKHOLE_DEV=m -# CONFIG_FIND_BIT_BENCHMARK is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_BITFIELD_KUNIT is not set -# CONFIG_CHECKSUM_KUNIT is not set -# CONFIG_HASH_KUNIT_TEST is not set -CONFIG_RESOURCE_KUNIT_TEST=m -# CONFIG_SYSCTL_KUNIT_TEST is not set -# CONFIG_LIST_KUNIT_TEST is not set -# CONFIG_HASHTABLE_KUNIT_TEST is not set -# CONFIG_LINEAR_RANGES_TEST is not set -CONFIG_CMDLINE_KUNIT_TEST=m -# CONFIG_BITS_TEST is not set -CONFIG_SLUB_KUNIT_TEST=m -CONFIG_RATIONAL_KUNIT_TEST=m -CONFIG_MEMCPY_KUNIT_TEST=m -# CONFIG_IS_SIGNED_TYPE_KUNIT_TEST is not set -# CONFIG_OVERFLOW_KUNIT_TEST is not set -# CONFIG_STACKINIT_KUNIT_TEST is not set -# CONFIG_FORTIFY_KUNIT_TEST is not set -# CONFIG_SIPHASH_KUNIT_TEST is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_DYNAMIC_DEBUG is not set -# CONFIG_TEST_KMOD is not set -CONFIG_TEST_MEMCAT_P=m -# CONFIG_TEST_MEMINIT is not set -# CONFIG_TEST_FREE_PAGES is not set -# CONFIG_TEST_FPU is not set -# CONFIG_TEST_OBJPOOL is not set -CONFIG_ARCH_USE_MEMTEST=y -CONFIG_MEMTEST=y -# end of Kernel Testing and Coverage - -# -# Rust hacking -# -# end of Rust hacking -# end of Kernel hacking diff --git a/config/kernel/linux-rockchip-rk3588-6.11.config b/config/kernel/linux-rockchip-rk3588-6.11.config index 31d3372d74fa..fb824d03ff15 100644 --- a/config/kernel/linux-rockchip-rk3588-6.11.config +++ b/config/kernel/linux-rockchip-rk3588-6.11.config @@ -1,15 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.11.0-rc4 Kernel Configuration +# Linux/arm64 6.11.0 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 13.2.0-23ubuntu4) 13.2.0" +CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=130200 +CONFIG_GCC_VERSION=110400 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=24200 +CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=24200 +CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -441,7 +441,6 @@ CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HW_PERF_EVENTS=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_ARCH_SUPPORTS_KEXEC=y @@ -772,8 +771,6 @@ CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y -# CONFIG_SHADOW_CALL_STACK is not set CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y @@ -6449,8 +6446,9 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_DISPLAY_HELPER=m CONFIG_DRM_DISPLAY_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_BRIDGE_CONNECTOR=y # CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set # CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set CONFIG_DRM_DISPLAY_DP_HELPER=y @@ -7484,6 +7482,7 @@ CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m +# CONFIG_HID_PLAYSTATION is not set CONFIG_HID_PXRC=m # CONFIG_HID_RAZER is not set CONFIG_HID_PRIMAX=m @@ -8045,6 +8044,7 @@ CONFIG_LEDS_AN30259A=m # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=y CONFIG_LEDS_EL15203000=m # CONFIG_LEDS_LM3530 is not set CONFIG_LEDS_LM3532=m @@ -8054,6 +8054,8 @@ CONFIG_LEDS_LM3692X=m CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -8097,6 +8099,12 @@ CONFIG_LEDS_LM3697=m # # RGB LED drivers # +# CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set +# CONFIG_LEDS_PWM_MULTICOLOR is not set +# CONFIG_LEDS_QCOM_LPG is not set +# CONFIG_LEDS_MT6370_RGB is not set # # LED Triggers @@ -10021,7 +10029,6 @@ CONFIG_CIFS_DFS_UPCALL=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y CONFIG_SMB_SERVER=m -CONFIG_SMB_SERVER_SMBDIRECT=y CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y CONFIG_SMB_SERVER_KERBEROS5=y CONFIG_SMBFS=m @@ -10199,12 +10206,7 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor" # # Memory initialization # -CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_STACK_ALL_PATTERN is not set -# CONFIG_INIT_STACK_ALL_ZERO is not set CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y @@ -10965,7 +10967,6 @@ CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_DHRY is not set # CONFIG_LKDTM is not set diff --git a/config/sources/families/rockchip-rk3588.conf b/config/sources/families/rockchip-rk3588.conf index 9bfb1941c2a5..9682186fcbf7 100644 --- a/config/sources/families/rockchip-rk3588.conf +++ b/config/sources/families/rockchip-rk3588.conf @@ -42,7 +42,7 @@ case $BRANCH in current) # Branch based on a stable kernel release (will stay on the next LTS kernel release once released, 6.12? LTS) LINUXFAMILY=rockchip-rk3588 - KERNEL_MAJOR_MINOR="6.10" # Major and minor versions of this kernel. + KERNEL_MAJOR_MINOR="6.11" # Major and minor versions of this kernel. LINUXCONFIG="linux-rockchip-rk3588-${KERNEL_MAJOR_MINOR}" # Attention: not -${BRANCH} (edge/current/legacy), but -${KERNEL_MAJOR_MINOR} thus 6.6 / 6.12 etc # No need to set KERNELPATCHDIR, since default is: KERNELPATCHDIR='archive/rockchip-rk3588-${KERNEL_MAJOR_MINOR}' ;; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0000.patching_config.yaml b/patch/kernel/archive/rockchip-rk3588-6.10/0000.patching_config.yaml deleted file mode 100644 index 6815f3cc8af9..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0000.patching_config.yaml +++ /dev/null @@ -1,47 +0,0 @@ -config: # This is file 'patch/kernel/rockchip-rk3588-edge/0000.patching_config.yaml' - - # PATCH NUMBERING INFO - # - # Patches should be ordered in such a way that general kernel patches are applied first, then SoC-related patches and at last board-specific patches - # - # Patch numbers in this folder are sorted by category: - # - # 000* for general patches - # 01** for GPU/HDMI related patches - # 08** for wireless patches - # 1*** for board specific patches: - # 101* for Rock-5B, 102* for Rock-5A and so on - - # Just some info stuff; not used by the patching scripts - name: rockchip-rk3588-edge - kind: kernel - type: mainline # or: vendor - branch: linux-6.10.y - last-known-good-tag: v6.10-rc2 - maintainers: - - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini } - - # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones. - # This is meant to provide a way to "add a board DTS" without having to null-patch them in. - dts-directories: - - { source: "dt", target: "arch/arm64/boot/dts/rockchip" } - - # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones - # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in. - # @TODO need a solution to auto-Makefile the overlays as well - overlay-directories: - - { source: "overlay", target: "arch/arm64/boot/dts/rockchip/overlay" } - - # the Makefile in each of these directories will be magically patched to include the dts files copied - # or patched-in; overlay subdir will be included "-y" if it exists. - # No more Makefile patching needed, yay! - auto-patch-dt-makefile: - - { directory: "arch/arm64/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" } - - # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers) - patches-to-git: - do-not-commit-files: - - "MAINTAINERS" # constant churn, drop them. sorry. - - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry. - do-not-commit-regexes: # Python-style regexes - - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0001-general-add-overlay-support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0001-general-add-overlay-support.patch deleted file mode 100644 index afc010c2107c..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0001-general-add-overlay-support.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paolo Sabatino -Date: Sun, 2 Jun 2024 21:53:01 +0200 -Subject: compile .scr and install overlays in right path - ---- - scripts/Makefile.dtbinst | 13 +++++++++- - scripts/Makefile.lib | 8 +++++- - 2 files changed, 19 insertions(+), 2 deletions(-) - -diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst -index 111111111111..222222222222 100644 ---- a/scripts/Makefile.dtbinst -+++ b/scripts/Makefile.dtbinst -@@ -33,7 +33,18 @@ endef - - $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) - --dtbs := $(notdir $(dtbs)) -+# Very convoluted way to flatten all the device tree -+# directories, but keep the "/overlay/" directory -+ -+# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) -+topmost_dir = $(firstword $(subst /, ,$(dtbs))) -+# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" -+dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) -+# collect the non-overlay dtbs -+dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) -+# compose the dtbs variable flattening all the non-overlays entries -+# and appending the overlays entries -+dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) - - endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL - -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index 111111111111..222222222222 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -402,7 +402,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE - - quiet_cmd_dtc = DTC $@ - cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ -- $(DTC) -o $@ -b 0 \ -+ $(DTC) -@ -o $@ -b 0 \ - $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ - -d $(depfile).dtc.tmp $(dtc-tmp) ; \ - cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -@@ -431,12 +431,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc) - cmd_dtb = $(cmd_dtc) - endif - -+quiet_cmd_scr = MKIMAGE $@ -+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ -+ - $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE - $(call if_changed_dep,dtb) - - $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE - $(call if_changed_dep,dtc) - -+$(obj)/%.scr: $(src)/%.scr-cmd FORCE -+ $(call if_changed,scr) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0010-fix-clk-divisions.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0010-fix-clk-divisions.patch deleted file mode 100644 index 25c4a67db09b..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0010-fix-clk-divisions.patch +++ /dev/null @@ -1,142 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 16:09:35 +0200 -Subject: math.h: add DIV_ROUND_UP_NO_OVERFLOW - -Add a new DIV_ROUND_UP helper, which cannot overflow when -big numbers are being used. - -Signed-off-by: Sebastian Reichel ---- - include/linux/math.h | 11 ++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/include/linux/math.h b/include/linux/math.h -index 111111111111..222222222222 100644 ---- a/include/linux/math.h -+++ b/include/linux/math.h -@@ -36,6 +36,17 @@ - - #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP - -+/** -+ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up -+ * @n: numerator / dividend -+ * @d: denominator / divisor -+ * -+ * This functions does the same as DIV_ROUND_UP, but internally uses a -+ * division and a modulo operation instead of math tricks. This way it -+ * avoids overflowing when handling big numbers. -+ */ -+#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d))) -+ - #define DIV_ROUND_DOWN_ULL(ll, d) \ - ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 16:13:50 +0200 -Subject: clk: divider: Fix divisor masking on 64 bit platforms - -The clock framework handles clock rates as "unsigned long", so u32 on -32-bit architectures and u64 on 64-bit architectures. - -The current code casts the dividend to u64 on 32-bit to avoid a -potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000) -= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been -introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow -when dividing large clock rates"). - -On 64 bit platforms this masks the divisor, so that only the lower -32 bit are used. Thus requesting a frequency >= 4.3GHz results -in incorrect values. For example requesting 4300000000 (4.3 GHz) will -effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX) -is a bit of a special case, since that still returns correct values as -long as the parent clock is below 8.5 GHz. - -Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot -overflow. This avoids any requirements on the arguments (except -that divisor should not be 0 obviously). - -Signed-off-by: Sebastian Reichel ---- - drivers/clk/clk-divider.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/clk-divider.c -+++ b/drivers/clk/clk-divider.c -@@ -220,7 +220,7 @@ static int _div_round_up(const struct clk_div_table *table, - unsigned long parent_rate, unsigned long rate, - unsigned long flags) - { -- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - - if (flags & CLK_DIVIDER_POWER_OF_TWO) - div = __roundup_pow_of_two(div); -@@ -237,7 +237,7 @@ static int _div_round_closest(const struct clk_div_table *table, - int up, down; - unsigned long up_rate, down_rate; - -- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - down = parent_rate / rate; - - if (flags & CLK_DIVIDER_POWER_OF_TWO) { -@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, - { - unsigned int div, value; - -- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); - - if (!_is_valid_div(table, div, flags)) - return -EINVAL; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Oct 2023 18:09:57 +0200 -Subject: clk: composite: replace open-coded abs_diff() - -Replace the open coded abs_diff() with the existing helper function. - -Suggested-by: Andy Shevchenko -Signed-off-by: Sebastian Reichel ---- - drivers/clk/clk-composite.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/clk-composite.c -+++ b/drivers/clk/clk-composite.c -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - - static u8 clk_composite_get_parent(struct clk_hw *hw) -@@ -119,10 +120,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, - if (ret) - continue; - -- if (req->rate >= tmp_req.rate) -- rate_diff = req->rate - tmp_req.rate; -- else -- rate_diff = tmp_req.rate - req->rate; -+ rate_diff = abs_diff(req->rate, tmp_req.rate); - - if (!rate_diff || !req->best_parent_hw - || best_rate_diff > rate_diff) { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0011-irqchip-fix-its-timeout-issue.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0011-irqchip-fix-its-timeout-issue.patch deleted file mode 100644 index afbe3796fb8d..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0011-irqchip-fix-its-timeout-issue.patch +++ /dev/null @@ -1,214 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Fri, 11 Aug 2023 17:56:00 +0300 -Subject: irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx boards - ---- - drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++- - 1 file changed, 72 insertions(+), 7 deletions(-) - -diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c -index 111111111111..222222222222 100644 ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -163,6 +163,7 @@ struct its_device { - struct its_node *its; - struct event_lpi_map event_map; - void *itt; -+ u32 itt_sz; - u32 nr_ites; - u32 device_id; - bool shared; -@@ -2191,6 +2192,9 @@ static void gic_reset_prop_table(void *va) - static struct page *its_allocate_prop_table(gfp_t gfp_flags) - { - struct page *prop_page; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; - - prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); - if (!prop_page) -@@ -2315,6 +2319,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - u32 alloc_pages, psz; - struct page *page; - void *base; -+ gfp_t gfp_flags; - - psz = baser->psz; - alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); -@@ -2326,7 +2331,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - order = get_order(GITS_BASER_PAGES_MAX * psz); - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); -+ gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ -+ page = alloc_pages_node(its->numa_node, gfp_flags, order); - if (!page) - return -ENOMEM; - -@@ -2376,6 +2385,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, - its_write_baser(its, baser, val); - tmp = baser->val; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) { -+ if (tmp & GITS_BASER_SHAREABILITY_MASK) -+ tmp &= ~GITS_BASER_SHAREABILITY_MASK; -+ else -+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); -+ } -+ - if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { - /* - * Shareability didn't stick. Just use -@@ -2965,7 +2983,9 @@ static int its_alloc_collections(struct its_node *its) - static struct page *its_allocate_pending_table(gfp_t gfp_flags) - { - struct page *pend_page; -- -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; - pend_page = alloc_pages(gfp_flags | __GFP_ZERO, - get_order(LPI_PENDBASE_SZ)); - if (!pend_page) -@@ -3124,6 +3144,11 @@ static void its_cpu_init_lpis(void) - if (!rdists_support_shareable()) - tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; -+ - if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { - if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { - /* -@@ -3151,6 +3176,11 @@ static void its_cpu_init_lpis(void) - if (!rdists_support_shareable()) - tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; -+ - if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { - /* - * The HW reports non-shareable, we must remove the -@@ -3314,7 +3344,11 @@ static bool its_alloc_table_entry(struct its_node *its, - - /* Allocate memory for 2nd level table */ - if (!table[idx]) { -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ page = alloc_pages_node(its->numa_node, gfp_flags, - get_order(baser->psz)); - if (!page) - return false; -@@ -3403,6 +3437,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - int nr_lpis; - int nr_ites; - int sz; -+ gfp_t gfp_flags; - - if (!its_alloc_device_table(its, dev_id)) - return NULL; -@@ -3418,7 +3453,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - nr_ites = max(2, nvecs); - sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); - sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; -- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); -+ gfp_flags = GFP_KERNEL; -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) { -+ gfp_flags |= GFP_DMA32; -+ itt = (void *)__get_free_pages(gfp_flags, get_order(sz)); -+ } else { -+ itt = kzalloc_node(sz, gfp_flags, its->numa_node); -+ } -+ - if (alloc_lpis) { - lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); - if (lpi_map) -@@ -3432,7 +3475,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - - if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { - kfree(dev); -- kfree(itt); -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ free_pages((unsigned long)itt, get_order(sz)); -+ else -+ kfree(itt); -+ - bitmap_free(lpi_map); - kfree(col_map); - return NULL; -@@ -3442,6 +3491,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, - - dev->its = its; - dev->itt = itt; -+ dev->itt_sz = sz; - dev->nr_ites = nr_ites; - dev->event_map.lpi_map = lpi_map; - dev->event_map.col_map = col_map; -@@ -3469,7 +3519,13 @@ static void its_free_device(struct its_device *its_dev) - list_del(&its_dev->entry); - raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); - kfree(its_dev->event_map.col_map); -- kfree(its_dev->itt); -+ -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); -+ else -+ kfree(its_dev->itt); -+ - kfree(its_dev); - } - -@@ -5078,6 +5134,7 @@ static int __init its_probe_one(struct its_node *its) - struct page *page; - u32 ctlr; - int err; -+ gfp_t gfp_flags; - - its_enable_quirks(its); - -@@ -5111,7 +5168,10 @@ static int __init its_probe_one(struct its_node *its) - } - } - -- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, -+ gfp_flags = GFP_KERNEL | __GFP_ZERO; -+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) -+ gfp_flags |= GFP_DMA32; -+ page = alloc_pages_node(its->numa_node, gfp_flags, - get_order(ITS_CMD_QUEUE_SZ)); - if (!page) { - err = -ENOMEM; -@@ -5140,6 +5200,11 @@ static int __init its_probe_one(struct its_node *its) - if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) - tmp &= ~GITS_CBASER_SHAREABILITY_MASK; - -+ if (of_machine_is_compatible("rockchip,rk3568") || -+ of_machine_is_compatible("rockchip,rk3566") || -+ of_machine_is_compatible("rockchip,rk3588")) -+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK; -+ - if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { - if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { - /* --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch deleted file mode 100644 index 502bd2a5f722..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch +++ /dev/null @@ -1,758 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:32 +0400 -Subject: arm64: dts: rockchip: add thermal zones information on RK3588 - -This includes the necessary device tree data to allow thermal -monitoring on RK3588(s) using the on-chip TSADC device, along with -trip points for automatic thermal management. - -Each of the CPU clusters (one for the little cores and two for -the big cores) get a passive cooling trip point at 85C, which -will trigger DVFS throttling of the respective cluster upon -reaching a high temperature condition. - -All zones also have a critical trip point at 115C, which will -trigger a reset. - -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 147 ++++++++++ - 1 file changed, 147 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - - / { - compatible = "rockchip,rk3588"; -@@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 { - status = "disabled"; - }; - -+ thermal_zones: thermal-zones { -+ /* sensor near the center of the SoC */ -+ package_thermal: package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 0>; -+ -+ trips { -+ package_crit: package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ /* sensor between A76 cores 0 and 1 */ -+ bigcore0_thermal: bigcore0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 1>; -+ -+ trips { -+ bigcore0_alert: bigcore0-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ bigcore0_crit: bigcore0-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&bigcore0_alert>; -+ cooling-device = -+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor between A76 cores 2 and 3 */ -+ bigcore2_thermal: bigcore2-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 2>; -+ -+ trips { -+ bigcore2_alert: bigcore2-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ bigcore2_crit: bigcore2-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&bigcore2_alert>; -+ cooling-device = -+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor between the four A55 cores */ -+ little_core_thermal: littlecore-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 3>; -+ -+ trips { -+ littlecore_alert: littlecore-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ littlecore_crit: littlecore-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&littlecore_alert>; -+ cooling-device = -+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ /* sensor near the PD_CENTER power domain */ -+ center_thermal: center-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 4>; -+ -+ trips { -+ center_crit: center-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu_thermal: gpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 5>; -+ -+ trips { -+ gpu_crit: gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ npu_thermal: npu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 6>; -+ -+ trips { -+ npu_crit: npu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:33 +0400 -Subject: arm64: dts: rockchip: enable thermal management on all RK3588 boards - -This enables the on-chip thermal monitoring sensor (TSADC) on all -RK3588(s) boards that don't have it enabled yet. It provides temperature -monitoring for the SoC and emergency thermal shutdowns, and is thus -important to have in place before CPU DVFS is enabled, as high CPU -operating performance points can overheat the chip quickly in the -absence of thermal management. - -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ - 8 files changed, 32 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -673,6 +673,10 @@ regulator-state-mem { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy0 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi -@@ -466,3 +466,7 @@ regulator-state-mem { - }; - }; - }; -+ -+&tsadc { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -1131,6 +1131,10 @@ &sata0 { - status = "okay"; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy0 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts -@@ -376,6 +376,10 @@ &sdmmc { - status = "okay"; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -743,6 +743,10 @@ regulator-state-mem { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts -@@ -648,6 +648,10 @@ regulator-state-mem { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -601,6 +601,10 @@ regulator-state-mem { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -699,6 +699,10 @@ regulator-state-mem { - }; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &u2phy0 { - status = "okay"; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:34 +0400 -Subject: arm64: dts: rockchip: add passive GPU cooling on RK3588 - -As the GPU support on RK3588 has been merged upstream, along with OPP -values, add a corresponding cooling map for passive cooling using the GPU. - -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 +++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -2487,17 +2487,29 @@ center_crit: center-crit { - }; - - gpu_thermal: gpu-thermal { -- polling-delay-passive = <0>; -+ polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 5>; - - trips { -+ gpu_alert: gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; - gpu_crit: gpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; -+ cooling-maps { -+ map0 { -+ trip = <&gpu_alert>; -+ cooling-device = -+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; - }; - - npu_thermal: npu-thermal { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:36 +0400 -Subject: arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588 - -RK3588 chips allow for their CPU cores to be powered by a different -supply vs. their corresponding memory interfaces, and two of the -boards currently upstream do that (EVB1 and QuartzPro64). - -The voltage of the memory interface though has to match that of the -CPU cores that use it, which downstream kernels achieve by the means -of a custom cpufreq driver which adjusts both at the same time. - -It seems that regulator coupling is a more appropriate generic -interface for it, so this patch introduces coupling to affected -device trees to ensure that memory interface voltage is also updated -whenever cpufreq switches between CPU OPPs. - -Note that other boards, such as Radxa Rock 5B, define both the CPU -and memory interface regulators as aliases to the same DT node, so -this doesn't apply there. - -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++ - arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++ - 2 files changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -878,6 +878,8 @@ regulators { - vdd_cpu_big1_s0: dcdc-reg1 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -890,6 +892,8 @@ regulator-state-mem { - vdd_cpu_big0_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -902,6 +906,8 @@ regulator-state-mem { - vdd_cpu_lit_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; -@@ -926,6 +932,8 @@ regulator-state-mem { - vdd_cpu_big1_mem_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big1_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -939,6 +947,8 @@ regulator-state-mem { - vdd_cpu_big0_mem_s0: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big0_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -963,6 +973,8 @@ regulator-state-mem { - vdd_cpu_lit_mem_s0: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_lit_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts -@@ -833,6 +833,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -846,6 +848,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -859,6 +863,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; -@@ -885,6 +891,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { - regulator-name = "vdd_cpu_big1_mem_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big1_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -899,6 +907,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { - regulator-name = "vdd_cpu_big0_mem_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_big0_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; -@@ -925,6 +935,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { - regulator-name = "vdd_cpu_lit_mem_s0"; - regulator-always-on; - regulator-boot-on; -+ regulator-coupled-with = <&vdd_cpu_lit_s0>; -+ regulator-coupled-max-spread = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:37 +0400 -Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 - -By default the CPUs on RK3588 start up in a conservative performance -mode. Add frequency and voltage mappings to the device tree to enable -dynamic scaling via cpufreq. - -OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], -stripping them down to the minimum frequency and voltage combinations -as expected by the generic upstream cpufreq-dt driver, and also dropping -those OPPs that don't differ in voltage but only in frequency (keeping -the top frequency OPP in each case). - -Note that this patch ignores voltage scaling for the CPU memory -interface which the downstream kernel does through a custom cpufreq -driver, and which is why the downstream version has two sets of voltage -values for each OPP (the second one being meant for the memory -interface supply regulator). This is done instead via regulator -coupling between CPU and memory interface supplies on affected boards. - -This has been tested on Rock 5B with u-boot 2023.11 compiled from -Collabora's integration tree [2] with binary bl31 and appears to be -stable both under active cooling and passive cooling (with throttling) - -[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot - -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++ - 1 file changed, 122 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -97,6 +97,7 @@ cpu_l0: cpu@0 { - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; -+ operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; -@@ -116,6 +117,7 @@ cpu_l1: cpu@100 { - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; -@@ -135,6 +137,7 @@ cpu_l2: cpu@200 { - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; -@@ -154,6 +157,7 @@ cpu_l3: cpu@300 { - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; -+ operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; -@@ -175,6 +179,7 @@ cpu_b0: cpu@400 { - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; -+ operating-points-v2 = <&cluster1_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; -@@ -194,6 +199,7 @@ cpu_b1: cpu@500 { - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; -+ operating-points-v2 = <&cluster1_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; -@@ -215,6 +221,7 @@ cpu_b2: cpu@600 { - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; -+ operating-points-v2 = <&cluster2_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; -@@ -234,6 +241,7 @@ cpu_b3: cpu@700 { - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; -+ operating-points-v2 = <&cluster2_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; -@@ -348,6 +356,120 @@ l3_cache: l3-cache { - }; - }; - -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <675000 675000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <712500 712500 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <762500 762500 950000>; -+ clock-latency-ns = <40000>; -+ opp-suspend; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <850000 850000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <950000 950000 950000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <725000 725000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <762500 762500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <925000 925000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2208000000 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <987500 987500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ -+ cluster2_opp_table: opp-table-cluster2 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <675000 675000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <725000 725000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <762500 762500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2016000000 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <925000 925000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2208000000 { -+ opp-hz = /bits/ 64 <2208000000>; -+ opp-microvolt = <987500 987500 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ }; -+ - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0024-RK3588-Add-Crypto-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0024-RK3588-Add-Crypto-Support.patch deleted file mode 100644 index 06818ca18d93..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0024-RK3588-Add-Crypto-Support.patch +++ /dev/null @@ -1,2328 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 7 Nov 2023 15:55:27 +0000 -Subject: dt-bindings: crypto: add support for rockchip,crypto-rk3588 - -Add device tree binding documentation for the Rockchip cryptographic -offloader V2. - -Signed-off-by: Corentin Labbe ---- - Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml | 65 ++++++++++ - 1 file changed, 65 insertions(+) - -diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml -@@ -0,0 +1,65 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip cryptographic offloader V2 -+ -+maintainers: -+ - Corentin Labbe -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3568-crypto -+ - rockchip,rk3588-crypto -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 3 -+ -+ clock-names: -+ items: -+ - const: core -+ - const: a -+ - const: h -+ -+ resets: -+ minItems: 1 -+ -+ reset-names: -+ items: -+ - const: core -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ crypto@fe370000 { -+ compatible = "rockchip,rk3588-crypto"; -+ reg = <0xfe370000 0x4000>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, -+ <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ clock-names = "core", "a", "h"; -+ resets = <&scmi_reset SRST_CRYPTO_CORE>; -+ reset-names = "core"; -+ }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 7 Nov 2023 15:55:29 +0000 -Subject: ARM64: dts: rk3588: add crypto node - -The rk3588 has a crypto IP handled by the rk3588 crypto driver so adds a -node for it. - -Signed-off-by: Corentin Labbe ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1923,6 +1923,18 @@ sdhci: mmc@fe2e0000 { - status = "disabled"; - }; - -+ crypto: crypto@fe370000 { -+ compatible = "rockchip,rk3588-crypto"; -+ reg = <0x0 0xfe370000 0x0 0x2000>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, -+ <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ clock-names = "core", "aclk", "hclk"; -+ resets = <&scmi_reset SRST_CRYPTO_CORE>; -+ reset-names = "core"; -+ status = "okay"; -+ }; -+ - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 7 Nov 2023 15:55:30 +0000 -Subject: ARM64: dts: rk356x: add crypto node - -Both RK3566 and RK3568 have a crypto IP handled by the rk3588 crypto driver so adds a -node for it. - -Tested-by: Ricardo Pardini -Signed-off-by: Corentin Labbe ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1113,6 +1113,18 @@ sdhci: mmc@fe310000 { - status = "disabled"; - }; - -+ crypto: crypto@fe380000 { -+ compatible = "rockchip,rk3568-crypto"; -+ reg = <0x0 0xfe380000 0x0 0x2000>; -+ interrupts = ; -+ clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, -+ <&cru CLK_CRYPTO_NS_CORE>; -+ clock-names = "aclk", "hclk", "core"; -+ resets = <&cru SRST_CRYPTO_NS_CORE>; -+ reset-names = "core"; -+ status = "okay"; -+ }; -+ - i2s0_8ch: i2s@fe400000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe400000 0x0 0x1000>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 7 Nov 2023 15:55:31 +0000 -Subject: reset: rockchip: secure reset must be used by SCMI - -While working on the rk3588 crypto driver, I loose lot of time -understanding why resetting the IP failed. -This is due to RK3588_SECURECRU_RESET_OFFSET being in the secure world, -so impossible to operate on it from the kernel. -All resets in this block must be handled via SCMI call. - -Signed-off-by: Corentin Labbe ---- - drivers/clk/rockchip/rst-rk3588.c | 42 ------ - include/dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++----- - 2 files changed, 34 insertions(+), 76 deletions(-) - -diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c -index 111111111111..222222222222 100644 ---- a/drivers/clk/rockchip/rst-rk3588.c -+++ b/drivers/clk/rockchip/rst-rk3588.c -@@ -16,9 +16,6 @@ - /* 0xFD7C8000 + 0x0A00 */ - #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) - --/* 0xFD7D0000 + 0x0A00 */ --#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) -- - /* 0xFD7F0000 + 0x0A00 */ - #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) - -@@ -807,45 +804,6 @@ static const int rk3588_register_offset[] = { - RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), - RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), - RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), -- -- /* SECURECRU_SOFTRST_CON00 */ -- RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), -- RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), -- RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), -- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), -- -- /* SECURECRU_SOFTRST_CON01 */ -- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), -- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), -- RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), -- RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), -- RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), -- RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), -- RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), -- RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), -- RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), -- -- /* SECURECRU_SOFTRST_CON02 */ -- RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), -- RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), -- RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), -- RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), -- -- /* SECURECRU_SOFTRST_CON03 */ -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), -- RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), -- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), -- RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), -- RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), -- RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), - }; - - void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) -diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h -index 111111111111..222222222222 100644 ---- a/include/dt-bindings/reset/rockchip,rk3588-cru.h -+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h -@@ -716,40 +716,40 @@ - #define SRST_P_GPIO0 627 - #define SRST_GPIO0 628 - --#define SRST_A_SECURE_NS_BIU 629 --#define SRST_H_SECURE_NS_BIU 630 --#define SRST_A_SECURE_S_BIU 631 --#define SRST_H_SECURE_S_BIU 632 --#define SRST_P_SECURE_S_BIU 633 --#define SRST_CRYPTO_CORE 634 -- --#define SRST_CRYPTO_PKA 635 --#define SRST_CRYPTO_RNG 636 --#define SRST_A_CRYPTO 637 --#define SRST_H_CRYPTO 638 --#define SRST_KEYLADDER_CORE 639 --#define SRST_KEYLADDER_RNG 640 --#define SRST_A_KEYLADDER 641 --#define SRST_H_KEYLADDER 642 --#define SRST_P_OTPC_S 643 --#define SRST_OTPC_S 644 --#define SRST_WDT_S 645 -- --#define SRST_T_WDT_S 646 --#define SRST_H_BOOTROM 647 --#define SRST_A_DCF 648 --#define SRST_P_DCF 649 --#define SRST_H_BOOTROM_NS 650 --#define SRST_P_KEYLADDER 651 --#define SRST_H_TRNG_S 652 -- --#define SRST_H_TRNG_NS 653 --#define SRST_D_SDMMC_BUFFER 654 --#define SRST_H_SDMMC 655 --#define SRST_H_SDMMC_BUFFER 656 --#define SRST_SDMMC 657 --#define SRST_P_TRNG_CHK 658 --#define SRST_TRNG_S 659 -+#define SRST_A_SECURE_NS_BIU 10 -+#define SRST_H_SECURE_NS_BIU 11 -+#define SRST_A_SECURE_S_BIU 12 -+#define SRST_H_SECURE_S_BIU 13 -+#define SRST_P_SECURE_S_BIU 14 -+#define SRST_CRYPTO_CORE 15 -+ -+#define SRST_CRYPTO_PKA 16 -+#define SRST_CRYPTO_RNG 17 -+#define SRST_A_CRYPTO 18 -+#define SRST_H_CRYPTO 19 -+#define SRST_KEYLADDER_CORE 25 -+#define SRST_KEYLADDER_RNG 26 -+#define SRST_A_KEYLADDER 27 -+#define SRST_H_KEYLADDER 28 -+#define SRST_P_OTPC_S 29 -+#define SRST_OTPC_S 30 -+#define SRST_WDT_S 31 -+ -+#define SRST_T_WDT_S 32 -+#define SRST_H_BOOTROM 33 -+#define SRST_A_DCF 34 -+#define SRST_P_DCF 35 -+#define SRST_H_BOOTROM_NS 37 -+#define SRST_P_KEYLADDER 46 -+#define SRST_H_TRNG_S 47 -+ -+#define SRST_H_TRNG_NS 48 -+#define SRST_D_SDMMC_BUFFER 49 -+#define SRST_H_SDMMC 50 -+#define SRST_H_SDMMC_BUFFER 51 -+#define SRST_SDMMC 52 -+#define SRST_P_TRNG_CHK 53 -+#define SRST_TRNG_S 54 - - #define SRST_A_HDMIRX_BIU 660 - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Corentin Labbe -Date: Tue, 7 Nov 2023 15:55:32 +0000 -Subject: crypto: rockchip: add rk3588 driver - -RK3588 have a new crypto IP, this patch adds basic support for it. -Only hashes and cipher are handled for the moment. - -Signed-off-by: Corentin Labbe ---- - drivers/crypto/Kconfig | 29 + - drivers/crypto/rockchip/Makefile | 5 + - drivers/crypto/rockchip/rk2_crypto.c | 739 ++++++++++ - drivers/crypto/rockchip/rk2_crypto.h | 246 +++ - drivers/crypto/rockchip/rk2_crypto_ahash.c | 344 +++++ - drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++ - 6 files changed, 1939 insertions(+) - -diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA - Select this to enable Tegra Security Engine which accelerates various - AES encryption/decryption and HASH algorithms. - -+config CRYPTO_DEV_ROCKCHIP2 -+ tristate "Rockchip's cryptographic offloader V2" -+ depends on OF && ARCH_ROCKCHIP -+ depends on PM -+ select CRYPTO_ECB -+ select CRYPTO_CBC -+ select CRYPTO_AES -+ select CRYPTO_MD5 -+ select CRYPTO_SHA1 -+ select CRYPTO_SHA256 -+ select CRYPTO_SHA512 -+ select CRYPTO_SM3_GENERIC -+ select CRYPTO_HASH -+ select CRYPTO_SKCIPHER -+ select CRYPTO_ENGINE -+ -+ help -+ This driver interfaces with the hardware crypto offloader present -+ on RK3566, RK3568 and RK3588. -+ -+config CRYPTO_DEV_ROCKCHIP2_DEBUG -+ bool "Enable Rockchip V2 crypto stats" -+ depends on CRYPTO_DEV_ROCKCHIP2 -+ depends on DEBUG_FS -+ help -+ Say y to enable Rockchip crypto debug stats. -+ This will create /sys/kernel/debug/rk3588_crypto/stats for displaying -+ the number of requests per algorithm and other internal stats. -+ - config CRYPTO_DEV_ZYNQMP_AES - tristate "Support for Xilinx ZynqMP AES hw accelerator" - depends on ZYNQMP_FIRMWARE || COMPILE_TEST -diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/crypto/rockchip/Makefile -+++ b/drivers/crypto/rockchip/Makefile -@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o - rk_crypto-objs := rk3288_crypto.o \ - rk3288_crypto_skcipher.o \ - rk3288_crypto_ahash.o -+ -+obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o -+rk_crypto2-objs := rk2_crypto.o \ -+ rk2_crypto_skcipher.o \ -+ rk2_crypto_ahash.o -diff --git a/drivers/crypto/rockchip/rk2_crypto.c b/drivers/crypto/rockchip/rk2_crypto.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/crypto/rockchip/rk2_crypto.c -@@ -0,0 +1,739 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * hardware cryptographic offloader for RK3568/RK3588 SoC -+ * -+ * Copyright (c) 2022-2023, Corentin Labbe -+ */ -+ -+#include "rk2_crypto.h" -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static struct rockchip_ip rocklist = { -+ .dev_list = LIST_HEAD_INIT(rocklist.dev_list), -+ .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock), -+}; -+ -+struct rk2_crypto_dev *get_rk2_crypto(void) -+{ -+ struct rk2_crypto_dev *first; -+ -+ spin_lock(&rocklist.lock); -+ first = list_first_entry_or_null(&rocklist.dev_list, -+ struct rk2_crypto_dev, list); -+ list_rotate_left(&rocklist.dev_list); -+ spin_unlock(&rocklist.lock); -+ return first; -+} -+ -+static const struct rk2_variant rk3568_variant = { -+ .num_clks = 3, -+}; -+ -+static const struct rk2_variant rk3588_variant = { -+ .num_clks = 3, -+}; -+ -+static int rk2_crypto_get_clks(struct rk2_crypto_dev *dev) -+{ -+ int i, j, err; -+ unsigned long cr; -+ -+ dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks); -+ if (dev->num_clks < dev->variant->num_clks) { -+ dev_err(dev->dev, "Missing clocks, got %d instead of %d\n", -+ dev->num_clks, dev->variant->num_clks); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < dev->num_clks; i++) { -+ cr = clk_get_rate(dev->clks[i].clk); -+ for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) { -+ if (dev->variant->rkclks[j].max == 0) -+ continue; -+ if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id)) -+ continue; -+ if (cr > dev->variant->rkclks[j].max) { -+ err = clk_set_rate(dev->clks[i].clk, -+ dev->variant->rkclks[j].max); -+ if (err) -+ dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n", -+ dev->variant->rkclks[j].name, cr, -+ dev->variant->rkclks[j].max); -+ else -+ dev_info(dev->dev, "Downclocking %s from %lu to %lu\n", -+ dev->variant->rkclks[j].name, cr, -+ dev->variant->rkclks[j].max); -+ } -+ } -+ } -+ return 0; -+} -+ -+static int rk2_crypto_enable_clk(struct rk2_crypto_dev *dev) -+{ -+ int err; -+ -+ err = clk_bulk_prepare_enable(dev->num_clks, dev->clks); -+ if (err) -+ dev_err(dev->dev, "Could not enable clock clks\n"); -+ -+ return err; -+} -+ -+static void rk2_crypto_disable_clk(struct rk2_crypto_dev *dev) -+{ -+ clk_bulk_disable_unprepare(dev->num_clks, dev->clks); -+} -+ -+/* -+ * Power management strategy: The device is suspended until a request -+ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s. -+ */ -+static int rk2_crypto_pm_suspend(struct device *dev) -+{ -+ struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev); -+ -+ rk2_crypto_disable_clk(rkdev); -+ reset_control_assert(rkdev->rst); -+ -+ return 0; -+} -+ -+static int rk2_crypto_pm_resume(struct device *dev) -+{ -+ struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = rk2_crypto_enable_clk(rkdev); -+ if (ret) -+ return ret; -+ -+ reset_control_deassert(rkdev->rst); -+ return 0; -+} -+ -+static const struct dev_pm_ops rk2_crypto_pm_ops = { -+ SET_RUNTIME_PM_OPS(rk2_crypto_pm_suspend, rk2_crypto_pm_resume, NULL) -+}; -+ -+static int rk2_crypto_pm_init(struct rk2_crypto_dev *rkdev) -+{ -+ int err; -+ -+ pm_runtime_use_autosuspend(rkdev->dev); -+ pm_runtime_set_autosuspend_delay(rkdev->dev, 2000); -+ -+ err = pm_runtime_set_suspended(rkdev->dev); -+ if (err) -+ return err; -+ pm_runtime_enable(rkdev->dev); -+ return err; -+} -+ -+static void rk2_crypto_pm_exit(struct rk2_crypto_dev *rkdev) -+{ -+ pm_runtime_disable(rkdev->dev); -+} -+ -+static irqreturn_t rk2_crypto_irq_handle(int irq, void *dev_id) -+{ -+ struct rk2_crypto_dev *rkc = platform_get_drvdata(dev_id); -+ u32 v; -+ -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST); -+ writel(v, rkc->reg + RK2_CRYPTO_DMA_INT_ST); -+ -+ rkc->status = 1; -+ if (v & 0xF8) { -+ dev_warn(rkc->dev, "DMA Error\n"); -+ rkc->status = 0; -+ } -+ complete(&rkc->complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct rk2_crypto_template rk2_crypto_algs[] = { -+ { -+ .type = CRYPTO_ALG_TYPE_SKCIPHER, -+ .rk2_mode = RK2_CRYPTO_AES_ECB, -+ .alg.skcipher.base = { -+ .base.cra_name = "ecb(aes)", -+ .base.cra_driver_name = "ecb-aes-rk2", -+ .base.cra_priority = 300, -+ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, -+ .base.cra_blocksize = AES_BLOCK_SIZE, -+ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), -+ .base.cra_alignmask = 0x0f, -+ .base.cra_module = THIS_MODULE, -+ -+ .init = rk2_cipher_tfm_init, -+ .exit = rk2_cipher_tfm_exit, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .setkey = rk2_aes_setkey, -+ .encrypt = rk2_skcipher_encrypt, -+ .decrypt = rk2_skcipher_decrypt, -+ }, -+ .alg.skcipher.op = { -+ .do_one_request = rk2_cipher_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_SKCIPHER, -+ .rk2_mode = RK2_CRYPTO_AES_CBC, -+ .alg.skcipher.base = { -+ .base.cra_name = "cbc(aes)", -+ .base.cra_driver_name = "cbc-aes-rk2", -+ .base.cra_priority = 300, -+ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, -+ .base.cra_blocksize = AES_BLOCK_SIZE, -+ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), -+ .base.cra_alignmask = 0x0f, -+ .base.cra_module = THIS_MODULE, -+ -+ .init = rk2_cipher_tfm_init, -+ .exit = rk2_cipher_tfm_exit, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .setkey = rk2_aes_setkey, -+ .encrypt = rk2_skcipher_encrypt, -+ .decrypt = rk2_skcipher_decrypt, -+ }, -+ .alg.skcipher.op = { -+ .do_one_request = rk2_cipher_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_SKCIPHER, -+ .rk2_mode = RK2_CRYPTO_AES_XTS, -+ .is_xts = true, -+ .alg.skcipher.base = { -+ .base.cra_name = "xts(aes)", -+ .base.cra_driver_name = "xts-aes-rk2", -+ .base.cra_priority = 300, -+ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, -+ .base.cra_blocksize = AES_BLOCK_SIZE, -+ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), -+ .base.cra_alignmask = 0x0f, -+ .base.cra_module = THIS_MODULE, -+ -+ .init = rk2_cipher_tfm_init, -+ .exit = rk2_cipher_tfm_exit, -+ .min_keysize = AES_MIN_KEY_SIZE * 2, -+ .max_keysize = AES_MAX_KEY_SIZE * 2, -+ .ivsize = AES_BLOCK_SIZE, -+ .setkey = rk2_aes_xts_setkey, -+ .encrypt = rk2_skcipher_encrypt, -+ .decrypt = rk2_skcipher_decrypt, -+ }, -+ .alg.skcipher.op = { -+ .do_one_request = rk2_cipher_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_MD5, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = MD5_DIGEST_SIZE, -+ .statesize = sizeof(struct md5_state), -+ .base = { -+ .cra_name = "md5", -+ .cra_driver_name = "rk2-md5", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_SHA1, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = SHA1_DIGEST_SIZE, -+ .statesize = sizeof(struct sha1_state), -+ .base = { -+ .cra_name = "sha1", -+ .cra_driver_name = "rk2-sha1", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = SHA1_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_SHA256, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = SHA256_DIGEST_SIZE, -+ .statesize = sizeof(struct sha256_state), -+ .base = { -+ .cra_name = "sha256", -+ .cra_driver_name = "rk2-sha256", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = SHA256_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_SHA384, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = SHA384_DIGEST_SIZE, -+ .statesize = sizeof(struct sha512_state), -+ .base = { -+ .cra_name = "sha384", -+ .cra_driver_name = "rk2-sha384", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = SHA384_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_SHA512, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = SHA512_DIGEST_SIZE, -+ .statesize = sizeof(struct sha512_state), -+ .base = { -+ .cra_name = "sha512", -+ .cra_driver_name = "rk2-sha512", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = SHA512_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ }, -+ { -+ .type = CRYPTO_ALG_TYPE_AHASH, -+ .rk2_mode = RK2_CRYPTO_SM3, -+ .alg.hash.base = { -+ .init = rk2_ahash_init, -+ .update = rk2_ahash_update, -+ .final = rk2_ahash_final, -+ .finup = rk2_ahash_finup, -+ .export = rk2_ahash_export, -+ .import = rk2_ahash_import, -+ .digest = rk2_ahash_digest, -+ .init_tfm = rk2_hash_init_tfm, -+ .exit_tfm = rk2_hash_exit_tfm, -+ .halg = { -+ .digestsize = SM3_DIGEST_SIZE, -+ .statesize = sizeof(struct sm3_state), -+ .base = { -+ .cra_name = "sm3", -+ .cra_driver_name = "rk2-sm3", -+ .cra_priority = 300, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK, -+ .cra_blocksize = SM3_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), -+ .cra_module = THIS_MODULE, -+ } -+ } -+ }, -+ .alg.hash.op = { -+ .do_one_request = rk2_hash_run, -+ }, -+ }, -+}; -+ -+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG -+static int rk2_crypto_debugfs_stats_show(struct seq_file *seq, void *v) -+{ -+ struct rk2_crypto_dev *rkc; -+ unsigned int i; -+ -+ spin_lock(&rocklist.lock); -+ list_for_each_entry(rkc, &rocklist.dev_list, list) { -+ seq_printf(seq, "%s %s requests: %lu\n", -+ dev_driver_string(rkc->dev), dev_name(rkc->dev), -+ rkc->nreq); -+ } -+ spin_unlock(&rocklist.lock); -+ -+ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { -+ if (!rk2_crypto_algs[i].dev) -+ continue; -+ switch (rk2_crypto_algs[i].type) { -+ case CRYPTO_ALG_TYPE_SKCIPHER: -+ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", -+ rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name, -+ rk2_crypto_algs[i].alg.skcipher.base.base.cra_name, -+ rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb); -+ seq_printf(seq, "\tfallback due to length: %lu\n", -+ rk2_crypto_algs[i].stat_fb_len); -+ seq_printf(seq, "\tfallback due to alignment: %lu\n", -+ rk2_crypto_algs[i].stat_fb_align); -+ seq_printf(seq, "\tfallback due to SGs: %lu\n", -+ rk2_crypto_algs[i].stat_fb_sgdiff); -+ break; -+ case CRYPTO_ALG_TYPE_AHASH: -+ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", -+ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, -+ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name, -+ rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb); -+ break; -+ } -+ } -+ return 0; -+} -+ -+static int rk2_crypto_debugfs_info_show(struct seq_file *seq, void *d) -+{ -+ struct rk2_crypto_dev *rkc; -+ u32 v; -+ -+ spin_lock(&rocklist.lock); -+ list_for_each_entry(rkc, &rocklist.dev_list, list) { -+ v = readl(rkc->reg + RK2_CRYPTO_CLK_CTL); -+ seq_printf(seq, "CRYPTO_CLK_CTL %x\n", v); -+ v = readl(rkc->reg + RK2_CRYPTO_RST_CTL); -+ seq_printf(seq, "CRYPTO_RST_CTL %x\n", v); -+ -+ v = readl(rkc->reg + CRYPTO_AES_VERSION); -+ seq_printf(seq, "CRYPTO_AES_VERSION %x\n", v); -+ if (v & BIT(17)) -+ seq_puts(seq, "AES 192\n"); -+ -+ v = readl(rkc->reg + CRYPTO_DES_VERSION); -+ seq_printf(seq, "CRYPTO_DES_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_SM4_VERSION); -+ seq_printf(seq, "CRYPTO_SM4_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_HASH_VERSION); -+ seq_printf(seq, "CRYPTO_HASH_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_HMAC_VERSION); -+ seq_printf(seq, "CRYPTO_HMAC_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_RNG_VERSION); -+ seq_printf(seq, "CRYPTO_RNG_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_PKA_VERSION); -+ seq_printf(seq, "CRYPTO_PKA_VERSION %x\n", v); -+ v = readl(rkc->reg + CRYPTO_CRYPTO_VERSION); -+ seq_printf(seq, "CRYPTO_CRYPTO_VERSION %x\n", v); -+ } -+ spin_unlock(&rocklist.lock); -+ -+ return 0; -+} -+ -+DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_stats); -+DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_info); -+ -+#endif -+ -+static void register_debugfs(struct rk2_crypto_dev *crypto_dev) -+{ -+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG -+ /* Ignore error of debugfs */ -+ rocklist.dbgfs_dir = debugfs_create_dir("rk2_crypto", NULL); -+ rocklist.dbgfs_stats = debugfs_create_file("stats", 0440, -+ rocklist.dbgfs_dir, -+ &rocklist, -+ &rk2_crypto_debugfs_stats_fops); -+ rocklist.dbgfs_stats = debugfs_create_file("info", 0440, -+ rocklist.dbgfs_dir, -+ &rocklist, -+ &rk2_crypto_debugfs_info_fops); -+#endif -+} -+ -+static int rk2_crypto_register(struct rk2_crypto_dev *rkc) -+{ -+ unsigned int i, k; -+ int err = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { -+ rk2_crypto_algs[i].dev = rkc; -+ switch (rk2_crypto_algs[i].type) { -+ case CRYPTO_ALG_TYPE_SKCIPHER: -+ dev_info(rkc->dev, "Register %s as %s\n", -+ rk2_crypto_algs[i].alg.skcipher.base.base.cra_name, -+ rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name); -+ err = crypto_engine_register_skcipher(&rk2_crypto_algs[i].alg.skcipher); -+ break; -+ case CRYPTO_ALG_TYPE_AHASH: -+ dev_info(rkc->dev, "Register %s as %s %d\n", -+ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name, -+ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, i); -+ err = crypto_engine_register_ahash(&rk2_crypto_algs[i].alg.hash); -+ break; -+ default: -+ dev_err(rkc->dev, "unknown algorithm\n"); -+ } -+ if (err) -+ goto err_cipher_algs; -+ } -+ return 0; -+ -+err_cipher_algs: -+ for (k = 0; k < i; k++) { -+ if (rk2_crypto_algs[k].type == CRYPTO_ALG_TYPE_SKCIPHER) -+ crypto_engine_unregister_skcipher(&rk2_crypto_algs[k].alg.skcipher); -+ else -+ crypto_engine_unregister_ahash(&rk2_crypto_algs[k].alg.hash); -+ } -+ return err; -+} -+ -+static void rk2_crypto_unregister(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { -+ if (rk2_crypto_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER) -+ crypto_engine_unregister_skcipher(&rk2_crypto_algs[i].alg.skcipher); -+ else -+ crypto_engine_unregister_ahash(&rk2_crypto_algs[i].alg.hash); -+ } -+} -+ -+static const struct of_device_id crypto_of_id_table[] = { -+ { .compatible = "rockchip,rk3568-crypto", -+ .data = &rk3568_variant, -+ }, -+ { .compatible = "rockchip,rk3588-crypto", -+ .data = &rk3588_variant, -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, crypto_of_id_table); -+ -+static int rk2_crypto_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rk2_crypto_dev *rkc, *first; -+ int err = 0; -+ -+ rkc = devm_kzalloc(&pdev->dev, sizeof(*rkc), GFP_KERNEL); -+ if (!rkc) { -+ err = -ENOMEM; -+ goto err_crypto; -+ } -+ -+ rkc->dev = &pdev->dev; -+ platform_set_drvdata(pdev, rkc); -+ -+ rkc->variant = of_device_get_match_data(&pdev->dev); -+ if (!rkc->variant) { -+ dev_err(&pdev->dev, "Missing variant\n"); -+ return -EINVAL; -+ } -+ -+ rkc->rst = devm_reset_control_array_get_exclusive(dev); -+ if (IS_ERR(rkc->rst)) { -+ err = PTR_ERR(rkc->rst); -+ dev_err(&pdev->dev, "Fail to get resets err=%d\n", err); -+ goto err_crypto; -+ } -+ -+ rkc->tl = dma_alloc_coherent(rkc->dev, -+ sizeof(struct rk2_crypto_lli) * MAX_LLI, -+ &rkc->t_phy, GFP_KERNEL); -+ if (!rkc->tl) { -+ dev_err(rkc->dev, "Cannot get DMA memory for task\n"); -+ err = -ENOMEM; -+ goto err_crypto; -+ } -+ -+ reset_control_assert(rkc->rst); -+ usleep_range(10, 20); -+ reset_control_deassert(rkc->rst); -+ -+ rkc->reg = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(rkc->reg)) { -+ err = PTR_ERR(rkc->reg); -+ dev_err(&pdev->dev, "Fail to get resources\n"); -+ goto err_crypto; -+ } -+ -+ err = rk2_crypto_get_clks(rkc); -+ if (err) -+ goto err_crypto; -+ -+ rkc->irq = platform_get_irq(pdev, 0); -+ if (rkc->irq < 0) { -+ dev_err(&pdev->dev, "control Interrupt is not available.\n"); -+ err = rkc->irq; -+ goto err_crypto; -+ } -+ -+ err = devm_request_irq(&pdev->dev, rkc->irq, -+ rk2_crypto_irq_handle, IRQF_SHARED, -+ "rk-crypto", pdev); -+ -+ if (err) { -+ dev_err(&pdev->dev, "irq request failed.\n"); -+ goto err_crypto; -+ } -+ -+ rkc->engine = crypto_engine_alloc_init(&pdev->dev, true); -+ crypto_engine_start(rkc->engine); -+ init_completion(&rkc->complete); -+ -+ err = rk2_crypto_pm_init(rkc); -+ if (err) -+ goto err_pm; -+ -+ err = pm_runtime_resume_and_get(&pdev->dev); -+ -+ spin_lock(&rocklist.lock); -+ first = list_first_entry_or_null(&rocklist.dev_list, -+ struct rk2_crypto_dev, list); -+ list_add_tail(&rkc->list, &rocklist.dev_list); -+ spin_unlock(&rocklist.lock); -+ -+ if (!first) { -+ dev_info(dev, "Registers crypto algos\n"); -+ err = rk2_crypto_register(rkc); -+ if (err) { -+ dev_err(dev, "Fail to register crypto algorithms"); -+ goto err_register_alg; -+ } -+ -+ register_debugfs(rkc); -+ } -+ -+ return 0; -+ -+err_register_alg: -+ rk2_crypto_pm_exit(rkc); -+err_pm: -+ crypto_engine_exit(rkc->engine); -+err_crypto: -+ dev_err(dev, "Crypto Accelerator not successfully registered\n"); -+ return err; -+} -+ -+static int rk2_crypto_remove(struct platform_device *pdev) -+{ -+ struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev); -+ struct rk2_crypto_dev *first; -+ -+ spin_lock_bh(&rocklist.lock); -+ list_del(&rkc->list); -+ first = list_first_entry_or_null(&rocklist.dev_list, -+ struct rk2_crypto_dev, list); -+ spin_unlock_bh(&rocklist.lock); -+ -+ if (!first) { -+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG -+ debugfs_remove_recursive(rocklist.dbgfs_dir); -+#endif -+ rk2_crypto_unregister(); -+ } -+ rk2_crypto_pm_exit(rkc); -+ crypto_engine_exit(rkc->engine); -+ return 0; -+} -+ -+static struct platform_driver crypto_driver = { -+ .probe = rk2_crypto_probe, -+ .remove = rk2_crypto_remove, -+ .driver = { -+ .name = "rk2-crypto", -+ .pm = &rk2_crypto_pm_ops, -+ .of_match_table = crypto_of_id_table, -+ }, -+}; -+ -+module_platform_driver(crypto_driver); -+ -+MODULE_DESCRIPTION("Rockchip Crypto Engine cryptographic offloader"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Corentin Labbe "); -diff --git a/drivers/crypto/rockchip/rk2_crypto.h b/drivers/crypto/rockchip/rk2_crypto.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/crypto/rockchip/rk2_crypto.h -@@ -0,0 +1,246 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RK2_CRYPTO_CLK_CTL 0x0000 -+#define RK2_CRYPTO_RST_CTL 0x0004 -+ -+#define RK2_CRYPTO_DMA_INT_EN 0x0008 -+/* values for RK2_CRYPTO_DMA_INT_EN */ -+#define RK2_CRYPTO_DMA_INT_LISTDONE BIT(0) -+ -+#define RK2_CRYPTO_DMA_INT_ST 0x000C -+/* values in RK2_CRYPTO_DMA_INT_ST are the same than in RK2_CRYPTO_DMA_INT_EN */ -+ -+#define RK2_CRYPTO_DMA_CTL 0x0010 -+#define RK2_CRYPTO_DMA_CTL_START BIT(0) -+ -+#define RK2_CRYPTO_DMA_LLI_ADDR 0x0014 -+#define RK2_CRYPTO_DMA_ST 0x0018 -+#define RK2_CRYPTO_DMA_STATE 0x001C -+#define RK2_CRYPTO_DMA_LLI_RADDR 0x0020 -+#define RK2_CRYPTO_DMA_SRC_RADDR 0x0024 -+#define RK2_CRYPTO_DMA_DST_WADDR 0x0028 -+#define RK2_CRYPTO_DMA_ITEM_ID 0x002C -+ -+#define RK2_CRYPTO_FIFO_CTL 0x0040 -+ -+#define RK2_CRYPTO_BC_CTL 0x0044 -+#define RK2_CRYPTO_AES (0 << 8) -+#define RK2_CRYPTO_MODE_ECB (0 << 4) -+#define RK2_CRYPTO_MODE_CBC (1 << 4) -+#define RK2_CRYPTO_XTS (6 << 4) -+ -+#define RK2_CRYPTO_HASH_CTL 0x0048 -+#define RK2_CRYPTO_HW_PAD BIT(2) -+#define RK2_CRYPTO_SHA1 (0 << 4) -+#define RK2_CRYPTO_MD5 (1 << 4) -+#define RK2_CRYPTO_SHA224 (3 << 4) -+#define RK2_CRYPTO_SHA256 (2 << 4) -+#define RK2_CRYPTO_SHA384 (9 << 4) -+#define RK2_CRYPTO_SHA512 (8 << 4) -+#define RK2_CRYPTO_SM3 (4 << 4) -+ -+#define RK2_CRYPTO_AES_ECB (RK2_CRYPTO_AES | RK2_CRYPTO_MODE_ECB) -+#define RK2_CRYPTO_AES_CBC (RK2_CRYPTO_AES | RK2_CRYPTO_MODE_CBC) -+#define RK2_CRYPTO_AES_XTS (RK2_CRYPTO_AES | RK2_CRYPTO_XTS) -+#define RK2_CRYPTO_AES_CTR_MODE 3 -+#define RK2_CRYPTO_AES_128BIT_key (0 << 2) -+#define RK2_CRYPTO_AES_192BIT_key (1 << 2) -+#define RK2_CRYPTO_AES_256BIT_key (2 << 2) -+ -+#define RK2_CRYPTO_DEC BIT(1) -+#define RK2_CRYPTO_ENABLE BIT(0) -+ -+#define RK2_CRYPTO_CIPHER_ST 0x004C -+#define RK2_CRYPTO_CIPHER_STATE 0x0050 -+ -+#define RK2_CRYPTO_CH0_IV_0 0x0100 -+ -+#define RK2_CRYPTO_KEY0 0x0180 -+#define RK2_CRYPTO_KEY1 0x0184 -+#define RK2_CRYPTO_KEY2 0x0188 -+#define RK2_CRYPTO_KEY3 0x018C -+#define RK2_CRYPTO_KEY4 0x0190 -+#define RK2_CRYPTO_KEY5 0x0194 -+#define RK2_CRYPTO_KEY6 0x0198 -+#define RK2_CRYPTO_KEY7 0x019C -+#define RK2_CRYPTO_CH4_KEY0 0x01c0 -+ -+#define RK2_CRYPTO_CH0_PC_LEN_0 0x0280 -+ -+#define RK2_CRYPTO_CH0_IV_LEN 0x0300 -+ -+#define RK2_CRYPTO_HASH_DOUT_0 0x03A0 -+#define RK2_CRYPTO_HASH_VALID 0x03E4 -+ -+#define RK2_CRYPTO_TRNG_CTL 0x0400 -+#define RK2_CRYPTO_TRNG_START BIT(0) -+#define RK2_CRYPTO_TRNG_ENABLE BIT(1) -+#define RK2_CRYPTO_TRNG_256 (0x3 << 4) -+#define RK2_CRYPTO_TRNG_SAMPLE_CNT 0x0404 -+#define RK2_CRYPTO_TRNG_DOUT 0x0410 -+ -+#define CRYPTO_AES_VERSION 0x0680 -+#define CRYPTO_DES_VERSION 0x0684 -+#define CRYPTO_SM4_VERSION 0x0688 -+#define CRYPTO_HASH_VERSION 0x068C -+#define CRYPTO_HMAC_VERSION 0x0690 -+#define CRYPTO_RNG_VERSION 0x0694 -+#define CRYPTO_PKA_VERSION 0x0698 -+#define CRYPTO_CRYPTO_VERSION 0x06F0 -+ -+#define RK2_LLI_DMA_CTRL_SRC_INT BIT(10) -+#define RK2_LLI_DMA_CTRL_DST_INT BIT(9) -+#define RK2_LLI_DMA_CTRL_LIST_INT BIT(8) -+#define RK2_LLI_DMA_CTRL_LAST BIT(0) -+ -+#define RK2_LLI_STRING_LAST BIT(2) -+#define RK2_LLI_STRING_FIRST BIT(1) -+#define RK2_LLI_CIPHER_START BIT(0) -+ -+#define RK2_MAX_CLKS 4 -+ -+#define MAX_LLI 20 -+ -+struct rk2_crypto_lli { -+ __le32 src_addr; -+ __le32 src_len; -+ __le32 dst_addr; -+ __le32 dst_len; -+ __le32 user; -+ __le32 iv; -+ __le32 dma_ctrl; -+ __le32 next; -+}; -+ -+/* -+ * struct rockchip_ip - struct for managing a list of RK crypto instance -+ * @dev_list: Used for doing a list of rk2_crypto_dev -+ * @lock: Control access to dev_list -+ * @dbgfs_dir: Debugfs dentry for statistic directory -+ * @dbgfs_stats: Debugfs dentry for statistic counters -+ */ -+struct rockchip_ip { -+ struct list_head dev_list; -+ spinlock_t lock; /* Control access to dev_list */ -+ struct dentry *dbgfs_dir; -+ struct dentry *dbgfs_stats; -+}; -+ -+struct rk2_clks { -+ const char *name; -+ unsigned long max; -+}; -+ -+struct rk2_variant { -+ int num_clks; -+ struct rk2_clks rkclks[RK2_MAX_CLKS]; -+}; -+ -+struct rk2_crypto_dev { -+ struct list_head list; -+ struct device *dev; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct reset_control *rst; -+ void __iomem *reg; -+ int irq; -+ const struct rk2_variant *variant; -+ unsigned long nreq; -+ struct crypto_engine *engine; -+ struct completion complete; -+ int status; -+ struct rk2_crypto_lli *tl; -+ dma_addr_t t_phy; -+}; -+ -+/* the private variable of hash */ -+struct rk2_ahash_ctx { -+ /* for fallback */ -+ struct crypto_ahash *fallback_tfm; -+}; -+ -+/* the private variable of hash for fallback */ -+struct rk2_ahash_rctx { -+ struct rk2_crypto_dev *dev; -+ struct ahash_request fallback_req; -+ u32 mode; -+ int nrsgs; -+}; -+ -+/* the private variable of cipher */ -+struct rk2_cipher_ctx { -+ unsigned int keylen; -+ u8 key[AES_MAX_KEY_SIZE * 2]; -+ u8 iv[AES_BLOCK_SIZE]; -+ struct crypto_skcipher *fallback_tfm; -+}; -+ -+struct rk2_cipher_rctx { -+ struct rk2_crypto_dev *dev; -+ u8 backup_iv[AES_BLOCK_SIZE]; -+ u32 mode; -+ struct skcipher_request fallback_req; // keep at the end -+}; -+ -+struct rk2_crypto_template { -+ u32 type; -+ u32 rk2_mode; -+ bool is_xts; -+ struct rk2_crypto_dev *dev; -+ union { -+ struct skcipher_engine_alg skcipher; -+ struct ahash_engine_alg hash; -+ } alg; -+ unsigned long stat_req; -+ unsigned long stat_fb; -+ unsigned long stat_fb_len; -+ unsigned long stat_fb_sglen; -+ unsigned long stat_fb_align; -+ unsigned long stat_fb_sgdiff; -+}; -+ -+struct rk2_crypto_dev *get_rk2_crypto(void); -+int rk2_cipher_run(struct crypto_engine *engine, void *async_req); -+int rk2_hash_run(struct crypto_engine *engine, void *breq); -+ -+int rk2_cipher_tfm_init(struct crypto_skcipher *tfm); -+void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm); -+int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, -+ unsigned int keylen); -+int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key, -+ unsigned int keylen); -+int rk2_skcipher_encrypt(struct skcipher_request *req); -+int rk2_skcipher_decrypt(struct skcipher_request *req); -+int rk2_aes_ecb_encrypt(struct skcipher_request *req); -+int rk2_aes_ecb_decrypt(struct skcipher_request *req); -+int rk2_aes_cbc_encrypt(struct skcipher_request *req); -+int rk2_aes_cbc_decrypt(struct skcipher_request *req); -+ -+int rk2_ahash_init(struct ahash_request *req); -+int rk2_ahash_update(struct ahash_request *req); -+int rk2_ahash_final(struct ahash_request *req); -+int rk2_ahash_finup(struct ahash_request *req); -+int rk2_ahash_import(struct ahash_request *req, const void *in); -+int rk2_ahash_export(struct ahash_request *req, void *out); -+int rk2_ahash_digest(struct ahash_request *req); -+int rk2_hash_init_tfm(struct crypto_ahash *tfm); -+void rk2_hash_exit_tfm(struct crypto_ahash *tfm); -diff --git a/drivers/crypto/rockchip/rk2_crypto_ahash.c b/drivers/crypto/rockchip/rk2_crypto_ahash.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/crypto/rockchip/rk2_crypto_ahash.c -@@ -0,0 +1,344 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Crypto offloader support for Rockchip RK3568/RK3588 -+ * -+ * Copyright (c) 2022-2023 Corentin Labbe -+ */ -+#include -+#include -+#include "rk2_crypto.h" -+ -+static bool rk2_ahash_need_fallback(struct ahash_request *areq) -+{ -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); -+ struct ahash_alg *alg = crypto_ahash_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); -+ struct scatterlist *sg; -+ -+ sg = areq->src; -+ while (sg) { -+ if (!IS_ALIGNED(sg->offset, sizeof(u32))) { -+ algt->stat_fb_align++; -+ return true; -+ } -+ if (sg->length % 4) { -+ algt->stat_fb_sglen++; -+ return true; -+ } -+ sg = sg_next(sg); -+ } -+ return false; -+} -+ -+static int rk2_ahash_digest_fb(struct ahash_request *areq) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); -+ struct rk2_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm); -+ struct ahash_alg *alg = crypto_ahash_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); -+ -+ algt->stat_fb++; -+ -+ ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm); -+ rctx->fallback_req.base.flags = areq->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ -+ rctx->fallback_req.nbytes = areq->nbytes; -+ rctx->fallback_req.src = areq->src; -+ rctx->fallback_req.result = areq->result; -+ -+ return crypto_ahash_digest(&rctx->fallback_req); -+} -+ -+static int zero_message_process(struct ahash_request *req) -+{ -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct ahash_alg *alg = crypto_ahash_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); -+ int digestsize = crypto_ahash_digestsize(tfm); -+ -+ switch (algt->rk2_mode) { -+ case RK2_CRYPTO_SHA1: -+ memcpy(req->result, sha1_zero_message_hash, digestsize); -+ break; -+ case RK2_CRYPTO_SHA256: -+ memcpy(req->result, sha256_zero_message_hash, digestsize); -+ break; -+ case RK2_CRYPTO_SHA384: -+ memcpy(req->result, sha384_zero_message_hash, digestsize); -+ break; -+ case RK2_CRYPTO_SHA512: -+ memcpy(req->result, sha512_zero_message_hash, digestsize); -+ break; -+ case RK2_CRYPTO_MD5: -+ memcpy(req->result, md5_zero_message_hash, digestsize); -+ break; -+ case RK2_CRYPTO_SM3: -+ memcpy(req->result, sm3_zero_message_hash, digestsize); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int rk2_ahash_init(struct ahash_request *req) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ -+ return crypto_ahash_init(&rctx->fallback_req); -+} -+ -+int rk2_ahash_update(struct ahash_request *req) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ rctx->fallback_req.nbytes = req->nbytes; -+ rctx->fallback_req.src = req->src; -+ -+ return crypto_ahash_update(&rctx->fallback_req); -+} -+ -+int rk2_ahash_final(struct ahash_request *req) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ rctx->fallback_req.result = req->result; -+ -+ return crypto_ahash_final(&rctx->fallback_req); -+} -+ -+int rk2_ahash_finup(struct ahash_request *req) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ -+ rctx->fallback_req.nbytes = req->nbytes; -+ rctx->fallback_req.src = req->src; -+ rctx->fallback_req.result = req->result; -+ -+ return crypto_ahash_finup(&rctx->fallback_req); -+} -+ -+int rk2_ahash_import(struct ahash_request *req, const void *in) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ -+ return crypto_ahash_import(&rctx->fallback_req, in); -+} -+ -+int rk2_ahash_export(struct ahash_request *req, void *out) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); -+ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); -+ -+ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); -+ rctx->fallback_req.base.flags = req->base.flags & -+ CRYPTO_TFM_REQ_MAY_SLEEP; -+ -+ return crypto_ahash_export(&rctx->fallback_req, out); -+} -+ -+int rk2_ahash_digest(struct ahash_request *req) -+{ -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); -+ struct rk2_crypto_dev *dev; -+ struct crypto_engine *engine; -+ -+ if (rk2_ahash_need_fallback(req)) -+ return rk2_ahash_digest_fb(req); -+ -+ if (!req->nbytes) -+ return zero_message_process(req); -+ -+ dev = get_rk2_crypto(); -+ -+ rctx->dev = dev; -+ engine = dev->engine; -+ -+ return crypto_transfer_hash_request_to_engine(engine, req); -+} -+ -+static int rk2_hash_prepare(struct crypto_engine *engine, void *breq) -+{ -+ struct ahash_request *areq = container_of(breq, struct ahash_request, base); -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); -+ struct rk2_crypto_dev *rkc = rctx->dev; -+ int ret; -+ -+ ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); -+ if (ret <= 0) -+ return -EINVAL; -+ -+ rctx->nrsgs = ret; -+ -+ return 0; -+} -+ -+static void rk2_hash_unprepare(struct crypto_engine *engine, void *breq) -+{ -+ struct ahash_request *areq = container_of(breq, struct ahash_request, base); -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); -+ struct rk2_crypto_dev *rkc = rctx->dev; -+ -+ dma_unmap_sg(rkc->dev, areq->src, rctx->nrsgs, DMA_TO_DEVICE); -+} -+ -+int rk2_hash_run(struct crypto_engine *engine, void *breq) -+{ -+ struct ahash_request *areq = container_of(breq, struct ahash_request, base); -+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); -+ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); -+ struct ahash_alg *alg = crypto_ahash_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); -+ struct scatterlist *sgs = areq->src; -+ struct rk2_crypto_dev *rkc = rctx->dev; -+ struct rk2_crypto_lli *dd = &rkc->tl[0]; -+ int ddi = 0; -+ int err = 0; -+ unsigned int len = areq->nbytes; -+ unsigned int todo; -+ u32 v; -+ int i; -+ -+ err = rk2_hash_prepare(engine, breq); -+ -+ err = pm_runtime_resume_and_get(rkc->dev); -+ if (err) -+ return err; -+ -+ dev_dbg(rkc->dev, "%s %s len=%d\n", __func__, -+ crypto_tfm_alg_name(areq->base.tfm), areq->nbytes); -+ -+ algt->stat_req++; -+ rkc->nreq++; -+ -+ rctx->mode = algt->rk2_mode; -+ rctx->mode |= 0xffff0000; -+ rctx->mode |= RK2_CRYPTO_ENABLE | RK2_CRYPTO_HW_PAD; -+ writel(rctx->mode, rkc->reg + RK2_CRYPTO_HASH_CTL); -+ -+ while (sgs && len > 0) { -+ dd = &rkc->tl[ddi]; -+ -+ todo = min(sg_dma_len(sgs), len); -+ dd->src_addr = sg_dma_address(sgs); -+ dd->src_len = todo; -+ dd->dst_addr = 0; -+ dd->dst_len = 0; -+ dd->dma_ctrl = ddi << 24; -+ dd->iv = 0; -+ dd->next = rkc->t_phy + sizeof(struct rk2_crypto_lli) * (ddi + 1); -+ -+ if (ddi == 0) -+ dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST; -+ else -+ dd->user = 0; -+ -+ len -= todo; -+ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_SRC_INT; -+ if (len == 0) { -+ dd->user |= RK2_LLI_STRING_LAST; -+ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_LAST; -+ } -+ dev_dbg(rkc->dev, "HASH SG %d sglen=%d user=%x dma=%x mode=%x len=%d todo=%d phy=%llx\n", -+ ddi, sgs->length, dd->user, dd->dma_ctrl, rctx->mode, len, todo, rkc->t_phy); -+ -+ sgs = sg_next(sgs); -+ ddi++; -+ } -+ dd->next = 1; -+ writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN); -+ -+ writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR); -+ -+ reinit_completion(&rkc->complete); -+ rkc->status = 0; -+ -+ writel(RK2_CRYPTO_DMA_CTL_START | RK2_CRYPTO_DMA_CTL_START << 16, rkc->reg + RK2_CRYPTO_DMA_CTL); -+ -+ wait_for_completion_interruptible_timeout(&rkc->complete, -+ msecs_to_jiffies(2000)); -+ if (!rkc->status) { -+ dev_err(rkc->dev, "DMA timeout\n"); -+ err = -EFAULT; -+ goto theend; -+ } -+ -+ readl_poll_timeout_atomic(rkc->reg + RK2_CRYPTO_HASH_VALID, v, v == 1, -+ 10, 1000); -+ -+ for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { -+ v = readl(rkc->reg + RK2_CRYPTO_HASH_DOUT_0 + i * 4); -+ put_unaligned_le32(be32_to_cpu(v), areq->result + i * 4); -+ } -+ -+theend: -+ pm_runtime_put_autosuspend(rkc->dev); -+ -+ rk2_hash_unprepare(engine, breq); -+ -+ local_bh_disable(); -+ crypto_finalize_hash_request(engine, breq, err); -+ local_bh_enable(); -+ -+ return 0; -+} -+ -+int rk2_hash_init_tfm(struct crypto_ahash *tfm) -+{ -+ struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm); -+ const char *alg_name = crypto_ahash_alg_name(tfm); -+ struct ahash_alg *alg = crypto_ahash_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); -+ -+ /* for fallback */ -+ tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, -+ CRYPTO_ALG_NEED_FALLBACK); -+ if (IS_ERR(tctx->fallback_tfm)) { -+ dev_err(algt->dev->dev, "Could not load fallback driver.\n"); -+ return PTR_ERR(tctx->fallback_tfm); -+ } -+ -+ crypto_ahash_set_reqsize(tfm, -+ sizeof(struct rk2_ahash_rctx) + -+ crypto_ahash_reqsize(tctx->fallback_tfm)); -+ return 0; -+} -+ -+void rk2_hash_exit_tfm(struct crypto_ahash *tfm) -+{ -+ struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm); -+ -+ crypto_free_ahash(tctx->fallback_tfm); -+} -diff --git a/drivers/crypto/rockchip/rk2_crypto_skcipher.c b/drivers/crypto/rockchip/rk2_crypto_skcipher.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/crypto/rockchip/rk2_crypto_skcipher.c -@@ -0,0 +1,576 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * hardware cryptographic offloader for RK3568/RK3588 SoC -+ * -+ * Copyright (c) 2022-2023 Corentin Labbe -+ */ -+#include -+#include "rk2_crypto.h" -+ -+static void rk2_print(struct rk2_crypto_dev *rkc) -+{ -+ u32 v; -+ -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_ST); -+ dev_info(rkc->dev, "DMA_ST %x\n", v); -+ switch (v) { -+ case 0: -+ dev_info(rkc->dev, "DMA_ST: DMA IDLE\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "DMA_ST: DMA BUSY\n"); -+ break; -+ default: -+ dev_err(rkc->dev, "DMA_ST: invalid value\n"); -+ } -+ -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_STATE); -+ dev_info(rkc->dev, "DMA_STATE %x\n", v); -+ -+ switch (v & 0x3) { -+ case 0: -+ dev_info(rkc->dev, "DMA_STATE: DMA DST IDLE\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "DMA_STATE: DMA DST LOAD\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "DMA_STATE: DMA DST WORK\n"); -+ break; -+ default: -+ dev_err(rkc->dev, "DMA DST invalid\n"); -+ break; -+ } -+ switch (v & 0xC) { -+ case 0: -+ dev_info(rkc->dev, "DMA_STATE: DMA SRC IDLE\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "DMA_STATE: DMA SRC LOAD\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "DMA_STATE: DMA SRC WORK\n"); -+ break; -+ default: -+ dev_err(rkc->dev, "DMA_STATE: DMA SRC invalid\n"); -+ break; -+ } -+ switch (v & 0x30) { -+ case 0: -+ dev_info(rkc->dev, "DMA_STATE: DMA LLI IDLE\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "DMA_STATE: DMA LLI LOAD\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "DMA LLI WORK\n"); -+ break; -+ default: -+ dev_err(rkc->dev, "DMA LLI invalid\n"); -+ break; -+ } -+ -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_LLI_RADDR); -+ dev_info(rkc->dev, "DMA_LLI_RADDR %x\n", v); -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_SRC_RADDR); -+ dev_info(rkc->dev, "DMA_SRC_RADDR %x\n", v); -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_DST_WADDR); -+ dev_info(rkc->dev, "DMA_LLI_WADDR %x\n", v); -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_ITEM_ID); -+ dev_info(rkc->dev, "DMA_LLI_ITEMID %x\n", v); -+ -+ v = readl(rkc->reg + RK2_CRYPTO_CIPHER_ST); -+ dev_info(rkc->dev, "CIPHER_ST %x\n", v); -+ if (v & BIT(0)) -+ dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER BUSY\n"); -+ else -+ dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER IDLE\n"); -+ if (v & BIT(2)) -+ dev_info(rkc->dev, "CIPHER_ST: HASH BUSY\n"); -+ else -+ dev_info(rkc->dev, "CIPHER_ST: HASH IDLE\n"); -+ if (v & BIT(2)) -+ dev_info(rkc->dev, "CIPHER_ST: OTP KEY VALID\n"); -+ else -+ dev_info(rkc->dev, "CIPHER_ST: OTP KEY INVALID\n"); -+ -+ v = readl(rkc->reg + RK2_CRYPTO_CIPHER_STATE); -+ dev_info(rkc->dev, "CIPHER_STATE %x\n", v); -+ switch (v & 0x3) { -+ case 0: -+ dev_info(rkc->dev, "serial: IDLE state\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "serial: PRE state\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "serial: BULK state\n"); -+ break; -+ default: -+ dev_info(rkc->dev, "serial: reserved state\n"); -+ break; -+ } -+ switch (v & 0xC) { -+ case 0: -+ dev_info(rkc->dev, "mac_state: IDLE state\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "mac_state: PRE state\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "mac_state: BULK state\n"); -+ break; -+ default: -+ dev_info(rkc->dev, "mac_state: reserved state\n"); -+ break; -+ } -+ switch (v & 0x30) { -+ case 0: -+ dev_info(rkc->dev, "parallel_state: IDLE state\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "parallel_state: PRE state\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "parallel_state: BULK state\n"); -+ break; -+ default: -+ dev_info(rkc->dev, "parallel_state: reserved state\n"); -+ break; -+ } -+ switch (v & 0xC0) { -+ case 0: -+ dev_info(rkc->dev, "ccm_state: IDLE state\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "ccm_state: PRE state\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "ccm_state: NA state\n"); -+ break; -+ default: -+ dev_info(rkc->dev, "ccm_state: reserved state\n"); -+ break; -+ } -+ switch (v & 0xF00) { -+ case 0: -+ dev_info(rkc->dev, "gcm_state: IDLE state\n"); -+ break; -+ case 1: -+ dev_info(rkc->dev, "gcm_state: PRE state\n"); -+ break; -+ case 2: -+ dev_info(rkc->dev, "gcm_state: NA state\n"); -+ break; -+ case 3: -+ dev_info(rkc->dev, "gcm_state: PC state\n"); -+ break; -+ } -+ switch (v & 0xC00) { -+ case 0x1: -+ dev_info(rkc->dev, "hash_state: IDLE state\n"); -+ break; -+ case 0x2: -+ dev_info(rkc->dev, "hash_state: IPAD state\n"); -+ break; -+ case 0x4: -+ dev_info(rkc->dev, "hash_state: TEXT state\n"); -+ break; -+ case 0x8: -+ dev_info(rkc->dev, "hash_state: OPAD state\n"); -+ break; -+ case 0x10: -+ dev_info(rkc->dev, "hash_state: OPAD EXT state\n"); -+ break; -+ default: -+ dev_info(rkc->dev, "hash_state: invalid state\n"); -+ break; -+ } -+ -+ v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST); -+ dev_info(rkc->dev, "RK2_CRYPTO_DMA_INT_ST %x\n", v); -+} -+ -+static int rk2_cipher_need_fallback(struct skcipher_request *req) -+{ -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ struct scatterlist *sgs, *sgd; -+ unsigned int stodo, dtodo, len; -+ unsigned int bs = crypto_skcipher_blocksize(tfm); -+ -+ if (!req->cryptlen) -+ return true; -+ -+ if (algt->is_xts) { -+ if (sg_nents_for_len(req->src, req->cryptlen) > 1) -+ return true; -+ if (sg_nents_for_len(req->dst, req->cryptlen) > 1) -+ return true; -+ } -+ -+ len = req->cryptlen; -+ sgs = req->src; -+ sgd = req->dst; -+ while (sgs && sgd) { -+ if (!IS_ALIGNED(sgs->offset, sizeof(u32))) { -+ algt->stat_fb_align++; -+ return true; -+ } -+ if (!IS_ALIGNED(sgd->offset, sizeof(u32))) { -+ algt->stat_fb_align++; -+ return true; -+ } -+ stodo = min(len, sgs->length); -+ if (stodo % bs) { -+ algt->stat_fb_len++; -+ return true; -+ } -+ dtodo = min(len, sgd->length); -+ if (dtodo % bs) { -+ algt->stat_fb_len++; -+ return true; -+ } -+ if (stodo != dtodo) { -+ algt->stat_fb_sgdiff++; -+ return true; -+ } -+ len -= stodo; -+ sgs = sg_next(sgs); -+ sgd = sg_next(sgd); -+ } -+ return false; -+} -+ -+static int rk2_cipher_fallback(struct skcipher_request *areq) -+{ -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); -+ struct rk2_cipher_ctx *op = crypto_skcipher_ctx(tfm); -+ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ int err; -+ -+ algt->stat_fb++; -+ -+ skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); -+ skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, -+ areq->base.complete, areq->base.data); -+ skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst, -+ areq->cryptlen, areq->iv); -+ if (rctx->mode & RK2_CRYPTO_DEC) -+ err = crypto_skcipher_decrypt(&rctx->fallback_req); -+ else -+ err = crypto_skcipher_encrypt(&rctx->fallback_req); -+ return err; -+} -+ -+static int rk2_cipher_handle_req(struct skcipher_request *req) -+{ -+ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); -+ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ struct rk2_crypto_dev *rkc; -+ struct crypto_engine *engine; -+ -+ if (ctx->keylen == AES_KEYSIZE_192 * 2) -+ return rk2_cipher_fallback(req); -+ -+ if (rk2_cipher_need_fallback(req)) -+ return rk2_cipher_fallback(req); -+ -+ rkc = get_rk2_crypto(); -+ -+ engine = rkc->engine; -+ rctx->dev = rkc; -+ -+ return crypto_transfer_skcipher_request_to_engine(engine, req); -+} -+ -+int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key, -+ unsigned int keylen) -+{ -+ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); -+ struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -+ int err; -+ -+ err = xts_verify_key(cipher, key, keylen); -+ if (err) -+ return err; -+ -+ ctx->keylen = keylen; -+ memcpy(ctx->key, key, keylen); -+ -+ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); -+} -+ -+int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, -+ unsigned int keylen) -+{ -+ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); -+ struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm); -+ -+ if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && -+ keylen != AES_KEYSIZE_256) -+ return -EINVAL; -+ ctx->keylen = keylen; -+ memcpy(ctx->key, key, keylen); -+ -+ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); -+} -+ -+int rk2_skcipher_encrypt(struct skcipher_request *req) -+{ -+ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ -+ rctx->mode = algt->rk2_mode; -+ return rk2_cipher_handle_req(req); -+} -+ -+int rk2_skcipher_decrypt(struct skcipher_request *req) -+{ -+ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ -+ rctx->mode = algt->rk2_mode | RK2_CRYPTO_DEC; -+ return rk2_cipher_handle_req(req); -+} -+ -+int rk2_cipher_run(struct crypto_engine *engine, void *async_req) -+{ -+ struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base); -+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); -+ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq); -+ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ struct scatterlist *sgs, *sgd; -+ int err = 0; -+ int ivsize = crypto_skcipher_ivsize(tfm); -+ unsigned int len = areq->cryptlen; -+ unsigned int todo; -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ struct rk2_crypto_dev *rkc = rctx->dev; -+ struct rk2_crypto_lli *dd = &rkc->tl[0]; -+ u32 m, v; -+ u32 *rkey = (u32 *)ctx->key; -+ u32 *riv = (u32 *)areq->iv; -+ int i; -+ unsigned int offset; -+ -+ algt->stat_req++; -+ rkc->nreq++; -+ -+ m = rctx->mode | RK2_CRYPTO_ENABLE; -+ if (algt->is_xts) { -+ switch (ctx->keylen) { -+ case AES_KEYSIZE_128 * 2: -+ m |= RK2_CRYPTO_AES_128BIT_key; -+ break; -+ case AES_KEYSIZE_256 * 2: -+ m |= RK2_CRYPTO_AES_256BIT_key; -+ break; -+ default: -+ dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen); -+ return -EINVAL; -+ } -+ } else { -+ switch (ctx->keylen) { -+ case AES_KEYSIZE_128: -+ m |= RK2_CRYPTO_AES_128BIT_key; -+ break; -+ case AES_KEYSIZE_192: -+ m |= RK2_CRYPTO_AES_192BIT_key; -+ break; -+ case AES_KEYSIZE_256: -+ m |= RK2_CRYPTO_AES_256BIT_key; -+ break; -+ default: -+ dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen); -+ return -EINVAL; -+ } -+ } -+ -+ err = pm_runtime_resume_and_get(rkc->dev); -+ if (err) -+ return err; -+ -+ /* the upper bits are a write enable mask, so we need to write 1 to all -+ * upper 16 bits to allow write to the 16 lower bits -+ */ -+ m |= 0xffff0000; -+ -+ dev_dbg(rkc->dev, "%s %s len=%u keylen=%u mode=%x\n", __func__, -+ crypto_tfm_alg_name(areq->base.tfm), -+ areq->cryptlen, ctx->keylen, m); -+ sgs = areq->src; -+ sgd = areq->dst; -+ -+ while (sgs && sgd && len) { -+ ivsize = crypto_skcipher_ivsize(tfm); -+ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { -+ if (rctx->mode & RK2_CRYPTO_DEC) { -+ offset = sgs->length - ivsize; -+ scatterwalk_map_and_copy(rctx->backup_iv, sgs, -+ offset, ivsize, 0); -+ } -+ } -+ -+ dev_dbg(rkc->dev, "SG len=%u mode=%x ivsize=%u\n", sgs->length, m, ivsize); -+ -+ if (sgs == sgd) { -+ err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); -+ if (err != 1) { -+ dev_err(rkc->dev, "Invalid sg number %d\n", err); -+ err = -EINVAL; -+ goto theend; -+ } -+ } else { -+ err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); -+ if (err != 1) { -+ dev_err(rkc->dev, "Invalid sg number %d\n", err); -+ err = -EINVAL; -+ goto theend; -+ } -+ err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); -+ if (err != 1) { -+ dev_err(rkc->dev, "Invalid sg number %d\n", err); -+ err = -EINVAL; -+ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); -+ goto theend; -+ } -+ } -+ err = 0; -+ writel(m, rkc->reg + RK2_CRYPTO_BC_CTL); -+ -+ if (algt->is_xts) { -+ for (i = 0; i < ctx->keylen / 8; i++) { -+ v = cpu_to_be32(rkey[i]); -+ writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4); -+ } -+ for (i = 0; i < (ctx->keylen / 8); i++) { -+ v = cpu_to_be32(rkey[i + ctx->keylen / 8]); -+ writel(v, rkc->reg + RK2_CRYPTO_CH4_KEY0 + i * 4); -+ } -+ } else { -+ for (i = 0; i < ctx->keylen / 4; i++) { -+ v = cpu_to_be32(rkey[i]); -+ writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4); -+ } -+ } -+ -+ if (ivsize) { -+ for (i = 0; i < ivsize / 4; i++) -+ writel(cpu_to_be32(riv[i]), -+ rkc->reg + RK2_CRYPTO_CH0_IV_0 + i * 4); -+ writel(ivsize, rkc->reg + RK2_CRYPTO_CH0_IV_LEN); -+ } -+ if (!sgs->length) { -+ sgs = sg_next(sgs); -+ sgd = sg_next(sgd); -+ continue; -+ } -+ -+ /* The hw support multiple descriptor, so why this driver use -+ * only one descriptor ? -+ * Using one descriptor per SG seems the way to do and it works -+ * but only when doing encryption. -+ * With decryption it always fail on second descriptor. -+ * Probably the HW dont know how to use IV. -+ */ -+ todo = min(sg_dma_len(sgs), len); -+ len -= todo; -+ dd->src_addr = sg_dma_address(sgs); -+ dd->src_len = todo; -+ dd->dst_addr = sg_dma_address(sgd); -+ dd->dst_len = todo; -+ dd->iv = 0; -+ dd->next = 1; -+ -+ dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST | RK2_LLI_STRING_LAST; -+ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_DST_INT | RK2_LLI_DMA_CTRL_LAST; -+ -+ writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN); -+ -+ /*writel(0x00030000, rkc->reg + RK2_CRYPTO_FIFO_CTL);*/ -+ writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR); -+ -+ reinit_completion(&rkc->complete); -+ rkc->status = 0; -+ -+ writel(RK2_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK2_CRYPTO_DMA_CTL); -+ -+ wait_for_completion_interruptible_timeout(&rkc->complete, -+ msecs_to_jiffies(10000)); -+ if (sgs == sgd) { -+ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); -+ } else { -+ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); -+ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); -+ } -+ -+ if (!rkc->status) { -+ dev_err(rkc->dev, "DMA timeout\n"); -+ rk2_print(rkc); -+ err = -EFAULT; -+ goto theend; -+ } -+ if (areq->iv && ivsize > 0) { -+ offset = sgd->length - ivsize; -+ if (rctx->mode & RK2_CRYPTO_DEC) { -+ memcpy(areq->iv, rctx->backup_iv, ivsize); -+ memzero_explicit(rctx->backup_iv, ivsize); -+ } else { -+ scatterwalk_map_and_copy(areq->iv, sgd, offset, -+ ivsize, 0); -+ } -+ } -+ sgs = sg_next(sgs); -+ sgd = sg_next(sgd); -+ } -+theend: -+ writel(0xffff0000, rkc->reg + RK2_CRYPTO_BC_CTL); -+ pm_runtime_put_autosuspend(rkc->dev); -+ -+ local_bh_disable(); -+ crypto_finalize_skcipher_request(engine, areq, err); -+ local_bh_enable(); -+ return 0; -+} -+ -+int rk2_cipher_tfm_init(struct crypto_skcipher *tfm) -+{ -+ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ const char *name = crypto_tfm_alg_name(&tfm->base); -+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); -+ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); -+ -+ ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); -+ if (IS_ERR(ctx->fallback_tfm)) { -+ dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", -+ name, PTR_ERR(ctx->fallback_tfm)); -+ return PTR_ERR(ctx->fallback_tfm); -+ } -+ -+ dev_info(algt->dev->dev, "Fallback for %s is %s\n", -+ crypto_tfm_alg_driver_name(&tfm->base), -+ crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm))); -+ -+ tfm->reqsize = sizeof(struct rk2_cipher_rctx) + -+ crypto_skcipher_reqsize(ctx->fallback_tfm); -+ -+ return 0; -+} -+ -+void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm) -+{ -+ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); -+ -+ memzero_explicit(ctx->key, ctx->keylen); -+ crypto_free_skcipher(ctx->fallback_tfm); -+} --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0025-RK3588-Add-HW-RNG-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0025-RK3588-Add-HW-RNG-Support.patch deleted file mode 100644 index 92a0d755f3dd..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0025-RK3588-Add-HW-RNG-Support.patch +++ /dev/null @@ -1,663 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 16 Nov 2023 17:49:42 +0300 -Subject: hwrng: rockchip: Add support for Rockchip HW RNG - ---- - drivers/char/hw_random/Kconfig | 13 + - drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++ - 3 files changed, 588 insertions(+) - -diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA - To compile this driver as a module, choose M here: the - module will be called xiphera-trng. - -+config HW_RANDOM_ROCKCHIP -+ tristate "Rockchip Random Number Generator support" -+ depends on ARCH_ROCKCHIP -+ default HW_RANDOM -+ help -+ This driver provides kernel-side support for the Random Number -+ Generator hardware found on Rockchip cpus. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called rockchip-rng. -+ -+ If unsure, say Y. -+ - config HW_RANDOM_ARM_SMCCC_TRNG - tristate "Arm SMCCC TRNG firmware interface support" - depends on HAVE_ARM_SMCCC_DISCOVERY -diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/char/hw_random/Makefile -+++ b/drivers/char/hw_random/Makefile -@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o - obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o - obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o - obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o -+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o - obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o - obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o - obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o -diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -0,0 +1,574 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * rockchip-rng.c Random Number Generator driver for the Rockchip -+ * -+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. -+ * Author: Lin Jinhan -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define _SBF(s, v) ((v) << (s)) -+#define HIWORD_UPDATE(val, mask, shift) \ -+ ((val) << (shift) | (mask) << ((shift) + 16)) -+ -+#define ROCKCHIP_AUTOSUSPEND_DELAY 100 -+#define ROCKCHIP_POLL_PERIOD_US 100 -+#define ROCKCHIP_POLL_TIMEOUT_US 50000 -+#define RK_MAX_RNG_BYTE (32) -+ -+/* start of CRYPTO V1 register define */ -+#define CRYPTO_V1_CTRL 0x0008 -+#define CRYPTO_V1_RNG_START BIT(8) -+#define CRYPTO_V1_RNG_FLUSH BIT(9) -+ -+#define CRYPTO_V1_TRNG_CTRL 0x0200 -+#define CRYPTO_V1_OSC_ENABLE BIT(16) -+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) -+ -+#define CRYPTO_V1_TRNG_DOUT_0 0x0204 -+/* end of CRYPTO V1 register define */ -+ -+/* start of CRYPTO V2 register define */ -+#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400 -+#define CRYPTO_V2_RNG_CTL 0x0 -+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) -+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) -+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) -+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) -+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) -+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) -+#define CRYPTO_V2_RNG_ENABLE BIT(1) -+#define CRYPTO_V2_RNG_START BIT(0) -+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004 -+#define CRYPTO_V2_RNG_DOUT_0 0x0010 -+/* end of CRYPTO V2 register define */ -+ -+/* start of TRNG_V1 register define */ -+/* TRNG is no longer subordinate to the Crypto module */ -+#define TRNG_V1_CTRL 0x0000 -+#define TRNG_V1_CTRL_NOP _SBF(0, 0x00) -+#define TRNG_V1_CTRL_RAND _SBF(0, 0x01) -+#define TRNG_V1_CTRL_SEED _SBF(0, 0x02) -+ -+#define TRNG_V1_STAT 0x0004 -+#define TRNG_V1_STAT_SEEDED BIT(9) -+#define TRNG_V1_STAT_GENERATING BIT(30) -+#define TRNG_V1_STAT_RESEEDING BIT(31) -+ -+#define TRNG_V1_MODE 0x0008 -+#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00) -+#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01) -+ -+#define TRNG_V1_IE 0x0010 -+#define TRNG_V1_IE_GLBL_EN BIT(31) -+#define TRNG_V1_IE_SEED_DONE_EN BIT(1) -+#define TRNG_V1_IE_RAND_RDY_EN BIT(0) -+ -+#define TRNG_V1_ISTAT 0x0014 -+#define TRNG_V1_ISTAT_RAND_RDY BIT(0) -+ -+/* RAND0 ~ RAND7 */ -+#define TRNG_V1_RAND0 0x0020 -+#define TRNG_V1_RAND7 0x003C -+ -+#define TRNG_V1_AUTO_RQSTS 0x0060 -+ -+#define TRNG_V1_VERSION 0x00F0 -+#define TRNG_v1_VERSION_CODE 0x46bc -+/* end of TRNG_V1 register define */ -+ -+/* start of RKRNG register define */ -+#define RKRNG_CTRL 0x0010 -+#define RKRNG_CTRL_INST_REQ BIT(0) -+#define RKRNG_CTRL_RESEED_REQ BIT(1) -+#define RKRNG_CTRL_TEST_REQ BIT(2) -+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3) -+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4) -+ -+#define RKRNG_STATE 0x0014 -+#define RKRNG_STATE_INST_ACK BIT(0) -+#define RKRNG_STATE_RESEED_ACK BIT(1) -+#define RKRNG_STATE_TEST_ACK BIT(2) -+#define RKRNG_STATE_SW_DRNG_ACK BIT(3) -+#define RKRNG_STATE_SW_TRNG_ACK BIT(4) -+ -+/* DRNG_DATA_0 ~ DNG_DATA_7 */ -+#define RKRNG_DRNG_DATA_0 0x0070 -+#define RKRNG_DRNG_DATA_7 0x008C -+ -+/* end of RKRNG register define */ -+ -+struct rk_rng_soc_data { -+ u32 default_offset; -+ -+ int (*rk_rng_init)(struct hwrng *rng); -+ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); -+}; -+ -+struct rk_rng { -+ struct device *dev; -+ struct hwrng rng; -+ void __iomem *mem; -+ struct rk_rng_soc_data *soc_data; -+ int clk_num; -+ struct clk_bulk_data *clk_bulks; -+}; -+ -+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) -+{ -+ __raw_writel(val, rng->mem + offset); -+} -+ -+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) -+{ -+ return __raw_readl(rng->mem + offset); -+} -+ -+static int rk_rng_init(struct hwrng *rng) -+{ -+ int ret; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); -+ -+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); -+ if (ret < 0) { -+ dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk_rng_cleanup(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+} -+ -+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret; -+ int read_len = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ if (!rk_rng->soc_data->rk_rng_read) -+ return -EFAULT; -+ -+ ret = pm_runtime_get_sync(rk_rng->dev); -+ if (ret < 0) { -+ pm_runtime_put_noidle(rk_rng->dev); -+ return ret; -+ } -+ -+ ret = 0; -+ while (max > ret) { -+ read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret, -+ max - ret, wait); -+ if (read_len < 0) { -+ ret = read_len; -+ break; -+ } -+ ret += read_len; -+ } -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ -+ return ret; -+} -+ -+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, -+ size_t size) -+{ -+ u32 i; -+ -+ for (i = 0; i < size; i += 4) -+ *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); -+} -+ -+static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); -+ -+ reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); -+ -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); -+ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V1_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, CRYPTO_V1_CTRL); -+ -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), -+ CRYPTO_V1_CTRL); -+ -+ return ret; -+} -+ -+static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); -+ -+ reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; -+ reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; -+ reg_ctrl |= CRYPTO_V2_RNG_ENABLE; -+ reg_ctrl |= CRYPTO_V2_RNG_START; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), -+ CRYPTO_V2_RNG_CTL); -+ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V2_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, CRYPTO_V2_RNG_CTL); -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); -+ -+ return ret; -+} -+ -+static int trng_v1_init(struct hwrng *rng) -+{ -+ int ret; -+ uint32_t auto_reseed_cnt = 1000; -+ uint32_t reg_ctrl, status, version; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); -+ if (version != TRNG_v1_VERSION_CODE) { -+ dev_err(rk_rng->dev, -+ "wrong trng version, expected = %08x, actual = %08x\n", -+ TRNG_V1_VERSION, version); -+ ret = -EFAULT; -+ goto exit; -+ } -+ -+ status = rk_rng_readl(rk_rng, TRNG_V1_STAT); -+ -+ /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */ -+ if (!(status & TRNG_V1_STAT_SEEDED) || -+ (status & TRNG_V1_STAT_GENERATING) || -+ (status & TRNG_V1_STAT_RESEEDING)) { -+ uint32_t mask = TRNG_V1_STAT_SEEDED | -+ TRNG_V1_STAT_GENERATING | -+ TRNG_V1_STAT_RESEEDING; -+ -+ udelay(10); -+ -+ /* wait for GENERATING and RESEEDING flag to clear */ -+ read_poll_timeout(rk_rng_readl, reg_ctrl, -+ (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED, -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, TRNG_V1_STAT); -+ } -+ -+ /* clear ISTAT flag because trng may auto reseeding when power on */ -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+ -+ /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */ -+ rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS); -+ -+ ret = 0; -+exit: -+ -+ return ret; -+} -+ -+static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* clear ISTAT anyway */ -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+ -+ /* generate 256bit random */ -+ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); -+ -+ /* -+ * Generate2 56 bit random data will cost 1024 clock cycles. -+ * Estimated at 150M RNG module frequency, it takes 6.7 microseconds. -+ */ -+ udelay(10); -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) { -+ /* wait RAND_RDY triggered */ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, TRNG_V1_ISTAT); -+ if (ret < 0) -+ goto out; -+ } -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret); -+ -+ /* clear all status flag */ -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); -+ -+ return ret; -+} -+ -+static int rkrng_init(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg = 0; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); -+ -+ reg = rk_rng_readl(rk_rng, RKRNG_STATE); -+ rk_rng_writel(rk_rng, reg, RKRNG_STATE); -+ -+ return 0; -+} -+ -+static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg_ctrl = 0; -+ int ret; -+ -+ reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL); -+ -+ ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl, -+ (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US); -+ -+ if (ret) -+ goto exit; -+ -+ rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE); -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret); -+ -+exit: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); -+ -+ return ret; -+} -+ -+static const struct rk_rng_soc_data crypto_v1_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_read = crypto_v1_read, -+}; -+ -+static const struct rk_rng_soc_data crypto_v2_soc_data = { -+ .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET, -+ -+ .rk_rng_read = crypto_v2_read, -+}; -+ -+static const struct rk_rng_soc_data trng_v1_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_init = trng_v1_init, -+ .rk_rng_read = trng_v1_read, -+}; -+ -+static const struct rk_rng_soc_data rkrng_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_init = rkrng_init, -+ .rk_rng_read = rkrng_read, -+}; -+ -+static const struct of_device_id rk_rng_dt_match[] = { -+ { -+ .compatible = "rockchip,cryptov1-rng", -+ .data = (void *)&crypto_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,cryptov2-rng", -+ .data = (void *)&crypto_v2_soc_data, -+ }, -+ { -+ .compatible = "rockchip,trngv1", -+ .data = (void *)&trng_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,rkrng", -+ .data = (void *)&rkrng_soc_data, -+ }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, rk_rng_dt_match); -+ -+static int rk_rng_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct rk_rng *rk_rng; -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *match; -+ resource_size_t map_size; -+ -+ dev_dbg(&pdev->dev, "probing...\n"); -+ rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); -+ if (!rk_rng) -+ return -ENOMEM; -+ -+ match = of_match_node(rk_rng_dt_match, np); -+ rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; -+ -+ rk_rng->dev = &pdev->dev; -+ rk_rng->rng.name = "rockchip"; -+#ifndef CONFIG_PM -+ rk_rng->rng.init = rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng_cleanup, -+#endif -+ rk_rng->rng.read = rk_rng_read; -+ rk_rng->rng.quality = 999; -+ -+ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size); -+ if (IS_ERR(rk_rng->mem)) -+ return PTR_ERR(rk_rng->mem); -+ -+ /* compatible with crypto v2 module */ -+ /* -+ * With old dtsi configurations, the RNG base was equal to the crypto -+ * base, so both drivers could not be enabled at the same time. -+ * RNG base = CRYPTO base + RNG offset -+ * (Since RK356X, RNG module is no longer belongs to CRYPTO module) -+ * -+ * With new dtsi configurations, CRYPTO regs is divided into two parts -+ * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base. -+ * RNG driver and CRYPTO driver could be enabled at the same time. -+ */ -+ if (map_size > rk_rng->soc_data->default_offset) -+ rk_rng->mem += rk_rng->soc_data->default_offset; -+ -+ rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks); -+ if (rk_rng->clk_num < 0) { -+ dev_err(&pdev->dev, "failed to get clks property\n"); -+ return -ENODEV; -+ } -+ -+ platform_set_drvdata(pdev, rk_rng); -+ -+ pm_runtime_set_autosuspend_delay(&pdev->dev, -+ ROCKCHIP_AUTOSUSPEND_DELAY); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_enable(&pdev->dev); -+ -+ ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); -+ if (ret) { -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ } -+ -+ /* for some platform need hardware operation when probe */ -+ if (rk_rng->soc_data->rk_rng_init) { -+ pm_runtime_get_sync(rk_rng->dev); -+ -+ ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng); -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ } -+ -+ return ret; -+} -+ -+#ifdef CONFIG_PM -+static int rk_rng_runtime_suspend(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ rk_rng_cleanup(&rk_rng->rng); -+ -+ return 0; -+} -+ -+static int rk_rng_runtime_resume(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ return rk_rng_init(&rk_rng->rng); -+} -+ -+static const struct dev_pm_ops rk_rng_pm_ops = { -+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, -+ rk_rng_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ -+#endif -+ -+static struct platform_driver rk_rng_driver = { -+ .driver = { -+ .name = "rockchip-rng", -+#ifdef CONFIG_PM -+ .pm = &rk_rng_pm_ops, -+#endif -+ .of_match_table = rk_rng_dt_match, -+ }, -+ .probe = rk_rng_probe, -+}; -+ -+module_platform_driver(rk_rng_driver); -+ -+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); -+MODULE_AUTHOR("Lin Jinhan "); -+MODULE_LICENSE("GPL v2"); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 16 Nov 2023 17:52:35 +0300 -Subject: arm64: dts: Add HW RNG support to RK3588S - ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1935,6 +1935,16 @@ crypto: crypto@fe370000 { - status = "okay"; - }; - -+ rng: rng@fe378000 { -+ compatible = "rockchip,trngv1"; -+ reg = <0x0 0xfe378000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ clock-names = "hclk_trng"; -+ resets = <&scmi_reset SRST_H_TRNG_NS>; -+ reset-names = "reset"; -+ }; -+ - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch deleted file mode 100644 index 78b7d8bf8bb1..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch +++ /dev/null @@ -1,311 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 15:48:42 +0200 -Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121 - -From: Emmanuel Gil Peyrot - -This encoder-only device is present four times on this SoC, and should -support everything the rk3568 vepu supports (so JPEG, H.264 and VP8 -encoding). No fallback compatible has been added, since the operating -systems might already support RK3568 VEPU and want to avoid registering -four of them separately considering they can be used as a cluster. - -Signed-off-by: Emmanuel Gil Peyrot -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -@@ -17,6 +17,7 @@ properties: - compatible: - enum: - - rockchip,rk3568-vepu -+ - rockchip,rk3588-vepu121 - - reg: - maxItems: 1 --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 15:48:44 +0200 -Subject: media: hantro: Disable multicore support - -Avoid exposing equal Hantro video codecs to userspace. Equal video -codecs allow scheduling work between the cores. For that kernel support -is required, which does not yet exist. Until that is implemented avoid -exposing each core separately to userspace so that multicore can be -added in the future without breaking userspace ABI. - -This was written with Rockchip RK3588 in mind (which has 4 Hantro H1 -cores), but applies to all SoCs. - -Signed-off-by: Sebastian Reichel ---- - drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++ - 1 file changed, 37 insertions(+) - -diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/hantro_drv.c -+++ b/drivers/media/platform/verisilicon/hantro_drv.c -@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = { - .req_queue = v4l2_m2m_request_queue, - }; - -+/* -+ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the -+ * kernel is currently missing support for multi-core handling. Exposing -+ * separate devices for each core to userspace is bad, since that does -+ * not allow scheduling tasks properly (and creates ABI). With this workaround -+ * the driver will only probe for the first core and early exit for the other -+ * cores. Once the driver gains multi-core support, the same technique -+ * for detecting the main core can be used to cluster all cores together. -+ */ -+static int hantro_disable_multicore(struct hantro_dev *vpu) -+{ -+ const char *compatible; -+ struct device_node *node; -+ int ret; -+ -+ /* Intentionally ignores the fallback strings */ -+ ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible); -+ if (ret) -+ return ret; -+ -+ /* first compatible node found from the root node is considered the main core */ -+ node = of_find_compatible_node(NULL, NULL, compatible); -+ if (!node) -+ return -EINVAL; /* broken DT? */ -+ -+ if (vpu->dev->of_node != node) { -+ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - static int hantro_probe(struct platform_device *pdev) - { - const struct of_device_id *match; -@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev) - match = of_match_node(of_hantro_match, pdev->dev.of_node); - vpu->variant = match->data; - -+ ret = hantro_disable_multicore(vpu); -+ if (ret) -+ return ret; -+ - /* - * Support for nxp,imx8mq-vpu is kept for backwards compatibility - * but it's deprecated. Please update your DTS file to use --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 15:48:45 +0200 -Subject: media: hantro: Add RK3588 VEPU121 - -RK3588 handling is exactly the same as RK3568. This is not -handled using fallback compatibles to avoid exposing multiple -video devices on kernels not having the multicore disable -patch. - -Signed-off-by: Sebastian Reichel ---- - drivers/media/platform/verisilicon/hantro_drv.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/hantro_drv.c -+++ b/drivers/media/platform/verisilicon/hantro_drv.c -@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = { - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, - { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, -+ { .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 15:48:46 +0200 -Subject: arm64: dts: rockchip: Add VEPU121 to RK3588 - -From: Emmanuel Gil Peyrot - -RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP, -but can be used as a cluster (i.e. sharing work between the cores). -These cores are called VEPU121 in the TRM. The TRM describes one more -VEPU121, but that is combined with a Hantro H1. That one will be handled -using the VPU binding instead. - -Signed-off-by: Emmanuel Gil Peyrot -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1282,6 +1282,86 @@ power-domain@RK3588_PD_SDMMC { - }; - }; - -+ vepu121_0: video-codec@fdba0000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba0000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_0_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_0_mmu: iommu@fdba0800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba0800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_1: video-codec@fdba4000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba4000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_1_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_1_mmu: iommu@fdba4800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba4800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_2: video-codec@fdba8000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba8000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_2_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_2_mmu: iommu@fdba8800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba8800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_3: video-codec@fdbac000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdbac000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_3_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_3_mmu: iommu@fdbac800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdbac800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 15:48:47 +0200 -Subject: arm64: dts: rockchip: Add VPU121 support for RK3588 - -From: Jianfeng Liu - -Enable Hantro G1 video decoder in RK3588's devicetree. - -Tested with FFmpeg v4l2_request code taken from [1] -with MPEG2, H.264 and VP8 samples. - -[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch - -Signed-off-by: Jianfeng Liu -Tested-by: Hugh Cole-Baker -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1282,6 +1282,28 @@ power-domain@RK3588_PD_SDMMC { - }; - }; - -+ vpu121: video-codec@fdb50000 { -+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu"; -+ reg = <0x0 0xfdb50000 0x0 0x800>; -+ interrupts = , -+ ; -+ interrupt-names = "vepu", "vdpu"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vpu121_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vpu121_mmu: iommu@fdb50800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdb50800 0x0 0x40>; -+ interrupts = ; -+ clock-names = "aclk", "iface"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ - vepu121_0: video-codec@fdba0000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdba0000 0x0 0x800>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch deleted file mode 100644 index 8f1f4ce87cf7..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch +++ /dev/null @@ -1,3746 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 20 Jun 2024 10:19:43 -0400 -Subject: media: rockchip: Move H264 CABAC table to header file - -The table will be shared with the rkvdec2 driver in following commits. - -Signed-off-by: Detlev Casanova ---- - drivers/staging/media/rkvdec/rkvdec-h264-cabac.h | 509 ++++++++++ - drivers/staging/media/rkvdec/rkvdec-h264.c | 500 +-------- - 2 files changed, 510 insertions(+), 499 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h b/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h -@@ -0,0 +1,509 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+/* -+ * Define the H264 CABAC table common to rkvdec and rkvdec2 drivers. -+ */ -+ -+#ifndef RKVDEC_H264_CABAC_H_ -+#define RKVDEC_H264_CABAC_H_ -+ -+#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ -+ idc2_m, idc2_n, intra_m, intra_n) \ -+ [0][(ctxidx)] = {idc0_m, idc0_n}, \ -+ [1][(ctxidx)] = {idc1_m, idc1_n}, \ -+ [2][(ctxidx)] = {idc2_m, idc2_n}, \ -+ [3][(ctxidx)] = {intra_m, intra_n} -+ -+/* -+ * Constant CABAC table. -+ * Built from the tables described in section '9.3.1.1 Initialisation process -+ * for context variables' of the H264 spec. -+ */ -+static const s8 rkvdec_h264_cabac_table[4][464][2] = { -+ /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ -+ CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), -+ CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), -+ CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), -+ CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), -+ CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), -+ CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), -+ CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), -+ CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), -+ CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), -+ CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), -+ CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), -+ -+ /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ -+ CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), -+ CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), -+ CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), -+ CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), -+ CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), -+ CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), -+ CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), -+ CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), -+ CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), -+ CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), -+ CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), -+ CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), -+ CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), -+ -+ /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ -+ CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), -+ CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), -+ CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), -+ CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), -+ CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), -+ CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), -+ CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), -+ CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), -+ CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), -+ CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), -+ CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), -+ CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), -+ CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), -+ CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), -+ CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), -+ CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), -+ -+ /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ -+ CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), -+ CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), -+ CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), -+ CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), -+ CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), -+ CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), -+ CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), -+ CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), -+ CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), -+ CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), -+ CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), -+ CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), -+ CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), -+ CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), -+ -+ /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ -+ CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), -+ CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), -+ CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), -+ CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), -+ CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), -+ CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), -+ -+ /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ -+ CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), -+ CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), -+ CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), -+ CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), -+ CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), -+ CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), -+ CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), -+ -+ /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ -+ CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), -+ CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), -+ CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), -+ CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), -+ CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), -+ CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), -+ CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), -+ CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), -+ CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), -+ CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), -+ CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), -+ CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), -+ CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), -+ CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), -+ CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), -+ CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), -+ CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), -+ CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), -+ CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), -+ CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), -+ CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), -+ CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), -+ CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), -+ CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), -+ CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), -+ CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), -+ CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), -+ CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), -+ CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), -+ CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), -+ CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), -+ CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), -+ CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), -+ CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), -+ CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), -+ -+ /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ -+ CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), -+ CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), -+ CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), -+ CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), -+ CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), -+ CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), -+ CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), -+ CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), -+ CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), -+ CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), -+ CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), -+ CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), -+ CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), -+ CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), -+ CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), -+ CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), -+ CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), -+ CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), -+ CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), -+ CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), -+ CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), -+ CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), -+ CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), -+ CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), -+ CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), -+ CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), -+ CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), -+ CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), -+ CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), -+ CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), -+ CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), -+ CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), -+ CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), -+ CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), -+ CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), -+ CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), -+ CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), -+ CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), -+ CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), -+ CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), -+ CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), -+ CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), -+ CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), -+ CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), -+ CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), -+ CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), -+ CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), -+ CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), -+ CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), -+ CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), -+ CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), -+ CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), -+ CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), -+ CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), -+ CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), -+ CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), -+ CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), -+ CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), -+ CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), -+ CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), -+ CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), -+ -+ /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ -+ CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), -+ CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), -+ CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), -+ CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), -+ CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), -+ CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), -+ CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), -+ CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), -+ CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), -+ CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), -+ CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), -+ CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), -+ CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), -+ CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), -+ CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), -+ CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), -+ CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), -+ CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), -+ CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), -+ CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), -+ CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), -+ CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), -+ CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), -+ CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), -+ CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), -+ CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), -+ CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), -+ CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), -+ CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), -+ CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), -+ CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), -+ CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), -+ CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), -+ CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), -+ CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), -+ CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), -+ CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), -+ CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), -+ CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), -+ CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), -+ CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), -+ CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), -+ CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), -+ CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), -+ CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), -+ CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), -+ CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), -+ CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), -+ CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), -+ CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), -+ CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), -+ CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), -+ CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), -+ CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), -+ CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), -+ CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), -+ CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), -+ CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), -+ CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), -+ CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), -+ CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), -+ -+ /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ -+ CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), -+ CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), -+ CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), -+ CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), -+ CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), -+ CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), -+ CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), -+ CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), -+ CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), -+ CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), -+ CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), -+ CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), -+ CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), -+ CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), -+ CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), -+ CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), -+ CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), -+ CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), -+ CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), -+ CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), -+ CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), -+ CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), -+ CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), -+ CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), -+ CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), -+ CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), -+ CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), -+ CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), -+ CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), -+ CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), -+ CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), -+ CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), -+ CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), -+ CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), -+ CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), -+ CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), -+ CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), -+ CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), -+ CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), -+ CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), -+ CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), -+ CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), -+ CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), -+ CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), -+ CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), -+ CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), -+ CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), -+ CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), -+ CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), -+ -+ /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ -+ CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), -+ CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), -+ CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), -+ CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), -+ CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), -+ CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), -+ CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), -+ CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), -+ CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), -+ CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), -+ CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), -+ CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), -+ CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), -+ CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), -+ CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), -+ CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), -+ CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), -+ CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), -+ CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), -+ CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), -+ CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), -+ CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), -+ CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), -+ CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), -+ CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), -+ CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), -+ CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), -+ CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), -+ CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), -+ CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), -+ CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), -+ CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), -+ CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), -+ CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), -+ CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), -+ CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), -+ CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), -+ CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), -+ CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), -+ CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), -+ CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), -+ CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), -+ CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), -+ CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), -+ CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), -+ CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), -+ CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), -+ CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), -+ CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), -+ CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), -+ CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), -+ CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), -+ CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), -+ CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), -+ CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), -+ CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), -+ CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), -+ CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), -+ CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), -+ CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), -+ CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), -+ -+ /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ -+ CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), -+ CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), -+ CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), -+ CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), -+ CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), -+ CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), -+ CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), -+ CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), -+ CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), -+ CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), -+ CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), -+ CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), -+ CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), -+ CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), -+ CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), -+ CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), -+ CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), -+ CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), -+ CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), -+ CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), -+ CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), -+ CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), -+ CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), -+ CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), -+ CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), -+ CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), -+ CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), -+ CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), -+ CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), -+ CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), -+ CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), -+ CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), -+ CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), -+ CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), -+ CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), -+ CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), -+ CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), -+ CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), -+ CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), -+ CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), -+ CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), -+ CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), -+ CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), -+ CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), -+ CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), -+ CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), -+ CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), -+ CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), -+ CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), -+ CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), -+ CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), -+ CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), -+ CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), -+ CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), -+ CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), -+ CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), -+ CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), -+ CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), -+ CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), -+ CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), -+ CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), -+ -+ /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ -+ CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), -+ CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), -+ CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), -+ CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), -+ CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), -+ CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), -+ CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), -+ CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), -+ CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), -+ CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), -+ CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), -+ CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), -+ CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), -+ CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), -+ CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), -+ CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), -+ CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), -+ CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), -+ CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), -+ CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), -+ CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), -+ CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), -+ CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), -+ CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), -+ CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), -+ CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), -+ CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), -+ CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), -+ CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), -+ CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), -+ CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), -+ CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), -+ CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), -+ CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), -+ CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), -+ CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), -+ CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), -+ CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), -+ CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), -+ CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), -+ CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), -+ CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), -+ CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), -+ CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), -+ CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), -+ CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), -+ CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), -+ CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), -+ CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), -+ CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), -+ CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), -+ CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), -+ CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), -+ CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), -+ CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), -+ CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), -+ CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), -+ CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), -+ CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), -+ CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), -+ CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), -+}; -+ -+#endif /* RKVDEC_H264_CABAC_H_ */ -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -14,6 +14,7 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" -+#include "rkvdec-h264-cabac.h" - - /* Size with u32 units. */ - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) -@@ -117,505 +118,6 @@ struct rkvdec_h264_ctx { - struct rkvdec_h264_reflists reflists; - }; - --#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ -- idc2_m, idc2_n, intra_m, intra_n) \ -- [0][(ctxidx)] = {idc0_m, idc0_n}, \ -- [1][(ctxidx)] = {idc1_m, idc1_n}, \ -- [2][(ctxidx)] = {idc2_m, idc2_n}, \ -- [3][(ctxidx)] = {intra_m, intra_n} -- --/* -- * Constant CABAC table. -- * Built from the tables described in section '9.3.1.1 Initialisation process -- * for context variables' of the H264 spec. -- */ --static const s8 rkvdec_h264_cabac_table[4][464][2] = { -- /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ -- CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), -- CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), -- CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), -- CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), -- CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), -- CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), -- CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), -- CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), -- CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), -- CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), -- CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), -- -- /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ -- CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), -- CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), -- CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), -- CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), -- CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), -- CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), -- CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), -- CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), -- CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), -- CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), -- CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), -- CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), -- CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), -- -- /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ -- CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), -- CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), -- CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), -- CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), -- CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), -- CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), -- CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), -- CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), -- CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), -- CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), -- CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), -- CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), -- CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), -- CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), -- CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), -- CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), -- -- /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ -- CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), -- CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), -- CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), -- CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), -- CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), -- CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), -- CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), -- CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), -- CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), -- CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), -- CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), -- CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), -- CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), -- CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), -- -- /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ -- CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), -- CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), -- CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), -- CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), -- CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), -- CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), -- -- /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ -- CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), -- CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), -- CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), -- CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), -- CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), -- CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), -- CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), -- -- /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ -- CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), -- CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), -- CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), -- CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), -- CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), -- CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), -- CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), -- CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), -- CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), -- CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), -- CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), -- CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), -- CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), -- CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), -- CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), -- CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), -- CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), -- CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), -- CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), -- CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), -- CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), -- CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), -- CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), -- CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), -- CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), -- CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), -- CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), -- CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), -- CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), -- CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), -- CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), -- CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), -- CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), -- CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), -- CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), -- -- /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ -- CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), -- CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), -- CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), -- CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), -- CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), -- CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), -- CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), -- CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), -- CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), -- CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), -- CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), -- CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), -- CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), -- CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), -- CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), -- CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), -- CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), -- CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), -- CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), -- CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), -- CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), -- CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), -- CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), -- CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), -- CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), -- CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), -- CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), -- CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), -- CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), -- CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), -- CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), -- CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), -- CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), -- CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), -- CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), -- CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), -- CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), -- CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), -- CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), -- CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), -- CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), -- CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), -- CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), -- CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), -- CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), -- CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), -- CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), -- CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), -- CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), -- CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), -- CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), -- CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), -- CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), -- CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), -- CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), -- CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), -- CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), -- CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), -- CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), -- CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), -- CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), -- -- /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ -- CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), -- CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), -- CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), -- CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), -- CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), -- CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), -- CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), -- CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), -- CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), -- CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), -- CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), -- CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), -- CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), -- CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), -- CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), -- CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), -- CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), -- CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), -- CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), -- CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), -- CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), -- CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), -- CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), -- CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), -- CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), -- CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), -- CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), -- CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), -- CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), -- CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), -- CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), -- CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), -- CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), -- CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), -- CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), -- CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), -- CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), -- CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), -- CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), -- CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), -- CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), -- CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), -- CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), -- CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), -- CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), -- CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), -- CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), -- CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), -- CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), -- CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), -- CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), -- CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), -- CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), -- CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), -- CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), -- CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), -- CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), -- CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), -- CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), -- CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), -- CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), -- -- /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ -- CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), -- CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), -- CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), -- CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), -- CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), -- CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), -- CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), -- CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), -- CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), -- CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), -- CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), -- CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), -- CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), -- CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), -- CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), -- CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), -- CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), -- CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), -- CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), -- CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), -- CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), -- CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), -- CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), -- CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), -- CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), -- CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), -- CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), -- CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), -- CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), -- CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), -- CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), -- CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), -- CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), -- CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), -- CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), -- CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), -- CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), -- CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), -- CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), -- CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), -- CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), -- CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), -- CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), -- CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), -- CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), -- CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), -- CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), -- CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), -- CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), -- -- /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ -- CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), -- CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), -- CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), -- CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), -- CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), -- CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), -- CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), -- CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), -- CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), -- CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), -- CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), -- CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), -- CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), -- CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), -- CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), -- CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), -- CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), -- CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), -- CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), -- CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), -- CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), -- CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), -- CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), -- CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), -- CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), -- CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), -- CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), -- CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), -- CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), -- CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), -- CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), -- CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), -- CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), -- CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), -- CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), -- CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), -- CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), -- CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), -- CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), -- CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), -- CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), -- CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), -- CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), -- CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), -- CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), -- CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), -- CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), -- CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), -- CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), -- CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), -- CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), -- CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), -- CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), -- CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), -- CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), -- CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), -- CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), -- CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), -- CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), -- CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), -- CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), -- -- /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ -- CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), -- CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), -- CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), -- CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), -- CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), -- CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), -- CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), -- CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), -- CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), -- CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), -- CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), -- CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), -- CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), -- CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), -- CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), -- CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), -- CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), -- CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), -- CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), -- CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), -- CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), -- CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), -- CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), -- CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), -- CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), -- CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), -- CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), -- CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), -- CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), -- CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), -- CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), -- CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), -- CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), -- CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), -- CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), -- CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), -- CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), -- CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), -- CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), -- CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), -- CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), -- CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), -- CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), -- CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), -- CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), -- CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), -- CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), -- CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), -- CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), -- CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), -- CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), -- CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), -- CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), -- CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), -- CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), -- CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), -- CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), -- CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), -- CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), -- CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), -- CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), -- -- /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ -- CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), -- CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), -- CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), -- CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), -- CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), -- CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), -- CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), -- CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), -- CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), -- CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), -- CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), -- CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), -- CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), -- CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), -- CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), -- CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), -- CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), -- CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), -- CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), -- CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), -- CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), -- CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), -- CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), -- CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), -- CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), -- CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), -- CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), -- CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), -- CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), -- CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), -- CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), -- CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), -- CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), -- CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), -- CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), -- CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), -- CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), -- CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), -- CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), -- CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), -- CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), -- CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), -- CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), -- CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), -- CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), -- CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), -- CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), -- CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), -- CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), -- CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), -- CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), -- CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), -- CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), -- CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), -- CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), -- CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), -- CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), -- CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), -- CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), -- CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), -- CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), --}; -- - static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) - { - u8 bit = field.offset % 32, word = field.offset / 32; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 20 Jun 2024 10:19:44 -0400 -Subject: media: rockchip: Introduce the rkvdec2 driver - -This driver supports the second generation of the Rockchip Video -decoder, also known as vdpu34x. -It is currently only used on the RK3588(s) SoC. - -There are 2 decoders on the RK3588 SoC that can work in pair to decode -8K video at 30 FPS but currently, only using one core at a time is -supported. - -Scheduling requests between the two cores will be implemented later. - -The core supports H264, HEVC, VP9 and AVS2 decoding but this driver -currently only supports H264. - -The driver is based on rkvdec and they may share some code in the -future. -The decision to make a different driver is mainly because rkvdec2 has -more features and can work with multiple cores. - -The registers are mapped in a struct in RAM using bitfields. It is IO -copied to the HW when all values are configured. -The decision to use such a struct instead of writing buffers one by one -is based on the following reasons: - - Rockchip cores are known to misbehave when registers are not written - in address order, - - Those cores also need the software to write all registers, even if - they are written their default values or are not related to the task - (this core will not start decoding some H264 frames if some VP9 - registers are not written to 0) - - In the future, to support multiple cores, the scheduler could be - optimized by storing the precomputed registers values and copy them - to the HW as soos as a core becomes available. - -This makes the code more readable and may bring performance improvements -in future features. - -Signed-off-by: Detlev Casanova ---- - drivers/staging/media/Kconfig | 1 + - drivers/staging/media/Makefile | 1 + - drivers/staging/media/rkvdec2/Kconfig | 15 + - drivers/staging/media/rkvdec2/Makefile | 3 + - drivers/staging/media/rkvdec2/TODO | 9 + - drivers/staging/media/rkvdec2/rkvdec2-h264.c | 739 ++++++ - drivers/staging/media/rkvdec2/rkvdec2-regs.h | 345 +++ - drivers/staging/media/rkvdec2/rkvdec2.c | 1253 ++++++++++ - drivers/staging/media/rkvdec2/rkvdec2.h | 130 + - 9 files changed, 2496 insertions(+) - -diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/Kconfig -+++ b/drivers/staging/media/Kconfig -@@ -35,6 +35,7 @@ source "drivers/staging/media/meson/vdec/Kconfig" - source "drivers/staging/media/omap4iss/Kconfig" - - source "drivers/staging/media/rkvdec/Kconfig" -+source "drivers/staging/media/rkvdec2/Kconfig" - - source "drivers/staging/media/starfive/Kconfig" - -diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/Makefile -+++ b/drivers/staging/media/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_VIDEO_MAX96712) += max96712/ - obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/ - obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/ -+obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2) += rkvdec2/ - obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive/ - obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ - obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/ -diff --git a/drivers/staging/media/rkvdec2/Kconfig b/drivers/staging/media/rkvdec2/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/Kconfig -@@ -0,0 +1,15 @@ -+# SPDX-License-Identifier: GPL-2.0 -+config VIDEO_ROCKCHIP_VDEC2 -+ tristate "Rockchip Video Decoder driver 2" -+ depends on ARCH_ROCKCHIP || COMPILE_TEST -+ depends on VIDEO_DEV -+ select MEDIA_CONTROLLER -+ select VIDEOBUF2_DMA_CONTIG -+ select VIDEOBUF2_VMALLOC -+ select V4L2_MEM2MEM_DEV -+ select V4L2_H264 -+ help -+ Support for the Rockchip Video Decoder 2 IP present on Rockchip SoCs, -+ which accelerates video decoding. -+ To compile this driver as a module, choose M here: the module -+ will be called rockchip-vdec2. -diff --git a/drivers/staging/media/rkvdec2/Makefile b/drivers/staging/media/rkvdec2/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/Makefile -@@ -0,0 +1,3 @@ -+obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2) += rockchip-vdec2.o -+ -+rockchip-vdec2-y += rkvdec2.o rkvdec2-h264.o -diff --git a/drivers/staging/media/rkvdec2/TODO b/drivers/staging/media/rkvdec2/TODO -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/TODO -@@ -0,0 +1,9 @@ -+* Support for 4:2:2 and 10 bits -+* Support for rockchip IOMMU -+* Support for HEVC and VP9 are planned for this driver. -+ -+ First, the h264 backend needs to be stabilized. -+ -+* Evaluate sharing code with rkvdec -+ -+ As rkvdec is still in staging, this driver stays there as well. -diff --git a/drivers/staging/media/rkvdec2/rkvdec2-h264.c b/drivers/staging/media/rkvdec2/rkvdec2-h264.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/rkvdec2-h264.c -@@ -0,0 +1,739 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder 2 H264 backend -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ * -+ * Based on rkvdec driver by Boris Brezillon -+ */ -+ -+#include -+#include -+ -+#include "rkvdec2.h" -+#include "rkvdec2-regs.h" -+/* This header will move to a rockchip/common folder when de-staging */ -+#include "../rkvdec/rkvdec-h264-cabac.h" -+ -+#define RKVDEC_NUM_REFLIST 3 -+ -+struct rkvdec2_h264_scaling_list { -+ u8 scaling_list_4x4[6][16]; -+ u8 scaling_list_8x8[6][64]; -+ u8 padding[128]; -+}; -+ -+struct rkvdec2_sps { -+ u16 seq_parameter_set_id: 4; -+ u16 profile_idc: 8; -+ u16 constraint_set3_flag: 1; -+ u16 chroma_format_idc: 2; -+ u16 bit_depth_luma: 3; -+ u16 bit_depth_chroma: 3; -+ u16 qpprime_y_zero_transform_bypass_flag: 1; -+ u16 log2_max_frame_num_minus4: 4; -+ u16 max_num_ref_frames: 5; -+ u16 pic_order_cnt_type: 2; -+ u16 log2_max_pic_order_cnt_lsb_minus4: 4; -+ u16 delta_pic_order_always_zero_flag: 1; -+ u16 pic_width_in_mbs: 12; -+ u16 pic_height_in_mbs: 12; -+ u16 frame_mbs_only_flag: 1; -+ u16 mb_adaptive_frame_field_flag: 1; -+ u16 direct_8x8_inference_flag: 1; -+ u16 mvc_extension_enable: 1; -+ u16 num_views: 2; -+ -+ u16 reserved_bits: 12; -+ u16 reserved[11]; -+} __packed; -+ -+struct rkvdec2_pps { -+ u16 pic_parameter_set_id: 8; -+ u16 pps_seq_parameter_set_id: 5; -+ u16 entropy_coding_mode_flag: 1; -+ u16 bottom_field_pic_order_in_frame_present_flag: 1; -+ u16 num_ref_idx_l0_default_active_minus1: 5; -+ u16 num_ref_idx_l1_default_active_minus1: 5; -+ u16 weighted_pred_flag: 1; -+ u16 weighted_bipred_idc: 2; -+ u16 pic_init_qp_minus26: 7; -+ u16 pic_init_qs_minus26: 6; -+ u16 chroma_qp_index_offset: 5; -+ u16 deblocking_filter_control_present_flag: 1; -+ u16 constrained_intra_pred_flag: 1; -+ u16 redundant_pic_cnt_present: 1; -+ u16 transform_8x8_mode_flag: 1; -+ u16 second_chroma_qp_index_offset: 5; -+ u16 scaling_list_enable_flag: 1; -+ u32 scaling_list_address; -+ u16 is_longterm; -+ -+ u8 reserved[3]; -+} __packed; -+ -+struct rkvdec2_rps_entry { -+ u32 dpb_info0: 5; -+ u32 bottom_flag0: 1; -+ u32 view_index_off0: 1; -+ u32 dpb_info1: 5; -+ u32 bottom_flag1: 1; -+ u32 view_index_off1: 1; -+ u32 dpb_info2: 5; -+ u32 bottom_flag2: 1; -+ u32 view_index_off2: 1; -+ u32 dpb_info3: 5; -+ u32 bottom_flag3: 1; -+ u32 view_index_off3: 1; -+ u32 dpb_info4: 5; -+ u32 bottom_flag4: 1; -+ u32 view_index_off4: 1; -+ u32 dpb_info5: 5; -+ u32 bottom_flag5: 1; -+ u32 view_index_off5: 1; -+ u32 dpb_info6: 5; -+ u32 bottom_flag6: 1; -+ u32 view_index_off6: 1; -+ u32 dpb_info7: 5; -+ u32 bottom_flag7: 1; -+ u32 view_index_off7: 1; -+} __packed; -+ -+struct rkvdec2_rps { -+ u16 frame_num[16]; -+ u32 reserved0; -+ struct rkvdec2_rps_entry entries[12]; -+ u32 reserved1[66]; -+} __packed; -+ -+struct rkvdec2_sps_pps { -+ struct rkvdec2_sps sps; -+ struct rkvdec2_pps pps; -+} __packed; -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec2_h264_priv_tbl { -+ u32 cabac_table[928]; -+ struct rkvdec2_h264_scaling_list scaling_list; -+ struct rkvdec2_sps_pps param_set[256]; -+ struct rkvdec2_rps rps; -+}; -+ -+struct rkvdec2_h264_reflists { -+ struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; -+ struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; -+ struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; -+}; -+ -+struct rkvdec2_h264_run { -+ struct rkvdec2_run base; -+ const struct v4l2_ctrl_h264_decode_params *decode_params; -+ const struct v4l2_ctrl_h264_sps *sps; -+ const struct v4l2_ctrl_h264_pps *pps; -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -+ struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES]; -+}; -+ -+struct rkvdec2_h264_ctx { -+ struct rkvdec2_aux_buf priv_tbl; -+ struct rkvdec2_h264_reflists reflists; -+ struct rkvdec2_regs_h264 regs; -+}; -+ -+static void assemble_hw_pps(struct rkvdec2_ctx *ctx, -+ struct rkvdec2_h264_run *run) -+{ -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_h264_sps *sps = run->sps; -+ const struct v4l2_ctrl_h264_pps *pps = run->pps; -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec2_sps_pps *hw_ps; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->sps.seq_parameter_set_id = 0xf; -+ hw_ps->sps.profile_idc = 0xff; -+ hw_ps->sps.constraint_set3_flag = 1; -+ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; -+ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8; -+ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8; -+ hw_ps->sps.qpprime_y_zero_transform_bypass_flag = 0; -+ hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4; -+ hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames; -+ hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type; -+ hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 = -+ sps->log2_max_pic_order_cnt_lsb_minus4; -+ hw_ps->sps.delta_pic_order_always_zero_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); -+ hw_ps->sps.mvc_extension_enable = 1; -+ hw_ps->sps.num_views = 1; -+ -+ /* -+ * Use the SPS values since they are already in macroblocks -+ * dimensions, height can be field height (halved) if -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows -+ * decoding smaller images into larger allocation which can be used -+ * to implementing SVC spatial layer support. -+ */ -+ hw_ps->sps.pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; -+ hw_ps->sps.pic_height_in_mbs = sps->pic_height_in_map_units_minus1 + 1; -+ hw_ps->sps.frame_mbs_only_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); -+ hw_ps->sps.mb_adaptive_frame_field_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); -+ hw_ps->sps.direct_8x8_inference_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); -+ -+ /* write pps */ -+ hw_ps->pps.pic_parameter_set_id = 0xff; -+ hw_ps->pps.pps_seq_parameter_set_id = 0x1f; -+ hw_ps->pps.entropy_coding_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); -+ hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); -+ hw_ps->pps.num_ref_idx_l0_default_active_minus1 = -+ pps->num_ref_idx_l0_default_active_minus1; -+ hw_ps->pps.num_ref_idx_l1_default_active_minus1 = -+ pps->num_ref_idx_l1_default_active_minus1; -+ hw_ps->pps.weighted_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc; -+ hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26; -+ hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26; -+ hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset; -+ hw_ps->pps.deblocking_filter_control_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); -+ hw_ps->pps.constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->pps.redundant_pic_cnt_present = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); -+ hw_ps->pps.transform_8x8_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); -+ hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset; -+ hw_ps->pps.scaling_list_enable_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); -+ -+ /* -+ * To be on the safe side, program the scaling matrix address -+ * -+ * With this set here, -+ * RKVDEC_SWREG12_SENCODARY_EN:sw_scanlist_addr_valid_en -+ * can stay at 0 -+ */ -+ scaling_distance = offsetof(struct rkvdec2_h264_priv_tbl, scaling_list); -+ scaling_list_address = h264_ctx->priv_tbl.dma + scaling_distance; -+ hw_ps->pps.scaling_list_address = scaling_list_address; -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ hw_ps->pps.is_longterm |= (1 << i); -+ } -+} -+ -+static void lookup_ref_buf_idx(struct rkvdec2_ctx *ctx, -+ struct rkvdec2_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ u32 i; -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { -+ buf = vb2_find_buffer(cap_q, dpb[i].reference_ts); -+ if (!buf) { -+ dev_dbg(ctx->dev->dev, "No buffer for reference_ts %llu", -+ dpb[i].reference_ts); -+ } -+ } -+ -+ run->ref_buf[i] = buf; -+ } -+} -+ -+static void set_dpb_info(struct rkvdec2_rps_entry *entries, -+ u8 reflist, -+ u8 refnum, -+ u8 info, -+ bool bottom) -+{ -+ struct rkvdec2_rps_entry *entry = &entries[(reflist * 4) + refnum / 8]; -+ u8 idx = refnum % 8; -+ -+ switch (idx) { -+ case 0: -+ entry->dpb_info0 = info; -+ entry->bottom_flag0 = bottom; -+ break; -+ case 1: -+ entry->dpb_info1 = info; -+ entry->bottom_flag1 = bottom; -+ break; -+ case 2: -+ entry->dpb_info2 = info; -+ entry->bottom_flag2 = bottom; -+ break; -+ case 3: -+ entry->dpb_info3 = info; -+ entry->bottom_flag3 = bottom; -+ break; -+ case 4: -+ entry->dpb_info4 = info; -+ entry->bottom_flag4 = bottom; -+ break; -+ case 5: -+ entry->dpb_info5 = info; -+ entry->bottom_flag5 = bottom; -+ break; -+ case 6: -+ entry->dpb_info6 = info; -+ entry->bottom_flag6 = bottom; -+ break; -+ case 7: -+ entry->dpb_info7 = info; -+ entry->bottom_flag7 = bottom; -+ break; -+ } -+} -+ -+static void assemble_hw_rps(struct rkvdec2_ctx *ctx, -+ struct v4l2_h264_reflist_builder *builder, -+ struct rkvdec2_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ -+ struct rkvdec2_rps *hw_rps = &priv_tbl->rps; -+ u32 i, j; -+ -+ memset(hw_rps, 0, sizeof(priv_tbl->rps)); -+ -+ /* -+ * Assign an invalid pic_num if DPB entry at that position is inactive. -+ * If we assign 0 in that position hardware will treat that as a real -+ * reference picture with pic_num 0, triggering output picture -+ * corruption. -+ */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ hw_rps->frame_num[i] = builder->refs[i].frame_num; -+ } -+ -+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -+ for (i = 0; i < builder->num_valid; i++) { -+ struct v4l2_h264_reference *ref; -+ bool dpb_valid; -+ bool bottom; -+ -+ switch (j) { -+ case 0: -+ ref = &h264_ctx->reflists.p[i]; -+ break; -+ case 1: -+ ref = &h264_ctx->reflists.b0[i]; -+ break; -+ case 2: -+ ref = &h264_ctx->reflists.b1[i]; -+ break; -+ } -+ -+ if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb))) -+ continue; -+ -+ dpb_valid = !!(run->ref_buf[ref->index]); -+ bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; -+ -+ set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom); -+ } -+ } -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec2_ctx *ctx, -+ struct rkvdec2_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling = run->scaling_matrix; -+ const struct v4l2_ctrl_h264_pps *pps = run->pps; -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec2_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; -+ -+ if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) -+ return; -+ -+ BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_4x4) != -+ sizeof(scaling->scaling_list_4x4)); -+ BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_8x8) != -+ sizeof(scaling->scaling_list_8x8)); -+ -+ memcpy(tbl->scaling_list.scaling_list_4x4, -+ scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); -+ -+ memcpy(tbl->scaling_list.scaling_list_8x8, -+ scaling->scaling_list_8x8, -+ sizeof(scaling->scaling_list_8x8)); -+} -+ -+static inline void rkvdec2_memcpy_toio(void __iomem *dst, void *src, size_t len) -+{ -+#ifdef CONFIG_ARM64 -+ __iowrite32_copy(dst, src, len); -+#elif defined(CONFIG_ARM) -+ memcpy_toio(dst, src, len); -+#endif -+} -+ -+static void rkvdec2_write_regs(struct rkvdec2_ctx *ctx) -+{ -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ -+ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, -+ &h264_ctx->regs.common, -+ sizeof(h264_ctx->regs.common)); -+ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, -+ &h264_ctx->regs.h264_param, -+ sizeof(h264_ctx->regs.h264_param)); -+ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, -+ &h264_ctx->regs.common_addr, -+ sizeof(h264_ctx->regs.common_addr)); -+ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, -+ &h264_ctx->regs.h264_addr, -+ sizeof(h264_ctx->regs.h264_addr)); -+ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, -+ &h264_ctx->regs.h264_highpoc, -+ sizeof(h264_ctx->regs.h264_highpoc)); -+} -+ -+static void config_registers(struct rkvdec2_ctx *ctx, -+ struct rkvdec2_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_ctrl_h264_sps *sps = run->sps; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ struct rkvdec2_regs_h264 *regs = &h264_ctx->regs; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t dst_addr; -+ u32 hor_virstride = 0; -+ u32 ver_virstride = 0; -+ u32 y_virstride = 0; -+ u32 offset; -+ u32 pixels; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set H264 mode */ -+ regs->common.reg009.dec_mode = RKVDEC2_MODE_H264; -+ -+ /* Set config */ -+ regs->common.reg011.buf_empty_en = 1; -+ regs->common.reg011.dec_clkgate_e = 1; -+ regs->common.reg011.dec_timeout_e = 1; -+ regs->common.reg011.pix_range_detection_e = 1; -+ -+ /* Set IDR flag */ -+ regs->common.reg013.cur_pic_is_idr = -+ !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC); -+ -+ /* Set input stream length */ -+ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set max slice number */ -+ regs->common.reg017.slice_num = MAX_SLICE_NUMBER; -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; -+ ver_virstride = round_up(dst_fmt->height, 16); -+ y_virstride = hor_virstride * ver_virstride; -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->common.reg018.y_hor_virstride = hor_virstride / 16; -+ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg020.y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg026.swreg_block_gating_e = 0xfffef; -+ regs->common.reg026.reg_cfg_gating_en = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < RKVDEC2_1080P_PIXELS) -+ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_1080p; -+ else if (pixels < RKVDEC2_4K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_4K; -+ else if (pixels < RKVDEC2_8K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_8K; -+ -+ /* Set TOP and BOTTOM POCs */ -+ regs->h264_param.cur_top_poc = dec_params->top_field_order_cnt; -+ regs->h264_param.cur_bot_poc = dec_params->bottom_field_order_cnt; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct vb2_buffer *vb_buf = run->ref_buf[i]; -+ dma_addr_t buf_dma; -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb_buf) -+ vb_buf = &dst_buf->vb2_buf; -+ -+ buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ -+ /* Set reference addresses */ -+ regs->h264_addr.ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->h264_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; -+ -+ struct rkvdec2_h264_ref_info *ref_info = -+ ®s->h264_param.ref_info_regs[i / 4].ref_info[i % 4]; -+ -+ ref_info->ref_field = -+ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD); -+ ref_info->ref_colmv_use_flag = -+ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); -+ ref_info->ref_topfield_used = -+ !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF); -+ ref_info->ref_botfield_used = -+ !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF); -+ -+ regs->h264_param.ref_pocs[i * 2] = -+ dpb[i].top_field_order_cnt; -+ regs->h264_param.ref_pocs[i * 2 + 1] = -+ dpb[i].bottom_field_order_cnt; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.rlc_base = rlc_addr; -+ regs->common_addr.rlcwrite_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->common_addr.decout_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) -+ regs->common_addr.rcb_base[i] = ctx->rcb_bufs[i].dma; -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec2_h264_priv_tbl, param_set); -+ regs->h264_addr.pps_base = priv_start_addr + offset; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec2_h264_priv_tbl, rps); -+ regs->h264_addr.rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec2_h264_priv_tbl, cabac_table); -+ regs->h264_addr.cabactbl_base = priv_start_addr + offset; -+ -+ rkvdec2_write_regs(ctx); -+} -+ -+#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec2_h264_adjust_fmt(struct rkvdec2_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_H264_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static int rkvdec2_h264_validate_sps(struct rkvdec2_ctx *ctx, -+ const struct v4l2_ctrl_h264_sps *sps) -+{ -+ unsigned int width, height; -+ -+ /* -+ * TODO: The hardware supports 10-bit and 4:2:2 profiles, -+ * but it's currently broken in the driver. -+ * Reject them for now, until it's fixed. -+ */ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0) -+ /* Only 8-bit is supported */ -+ return -EINVAL; -+ -+ width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -+ height = (sps->pic_height_in_map_units_minus1 + 1) * 16; -+ -+ /* -+ * When frame_mbs_only_flag is not set, this is field height, -+ * which is half the final height (see (7-8) in the -+ * specification) -+ */ -+ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) -+ height *= 2; -+ -+ if (width > ctx->coded_fmt.fmt.pix_mp.width || -+ height > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec2_h264_start(struct rkvdec2_ctx *ctx) -+{ -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ struct rkvdec2_h264_priv_tbl *priv_tbl; -+ struct rkvdec2_h264_ctx *h264_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ if (ret) -+ return ret; -+ -+ h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); -+ if (!h264_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &h264_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ h264_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ h264_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table, -+ sizeof(rkvdec_h264_cabac_table)); -+ -+ ctx->priv = h264_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(h264_ctx); -+ return ret; -+} -+ -+static void rkvdec2_h264_stop(struct rkvdec2_ctx *ctx) -+{ -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size, -+ h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma); -+ kfree(h264_ctx); -+} -+ -+static void rkvdec2_h264_run_preamble(struct rkvdec2_ctx *ctx, -+ struct rkvdec2_h264_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec2_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec2_h264_run(struct rkvdec2_ctx *ctx) -+{ -+ struct v4l2_h264_reflist_builder reflist_builder; -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec2_h264_run run; -+ -+ rkvdec2_h264_run_preamble(ctx, &run); -+ -+ /* Build the P/B{0,1} ref lists. */ -+ v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params, -+ run.sps, run.decode_params->dpb); -+ v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); -+ v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, -+ h264_ctx->reflists.b1); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ lookup_ref_buf_idx(ctx, &run); -+ assemble_hw_rps(ctx, &reflist_builder, &run); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec2_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ /* Start decoding! */ -+ writel(RKVDEC2_REG_DEC_E_BIT, rkvdec->regs + RKVDEC2_REG_DEC_E); -+ -+ return 0; -+} -+ -+static int rkvdec2_h264_try_ctrl(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) -+ return rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops = { -+ .adjust_fmt = rkvdec2_h264_adjust_fmt, -+ .start = rkvdec2_h264_start, -+ .stop = rkvdec2_h264_stop, -+ .run = rkvdec2_h264_run, -+ .try_ctrl = rkvdec2_h264_try_ctrl, -+}; -diff --git a/drivers/staging/media/rkvdec2/rkvdec2-regs.h b/drivers/staging/media/rkvdec2/rkvdec2-regs.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/rkvdec2-regs.h -@@ -0,0 +1,345 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip Video Decoder 2 driver registers description -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#ifndef _RKVDEC_REGS_H_ -+#define _RKVDEC_REGS_H_ -+ -+#define OFFSET_COMMON_REGS (8 * sizeof(u32)) -+#define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(u32)) -+#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(u32)) -+#define OFFSET_CODEC_ADDR_REGS (160 * sizeof(u32)) -+#define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(u32)) -+ -+#define RKVDEC2_MODE_HEVC 0 -+#define RKVDEC2_MODE_H264 1 -+#define RKVDEC2_MODE_VP9 2 -+#define RKVDEC2_MODE_AVS2 3 -+ -+#define MAX_SLICE_NUMBER 0x3fff -+ -+#define RKVDEC2_1080P_PIXELS (1920 * 1080) -+#define RKVDEC2_4K_PIXELS (4096 * 2304) -+#define RKVDEC2_8K_PIXELS (7680 * 4320) -+#define RKVDEC2_TIMEOUT_1080p (0xefffff) -+#define RKVDEC2_TIMEOUT_4K (0x2cfffff) -+#define RKVDEC2_TIMEOUT_8K (0x4ffffff) -+ -+#define RKVDEC2_REG_DEC_E 0x028 -+#define RKVDEC2_REG_DEC_E_BIT 1 -+ -+#define RKVDEC2_REG_IMPORTANT_EN 0x02c -+#define RKVDEC2_REG_DEC_IRQ_DISABLE BIT(4) -+ -+#define RKVDEC2_REG_STA_INT 0x380 -+#define STA_INT_DEC_RDY_STA BIT(2) -+ -+/* base: OFFSET_COMMON_REGS */ -+struct rkvdec2_regs_common { -+ struct rkvdec2_in_out { -+ u32 in_endian : 1; -+ u32 in_swap32_e : 1; -+ u32 in_swap64_e : 1; -+ u32 str_endian : 1; -+ u32 str_swap32_e : 1; -+ u32 str_swap64_e : 1; -+ u32 out_endian : 1; -+ u32 out_swap32_e : 1; -+ u32 out_cbcr_swap : 1; -+ u32 out_swap64_e : 1; -+ u32 reserved : 22; -+ } reg008; -+ -+ struct rkvdec2_dec_mode { -+ u32 dec_mode : 10; -+ u32 reserved : 22; -+ } reg009; -+ -+ struct rkvdec2_dec_e { -+ u32 dec_e : 1; -+ u32 reserved : 31; -+ } reg010; -+ -+ struct rkvdec2_important_en { -+ u32 reserved : 1; -+ u32 dec_clkgate_e : 1; -+ u32 dec_e_strmd_clkgate_dis : 1; -+ u32 reserved0 : 1; -+ -+ u32 dec_irq_dis : 1; -+ u32 dec_timeout_e : 1; -+ u32 buf_empty_en : 1; -+ u32 reserved1 : 3; -+ -+ u32 dec_e_rewrite_valid : 1; -+ u32 reserved2 : 9; -+ u32 softrst_en_p : 1; -+ u32 force_softreset_valid : 1; -+ u32 reserved3 : 2; -+ u32 pix_range_detection_e : 1; -+ u32 reserved4 : 7; -+ } reg011; -+ -+ struct rkvdec2_sencodary_en { -+ u32 wr_ddr_align_en : 1; -+ u32 colmv_compress_en : 1; -+ u32 fbc_e : 1; -+ u32 reserved0 : 1; -+ -+ u32 buspr_slot_disable : 1; -+ u32 error_info_en : 1; -+ u32 info_collect_en : 1; -+ u32 wait_reset_en : 1; -+ -+ u32 scanlist_addr_valid_en : 1; -+ u32 scale_down_en : 1; -+ u32 error_cfg_wr_disable : 1; -+ u32 reserved1 : 21; -+ } reg012; -+ -+ struct rkvdec2_en_mode_set { -+ u32 timeout_mode : 1; -+ u32 req_timeout_rst_sel : 1; -+ u32 reserved0 : 1; -+ u32 dec_commonirq_mode : 1; -+ u32 reserved1 : 2; -+ u32 stmerror_waitdecfifo_empty : 1; -+ u32 reserved2 : 2; -+ u32 h26x_streamd_error_mode : 1; -+ u32 reserved3 : 2; -+ u32 allow_not_wr_unref_bframe : 1; -+ u32 fbc_output_wr_disable : 1; -+ u32 reserved4 : 1; -+ u32 colmv_error_mode : 1; -+ -+ u32 reserved5 : 2; -+ u32 h26x_error_mode : 1; -+ u32 reserved6 : 2; -+ u32 ycacherd_prior : 1; -+ u32 reserved7 : 2; -+ u32 cur_pic_is_idr : 1; -+ u32 reserved8 : 1; -+ u32 right_auto_rst_disable : 1; -+ u32 frame_end_err_rst_flag : 1; -+ u32 rd_prior_mode : 1; -+ u32 rd_ctrl_prior_mode : 1; -+ u32 reserved9 : 1; -+ u32 filter_outbuf_mode : 1; -+ } reg013; -+ -+ struct rkvdec2_fbc_param_set { -+ u32 fbc_force_uncompress : 1; -+ -+ u32 reserved0 : 2; -+ u32 allow_16x8_cp_flag : 1; -+ u32 reserved1 : 2; -+ -+ u32 fbc_h264_exten_4or8_flag : 1; -+ u32 reserved2 : 25; -+ } reg014; -+ -+ struct rkvdec2_stream_param_set { -+ u32 rlc_mode_direct_write : 1; -+ u32 rlc_mode : 1; -+ u32 reserved0 : 3; -+ -+ u32 strm_start_bit : 7; -+ u32 reserved1 : 20; -+ } reg015; -+ -+ u32 stream_len; -+ -+ struct rkvdec2_slice_number { -+ u32 slice_num : 25; -+ u32 reserved : 7; -+ } reg017; -+ -+ struct rkvdec2_y_hor_stride { -+ u32 y_hor_virstride : 16; -+ u32 reserved : 16; -+ } reg018; -+ -+ struct rkvdec2_uv_hor_stride { -+ u32 uv_hor_virstride : 16; -+ u32 reserved : 16; -+ } reg019; -+ -+ struct rkvdec2_y_stride { -+ u32 y_virstride : 28; -+ u32 reserved : 4; -+ } reg020; -+ -+ struct rkvdec2_error_ctrl_set { -+ u32 inter_error_prc_mode : 1; -+ u32 error_intra_mode : 1; -+ u32 error_deb_en : 1; -+ u32 picidx_replace : 5; -+ u32 error_spread_e : 1; -+ u32 reserved0 : 3; -+ u32 error_inter_pred_cross_slice : 1; -+ u32 reserved1 : 11; -+ u32 roi_error_ctu_cal_en : 1; -+ u32 reserved2 : 7; -+ } reg021; -+ -+ struct rkvdec2_err_roi_ctu_offset_start { -+ u32 roi_x_ctu_offset_st : 12; -+ u32 reserved0 : 4; -+ u32 roi_y_ctu_offset_st : 12; -+ u32 reserved1 : 4; -+ } reg022; -+ -+ struct rkvdec2_err_roi_ctu_offset_end { -+ u32 roi_x_ctu_offset_end : 12; -+ u32 reserved0 : 4; -+ u32 roi_y_ctu_offset_end : 12; -+ u32 reserved1 : 4; -+ } reg023; -+ -+ struct rkvdec2_cabac_error_en_lowbits { -+ u32 cabac_err_en_lowbits : 32; -+ } reg024; -+ -+ struct rkvdec2_cabac_error_en_highbits { -+ u32 cabac_err_en_highbits : 30; -+ u32 reserved : 2; -+ } reg025; -+ -+ struct rkvdec2_block_gating_en { -+ u32 swreg_block_gating_e : 20; -+ u32 reserved : 11; -+ u32 reg_cfg_gating_en : 1; -+ } reg026; -+ -+ struct SW027_CORE_SAFE_PIXELS { -+ u32 core_safe_x_pixels : 16; -+ u32 core_safe_y_pixels : 16; -+ } reg027; -+ -+ struct rkvdec2_multiply_core_ctrl { -+ u32 swreg_vp9_wr_prob_idx : 3; -+ u32 reserved0 : 1; -+ u32 swreg_vp9_rd_prob_idx : 3; -+ u32 reserved1 : 1; -+ -+ u32 swreg_ref_req_advance_flag : 1; -+ u32 sw_colmv_req_advance_flag : 1; -+ u32 sw_poc_only_highbit_flag : 1; -+ u32 sw_poc_arb_flag : 1; -+ -+ u32 reserved2 : 4; -+ u32 sw_film_idx : 10; -+ u32 reserved3 : 2; -+ u32 sw_pu_req_mismatch_dis : 1; -+ u32 sw_colmv_req_mismatch_dis : 1; -+ u32 reserved4 : 2; -+ } reg028; -+ -+ struct SW029_SCALE_DOWN_CTRL { -+ u32 scale_down_hor_ratio : 2; -+ u32 reserved0 : 6; -+ u32 scale_down_vrz_ratio : 2; -+ u32 reserved1 : 22; -+ } reg029; -+ -+ struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE { -+ u32 y_scale_down_hor_stride : 20; -+ u32 reserved0 : 12; -+ } reg030; -+ -+ struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE { -+ u32 uv_scale_down_hor_stride : 20; -+ u32 reserved0 : 12; -+ } reg031; -+ -+ u32 timeout_threshold; -+} __packed; -+ -+/* base: OFFSET_COMMON_ADDR_REGS */ -+struct rkvdec2_regs_common_addr { -+ u32 rlc_base; -+ u32 rlcwrite_base; -+ u32 decout_base; -+ u32 colmv_cur_base; -+ u32 error_ref_base; -+ u32 rcb_base[10]; -+} __packed; -+ -+/* base: OFFSET_CODEC_PARAMS_REGS */ -+struct rkvdec2_regs_h264_params { -+ struct rkvdec2_h26x_set { -+ u32 h26x_frame_orslice : 1; -+ u32 h26x_rps_mode : 1; -+ u32 h26x_stream_mode : 1; -+ u32 h26x_stream_lastpacket : 1; -+ u32 h264_firstslice_flag : 1; -+ u32 reserved : 27; -+ } reg064; -+ -+ u32 cur_top_poc; -+ u32 cur_bot_poc; -+ u32 ref_pocs[32]; -+ -+ struct rkvdec2_h264_info { -+ struct rkvdec2_h264_ref_info { -+ u32 ref_field : 1; -+ u32 ref_topfield_used : 1; -+ u32 ref_botfield_used : 1; -+ u32 ref_colmv_use_flag : 1; -+ u32 ref_reserved : 4; -+ } __packed ref_info[4]; -+ } __packed ref_info_regs[4]; -+ -+ u32 reserved_103_111[9]; -+ -+ struct rkvdec2_error_ref_info { -+ u32 avs2_ref_error_field : 1; -+ u32 avs2_ref_error_topfield : 1; -+ u32 ref_error_topfield_used : 1; -+ u32 ref_error_botfield_used : 1; -+ u32 reserved : 28; -+ } reg112; -+} __packed; -+ -+/* base: OFFSET_CODEC_ADDR_REGS */ -+struct rkvdec2_regs_h264_addr { -+ u32 reserved_160; -+ u32 pps_base; -+ u32 reserved_162; -+ u32 rps_base; -+ u32 ref_base[16]; -+ u32 scanlist_addr; -+ u32 colmv_base[16]; -+ u32 cabactbl_base; -+} __packed; -+ -+struct rkvdec2_regs_h264_highpoc { -+ struct rkvdec2_ref_poc_highbit { -+ u32 ref0_poc_highbit : 4; -+ u32 ref1_poc_highbit : 4; -+ u32 ref2_poc_highbit : 4; -+ u32 ref3_poc_highbit : 4; -+ u32 ref4_poc_highbit : 4; -+ u32 ref5_poc_highbit : 4; -+ u32 ref6_poc_highbit : 4; -+ u32 ref7_poc_highbit : 4; -+ } reg200[4]; -+ struct rkvdec2_cur_poc_highbit { -+ u32 cur_poc_highbit : 4; -+ u32 reserved : 28; -+ } reg204; -+} __packed; -+ -+struct rkvdec2_regs_h264 { -+ struct rkvdec2_regs_common common; -+ struct rkvdec2_regs_h264_params h264_param; -+ struct rkvdec2_regs_common_addr common_addr; -+ struct rkvdec2_regs_h264_addr h264_addr; -+ struct rkvdec2_regs_h264_highpoc h264_highpoc; -+} __packed; -+ -+#endif /* __RKVDEC_REGS_H__ */ -diff --git a/drivers/staging/media/rkvdec2/rkvdec2.c b/drivers/staging/media/rkvdec2/rkvdec2.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/rkvdec2.c -@@ -0,0 +1,1253 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder 2 driver -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ * -+ * Based on rkvdec driver by Boris Brezillon -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "rkvdec2.h" -+ -+static int rkvdec2_try_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec2_ctx *ctx = container_of(ctrl->handler, struct rkvdec2_ctx, ctrl_hdl); -+ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ -+ if (desc->ops->try_ctrl) -+ return desc->ops->try_ctrl(ctx, ctrl); -+ -+ return 0; -+} -+ -+static const struct v4l2_ctrl_ops rkvdec2_ctrl_ops = { -+ .try_ctrl = rkvdec2_try_ctrl, -+}; -+ -+static const struct rkvdec2_ctrl_desc rkvdec2_h264_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_SPS, -+ .cfg.ops = &rkvdec2_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_H264_START_CODE, -+ .cfg.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, -+ .cfg.menu_skip_mask = -+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), -+ .cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_1, -+ }, -+}; -+ -+static const struct rkvdec2_ctrls rkvdec2_h264_ctrls = { -+ .ctrls = rkvdec2_h264_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec2_h264_ctrl_descs), -+}; -+ -+static const u32 rkvdec2_h264_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12 -+}; -+ -+static const struct rkvdec2_coded_fmt_desc rkvdec2_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, -+ .frmsize = { -+ .min_width = 16, -+ .max_width = 65520, -+ .step_width = 16, -+ .min_height = 16, -+ .max_height = 65520, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec2_h264_ctrls, -+ .ops = &rkvdec2_h264_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec2_h264_decoded_fmts), -+ .decoded_fmts = rkvdec2_h264_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ }, -+}; -+ -+enum rcb_axis { -+ PIC_WIDTH = 0, -+ PIC_HEIGHT = 1 -+}; -+ -+struct rcb_size_info { -+ u8 multiplier; -+ enum rcb_axis axis; -+}; -+ -+static struct rcb_size_info rcb_sizes[] = { -+ {6, PIC_WIDTH}, // intrar -+ {1, PIC_WIDTH}, // transdr (Is actually 0.4*pic_width) -+ {1, PIC_HEIGHT}, // transdc (Is actually 0.1*pic_height) -+ {3, PIC_WIDTH}, // streamdr -+ {6, PIC_WIDTH}, // interr -+ {3, PIC_HEIGHT}, // interc -+ {22, PIC_WIDTH}, // dblkr -+ {6, PIC_WIDTH}, // saor -+ {11, PIC_WIDTH}, // fbcr -+ {67, PIC_HEIGHT}, // filtc col -+}; -+ -+#define RCB_SIZE(n) (rcb_sizes[(n)].multiplier * (rcb_sizes[(n)].axis ? height : width)) -+ -+static const struct rkvdec2_coded_fmt_desc * -+rkvdec2_find_coded_fmt_desc(u32 fourcc) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) { -+ if (rkvdec2_coded_fmts[i].fourcc == fourcc) -+ return &rkvdec2_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static void rkvdec2_reset_fmt(struct rkvdec2_ctx *ctx, struct v4l2_format *f, -+ u32 fourcc) -+{ -+ memset(f, 0, sizeof(*f)); -+ f->fmt.pix_mp.pixelformat = fourcc; -+ f->fmt.pix_mp.field = V4L2_FIELD_NONE; -+ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; -+ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; -+ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; -+ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; -+} -+ -+static void rkvdec2_reset_coded_fmt(struct rkvdec2_ctx *ctx) -+{ -+ struct v4l2_format *f = &ctx->coded_fmt; -+ -+ ctx->coded_fmt_desc = &rkvdec2_coded_fmts[0]; -+ rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); -+ -+ f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -+ f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width; -+ f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height; -+ -+ if (ctx->coded_fmt_desc->ops->adjust_fmt) -+ ctx->coded_fmt_desc->ops->adjust_fmt(ctx, f); -+} -+ -+static void rkvdec2_reset_decoded_fmt(struct rkvdec2_ctx *ctx) -+{ -+ struct v4l2_format *f = &ctx->decoded_fmt; -+ -+ rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); -+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -+ v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, -+ ctx->coded_fmt_desc->decoded_fmts[0], -+ ctx->coded_fmt.fmt.pix_mp.width, -+ ctx->coded_fmt.fmt.pix_mp.height); -+ -+ ctx->colmv_offset = f->fmt.pix_mp.plane_fmt[0].sizeimage; -+ -+ f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * -+ DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * -+ DIV_ROUND_UP(f->fmt.pix_mp.height, 16); -+} -+ -+static int rkvdec2_enum_framesizes(struct file *file, void *priv, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ const struct rkvdec2_coded_fmt_desc *fmt; -+ -+ if (fsize->index != 0) -+ return -EINVAL; -+ -+ fmt = rkvdec2_find_coded_fmt_desc(fsize->pixel_format); -+ if (!fmt) -+ return -EINVAL; -+ -+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; -+ fsize->stepwise = fmt->frmsize; -+ return 0; -+} -+ -+static int rkvdec2_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ struct rkvdec2_dev *rkvdec = video_drvdata(file); -+ struct video_device *vdev = video_devdata(file); -+ -+ strscpy(cap->driver, rkvdec->dev->driver->name, -+ sizeof(cap->driver)); -+ strscpy(cap->card, vdev->name, sizeof(cap->card)); -+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", -+ rkvdec->dev->driver->name); -+ return 0; -+} -+ -+static int rkvdec2_try_capture_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ const struct rkvdec2_coded_fmt_desc *coded_desc; -+ unsigned int i; -+ -+ /* -+ * The codec context should point to a coded format desc, if the format -+ * on the coded end has not been set yet, it should point to the -+ * default value. -+ */ -+ coded_desc = ctx->coded_fmt_desc; -+ if (WARN_ON(!coded_desc)) -+ return -EINVAL; -+ -+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -+ break; -+ } -+ -+ if (i == coded_desc->num_decoded_fmts) -+ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ -+ /* Always apply the frmsize constraint of the coded end. */ -+ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -+ pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height); -+ v4l2_apply_frmsize_constraints(&pix_mp->width, -+ &pix_mp->height, -+ &coded_desc->frmsize); -+ -+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -+ pix_mp->width, pix_mp->height); -+ -+ pix_mp->plane_fmt[0].sizeimage += -+ 128 * -+ DIV_ROUND_UP(pix_mp->width, 16) * -+ DIV_ROUND_UP(pix_mp->height, 16); -+ -+ pix_mp->field = V4L2_FIELD_NONE; -+ -+ return 0; -+} -+ -+static int rkvdec2_try_output_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ const struct rkvdec2_coded_fmt_desc *desc; -+ -+ desc = rkvdec2_find_coded_fmt_desc(pix_mp->pixelformat); -+ if (!desc) { -+ pix_mp->pixelformat = rkvdec2_coded_fmts[0].fourcc; -+ desc = &rkvdec2_coded_fmts[0]; -+ } -+ -+ v4l2_apply_frmsize_constraints(&pix_mp->width, -+ &pix_mp->height, -+ &desc->frmsize); -+ -+ pix_mp->field = V4L2_FIELD_NONE; -+ /* All coded formats are considered single planar for now. */ -+ pix_mp->num_planes = 1; -+ -+ if (desc->ops->adjust_fmt) { -+ int ret; -+ -+ ret = desc->ops->adjust_fmt(ctx, f); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec2_s_capture_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ struct vb2_queue *vq; -+ int ret; -+ -+ /* Change not allowed if queue is busy */ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, -+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); -+ if (vb2_is_busy(vq)) -+ return -EBUSY; -+ -+ ret = rkvdec2_try_capture_fmt(file, priv, f); -+ if (ret) -+ return ret; -+ -+ ctx->decoded_fmt = *f; -+ return 0; -+} -+ -+static int rkvdec2_s_output_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct rkvdec2_coded_fmt_desc *desc; -+ struct v4l2_format *cap_fmt; -+ struct vb2_queue *peer_vq, *vq; -+ int ret; -+ -+ /* -+ * In order to support dynamic resolution change, the decoder admits -+ * a resolution change, as long as the pixelformat remains. Can't be -+ * done if streaming. -+ */ -+ vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); -+ if (vb2_is_streaming(vq) || -+ (vb2_is_busy(vq) && -+ f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat)) -+ return -EBUSY; -+ -+ /* -+ * Since format change on the OUTPUT queue will reset the CAPTURE -+ * queue, we can't allow doing so when the CAPTURE queue has buffers -+ * allocated. -+ */ -+ peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); -+ if (vb2_is_busy(peer_vq)) -+ return -EBUSY; -+ -+ ret = rkvdec2_try_output_fmt(file, priv, f); -+ if (ret) -+ return ret; -+ -+ desc = rkvdec2_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ if (!desc) -+ return -EINVAL; -+ ctx->coded_fmt_desc = desc; -+ ctx->coded_fmt = *f; -+ -+ /* -+ * Current decoded format might have become invalid with newly -+ * selected codec, so reset it to default just to be safe and -+ * keep internal driver state sane. User is mandated to set -+ * the decoded format again after we return, so we don't need -+ * anything smarter. -+ * -+ * Note that this will propagate any size changes to the decoded format. -+ */ -+ rkvdec2_reset_decoded_fmt(ctx); -+ -+ /* Propagate colorspace information to capture. */ -+ cap_fmt = &ctx->decoded_fmt; -+ cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace; -+ cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; -+ cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; -+ cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; -+ -+ /* Enable format specific queue features */ -+ vq->subsystem_flags |= desc->subsystem_flags; -+ -+ return 0; -+} -+ -+static int rkvdec2_g_output_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ -+ *f = ctx->coded_fmt; -+ return 0; -+} -+ -+static int rkvdec2_g_capture_fmt(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ -+ *f = ctx->decoded_fmt; -+ return 0; -+} -+ -+static int rkvdec2_enum_output_fmt(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ if (f->index >= ARRAY_SIZE(rkvdec2_coded_fmts)) -+ return -EINVAL; -+ -+ f->pixelformat = rkvdec2_coded_fmts[f->index].fourcc; -+ return 0; -+} -+ -+static int rkvdec2_enum_capture_fmt(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); -+ -+ if (WARN_ON(!ctx->coded_fmt_desc)) -+ return -EINVAL; -+ -+ if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) -+ return -EINVAL; -+ -+ f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; -+ return 0; -+} -+ -+static const struct v4l2_ioctl_ops rkvdec2_ioctl_ops = { -+ .vidioc_querycap = rkvdec2_querycap, -+ .vidioc_enum_framesizes = rkvdec2_enum_framesizes, -+ -+ .vidioc_try_fmt_vid_cap_mplane = rkvdec2_try_capture_fmt, -+ .vidioc_try_fmt_vid_out_mplane = rkvdec2_try_output_fmt, -+ .vidioc_s_fmt_vid_out_mplane = rkvdec2_s_output_fmt, -+ .vidioc_s_fmt_vid_cap_mplane = rkvdec2_s_capture_fmt, -+ .vidioc_g_fmt_vid_out_mplane = rkvdec2_g_output_fmt, -+ .vidioc_g_fmt_vid_cap_mplane = rkvdec2_g_capture_fmt, -+ .vidioc_enum_fmt_vid_out = rkvdec2_enum_output_fmt, -+ .vidioc_enum_fmt_vid_cap = rkvdec2_enum_capture_fmt, -+ -+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, -+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, -+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, -+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, -+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, -+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, -+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, -+ -+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+ -+ .vidioc_streamon = v4l2_m2m_ioctl_streamon, -+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, -+ -+ .vidioc_decoder_cmd = v4l2_m2m_ioctl_stateless_decoder_cmd, -+ .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_stateless_try_decoder_cmd, -+}; -+ -+static int rkvdec2_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers, -+ unsigned int *num_planes, unsigned int sizes[], -+ struct device *alloc_devs[]) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_format *f; -+ unsigned int i; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ f = &ctx->coded_fmt; -+ else -+ f = &ctx->decoded_fmt; -+ -+ if (*num_planes) { -+ if (*num_planes != f->fmt.pix_mp.num_planes) -+ return -EINVAL; -+ -+ for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { -+ if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage) -+ return -EINVAL; -+ } -+ } else { -+ *num_planes = f->fmt.pix_mp.num_planes; -+ for (i = 0; i < f->fmt.pix_mp.num_planes; i++) -+ sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec2_buf_prepare(struct vb2_buffer *vb) -+{ -+ struct vb2_queue *vq = vb->vb2_queue; -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); -+ struct v4l2_format *f; -+ unsigned int i; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ f = &ctx->coded_fmt; -+ else -+ f = &ctx->decoded_fmt; -+ -+ for (i = 0; i < f->fmt.pix_mp.num_planes; ++i) { -+ u32 sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; -+ -+ if (vb2_plane_size(vb, i) < sizeimage) -+ return -EINVAL; -+ } -+ -+ /* -+ * Buffer's bytesused must be written by driver for CAPTURE buffers. -+ * (for OUTPUT buffers, if userspace passes 0 bytesused, v4l2-core sets -+ * it to buffer length). -+ */ -+ if (V4L2_TYPE_IS_CAPTURE(vq->type)) -+ vb2_set_plane_payload(vb, 0, f->fmt.pix_mp.plane_fmt[0].sizeimage); -+ -+ return 0; -+} -+ -+static void rkvdec2_buf_queue(struct vb2_buffer *vb) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); -+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -+ -+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); -+} -+ -+static int rkvdec2_buf_out_validate(struct vb2_buffer *vb) -+{ -+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -+ -+ vbuf->field = V4L2_FIELD_NONE; -+ return 0; -+} -+ -+static void rkvdec2_buf_request_complete(struct vb2_buffer *vb) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); -+ -+ v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl); -+} -+ -+static void rkvdec2_free_rcb(struct rkvdec2_ctx *ctx) -+{ -+ u32 width, height; -+ int i; -+ -+ width = ctx->decoded_fmt.fmt.pix_mp.width; -+ height = ctx->decoded_fmt.fmt.pix_mp.height; -+ -+ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) { -+ if (!ctx->rcb_bufs[i].cpu) -+ continue; -+ -+ switch (ctx->rcb_bufs[i].type) { -+ case RKVDEC2_ALLOC_SRAM: -+ gen_pool_free(ctx->dev->sram_pool, -+ (unsigned long)ctx->rcb_bufs[i].cpu, -+ RCB_SIZE(i)); -+ break; -+ case RKVDEC2_ALLOC_DMA: -+ dma_free_coherent(ctx->dev->dev, -+ RCB_SIZE(i), -+ ctx->rcb_bufs[i].cpu, -+ ctx->rcb_bufs[i].dma); -+ break; -+ } -+ } -+} -+ -+static int rkvdec2_allocate_rcb(struct rkvdec2_ctx *ctx) -+{ -+ int ret, i; -+ u32 width, height; -+ -+ memset(ctx->rcb_bufs, 0, sizeof(*ctx->rcb_bufs)); -+ -+ width = ctx->decoded_fmt.fmt.pix_mp.width; -+ height = ctx->decoded_fmt.fmt.pix_mp.height; -+ -+ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) { -+ void *cpu = NULL; -+ dma_addr_t dma; -+ size_t rcb_size = RCB_SIZE(i); -+ enum rkvdec2_alloc_type alloc_type = RKVDEC2_ALLOC_SRAM; -+ -+ if (ctx->dev->sram_pool) { -+ cpu = gen_pool_dma_zalloc_align(ctx->dev->sram_pool, -+ rcb_size, -+ &dma, -+ 64); -+ } -+ -+ /* Fallback to RAM */ -+ if (!cpu) { -+ cpu = dma_alloc_coherent(ctx->dev->dev, -+ rcb_size, -+ &dma, -+ GFP_KERNEL); -+ alloc_type = RKVDEC2_ALLOC_DMA; -+ } -+ -+ if (!cpu) { -+ ret = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ ctx->rcb_bufs[i].cpu = cpu; -+ ctx->rcb_bufs[i].dma = dma; -+ ctx->rcb_bufs[i].size = rcb_size; -+ ctx->rcb_bufs[i].type = alloc_type; -+ } -+ -+ return 0; -+ -+err_alloc: -+ rkvdec2_free_rcb(ctx); -+ -+ return ret; -+} -+ -+static int rkvdec2_start_streaming(struct vb2_queue *q, unsigned int count) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q); -+ const struct rkvdec2_coded_fmt_desc *desc; -+ int ret; -+ -+ if (V4L2_TYPE_IS_CAPTURE(q->type)) -+ return 0; -+ -+ desc = ctx->coded_fmt_desc; -+ if (WARN_ON(!desc)) -+ return -EINVAL; -+ -+ ret = rkvdec2_allocate_rcb(ctx); -+ if (ret) -+ return ret; -+ -+ if (desc->ops->start) { -+ ret = desc->ops->start(ctx); -+ if (ret) -+ goto err_ops_start; -+ } -+ -+ return 0; -+ -+err_ops_start: -+ rkvdec2_free_rcb(ctx); -+ -+ return ret; -+} -+ -+static void rkvdec2_queue_cleanup(struct vb2_queue *vq, u32 state) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); -+ -+ while (true) { -+ struct vb2_v4l2_buffer *vbuf; -+ -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -+ else -+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -+ -+ if (!vbuf) -+ break; -+ -+ v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, -+ &ctx->ctrl_hdl); -+ v4l2_m2m_buf_done(vbuf, state); -+ } -+} -+ -+static void rkvdec2_stop_streaming(struct vb2_queue *q) -+{ -+ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q); -+ -+ if (V4L2_TYPE_IS_OUTPUT(q->type)) { -+ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ -+ if (WARN_ON(!desc)) -+ return; -+ -+ if (desc->ops->stop) -+ desc->ops->stop(ctx); -+ -+ rkvdec2_free_rcb(ctx); -+ } -+ -+ rkvdec2_queue_cleanup(q, VB2_BUF_STATE_ERROR); -+} -+ -+static const struct vb2_ops rkvdec2_queue_ops = { -+ .queue_setup = rkvdec2_queue_setup, -+ .buf_prepare = rkvdec2_buf_prepare, -+ .buf_queue = rkvdec2_buf_queue, -+ .buf_out_validate = rkvdec2_buf_out_validate, -+ .buf_request_complete = rkvdec2_buf_request_complete, -+ .start_streaming = rkvdec2_start_streaming, -+ .stop_streaming = rkvdec2_stop_streaming, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+}; -+ -+static int rkvdec2_request_validate(struct media_request *req) -+{ -+ unsigned int count; -+ -+ count = vb2_request_buffer_cnt(req); -+ if (!count) -+ return -ENOENT; -+ else if (count > 1) -+ return -EINVAL; -+ -+ return vb2_request_validate(req); -+} -+ -+static const struct media_device_ops rkvdec2_media_ops = { -+ .req_validate = rkvdec2_request_validate, -+ .req_queue = v4l2_m2m_request_queue, -+}; -+ -+static void rkvdec2_job_finish_no_pm(struct rkvdec2_ctx *ctx, -+ enum vb2_buffer_state result) -+{ -+ if (ctx->coded_fmt_desc->ops->done) { -+ struct vb2_v4l2_buffer *src_buf, *dst_buf; -+ -+ src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); -+ dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); -+ ctx->coded_fmt_desc->ops->done(ctx, src_buf, dst_buf, result); -+ } -+ -+ v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, -+ result); -+} -+ -+static void rkvdec2_job_finish(struct rkvdec2_ctx *ctx, -+ enum vb2_buffer_state result) -+{ -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ -+ pm_runtime_mark_last_busy(rkvdec->dev); -+ pm_runtime_put_autosuspend(rkvdec->dev); -+ rkvdec2_job_finish_no_pm(ctx, result); -+} -+ -+void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run) -+{ -+ struct media_request *src_req; -+ -+ memset(run, 0, sizeof(*run)); -+ -+ run->bufs.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); -+ run->bufs.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); -+ -+ /* Apply request(s) controls if needed. */ -+ src_req = run->bufs.src->vb2_buf.req_obj.req; -+ if (src_req) -+ v4l2_ctrl_request_setup(src_req, &ctx->ctrl_hdl); -+ -+ v4l2_m2m_buf_copy_metadata(run->bufs.src, run->bufs.dst, true); -+} -+ -+void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run) -+{ -+ struct media_request *src_req = run->bufs.src->vb2_buf.req_obj.req; -+ -+ if (src_req) -+ v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl); -+} -+ -+static void rkvdec2_device_run(void *priv) -+{ -+ struct rkvdec2_ctx *ctx = priv; -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ int ret; -+ -+ if (WARN_ON(!desc)) -+ return; -+ -+ ret = pm_runtime_resume_and_get(rkvdec->dev); -+ if (ret < 0) { -+ rkvdec2_job_finish_no_pm(ctx, VB2_BUF_STATE_ERROR); -+ return; -+ } -+ -+ ret = desc->ops->run(ctx); -+ if (ret) -+ rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR); -+} -+ -+static const struct v4l2_m2m_ops rkvdec2_m2m_ops = { -+ .device_run = rkvdec2_device_run, -+}; -+ -+static int rkvdec2_queue_init(void *priv, -+ struct vb2_queue *src_vq, -+ struct vb2_queue *dst_vq) -+{ -+ struct rkvdec2_ctx *ctx = priv; -+ struct rkvdec2_dev *rkvdec = ctx->dev; -+ int ret; -+ -+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ src_vq->drv_priv = ctx; -+ src_vq->ops = &rkvdec2_queue_ops; -+ src_vq->mem_ops = &vb2_dma_contig_memops; -+ -+ /* -+ * No CPU access on the queues, so no kernel mapping needed. -+ */ -+ src_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING; -+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ src_vq->lock = &rkvdec->vdev_lock; -+ src_vq->dev = rkvdec->v4l2_dev.dev; -+ src_vq->supports_requests = true; -+ src_vq->requires_requests = true; -+ -+ ret = vb2_queue_init(src_vq); -+ if (ret) -+ return ret; -+ -+ dst_vq->bidirectional = true; -+ dst_vq->mem_ops = &vb2_dma_contig_memops; -+ dst_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING; -+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; -+ dst_vq->drv_priv = ctx; -+ dst_vq->ops = &rkvdec2_queue_ops; -+ dst_vq->buf_struct_size = sizeof(struct rkvdec2_decoded_buffer); -+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; -+ dst_vq->lock = &rkvdec->vdev_lock; -+ dst_vq->dev = rkvdec->v4l2_dev.dev; -+ -+ return vb2_queue_init(dst_vq); -+} -+ -+static int rkvdec2_add_ctrls(struct rkvdec2_ctx *ctx, -+ const struct rkvdec2_ctrls *ctrls) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ctrls->num_ctrls; i++) { -+ const struct v4l2_ctrl_config *cfg = &ctrls->ctrls[i].cfg; -+ -+ v4l2_ctrl_new_custom(&ctx->ctrl_hdl, cfg, ctx); -+ if (ctx->ctrl_hdl.error) -+ return ctx->ctrl_hdl.error; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec2_init_ctrls(struct rkvdec2_ctx *ctx) -+{ -+ unsigned int i, nctrls = 0; -+ int ret; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) -+ nctrls += rkvdec2_coded_fmts[i].ctrls->num_ctrls; -+ -+ v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) { -+ ret = rkvdec2_add_ctrls(ctx, rkvdec2_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } -+ -+ ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -+ if (ret) -+ goto err_free_handler; -+ -+ ctx->fh.ctrl_handler = &ctx->ctrl_hdl; -+ return 0; -+ -+err_free_handler: -+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); -+ return ret; -+} -+ -+static int rkvdec2_open(struct file *filp) -+{ -+ struct rkvdec2_dev *rkvdec = video_drvdata(filp); -+ struct rkvdec2_ctx *ctx; -+ int ret; -+ -+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); -+ if (!ctx) -+ return -ENOMEM; -+ -+ ctx->dev = rkvdec; -+ rkvdec2_reset_coded_fmt(ctx); -+ rkvdec2_reset_decoded_fmt(ctx); -+ v4l2_fh_init(&ctx->fh, video_devdata(filp)); -+ -+ ret = rkvdec2_init_ctrls(ctx); -+ if (ret) -+ goto err_free_ctx; -+ -+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rkvdec->m2m_dev, ctx, -+ rkvdec2_queue_init); -+ if (IS_ERR(ctx->fh.m2m_ctx)) { -+ ret = PTR_ERR(ctx->fh.m2m_ctx); -+ goto err_cleanup_ctrls; -+ } -+ -+ filp->private_data = &ctx->fh; -+ v4l2_fh_add(&ctx->fh); -+ -+ return 0; -+ -+err_cleanup_ctrls: -+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); -+ -+err_free_ctx: -+ kfree(ctx); -+ return ret; -+} -+ -+static int rkvdec2_release(struct file *filp) -+{ -+ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(filp->private_data); -+ -+ v4l2_fh_del(&ctx->fh); -+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); -+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); -+ v4l2_fh_exit(&ctx->fh); -+ kfree(ctx); -+ -+ return 0; -+} -+ -+static const struct v4l2_file_operations rkvdec2_fops = { -+ .owner = THIS_MODULE, -+ .open = rkvdec2_open, -+ .release = rkvdec2_release, -+ .poll = v4l2_m2m_fop_poll, -+ .unlocked_ioctl = video_ioctl2, -+ .mmap = v4l2_m2m_fop_mmap, -+}; -+ -+static int rkvdec2_v4l2_init(struct rkvdec2_dev *rkvdec) -+{ -+ int ret; -+ -+ ret = v4l2_device_register(rkvdec->dev, &rkvdec->v4l2_dev); -+ if (ret) { -+ dev_err(rkvdec->dev, "Failed to register V4L2 device\n"); -+ return ret; -+ } -+ -+ rkvdec->m2m_dev = v4l2_m2m_init(&rkvdec2_m2m_ops); -+ if (IS_ERR(rkvdec->m2m_dev)) { -+ v4l2_err(&rkvdec->v4l2_dev, "Failed to init mem2mem device\n"); -+ ret = PTR_ERR(rkvdec->m2m_dev); -+ goto err_unregister_v4l2; -+ } -+ -+ rkvdec->mdev.dev = rkvdec->dev; -+ strscpy(rkvdec->mdev.model, "rkvdec2", sizeof(rkvdec->mdev.model)); -+ strscpy(rkvdec->mdev.bus_info, "platform:rkvdec2", -+ sizeof(rkvdec->mdev.bus_info)); -+ media_device_init(&rkvdec->mdev); -+ rkvdec->mdev.ops = &rkvdec2_media_ops; -+ rkvdec->v4l2_dev.mdev = &rkvdec->mdev; -+ -+ rkvdec->vdev.lock = &rkvdec->vdev_lock; -+ rkvdec->vdev.v4l2_dev = &rkvdec->v4l2_dev; -+ rkvdec->vdev.fops = &rkvdec2_fops; -+ rkvdec->vdev.release = video_device_release_empty; -+ rkvdec->vdev.vfl_dir = VFL_DIR_M2M; -+ rkvdec->vdev.device_caps = V4L2_CAP_STREAMING | -+ V4L2_CAP_VIDEO_M2M_MPLANE; -+ rkvdec->vdev.ioctl_ops = &rkvdec2_ioctl_ops; -+ video_set_drvdata(&rkvdec->vdev, rkvdec); -+ strscpy(rkvdec->vdev.name, "rkvdec2", sizeof(rkvdec->vdev.name)); -+ -+ ret = video_register_device(&rkvdec->vdev, VFL_TYPE_VIDEO, -1); -+ if (ret) { -+ v4l2_err(&rkvdec->v4l2_dev, "Failed to register video device\n"); -+ goto err_cleanup_mc; -+ } -+ -+ ret = v4l2_m2m_register_media_controller(rkvdec->m2m_dev, &rkvdec->vdev, -+ MEDIA_ENT_F_PROC_VIDEO_DECODER); -+ if (ret) { -+ v4l2_err(&rkvdec->v4l2_dev, -+ "Failed to initialize V4L2 M2M media controller\n"); -+ goto err_unregister_vdev; -+ } -+ -+ ret = media_device_register(&rkvdec->mdev); -+ if (ret) { -+ v4l2_err(&rkvdec->v4l2_dev, "Failed to register media device\n"); -+ goto err_unregister_mc; -+ } -+ -+ return 0; -+ -+err_unregister_mc: -+ v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev); -+ -+err_unregister_vdev: -+ video_unregister_device(&rkvdec->vdev); -+ -+err_cleanup_mc: -+ media_device_cleanup(&rkvdec->mdev); -+ v4l2_m2m_release(rkvdec->m2m_dev); -+ -+err_unregister_v4l2: -+ v4l2_device_unregister(&rkvdec->v4l2_dev); -+ return ret; -+} -+ -+static void rkvdec2_v4l2_cleanup(struct rkvdec2_dev *rkvdec) -+{ -+ media_device_unregister(&rkvdec->mdev); -+ v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev); -+ video_unregister_device(&rkvdec->vdev); -+ media_device_cleanup(&rkvdec->mdev); -+ v4l2_m2m_release(rkvdec->m2m_dev); -+ v4l2_device_unregister(&rkvdec->v4l2_dev); -+} -+ -+static irqreturn_t rkvdec2_irq_handler(int irq, void *priv) -+{ -+ struct rkvdec2_dev *rkvdec = priv; -+ enum vb2_buffer_state state; -+ u32 status; -+ -+ status = readl(rkvdec->regs + RKVDEC2_REG_STA_INT); -+ state = (status & STA_INT_DEC_RDY_STA) ? -+ VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -+ -+ /* Clear interrupt status */ -+ writel(0, rkvdec->regs + RKVDEC2_REG_STA_INT); -+ if (cancel_delayed_work(&rkvdec->watchdog_work)) { -+ struct rkvdec2_ctx *ctx; -+ -+ ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -+ rkvdec2_job_finish(ctx, state); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static void rkvdec2_watchdog_func(struct work_struct *work) -+{ -+ struct rkvdec2_dev *rkvdec = container_of(to_delayed_work(work), struct rkvdec2_dev, -+ watchdog_work); -+ struct rkvdec2_ctx *ctx; -+ -+ ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -+ if (ctx) { -+ dev_err(rkvdec->dev, "Frame processing timed out!\n"); -+ writel(RKVDEC2_REG_DEC_IRQ_DISABLE, rkvdec->regs + RKVDEC2_REG_IMPORTANT_EN); -+ writel(0, rkvdec->regs + RKVDEC2_REG_DEC_E); -+ rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR); -+ } -+} -+ -+static const struct of_device_id of_rkvdec2_match[] = { -+ { .compatible = "rockchip,rk3588-vdec" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_rkvdec2_match); -+ -+static const char * const rkvdec2_clk_names[] = { -+ "axi", -+ "ahb", -+ "core", -+ "cabac", -+ "hevc_cabac", -+}; -+ -+/* -+ * Some SoCs, like RK3588 have multiple identical vdpu34x cores, but the -+ * kernel is currently missing support for multi-core handling. Exposing -+ * separate devices for each core to userspace is bad, since that does -+ * not allow scheduling tasks properly (and creates ABI). With this workaround -+ * the driver will only probe for the first core and early exit for the other -+ * cores. Once the driver gains multi-core support, the same technique -+ * for detecting the main core can be used to cluster all cores together. -+ */ -+static int rkvdec2_disable_multicore(struct rkvdec2_dev *rkvdec) -+{ -+ const char *compatible; -+ struct device_node *node; -+ int ret; -+ -+ /* Intentionally ignores the fallback strings */ -+ ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible); -+ if (ret) -+ return ret; -+ -+ /* first compatible node found from the root node is considered the main core */ -+ node = of_find_compatible_node(NULL, NULL, compatible); -+ if (!node) -+ return -EINVAL; /* broken DT? */ -+ -+ if (rkvdec->dev->of_node != node) { -+ dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec2_probe(struct platform_device *pdev) -+{ -+ struct rkvdec2_dev *rkvdec; -+ unsigned int i; -+ int ret, irq; -+ -+ rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); -+ if (!rkvdec) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, rkvdec); -+ rkvdec->dev = &pdev->dev; -+ -+ ret = rkvdec2_disable_multicore(rkvdec); -+ if (ret) -+ return ret; -+ -+ mutex_init(&rkvdec->vdev_lock); -+ INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec2_watchdog_func); -+ -+ rkvdec->clocks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names), -+ sizeof(*rkvdec->clocks), GFP_KERNEL); -+ if (!rkvdec->clocks) -+ return -ENOMEM; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec2_clk_names); i++) -+ rkvdec->clocks[i].id = rkvdec2_clk_names[i]; -+ -+ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names), -+ rkvdec->clocks); -+ if (ret) -+ return ret; -+ -+ rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(rkvdec->regs)) -+ return PTR_ERR(rkvdec->regs); -+ -+ /* -+ * Without IOMMU support, keep DMA in the lower 32 bits. -+ */ -+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); -+ return ret; -+ } -+ -+ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq <= 0) -+ return -ENXIO; -+ -+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, -+ rkvdec2_irq_handler, IRQF_ONESHOT, -+ dev_name(&pdev->dev), rkvdec); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not request vdec2 IRQ\n"); -+ return ret; -+ } -+ -+ rkvdec->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); -+ if (!rkvdec->sram_pool) -+ dev_info(&pdev->dev, "No sram node, RCB will be stored in RAM\n"); -+ -+ pm_runtime_set_autosuspend_delay(&pdev->dev, 100); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_enable(&pdev->dev); -+ -+ ret = rkvdec2_v4l2_init(rkvdec); -+ if (ret) -+ goto err_disable_runtime_pm; -+ -+ return 0; -+ -+err_disable_runtime_pm: -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ -+ if (rkvdec->sram_pool) -+ gen_pool_destroy(rkvdec->sram_pool); -+ -+ return ret; -+} -+ -+static void rkvdec2_remove(struct platform_device *pdev) -+{ -+ struct rkvdec2_dev *rkvdec = platform_get_drvdata(pdev); -+ -+ cancel_delayed_work_sync(&rkvdec->watchdog_work); -+ -+ rkvdec2_v4l2_cleanup(rkvdec); -+ pm_runtime_disable(&pdev->dev); -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ -+ if (rkvdec->sram_pool) -+ gen_pool_destroy(rkvdec->sram_pool); -+} -+ -+#ifdef CONFIG_PM -+static int rkvdec2_runtime_resume(struct device *dev) -+{ -+ struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev); -+ -+ return clk_bulk_prepare_enable(ARRAY_SIZE(rkvdec2_clk_names), -+ rkvdec->clocks); -+} -+ -+static int rkvdec2_runtime_suspend(struct device *dev) -+{ -+ struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev); -+ -+ clk_bulk_disable_unprepare(ARRAY_SIZE(rkvdec2_clk_names), -+ rkvdec->clocks); -+ return 0; -+} -+#endif -+ -+static const struct dev_pm_ops rkvdec2_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+ SET_RUNTIME_PM_OPS(rkvdec2_runtime_suspend, rkvdec2_runtime_resume, NULL) -+}; -+ -+static struct platform_driver rkvdec2_driver = { -+ .probe = rkvdec2_probe, -+ .remove_new = rkvdec2_remove, -+ .driver = { -+ .name = "rkvdec2", -+ .of_match_table = of_rkvdec2_match, -+ .pm = &rkvdec2_pm_ops, -+ }, -+}; -+module_platform_driver(rkvdec2_driver); -+ -+MODULE_AUTHOR("Detlev Casanova "); -+MODULE_DESCRIPTION("Rockchip Video Decoder 2 driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/staging/media/rkvdec2/rkvdec2.h b/drivers/staging/media/rkvdec2/rkvdec2.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec2/rkvdec2.h -@@ -0,0 +1,130 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip Video Decoder 2 driver -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ * -+ * Based on rkvdec driver by Boris Brezillon -+ */ -+#ifndef RKVDEC_H_ -+#define RKVDEC_H_ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "rkvdec2-regs.h" -+ -+#define RKVDEC2_RCB_COUNT 10 -+ -+struct rkvdec2_ctx; -+ -+enum rkvdec2_alloc_type { -+ RKVDEC2_ALLOC_SRAM, -+ RKVDEC2_ALLOC_DMA, -+}; -+ -+struct rkvdec2_aux_buf { -+ void *cpu; -+ dma_addr_t dma; -+ size_t size; -+ enum rkvdec2_alloc_type type; -+}; -+ -+struct rkvdec2_ctrl_desc { -+ struct v4l2_ctrl_config cfg; -+}; -+ -+struct rkvdec2_ctrls { -+ const struct rkvdec2_ctrl_desc *ctrls; -+ unsigned int num_ctrls; -+}; -+ -+struct rkvdec2_run { -+ struct { -+ struct vb2_v4l2_buffer *src; -+ struct vb2_v4l2_buffer *dst; -+ } bufs; -+}; -+ -+struct rkvdec2_decoded_buffer { -+ /* Must be the first field in this struct. */ -+ struct v4l2_m2m_buffer base; -+}; -+ -+static inline struct rkvdec2_decoded_buffer * -+vb2_to_rkvdec2_decoded_buf(struct vb2_buffer *buf) -+{ -+ return container_of(buf, struct rkvdec2_decoded_buffer, -+ base.vb.vb2_buf); -+} -+ -+struct rkvdec2_coded_fmt_ops { -+ int (*adjust_fmt)(struct rkvdec2_ctx *ctx, -+ struct v4l2_format *f); -+ int (*start)(struct rkvdec2_ctx *ctx); -+ void (*stop)(struct rkvdec2_ctx *ctx); -+ int (*run)(struct rkvdec2_ctx *ctx); -+ void (*done)(struct rkvdec2_ctx *ctx, struct vb2_v4l2_buffer *src_buf, -+ struct vb2_v4l2_buffer *dst_buf, -+ enum vb2_buffer_state result); -+ int (*try_ctrl)(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl); -+}; -+ -+struct rkvdec2_coded_fmt_desc { -+ u32 fourcc; -+ struct v4l2_frmsize_stepwise frmsize; -+ const struct rkvdec2_ctrls *ctrls; -+ const struct rkvdec2_coded_fmt_ops *ops; -+ unsigned int num_decoded_fmts; -+ const u32 *decoded_fmts; -+ u32 subsystem_flags; -+}; -+ -+struct rkvdec2_dev { -+ struct v4l2_device v4l2_dev; -+ struct media_device mdev; -+ struct video_device vdev; -+ struct v4l2_m2m_dev *m2m_dev; -+ struct device *dev; -+ struct clk_bulk_data *clocks; -+ void __iomem *regs; -+ struct gen_pool *sram_pool; -+ struct mutex vdev_lock; /* serializes ioctls */ -+ struct delayed_work watchdog_work; -+}; -+ -+struct rkvdec2_ctx { -+ struct v4l2_fh fh; -+ struct v4l2_format coded_fmt; -+ struct v4l2_format decoded_fmt; -+ const struct rkvdec2_coded_fmt_desc *coded_fmt_desc; -+ struct v4l2_ctrl_handler ctrl_hdl; -+ struct rkvdec2_dev *dev; -+ struct rkvdec2_aux_buf rcb_bufs[RKVDEC2_RCB_COUNT]; -+ -+ u32 colmv_offset; -+ -+ void *priv; -+}; -+ -+static inline struct rkvdec2_ctx *fh_to_rkvdec2_ctx(struct v4l2_fh *fh) -+{ -+ return container_of(fh, struct rkvdec2_ctx, fh); -+} -+ -+void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run); -+void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run); -+ -+extern const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops; -+ -+#endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 20 Jun 2024 10:19:46 -0400 -Subject: arm64: dts: rockchip: Add rkvdec2 Video Decoder on rk3588(s) - -Add the rkvdec2 Video Decoder to the RK3588s devicetree. - -Signed-off-by: Detlev Casanova ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 ++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -3001,6 +3001,16 @@ system_sram2: sram@ff001000 { - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ vdec0_sram: rkvdec-sram@0 { -+ reg = <0x0 0x78000>; -+ pool; -+ }; -+ -+ vdec1_sram: rkvdec-sram@1 { -+ reg = <0x78000 0x77000>; -+ pool; -+ }; - }; - - pinctrl: pinctrl { -@@ -3070,6 +3080,44 @@ gpio4: gpio@fec50000 { - #interrupt-cells = <2>; - }; - }; -+ -+ vdec0: video-decoder@fdc38100 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc38100 0x0 0x500>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, -+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, -+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, -+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; -+ reset-names = "rst_axi", "rst_ahb", "rst_cabac", -+ "rst_core", "rst_hevc_cabac"; -+ power-domains = <&power RK3588_PD_RKVDEC0>; -+ sram = <&vdec0_sram>; -+ }; -+ -+ vdec1: video-decoder@fdc40100 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc40100 0x0 0x500>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, -+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, -+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, -+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; -+ reset-names = "rst_axi", "rst_ahb", "rst_cabac", -+ "rst_core", "rst_hevc_cabac"; -+ power-domains = <&power RK3588_PD_RKVDEC1>; -+ sram = <&vdec1_sram>; -+ }; - }; - - #include "rk3588s-pinctrl.dtsi" --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch deleted file mode 100644 index 13b5aecefc5b..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Fri, 21 Jun 2024 16:32:55 +0800 -Subject: media: v4l2-core: Initialize h264 frame_mbs_only_flag as 1 - ---- - drivers/media/v4l2-core/v4l2-ctrls-core.c | 13 ++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -111,6 +111,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, - struct v4l2_ctrl_vp9_frame *p_vp9_frame; - struct v4l2_ctrl_fwht_params *p_fwht_params; - struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; -+ struct v4l2_ctrl_h264_sps *p_h264_sps; - struct v4l2_ctrl_av1_sequence *p_av1_sequence; - void *p = ptr.p + idx * ctrl->elem_size; - -@@ -179,6 +180,18 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, - */ - memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix)); - break; -+ case V4L2_CTRL_TYPE_H264_SPS: -+ p_h264_sps = p; -+ /* -+ * Without V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY, -+ * frame_mbs_only_flag set to 0 will translate to a miniumum -+ * height of 32 (see H.264 specification 7-8). Some driver may -+ * have a minimum size lower then 32, which would fail -+ * validation with the SPS value. Set this flag, so that there -+ * is now doubling in the height, allowing a valid default. -+ */ -+ p_h264_sps->flags = V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY; -+ break; - } - } - --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch deleted file mode 100644 index 3112a0d954df..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch +++ /dev/null @@ -1,3921 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Wed, 7 Aug 2024 11:33:46 +0000 -Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller - ---- - arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi | 42 + - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 57 + - drivers/media/platform/Kconfig | 1 + - drivers/media/platform/Makefile | 1 + - drivers/media/platform/synopsys/Kconfig | 3 + - drivers/media/platform/synopsys/Makefile | 2 + - drivers/media/platform/synopsys/hdmirx/Kconfig | 27 + - drivers/media/platform/synopsys/hdmirx/Makefile | 4 + - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2763 ++++++++++ - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h | 394 ++ - drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c | 285 + - drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h | 44 + - 12 files changed, 3623 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi -@@ -169,6 +169,48 @@ hdmim0_tx1_sda: hdmim0-tx1-sda { - /* hdmim0_tx1_sda */ - <2 RK_PB4 4 &pcfg_pull_none>; - }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx: hdmim1-rx { -+ rockchip,pins = -+ /* hdmim1_rx_cec */ -+ <3 RK_PD1 5 &pcfg_pull_none>, -+ /* hdmim1_rx_scl */ -+ <3 RK_PD2 5 &pcfg_pull_none_smt>, -+ /* hdmim1_rx_sda */ -+ <3 RK_PD3 5 &pcfg_pull_none_smt>, -+ /* hdmim1_rx_hpdin */ -+ <3 RK_PD4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_cec: hdmim1-rx-cec { -+ rockchip,pins = -+ /* hdmim1_rx_cec */ -+ <3 RK_PD1 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_hpdin: hdmim1-rx-hpdin { -+ rockchip,pins = -+ /* hdmim1_rx_hpdin */ -+ <3 RK_PD4 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_scl: hdmim1-rx-scl { -+ rockchip,pins = -+ /* hdmim1_rx_scl */ -+ <3 RK_PD2 5 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ hdmim1_rx_sda: hdmim1-rx-sda { -+ rockchip,pins = -+ /* hdmim1_rx_sda */ -+ <3 RK_PD3 5 &pcfg_pull_none>; -+ }; -+ - }; - - i2c0 { -diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -7,6 +7,29 @@ - #include "rk3588-pinctrl.dtsi" - - / { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ /* -+ * The 4k HDMI capture controller works only with 32bit -+ * phys addresses and doesn't support IOMMU. HDMI RX CMA -+ * must be reserved below 4GB. -+ * The size of 160MB was determined as follows: -+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB -+ * To ensure sufficient support for practical use-cases, -+ * we doubled the 66MB value. -+ */ -+ hdmi_receiver_cma: hdmi-receiver-cma { -+ compatible = "shared-dma-pool"; -+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; -+ size = <0x0 (160 * 0x100000)>; /* 160MiB */ -+ no-map; -+ status = "disabled"; -+ }; -+ }; -+ - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; -@@ -27,6 +50,40 @@ usb_host1_xhci: usb@fc400000 { - status = "disabled"; - }; - -+ hdmi_receiver: hdmi_receiver@fdee0000 { -+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; -+ reg = <0x0 0xfdee0000 0x0 0x6000>; -+ power-domains = <&power RK3588_PD_VO1>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo1-grf = <&vo1_grf>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "cec", "hdmi", "dma"; -+ clocks = <&cru ACLK_HDMIRX>, -+ <&cru CLK_HDMIRX_AUD>, -+ <&cru CLK_CR_PARA>, -+ <&cru PCLK_HDMIRX>, -+ <&cru CLK_HDMIRX_REF>, -+ <&cru PCLK_S_HDMIRX>, -+ <&cru HCLK_VO1>; -+ clock-names = "aclk", -+ "audio", -+ "cr_para", -+ "pclk", -+ "ref", -+ "hclk_s_hdmirx", -+ "hclk_vo1"; -+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, -+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; -+ reset-names = "axi", "apb", "ref", "biu"; -+ memory-region = <&hdmi_receiver_cma>; -+ pinctrl-0 = <&hdmim1_rx>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ -+ - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; -diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/Kconfig -+++ b/drivers/media/platform/Kconfig -@@ -83,6 +83,7 @@ source "drivers/media/platform/rockchip/Kconfig" - source "drivers/media/platform/samsung/Kconfig" - source "drivers/media/platform/st/Kconfig" - source "drivers/media/platform/sunxi/Kconfig" -+source "drivers/media/platform/synopsys/Kconfig" - source "drivers/media/platform/ti/Kconfig" - source "drivers/media/platform/verisilicon/Kconfig" - source "drivers/media/platform/via/Kconfig" -diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/Makefile -+++ b/drivers/media/platform/Makefile -@@ -26,6 +26,7 @@ obj-y += rockchip/ - obj-y += samsung/ - obj-y += st/ - obj-y += sunxi/ -+obj-y += synopsys/ - obj-y += ti/ - obj-y += verisilicon/ - obj-y += via/ -diff --git a/drivers/media/platform/synopsys/Kconfig b/drivers/media/platform/synopsys/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/Kconfig -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+source "drivers/media/platform/synopsys/hdmirx/Kconfig" -diff --git a/drivers/media/platform/synopsys/Makefile b/drivers/media/platform/synopsys/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-y += hdmirx/ -diff --git a/drivers/media/platform/synopsys/hdmirx/Kconfig b/drivers/media/platform/synopsys/hdmirx/Kconfig -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/Kconfig -@@ -0,0 +1,27 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+config VIDEO_SYNOPSYS_HDMIRX -+ tristate "Synopsys DesignWare HDMI Receiver driver" -+ depends on VIDEO_DEV -+ depends on ARCH_ROCKCHIP -+ select MEDIA_CONTROLLER -+ select VIDEO_V4L2_SUBDEV_API -+ select VIDEOBUF2_DMA_CONTIG -+ select CEC_CORE -+ select CEC_NOTIFIER -+ select HDMI -+ help -+ Support for Synopsys HDMI HDMI RX Controller. -+ This driver supports HDMI 2.0 version. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called synopsys_hdmirx. -+ -+config HDMIRX_LOAD_DEFAULT_EDID -+ bool "Load default EDID" -+ depends on VIDEO_SYNOPSYS_HDMIRX -+ default "y" -+ help -+ Preload the default EDID (Extended Display Identification Data). -+ EDID contains information about the capabilities of the display, -+ such as supported resolutions, refresh rates, and audio formats. -diff --git a/drivers/media/platform/synopsys/hdmirx/Makefile b/drivers/media/platform/synopsys/hdmirx/Makefile -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+synopsys-hdmirx-objs := snps_hdmirx.o snps_hdmirx_cec.o -+ -+obj-$(CONFIG_VIDEO_SYNOPSYS_HDMIRX) += synopsys-hdmirx.o -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -0,0 +1,2763 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Author: Shreeya Patel -+ * -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * Author: Dingxian Wen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "snps_hdmirx.h" -+#include "snps_hdmirx_cec.h" -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "debug level (0-3)"); -+ -+#define EDID_NUM_BLOCKS_MAX 2 -+#define EDID_BLOCK_SIZE 128 -+#define HDMIRX_STORED_BIT_WIDTH 8 -+#define IREF_CLK_FREQ_HZ 428571429 -+#define MEMORY_ALIGN_ROUND_UP_BYTES 64 -+#define HDMIRX_PLANE_Y 0 -+#define HDMIRX_PLANE_CBCR 1 -+#define RK_IRQ_HDMIRX_HDMI 210 -+#define FILTER_FRAME_CNT 6 -+#define RK_SIP_FIQ_CTRL 0x82000024 -+#define SIP_WDT_CFG 0x82000026 -+#define DETECTION_THRESHOLD 7 -+ -+/* fiq control sub func */ -+enum { -+ RK_SIP_FIQ_CTRL_FIQ_EN = 1, -+ RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_SIP_FIQ_CTRL_SET_AFF -+}; -+ -+/* SIP_WDT_CONFIG call types */ -+enum { -+ WDT_START = 0, -+ WDT_STOP = 1, -+ WDT_PING = 2, -+}; -+ -+enum hdmirx_pix_fmt { -+ HDMIRX_RGB888 = 0, -+ HDMIRX_YUV422 = 1, -+ HDMIRX_YUV444 = 2, -+ HDMIRX_YUV420 = 3, -+}; -+ -+enum ddr_store_fmt { -+ STORE_RGB888 = 0, -+ STORE_RGBA_ARGB, -+ STORE_YUV420_8BIT, -+ STORE_YUV420_10BIT, -+ STORE_YUV422_8BIT, -+ STORE_YUV422_10BIT, -+ STORE_YUV444_8BIT, -+ STORE_YUV420_16BIT = 8, -+ STORE_YUV422_16BIT = 9, -+}; -+ -+enum hdmirx_reg_attr { -+ HDMIRX_ATTR_RW = 0, -+ HDMIRX_ATTR_RO = 1, -+ HDMIRX_ATTR_WO = 2, -+ HDMIRX_ATTR_RE = 3, -+}; -+ -+enum { -+ HDMIRX_RST_A, -+ HDMIRX_RST_P, -+ HDMIRX_RST_REF, -+ HDMIRX_RST_BIU, -+ HDMIRX_NUM_RST, -+}; -+ -+static const char * const pix_fmt_str[] = { -+ "RGB888", -+ "YUV422", -+ "YUV444", -+ "YUV420", -+}; -+ -+struct hdmirx_buffer { -+ struct vb2_v4l2_buffer vb; -+ struct list_head queue; -+ u32 buff_addr[VIDEO_MAX_PLANES]; -+}; -+ -+struct hdmirx_stream { -+ struct snps_hdmirx_dev *hdmirx_dev; -+ struct video_device vdev; -+ struct vb2_queue buf_queue; -+ struct list_head buf_head; -+ struct hdmirx_buffer *curr_buf; -+ struct hdmirx_buffer *next_buf; -+ struct v4l2_pix_format_mplane pixm; -+ const struct v4l2_format_info *out_finfo; -+ struct mutex vlock; /* to lock resources associated with video buffer and video device */ -+ spinlock_t vbq_lock; /* to lock video buffer queue */ -+ bool stopping; -+ wait_queue_head_t wq_stopped; -+ u32 frame_idx; -+ u32 line_flag_int_cnt; -+ u32 irq_stat; -+}; -+ -+struct snps_hdmirx_dev { -+ struct device *dev; -+ struct device *codec_dev; -+ struct hdmirx_stream stream; -+ struct v4l2_device v4l2_dev; -+ struct v4l2_ctrl_handler hdl; -+ struct v4l2_ctrl *detect_tx_5v_ctrl; -+ struct v4l2_ctrl *rgb_range; -+ struct v4l2_dv_timings timings; -+ struct gpio_desc *detect_5v_gpio; -+ struct work_struct work_wdt_config; -+ struct delayed_work delayed_work_hotplug; -+ struct delayed_work delayed_work_res_change; -+ struct delayed_work delayed_work_heartbeat; -+ struct cec_notifier *cec_notifier; -+ struct hdmirx_cec *cec; -+ struct mutex stream_lock; /* to lock video stream capture */ -+ struct mutex work_lock; /* to lock the critical section of hotplug event */ -+ struct reset_control_bulk_data resets[HDMIRX_NUM_RST]; -+ struct clk_bulk_data *clks; -+ struct regmap *grf; -+ struct regmap *vo1_grf; -+ struct completion cr_write_done; -+ struct completion timer_base_lock; -+ struct completion avi_pkt_rcv; -+ enum hdmirx_pix_fmt pix_fmt; -+ void __iomem *regs; -+ int hdmi_irq; -+ int dma_irq; -+ int det_irq; -+ bool hpd_trigger_level; -+ bool tmds_clk_ratio; -+ bool is_dvi_mode; -+ bool got_timing; -+ u32 num_clks; -+ u32 edid_blocks_written; -+ u32 cur_vic; -+ u32 cur_fmt_fourcc; -+ u32 color_depth; -+ u8 edid[EDID_BLOCK_SIZE * 2]; -+ hdmi_codec_plugged_cb plugged_cb; -+ spinlock_t rst_lock; /* to lock register access */ -+}; -+ -+static u8 edid_init_data_340M[] = { -+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00, -+ 0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78, -+ 0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23, -+ 0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40, -+ 0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0, -+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, -+ 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, -+ 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, -+ 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, -+ 0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00, -+ 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52, -+ 0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20, -+ 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD, -+ 0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A, -+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7, -+ -+ 0x02, 0x03, 0x2F, 0xD1, 0x51, 0x07, 0x16, 0x14, -+ 0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F, -+ 0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09, -+ 0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03, -+ 0x0C, 0x00, 0x30, 0x00, 0x10, 0x44, 0xE3, 0x05, -+ 0x03, 0x01, 0xE4, 0x0F, 0x00, 0x80, 0x01, 0x02, -+ 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, -+ 0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, -+ 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, -+}; -+ -+static const struct v4l2_dv_timings cea640x480 = V4L2_DV_BT_CEA_640X480P59_94; -+ -+static const struct v4l2_dv_timings_cap hdmirx_timings_cap = { -+ .type = V4L2_DV_BT_656_1120, -+ .reserved = { 0 }, -+ V4L2_INIT_BT_TIMINGS(640, 4096, /* min/max width */ -+ 480, 2160, /* min/max height */ -+ 20000000, 600000000, /* min/max pixelclock */ -+ /* standards */ -+ V4L2_DV_BT_STD_CEA861, -+ /* capabilities */ -+ V4L2_DV_BT_CAP_PROGRESSIVE | -+ V4L2_DV_BT_CAP_INTERLACED) -+}; -+ -+static void hdmirx_writel(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val) -+{ -+ unsigned long lock_flags = 0; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ writel(val, hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static u32 hdmirx_readl(struct snps_hdmirx_dev *hdmirx_dev, int reg) -+{ -+ unsigned long lock_flags = 0; -+ u32 val; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ val = readl(hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+ return val; -+} -+ -+static void hdmirx_reset_dma(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ unsigned long lock_flags = 0; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ reset_control_reset(hdmirx_dev->resets[0].rstc); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static void hdmirx_update_bits(struct snps_hdmirx_dev *hdmirx_dev, int reg, -+ u32 mask, u32 data) -+{ -+ unsigned long lock_flags = 0; -+ u32 val; -+ -+ spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags); -+ val = readl(hdmirx_dev->regs + reg) & ~mask; -+ val |= (data & mask); -+ writel(val, hdmirx_dev->regs + reg); -+ spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags); -+} -+ -+static int hdmirx_subscribe_event(struct v4l2_fh *fh, -+ const struct v4l2_event_subscription *sub) -+{ -+ switch (sub->type) { -+ case V4L2_EVENT_SOURCE_CHANGE: -+ if (fh->vdev->vfl_dir == VFL_DIR_RX) -+ return v4l2_src_change_event_subscribe(fh, sub); -+ break; -+ case V4L2_EVENT_CTRL: -+ return v4l2_ctrl_subscribe_event(fh, sub); -+ default: -+ break; -+ } -+ -+ return -EINVAL; -+} -+ -+static bool tx_5v_power_present(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ bool ret; -+ int val, i, cnt; -+ -+ cnt = 0; -+ for (i = 0; i < 10; i++) { -+ usleep_range(1000, 1100); -+ val = gpiod_get_value(hdmirx_dev->detect_5v_gpio); -+ if (val > 0) -+ cnt++; -+ if (cnt >= DETECTION_THRESHOLD) -+ break; -+ } -+ -+ ret = (cnt >= DETECTION_THRESHOLD) ? true : false; -+ v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static bool signal_not_lock(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ u32 mu_status, dma_st10, cmu_st; -+ -+ mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS); -+ dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10); -+ cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS); -+ -+ if ((mu_status & TMDSVALID_STABLE_ST) && -+ (dma_st10 & HDMIRX_LOCK) && -+ (cmu_st & TMDSQPCLK_LOCKED_ST)) -+ return false; -+ -+ return true; -+} -+ -+static void hdmirx_get_colordepth(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val, color_depth_reg; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3; -+ -+ switch (color_depth_reg) { -+ case 0x4: -+ hdmirx_dev->color_depth = 24; -+ break; -+ case 0x5: -+ hdmirx_dev->color_depth = 30; -+ break; -+ case 0x6: -+ hdmirx_dev->color_depth = 36; -+ break; -+ case 0x7: -+ hdmirx_dev->color_depth = 48; -+ break; -+ default: -+ hdmirx_dev->color_depth = 24; -+ break; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n", -+ __func__, hdmirx_dev->color_depth, color_depth_reg); -+} -+ -+static void hdmirx_get_pix_fmt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK; -+ -+ switch (hdmirx_dev->pix_fmt) { -+ case HDMIRX_RGB888: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ break; -+ case HDMIRX_YUV422: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16; -+ break; -+ case HDMIRX_YUV444: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24; -+ break; -+ case HDMIRX_YUV420: -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12; -+ break; -+ default: -+ v4l2_err(v4l2_dev, -+ "%s: err pix_fmt: %d, set RGB888 as default\n", -+ __func__, hdmirx_dev->pix_fmt); -+ hdmirx_dev->pix_fmt = HDMIRX_RGB888; -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ break; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__, -+ pix_fmt_str[hdmirx_dev->pix_fmt]); -+} -+ -+static void hdmirx_get_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_bt_timings *bt, bool from_dma) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 hact, vact, htotal, vtotal, fps; -+ u32 hfp, hs, hbp, vfp, vs, vbp; -+ u32 val; -+ -+ if (from_dma) { -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS2); -+ hact = (val >> 16) & 0xffff; -+ vact = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS3); -+ htotal = (val >> 16) & 0xffff; -+ vtotal = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS4); -+ hs = (val >> 16) & 0xffff; -+ vs = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS5); -+ hbp = (val >> 16) & 0xffff; -+ vbp = val & 0xffff; -+ hfp = htotal - hact - hs - hbp; -+ vfp = vtotal - vact - vs - vbp; -+ } else { -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS1); -+ hs = (val >> 16) & 0xffff; -+ hfp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS2); -+ hbp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS3); -+ htotal = (val >> 16) & 0xffff; -+ hact = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS4); -+ vs = (val >> 16) & 0xffff; -+ vfp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS5); -+ vbp = val & 0xffff; -+ val = hdmirx_readl(hdmirx_dev, VMON_STATUS6); -+ vtotal = (val >> 16) & 0xffff; -+ vact = val & 0xffff; -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ hact *= 2; -+ } -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ htotal *= 2; -+ fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal); -+ if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) -+ fps *= 2; -+ bt->width = hact; -+ bt->height = vact; -+ bt->hfrontporch = hfp; -+ bt->hsync = hs; -+ bt->hbackporch = hbp; -+ bt->vfrontporch = vfp; -+ bt->vsync = vs; -+ bt->vbackporch = vbp; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl"); -+ v4l2_dbg(1, debug, v4l2_dev, "act:%ux%u, total:%ux%u, fps:%u, pixclk:%llu\n", -+ bt->width, bt->height, htotal, vtotal, fps, bt->pixelclock); -+ -+ v4l2_dbg(2, debug, v4l2_dev, "hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n", -+ bt->hfrontporch, bt->hsync, bt->hbackporch, -+ bt->vfrontporch, bt->vsync, bt->vbackporch); -+} -+ -+static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt) -+{ -+ if (bt->width < 100 || bt->width > 5000 || -+ bt->height < 100 || bt->height > 5000) -+ return false; -+ -+ if (!bt->hsync || bt->hsync > 200 || -+ !bt->vsync || bt->vsync > 100) -+ return false; -+ -+ if (!bt->hbackporch || bt->hbackporch > 2000 || -+ !bt->vbackporch || bt->vbackporch > 2000) -+ return false; -+ -+ if (!bt->hfrontporch || bt->hfrontporch > 2000 || -+ !bt->vfrontporch || bt->vfrontporch > 2000) -+ return false; -+ -+ return true; -+} -+ -+static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ union hdmi_infoframe frame = {}; -+ int err, i, b, itr = 0; -+ u8 aviif[3 + 7 * 4]; -+ u32 val; -+ -+ aviif[itr++] = HDMI_INFOFRAME_TYPE_AVI; -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1); -+ aviif[itr++] = val & 0xff; -+ aviif[itr++] = (val >> 8) & 0xff; -+ -+ for (i = 0; i < 7; i++) { -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0 + 4 * i); -+ -+ for (b = 0; b < 4; b++) -+ aviif[itr++] = (val >> (8 * b)) & 0xff; -+ } -+ -+ err = hdmi_infoframe_unpack(&frame, aviif, sizeof(aviif)); -+ if (err) { -+ v4l2_err(v4l2_dev, "failed to unpack AVI infoframe\n"); -+ return; -+ } -+ -+ v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range); -+} -+ -+/* -+ * When querying DV timings during preview, if the DMA's timing is stable, -+ * we retrieve the timings directly from the DMA. However, if the current -+ * resolution is negative, obtaining the timing from CTRL may require a -+ * change in the sync polarity, potentially leading to DMA errors. -+ */ -+static int hdmirx_get_detected_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_dv_timings *timings, -+ bool from_dma) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_bt_timings *bt = &timings->bt; -+ u32 field_type, color_depth, deframer_st; -+ u32 val, tmdsqpclk_freq, pix_clk; -+ u64 tmp_data, tmds_clk; -+ -+ memset(timings, 0, sizeof(struct v4l2_dv_timings)); -+ timings->type = V4L2_DV_BT_656_1120; -+ -+ val = hdmirx_readl(hdmirx_dev, DMA_STATUS11); -+ field_type = (val & HDMIRX_TYPE_MASK) >> 7; -+ hdmirx_get_pix_fmt(hdmirx_dev); -+ bt->interlaced = field_type & BIT(0) ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; -+ val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4); -+ hdmirx_dev->cur_vic = val | VIC_VAL_MASK; -+ hdmirx_get_colordepth(hdmirx_dev); -+ color_depth = hdmirx_dev->color_depth; -+ deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS); -+ hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true; -+ tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ); -+ tmds_clk = tmdsqpclk_freq * 4 * 1000; -+ tmp_data = tmds_clk * 24; -+ do_div(tmp_data, color_depth); -+ pix_clk = tmp_data; -+ bt->pixelclock = pix_clk; -+ -+ hdmirx_get_avi_infoframe(hdmirx_dev); -+ -+ hdmirx_get_timings(hdmirx_dev, bt, from_dma); -+ if (bt->interlaced == V4L2_DV_INTERLACED) { -+ bt->height *= 2; -+ bt->il_vsync = bt->vsync + 1; -+ } -+ -+ v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu\n", tmds_clk); -+ v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n", -+ bt->interlaced, hdmirx_dev->pix_fmt, -+ hdmirx_dev->cur_vic, hdmirx_dev->color_depth, -+ hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi"); -+ v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st); -+ -+ if (!hdmirx_check_timing_valid(bt)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static bool port_no_link(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ return !tx_5v_power_present(hdmirx_dev); -+} -+ -+static int hdmirx_query_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ if (port_no_link(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: port has no link\n", __func__); -+ return -ENOLINK; -+ } -+ -+ if (signal_not_lock(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: signal is not locked\n", __func__); -+ return -ENOLCK; -+ } -+ -+ ret = hdmirx_get_detected_timings(hdmirx_dev, timings, true); -+ if (ret) -+ return ret; -+ -+ if (debug) -+ v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name, -+ "query_dv_timings: ", timings, false); -+ -+ if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__); -+ return -ERANGE; -+ } -+ -+ return 0; -+} -+ -+static void hdmirx_hpd_ctrl(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n", -+ __func__, en ? "en" : "dis", -+ hdmirx_dev->hpd_trigger_level); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW); -+ en = hdmirx_dev->hpd_trigger_level ? en : !en; -+ hdmirx_writel(hdmirx_dev, CORE_CONFIG, en); -+} -+ -+static int hdmirx_write_edid(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_edid *edid, bool hpd_up) -+{ -+ u32 edid_len = edid->blocks * EDID_BLOCK_SIZE; -+ char data[300]; -+ u32 i; -+ -+ memset(edid->reserved, 0, sizeof(edid->reserved)); -+ if (edid->pad) -+ return -EINVAL; -+ -+ if (edid->start_block) -+ return -EINVAL; -+ -+ if (edid->blocks > EDID_NUM_BLOCKS_MAX) { -+ edid->blocks = EDID_NUM_BLOCKS_MAX; -+ return -E2BIG; -+ } -+ -+ if (!edid->blocks) { -+ hdmirx_dev->edid_blocks_written = 0; -+ return 0; -+ } -+ -+ cec_s_phys_addr_from_edid(hdmirx_dev->cec->adap, -+ (const struct edid *)edid->edid); -+ -+ memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid)); -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | -+ EDID_WRITE_EN_MASK | -+ EDID_SLAVE_ADDR_MASK, -+ EDID_READ_EN(0) | -+ EDID_WRITE_EN(1) | -+ EDID_SLAVE_ADDR(0x50)); -+ for (i = 0; i < edid_len; i++) -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid->edid[i]); -+ -+ /* read out for debug */ -+ if (debug >= 2) { -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | -+ EDID_WRITE_EN_MASK, -+ EDID_READ_EN(1) | -+ EDID_WRITE_EN(0)); -+ edid_len = edid_len > sizeof(data) ? sizeof(data) : edid_len; -+ memset(data, 0, sizeof(data)); -+ for (i = 0; i < edid_len; i++) -+ data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14); -+ -+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data, -+ edid_len, false); -+ } -+ -+ /* -+ * You must set EDID_READ_EN & EDID_WRITE_EN bit to 0, -+ * when the read/write edid operation is completed.Otherwise, it -+ * will affect the reading and writing of other registers -+ */ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11, -+ EDID_READ_EN_MASK | EDID_WRITE_EN_MASK, -+ EDID_READ_EN(0) | EDID_WRITE_EN(0)); -+ -+ hdmirx_dev->edid_blocks_written = edid->blocks; -+ memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE); -+ if (hpd_up) { -+ if (tx_5v_power_present(hdmirx_dev)) { -+ /* Add 100ms delay after updating the EDID as per HDMI specs */ -+ msleep(100); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ } -+ } -+ -+ return 0; -+} -+ -+/* -+ * Before clearing interrupt, we need to read the interrupt status. -+ */ -+static inline void hdmirx_clear_interrupt(struct snps_hdmirx_dev *hdmirx_dev, -+ u32 reg, u32 val) -+{ -+ /* (interrupt status register) = (interrupt clear register) - 0x8 */ -+ hdmirx_readl(hdmirx_dev, reg - 0x8); -+ hdmirx_writel(hdmirx_dev, reg, val); -+} -+ -+static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: %sable\n", -+ __func__, en ? "en" : "dis"); -+ -+ /* Note: In DVI mode, it needs to be written twice to take effect. */ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ -+ if (en) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG, -+ TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG); -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG); -+ hdmirx_update_bits(hdmirx_dev, AVPUNIT_0_INT_MASK_N, -+ CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ, -+ CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ); -+ } else { -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0); -+ } -+} -+ -+static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct arm_smccc_res res; -+ -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0); -+ hdmirx_interrupts_setup(hdmirx_dev, false); -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ hdmirx_reset_dma(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET | -+ PHY_PDDQ, HDMI_DISABLE); -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0); -+ cancel_delayed_work(&hdmirx_dev->delayed_work_res_change); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); -+ flush_work(&hdmirx_dev->work_wdt_config); -+ arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct arm_smccc_res res; -+ int ret; -+ -+ disable_irq(hdmirx_dev->hdmi_irq); -+ disable_irq(hdmirx_dev->dma_irq); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ if (tx_5v_power_present(hdmirx_dev)) -+ hdmirx_plugout(hdmirx_dev); -+ ret = hdmirx_write_edid(hdmirx_dev, edid, false); -+ if (ret) -+ return ret; -+ -+ enable_irq(hdmirx_dev->hdmi_irq); -+ enable_irq(hdmirx_dev->dma_irq); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(500)); -+ return 0; -+} -+ -+static int hdmirx_get_edid(struct file *file, void *fh, struct v4l2_edid *edid) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ memset(edid->reserved, 0, sizeof(edid->reserved)); -+ -+ if (edid->pad) -+ return -EINVAL; -+ -+ if (!edid->start_block && !edid->blocks) { -+ edid->blocks = hdmirx_dev->edid_blocks_written; -+ return 0; -+ } -+ -+ if (!hdmirx_dev->edid_blocks_written) -+ return -ENODATA; -+ -+ if (edid->start_block >= hdmirx_dev->edid_blocks_written || !edid->blocks) -+ return -EINVAL; -+ -+ if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written) -+ edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block; -+ -+ memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE); -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: read EDID:\n", __func__); -+ if (debug > 0) -+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, -+ edid->edid, edid->blocks * EDID_BLOCK_SIZE, false); -+ -+ return 0; -+} -+ -+static int hdmirx_g_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *parm) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_fract fps; -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) -+ return -EINVAL; -+ -+ fps = v4l2_calc_timeperframe(&hdmirx_dev->timings); -+ parm->parm.capture.timeperframe.numerator = fps.numerator; -+ parm->parm.capture.timeperframe.denominator = fps.denominator; -+ -+ return 0; -+} -+ -+static int hdmirx_dv_timings_cap(struct file *file, void *fh, -+ struct v4l2_dv_timings_cap *cap) -+{ -+ *cap = hdmirx_timings_cap; -+ return 0; -+} -+ -+static int hdmirx_enum_dv_timings(struct file *file, void *_fh, -+ struct v4l2_enum_dv_timings *timings) -+{ -+ return v4l2_enum_dv_timings_cap(timings, &hdmirx_timings_cap, NULL, NULL); -+} -+ -+static void hdmirx_scdc_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, I2C_SLAVE_CONFIG1, -+ I2C_SDA_OUT_HOLD_VALUE_QST_MASK | -+ I2C_SDA_IN_HOLD_VALUE_QST_MASK, -+ I2C_SDA_OUT_HOLD_VALUE_QST(0x80) | -+ I2C_SDA_IN_HOLD_VALUE_QST(0x15)); -+ hdmirx_update_bits(hdmirx_dev, SCDC_REGBANK_CONFIG0, -+ SCDC_SINKVERSION_QST_MASK, -+ SCDC_SINKVERSION_QST(1)); -+} -+ -+static int wait_reg_bit_status(struct snps_hdmirx_dev *hdmirx_dev, u32 reg, -+ u32 bit_mask, u32 expect_val, bool is_grf, -+ u32 ms) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 i, val; -+ -+ for (i = 0; i < ms; i++) { -+ if (is_grf) -+ regmap_read(hdmirx_dev->grf, reg, &val); -+ else -+ val = hdmirx_readl(hdmirx_dev, reg); -+ -+ if ((val & bit_mask) == expect_val) { -+ v4l2_dbg(2, debug, v4l2_dev, -+ "%s: i:%d, time: %dms\n", __func__, i, ms); -+ break; -+ } -+ usleep_range(1000, 1010); -+ } -+ -+ if (i == ms) -+ return -1; -+ -+ return 0; -+} -+ -+static int hdmirx_phy_register_write(struct snps_hdmirx_dev *hdmirx_dev, -+ u32 phy_reg, u32 val) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ reinit_completion(&hdmirx_dev->cr_write_done); -+ /* clear irq status */ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ /* en irq */ -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ PHYCREG_CR_WRITE_DONE, PHYCREG_CR_WRITE_DONE); -+ /* write phy reg addr */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg); -+ /* write phy reg val */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val); -+ /* config write enable */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->cr_write_done, -+ msecs_to_jiffies(20))) { -+ dev_err(dev, "%s wait cr write done failed\n", __func__); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static void hdmirx_tmds_clk_ratio_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 val; -+ -+ val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1); -+ v4l2_dbg(3, debug, v4l2_dev, "%s: scdc_regbank_st:%#x\n", __func__, val); -+ hdmirx_dev->tmds_clk_ratio = (val & SCDC_TMDSBITCLKRATIO) > 0; -+ -+ if (hdmirx_dev->tmds_clk_ratio) { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX greater than 3.4Gbps\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, -+ TMDS_CLOCK_RATIO, TMDS_CLOCK_RATIO); -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: HDMITX less than 3.4Gbps\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, -+ TMDS_CLOCK_RATIO, 0); -+ } -+} -+ -+static void hdmirx_phy_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, SCDC_INT_MASK_N, SCDCTMDSCCFG_CHG, -+ SCDCTMDSCCFG_CHG); -+ /* cr_para_clk 24M */ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0)); -+ /* rx data width 40bit valid */ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET); -+ usleep_range(100, 110); -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0); -+ usleep_range(100, 110); -+ /* select cr para interface */ -+ hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3); -+ -+ if (wait_reg_bit_status(hdmirx_dev, SYS_GRF_SOC_STATUS1, -+ HDMIRXPHY_SRAM_INIT_DONE, -+ HDMIRXPHY_SRAM_INIT_DONE, true, 10)) -+ dev_err(dev, "%s: phy SRAM init failed\n", __func__); -+ -+ regmap_write(hdmirx_dev->grf, SYS_GRF_SOC_CON1, -+ (HDMIRXPHY_SRAM_EXT_LD_DONE << 16) | -+ HDMIRXPHY_SRAM_EXT_LD_DONE); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 1); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0); -+ -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG, -+ CDR_SETTING_BOUNDARY_3_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG, -+ CDR_SETTING_BOUNDARY_4_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG, -+ CDR_SETTING_BOUNDARY_5_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG, -+ CDR_SETTING_BOUNDARY_6_DEFAULT); -+ hdmirx_phy_register_write(hdmirx_dev, -+ HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG, -+ CDR_SETTING_BOUNDARY_7_DEFAULT); -+ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0); -+ if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10)) -+ dev_err(dev, "%s: wait pddq ack failed\n", __func__); -+ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0); -+ if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, HDMI_DISABLE_ACK, 0, -+ false, 50)) -+ dev_err(dev, "%s: wait hdmi disable ack failed\n", __func__); -+ -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+} -+ -+static void hdmirx_controller_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ -+ reinit_completion(&hdmirx_dev->timer_base_lock); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ /* en irq */ -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TIMER_BASE_LOCKED_IRQ, TIMER_BASE_LOCKED_IRQ); -+ /* write irefclk freq */ -+ hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, IREF_CLK_FREQ_HZ); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->timer_base_lock, -+ msecs_to_jiffies(20))) -+ dev_err(dev, "%s wait timer base lock failed\n", __func__); -+ -+ hdmirx_update_bits(hdmirx_dev, CMU_CONFIG0, -+ TMDSQPCLK_STABLE_FREQ_MARGIN_MASK | -+ AUDCLK_STABLE_FREQ_MARGIN_MASK, -+ TMDSQPCLK_STABLE_FREQ_MARGIN(2) | -+ AUDCLK_STABLE_FREQ_MARGIN(1)); -+ hdmirx_update_bits(hdmirx_dev, DESCRAND_EN_CONTROL, -+ SCRAMB_EN_SEL_QST_MASK, SCRAMB_EN_SEL_QST(1)); -+ hdmirx_update_bits(hdmirx_dev, CED_CONFIG, -+ CED_VIDDATACHECKEN_QST | -+ CED_DATAISCHECKEN_QST | -+ CED_GBCHECKEN_QST | -+ CED_CTRLCHECKEN_QST | -+ CED_CHLOCKMAXER_QST_MASK, -+ CED_VIDDATACHECKEN_QST | -+ CED_GBCHECKEN_QST | -+ CED_CTRLCHECKEN_QST | -+ CED_CHLOCKMAXER_QST(0x10)); -+ hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0, -+ VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST_MASK, -+ VS_REMAPFILTER_EN_QST | VS_FILTER_ORDER_QST(0x3)); -+} -+ -+static void hdmirx_set_negative_pol(struct snps_hdmirx_dev *hdmirx_dev, bool en) -+{ -+ if (en) { -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN); -+ hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2, -+ VPROC_VSYNC_POL_OVR_VALUE | -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_VALUE | -+ VPROC_HSYNC_POL_OVR_EN, -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_EN); -+ return; -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, -+ VSYNC_TOGGLE_EN | HSYNC_TOGGLE_EN, 0); -+ -+ hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2, -+ VPROC_VSYNC_POL_OVR_VALUE | -+ VPROC_VSYNC_POL_OVR_EN | -+ VPROC_HSYNC_POL_OVR_VALUE | -+ VPROC_HSYNC_POL_OVR_EN, 0); -+} -+ -+static int hdmirx_try_to_get_timings(struct snps_hdmirx_dev *hdmirx_dev, -+ struct v4l2_dv_timings *timings, -+ int try_cnt) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int i, cnt = 0, fail_cnt = 0, ret = 0; -+ bool from_dma = false; -+ -+ hdmirx_set_negative_pol(hdmirx_dev, false); -+ for (i = 0; i < try_cnt; i++) { -+ ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma); -+ if (ret) { -+ cnt = 0; -+ fail_cnt++; -+ if (fail_cnt > 3) { -+ hdmirx_set_negative_pol(hdmirx_dev, true); -+ from_dma = true; -+ } -+ } else { -+ cnt++; -+ } -+ if (cnt >= 5) -+ break; -+ -+ usleep_range(10 * 1000, 10 * 1100); -+ } -+ -+ if (try_cnt > 8 && cnt < 5) -+ v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable\n", __func__); -+ -+ return ret; -+} -+ -+static void hdmirx_format_change(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_dv_timings timings; -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ const struct v4l2_event ev_src_chg = { -+ .type = V4L2_EVENT_SOURCE_CHANGE, -+ .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, -+ }; -+ -+ if (hdmirx_try_to_get_timings(hdmirx_dev, &timings, 20)) { -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(20)); -+ return; -+ } -+ -+ hdmirx_dev->got_timing = true; -+ v4l2_dbg(1, debug, v4l2_dev, "%s: queue res_chg_event\n", __func__); -+ v4l2_event_queue(&stream->vdev, &ev_src_chg); -+} -+ -+static void hdmirx_set_ddr_store_fmt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ enum ddr_store_fmt store_fmt; -+ u32 dma_cfg1; -+ -+ switch (hdmirx_dev->pix_fmt) { -+ case HDMIRX_RGB888: -+ store_fmt = STORE_RGB888; -+ break; -+ case HDMIRX_YUV444: -+ store_fmt = STORE_YUV444_8BIT; -+ break; -+ case HDMIRX_YUV422: -+ store_fmt = STORE_YUV422_8BIT; -+ break; -+ case HDMIRX_YUV420: -+ store_fmt = STORE_YUV420_8BIT; -+ break; -+ default: -+ store_fmt = STORE_RGB888; -+ break; -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1, -+ DDR_STORE_FORMAT_MASK, DDR_STORE_FORMAT(store_fmt)); -+ dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n", -+ __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1); -+} -+ -+static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 mu_status, scdc_status, dma_st10, cmu_st; -+ u32 i; -+ -+ for (i = 0; i < 300; i++) { -+ mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS); -+ scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3); -+ dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10); -+ cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS); -+ -+ if ((mu_status & TMDSVALID_STABLE_ST) && -+ (dma_st10 & HDMIRX_LOCK) && -+ (cmu_st & TMDSQPCLK_LOCKED_ST)) -+ break; -+ -+ if (!tx_5v_power_present(hdmirx_dev)) { -+ v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); -+ return -1; -+ } -+ -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+ } -+ -+ if (i == 300) { -+ v4l2_err(v4l2_dev, "%s: signal not lock, tmds_clk_ratio:%d\n", -+ __func__, hdmirx_dev->tmds_clk_ratio); -+ v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n", -+ __func__, mu_status, scdc_status, dma_st10); -+ return -1; -+ } -+ -+ v4l2_info(v4l2_dev, "%s: signal lock ok, i:%d\n", __func__, i); -+ hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ); -+ -+ reinit_completion(&hdmirx_dev->avi_pkt_rcv); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, PKTDEC_AVIIF_RCV_IRQ); -+ -+ if (!wait_for_completion_timeout(&hdmirx_dev->avi_pkt_rcv, -+ msecs_to_jiffies(300))) { -+ v4l2_err(v4l2_dev, "%s wait avi_pkt_rcv failed\n", __func__); -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, 0); -+ } -+ -+ usleep_range(50 * 1000, 50 * 1010); -+ hdmirx_format_change(hdmirx_dev); -+ -+ return 0; -+} -+ -+static void hdmirx_dma_config(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_set_ddr_store_fmt(hdmirx_dev); -+ -+ /* Note: uv_swap, rb can not swap, doc err*/ -+ if (hdmirx_dev->cur_fmt_fourcc != V4L2_PIX_FMT_NV16) -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, RB_SWAP_EN); -+ else -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, 0); -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7, -+ LOCK_FRAME_NUM_MASK, -+ LOCK_FRAME_NUM(2)); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1, -+ UV_WID_MASK | Y_WID_MASK | ABANDON_EN, -+ UV_WID(1) | Y_WID(2) | ABANDON_EN); -+} -+ -+static void hdmirx_submodule_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ /* Note: if not config HDCP2_CONFIG, there will be some errors; */ -+ hdmirx_update_bits(hdmirx_dev, HDCP2_CONFIG, -+ HDCP2_SWITCH_OVR_VALUE | -+ HDCP2_SWITCH_OVR_EN, -+ HDCP2_SWITCH_OVR_EN); -+ hdmirx_scdc_init(hdmirx_dev); -+ hdmirx_controller_init(hdmirx_dev); -+} -+ -+static int hdmirx_enum_input(struct file *file, void *priv, -+ struct v4l2_input *input) -+{ -+ if (input->index > 0) -+ return -EINVAL; -+ -+ input->type = V4L2_INPUT_TYPE_CAMERA; -+ input->std = 0; -+ strscpy(input->name, "HDMI IN", sizeof(input->name)); -+ input->capabilities = V4L2_IN_CAP_DV_TIMINGS; -+ -+ return 0; -+} -+ -+static int hdmirx_get_input(struct file *file, void *priv, unsigned int *i) -+{ -+ *i = 0; -+ return 0; -+} -+ -+static int hdmirx_set_input(struct file *file, void *priv, unsigned int i) -+{ -+ if (i) -+ return -EINVAL; -+ return 0; -+} -+ -+static void hdmirx_set_fmt(struct hdmirx_stream *stream, -+ struct v4l2_pix_format_mplane *pixm, bool try) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt; -+ const struct v4l2_format_info *finfo; -+ unsigned int imagesize = 0; -+ int i; -+ -+ memset(&pixm->plane_fmt[0], 0, sizeof(struct v4l2_plane_pix_format)); -+ finfo = v4l2_format_info(pixm->pixelformat); -+ if (!finfo) { -+ finfo = v4l2_format_info(V4L2_PIX_FMT_BGR24); -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: set_fmt:%#x not supported, use def_fmt:%x\n", -+ __func__, pixm->pixelformat, finfo->format); -+ } -+ -+ if (!bt->width || !bt->height) -+ v4l2_dbg(1, debug, v4l2_dev, "%s: invalid resolution:%#xx%#x\n", -+ __func__, bt->width, bt->height); -+ -+ pixm->pixelformat = finfo->format; -+ pixm->width = bt->width; -+ pixm->height = bt->height; -+ pixm->num_planes = finfo->mem_planes; -+ pixm->quantization = V4L2_QUANTIZATION_DEFAULT; -+ pixm->colorspace = V4L2_COLORSPACE_SRGB; -+ pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; -+ -+ if (bt->interlaced == V4L2_DV_INTERLACED) -+ pixm->field = V4L2_FIELD_INTERLACED_TB; -+ else -+ pixm->field = V4L2_FIELD_NONE; -+ -+ memset(pixm->reserved, 0, sizeof(pixm->reserved)); -+ -+ v4l2_fill_pixfmt_mp(pixm, finfo->format, pixm->width, pixm->height); -+ -+ for (i = 0; i < pixm->num_planes; i++) { -+ struct v4l2_plane_pix_format *plane_fmt; -+ int width, height, bpl, size, bpp = 0; -+ -+ if (!i) { -+ width = pixm->width; -+ height = pixm->height; -+ } else { -+ width = pixm->width / finfo->hdiv; -+ height = pixm->height / finfo->vdiv; -+ } -+ -+ switch (finfo->format) { -+ case V4L2_PIX_FMT_NV24: -+ case V4L2_PIX_FMT_NV16: -+ case V4L2_PIX_FMT_NV12: -+ case V4L2_PIX_FMT_BGR24: -+ bpp = finfo->bpp[i]; -+ break; -+ default: -+ v4l2_dbg(1, debug, v4l2_dev, -+ "fourcc: %#x is not supported\n", -+ finfo->format); -+ break; -+ } -+ -+ bpl = ALIGN(width * bpp, MEMORY_ALIGN_ROUND_UP_BYTES); -+ size = bpl * height; -+ imagesize += size; -+ -+ if (finfo->mem_planes > i) { -+ /* Set bpl and size for each mplane */ -+ plane_fmt = pixm->plane_fmt + i; -+ plane_fmt->bytesperline = bpl; -+ plane_fmt->sizeimage = size; -+ } -+ -+ v4l2_dbg(1, debug, v4l2_dev, -+ "C-Plane %i size: %d, Total imagesize: %d\n", -+ i, size, imagesize); -+ } -+ -+ /* Convert to non-MPLANE format as we want to unify non-MPLANE and MPLANE */ -+ if (finfo->mem_planes == 1) -+ pixm->plane_fmt[0].sizeimage = imagesize; -+ -+ if (!try) { -+ stream->out_finfo = finfo; -+ stream->pixm = *pixm; -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: req(%d, %d), out(%d, %d), fmt:%#x\n", __func__, -+ pixm->width, pixm->height, stream->pixm.width, -+ stream->pixm.height, finfo->format); -+ } -+} -+ -+static int hdmirx_enum_fmt_vid_cap_mplane(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ -+ if (f->index >= 1) -+ return -EINVAL; -+ -+ f->pixelformat = hdmirx_dev->cur_fmt_fourcc; -+ -+ return 0; -+} -+ -+static int hdmirx_s_fmt_vid_cap_mplane(struct file *file, -+ void *priv, struct v4l2_format *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (vb2_is_busy(&stream->buf_queue)) { -+ v4l2_err(v4l2_dev, "%s: queue busy\n", __func__); -+ return -EBUSY; -+ } -+ -+ hdmirx_set_fmt(stream, &f->fmt.pix_mp, false); -+ -+ return 0; -+} -+ -+static int hdmirx_g_fmt_vid_cap_mplane(struct file *file, void *fh, -+ struct v4l2_format *f) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_pix_format_mplane pixm = {}; -+ -+ pixm.pixelformat = hdmirx_dev->cur_fmt_fourcc; -+ hdmirx_set_fmt(stream, &pixm, true); -+ f->fmt.pix_mp = pixm; -+ -+ return 0; -+} -+ -+static int hdmirx_g_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 dma_cfg1; -+ -+ *timings = hdmirx_dev->timings; -+ dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n", -+ __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1); -+ -+ return 0; -+} -+ -+static int hdmirx_s_dv_timings(struct file *file, void *_fh, -+ struct v4l2_dv_timings *timings) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (!timings) -+ return -EINVAL; -+ -+ if (debug) -+ v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name, -+ "s_dv_timings: ", timings, false); -+ -+ if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) { -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: timings out of range\n", __func__); -+ return -ERANGE; -+ } -+ -+ /* Check if the timings are part of the CEA-861 timings. */ -+ v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap, 0, NULL, NULL); -+ -+ if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__); -+ return 0; -+ } -+ -+ /* -+ * Changing the timings implies a format change, which is not allowed -+ * while buffers for use with streaming have already been allocated. -+ */ -+ if (vb2_is_busy(&stream->buf_queue)) -+ return -EBUSY; -+ -+ hdmirx_dev->timings = *timings; -+ /* Update the internal format */ -+ hdmirx_set_fmt(stream, &stream->pixm, false); -+ -+ return 0; -+} -+ -+static int hdmirx_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ struct hdmirx_stream *stream = video_drvdata(file); -+ struct device *dev = stream->hdmirx_dev->dev; -+ -+ strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); -+ strscpy(cap->card, dev->driver->name, sizeof(cap->card)); -+ -+ return 0; -+} -+ -+static int hdmirx_queue_setup(struct vb2_queue *queue, -+ unsigned int *num_buffers, -+ unsigned int *num_planes, -+ unsigned int sizes[], -+ struct device *alloc_ctxs[]) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ const struct v4l2_pix_format_mplane *pixm = NULL; -+ const struct v4l2_format_info *out_finfo; -+ u32 i, height; -+ -+ pixm = &stream->pixm; -+ out_finfo = stream->out_finfo; -+ -+ if (!num_planes || !out_finfo) { -+ v4l2_err(v4l2_dev, "%s: out_fmt not set\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (*num_planes) { -+ if (*num_planes != pixm->num_planes) -+ return -EINVAL; -+ -+ for (i = 0; i < *num_planes; i++) -+ if (sizes[i] < pixm->plane_fmt[i].sizeimage) -+ return -EINVAL; -+ return 0; -+ } -+ -+ *num_planes = out_finfo->mem_planes; -+ height = pixm->height; -+ -+ for (i = 0; i < out_finfo->mem_planes; i++) -+ sizes[i] = pixm->plane_fmt[i].sizeimage; -+ -+ v4l2_dbg(1, debug, v4l2_dev, "%s: count %d, size %d\n", -+ v4l2_type_names[queue->type], *num_buffers, sizes[0]); -+ -+ return 0; -+} -+ -+/* -+ * The vb2_buffer are stored in hdmirx_buffer, in order to unify -+ * mplane buffer and none-mplane buffer. -+ */ -+static void hdmirx_buf_queue(struct vb2_buffer *vb) -+{ -+ const struct v4l2_format_info *out_finfo; -+ struct vb2_v4l2_buffer *vbuf; -+ struct hdmirx_buffer *hdmirx_buf; -+ struct vb2_queue *queue; -+ struct hdmirx_stream *stream; -+ const struct v4l2_pix_format_mplane *pixm; -+ unsigned long lock_flags = 0; -+ int i; -+ -+ vbuf = to_vb2_v4l2_buffer(vb); -+ hdmirx_buf = container_of(vbuf, struct hdmirx_buffer, vb); -+ queue = vb->vb2_queue; -+ stream = vb2_get_drv_priv(queue); -+ pixm = &stream->pixm; -+ out_finfo = stream->out_finfo; -+ -+ memset(hdmirx_buf->buff_addr, 0, sizeof(hdmirx_buf->buff_addr)); -+ -+ /* -+ * If mplanes > 1, every c-plane has its own m-plane, -+ * otherwise, multiple c-planes are in the same m-plane -+ */ -+ for (i = 0; i < out_finfo->mem_planes; i++) -+ hdmirx_buf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); -+ -+ if (out_finfo->mem_planes == 1) { -+ if (out_finfo->comp_planes == 1) { -+ hdmirx_buf->buff_addr[HDMIRX_PLANE_CBCR] = -+ hdmirx_buf->buff_addr[HDMIRX_PLANE_Y]; -+ } else { -+ for (i = 0; i < out_finfo->comp_planes - 1; i++) -+ hdmirx_buf->buff_addr[i + 1] = -+ hdmirx_buf->buff_addr[i] + -+ pixm->plane_fmt[i].bytesperline * -+ pixm->height; -+ } -+ } -+ -+ spin_lock_irqsave(&stream->vbq_lock, lock_flags); -+ list_add_tail(&hdmirx_buf->queue, &stream->buf_head); -+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); -+} -+ -+static void return_all_buffers(struct hdmirx_stream *stream, -+ enum vb2_buffer_state state) -+{ -+ struct hdmirx_buffer *buf; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&stream->vbq_lock, flags); -+ if (stream->curr_buf) -+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head); -+ if (stream->next_buf && stream->next_buf != stream->curr_buf) -+ list_add_tail(&stream->next_buf->queue, &stream->buf_head); -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ -+ while (!list_empty(&stream->buf_head)) { -+ buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, queue); -+ list_del(&buf->queue); -+ spin_unlock_irqrestore(&stream->vbq_lock, flags); -+ vb2_buffer_done(&buf->vb.vb2_buf, state); -+ spin_lock_irqsave(&stream->vbq_lock, flags); -+ } -+ spin_unlock_irqrestore(&stream->vbq_lock, flags); -+} -+ -+static void hdmirx_stop_streaming(struct vb2_queue *queue) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ v4l2_info(v4l2_dev, "stream start stopping\n"); -+ mutex_lock(&hdmirx_dev->stream_lock); -+ WRITE_ONCE(stream->stopping, true); -+ -+ /* wait last irq to return the buffer */ -+ ret = wait_event_timeout(stream->wq_stopped, !stream->stopping, -+ msecs_to_jiffies(500)); -+ if (!ret) { -+ v4l2_err(v4l2_dev, "%s: timeout waiting last irq\n", -+ __func__); -+ WRITE_ONCE(stream->stopping, false); -+ } -+ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ return_all_buffers(stream, VB2_BUF_STATE_ERROR); -+ mutex_unlock(&hdmirx_dev->stream_lock); -+ v4l2_info(v4l2_dev, "stream stopping finished\n"); -+} -+ -+static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count) -+{ -+ struct hdmirx_stream *stream = vb2_get_drv_priv(queue); -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ unsigned long lock_flags = 0; -+ int line_flag; -+ -+ if (!hdmirx_dev->got_timing) { -+ v4l2_dbg(1, debug, v4l2_dev, "timing is invalid\n"); -+ return 0; -+ } -+ -+ mutex_lock(&hdmirx_dev->stream_lock); -+ stream->frame_idx = 0; -+ stream->line_flag_int_cnt = 0; -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ stream->irq_stat = 0; -+ queue->min_queued_buffers = 1; -+ -+ WRITE_ONCE(stream->stopping, false); -+ -+ spin_lock_irqsave(&stream->vbq_lock, lock_flags); -+ if (!stream->curr_buf) { -+ if (!list_empty(&stream->buf_head)) { -+ stream->curr_buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, -+ queue); -+ list_del(&stream->curr_buf->queue); -+ } else { -+ stream->curr_buf = NULL; -+ } -+ } -+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags); -+ -+ v4l2_dbg(2, debug, v4l2_dev, -+ "%s: start_stream cur_buf y_addr:%#x, uv_addr:%#x\n", -+ __func__, stream->curr_buf->buff_addr[HDMIRX_PLANE_Y], -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG2, -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_Y]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG3, -+ stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ -+ if (bt->height) { -+ if (bt->interlaced == V4L2_DV_INTERLACED) -+ line_flag = bt->height / 4; -+ else -+ line_flag = bt->height / 2; -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7, -+ LINE_FLAG_NUM_MASK, -+ LINE_FLAG_NUM(line_flag)); -+ } else { -+ v4l2_err(v4l2_dev, "height err: %d\n", bt->height); -+ } -+ -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, HDMIRX_DMA_EN); -+ v4l2_dbg(1, debug, v4l2_dev, "%s: enable dma", __func__); -+ mutex_unlock(&hdmirx_dev->stream_lock); -+ -+ return 0; -+} -+ -+/* vb2 queue */ -+static const struct vb2_ops hdmirx_vb2_ops = { -+ .queue_setup = hdmirx_queue_setup, -+ .buf_queue = hdmirx_buf_queue, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+ .stop_streaming = hdmirx_stop_streaming, -+ .start_streaming = hdmirx_start_streaming, -+}; -+ -+static int hdmirx_init_vb2_queue(struct vb2_queue *q, -+ struct hdmirx_stream *stream, -+ enum v4l2_buf_type buf_type) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ -+ q->type = buf_type; -+ q->io_modes = VB2_MMAP | VB2_DMABUF; -+ q->drv_priv = stream; -+ q->ops = &hdmirx_vb2_ops; -+ q->mem_ops = &vb2_dma_contig_memops; -+ q->buf_struct_size = sizeof(struct hdmirx_buffer); -+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; -+ q->lock = &stream->vlock; -+ q->dev = hdmirx_dev->dev; -+ /* -+ * rk3588 doesn't use iommu and works only with dma buffers -+ * that are physically contiguous in memory. -+ */ -+ q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; -+ return vb2_queue_init(q); -+} -+ -+/* video device */ -+static const struct v4l2_ioctl_ops hdmirx_v4l2_ioctl_ops = { -+ .vidioc_querycap = hdmirx_querycap, -+ .vidioc_try_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane, -+ .vidioc_s_fmt_vid_cap_mplane = hdmirx_s_fmt_vid_cap_mplane, -+ .vidioc_g_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane, -+ .vidioc_enum_fmt_vid_cap = hdmirx_enum_fmt_vid_cap_mplane, -+ -+ .vidioc_s_dv_timings = hdmirx_s_dv_timings, -+ .vidioc_g_dv_timings = hdmirx_g_dv_timings, -+ .vidioc_enum_dv_timings = hdmirx_enum_dv_timings, -+ .vidioc_query_dv_timings = hdmirx_query_dv_timings, -+ .vidioc_dv_timings_cap = hdmirx_dv_timings_cap, -+ .vidioc_enum_input = hdmirx_enum_input, -+ .vidioc_g_input = hdmirx_get_input, -+ .vidioc_s_input = hdmirx_set_input, -+ .vidioc_g_edid = hdmirx_get_edid, -+ .vidioc_s_edid = hdmirx_set_edid, -+ .vidioc_g_parm = hdmirx_g_parm, -+ -+ .vidioc_reqbufs = vb2_ioctl_reqbufs, -+ .vidioc_querybuf = vb2_ioctl_querybuf, -+ .vidioc_create_bufs = vb2_ioctl_create_bufs, -+ .vidioc_qbuf = vb2_ioctl_qbuf, -+ .vidioc_expbuf = vb2_ioctl_expbuf, -+ .vidioc_dqbuf = vb2_ioctl_dqbuf, -+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, -+ .vidioc_streamon = vb2_ioctl_streamon, -+ .vidioc_streamoff = vb2_ioctl_streamoff, -+ -+ .vidioc_log_status = v4l2_ctrl_log_status, -+ .vidioc_subscribe_event = hdmirx_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+}; -+ -+static const struct v4l2_file_operations hdmirx_fops = { -+ .owner = THIS_MODULE, -+ .open = v4l2_fh_open, -+ .release = vb2_fop_release, -+ .unlocked_ioctl = video_ioctl2, -+ .poll = vb2_fop_poll, -+ .mmap = vb2_fop_mmap, -+}; -+ -+static int hdmirx_register_stream_vdev(struct hdmirx_stream *stream) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct video_device *vdev = &stream->vdev; -+ int ret = 0; -+ -+ strscpy(vdev->name, "stream_hdmirx", sizeof(vdev->name)); -+ INIT_LIST_HEAD(&stream->buf_head); -+ spin_lock_init(&stream->vbq_lock); -+ mutex_init(&stream->vlock); -+ init_waitqueue_head(&stream->wq_stopped); -+ stream->curr_buf = NULL; -+ stream->next_buf = NULL; -+ -+ vdev->ioctl_ops = &hdmirx_v4l2_ioctl_ops; -+ vdev->release = video_device_release_empty; -+ vdev->fops = &hdmirx_fops; -+ vdev->minor = -1; -+ vdev->v4l2_dev = v4l2_dev; -+ vdev->lock = &stream->vlock; -+ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | -+ V4L2_CAP_STREAMING; -+ video_set_drvdata(vdev, stream); -+ vdev->vfl_dir = VFL_DIR_RX; -+ -+ hdmirx_init_vb2_queue(&stream->buf_queue, stream, -+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); -+ vdev->queue = &stream->buf_queue; -+ -+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); -+ if (ret < 0) { -+ v4l2_err(v4l2_dev, "video_register_device failed: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void process_signal_change(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ hdmirx_reset_dma(hdmirx_dev); -+ hdmirx_dev->got_timing = false; -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_res_change, -+ msecs_to_jiffies(50)); -+} -+ -+static void avpunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (status & (CED_DYN_CNT_CH2_IRQ | -+ CED_DYN_CNT_CH1_IRQ | -+ CED_DYN_CNT_CH0_IRQ)) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: avp0_st:%#x\n", -+ __func__, status); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0); -+} -+ -+static void avpunit_1_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ if (status & DEFRAMER_VSYNC_THR_REACHED_IRQ) { -+ v4l2_info(v4l2_dev, "Vertical Sync threshold reached interrupt %#x", status); -+ hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N, -+ DEFRAMER_VSYNC_THR_REACHED_MASK_N, 0); -+ *handled = true; -+ } -+} -+ -+static void mainunit_0_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "mu0_st:%#x\n", status); -+ if (status & TIMER_BASE_LOCKED_IRQ) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, -+ TIMER_BASE_LOCKED_IRQ, 0); -+ complete(&hdmirx_dev->timer_base_lock); -+ *handled = true; -+ } -+ -+ if (status & TMDSQPCLK_OFF_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_OFF_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ if (status & TMDSQPCLK_LOCKED_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_LOCKED_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0); -+} -+ -+static void mainunit_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "mu2_st:%#x\n", status); -+ if (status & PHYCREG_CR_WRITE_DONE) { -+ hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N, -+ PHYCREG_CR_WRITE_DONE, 0); -+ complete(&hdmirx_dev->cr_write_done); -+ *handled = true; -+ } -+ -+ if (status & TMDSVALID_STABLE_CHG) { -+ process_signal_change(hdmirx_dev); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSVALID_STABLE_CHG\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0); -+} -+ -+static void pkt_2_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: pk2_st:%#x\n", __func__, status); -+ if (status & PKTDEC_AVIIF_RCV_IRQ) { -+ hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N, -+ PKTDEC_AVIIF_RCV_IRQ, 0); -+ complete(&hdmirx_dev->avi_pkt_rcv); -+ v4l2_dbg(2, debug, v4l2_dev, "%s: AVIIF_RCV_IRQ\n", __func__); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+} -+ -+static void scdc_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ int status, bool *handled) -+{ -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: scdc_st:%#x\n", __func__, status); -+ if (status & SCDCTMDSCCFG_CHG) { -+ hdmirx_tmds_clk_ratio_config(hdmirx_dev); -+ *handled = true; -+ } -+ -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+} -+ -+static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct arm_smccc_res res; -+ u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st; -+ u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk; -+ bool handled = false; -+ -+ mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N); -+ mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N); -+ pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N); -+ scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N); -+ mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS); -+ mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS); -+ pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS); -+ scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS); -+ avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS); -+ avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS); -+ avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N); -+ avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N); -+ mu0_st &= mu0_mask; -+ mu2_st &= mu2_mask; -+ pk2_st &= pk2_mask; -+ avp1_st &= avp1_msk; -+ avp0_st &= avp0_msk; -+ scdc_st &= scdc_mask; -+ -+ if (avp0_st) -+ avpunit_0_int_handler(hdmirx_dev, avp0_st, &handled); -+ if (avp1_st) -+ avpunit_1_int_handler(hdmirx_dev, avp1_st, &handled); -+ if (mu0_st) -+ mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled); -+ if (mu2_st) -+ mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled); -+ if (pk2_st) -+ pkt_2_int_handler(hdmirx_dev, pk2_st, &handled); -+ if (scdc_st) -+ scdc_int_handler(hdmirx_dev, scdc_st, &handled); -+ -+ if (!handled) { -+ v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled", __func__); -+ v4l2_dbg(2, debug, v4l2_dev, -+ "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk2:%#x, scdc:%#x\n", -+ avp0_st, avp1_st, mu0_st, mu2_st, pk2_st, scdc_st); -+ } -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__); -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ return handled ? IRQ_HANDLED : IRQ_NONE; -+} -+ -+static void hdmirx_vb_done(struct hdmirx_stream *stream, -+ struct vb2_v4l2_buffer *vb_done) -+{ -+ const struct v4l2_format_info *finfo = stream->out_finfo; -+ u32 i; -+ -+ /* Dequeue a filled buffer */ -+ for (i = 0; i < finfo->mem_planes; i++) { -+ vb2_set_plane_payload(&vb_done->vb2_buf, i, -+ stream->pixm.plane_fmt[i].sizeimage); -+ } -+ -+ vb_done->vb2_buf.timestamp = ktime_get_ns(); -+ vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE); -+} -+ -+static void dma_idle_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ bool *handled) -+{ -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ struct vb2_v4l2_buffer *vb_done = NULL; -+ -+ if (!(stream->irq_stat) && !(stream->irq_stat & LINE_FLAG_INT_EN)) -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: last time have no line_flag_irq\n", __func__); -+ -+ if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT) -+ goto DMA_IDLE_OUT; -+ -+ if (bt->interlaced != V4L2_DV_INTERLACED || -+ !(stream->line_flag_int_cnt % 2)) { -+ if (stream->next_buf) { -+ if (stream->curr_buf) -+ vb_done = &stream->curr_buf->vb; -+ -+ if (vb_done) { -+ vb_done->vb2_buf.timestamp = ktime_get_ns(); -+ vb_done->sequence = stream->frame_idx; -+ hdmirx_vb_done(stream, vb_done); -+ stream->frame_idx++; -+ if (stream->frame_idx == 30) -+ v4l2_info(v4l2_dev, "rcv frames\n"); -+ } -+ -+ stream->curr_buf = NULL; -+ if (stream->next_buf) { -+ stream->curr_buf = stream->next_buf; -+ stream->next_buf = NULL; -+ } -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: next_buf NULL, skip vb_done\n", __func__); -+ } -+ } -+ -+DMA_IDLE_OUT: -+ *handled = true; -+} -+ -+static void line_flag_int_handler(struct snps_hdmirx_dev *hdmirx_dev, -+ bool *handled) -+{ -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ struct v4l2_dv_timings timings = hdmirx_dev->timings; -+ struct v4l2_bt_timings *bt = &timings.bt; -+ u32 dma_cfg6; -+ -+ stream->line_flag_int_cnt++; -+ if (!(stream->irq_stat) && !(stream->irq_stat & HDMIRX_DMA_IDLE_INT)) -+ v4l2_dbg(1, debug, v4l2_dev, -+ "%s: last have no dma_idle_irq\n", __func__); -+ dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6); -+ if (!(dma_cfg6 & HDMIRX_DMA_EN)) { -+ v4l2_dbg(2, debug, v4l2_dev, "%s: dma not on\n", __func__); -+ goto LINE_FLAG_OUT; -+ } -+ -+ if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT) -+ goto LINE_FLAG_OUT; -+ -+ if (bt->interlaced != V4L2_DV_INTERLACED || -+ !(stream->line_flag_int_cnt % 2)) { -+ if (!stream->next_buf) { -+ spin_lock(&stream->vbq_lock); -+ if (!list_empty(&stream->buf_head)) { -+ stream->next_buf = list_first_entry(&stream->buf_head, -+ struct hdmirx_buffer, -+ queue); -+ list_del(&stream->next_buf->queue); -+ } else { -+ stream->next_buf = NULL; -+ } -+ spin_unlock(&stream->vbq_lock); -+ -+ if (stream->next_buf) { -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG2, -+ stream->next_buf->buff_addr[HDMIRX_PLANE_Y]); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG3, -+ stream->next_buf->buff_addr[HDMIRX_PLANE_CBCR]); -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: no buffer is available\n", __func__); -+ } -+ } -+ } else { -+ v4l2_dbg(3, debug, v4l2_dev, "%s: interlace:%d, line_flag_int_cnt:%d\n", -+ __func__, bt->interlaced, stream->line_flag_int_cnt); -+ } -+ -+LINE_FLAG_OUT: -+ *handled = true; -+} -+ -+static irqreturn_t hdmirx_dma_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ struct hdmirx_stream *stream = &hdmirx_dev->stream; -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ u32 dma_stat1, dma_stat13; -+ bool handled = false; -+ -+ dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1); -+ dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13); -+ v4l2_dbg(3, debug, v4l2_dev, "dma_irq st1:%#x, st13:%d\n", -+ dma_stat1, dma_stat13); -+ -+ if (READ_ONCE(stream->stopping)) { -+ v4l2_dbg(1, debug, v4l2_dev, "%s: stop stream\n", __func__); -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, -+ LINE_FLAG_INT_EN | -+ HDMIRX_DMA_IDLE_INT | -+ HDMIRX_LOCK_DISABLE_INT | -+ LAST_FRAME_AXI_UNFINISH_INT_EN | -+ FIFO_OVERFLOW_INT_EN | -+ FIFO_UNDERFLOW_INT_EN | -+ HDMIRX_AXI_ERROR_INT_EN, 0); -+ WRITE_ONCE(stream->stopping, false); -+ wake_up(&stream->wq_stopped); -+ return IRQ_HANDLED; -+ } -+ -+ if (dma_stat1 & HDMIRX_DMA_IDLE_INT) -+ dma_idle_int_handler(hdmirx_dev, &handled); -+ -+ if (dma_stat1 & LINE_FLAG_INT_EN) -+ line_flag_int_handler(hdmirx_dev, &handled); -+ -+ if (!handled) -+ v4l2_dbg(3, debug, v4l2_dev, -+ "%s: dma irq not handled, dma_stat1:%#x\n", -+ __func__, dma_stat1); -+ -+ stream->irq_stat = dma_stat1; -+ hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff); -+ -+ return IRQ_HANDLED; -+} -+ -+static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct arm_smccc_res res; -+ int ret; -+ -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_heartbeat, -+ msecs_to_jiffies(10)); -+ arm_smccc_smc(SIP_WDT_CFG, WDT_START, 0, 0, 0, 0, 0, 0, &res); -+ hdmirx_submodule_init(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, -+ POWERPROVIDED); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ hdmirx_phy_config(hdmirx_dev); -+ ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev); -+ if (ret) { -+ hdmirx_plugout(hdmirx_dev); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(200)); -+ return; -+ } -+ hdmirx_dma_config(hdmirx_dev); -+ hdmirx_interrupts_setup(hdmirx_dev, true); -+} -+ -+static void hdmirx_delayed_work_hotplug(struct work_struct *work) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ bool plugin; -+ -+ hdmirx_dev = container_of(work, struct snps_hdmirx_dev, -+ delayed_work_hotplug.work); -+ -+ mutex_lock(&hdmirx_dev->work_lock); -+ hdmirx_dev->got_timing = false; -+ plugin = tx_5v_power_present(hdmirx_dev); -+ v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin); -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n", -+ __func__, plugin); -+ -+ if (plugin) -+ hdmirx_plugin(hdmirx_dev); -+ else -+ hdmirx_plugout(hdmirx_dev); -+ -+ mutex_unlock(&hdmirx_dev->work_lock); -+} -+ -+static void hdmirx_delayed_work_res_change(struct work_struct *work) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ bool plugin; -+ -+ hdmirx_dev = container_of(work, struct snps_hdmirx_dev, -+ delayed_work_res_change.work); -+ -+ mutex_lock(&hdmirx_dev->work_lock); -+ plugin = tx_5v_power_present(hdmirx_dev); -+ v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: plugin:%d\n", -+ __func__, plugin); -+ if (plugin) { -+ hdmirx_interrupts_setup(hdmirx_dev, false); -+ hdmirx_submodule_init(hdmirx_dev); -+ hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, -+ POWERPROVIDED); -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ hdmirx_phy_config(hdmirx_dev); -+ -+ if (hdmirx_wait_lock_and_get_timing(hdmirx_dev)) { -+ hdmirx_plugout(hdmirx_dev); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(200)); -+ } else { -+ hdmirx_dma_config(hdmirx_dev); -+ hdmirx_interrupts_setup(hdmirx_dev, true); -+ } -+ } -+ mutex_unlock(&hdmirx_dev->work_lock); -+} -+ -+static void hdmirx_delayed_work_heartbeat(struct work_struct *work) -+{ -+ struct delayed_work *dwork = to_delayed_work(work); -+ struct snps_hdmirx_dev *hdmirx_dev = container_of(dwork, -+ struct snps_hdmirx_dev, -+ delayed_work_heartbeat); -+ -+ queue_work(system_highpri_wq, &hdmirx_dev->work_wdt_config); -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_heartbeat, HZ); -+} -+ -+static void hdmirx_work_wdt_config(struct work_struct *work) -+{ -+ struct arm_smccc_res res; -+ struct snps_hdmirx_dev *hdmirx_dev = container_of(work, -+ struct snps_hdmirx_dev, -+ work_wdt_config); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ arm_smccc_smc(SIP_WDT_CFG, WDT_PING, 0, 0, 0, 0, 0, 0, &res); -+ v4l2_dbg(3, debug, v4l2_dev, "hb\n"); -+} -+ -+static irqreturn_t hdmirx_5v_det_irq_handler(int irq, void *dev_id) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_id; -+ u32 val; -+ -+ val = gpiod_get_value(hdmirx_dev->detect_5v_gpio); -+ v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: 5v:%d\n", __func__, val); -+ -+ queue_delayed_work(system_unbound_wq, -+ &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(10)); -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct hdmirx_cec_ops hdmirx_cec_ops = { -+ .write = hdmirx_writel, -+ .read = hdmirx_readl, -+}; -+ -+static int hdmirx_parse_dt(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ int ret; -+ -+ hdmirx_dev->num_clks = devm_clk_bulk_get_all(dev, &hdmirx_dev->clks); -+ if (hdmirx_dev->num_clks < 1) -+ return -ENODEV; -+ -+ hdmirx_dev->resets[HDMIRX_RST_A].id = "axi"; -+ hdmirx_dev->resets[HDMIRX_RST_P].id = "apb"; -+ hdmirx_dev->resets[HDMIRX_RST_REF].id = "ref"; -+ hdmirx_dev->resets[HDMIRX_RST_BIU].id = "biu"; -+ -+ ret = devm_reset_control_bulk_get_exclusive(dev, HDMIRX_NUM_RST, -+ hdmirx_dev->resets); -+ if (ret < 0) { -+ dev_err(dev, "failed to get reset controls\n"); -+ return ret; -+ } -+ -+ hdmirx_dev->detect_5v_gpio = -+ devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); -+ -+ if (IS_ERR(hdmirx_dev->detect_5v_gpio)) { -+ dev_err(dev, "failed to get hdmirx hot plug detection gpio\n"); -+ return PTR_ERR(hdmirx_dev->detect_5v_gpio); -+ } -+ -+ hdmirx_dev->grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,grf"); -+ if (IS_ERR(hdmirx_dev->grf)) { -+ dev_err(dev, "failed to get rockchip,grf\n"); -+ return PTR_ERR(hdmirx_dev->grf); -+ } -+ -+ hdmirx_dev->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,vo1-grf"); -+ if (IS_ERR(hdmirx_dev->vo1_grf)) { -+ dev_err(dev, "failed to get rockchip,vo1-grf\n"); -+ return PTR_ERR(hdmirx_dev->vo1_grf); -+ } -+ -+ hdmirx_dev->hpd_trigger_level = !device_property_read_bool(dev, "hpd-is-active-low"); -+ -+ ret = of_reserved_mem_device_init(dev); -+ if (ret) -+ dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n"); -+ -+ return 0; -+} -+ -+static void hdmirx_disable_all_interrupts(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0); -+ hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0); -+ -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, HDCP_1_INT_CLEAR, 0xffffffff); -+ hdmirx_clear_interrupt(hdmirx_dev, CEC_INT_CLEAR, 0xffffffff); -+} -+ -+static int hdmirx_init(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0); -+ -+ regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2, -+ (HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) | -+ ((HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16)); -+ /* -+ * Some interrupts are enabled by default, so we disable -+ * all interrupts and clear interrupts status first. -+ */ -+ hdmirx_disable_all_interrupts(hdmirx_dev); -+ -+ return 0; -+} -+ -+static void hdmirx_load_default_edid(struct snps_hdmirx_dev *hdmirx_dev) -+{ -+ int ret; -+ struct v4l2_edid def_edid; -+ -+ hdmirx_hpd_ctrl(hdmirx_dev, false); -+ -+ /* disable hpd and write edid */ -+ def_edid.pad = 0; -+ def_edid.start_block = 0; -+ def_edid.blocks = EDID_NUM_BLOCKS_MAX; -+ -+ if (IS_ENABLED(CONFIG_HDMIRX_LOAD_DEFAULT_EDID)) -+ def_edid.edid = edid_init_data_340M; -+ else -+ def_edid.edid = hdmirx_dev->edid; -+ -+ ret = hdmirx_write_edid(hdmirx_dev, &def_edid, true); -+ if (ret) -+ dev_err(hdmirx_dev->dev, "%s: write edid failed\n", __func__); -+} -+ -+static void hdmirx_disable_irq(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct arm_smccc_res res; -+ -+ disable_irq(hdmirx_dev->hdmi_irq); -+ disable_irq(hdmirx_dev->dma_irq); -+ disable_irq(hdmirx_dev->det_irq); -+ -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_DIS, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_hotplug); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_res_change); -+ cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); -+ flush_work(&hdmirx_dev->work_wdt_config); -+ -+ arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static int hdmirx_disable(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ -+ clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks); -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: suspend\n", __func__); -+ -+ return pinctrl_pm_select_sleep_state(dev); -+} -+ -+static void hdmirx_enable_irq(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct arm_smccc_res res; -+ -+ enable_irq(hdmirx_dev->hdmi_irq); -+ enable_irq(hdmirx_dev->dma_irq); -+ enable_irq(hdmirx_dev->det_irq); -+ -+ arm_smccc_smc(RK_SIP_FIQ_CTRL, RK_SIP_FIQ_CTRL_FIQ_EN, -+ RK_IRQ_HDMIRX_HDMI, 0, 0, 0, 0, 0, &res); -+ -+ queue_delayed_work(system_unbound_wq, &hdmirx_dev->delayed_work_hotplug, -+ msecs_to_jiffies(20)); -+} -+ -+static int hdmirx_enable(struct device *dev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; -+ int ret; -+ -+ v4l2_dbg(2, debug, v4l2_dev, "%s: resume\n", __func__); -+ ret = pinctrl_pm_select_default_state(dev); -+ if (ret < 0) -+ return ret; -+ -+ ret = clk_bulk_prepare_enable(hdmirx_dev->num_clks, hdmirx_dev->clks); -+ if (ret) { -+ dev_err(dev, "failed to enable hdmirx bulk clks: %d\n", ret); -+ return ret; -+ } -+ -+ reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ usleep_range(150, 160); -+ reset_control_bulk_deassert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ usleep_range(150, 160); -+ -+ return 0; -+} -+ -+static int hdmirx_suspend(struct device *dev) -+{ -+ hdmirx_disable_irq(dev); -+ -+ return hdmirx_disable(dev); -+} -+ -+static int hdmirx_resume(struct device *dev) -+{ -+ int ret = hdmirx_enable(dev); -+ -+ if (ret) -+ return ret; -+ -+ hdmirx_enable_irq(dev); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops snps_hdmirx_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(hdmirx_suspend, hdmirx_resume) -+}; -+ -+static int hdmirx_setup_irq(struct snps_hdmirx_dev *hdmirx_dev, -+ struct platform_device *pdev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ int ret, irq; -+ -+ irq = platform_get_irq_byname(pdev, "hdmi"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get hdmi irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->hdmi_irq = irq; -+ ret = devm_request_irq(dev, irq, hdmirx_hdmi_irq_handler, 0, -+ "rk_hdmirx-hdmi", hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request hdmi irq\n"); -+ return ret; -+ } -+ -+ irq = platform_get_irq_byname(pdev, "dma"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get dma irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->dma_irq = irq; -+ ret = devm_request_threaded_irq(dev, irq, NULL, hdmirx_dma_irq_handler, -+ IRQF_ONESHOT, "rk_hdmirx-dma", -+ hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request dma irq\n"); -+ return ret; -+ } -+ -+ irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get hdmirx-5v irq\n"); -+ return irq; -+ } -+ -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ -+ hdmirx_dev->det_irq = irq; -+ ret = devm_request_irq(dev, irq, hdmirx_5v_det_irq_handler, -+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, -+ "rk_hdmirx-5v", hdmirx_dev); -+ if (ret) { -+ dev_err_probe(dev, ret, "failed to request hdmirx-5v irq\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int hdmirx_register_cec(struct snps_hdmirx_dev *hdmirx_dev, -+ struct platform_device *pdev) -+{ -+ struct device *dev = hdmirx_dev->dev; -+ struct hdmirx_cec_data cec_data; -+ int irq; -+ -+ irq = platform_get_irq_byname(pdev, "cec"); -+ if (irq < 0) { -+ dev_err_probe(dev, irq, "failed to get cec irq\n"); -+ return irq; -+ } -+ -+ hdmirx_dev->cec_notifier = cec_notifier_conn_register(dev, NULL, NULL); -+ if (!hdmirx_dev->cec_notifier) -+ return -EINVAL; -+ -+ cec_data.hdmirx = hdmirx_dev; -+ cec_data.dev = hdmirx_dev->dev; -+ cec_data.ops = &hdmirx_cec_ops; -+ cec_data.irq = irq; -+ -+ hdmirx_dev->cec = snps_hdmirx_cec_register(&cec_data); -+ if (!hdmirx_dev->cec) { -+ cec_notifier_conn_unregister(hdmirx_dev->cec_notifier); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int hdmirx_probe(struct platform_device *pdev) -+{ -+ struct snps_hdmirx_dev *hdmirx_dev; -+ struct device *dev = &pdev->dev; -+ struct v4l2_ctrl_handler *hdl; -+ struct hdmirx_stream *stream; -+ struct v4l2_device *v4l2_dev; -+ int ret; -+ -+ hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL); -+ if (!hdmirx_dev) -+ return -ENOMEM; -+ -+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); -+ if (ret) -+ return ret; -+ -+ hdmirx_dev->dev = dev; -+ dev_set_drvdata(dev, hdmirx_dev); -+ -+ ret = hdmirx_parse_dt(hdmirx_dev); -+ if (ret) -+ return ret; -+ -+ ret = hdmirx_setup_irq(hdmirx_dev, pdev); -+ if (ret) -+ return ret; -+ -+ hdmirx_dev->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(hdmirx_dev->regs)) -+ return dev_err_probe(dev, PTR_ERR(hdmirx_dev->regs), -+ "failed to remap regs resource\n"); -+ -+ mutex_init(&hdmirx_dev->stream_lock); -+ mutex_init(&hdmirx_dev->work_lock); -+ spin_lock_init(&hdmirx_dev->rst_lock); -+ -+ init_completion(&hdmirx_dev->cr_write_done); -+ init_completion(&hdmirx_dev->timer_base_lock); -+ init_completion(&hdmirx_dev->avi_pkt_rcv); -+ -+ INIT_WORK(&hdmirx_dev->work_wdt_config, hdmirx_work_wdt_config); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_hotplug, -+ hdmirx_delayed_work_hotplug); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_res_change, -+ hdmirx_delayed_work_res_change); -+ INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_heartbeat, -+ hdmirx_delayed_work_heartbeat); -+ -+ hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24; -+ hdmirx_dev->timings = cea640x480; -+ -+ hdmirx_enable(dev); -+ hdmirx_init(hdmirx_dev); -+ -+ v4l2_dev = &hdmirx_dev->v4l2_dev; -+ strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name)); -+ -+ hdl = &hdmirx_dev->hdl; -+ v4l2_ctrl_handler_init(hdl, 1); -+ -+ hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, -+ V4L2_CID_DV_RX_POWER_PRESENT, -+ 0, 1, 0, 0); -+ -+ hdmirx_dev->rgb_range = v4l2_ctrl_new_std_menu(hdl, 0, -+ V4L2_CID_DV_RX_RGB_RANGE, -+ V4L2_DV_RGB_RANGE_FULL, 0, -+ V4L2_DV_RGB_RANGE_AUTO); -+ -+ hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY; -+ -+ if (hdl->error) { -+ dev_err(dev, "v4l2 ctrl handler init failed\n"); -+ ret = hdl->error; -+ goto err_pm; -+ } -+ hdmirx_dev->v4l2_dev.ctrl_handler = hdl; -+ -+ ret = v4l2_device_register(dev, &hdmirx_dev->v4l2_dev); -+ if (ret < 0) { -+ dev_err(dev, "register v4l2 device failed\n"); -+ goto err_hdl; -+ } -+ -+ stream = &hdmirx_dev->stream; -+ stream->hdmirx_dev = hdmirx_dev; -+ ret = hdmirx_register_stream_vdev(stream); -+ if (ret < 0) { -+ dev_err(dev, "register video device failed\n"); -+ goto err_unreg_v4l2_dev; -+ } -+ -+ ret = hdmirx_register_cec(hdmirx_dev, pdev); -+ if (ret) -+ goto err_unreg_video_dev; -+ -+ hdmirx_load_default_edid(hdmirx_dev); -+ -+ hdmirx_enable_irq(dev); -+ -+ return 0; -+ -+err_unreg_video_dev: -+ video_unregister_device(&hdmirx_dev->stream.vdev); -+err_unreg_v4l2_dev: -+ v4l2_device_unregister(&hdmirx_dev->v4l2_dev); -+err_hdl: -+ v4l2_ctrl_handler_free(&hdmirx_dev->hdl); -+err_pm: -+ hdmirx_disable(dev); -+ -+ return ret; -+} -+ -+static void hdmirx_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct snps_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev); -+ -+ snps_hdmirx_cec_unregister(hdmirx_dev->cec); -+ cec_notifier_conn_unregister(hdmirx_dev->cec_notifier); -+ -+ hdmirx_disable_irq(dev); -+ -+ video_unregister_device(&hdmirx_dev->stream.vdev); -+ v4l2_ctrl_handler_free(&hdmirx_dev->hdl); -+ v4l2_device_unregister(&hdmirx_dev->v4l2_dev); -+ -+ hdmirx_disable(dev); -+ -+ reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets); -+ -+ of_reserved_mem_device_release(dev); -+} -+ -+static const struct of_device_id hdmirx_id[] = { -+ { .compatible = "rockchip,rk3588-hdmirx-ctrler" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, hdmirx_id); -+ -+static struct platform_driver hdmirx_driver = { -+ .probe = hdmirx_probe, -+ .remove_new = hdmirx_remove, -+ .driver = { -+ .name = "snps_hdmirx", -+ .of_match_table = hdmirx_id, -+ .pm = &snps_hdmirx_pm_ops, -+ } -+}; -+module_platform_driver(hdmirx_driver); -+ -+MODULE_DESCRIPTION("Rockchip HDMI Receiver Driver"); -+MODULE_AUTHOR("Dingxian Wen "); -+MODULE_AUTHOR("Shreeya Patel "); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h -@@ -0,0 +1,394 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Dingxian Wen -+ */ -+ -+#ifndef DW_HDMIRX_H -+#define DW_HDMIRX_H -+ -+#include -+ -+#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) -+#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) -+ -+/* SYS_GRF */ -+#define SYS_GRF_SOC_CON1 0x0304 -+#define HDMIRXPHY_SRAM_EXT_LD_DONE BIT(1) -+#define HDMIRXPHY_SRAM_BYPASS BIT(0) -+#define SYS_GRF_SOC_STATUS1 0x0384 -+#define HDMIRXPHY_SRAM_INIT_DONE BIT(10) -+#define SYS_GRF_CHIP_ID 0x0600 -+ -+/* VO1_GRF */ -+#define VO1_GRF_VO1_CON2 0x0008 -+#define HDMIRX_SDAIN_MSK BIT(2) -+#define HDMIRX_SCLIN_MSK BIT(1) -+ -+/* HDMIRX PHY */ -+#define SUP_DIG_ANA_CREGS_SUP_ANA_NC 0x004f -+ -+#define LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f -+#define LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f -+#define LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f -+#define LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f -+#define ASIC_ACK_OVRD_EN BIT(1) -+#define ASIC_ACK BIT(0) -+ -+#define LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x104a -+#define LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a -+#define LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a -+#define LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x134a -+#define FREQ_TUNE_START_VAL_MASK GENMASK(9, 0) -+#define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0) -+ -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG 0x20c4 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM 0x20c7 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG 0x20e9 -+#define CDR_SETTING_BOUNDARY_3_DEFAULT 0x52da -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG 0x20ea -+#define CDR_SETTING_BOUNDARY_4_DEFAULT 0x43cd -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG 0x20eb -+#define CDR_SETTING_BOUNDARY_5_DEFAULT 0x35b3 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG 0x20fb -+#define CDR_SETTING_BOUNDARY_6_DEFAULT 0x2799 -+#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG 0x20fc -+#define CDR_SETTING_BOUNDARY_7_DEFAULT 0x1b65 -+ -+#define RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e -+#define RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e -+#define RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e -+#define RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e -+#define PCS_ACK_WRITE_SELECT BIT(14) -+#define PCS_EN_CTL BIT(1) -+#define PCS_ACK BIT(0) -+ -+#define RAWLANE0_DIG_AON_FAST_FLAGS 0x305c -+#define RAWLANE1_DIG_AON_FAST_FLAGS 0x315c -+#define RAWLANE2_DIG_AON_FAST_FLAGS 0x325c -+#define RAWLANE3_DIG_AON_FAST_FLAGS 0x335c -+ -+/* HDMIRX Ctrler */ -+#define GLOBAL_SWRESET_REQUEST 0x0020 -+#define DATAPATH_SWRESETREQ BIT(12) -+#define GLOBAL_SWENABLE 0x0024 -+#define PHYCTRL_ENABLE BIT(21) -+#define CEC_ENABLE BIT(16) -+#define TMDS_ENABLE BIT(13) -+#define DATAPATH_ENABLE BIT(12) -+#define PKTFIFO_ENABLE BIT(11) -+#define AVPUNIT_ENABLE BIT(8) -+#define MAIN_ENABLE BIT(0) -+#define GLOBAL_TIMER_REF_BASE 0x0028 -+#define CORE_CONFIG 0x0050 -+#define CMU_CONFIG0 0x0060 -+#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK GENMASK(30, 16) -+#define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16) -+#define AUDCLK_STABLE_FREQ_MARGIN_MASK GENMASK(11, 9) -+#define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9) -+#define CMU_STATUS 0x007c -+#define TMDSQPCLK_LOCKED_ST BIT(4) -+#define CMU_TMDSQPCLK_FREQ 0x0084 -+#define PHY_CONFIG 0x00c0 -+#define LDO_AFE_PROG_MASK GENMASK(24, 23) -+#define LDO_AFE_PROG(x) UPDATE(x, 24, 23) -+#define LDO_PWRDN BIT(21) -+#define TMDS_CLOCK_RATIO BIT(16) -+#define RXDATA_WIDTH BIT(15) -+#define REFFREQ_SEL_MASK GENMASK(11, 9) -+#define REFFREQ_SEL(x) UPDATE(x, 11, 9) -+#define HDMI_DISABLE BIT(8) -+#define PHY_PDDQ BIT(1) -+#define PHY_RESET BIT(0) -+#define PHY_STATUS 0x00c8 -+#define HDMI_DISABLE_ACK BIT(1) -+#define PDDQ_ACK BIT(0) -+#define PHYCREG_CONFIG0 0x00e0 -+#define PHYCREG_CR_PARA_SELECTION_MODE_MASK GENMASK(1, 0) -+#define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0) -+#define PHYCREG_CONFIG1 0x00e4 -+#define PHYCREG_CONFIG2 0x00e8 -+#define PHYCREG_CONFIG3 0x00ec -+#define PHYCREG_CONTROL 0x00f0 -+#define PHYCREG_CR_PARA_WRITE_P BIT(1) -+#define PHYCREG_CR_PARA_READ_P BIT(0) -+#define PHYCREG_STATUS 0x00f4 -+ -+#define MAINUNIT_STATUS 0x0150 -+#define TMDSVALID_STABLE_ST BIT(1) -+#define DESCRAND_EN_CONTROL 0x0210 -+#define SCRAMB_EN_SEL_QST_MASK GENMASK(1, 0) -+#define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0) -+#define DESCRAND_SYNC_CONTROL 0x0214 -+#define RECOVER_UNSYNC_STREAM_QST BIT(0) -+#define DESCRAND_SYNC_SEQ_CONFIG 0x022c -+#define DESCRAND_SYNC_SEQ_ERR_CNT_EN BIT(0) -+#define DESCRAND_SYNC_SEQ_STATUS 0x0234 -+#define DEFRAMER_CONFIG0 0x0270 -+#define VS_CNT_THR_QST_MASK GENMASK(27, 20) -+#define VS_CNT_THR_QST(x) UPDATE(x, 27, 20) -+#define HS_POL_QST_MASK GENMASK(19, 18) -+#define HS_POL_QST(x) UPDATE(x, 19, 18) -+#define VS_POL_QST_MASK GENMASK(17, 16) -+#define VS_POL_QST(x) UPDATE(x, 17, 16) -+#define VS_REMAPFILTER_EN_QST BIT(8) -+#define VS_FILTER_ORDER_QST_MASK GENMASK(1, 0) -+#define VS_FILTER_ORDER_QST(x) UPDATE(x, 1, 0) -+#define DEFRAMER_VSYNC_CNT_CLEAR 0x0278 -+#define VSYNC_CNT_CLR_P BIT(0) -+#define DEFRAMER_STATUS 0x027c -+#define OPMODE_STS_MASK GENMASK(6, 4) -+#define I2C_SLAVE_CONFIG1 0x0164 -+#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK GENMASK(15, 8) -+#define I2C_SDA_OUT_HOLD_VALUE_QST(x) UPDATE(x, 15, 8) -+#define I2C_SDA_IN_HOLD_VALUE_QST_MASK GENMASK(7, 0) -+#define I2C_SDA_IN_HOLD_VALUE_QST(x) UPDATE(x, 7, 0) -+#define OPMODE_STS_MASK GENMASK(6, 4) -+#define REPEATER_QST BIT(28) -+#define FASTREAUTH_QST BIT(27) -+#define FEATURES_1DOT1_QST BIT(26) -+#define FASTI2C_QST BIT(25) -+#define EESS_CTL_THR_QST_MASK GENMASK(19, 16) -+#define EESS_CTL_THR_QST(x) UPDATE(x, 19, 16) -+#define OESS_CTL3_THR_QST_MASK GENMASK(11, 8) -+#define OESS_CTL3_THR_QST(x) UPDATE(x, 11, 8) -+#define EESS_OESS_SEL_QST_MASK GENMASK(5, 4) -+#define EESS_OESS_SEL_QST(x) UPDATE(x, 5, 4) -+#define KEY_DECRYPT_EN_QST BIT(0) -+#define KEY_DECRYPT_SEED_QST_MASK GENMASK(15, 0) -+#define KEY_DECRYPT_SEED_QST(x) UPDATE(x, 15, 0) -+#define HDCP_INT_CLEAR 0x50d8 -+#define HDCP_1_INT_CLEAR 0x50e8 -+#define HDCP2_CONFIG 0x02f0 -+#define HDCP2_SWITCH_OVR_VALUE BIT(2) -+#define HDCP2_SWITCH_OVR_EN BIT(1) -+ -+#define VIDEO_CONFIG2 0x042c -+#define VPROC_VSYNC_POL_OVR_VALUE BIT(19) -+#define VPROC_VSYNC_POL_OVR_EN BIT(18) -+#define VPROC_HSYNC_POL_OVR_VALUE BIT(17) -+#define VPROC_HSYNC_POL_OVR_EN BIT(16) -+#define VPROC_FMT_OVR_VALUE_MASK GENMASK(6, 4) -+#define VPROC_FMT_OVR_VALUE(x) UPDATE(x, 6, 4) -+#define VPROC_FMT_OVR_EN BIT(0) -+ -+#define AFIFO_FILL_RESTART BIT(0) -+#define AFIFO_INIT_P BIT(0) -+#define AFIFO_THR_LOW_QST_MASK GENMASK(25, 16) -+#define AFIFO_THR_LOW_QST(x) UPDATE(x, 25, 16) -+#define AFIFO_THR_HIGH_QST_MASK GENMASK(9, 0) -+#define AFIFO_THR_HIGH_QST(x) UPDATE(x, 9, 0) -+#define AFIFO_THR_MUTE_LOW_QST_MASK GENMASK(25, 16) -+#define AFIFO_THR_MUTE_LOW_QST(x) UPDATE(x, 25, 16) -+#define AFIFO_THR_MUTE_HIGH_QST_MASK GENMASK(9, 0) -+#define AFIFO_THR_MUTE_HIGH_QST(x) UPDATE(x, 9, 0) -+ -+#define AFIFO_UNDERFLOW_ST BIT(25) -+#define AFIFO_OVERFLOW_ST BIT(24) -+ -+#define SPEAKER_ALLOC_OVR_EN BIT(16) -+#define I2S_BPCUV_EN BIT(4) -+#define SPDIF_EN BIT(2) -+#define I2S_EN BIT(1) -+#define AFIFO_THR_PASS_DEMUTEMASK_N BIT(24) -+#define AVMUTE_DEMUTEMASK_N BIT(16) -+#define AFIFO_THR_MUTE_LOW_MUTEMASK_N BIT(9) -+#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N BIT(8) -+#define AVMUTE_MUTEMASK_N BIT(0) -+#define SCDC_CONFIG 0x0580 -+#define HPDLOW BIT(1) -+#define POWERPROVIDED BIT(0) -+#define SCDC_REGBANK_STATUS1 0x058c -+#define SCDC_TMDSBITCLKRATIO BIT(1) -+#define SCDC_REGBANK_STATUS3 0x0594 -+#define SCDC_REGBANK_CONFIG0 0x05c0 -+#define SCDC_SINKVERSION_QST_MASK GENMASK(7, 0) -+#define SCDC_SINKVERSION_QST(x) UPDATE(x, 7, 0) -+#define AGEN_LAYOUT BIT(4) -+#define AGEN_SPEAKER_ALLOC GENMASK(15, 8) -+ -+#define CED_CONFIG 0x0760 -+#define CED_VIDDATACHECKEN_QST BIT(27) -+#define CED_DATAISCHECKEN_QST BIT(26) -+#define CED_GBCHECKEN_QST BIT(25) -+#define CED_CTRLCHECKEN_QST BIT(24) -+#define CED_CHLOCKMAXER_QST_MASK GENMASK(14, 0) -+#define CED_CHLOCKMAXER_QST(x) UPDATE(x, 14, 0) -+#define CED_DYN_CONFIG 0x0768 -+#define CED_DYN_CONTROL 0x076c -+#define PKTEX_BCH_ERRFILT_CONFIG 0x07c4 -+#define PKTEX_CHKSUM_ERRFILT_CONFIG 0x07c8 -+ -+#define PKTDEC_ACR_PH2_1 0x1100 -+#define PKTDEC_ACR_PB3_0 0x1104 -+#define PKTDEC_ACR_PB7_4 0x1108 -+#define PKTDEC_AVIIF_PH2_1 0x1200 -+#define PKTDEC_AVIIF_PB3_0 0x1204 -+#define PKTDEC_AVIIF_PB7_4 0x1208 -+#define VIC_VAL_MASK GENMASK(6, 0) -+#define PKTDEC_AVIIF_PB11_8 0x120c -+#define PKTDEC_AVIIF_PB15_12 0x1210 -+#define PKTDEC_AVIIF_PB19_16 0x1214 -+#define PKTDEC_AVIIF_PB23_20 0x1218 -+#define PKTDEC_AVIIF_PB27_24 0x121c -+ -+#define PKTFIFO_CONFIG 0x1500 -+#define PKTFIFO_STORE_FILT_CONFIG 0x1504 -+#define PKTFIFO_THR_CONFIG0 0x1508 -+#define PKTFIFO_THR_CONFIG1 0x150c -+#define PKTFIFO_CONTROL 0x1510 -+ -+#define VMON_STATUS1 0x1580 -+#define VMON_STATUS2 0x1584 -+#define VMON_STATUS3 0x1588 -+#define VMON_STATUS4 0x158c -+#define VMON_STATUS5 0x1590 -+#define VMON_STATUS6 0x1594 -+#define VMON_STATUS7 0x1598 -+#define VMON_ILACE_DETECT BIT(4) -+ -+#define CEC_TX_CONTROL 0x2000 -+#define CEC_STATUS 0x2004 -+#define CEC_CONFIG 0x2008 -+#define RX_AUTO_DRIVE_ACKNOWLEDGE BIT(9) -+#define CEC_ADDR 0x200c -+#define CEC_TX_COUNT 0x2020 -+#define CEC_TX_DATA3_0 0x2024 -+#define CEC_RX_COUNT_STATUS 0x2040 -+#define CEC_RX_DATA3_0 0x2044 -+#define CEC_LOCK_CONTROL 0x2054 -+#define CEC_RXQUAL_BITTIME_CONFIG 0x2060 -+#define CEC_RX_BITTIME_CONFIG 0x2064 -+#define CEC_TX_BITTIME_CONFIG 0x2068 -+ -+#define DMA_CONFIG1 0x4400 -+#define UV_WID_MASK GENMASK(31, 28) -+#define UV_WID(x) UPDATE(x, 31, 28) -+#define Y_WID_MASK GENMASK(27, 24) -+#define Y_WID(x) UPDATE(x, 27, 24) -+#define DDR_STORE_FORMAT_MASK GENMASK(15, 12) -+#define DDR_STORE_FORMAT(x) UPDATE(x, 15, 12) -+#define ABANDON_EN BIT(0) -+#define DMA_CONFIG2 0x4404 -+#define DMA_CONFIG3 0x4408 -+#define DMA_CONFIG4 0x440c // dma irq en -+#define DMA_CONFIG5 0x4410 // dma irq clear status -+#define LINE_FLAG_INT_EN BIT(8) -+#define HDMIRX_DMA_IDLE_INT BIT(7) -+#define HDMIRX_LOCK_DISABLE_INT BIT(6) -+#define LAST_FRAME_AXI_UNFINISH_INT_EN BIT(5) -+#define FIFO_OVERFLOW_INT_EN BIT(2) -+#define FIFO_UNDERFLOW_INT_EN BIT(1) -+#define HDMIRX_AXI_ERROR_INT_EN BIT(0) -+#define DMA_CONFIG6 0x4414 -+#define RB_SWAP_EN BIT(9) -+#define HSYNC_TOGGLE_EN BIT(5) -+#define VSYNC_TOGGLE_EN BIT(4) -+#define HDMIRX_DMA_EN BIT(1) -+#define DMA_CONFIG7 0x4418 -+#define LINE_FLAG_NUM_MASK GENMASK(31, 16) -+#define LINE_FLAG_NUM(x) UPDATE(x, 31, 16) -+#define LOCK_FRAME_NUM_MASK GENMASK(11, 0) -+#define LOCK_FRAME_NUM(x) UPDATE(x, 11, 0) -+#define DMA_CONFIG8 0x441c -+#define REG_MIRROR_EN BIT(0) -+#define DMA_CONFIG9 0x4420 -+#define DMA_CONFIG10 0x4424 -+#define DMA_CONFIG11 0x4428 -+#define EDID_READ_EN_MASK BIT(8) -+#define EDID_READ_EN(x) UPDATE(x, 8, 8) -+#define EDID_WRITE_EN_MASK BIT(7) -+#define EDID_WRITE_EN(x) UPDATE(x, 7, 7) -+#define EDID_SLAVE_ADDR_MASK GENMASK(6, 0) -+#define EDID_SLAVE_ADDR(x) UPDATE(x, 6, 0) -+#define DMA_STATUS1 0x4430 // dma irq status -+#define DMA_STATUS2 0x4434 -+#define DMA_STATUS3 0x4438 -+#define DMA_STATUS4 0x443c -+#define DMA_STATUS5 0x4440 -+#define DMA_STATUS6 0x4444 -+#define DMA_STATUS7 0x4448 -+#define DMA_STATUS8 0x444c -+#define DMA_STATUS9 0x4450 -+#define DMA_STATUS10 0x4454 -+#define HDMIRX_LOCK BIT(3) -+#define DMA_STATUS11 0x4458 -+#define HDMIRX_TYPE_MASK GENMASK(8, 7) -+#define HDMIRX_COLOR_DEPTH_MASK GENMASK(6, 3) -+#define HDMIRX_FORMAT_MASK GENMASK(2, 0) -+#define DMA_STATUS12 0x445c -+#define DMA_STATUS13 0x4460 -+#define DMA_STATUS14 0x4464 -+ -+#define MAINUNIT_INTVEC_INDEX 0x5000 -+#define MAINUNIT_0_INT_STATUS 0x5010 -+#define CECRX_NOTIFY_ERR BIT(12) -+#define CECRX_EOM BIT(11) -+#define CECTX_DRIVE_ERR BIT(10) -+#define CECRX_BUSY BIT(9) -+#define CECTX_BUSY BIT(8) -+#define CECTX_FRAME_DISCARDED BIT(5) -+#define CECTX_NRETRANSMIT_FAIL BIT(4) -+#define CECTX_LINE_ERR BIT(3) -+#define CECTX_ARBLOST BIT(2) -+#define CECTX_NACK BIT(1) -+#define CECTX_DONE BIT(0) -+#define MAINUNIT_0_INT_MASK_N 0x5014 -+#define MAINUNIT_0_INT_CLEAR 0x5018 -+#define MAINUNIT_0_INT_FORCE 0x501c -+#define TIMER_BASE_LOCKED_IRQ BIT(26) -+#define TMDSQPCLK_OFF_CHG BIT(5) -+#define TMDSQPCLK_LOCKED_CHG BIT(4) -+#define MAINUNIT_1_INT_STATUS 0x5020 -+#define MAINUNIT_1_INT_MASK_N 0x5024 -+#define MAINUNIT_1_INT_CLEAR 0x5028 -+#define MAINUNIT_1_INT_FORCE 0x502c -+#define MAINUNIT_2_INT_STATUS 0x5030 -+#define MAINUNIT_2_INT_MASK_N 0x5034 -+#define MAINUNIT_2_INT_CLEAR 0x5038 -+#define MAINUNIT_2_INT_FORCE 0x503c -+#define PHYCREG_CR_READ_DONE BIT(11) -+#define PHYCREG_CR_WRITE_DONE BIT(10) -+#define TMDSVALID_STABLE_CHG BIT(1) -+ -+#define AVPUNIT_0_INT_STATUS 0x5040 -+#define AVPUNIT_0_INT_MASK_N 0x5044 -+#define AVPUNIT_0_INT_CLEAR 0x5048 -+#define AVPUNIT_0_INT_FORCE 0x504c -+#define CED_DYN_CNT_CH2_IRQ BIT(22) -+#define CED_DYN_CNT_CH1_IRQ BIT(21) -+#define CED_DYN_CNT_CH0_IRQ BIT(20) -+#define AVPUNIT_1_INT_STATUS 0x5050 -+#define DEFRAMER_VSYNC_THR_REACHED_IRQ BIT(1) -+#define AVPUNIT_1_INT_MASK_N 0x5054 -+#define DEFRAMER_VSYNC_THR_REACHED_MASK_N BIT(1) -+#define DEFRAMER_VSYNC_MASK_N BIT(0) -+#define AVPUNIT_1_INT_CLEAR 0x5058 -+#define DEFRAMER_VSYNC_THR_REACHED_CLEAR BIT(1) -+#define PKT_0_INT_STATUS 0x5080 -+#define PKTDEC_ACR_CHG_IRQ BIT(3) -+#define PKT_0_INT_MASK_N 0x5084 -+#define PKTDEC_ACR_CHG_MASK_N BIT(3) -+#define PKT_0_INT_CLEAR 0x5088 -+#define PKT_1_INT_STATUS 0x5090 -+#define PKT_1_INT_MASK_N 0x5094 -+#define PKT_1_INT_CLEAR 0x5098 -+#define PKT_2_INT_STATUS 0x50a0 -+#define PKTDEC_ACR_RCV_IRQ BIT(3) -+#define PKT_2_INT_MASK_N 0x50a4 -+#define PKTDEC_AVIIF_RCV_IRQ BIT(11) -+#define PKTDEC_ACR_RCV_MASK_N BIT(3) -+#define PKT_2_INT_CLEAR 0x50a8 -+#define PKTDEC_AVIIF_RCV_CLEAR BIT(11) -+#define PKTDEC_ACR_RCV_CLEAR BIT(3) -+#define SCDC_INT_STATUS 0x50c0 -+#define SCDC_INT_MASK_N 0x50c4 -+#define SCDC_INT_CLEAR 0x50c8 -+#define SCDCTMDSCCFG_CHG BIT(2) -+ -+#define CEC_INT_STATUS 0x5100 -+#define CEC_INT_MASK_N 0x5104 -+#define CEC_INT_CLEAR 0x5108 -+ -+#endif -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.c -@@ -0,0 +1,285 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Shunqing Chen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "snps_hdmirx.h" -+#include "snps_hdmirx_cec.h" -+ -+static void hdmirx_cec_write(struct hdmirx_cec *cec, int reg, u32 val) -+{ -+ cec->ops->write(cec->hdmirx, reg, val); -+} -+ -+static u32 hdmirx_cec_read(struct hdmirx_cec *cec, int reg) -+{ -+ return cec->ops->read(cec->hdmirx, reg); -+} -+ -+static void hdmirx_cec_update_bits(struct hdmirx_cec *cec, int reg, u32 mask, -+ u32 data) -+{ -+ u32 val = hdmirx_cec_read(cec, reg) & ~mask; -+ -+ val |= (data & mask); -+ hdmirx_cec_write(cec, reg, val); -+} -+ -+static int hdmirx_cec_log_addr(struct cec_adapter *adap, u8 logical_addr) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (logical_addr == CEC_LOG_ADDR_INVALID) -+ cec->addresses = 0; -+ else -+ cec->addresses |= BIT(logical_addr) | BIT(15); -+ -+ hdmirx_cec_write(cec, CEC_ADDR, cec->addresses); -+ -+ return 0; -+} -+ -+/* signal_free_time is handled by the Synopsys Designware -+ * HDMIRX Controller hardware. -+ */ -+static int hdmirx_cec_transmit(struct cec_adapter *adap, u8 attempts, -+ u32 signal_free_time, struct cec_msg *msg) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ u32 data[4] = {0}; -+ int i, data_len, msg_len; -+ -+ msg_len = msg->len; -+ -+ hdmirx_cec_write(cec, CEC_TX_COUNT, msg_len - 1); -+ for (i = 0; i < msg_len; i++) -+ data[i / 4] |= msg->msg[i] << (i % 4) * 8; -+ -+ data_len = DIV_ROUND_UP(msg_len, 4); -+ -+ for (i = 0; i < data_len; i++) -+ hdmirx_cec_write(cec, CEC_TX_DATA3_0 + i * 4, data[i]); -+ -+ hdmirx_cec_write(cec, CEC_TX_CONTROL, 0x1); -+ -+ return 0; -+} -+ -+static irqreturn_t hdmirx_cec_hardirq(int irq, void *data) -+{ -+ struct cec_adapter *adap = data; -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ u32 stat = hdmirx_cec_read(cec, CEC_INT_STATUS); -+ irqreturn_t ret = IRQ_HANDLED; -+ u32 val; -+ -+ if (!stat) -+ return IRQ_NONE; -+ -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, stat); -+ -+ if (stat & CECTX_LINE_ERR) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_DONE) { -+ cec->tx_status = CEC_TX_STATUS_OK; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_NACK) { -+ cec->tx_status = CEC_TX_STATUS_NACK; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } else if (stat & CECTX_ARBLOST) { -+ cec->tx_status = CEC_TX_STATUS_ARB_LOST; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; -+ } -+ -+ if (stat & CECRX_EOM) { -+ unsigned int len, i; -+ -+ val = hdmirx_cec_read(cec, CEC_RX_COUNT_STATUS); -+ /* rxbuffer locked status */ -+ if ((val & 0x80)) -+ return ret; -+ -+ len = (val & 0xf) + 1; -+ if (len > sizeof(cec->rx_msg.msg)) -+ len = sizeof(cec->rx_msg.msg); -+ -+ for (i = 0; i < len; i++) { -+ if (!(i % 4)) -+ val = hdmirx_cec_read(cec, CEC_RX_DATA3_0 + i / 4 * 4); -+ cec->rx_msg.msg[i] = (val >> ((i % 4) * 8)) & 0xff; -+ } -+ -+ cec->rx_msg.len = len; -+ smp_wmb(); /* receive RX msg */ -+ cec->rx_done = true; -+ hdmirx_cec_write(cec, CEC_LOCK_CONTROL, 0x1); -+ -+ ret = IRQ_WAKE_THREAD; -+ } -+ -+ return ret; -+} -+ -+static irqreturn_t hdmirx_cec_thread(int irq, void *data) -+{ -+ struct cec_adapter *adap = data; -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (cec->tx_done) { -+ cec->tx_done = false; -+ cec_transmit_attempt_done(adap, cec->tx_status); -+ } -+ if (cec->rx_done) { -+ cec->rx_done = false; -+ smp_rmb(); /* RX msg has been received */ -+ cec_received_msg(adap, &cec->rx_msg); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int hdmirx_cec_enable(struct cec_adapter *adap, bool enable) -+{ -+ struct hdmirx_cec *cec = cec_get_drvdata(adap); -+ -+ if (!enable) { -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, 0); -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, 0); -+ if (cec->ops->disable) -+ cec->ops->disable(cec->hdmirx); -+ } else { -+ unsigned int irqs; -+ -+ hdmirx_cec_log_addr(cec->adap, CEC_LOG_ADDR_INVALID); -+ if (cec->ops->enable) -+ cec->ops->enable(cec->hdmirx); -+ hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE); -+ -+ irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE; -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs); -+ } -+ -+ return 0; -+} -+ -+static const struct cec_adap_ops hdmirx_cec_ops = { -+ .adap_enable = hdmirx_cec_enable, -+ .adap_log_addr = hdmirx_cec_log_addr, -+ .adap_transmit = hdmirx_cec_transmit, -+}; -+ -+static void hdmirx_cec_del(void *data) -+{ -+ struct hdmirx_cec *cec = data; -+ -+ cec_delete_adapter(cec->adap); -+} -+ -+struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data) -+{ -+ struct hdmirx_cec *cec; -+ unsigned int irqs; -+ int ret; -+ -+ /* -+ * Our device is just a convenience - we want to link to the real -+ * hardware device here, so that userspace can see the association -+ * between the HDMI hardware and its associated CEC chardev. -+ */ -+ cec = devm_kzalloc(data->dev, sizeof(*cec), GFP_KERNEL); -+ if (!cec) -+ return NULL; -+ -+ cec->dev = data->dev; -+ cec->irq = data->irq; -+ cec->ops = data->ops; -+ cec->hdmirx = data->hdmirx; -+ -+ hdmirx_cec_update_bits(cec, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE); -+ hdmirx_cec_update_bits(cec, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE, -+ RX_AUTO_DRIVE_ACKNOWLEDGE); -+ -+ hdmirx_cec_write(cec, CEC_TX_COUNT, 0); -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, 0); -+ hdmirx_cec_write(cec, CEC_INT_CLEAR, ~0); -+ -+ cec->adap = cec_allocate_adapter(&hdmirx_cec_ops, cec, "snps-hdmirx", -+ CEC_CAP_LOG_ADDRS | CEC_CAP_TRANSMIT | -+ CEC_CAP_RC | CEC_CAP_PASSTHROUGH | -+ CEC_CAP_MONITOR_ALL, -+ CEC_MAX_LOG_ADDRS); -+ if (IS_ERR(cec->adap)) { -+ dev_err(cec->dev, "cec adap allocate failed\n"); -+ return NULL; -+ } -+ -+ /* override the module pointer */ -+ cec->adap->owner = THIS_MODULE; -+ -+ ret = devm_add_action(cec->dev, hdmirx_cec_del, cec); -+ if (ret) { -+ cec_delete_adapter(cec->adap); -+ return NULL; -+ } -+ -+ irq_set_status_flags(cec->irq, IRQ_NOAUTOEN); -+ -+ ret = devm_request_threaded_irq(cec->dev, cec->irq, -+ hdmirx_cec_hardirq, -+ hdmirx_cec_thread, IRQF_ONESHOT, -+ "rk_hdmirx_cec", cec->adap); -+ if (ret) { -+ dev_err(cec->dev, "cec irq request failed\n"); -+ return NULL; -+ } -+ -+ cec->notify = cec_notifier_cec_adap_register(cec->dev, -+ NULL, cec->adap); -+ if (!cec->notify) { -+ dev_err(cec->dev, "cec notify register failed\n"); -+ return NULL; -+ } -+ -+ ret = cec_register_adapter(cec->adap, cec->dev); -+ if (ret < 0) { -+ dev_err(cec->dev, "cec register adapter failed\n"); -+ cec_unregister_adapter(cec->adap); -+ return NULL; -+ } -+ -+ irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE; -+ hdmirx_cec_write(cec, CEC_INT_MASK_N, irqs); -+ -+ /* -+ * CEC documentation says we must not call cec_delete_adapter -+ * after a successful call to cec_register_adapter(). -+ */ -+ devm_remove_action(cec->dev, hdmirx_cec_del, cec); -+ -+ enable_irq(cec->irq); -+ -+ return cec; -+} -+ -+void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec) -+{ -+ disable_irq(cec->irq); -+ -+ cec_unregister_adapter(cec->adap); -+} -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx_cec.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. -+ * -+ * Author: Shunqing Chen -+ */ -+ -+#ifndef DW_HDMI_RX_CEC_H -+#define DW_HDMI_RX_CEC_H -+ -+struct snps_hdmirx_dev; -+ -+struct hdmirx_cec_ops { -+ void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val); -+ u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg); -+ void (*enable)(struct snps_hdmirx_dev *hdmirx); -+ void (*disable)(struct snps_hdmirx_dev *hdmirx); -+}; -+ -+struct hdmirx_cec_data { -+ struct snps_hdmirx_dev *hdmirx; -+ const struct hdmirx_cec_ops *ops; -+ struct device *dev; -+ int irq; -+}; -+ -+struct hdmirx_cec { -+ struct snps_hdmirx_dev *hdmirx; -+ struct device *dev; -+ const struct hdmirx_cec_ops *ops; -+ u32 addresses; -+ struct cec_adapter *adap; -+ struct cec_msg rx_msg; -+ unsigned int tx_status; -+ bool tx_done; -+ bool rx_done; -+ struct cec_notifier *notify; -+ int irq; -+}; -+ -+struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data); -+void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec); -+ -+#endif /* DW_HDMI_RX_CEC_H */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 1 Aug 2024 16:47:35 +0300 -Subject: comment v4l2 error on hdmirx - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -1180,7 +1180,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - break; - - if (!tx_5v_power_present(hdmirx_dev)) { -- v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); -+ //v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); - return -1; - } - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Sun, 15 Sep 2024 14:52:17 -0400 -Subject: [PATCH 1/2] fix spurious triggering of irq 5v while plugout code is - running - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -745,10 +745,17 @@ static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en) - static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) - { - struct arm_smccc_res res; -+ int irq; - - hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0); - hdmirx_interrupts_setup(hdmirx_dev, false); - hdmirx_hpd_ctrl(hdmirx_dev, false); -+ irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio); -+ -+ if (irq >= 0) { -+ disable_irq(irq); -+ } -+ - hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); - hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, - LINE_FLAG_INT_EN | -@@ -766,6 +773,11 @@ static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) - cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); - flush_work(&hdmirx_dev->work_wdt_config); - arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); -+ -+ hdmirx_hpd_ctrl(hdmirx_dev, true); -+ if (irq >= 0) { -+ enable_irq(irq); -+ } - } - - static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid) --- -Armbian - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Sun, 15 Sep 2024 14:53:25 -0400 -Subject: [PATCH 2/2] remove timing handling from plug in function - ---- - drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 7 ------- - 1 file changed, 7 deletions(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -2202,13 +2202,6 @@ static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev) - hdmirx_hpd_ctrl(hdmirx_dev, true); - hdmirx_phy_config(hdmirx_dev); - ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev); -- if (ret) { -- hdmirx_plugout(hdmirx_dev); -- queue_delayed_work(system_unbound_wq, -- &hdmirx_dev->delayed_work_hotplug, -- msecs_to_jiffies(200)); -- return; -- } - hdmirx_dma_config(hdmirx_dev); - hdmirx_interrupts_setup(hdmirx_dev, true); - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ben Hoff -Date: Mon, 23 Sep 2024 09:43:38 -0400 -Subject: [PATCH] expose itc type to v4l2 in synopsys hdmir rx - ---- - .../media/platform/synopsys/hdmirx/snps_hdmirx.c | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -+++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c -@@ -151,6 +151,7 @@ struct snps_hdmirx_dev { - struct v4l2_ctrl_handler hdl; - struct v4l2_ctrl *detect_tx_5v_ctrl; - struct v4l2_ctrl *rgb_range; -+ struct v4l2_ctrl *content_type; - struct v4l2_dv_timings timings; - struct gpio_desc *detect_5v_gpio; - struct work_struct work_wdt_config; -@@ -512,6 +513,11 @@ static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev) - } - - v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range); -+ if (frame.avi.itc) { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, frame.avi.content_type); -+ } else { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); -+ } - } - - /* -@@ -1192,6 +1198,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - break; - - if (!tx_5v_power_present(hdmirx_dev)) { -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); - //v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); - return -1; - } -@@ -1204,6 +1211,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) - __func__, hdmirx_dev->tmds_clk_ratio); - v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n", - __func__, mu_status, scdc_status, dma_st10); -+ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); - return -1; - } - -@@ -2668,7 +2676,7 @@ static int hdmirx_probe(struct platform_device *pdev) - strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name)); - - hdl = &hdmirx_dev->hdl; -- v4l2_ctrl_handler_init(hdl, 1); -+ v4l2_ctrl_handler_init(hdl, 3); - - hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, - V4L2_CID_DV_RX_POWER_PRESENT, -@@ -2681,6 +2689,12 @@ static int hdmirx_probe(struct platform_device *pdev) - - hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY; - -+ hdmirx_dev->content_type = v4l2_ctrl_new_std_menu(hdl, NULL, -+ V4L2_CID_DV_RX_IT_CONTENT_TYPE, -+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC, -+ 0, -+ V4L2_DV_IT_CONTENT_TYPE_NO_ITC); -+ - if (hdl->error) { - dev_err(dev, "v4l2 ctrl handler init failed\n"); - ret = hdl->error; --- -Armbian diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch deleted file mode 100644 index 0e5c748d021a..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 15 Jan 2024 22:47:41 +0200 -Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588 - -Add DT node for the HDMI0 bridge found on RK3588 SoC. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 55 ++++++++++ - 1 file changed, 55 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1516,6 +1516,61 @@ i2s9_8ch: i2s@fddfc000 { - status = "disabled"; - }; - -+ hdmi0: hdmi@fde80000 { -+ compatible = "rockchip,rk3588-dw-hdmi"; -+ reg = <0x0 0xfde80000 0x0 0x20000>; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ clocks = <&cru PCLK_HDMITX0>, -+ <&cru CLK_HDMIHDP0>, -+ <&cru CLK_HDMITX0_EARC>, -+ <&cru CLK_HDMITX0_REF>, -+ <&cru MCLK_I2S5_8CH_TX>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>, -+ <&cru DCLK_VOP3>, -+ <&cru HCLK_VO1>; -+ clock-names = "pclk", -+ "hpd", -+ "earc", -+ "hdmitx_ref", -+ "aud", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3", -+ "hclk_vo1"; -+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; -+ reset-names = "ref", "hdp"; -+ power-domains = <&power RK3588_PD_VO1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd -+ &hdmim0_tx0_scl &hdmim0_tx0_sda>; -+ reg-io-width = <4>; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo1_grf = <&vo1_grf>; -+ phys = <&hdptxphy_hdmi0>; -+ phy-names = "hdmi"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi0_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi0_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch deleted file mode 100644 index 6013a8d65a2f..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 16 Jan 2024 03:13:38 +0200 -Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on rk3588 - -The HDMI0 PHY can be used as a clock provider on RK3588, hence add the -missing #clock-cells property. ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -2985,6 +2985,7 @@ hdptxphy_hdmi0: phy@fed60000 { - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; -+ #clock-cells = <0>; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch deleted file mode 100644 index edcf535b204f..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch +++ /dev/null @@ -1,549 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 5 Feb 2024 01:38:48 +0200 -Subject: phy: phy-rockchip-samsung-hdptx: Add FRL & EARC support - -For upstreaming, this requires extending the standard PHY API to support -HDMI configuration options [1]. - -Currently, the bus_width PHY attribute is used to pass clock rate and -flags for 10-bit color depth, FRL and EARC. This is done by the HDMI -bridge driver via phy_set_bus_width(). - -[1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/ - -Signed-off-by: Cristian Ciocaltea ---- - drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 434 +++++++++- - 1 file changed, 431 insertions(+), 3 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -@@ -190,6 +190,12 @@ - #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) - #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) - -+#define HDMI20_MAX_RATE 600000000 -+#define DATA_RATE_MASK 0xFFFFFFF -+#define COLOR_DEPTH_MASK BIT(31) -+#define HDMI_MODE_MASK BIT(30) -+#define HDMI_EARC_MASK BIT(29) -+ - struct lcpll_config { - u32 bit_rate; - u8 lcvco_mode_en; -@@ -272,6 +278,25 @@ struct rk_hdptx_phy { - struct clk_bulk_data *clks; - int nr_clks; - struct reset_control_bulk_data rsts[RST_MAX]; -+ bool earc_en; -+}; -+ -+static const struct lcpll_config lcpll_cfg[] = { -+ { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2, -+ 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, -+ { 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1, -+ 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, }, -+ { 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1, -+ 0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1, }, -+}; -+ -+static const struct ropll_config ropll_frl_cfg[] = { -+ { 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, -+ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, -+ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, -+ { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, -+ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - }; - - static const struct ropll_config ropll_tmds_cfg[] = { -@@ -449,6 +474,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { - REG_SEQ0(CMN_REG(009b), 0x00), - }; - -+static const struct reg_sequence rk_hdtpx_frl_cmn_init_seq[] = { -+ REG_SEQ0(CMN_REG(0011), 0x00), -+ REG_SEQ0(CMN_REG(0017), 0x00), -+ REG_SEQ0(CMN_REG(0026), 0x53), -+ REG_SEQ0(CMN_REG(0030), 0x00), -+ REG_SEQ0(CMN_REG(0031), 0x20), -+ REG_SEQ0(CMN_REG(0032), 0x30), -+ REG_SEQ0(CMN_REG(0033), 0x0b), -+ REG_SEQ0(CMN_REG(0034), 0x23), -+ REG_SEQ0(CMN_REG(0042), 0xb8), -+ REG_SEQ0(CMN_REG(004e), 0x14), -+ REG_SEQ0(CMN_REG(0074), 0x00), -+ REG_SEQ0(CMN_REG(0081), 0x09), -+ REG_SEQ0(CMN_REG(0086), 0x01), -+ REG_SEQ0(CMN_REG(0087), 0x0c), -+ REG_SEQ0(CMN_REG(009b), 0x10), -+}; -+ -+static const struct reg_sequence rk_hdtpx_frl_ropll_cmn_init_seq[] = { -+ REG_SEQ0(CMN_REG(0008), 0x00), -+ REG_SEQ0(CMN_REG(001e), 0x14), -+ REG_SEQ0(CMN_REG(0020), 0x00), -+ REG_SEQ0(CMN_REG(0021), 0x00), -+ REG_SEQ0(CMN_REG(0022), 0x11), -+ REG_SEQ0(CMN_REG(0023), 0x00), -+ REG_SEQ0(CMN_REG(0025), 0x00), -+ REG_SEQ0(CMN_REG(0027), 0x00), -+ REG_SEQ0(CMN_REG(0028), 0x00), -+ REG_SEQ0(CMN_REG(002a), 0x01), -+ REG_SEQ0(CMN_REG(002b), 0x00), -+ REG_SEQ0(CMN_REG(002c), 0x00), -+ REG_SEQ0(CMN_REG(002d), 0x00), -+ REG_SEQ0(CMN_REG(002e), 0x00), -+ REG_SEQ0(CMN_REG(002f), 0x04), -+ REG_SEQ0(CMN_REG(003d), 0x40), -+ REG_SEQ0(CMN_REG(005c), 0x25), -+ REG_SEQ0(CMN_REG(0089), 0x00), -+ REG_SEQ0(CMN_REG(0094), 0x00), -+ REG_SEQ0(CMN_REG(0097), 0x02), -+ REG_SEQ0(CMN_REG(0099), 0x04), -+}; -+ -+static const struct reg_sequence rk_hdtpx_frl_lcpll_cmn_init_seq[] = { -+ REG_SEQ0(CMN_REG(0025), 0x10), -+ REG_SEQ0(CMN_REG(0027), 0x01), -+ REG_SEQ0(CMN_REG(0028), 0x0d), -+ REG_SEQ0(CMN_REG(002e), 0x02), -+ REG_SEQ0(CMN_REG(002f), 0x0d), -+ REG_SEQ0(CMN_REG(003d), 0x00), -+ REG_SEQ0(CMN_REG(0051), 0x00), -+ REG_SEQ0(CMN_REG(0055), 0x00), -+ REG_SEQ0(CMN_REG(0059), 0x11), -+ REG_SEQ0(CMN_REG(005a), 0x03), -+ REG_SEQ0(CMN_REG(005c), 0x05), -+ REG_SEQ0(CMN_REG(005e), 0x07), -+ REG_SEQ0(CMN_REG(0060), 0x01), -+ REG_SEQ0(CMN_REG(0064), 0x07), -+ REG_SEQ0(CMN_REG(0065), 0x00), -+ REG_SEQ0(CMN_REG(0069), 0x00), -+ REG_SEQ0(CMN_REG(006c), 0x00), -+ REG_SEQ0(CMN_REG(0070), 0x01), -+ REG_SEQ0(CMN_REG(0089), 0x02), -+ REG_SEQ0(CMN_REG(0095), 0x00), -+ REG_SEQ0(CMN_REG(0097), 0x00), -+ REG_SEQ0(CMN_REG(0099), 0x00), -+}; -+ - static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { - REG_SEQ0(SB_REG(0114), 0x00), - REG_SEQ0(SB_REG(0115), 0x00), -@@ -472,6 +564,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { - REG_SEQ0(LNTOP_REG(0205), 0x1f), - }; - -+static const struct reg_sequence rk_hdtpx_frl_lntop_init_seq[] = { -+ REG_SEQ0(LNTOP_REG(0200), 0x04), -+ REG_SEQ0(LNTOP_REG(0201), 0x00), -+ REG_SEQ0(LNTOP_REG(0202), 0x00), -+ REG_SEQ0(LNTOP_REG(0203), 0xf0), -+ REG_SEQ0(LNTOP_REG(0204), 0xff), -+ REG_SEQ0(LNTOP_REG(0205), 0xff), -+ REG_SEQ0(LNTOP_REG(0206), 0x05), -+ REG_SEQ0(LNTOP_REG(0207), 0x0f), -+}; -+ - static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { - REG_SEQ0(LANE_REG(0303), 0x0c), - REG_SEQ0(LANE_REG(0307), 0x20), -@@ -550,6 +653,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { - REG_SEQ0(LANE_REG(0606), 0x1c), - }; - -+static const struct reg_sequence rk_hdtpx_frl_ropll_lane_init_seq[] = { -+ REG_SEQ0(LANE_REG(0312), 0x3c), -+ REG_SEQ0(LANE_REG(0412), 0x3c), -+ REG_SEQ0(LANE_REG(0512), 0x3c), -+ REG_SEQ0(LANE_REG(0612), 0x3c), -+}; -+ -+static const struct reg_sequence rk_hdtpx_frl_lcpll_lane_init_seq[] = { -+ REG_SEQ0(LANE_REG(0312), 0x3c), -+ REG_SEQ0(LANE_REG(0412), 0x3c), -+ REG_SEQ0(LANE_REG(0512), 0x3c), -+ REG_SEQ0(LANE_REG(0612), 0x3c), -+ REG_SEQ0(LANE_REG(0303), 0x2f), -+ REG_SEQ0(LANE_REG(0403), 0x2f), -+ REG_SEQ0(LANE_REG(0503), 0x2f), -+ REG_SEQ0(LANE_REG(0603), 0x2f), -+ REG_SEQ0(LANE_REG(0305), 0x03), -+ REG_SEQ0(LANE_REG(0405), 0x03), -+ REG_SEQ0(LANE_REG(0505), 0x03), -+ REG_SEQ0(LANE_REG(0605), 0x03), -+ REG_SEQ0(LANE_REG(0306), 0xfc), -+ REG_SEQ0(LANE_REG(0406), 0xfc), -+ REG_SEQ0(LANE_REG(0506), 0xfc), -+ REG_SEQ0(LANE_REG(0606), 0xfc), -+ REG_SEQ0(LANE_REG(0305), 0x4f), -+ REG_SEQ0(LANE_REG(0405), 0x4f), -+ REG_SEQ0(LANE_REG(0505), 0x4f), -+ REG_SEQ0(LANE_REG(0605), 0x4f), -+ REG_SEQ0(LANE_REG(0304), 0x14), -+ REG_SEQ0(LANE_REG(0404), 0x14), -+ REG_SEQ0(LANE_REG(0504), 0x14), -+ REG_SEQ0(LANE_REG(0604), 0x14), -+}; -+ - static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) - { - switch (reg) { -@@ -651,6 +788,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) - return 0; - } - -+static int rk_hdptx_post_power_up(struct rk_hdptx_phy *hdptx) -+{ -+ u32 val; -+ int ret; -+ -+ val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | -+ HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+ -+ usleep_range(10, 15); -+ reset_control_deassert(hdptx->rsts[RST_INIT].rstc); -+ -+ usleep_range(10, 15); -+ val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; -+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); -+ -+ usleep_range(10, 15); -+ reset_control_deassert(hdptx->rsts[RST_CMN].rstc); -+ -+ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, -+ val & HDPTX_O_PLL_LOCK_DONE, 20, 400); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to get PHY PLL lock: %d\n", ret); -+ return ret; -+ } -+ -+ usleep_range(20, 30); -+ reset_control_deassert(hdptx->rsts[RST_LANE].rstc); -+ -+ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, -+ val & HDPTX_O_PHY_RDY, 100, 5000); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to get PHY ready: %d\n", ret); -+ return ret; -+ } -+ -+ dev_dbg(hdptx->dev, "PHY ready\n"); -+ -+ return 0; -+} -+ - static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) - { - u32 val; -@@ -680,6 +858,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) - regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); - } - -+static void rk_hdptx_earc_config(struct rk_hdptx_phy *hdptx) -+{ -+ regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RCAL_OPT_CODE_MASK, -+ FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 1)); -+ regmap_write(hdptx->regmap, SB_REG(011c), 0x04); -+ regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_AFC_TOL_MASK, -+ FIELD_PREP(SB_AFC_TOL_MASK, 3)); -+ regmap_write(hdptx->regmap, SB_REG(0109), 0x05); -+ -+ regmap_update_bits(hdptx->regmap, SB_REG(0120), -+ SB_EARC_EN_MASK | SB_EARC_AFC_EN_MASK, -+ FIELD_PREP(SB_EARC_EN_MASK, 1) | -+ FIELD_PREP(SB_EARC_AFC_EN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_EARC_SIG_DET_BYPASS_MASK, -+ FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(011f), -+ SB_PWM_AFC_CTRL_MASK | SB_RCAL_RSTN_MASK, -+ FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0xc) | -+ FIELD_PREP(SB_RCAL_RSTN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_READY_DELAY_TIME_MASK, -+ FIELD_PREP(SB_READY_DELAY_TIME_MASK, 2)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RTERM_CTRL_MASK, -+ FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 3)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK, -+ FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 3)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK, -+ FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 3)); -+ -+ regmap_write(hdptx->regmap, SB_REG(011a), 0x03); -+ regmap_write(hdptx->regmap, SB_REG(0118), 0x0a); -+ regmap_write(hdptx->regmap, SB_REG(011e), 0x6a); -+ regmap_write(hdptx->regmap, SB_REG(011d), 0x67); -+ -+ regmap_update_bits(hdptx->regmap, SB_REG(0117), FAST_PULSE_TIME_MASK, -+ FIELD_PREP(FAST_PULSE_TIME_MASK, 4)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0114), -+ SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK, -+ FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 2) | -+ FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 2)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK, -+ FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 7)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK, -+ FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 7)); -+ regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK, -+ FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0110), ANA_SB_VREG_REF_SEL_MASK, -+ FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_TG_OSC_EN_DELAY_TIME_MASK, -+ FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 2)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0116), AFC_RSTN_DELAY_TIME_MASK, -+ FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 2)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0109), ANA_SB_DMRX_AFC_DIV_RATIO_MASK, -+ FIELD_PREP(ANA_SB_DMRX_AFC_DIV_RATIO_MASK, 5)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, -+ FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK, -+ FIELD_PREP(OVRD_SB_EN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK, -+ FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0105), OVRD_SB_EARC_CMDC_EN_MASK, -+ FIELD_PREP(OVRD_SB_EARC_CMDC_EN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(010f), -+ OVRD_SB_VREG_EN_MASK | OVRD_SB_VREG_LPF_BYPASS_MASK, -+ FIELD_PREP(OVRD_SB_VREG_EN_MASK, 1) | -+ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(0123), OVRD_SB_READY_MASK, -+ FIELD_PREP(OVRD_SB_READY_MASK, 1)); -+ -+ usleep_range(1000, 1100); -+ regmap_update_bits(hdptx->regmap, SB_REG(0103), SB_RX_RESCAL_DONE_MASK, -+ FIELD_PREP(SB_RX_RESCAL_DONE_MASK, 1)); -+ usleep_range(50, 60); -+ regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK, -+ FIELD_PREP(SB_EN_MASK, 1)); -+ usleep_range(50, 60); -+ regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK, -+ FIELD_PREP(SB_RXTERM_EN_MASK, 1)); -+ usleep_range(50, 60); -+ regmap_update_bits(hdptx->regmap, SB_REG(0105), SB_EARC_CMDC_EN_MASK, -+ FIELD_PREP(SB_EARC_CMDC_EN_MASK, 1)); -+ regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK, -+ FIELD_PREP(SB_VREG_EN_MASK, 1)); -+ usleep_range(50, 60); -+ regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK, -+ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1)); -+ usleep_range(250, 300); -+ regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK, -+ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 0)); -+ usleep_range(100, 120); -+ regmap_update_bits(hdptx->regmap, SB_REG(0123), SB_READY_MASK, -+ FIELD_PREP(SB_READY_MASK, 1)); -+} -+ - static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, - struct ropll_config *cfg) - { -@@ -755,9 +1026,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, - static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) - { -+ int i, bus_width = phy_get_bus_width(hdptx->phy); -+ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; - const struct ropll_config *cfg = NULL; - struct ropll_config rc = {0}; -- int i; -+ -+ if (color_depth) -+ rate = rate * 10 / 8; - - for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate == ropll_tmds_cfg[i].bit_rate) { -@@ -813,6 +1088,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, - FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); - -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, -+ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); -+ - regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN, - PLL_PCG_CLK_EN); - -@@ -853,9 +1131,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); - -+ if (hdptx->earc_en) -+ rk_hdptx_earc_config(hdptx); -+ - return rk_hdptx_post_enable_lane(hdptx); - } - -+static int rk_hdptx_ropll_frl_mode_config(struct rk_hdptx_phy *hdptx, -+ u32 bus_width) -+{ -+ u32 bit_rate = bus_width & DATA_RATE_MASK; -+ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; -+ const struct ropll_config *cfg = NULL; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ropll_frl_cfg); i++) -+ if (bit_rate == ropll_frl_cfg[i].bit_rate) { -+ cfg = &ropll_frl_cfg[i]; -+ break; -+ } -+ -+ if (!cfg) { -+ dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); -+ return -EINVAL; -+ } -+ -+ rk_hdptx_pre_power_up(hdptx); -+ -+ reset_control_assert(hdptx->rsts[RST_ROPLL].rstc); -+ usleep_range(10, 20); -+ reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_cmn_init_seq); -+ -+ regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); -+ regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); -+ regmap_write(hdptx->regmap, CMN_REG(0059), -+ (cfg->pms_pdiv << 4) | cfg->pms_refdiv); -+ regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, -+ FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); -+ if (!cfg->sdm_en) -+ regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, -+ FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); -+ -+ regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); -+ regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, -+ FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); -+ -+ regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); -+ regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, -+ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, -+ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_lane_init_seq); -+ -+ if (hdptx->earc_en) -+ rk_hdptx_earc_config(hdptx); -+ -+ return rk_hdptx_post_power_up(hdptx); -+} -+ -+static int rk_hdptx_lcpll_frl_mode_config(struct rk_hdptx_phy *hdptx, -+ u32 bus_width) -+{ -+ u32 bit_rate = bus_width & DATA_RATE_MASK; -+ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; -+ const struct lcpll_config *cfg = NULL; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(lcpll_cfg); i++) -+ if (bit_rate == lcpll_cfg[i].bit_rate) { -+ cfg = &lcpll_cfg[i]; -+ break; -+ } -+ -+ if (!cfg) { -+ dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); -+ return -EINVAL; -+ } -+ -+ rk_hdptx_pre_power_up(hdptx); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_cmn_init_seq); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0008), -+ LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK, -+ FIELD_PREP(LCPLL_EN_MASK, 1) | -+ FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en)); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(001e), -+ LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK, -+ FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) | -+ FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m)); -+ -+ regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv); -+ regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc); -+ regmap_write(hdptx->regmap, CMN_REG(0022), -+ (cfg->pms_pdiv << 4) | cfg->pms_refdiv); -+ regmap_write(hdptx->regmap, CMN_REG(0023), -+ (cfg->pms_sdiv << 4) | cfg->pms_sdiv); -+ regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno); -+ regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign); -+ regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK, -+ FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n)); -+ -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, -+ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); -+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, -+ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq); -+ -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); -+ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_lane_init_seq); -+ -+ if (hdptx->earc_en) -+ rk_hdptx_earc_config(hdptx); -+ -+ return rk_hdptx_post_power_up(hdptx); -+} -+ - static int rk_hdptx_phy_power_on(struct phy *phy) - { - struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); -@@ -865,7 +1280,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) - * from the HDMI bridge driver until phy_configure_opts_hdmi - * becomes available in the PHY API. - */ -- unsigned int rate = bus_width & 0xfffffff; -+ unsigned int rate = bus_width & DATA_RATE_MASK; - - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", - __func__, bus_width, rate); -@@ -876,7 +1291,20 @@ static int rk_hdptx_phy_power_on(struct phy *phy) - return ret; - } - -- ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -+ if (bus_width & HDMI_EARC_MASK) -+ hdptx->earc_en = true; -+ else -+ hdptx->earc_en = false; -+ -+ if (bus_width & HDMI_MODE_MASK) { -+ if (rate > 24000000) -+ ret = rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width); -+ else -+ ret = rk_hdptx_ropll_frl_mode_config(hdptx, bus_width); -+ } else { -+ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -+ } -+ - if (ret) - pm_runtime_put(hdptx->dev); - --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch deleted file mode 100644 index 43173de65136..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch +++ /dev/null @@ -1,222 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 16 Jan 2024 19:27:40 +0200 -Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider - -The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU. -It provides more accurate clock rates required to properly support -various display modes, e.g. those relying on non-integer refresh rates. - -Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to -support HDMI 2.1 4K@120Hz mode. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 148 +++++++++- - 1 file changed, 143 insertions(+), 5 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -@@ -8,6 +8,7 @@ - */ - #include - #include -+#include - #include - #include - #include -@@ -279,6 +280,12 @@ struct rk_hdptx_phy { - int nr_clks; - struct reset_control_bulk_data rsts[RST_MAX]; - bool earc_en; -+ -+ /* clk provider */ -+ struct clk_hw hw; -+ unsigned long rate; -+ int id; -+ int count; - }; - - static const struct lcpll_config lcpll_cfg[] = { -@@ -1031,6 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - const struct ropll_config *cfg = NULL; - struct ropll_config rc = {0}; - -+ hdptx->rate = rate * 100; -+ - if (color_depth) - rate = rate * 10 / 8; - -@@ -1315,11 +1324,13 @@ static int rk_hdptx_phy_power_off(struct phy *phy) - { - struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); - u32 val; -- int ret; -+ int ret = 0; - -- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -- if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -- rk_hdptx_phy_disable(hdptx); -+ if (hdptx->count == 0) { -+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -+ rk_hdptx_phy_disable(hdptx); -+ } - - pm_runtime_put(hdptx->dev); - -@@ -1332,6 +1343,129 @@ static const struct phy_ops rk_hdptx_phy_ops = { - .owner = THIS_MODULE, - }; - -+static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) -+{ -+ return container_of(hw, struct rk_hdptx_phy, hw); -+} -+ -+static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ int ret; -+ -+ ret = pm_runtime_resume_and_get(hdptx->dev); -+ if (ret) { -+ dev_err(hdptx->dev, "Failed to resume phy clk: %d\n", ret); -+ return ret; -+ } -+ -+ if (!hdptx->count && hdptx->rate) { -+ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, hdptx->rate / 100); -+ if (ret < 0) { -+ dev_err(hdptx->dev, "Failed to init PHY PLL: %d\n", ret); -+ pm_runtime_put(hdptx->dev); -+ return ret; -+ } -+ } -+ -+ hdptx->count++; -+ -+ return 0; -+} -+ -+static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ if (hdptx->count == 1) { -+ u32 val; -+ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -+ rk_hdptx_phy_disable(hdptx); -+ } -+ -+ hdptx->count--; -+ pm_runtime_put(hdptx->dev); -+} -+ -+static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ return hdptx->rate; -+} -+ -+static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ const struct ropll_config *cfg = NULL; -+ u32 bit_rate = rate / 100; -+ int i; -+ -+ if (rate > HDMI20_MAX_RATE) -+ return rate; -+ -+ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) -+ if (bit_rate == ropll_tmds_cfg[i].bit_rate) { -+ cfg = &ropll_tmds_cfg[i]; -+ break; -+ } -+ -+ if (!cfg && !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) -+ return -EINVAL; -+ -+ return rate; -+} -+ -+static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ u32 val; -+ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -+ rk_hdptx_phy_disable(hdptx); -+ -+ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); -+} -+ -+static const struct clk_ops hdptx_phy_clk_ops = { -+ .prepare = rk_hdptx_phy_clk_prepare, -+ .unprepare = rk_hdptx_phy_clk_unprepare, -+ .recalc_rate = rk_hdptx_phy_clk_recalc_rate, -+ .round_rate = rk_hdptx_phy_clk_round_rate, -+ .set_rate = rk_hdptx_phy_clk_set_rate, -+}; -+ -+static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) -+{ -+ struct device *dev = hdptx->dev; -+ const char *name, *pname; -+ struct clk *refclk; -+ int ret; -+ -+ refclk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(refclk)) -+ return dev_err_probe(dev, PTR_ERR(refclk), -+ "Failed to get ref clock\n"); -+ -+ pname = __clk_get_name(refclk); -+ name = hdptx->id ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; -+ hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, -+ CLK_GET_RATE_NOCACHE); -+ -+ ret = devm_clk_hw_register(dev, &hdptx->hw); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to register clock\n"); -+ -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to register clk provider\n"); -+ return 0; -+} -+ - static int rk_hdptx_phy_runtime_suspend(struct device *dev) - { - struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); -@@ -1367,6 +1501,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) - - hdptx->dev = dev; - -+ hdptx->id = of_alias_get_id(dev->of_node, "hdptxphy"); -+ if (hdptx->id < 0) -+ hdptx->id = 0; -+ - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return dev_err_probe(dev, PTR_ERR(regs), -@@ -1426,7 +1564,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) - reset_control_deassert(hdptx->rsts[RST_CMN].rstc); - reset_control_deassert(hdptx->rsts[RST_INIT].rstc); - -- return 0; -+ return rk_hdptx_phy_clk_register(hdptx); - } - - static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch deleted file mode 100644 index ca6f5d4b6ffc..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch +++ /dev/null @@ -1,679 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Fri, 3 Nov 2023 19:58:02 +0200 -Subject: drm/rockchip: vop2: Improve display modes handling on rk3588 - -The initial vop2 support for rk3588 in mainline is not able to handle -all display modes supported by connected displays, e.g. -2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. - -Additionally, it doesn't cope with non-integer refresh rates like 59.94, -29.97, 23.98, etc. - -Improve HDMI0 clocking in order to support the additional display modes. - -Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 +++++++++- - 1 file changed, 552 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -5,6 +5,8 @@ - */ - #include - #include -+#include -+#include - #include - #include - #include -@@ -212,6 +214,10 @@ struct vop2 { - struct clk *hclk; - struct clk *aclk; - struct clk *pclk; -+ // [CC:] hack to support additional display modes -+ struct clk *hdmi0_phy_pll; -+ /* list_head of internal clk */ -+ struct list_head clk_list_head; - - /* optional internal rgb encoder */ - struct rockchip_rgb *rgb; -@@ -220,6 +226,19 @@ struct vop2 { - struct vop2_win win[]; - }; - -+struct vop2_clk { -+ struct vop2 *vop2; -+ struct list_head list; -+ unsigned long rate; -+ struct clk_hw hw; -+ struct clk_divider div; -+ int div_val; -+ u8 parent_index; -+}; -+ -+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw) -+#define VOP2_MAX_DCLK_RATE 600000 /* kHz */ -+ - #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ - (x) == ROCKCHIP_VOP2_EP_HDMI1) - -@@ -1476,9 +1495,30 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct drm_connector *connector; -+ struct drm_connector_list_iter conn_iter; -+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode); - drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | - CRTC_STEREO_DOUBLE); - -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) -+ adj_mode->crtc_clock *= 2; -+ -+ drm_connector_list_iter_begin(crtc->dev, &conn_iter); -+ drm_for_each_connector_iter(connector, &conn_iter) { -+ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) && -+ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || -+ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) { -+ drm_connector_list_iter_end(&conn_iter); -+ return true; -+ } -+ } -+ drm_connector_list_iter_end(&conn_iter); -+ -+ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) -+ adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, -+ adj_mode->crtc_clock * 1000), 1000); - return true; - } - -@@ -1663,6 +1703,31 @@ static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max - return 0; - } - -+static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name); -+ -+static int vop2_cru_set_rate(struct vop2_clk *if_pixclk, struct vop2_clk *if_dclk) -+{ -+ int ret = 0; -+ -+ if (if_pixclk) { -+ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate); -+ if (ret < 0) { -+ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n", -+ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret); -+ return ret; -+ } -+ } -+ -+ if (if_dclk) { -+ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate); -+ if (ret < 0) -+ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n", -+ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret); -+ } -+ -+ return ret; -+} -+ - /* - * 4 pixclk/cycle on rk3588 - * RGB/eDP/HDMI: if_pixclk >= dclk_core -@@ -1686,6 +1751,72 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, - int K = 1; - - if (vop2_output_if_is_hdmi(id)) { -+ if (vop2->data->soc_id == 3588 && id == ROCKCHIP_VOP2_EP_HDMI0 && -+ vop2->hdmi0_phy_pll) { -+ const char *clk_src_name = "hdmi_edp0_clk_src"; -+ const char *clk_parent_name = "dclk"; -+ const char *pixclk_name = "hdmi_edp0_pixclk"; -+ const char *dclk_name = "hdmi_edp0_dclk"; -+ struct vop2_clk *if_clk_src, *if_clk_parent, *if_pixclk, *if_dclk, *dclk, *dclk_core, *dclk_out; -+ char clk_name[32]; -+ int ret; -+ -+ if_clk_src = vop2_clk_get(vop2, clk_src_name); -+ snprintf(clk_name, sizeof(clk_name), "%s%d", clk_parent_name, vp->id); -+ if_clk_parent = vop2_clk_get(vop2, clk_name); -+ if_pixclk = vop2_clk_get(vop2, pixclk_name); -+ if_dclk = vop2_clk_get(vop2, dclk_name); -+ if (!if_pixclk || !if_clk_parent) { -+ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n"); -+ return -ENODEV; -+ } -+ -+ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk); -+ if (ret < 0) { -+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n", -+ __clk_get_name(if_clk_parent->hw.clk), -+ __clk_get_name(if_clk_src->hw.clk), ret); -+ return ret; -+ } -+ -+ if (output_mode == ROCKCHIP_OUT_MODE_YUV420) -+ K = 2; -+ -+ if_pixclk->rate = (dclk_core_rate << 1) / K; -+ if_dclk->rate = dclk_core_rate / K; -+ -+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id); -+ dclk_core = vop2_clk_get(vop2, clk_name); -+ -+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id); -+ dclk_out = vop2_clk_get(vop2, clk_name); -+ -+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); -+ dclk = vop2_clk_get(vop2, clk_name); -+ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) { -+ if (output_mode == ROCKCHIP_OUT_MODE_YUV420) -+ v_pixclk = v_pixclk >> 1; -+ } else { -+ v_pixclk = v_pixclk >> 2; -+ } -+ clk_set_rate(dclk->hw.clk, v_pixclk); -+ -+ if (dclk_core_rate > if_pixclk->rate) { -+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate); -+ ret = vop2_cru_set_rate(if_pixclk, if_dclk); -+ } else { -+ ret = vop2_cru_set_rate(if_pixclk, if_dclk); -+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate); -+ } -+ -+ *dclk_core_div = dclk_core->div_val; -+ *dclk_out_div = dclk_out->div_val; -+ *if_pixclk_div = if_pixclk->div_val; -+ *if_dclk_div = if_dclk->div_val; -+ -+ return dclk->rate; -+ } -+ - /* - * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate - * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate -@@ -1917,6 +2048,22 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) - return us * mode->clock / mode->htotal / 1000; - } - -+// [CC:] rework virtual clock -+static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name) -+{ -+ struct vop2_clk *clk, *n; -+ -+ if (!name) -+ return NULL; -+ -+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) { -+ if (!strcmp(clk_hw_get_name(&clk->hw), name)) -+ return clk; -+ } -+ -+ return NULL; -+} -+ - static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) - { -@@ -1944,6 +2091,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - u32 val, polflags; - int ret; - struct drm_encoder *encoder; -+ char clk_name[32]; -+ struct vop2_clk *dclk; - - drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", - hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", -@@ -2044,11 +2193,38 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - - if (mode->flags & DRM_MODE_FLAG_DBLCLK) { - dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; -- clock *= 2; -+ // [CC:] done via mode_fixup -+ // clock *= 2; - } - - vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); - -+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); -+ dclk = vop2_clk_get(vop2, clk_name); -+ if (dclk) { -+ /* -+ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available, -+ * otherwise use system cru as dclk source. -+ */ -+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ // [CC:] Using PHY PLL to handle all display modes -+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { -+ clk_get_rate(vop2->hdmi0_phy_pll); -+ -+ if (mode->crtc_clock <= VOP2_MAX_DCLK_RATE) { -+ ret = clk_set_parent(vp->dclk, vop2->hdmi0_phy_pll); -+ if (ret < 0) -+ DRM_WARN("failed to set clock parent for %s\n", -+ __clk_get_name(vp->dclk)); -+ } -+ -+ clock = dclk->rate; -+ } -+ } -+ } -+ - clk_set_rate(vp->dclk, clock); - - vop2_post_config(crtc); -@@ -2504,7 +2680,43 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, - spin_unlock_irq(&crtc->dev->event_lock); - } - -+static enum drm_mode_status -+vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) -+{ -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; -+ const struct vop2_data *vop2_data = vop2->data; -+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; -+ int request_clock = mode->clock; -+ int clock; -+ -+ if (mode->hdisplay > vp_data->max_output.width) -+ return MODE_BAD_HVALUE; -+ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) -+ request_clock *= 2; -+ -+ if (request_clock <= VOP2_MAX_DCLK_RATE) { -+ clock = request_clock; -+ } else { -+ request_clock = request_clock >> 2; -+ clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000; -+ } -+ -+ /* -+ * Hdmi or DisplayPort request a Accurate clock. -+ */ -+ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA || -+ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort) -+ if (clock != request_clock) -+ return MODE_CLOCK_RANGE; -+ -+ return MODE_OK; -+} -+ - static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { -+ .mode_valid = vop2_crtc_mode_valid, - .mode_fixup = vop2_crtc_mode_fixup, - .atomic_check = vop2_crtc_atomic_check, - .atomic_begin = vop2_crtc_atomic_begin, -@@ -3074,6 +3286,336 @@ static const struct regmap_config vop2_regmap_config = { - .cache_type = REGCACHE_MAPLE, - }; - -+/* -+ * BEGIN virtual clock -+ */ -+#define PLL_RATE_MIN 30000000 -+ -+#define cru_dbg(format, ...) do { \ -+ if (cru_debug) \ -+ pr_info("%s: " format, __func__, ## __VA_ARGS__); \ -+ } while (0) -+ -+#define PNAME(x) static const char *const x[] -+ -+enum vop_clk_branch_type { -+ branch_mux, -+ branch_divider, -+ branch_factor, -+ branch_virtual, -+}; -+ -+#define VIR(cname) \ -+ { \ -+ .branch_type = branch_virtual, \ -+ .name = cname, \ -+ } -+ -+ -+#define MUX(cname, pnames, f) \ -+ { \ -+ .branch_type = branch_mux, \ -+ .name = cname, \ -+ .parent_names = pnames, \ -+ .num_parents = ARRAY_SIZE(pnames), \ -+ .flags = f, \ -+ } -+ -+#define FACTOR(cname, pname, f) \ -+ { \ -+ .branch_type = branch_factor, \ -+ .name = cname, \ -+ .parent_names = (const char *[]){ pname }, \ -+ .num_parents = 1, \ -+ .flags = f, \ -+ } -+ -+#define DIV(cname, pname, f, w) \ -+ { \ -+ .branch_type = branch_divider, \ -+ .name = cname, \ -+ .parent_names = (const char *[]){ pname }, \ -+ .num_parents = 1, \ -+ .flags = f, \ -+ .div_width = w, \ -+ } -+ -+struct vop2_clk_branch { -+ enum vop_clk_branch_type branch_type; -+ const char *name; -+ const char *const *parent_names; -+ u8 num_parents; -+ unsigned long flags; -+ u8 div_shift; -+ u8 div_width; -+ u8 div_flags; -+}; -+ -+PNAME(mux_port0_dclk_src_p) = { "dclk0", "dclk1" }; -+PNAME(mux_port2_dclk_src_p) = { "dclk2", "dclk1" }; -+PNAME(mux_dp_pixclk_p) = { "dclk_out0", "dclk_out1", "dclk_out2" }; -+PNAME(mux_hdmi_edp_clk_src_p) = { "dclk0", "dclk1", "dclk2" }; -+PNAME(mux_mipi_clk_src_p) = { "dclk_out1", "dclk_out2", "dclk_out3" }; -+PNAME(mux_dsc_8k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" }; -+PNAME(mux_dsc_4k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" }; -+ -+/* -+ * We only use this clk driver calculate the div -+ * of dclk_core/dclk_out/if_pixclk/if_dclk and -+ * the rate of the dclk from the soc. -+ * -+ * We don't touch the cru in the vop here, as -+ * these registers has special read andy write -+ * limits. -+ */ -+static struct vop2_clk_branch rk3588_vop_clk_branches[] = { -+ VIR("dclk0"), -+ VIR("dclk1"), -+ VIR("dclk2"), -+ VIR("dclk3"), -+ -+ MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2), -+ DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2), -+ -+ FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT), -+ DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2), -+ DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2), -+ -+ MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2), -+ DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2), -+ -+ FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT), -+ DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2), -+ DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2), -+ -+ MUX("dp0_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ MUX("dp1_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ -+ MUX("hdmi_edp0_clk_src", mux_hdmi_edp_clk_src_p, -+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2), -+ DIV("hdmi_edp0_pixclk", "hdmi_edp0_clk_src", CLK_SET_RATE_PARENT, 1), -+ -+ MUX("hdmi_edp1_clk_src", mux_hdmi_edp_clk_src_p, -+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("hdmi_edp1_dclk", "hdmi_edp1_clk_src", 0, 2), -+ DIV("hdmi_edp1_pixclk", "hdmi_edp1_clk_src", CLK_SET_RATE_PARENT, 1), -+ -+ MUX("mipi0_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("mipi0_pixclk", "mipi0_clk_src", CLK_SET_RATE_PARENT, 2), -+ -+ MUX("mipi1_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("mipi1_pixclk", "mipi1_clk_src", CLK_SET_RATE_PARENT, 2), -+ -+ FACTOR("rgb_pixclk", "port3_dclk_src", CLK_SET_RATE_PARENT), -+ -+ MUX("dsc_8k_txp_clk_src", mux_dsc_8k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("dsc_8k_txp_clk", "dsc_8k_txp_clk_src", 0, 2), -+ DIV("dsc_8k_pxl_clk", "dsc_8k_txp_clk_src", 0, 2), -+ DIV("dsc_8k_cds_clk", "dsc_8k_txp_clk_src", 0, 2), -+ -+ MUX("dsc_4k_txp_clk_src", mux_dsc_4k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), -+ DIV("dsc_4k_txp_clk", "dsc_4k_txp_clk_src", 0, 2), -+ DIV("dsc_4k_pxl_clk", "dsc_4k_txp_clk_src", 0, 2), -+ DIV("dsc_4k_cds_clk", "dsc_4k_txp_clk_src", 0, 2), -+}; -+ -+static unsigned long clk_virtual_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ -+ return (unsigned long)vop2_clk->rate; -+} -+ -+static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ -+ vop2_clk->rate = rate; -+ -+ return rate; -+} -+ -+static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ return 0; -+} -+ -+const struct clk_ops clk_virtual_ops = { -+ .round_rate = clk_virtual_round_rate, -+ .set_rate = clk_virtual_set_rate, -+ .recalc_rate = clk_virtual_recalc_rate, -+}; -+ -+static u8 vop2_mux_get_parent(struct clk_hw *hw) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ -+ // cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index); -+ return vop2_clk->parent_index; -+} -+ -+static int vop2_mux_set_parent(struct clk_hw *hw, u8 index) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ -+ vop2_clk->parent_index = index; -+ -+ // cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index); -+ return 0; -+} -+ -+static int vop2_clk_mux_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ // cru_dbg("%s %ld(min: %ld max: %ld)\n", -+ // clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate); -+ return __clk_mux_determine_rate(hw, req); -+} -+ -+static const struct clk_ops vop2_mux_clk_ops = { -+ .get_parent = vop2_mux_get_parent, -+ .set_parent = vop2_mux_set_parent, -+ .determine_rate = vop2_clk_mux_determine_rate, -+}; -+ -+#define div_mask(width) ((1 << (width)) - 1) -+ -+static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate) -+{ -+ unsigned int div, value; -+ -+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); -+ -+ value = ilog2(div); -+ -+ return value; -+} -+ -+static unsigned long vop2_clk_div_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ unsigned long rate; -+ unsigned int div; -+ -+ div = 1 << vop2_clk->div_val; -+ rate = parent_rate / div; -+ -+ // cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate); -+ return rate; -+} -+ -+static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ -+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { -+ if (*prate < rate) -+ *prate = rate; -+ if ((*prate >> vop2_clk->div.width) > rate) -+ *prate = rate; -+ -+ if ((*prate % rate)) -+ *prate = rate; -+ -+ /* SOC PLL can't output a too low pll freq */ -+ if (*prate < PLL_RATE_MIN) -+ *prate = rate << vop2_clk->div.width; -+ } -+ -+ // cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate); -+ return rate; -+} -+ -+static int vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) -+{ -+ struct vop2_clk *vop2_clk = to_vop2_clk(hw); -+ int div_val; -+ -+ div_val = vop2_div_get_val(rate, parent_rate); -+ vop2_clk->div_val = div_val; -+ -+ // cru_dbg("%s prate: %ld rate: %ld div_val: %d\n", -+ // clk_hw_get_name(hw), parent_rate, rate, div_val); -+ return 0; -+} -+ -+static const struct clk_ops vop2_div_clk_ops = { -+ .recalc_rate = vop2_clk_div_recalc_rate, -+ .round_rate = vop2_clk_div_round_rate, -+ .set_rate = vop2_clk_div_set_rate, -+}; -+ -+static struct clk *vop2_clk_register(struct vop2 *vop2, struct vop2_clk_branch *branch) -+{ -+ struct clk_init_data init = {}; -+ struct vop2_clk *vop2_clk; -+ struct clk *clk; -+ -+ vop2_clk = devm_kzalloc(vop2->dev, sizeof(*vop2_clk), GFP_KERNEL); -+ if (!vop2_clk) -+ return ERR_PTR(-ENOMEM); -+ -+ vop2_clk->vop2 = vop2; -+ vop2_clk->hw.init = &init; -+ vop2_clk->div.shift = branch->div_shift; -+ vop2_clk->div.width = branch->div_width; -+ -+ init.name = branch->name; -+ init.flags = branch->flags; -+ init.num_parents = branch->num_parents; -+ init.parent_names = branch->parent_names; -+ if (branch->branch_type == branch_divider) { -+ init.ops = &vop2_div_clk_ops; -+ } else if (branch->branch_type == branch_virtual) { -+ init.ops = &clk_virtual_ops; -+ init.num_parents = 0; -+ init.parent_names = NULL; -+ } else { -+ init.ops = &vop2_mux_clk_ops; -+ } -+ -+ clk = devm_clk_register(vop2->dev, &vop2_clk->hw); -+ if (!IS_ERR(clk)) -+ list_add_tail(&vop2_clk->list, &vop2->clk_list_head); -+ else -+ DRM_DEV_ERROR(vop2->dev, "Register %s failed\n", branch->name); -+ -+ return clk; -+} -+ -+static int vop2_clk_init(struct vop2 *vop2) -+{ -+ struct vop2_clk_branch *branch = rk3588_vop_clk_branches; -+ unsigned int nr_clk = ARRAY_SIZE(rk3588_vop_clk_branches); -+ unsigned int idx; -+ struct vop2_clk *clk, *n; -+ -+ INIT_LIST_HEAD(&vop2->clk_list_head); -+ -+ if (vop2->data->soc_id < 3588 || vop2->hdmi0_phy_pll == NULL) -+ return 0; -+ -+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) { -+ list_del(&clk->list); -+ } -+ -+ for (idx = 0; idx < nr_clk; idx++, branch++) -+ vop2_clk_register(vop2, branch); -+ -+ return 0; -+} -+/* -+ * END virtual clock -+ */ -+ - static int vop2_bind(struct device *dev, struct device *master, void *data) - { - struct platform_device *pdev = to_platform_device(dev); -@@ -3167,6 +3709,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) - return PTR_ERR(vop2->pclk); - } - -+ vop2->hdmi0_phy_pll = devm_clk_get_optional(vop2->drm->dev, "hdmi0_phy_pll"); -+ if (IS_ERR(vop2->hdmi0_phy_pll)) { -+ DRM_DEV_ERROR(vop2->dev, "failed to get hdmi0_phy_pll source\n"); -+ return PTR_ERR(vop2->hdmi0_phy_pll); -+ } -+ - vop2->irq = platform_get_irq(pdev, 0); - if (vop2->irq < 0) { - drm_err(vop2->drm, "cannot find irq for vop2\n"); -@@ -3183,6 +3731,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) - if (ret) - return ret; - -+ // [CC:] rework virtual clock -+ vop2_clk_init(vop2); -+ - ret = vop2_find_rgb_encoder(vop2); - if (ret >= 0) { - vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch deleted file mode 100644 index e2b7486d10d3..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 13 May 2024 20:29:49 +0300 -Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes - ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 ++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -726,6 +726,17 @@ mmu600_php: iommu@fcb00000 { - status = "disabled"; - }; - -+ rga: rga@fdb80000 { -+ compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; -+ reg = <0x0 0xfdb80000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; -+ clock-names = "aclk", "hclk", "sclk"; -+ resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; -+ reset-names = "core", "axi", "ahb"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch deleted file mode 100644 index c4994f7d9164..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch +++ /dev/null @@ -1,6616 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 1 Nov 2023 18:50:38 +0200 -Subject: [WIP] drm/bridge: synopsys: Add initial support for DW HDMI QP TX - Controller - -Co-developed-by: Algea Cao -Signed-off-by: Algea Cao -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/bridge/synopsys/Makefile | 2 +- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2401 ++++++++ - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 831 +++ - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 89 + - drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 + - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2740 +++++++++- - include/drm/bridge/dw_hdmi.h | 101 + - 7 files changed, 6102 insertions(+), 66 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/Makefile -+++ b/drivers/gpu/drm/bridge/synopsys/Makefile -@@ -1,5 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o -+obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o dw-hdmi-qp.o - obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o - obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o - obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -0,0 +1,2401 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) Rockchip Electronics Co.Ltd -+ * Author: -+ * Algea Cao -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dw-hdmi-qp.h" -+ -+#define DDC_CI_ADDR 0x37 -+#define DDC_SEGMENT_ADDR 0x30 -+ -+#define HDMI_EDID_LEN 512 -+ -+/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ -+#define SCDC_MIN_SOURCE_VERSION 0x1 -+ -+#define HDMI14_MAX_TMDSCLK 340000000 -+#define HDMI20_MAX_TMDSCLK_KHZ 600000 -+ -+static const unsigned int dw_hdmi_cable[] = { -+ EXTCON_DISP_HDMI, -+ EXTCON_NONE, -+}; -+ -+static const struct drm_display_mode dw_hdmi_default_modes[] = { -+ /* 16 - 1920x1080@60Hz 16:9 */ -+ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, -+ 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, -+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, -+ /* 2 - 720x480@60Hz 4:3 */ -+ { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, -+ 798, 858, 0, 480, 489, 495, 525, 0, -+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, -+ /* 4 - 1280x720@60Hz 16:9 */ -+ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, -+ 1430, 1650, 0, 720, 725, 730, 750, 0, -+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, -+ /* 31 - 1920x1080@50Hz 16:9 */ -+ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, -+ 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, -+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, -+ /* 19 - 1280x720@50Hz 16:9 */ -+ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, -+ 1760, 1980, 0, 720, 725, 730, 750, 0, -+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, -+ /* 17 - 720x576@50Hz 4:3 */ -+ { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, -+ 796, 864, 0, 576, 581, 586, 625, 0, -+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, -+ /* 2 - 720x480@60Hz 4:3 */ -+ { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, -+ 798, 858, 0, 480, 489, 495, 525, 0, -+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, -+}; -+ -+enum frl_mask { -+ FRL_3GBPS_3LANE = 1, -+ FRL_6GBPS_3LANE, -+ FRL_6GBPS_4LANE, -+ FRL_8GBPS_4LANE, -+ FRL_10GBPS_4LANE, -+ FRL_12GBPS_4LANE, -+}; -+ -+struct hdmi_vmode_qp { -+ bool mdataenablepolarity; -+ -+ unsigned int previous_pixelclock; -+ unsigned long mpixelclock; -+ unsigned int mpixelrepetitioninput; -+ unsigned int mpixelrepetitionoutput; -+ unsigned long previous_tmdsclock; -+ unsigned int mtmdsclock; -+}; -+ -+struct hdmi_qp_data_info { -+ unsigned int enc_in_bus_format; -+ unsigned int enc_out_bus_format; -+ unsigned int enc_in_encoding; -+ unsigned int enc_out_encoding; -+ unsigned int quant_range; -+ unsigned int pix_repet_factor; -+ struct hdmi_vmode_qp video_mode; -+ bool update; -+}; -+ -+struct dw_hdmi_qp_i2c { -+ struct i2c_adapter adap; -+ -+ struct mutex lock; /* used to serialize data transfers */ -+ struct completion cmp; -+ u32 stat; -+ -+ u8 slave_reg; -+ bool is_regaddr; -+ bool is_segment; -+ -+ unsigned int scl_high_ns; -+ unsigned int scl_low_ns; -+}; -+ -+struct dw_hdmi_qp { -+ struct drm_connector connector; -+ struct drm_bridge bridge; -+ struct platform_device *hdcp_dev; -+ struct platform_device *audio; -+ struct platform_device *cec; -+ struct device *dev; -+ struct dw_hdmi_qp_i2c *i2c; -+ -+ struct hdmi_qp_data_info hdmi_data; -+ const struct dw_hdmi_plat_data *plat_data; -+ -+ int vic; -+ int main_irq; -+ int avp_irq; -+ int earc_irq; -+ -+ u8 edid[HDMI_EDID_LEN]; -+ -+ struct { -+ const struct dw_hdmi_qp_phy_ops *ops; -+ const char *name; -+ void *data; -+ bool enabled; -+ } phy; -+ -+ struct drm_display_mode previous_mode; -+ -+ struct i2c_adapter *ddc; -+ void __iomem *regs; -+ bool sink_is_hdmi; -+ -+ struct mutex mutex; /* for state below and previous_mode */ -+ //[CC:] curr_conn should be removed -+ struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ -+ enum drm_connector_force force; /* mutex-protected force state */ -+ bool disabled; /* DRM has disabled our bridge */ -+ bool bridge_is_on; /* indicates the bridge is on */ -+ bool rxsense; /* rxsense state */ -+ u8 phy_mask; /* desired phy int mask settings */ -+ u8 mc_clkdis; /* clock disable register */ -+ -+ u32 scdc_intr; -+ u32 flt_intr; -+ //[CC:] remove earc -+ u32 earc_intr; -+ -+ struct dentry *debugfs_dir; -+ bool scramble_low_rates; -+ -+ struct extcon_dev *extcon; -+ -+ struct regmap *regm; -+ -+ bool initialized; /* hdmi is enabled before bind */ -+ struct completion flt_cmp; -+ struct completion earc_cmp; -+ -+ hdmi_codec_plugged_cb plugged_cb; -+ struct device *codec_dev; -+ enum drm_connector_status last_connector_result; -+}; -+ -+static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) -+{ -+ regmap_write(hdmi->regm, offset, val); -+} -+ -+static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) -+{ -+ unsigned int val = 0; -+ -+ regmap_read(hdmi->regm, offset, &val); -+ -+ return val; -+} -+ -+static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged) -+{ -+ if (hdmi->plugged_cb && hdmi->codec_dev) -+ hdmi->plugged_cb(hdmi->codec_dev, plugged); -+} -+ -+static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg) -+{ -+ regmap_update_bits(hdmi->regm, reg, mask, data); -+} -+ -+static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: -+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static int hdmi_bus_fmt_color_depth(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ return 8; -+ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ return 10; -+ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: -+ return 12; -+ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: -+ return 16; -+ -+ default: -+ return 0; -+ } -+} -+ -+static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) -+{ -+ /* Software reset */ -+ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); -+ -+ hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); -+ -+ hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); -+ -+ /* Clear DONE and ERROR interrupts */ -+ hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, -+ MAINUNIT_1_INT_CLEAR); -+} -+ -+static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, -+ unsigned char *buf, unsigned int length) -+{ -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ int stat; -+ -+ if (!i2c->is_regaddr) { -+ dev_dbg(hdmi->dev, "set read register address to 0\n"); -+ i2c->slave_reg = 0x00; -+ i2c->is_regaddr = true; -+ } -+ -+ while (length--) { -+ reinit_completion(&i2c->cmp); -+ -+ hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, -+ I2CM_INTERFACE_CONTROL0); -+ -+ hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, -+ I2CM_INTERFACE_CONTROL0); -+ -+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); -+ if (!stat) { -+ dev_err(hdmi->dev, "i2c read time out!\n"); -+ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); -+ return -EAGAIN; -+ } -+ -+ /* Check for error condition on the bus */ -+ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { -+ dev_err(hdmi->dev, "i2c read err!\n"); -+ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); -+ return -EIO; -+ } -+ -+ *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; -+ hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); -+ } -+ i2c->is_segment = false; -+ -+ return 0; -+} -+ -+static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, -+ unsigned char *buf, unsigned int length) -+{ -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ int stat; -+ -+ if (!i2c->is_regaddr) { -+ /* Use the first write byte as register address */ -+ i2c->slave_reg = buf[0]; -+ length--; -+ buf++; -+ i2c->is_regaddr = true; -+ } -+ -+ while (length--) { -+ reinit_completion(&i2c->cmp); -+ -+ hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); -+ hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, -+ I2CM_INTERFACE_CONTROL0); -+ hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, -+ I2CM_INTERFACE_CONTROL0); -+ -+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); -+ if (!stat) { -+ dev_err(hdmi->dev, "i2c write time out!\n"); -+ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); -+ return -EAGAIN; -+ } -+ -+ /* Check for error condition on the bus */ -+ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { -+ dev_err(hdmi->dev, "i2c write nack!\n"); -+ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); -+ return -EIO; -+ } -+ hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); -+ } -+ -+ return 0; -+} -+ -+static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, -+ struct i2c_msg *msgs, int num) -+{ -+ struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ u8 addr = msgs[0].addr; -+ int i, ret = 0; -+ -+ if (addr == DDC_CI_ADDR) -+ /* -+ * The internal I2C controller does not support the multi-byte -+ * read and write operations needed for DDC/CI. -+ * TOFIX: Blacklist the DDC/CI address until we filter out -+ * unsupported I2C operations. -+ */ -+ return -EOPNOTSUPP; -+ -+ for (i = 0; i < num; i++) { -+ if (msgs[i].len == 0) { -+ dev_err(hdmi->dev, -+ "unsupported transfer %d/%d, no data\n", -+ i + 1, num); -+ return -EOPNOTSUPP; -+ } -+ } -+ -+ mutex_lock(&i2c->lock); -+ -+ /* Unmute DONE and ERROR interrupts */ -+ hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, -+ I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, -+ MAINUNIT_1_INT_MASK_N); -+ -+ /* Set slave device address taken from the first I2C message */ -+ if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) -+ addr = DDC_ADDR; -+ -+ hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); -+ -+ /* Set slave device register address on transfer */ -+ i2c->is_regaddr = false; -+ -+ /* Set segment pointer for I2C extended read mode operation */ -+ i2c->is_segment = false; -+ -+ for (i = 0; i < num; i++) { -+ if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { -+ i2c->is_segment = true; -+ hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, -+ I2CM_INTERFACE_CONTROL1); -+ hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, -+ I2CM_INTERFACE_CONTROL1); -+ } else { -+ if (msgs[i].flags & I2C_M_RD) -+ ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, -+ msgs[i].len); -+ else -+ ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, -+ msgs[i].len); -+ } -+ if (ret < 0) -+ break; -+ } -+ -+ if (!ret) -+ ret = num; -+ -+ /* Mute DONE and ERROR interrupts */ -+ hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, -+ MAINUNIT_1_INT_MASK_N); -+ -+ mutex_unlock(&i2c->lock); -+ -+ return ret; -+} -+ -+static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm dw_hdmi_algorithm = { -+ .master_xfer = dw_hdmi_i2c_xfer, -+ .functionality = dw_hdmi_i2c_func, -+}; -+ -+static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi) -+{ -+ struct i2c_adapter *adap; -+ struct dw_hdmi_qp_i2c *i2c; -+ int ret; -+ -+ i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); -+ if (!i2c) -+ return ERR_PTR(-ENOMEM); -+ -+ mutex_init(&i2c->lock); -+ init_completion(&i2c->cmp); -+ -+ adap = &i2c->adap; -+ adap->owner = THIS_MODULE; -+ adap->dev.parent = hdmi->dev; -+ adap->algo = &dw_hdmi_algorithm; -+ strscpy(adap->name, "ddc", sizeof(adap->name)); -+ i2c_set_adapdata(adap, hdmi); -+ -+ ret = i2c_add_adapter(adap); -+ if (ret) { -+ dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); -+ devm_kfree(hdmi->dev, i2c); -+ return ERR_PTR(ret); -+ } -+ -+ hdmi->i2c = i2c; -+ -+ dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); -+ -+ return adap; -+} -+ -+#define HDMI_PHY_EARC_MASK BIT(29) -+ -+/* ----------------------------------------------------------------------------- -+ * HDMI TX Setup -+ */ -+ -+static void hdmi_infoframe_set_checksum(u8 *ptr, int size) -+{ -+ u8 csum = 0; -+ int i; -+ -+ ptr[3] = 0; -+ /* compute checksum */ -+ for (i = 0; i < size; i++) -+ csum += ptr[i]; -+ -+ ptr[3] = 256 - csum; -+} -+ -+static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, -+ const struct drm_connector *connector, -+ const struct drm_display_mode *mode) -+{ -+ struct hdmi_avi_infoframe frame; -+ u32 val, i, j; -+ u8 buff[17]; -+ enum hdmi_quantization_range rgb_quant_range = -+ hdmi->hdmi_data.quant_range; -+ -+ /* Initialise info frame from DRM mode */ -+ drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); -+ -+ /* -+ * Ignore monitor selectable quantization, use quantization set -+ * by the user -+ */ -+ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range); -+ if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) -+ frame.colorspace = HDMI_COLORSPACE_YUV444; -+ else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) -+ frame.colorspace = HDMI_COLORSPACE_YUV422; -+ else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -+ frame.colorspace = HDMI_COLORSPACE_YUV420; -+ else -+ frame.colorspace = HDMI_COLORSPACE_RGB; -+ -+ /* Set up colorimetry */ -+ if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { -+ switch (hdmi->hdmi_data.enc_out_encoding) { -+ case V4L2_YCBCR_ENC_601: -+ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) -+ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; -+ else -+ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; -+ break; -+ case V4L2_YCBCR_ENC_709: -+ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) -+ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; -+ else -+ frame.colorimetry = HDMI_COLORIMETRY_ITU_709; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; -+ break; -+ case V4L2_YCBCR_ENC_BT2020: -+ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) -+ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; -+ else -+ frame.colorimetry = HDMI_COLORIMETRY_ITU_709; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_BT2020; -+ break; -+ default: /* Carries no data */ -+ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; -+ break; -+ } -+ } else { -+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { -+ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_BT2020; -+ } else { -+ frame.colorimetry = HDMI_COLORIMETRY_NONE; -+ frame.extended_colorimetry = -+ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; -+ } -+ } -+ -+ frame.scan_mode = HDMI_SCAN_MODE_NONE; -+ frame.video_code = hdmi->vic; -+ -+ hdmi_avi_infoframe_pack_only(&frame, buff, 17); -+ -+ /* mode which vic >= 128 must use avi version 3 */ -+ if (hdmi->vic >= 128) { -+ frame.version = 3; -+ buff[1] = frame.version; -+ buff[4] &= 0x1f; -+ buff[4] |= ((frame.colorspace & 0x7) << 5); -+ buff[7] = frame.video_code; -+ hdmi_infoframe_set_checksum(buff, 17); -+ } -+ -+ /* -+ * The Designware IP uses a different byte format from standard -+ * AVI info frames, though generally the bits are in the correct -+ * bytes. -+ */ -+ -+ val = (frame.version << 8) | (frame.length << 16); -+ hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); -+ -+ for (i = 0; i < 4; i++) { -+ for (j = 0; j < 4; j++) { -+ if (i * 4 + j >= 14) -+ break; -+ if (!j) -+ val = buff[i * 4 + j + 3]; -+ val |= buff[i * 4 + j + 3] << (8 * j); -+ } -+ -+ hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); -+ } -+ -+ hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); -+ -+ hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, -+ PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, -+ PKTSCHED_PKT_EN); -+} -+ -+static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi) -+{ -+ u8 ds_type = 0; -+ u8 sync = 1; -+ u8 vfr = 1; -+ u8 afr = 0; -+ u8 new = 1; -+ u8 end = 0; -+ u8 data_set_length = 136; -+ u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; -+ u8 *pps_body; -+ u32 val, i, reg; -+ struct drm_display_mode *mode = &hdmi->previous_mode; -+ int hsync, hfront, hback; -+ struct dw_hdmi_link_config *link_cfg; -+ void *data = hdmi->plat_data->phy_data; -+ -+ hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); -+ -+ if (hdmi->plat_data->get_link_cfg) { -+ link_cfg = hdmi->plat_data->get_link_cfg(data); -+ } else { -+ dev_err(hdmi->dev, "can't get frl link cfg\n"); -+ return; -+ } -+ -+ if (!link_cfg->dsc_mode) { -+ dev_info(hdmi->dev, "don't use dsc mode\n"); -+ return; -+ } -+ -+ pps_body = link_cfg->pps_payload; -+ -+ hsync = mode->hsync_end - mode->hsync_start; -+ hback = mode->htotal - mode->hsync_end; -+ hfront = mode->hsync_start - mode->hdisplay; -+ -+ for (i = 0; i < 6; i++) { -+ val = i << 16 | hb1[i] << 8; -+ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); -+ } -+ -+ val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | -+ vfr << 2 | sync << 1; -+ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); -+ -+ val = data_set_length << 16 | pps_body[0] << 24; -+ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); -+ -+ reg = PKT0_EMP_CVTEM_CONTENTS3; -+ for (i = 1; i < 125; i++) { -+ if (reg == PKT1_EMP_CVTEM_CONTENTS0 || -+ reg == PKT2_EMP_CVTEM_CONTENTS0 || -+ reg == PKT3_EMP_CVTEM_CONTENTS0 || -+ reg == PKT4_EMP_CVTEM_CONTENTS0 || -+ reg == PKT5_EMP_CVTEM_CONTENTS0) { -+ reg += 4; -+ i--; -+ continue; -+ } -+ if (i % 4 == 1) -+ val = pps_body[i]; -+ if (i % 4 == 2) -+ val |= pps_body[i] << 8; -+ if (i % 4 == 3) -+ val |= pps_body[i] << 16; -+ if (!(i % 4)) { -+ val |= pps_body[i] << 24; -+ hdmi_writel(hdmi, val, reg); -+ reg += 4; -+ } -+ } -+ -+ val = (hfront & 0xff) << 24 | pps_body[127] << 16 | -+ pps_body[126] << 8 | pps_body[125]; -+ hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); -+ -+ val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | -+ (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); -+ hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); -+ -+ val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); -+ hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); -+ -+ for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) -+ hdmi_writel(hdmi, 0, i); -+ -+ hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, -+ PKTSCHED_PKT_EN); -+} -+ -+static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi, -+ const struct drm_connector *connector) -+{ -+ const struct drm_connector_state *conn_state = connector->state; -+ struct hdr_output_metadata *hdr_metadata; -+ struct hdmi_drm_infoframe frame; -+ u8 buffer[30]; -+ ssize_t err; -+ int i; -+ u32 val; -+ -+ if (!hdmi->plat_data->use_drm_infoframe) -+ return; -+ -+ hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); -+ -+ if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) { -+ DRM_DEBUG("No need to set HDR metadata in infoframe\n"); -+ return; -+ } -+ -+ if (!conn_state->hdr_output_metadata) { -+ DRM_DEBUG("source metadata not set yet\n"); -+ return; -+ } -+ -+ hdr_metadata = (struct hdr_output_metadata *) -+ conn_state->hdr_output_metadata->data; -+ -+ if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf & -+ BIT(hdr_metadata->hdmi_metadata_type1.eotf))) { -+ DRM_ERROR("Not support EOTF %d\n", -+ hdr_metadata->hdmi_metadata_type1.eotf); -+ return; -+ } -+ -+ err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); -+ if (err < 0) -+ return; -+ -+ err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); -+ if (err < 0) { -+ dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); -+ return; -+ } -+ -+ val = (frame.version << 8) | (frame.length << 16); -+ hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0); -+ -+ for (i = 0; i <= frame.length; i++) { -+ if (i % 4 == 0) -+ val = buffer[3 + i]; -+ val |= buffer[3 + i] << ((i % 4) * 8); -+ -+ if (i % 4 == 3 || (i == (frame.length))) -+ hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4)); -+ } -+ -+ hdmi_modb(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); -+ -+ hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); -+ -+ DRM_DEBUG("%s eotf %d end\n", __func__, -+ hdr_metadata->hdmi_metadata_type1.eotf); -+} -+ -+/* Filter out invalid setups to avoid configuring SCDC and scrambling */ -+static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi, -+ const struct drm_display_info *display) -+{ -+ /* Disable if no DDC bus */ -+ if (!hdmi->ddc) -+ return false; -+ -+ /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ -+ if (!display->hdmi.scdc.supported || -+ !display->hdmi.scdc.scrambling.supported) -+ return false; -+ -+ /* -+ * Disable if display only support low TMDS rates and scrambling -+ * for low rates is not supported either -+ */ -+ if (!display->hdmi.scdc.scrambling.low_rates && -+ display->max_tmds_clock <= 340000) -+ return false; -+ -+ return true; -+} -+ -+static int hdmi_set_frl_mask(int frl_rate) -+{ -+ switch (frl_rate) { -+ case 48: -+ return FRL_12GBPS_4LANE; -+ case 40: -+ return FRL_10GBPS_4LANE; -+ case 32: -+ return FRL_8GBPS_4LANE; -+ case 24: -+ return FRL_6GBPS_4LANE; -+ case 18: -+ return FRL_6GBPS_3LANE; -+ case 9: -+ return FRL_3GBPS_3LANE; -+ } -+ -+ return 0; -+} -+ -+static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) -+{ -+ u8 val; -+ u8 ffe_lv = 0; -+ int i = 0, stat; -+ -+ /* FLT_READY & FFE_LEVELS read */ -+ for (i = 0; i < 20; i++) { -+ drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val); -+ if (val & BIT(6)) -+ break; -+ msleep(20); -+ } -+ -+ if (i == 20) { -+ dev_err(hdmi->dev, "sink flt isn't ready\n"); -+ return -EINVAL; -+ } -+ -+ hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ, -+ MAINUNIT_1_INT_MASK_N); -+ hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, -+ SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, -+ SCDC_CONFIG0); -+ -+ /* max ffe level 3 */ -+ val = 3 << 4 | hdmi_set_frl_mask(rate); -+ drm_scdc_writeb(hdmi->ddc, 0x31, val); -+ -+ /* select FRL_RATE & FFE_LEVELS */ -+ hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); -+ -+ /* Start LTS_3 state in source DUT */ -+ reinit_completion(&hdmi->flt_cmp); -+ hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ, -+ MAINUNIT_1_INT_MASK_N); -+ hdmi_writel(hdmi, 1, FLT_CONTROL0); -+ -+ /* wait for completed link training at source side */ -+ stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2); -+ if (!stat) { -+ dev_err(hdmi->dev, "wait lts3 finish time out\n"); -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | -+ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, -+ MAINUNIT_1_INT_MASK_N); -+ return -EAGAIN; -+ } -+ -+ if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) { -+ dev_err(hdmi->dev, "not to ltsp\n"); -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | -+ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, -+ MAINUNIT_1_INT_MASK_N); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+#define HDMI_MODE_FRL_MASK BIT(30) -+ -+static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, -+ struct dw_hdmi_link_config *link_cfg, -+ const struct drm_connector *connector) -+{ -+ int frl_rate; -+ int i; -+ -+ /* set sink frl mode disable and wait sink ready */ -+ hdmi_writel(hdmi, 0, FLT_CONFIG0); -+ if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) -+ drm_scdc_writeb(hdmi->ddc, 0x31, 0); -+ /* -+ * some TVs must wait a while before switching frl mode resolution, -+ * or the signal may not be recognized. -+ */ -+ msleep(200); -+ -+ if (!link_cfg->frl_mode) { -+ dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n"); -+ hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); -+ hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); -+ return; -+ } -+ -+ if (link_cfg->frl_lanes == 4) -+ hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, -+ LINK_CONFIG0); -+ else -+ hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); -+ -+ hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); -+ -+ frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; -+ hdmi_start_flt(hdmi, frl_rate); -+ -+ for (i = 0; i < 50; i++) { -+ hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); -+ mdelay(1); -+ hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); -+ } -+} -+ -+static unsigned long -+hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) -+{ -+ unsigned long tmdsclock = mpixelclock; -+ unsigned int depth = -+ hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); -+ -+ if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { -+ switch (depth) { -+ case 16: -+ tmdsclock = mpixelclock * 2; -+ break; -+ case 12: -+ tmdsclock = mpixelclock * 3 / 2; -+ break; -+ case 10: -+ tmdsclock = mpixelclock * 5 / 4; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ return tmdsclock; -+} -+ -+//[CC:] is connector param different from hdmi->connector? -+//[CC:] probably it possible to hook the whole implementation into dw-hdmi.c -+static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi, -+ struct drm_connector *connector, -+ struct drm_display_mode *mode) -+{ -+ int ret; -+ void *data = hdmi->plat_data->phy_data; -+ struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; -+ struct dw_hdmi_link_config *link_cfg; -+ u8 bytes = 0; -+ -+ hdmi->vic = drm_match_cea_mode(mode); -+ if (!hdmi->vic) -+ dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); -+ else -+ dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); -+ -+ if (hdmi->plat_data->get_enc_out_encoding) -+ hdmi->hdmi_data.enc_out_encoding = -+ hdmi->plat_data->get_enc_out_encoding(data); -+ else if ((hdmi->vic == 6) || (hdmi->vic == 7) || -+ (hdmi->vic == 21) || (hdmi->vic == 22) || -+ (hdmi->vic == 2) || (hdmi->vic == 3) || -+ (hdmi->vic == 17) || (hdmi->vic == 18)) -+ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; -+ else -+ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; -+ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) { -+ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; -+ hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; -+ } else { -+ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; -+ hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; -+ } -+ /* Get input format from plat data or fallback to RGB888 */ -+ if (hdmi->plat_data->get_input_bus_format) -+ hdmi->hdmi_data.enc_in_bus_format = -+ hdmi->plat_data->get_input_bus_format(data); -+ else if (hdmi->plat_data->input_bus_format) -+ hdmi->hdmi_data.enc_in_bus_format = -+ hdmi->plat_data->input_bus_format; -+ else -+ hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ /* Default to RGB888 output format */ -+ if (hdmi->plat_data->get_output_bus_format) -+ hdmi->hdmi_data.enc_out_bus_format = -+ hdmi->plat_data->get_output_bus_format(data); -+ else -+ hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ /* Get input encoding from plat data or fallback to none */ -+ if (hdmi->plat_data->get_enc_in_encoding) -+ hdmi->hdmi_data.enc_in_encoding = -+ hdmi->plat_data->get_enc_in_encoding(data); -+ else if (hdmi->plat_data->input_bus_encoding) -+ hdmi->hdmi_data.enc_in_encoding = -+ hdmi->plat_data->input_bus_encoding; -+ else -+ hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; -+ -+ if (hdmi->plat_data->get_quant_range) -+ hdmi->hdmi_data.quant_range = -+ hdmi->plat_data->get_quant_range(data); -+ else -+ hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; -+ -+ if (hdmi->plat_data->get_link_cfg) -+ link_cfg = hdmi->plat_data->get_link_cfg(data); -+ else -+ return -EINVAL; -+ -+ hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK, -+ link_cfg->frl_mode); -+ -+ /* -+ * According to the dw-hdmi specification 6.4.2 -+ * vp_pr_cd[3:0]: -+ * 0000b: No pixel repetition (pixel sent only once) -+ * 0001b: Pixel sent two times (pixel repeated once) -+ */ -+ hdmi->hdmi_data.pix_repet_factor = -+ (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; -+ hdmi->hdmi_data.video_mode.mdataenablepolarity = true; -+ -+ vmode->previous_pixelclock = vmode->mpixelclock; -+ //[CC:] no split mode -+ // if (hdmi->plat_data->split_mode) -+ // mode->crtc_clock /= 2; -+ vmode->mpixelclock = mode->crtc_clock * 1000; -+ if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) -+ vmode->mpixelclock *= 2; -+ dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock); -+ vmode->previous_tmdsclock = vmode->mtmdsclock; -+ vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); -+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -+ vmode->mtmdsclock /= 2; -+ dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock); -+ -+ ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); -+ if (ret) -+ return ret; -+ -+ if (hdmi->plat_data->set_grf_cfg) -+ hdmi->plat_data->set_grf_cfg(data); -+ -+ /* not for DVI mode */ -+ if (hdmi->sink_is_hdmi) { -+ dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); -+ hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); -+ hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); -+ if (!link_cfg->frl_mode) { -+ if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { -+ drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes); -+ drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, -+ min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); -+ //[CC:] use dw_hdmi_set_high_tmds_clock_ratio() -+ drm_scdc_set_high_tmds_clock_ratio(connector, 1); -+ drm_scdc_set_scrambling(connector, 1); -+ hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); -+ } else { -+ if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) { -+ drm_scdc_set_high_tmds_clock_ratio(connector, 0); -+ drm_scdc_set_scrambling(connector, 0); -+ } -+ hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); -+ } -+ } -+ /* HDMI Initialization Step F - Configure AVI InfoFrame */ -+ hdmi_config_AVI(hdmi, connector, mode); -+ hdmi_config_CVTEM(hdmi); -+ hdmi_config_drm_infoframe(hdmi, connector); -+ hdmi_set_op_mode(hdmi, link_cfg, connector); -+ } else { -+ hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); -+ hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); -+ dev_info(hdmi->dev, "%s DVI mode\n", __func__); -+ } -+ -+ return 0; -+} -+ -+static enum drm_connector_status -+dw_hdmi_connector_detect(struct drm_connector *connector, bool force) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ struct dw_hdmi_qp *secondary = NULL; -+ enum drm_connector_status result, result_secondary; -+ -+ mutex_lock(&hdmi->mutex); -+ hdmi->force = DRM_FORCE_UNSPECIFIED; -+ mutex_unlock(&hdmi->mutex); -+ -+ if (hdmi->plat_data->left) -+ secondary = hdmi->plat_data->left; -+ else if (hdmi->plat_data->right) -+ secondary = hdmi->plat_data->right; -+ -+ result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); -+ -+ if (secondary) { -+ result_secondary = secondary->phy.ops->read_hpd(secondary, secondary->phy.data); -+ if (result == connector_status_connected && -+ result_secondary == connector_status_connected) -+ result = connector_status_connected; -+ else -+ result = connector_status_disconnected; -+ } -+ -+ mutex_lock(&hdmi->mutex); -+ if (result != hdmi->last_connector_result) { -+ dev_dbg(hdmi->dev, "read_hpd result: %d", result); -+ handle_plugged_change(hdmi, -+ result == connector_status_connected); -+ hdmi->last_connector_result = result; -+ } -+ mutex_unlock(&hdmi->mutex); -+ -+ return result; -+} -+ -+static int -+dw_hdmi_update_hdr_property(struct drm_connector *connector) -+{ -+ struct drm_device *dev = connector->dev; -+ struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, -+ connector); -+ void *data = hdmi->plat_data->phy_data; -+ const struct hdr_static_metadata *metadata = -+ &connector->hdr_sink_metadata.hdmi_type1; -+ size_t size = sizeof(*metadata); -+ struct drm_property *property = NULL; -+ struct drm_property_blob *blob; -+ int ret; -+ -+ if (hdmi->plat_data->get_hdr_property) -+ property = hdmi->plat_data->get_hdr_property(data); -+ -+ if (!property) -+ return -EINVAL; -+ -+ if (hdmi->plat_data->get_hdr_blob) -+ blob = hdmi->plat_data->get_hdr_blob(data); -+ else -+ return -EINVAL; -+ -+ ret = drm_property_replace_global_blob(dev, &blob, size, metadata, -+ &connector->base, property); -+ return ret; -+} -+ -+static int dw_hdmi_connector_get_modes(struct drm_connector *connector) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ struct hdr_static_metadata *metedata = -+ &connector->hdr_sink_metadata.hdmi_type1; -+ struct edid *edid; -+ struct drm_display_mode *mode; -+ struct drm_display_info *info = &connector->display_info; -+ // void *data = hdmi->plat_data->phy_data; -+ int i, ret = 0; -+ -+ if (!hdmi->ddc) -+ return 0; -+ -+ memset(metedata, 0, sizeof(*metedata)); -+ edid = drm_get_edid(connector, hdmi->ddc); -+ if (edid) { -+ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", -+ edid->width_cm, edid->height_cm); -+ -+ hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ drm_connector_update_edid_property(connector, edid); -+ // if (hdmi->plat_data->get_edid_dsc_info) -+ // hdmi->plat_data->get_edid_dsc_info(data, edid); -+ ret = drm_add_edid_modes(connector, edid); -+ dw_hdmi_update_hdr_property(connector); -+ // if (ret > 0 && hdmi->plat_data->split_mode) { -+ // struct dw_hdmi_qp *secondary = NULL; -+ // void *secondary_data; -+ // -+ // if (hdmi->plat_data->left) -+ // secondary = hdmi->plat_data->left; -+ // else if (hdmi->plat_data->right) -+ // secondary = hdmi->plat_data->right; -+ // -+ // if (!secondary) -+ // return -ENOMEM; -+ // secondary_data = secondary->plat_data->phy_data; -+ // -+ // list_for_each_entry(mode, &connector->probed_modes, head) -+ // hdmi->plat_data->convert_to_split_mode(mode); -+ // -+ // secondary->sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ // if (secondary->plat_data->get_edid_dsc_info) -+ // secondary->plat_data->get_edid_dsc_info(secondary_data, edid); -+ // } -+ kfree(edid); -+ } else { -+ hdmi->sink_is_hdmi = true; -+ -+ if (hdmi->plat_data->split_mode) { -+ if (hdmi->plat_data->left) { -+ hdmi->plat_data->left->sink_is_hdmi = true; -+ } else if (hdmi->plat_data->right) { -+ hdmi->plat_data->right->sink_is_hdmi = true; -+ } -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) { -+ const struct drm_display_mode *ptr = -+ &dw_hdmi_default_modes[i]; -+ -+ mode = drm_mode_duplicate(connector->dev, ptr); -+ if (mode) { -+ if (!i) -+ mode->type = DRM_MODE_TYPE_PREFERRED; -+ drm_mode_probed_add(connector, mode); -+ ret++; -+ } -+ } -+ if (ret > 0 && hdmi->plat_data->split_mode) { -+ struct drm_display_mode *mode; -+ -+ list_for_each_entry(mode, &connector->probed_modes, head) -+ hdmi->plat_data->convert_to_split_mode(mode); -+ } -+ info->edid_hdmi_rgb444_dc_modes = 0; -+ info->hdmi.y420_dc_modes = 0; -+ info->color_formats = 0; -+ -+ dev_info(hdmi->dev, "failed to get edid\n"); -+ } -+ -+ return ret; -+} -+ -+static int -+dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, -+ struct drm_connector_state *state, -+ struct drm_property *property, -+ uint64_t val) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; -+ -+ if (ops && ops->set_property) -+ return ops->set_property(connector, state, property, -+ val, hdmi->plat_data->phy_data); -+ else -+ return -EINVAL; -+} -+ -+static int -+dw_hdmi_atomic_connector_get_property(struct drm_connector *connector, -+ const struct drm_connector_state *state, -+ struct drm_property *property, -+ uint64_t *val) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; -+ -+ if (ops && ops->get_property) -+ return ops->get_property(connector, state, property, -+ val, hdmi->plat_data->phy_data); -+ else -+ return -EINVAL; -+} -+ -+static int -+dw_hdmi_connector_set_property(struct drm_connector *connector, -+ struct drm_property *property, uint64_t val) -+{ -+ return dw_hdmi_atomic_connector_set_property(connector, NULL, -+ property, val); -+} -+ -+static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi) -+{ -+ unsigned int color = MEDIA_BUS_FMT_RGB888_1X24; -+ const struct dw_hdmi_property_ops *ops = -+ hdmi->plat_data->property_ops; -+ -+ if (ops && ops->attach_properties) -+ return ops->attach_properties(&hdmi->connector, color, 0, -+ hdmi->plat_data->phy_data); -+} -+ -+static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi) -+{ -+ const struct dw_hdmi_property_ops *ops = -+ hdmi->plat_data->property_ops; -+ -+ if (ops && ops->destroy_properties) -+ return ops->destroy_properties(&hdmi->connector, -+ hdmi->plat_data->phy_data); -+} -+ -+static struct drm_encoder * -+dw_hdmi_connector_best_encoder(struct drm_connector *connector) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ -+ return hdmi->bridge.encoder; -+} -+ -+static bool dw_hdmi_color_changed(struct drm_connector *connector, -+ struct drm_atomic_state *state) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ void *data = hdmi->plat_data->phy_data; -+ struct drm_connector_state *old_state = -+ drm_atomic_get_old_connector_state(state, connector); -+ struct drm_connector_state *new_state = -+ drm_atomic_get_new_connector_state(state, connector); -+ bool ret = false; -+ -+ if (hdmi->plat_data->get_color_changed) -+ ret = hdmi->plat_data->get_color_changed(data); -+ -+ if (new_state->colorspace != old_state->colorspace) -+ ret = true; -+ -+ return ret; -+} -+ -+static bool hdr_metadata_equal(const struct drm_connector_state *old_state, -+ const struct drm_connector_state *new_state) -+{ -+ struct drm_property_blob *old_blob = old_state->hdr_output_metadata; -+ struct drm_property_blob *new_blob = new_state->hdr_output_metadata; -+ -+ if (!old_blob || !new_blob) -+ return old_blob == new_blob; -+ -+ if (old_blob->length != new_blob->length) -+ return false; -+ -+ return !memcmp(old_blob->data, new_blob->data, old_blob->length); -+} -+ -+static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, -+ struct drm_atomic_state *state) -+{ -+ struct drm_connector_state *old_state = -+ drm_atomic_get_old_connector_state(state, connector); -+ struct drm_connector_state *new_state = -+ drm_atomic_get_new_connector_state(state, connector); -+ struct drm_crtc *crtc = new_state->crtc; -+ struct drm_crtc_state *crtc_state; -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ struct drm_display_mode *mode = NULL; -+ void *data = hdmi->plat_data->phy_data; -+ struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; -+ -+ if (!crtc) -+ return 0; -+ -+ crtc_state = drm_atomic_get_crtc_state(state, crtc); -+ if (IS_ERR(crtc_state)) -+ return PTR_ERR(crtc_state); -+ -+ /* -+ * If HDMI is enabled in uboot, it's need to record -+ * drm_display_mode and set phy status to enabled. -+ */ -+ if (!vmode->mpixelclock) { -+ crtc_state = drm_atomic_get_crtc_state(state, crtc); -+ if (hdmi->plat_data->get_enc_in_encoding) -+ hdmi->hdmi_data.enc_in_encoding = -+ hdmi->plat_data->get_enc_in_encoding(data); -+ if (hdmi->plat_data->get_enc_out_encoding) -+ hdmi->hdmi_data.enc_out_encoding = -+ hdmi->plat_data->get_enc_out_encoding(data); -+ if (hdmi->plat_data->get_input_bus_format) -+ hdmi->hdmi_data.enc_in_bus_format = -+ hdmi->plat_data->get_input_bus_format(data); -+ if (hdmi->plat_data->get_output_bus_format) -+ hdmi->hdmi_data.enc_out_bus_format = -+ hdmi->plat_data->get_output_bus_format(data); -+ -+ mode = &crtc_state->mode; -+ if (hdmi->plat_data->split_mode) { -+ hdmi->plat_data->convert_to_origin_mode(mode); -+ mode->crtc_clock /= 2; -+ } -+ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); -+ vmode->mpixelclock = mode->crtc_clock * 1000; -+ vmode->previous_pixelclock = mode->clock; -+ vmode->previous_tmdsclock = mode->clock; -+ vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, -+ vmode->mpixelclock); -+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -+ vmode->mtmdsclock /= 2; -+ } -+ -+ if (!hdr_metadata_equal(old_state, new_state) || -+ dw_hdmi_color_changed(connector, state)) { -+ crtc_state = drm_atomic_get_crtc_state(state, crtc); -+ if (IS_ERR(crtc_state)) -+ return PTR_ERR(crtc_state); -+ -+ crtc_state->mode_changed = true; -+ } -+ -+ return 0; -+} -+ -+static void dw_hdmi_connector_force(struct drm_connector *connector) -+{ -+ struct dw_hdmi_qp *hdmi = -+ container_of(connector, struct dw_hdmi_qp, connector); -+ -+ mutex_lock(&hdmi->mutex); -+ -+ if (hdmi->force != connector->force) { -+ if (!hdmi->disabled && connector->force == DRM_FORCE_OFF) -+ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, -+ false); -+ else if (hdmi->disabled && connector->force == DRM_FORCE_ON) -+ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, -+ true); -+ } -+ -+ hdmi->force = connector->force; -+ mutex_unlock(&hdmi->mutex); -+} -+ -+static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x, -+ u32 max_y) -+{ -+ return drm_helper_probe_single_connector_modes(connector, 9000, 9000); -+} -+ -+static const struct drm_connector_funcs dw_hdmi_connector_funcs = { -+ .fill_modes = dw_hdmi_qp_fill_modes, -+ .detect = dw_hdmi_connector_detect, -+ .destroy = drm_connector_cleanup, -+ .force = dw_hdmi_connector_force, -+ .reset = drm_atomic_helper_connector_reset, -+ .set_property = dw_hdmi_connector_set_property, -+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -+ .atomic_set_property = dw_hdmi_atomic_connector_set_property, -+ .atomic_get_property = dw_hdmi_atomic_connector_get_property, -+}; -+ -+static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { -+ .get_modes = dw_hdmi_connector_get_modes, -+ .best_encoder = dw_hdmi_connector_best_encoder, -+ .atomic_check = dw_hdmi_connector_atomic_check, -+}; -+ -+static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ struct drm_encoder *encoder = bridge->encoder; -+ struct drm_connector *connector = &hdmi->connector; -+ -+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) -+ return 0; -+ -+ connector->interlace_allowed = 1; -+ connector->polled = DRM_CONNECTOR_POLL_HPD; -+ -+ drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); -+ -+ // [CC:] use drm_connector_init_with_ddc or drmm_connector_init -+ // to provide ddc reference -+ drm_connector_init_with_ddc(bridge->dev, connector, -+ &dw_hdmi_connector_funcs, -+ DRM_MODE_CONNECTOR_HDMIA, -+ hdmi->ddc); -+ -+ drm_connector_attach_encoder(connector, encoder); -+ dw_hdmi_attach_properties(hdmi); -+ -+ return 0; -+} -+ -+static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge, -+ const struct drm_display_mode *orig_mode, -+ const struct drm_display_mode *mode) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ mutex_lock(&hdmi->mutex); -+ -+ /* Store the display mode for plugin/DKMS poweron events */ -+ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); -+ if (hdmi->plat_data->split_mode) -+ hdmi->plat_data->convert_to_origin_mode(&hdmi->previous_mode); -+ -+ mutex_unlock(&hdmi->mutex); -+} -+ -+static enum drm_mode_status -+dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ return MODE_OK; -+} -+ -+static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_state) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ struct drm_atomic_state *state = old_state->base.state; -+ struct drm_connector *connector; -+ -+ connector = drm_atomic_get_new_connector_for_encoder(state, -+ bridge->encoder); -+ -+ mutex_lock(&hdmi->mutex); -+ hdmi->curr_conn = connector; -+ dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); -+ hdmi->disabled = false; -+ mutex_unlock(&hdmi->mutex); -+ -+ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true); -+ handle_plugged_change(hdmi, true); -+} -+ -+static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_state) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false); -+ handle_plugged_change(hdmi, false); -+ mutex_lock(&hdmi->mutex); -+ -+ hdmi->curr_conn = NULL; -+ -+ if (hdmi->phy.ops->disable) -+ hdmi->phy.ops->disable(hdmi, hdmi->phy.data); -+ hdmi->disabled = true; -+ mutex_unlock(&hdmi->mutex); -+} -+ -+static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .attach = dw_hdmi_qp_bridge_attach, -+ .mode_set = dw_hdmi_qp_bridge_mode_set, -+ .mode_valid = dw_hdmi_qp_bridge_mode_valid, -+ .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, -+ .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, -+}; -+ -+static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ u32 stat; -+ -+ stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS); -+ -+ i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | -+ I2CM_NACK_RCVD_IRQ); -+ hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ | -+ SCDC_UPD_FLAGS_CHG_IRQ | -+ SCDC_UPD_FLAGS_CLR_IRQ | -+ SCDC_RR_REPLY_STOP_IRQ | -+ SCDC_NACK_RCVD_IRQ); -+ hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ | -+ FLT_EXIT_TO_LTS4_IRQ | -+ FLT_EXIT_TO_LTSL_IRQ); -+ -+ if (i2c->stat) { -+ hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); -+ complete(&i2c->cmp); -+ } -+ -+ if (hdmi->flt_intr) { -+ dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr); -+ hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR); -+ complete(&hdmi->flt_cmp); -+ } -+ -+ if (hdmi->scdc_intr) { -+ u8 val; -+ -+ dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr); -+ hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR); -+ val = hdmi_readl(hdmi, SCDC_STATUS0); -+ -+ /* frl start */ -+ if (val & BIT(4)) { -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | -+ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); -+ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, -+ MAINUNIT_1_INT_MASK_N); -+ dev_info(hdmi->dev, "frl start\n"); -+ } -+ -+ } -+ -+ if (stat) -+ return IRQ_HANDLED; -+ -+ return IRQ_NONE; -+} -+ -+static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ u32 stat; -+ -+ stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); -+ if (stat) { -+ dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat); -+ stat &= ~stat; -+ hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N); -+ return IRQ_WAKE_THREAD; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ u32 stat; -+ -+ stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); -+ if (stat) { -+ dev_dbg(hdmi->dev, "earc irq %#x\n", stat); -+ stat &= ~stat; -+ hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N); -+ return IRQ_WAKE_THREAD; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ u32 stat; -+ -+ stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); -+ -+ if (!stat) -+ return IRQ_NONE; -+ -+ hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR); -+ -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ u32 stat; -+ -+ stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); -+ -+ if (!stat) -+ return IRQ_NONE; -+ -+ hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR); -+ -+ hdmi->earc_intr = stat; -+ complete(&hdmi->earc_cmp); -+ -+ return IRQ_HANDLED; -+} -+ -+static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) -+{ -+ u8 phy_type; -+ -+ phy_type = hdmi->plat_data->phy_force_vendor ? -+ DW_HDMI_PHY_VENDOR_PHY : 0; -+ -+ if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { -+ /* Vendor PHYs require support from the glue layer. */ -+ if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { -+ dev_err(hdmi->dev, -+ "Vendor HDMI PHY not supported by glue layer\n"); -+ return -ENODEV; -+ } -+ -+ hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; -+ hdmi->phy.data = hdmi->plat_data->phy_data; -+ hdmi->phy.name = hdmi->plat_data->phy_name; -+ } -+ -+ return 0; -+} -+ -+static const struct regmap_config hdmi_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = EARCRX_1_INT_FORCE, -+}; -+ -+struct dw_hdmi_qp_reg_table { -+ int reg_base; -+ int reg_end; -+}; -+ -+static const struct dw_hdmi_qp_reg_table hdmi_reg_table[] = { -+ {0x0, 0xc}, -+ {0x14, 0x1c}, -+ {0x44, 0x48}, -+ {0x50, 0x58}, -+ {0x80, 0x84}, -+ {0xa0, 0xc4}, -+ {0xe0, 0xe8}, -+ {0xf0, 0x118}, -+ {0x140, 0x140}, -+ {0x150, 0x150}, -+ {0x160, 0x168}, -+ {0x180, 0x180}, -+ {0x800, 0x800}, -+ {0x808, 0x808}, -+ {0x814, 0x814}, -+ {0x81c, 0x824}, -+ {0x834, 0x834}, -+ {0x840, 0x864}, -+ {0x86c, 0x86c}, -+ {0x880, 0x89c}, -+ {0x8e0, 0x8e8}, -+ {0x900, 0x900}, -+ {0x908, 0x90c}, -+ {0x920, 0x938}, -+ {0x920, 0x938}, -+ {0x960, 0x960}, -+ {0x968, 0x968}, -+ {0xa20, 0xa20}, -+ {0xa30, 0xa30}, -+ {0xa40, 0xa40}, -+ {0xa54, 0xa54}, -+ {0xa80, 0xaac}, -+ {0xab4, 0xab8}, -+ {0xb00, 0xcbc}, -+ {0xce0, 0xce0}, -+ {0xd00, 0xddc}, -+ {0xe20, 0xe24}, -+ {0xe40, 0xe44}, -+ {0xe4c, 0xe4c}, -+ {0xe60, 0xe80}, -+ {0xea0, 0xf24}, -+ {0x1004, 0x100c}, -+ {0x1020, 0x1030}, -+ {0x1040, 0x1050}, -+ {0x1060, 0x1068}, -+ {0x1800, 0x1820}, -+ {0x182c, 0x182c}, -+ {0x1840, 0x1940}, -+ {0x1960, 0x1a60}, -+ {0x1b00, 0x1b00}, -+ {0x1c00, 0x1c00}, -+ {0x3000, 0x3000}, -+ {0x3010, 0x3014}, -+ {0x3020, 0x3024}, -+ {0x3800, 0x3800}, -+ {0x3810, 0x3814}, -+ {0x3820, 0x3824}, -+ {0x3830, 0x3834}, -+ {0x3840, 0x3844}, -+ {0x3850, 0x3854}, -+ {0x3860, 0x3864}, -+ {0x3870, 0x3874}, -+ {0x4000, 0x4004}, -+ {0x4800, 0x4800}, -+ {0x4810, 0x4814}, -+}; -+ -+static int dw_hdmi_ctrl_show(struct seq_file *s, void *v) -+{ -+ struct dw_hdmi_qp *hdmi = s->private; -+ u32 i = 0, j = 0, val = 0; -+ -+ seq_puts(s, "\n---------------------------------------------------"); -+ -+ for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) { -+ for (j = hdmi_reg_table[i].reg_base; -+ j <= hdmi_reg_table[i].reg_end; j += 4) { -+ val = hdmi_readl(hdmi, j); -+ -+ if ((j - hdmi_reg_table[i].reg_base) % 16 == 0) -+ seq_printf(s, "\n>>>hdmi_ctl %04x:", j); -+ seq_printf(s, " %08x", val); -+ } -+ } -+ seq_puts(s, "\n---------------------------------------------------\n"); -+ -+ return 0; -+} -+ -+static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, dw_hdmi_ctrl_show, inode->i_private); -+} -+ -+static ssize_t -+dw_hdmi_ctrl_write(struct file *file, const char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dw_hdmi_qp *hdmi = -+ ((struct seq_file *)file->private_data)->private; -+ u32 reg, val; -+ char kbuf[25]; -+ -+ if (count > 24) { -+ dev_err(hdmi->dev, "out of buf range\n"); -+ return count; -+ } -+ -+ if (copy_from_user(kbuf, buf, count)) -+ return -EFAULT; -+ kbuf[count - 1] = '\0'; -+ -+ if (sscanf(kbuf, "%x %x", ®, &val) == -1) -+ return -EFAULT; -+ if (reg > EARCRX_1_INT_FORCE) { -+ dev_err(hdmi->dev, "it is no a hdmi register\n"); -+ return count; -+ } -+ dev_info(hdmi->dev, "/**********hdmi register config******/"); -+ dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val); -+ hdmi_writel(hdmi, val, reg); -+ return count; -+} -+ -+static const struct file_operations dw_hdmi_ctrl_fops = { -+ .owner = THIS_MODULE, -+ .open = dw_hdmi_ctrl_open, -+ .read = seq_read, -+ .write = dw_hdmi_ctrl_write, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int dw_hdmi_status_show(struct seq_file *s, void *v) -+{ -+ struct dw_hdmi_qp *hdmi = s->private; -+ u32 val; -+ -+ seq_puts(s, "PHY: "); -+ if (hdmi->disabled) { -+ seq_puts(s, "disabled\n"); -+ return 0; -+ } -+ seq_puts(s, "enabled\t\t\tMode: "); -+ if (hdmi->sink_is_hdmi) -+ seq_puts(s, "HDMI\n"); -+ else -+ seq_puts(s, "DVI\n"); -+ -+ if (hdmi->hdmi_data.video_mode.mpixelclock > 600000000) { -+ seq_printf(s, "FRL Mode Pixel Clk: %luHz\n", -+ hdmi->hdmi_data.video_mode.mpixelclock); -+ } else { -+ if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) -+ val = hdmi->hdmi_data.video_mode.mtmdsclock / 4; -+ else -+ val = hdmi->hdmi_data.video_mode.mtmdsclock; -+ seq_printf(s, "TMDS Mode Pixel Clk: %luHz\t\tTMDS Clk: %uHz\n", -+ hdmi->hdmi_data.video_mode.mpixelclock, val); -+ } -+ -+ seq_puts(s, "Color Format: "); -+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) -+ seq_puts(s, "RGB"); -+ else if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) -+ seq_puts(s, "YUV444"); -+ else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) -+ seq_puts(s, "YUV422"); -+ else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) -+ seq_puts(s, "YUV420"); -+ else -+ seq_puts(s, "UNKNOWN"); -+ val = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); -+ seq_printf(s, "\t\tColor Depth: %d bit\n", val); -+ seq_puts(s, "Colorimetry: "); -+ switch (hdmi->hdmi_data.enc_out_encoding) { -+ case V4L2_YCBCR_ENC_601: -+ seq_puts(s, "ITU.BT601"); -+ break; -+ case V4L2_YCBCR_ENC_709: -+ seq_puts(s, "ITU.BT709"); -+ break; -+ case V4L2_YCBCR_ENC_BT2020: -+ seq_puts(s, "ITU.BT2020"); -+ break; -+ default: /* Carries no data */ -+ seq_puts(s, "ITU.BT601"); -+ break; -+ } -+ -+ seq_puts(s, "\t\tEOTF: "); -+ -+ val = hdmi_readl(hdmi, PKTSCHED_PKT_EN); -+ if (!(val & PKTSCHED_DRMI_TX_EN)) { -+ seq_puts(s, "Off\n"); -+ return 0; -+ } -+ -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); -+ val = (val >> 8) & 0x7; -+ switch (val) { -+ case HDMI_EOTF_TRADITIONAL_GAMMA_SDR: -+ seq_puts(s, "SDR"); -+ break; -+ case HDMI_EOTF_TRADITIONAL_GAMMA_HDR: -+ seq_puts(s, "HDR"); -+ break; -+ case HDMI_EOTF_SMPTE_ST2084: -+ seq_puts(s, "ST2084"); -+ break; -+ case HDMI_EOTF_BT_2100_HLG: -+ seq_puts(s, "HLG"); -+ break; -+ default: -+ seq_puts(s, "Not Defined\n"); -+ return 0; -+ } -+ -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "\nx0: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\t\ty0: %d\n", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "x1: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\t\ty1: %d\n", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "x2: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\t\ty2: %d\n", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "white x: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\twhite y: %d\n", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "max lum: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\tmin lum: %d\n", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); -+ val = (val >> 16) & 0xffff; -+ seq_printf(s, "max cll: %d", val); -+ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS7); -+ val = val & 0xffff; -+ seq_printf(s, "\t\t\tmax fall: %d\n", val); -+ return 0; -+} -+ -+static int dw_hdmi_status_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, dw_hdmi_status_show, inode->i_private); -+} -+ -+static const struct file_operations dw_hdmi_status_fops = { -+ .owner = THIS_MODULE, -+ .open = dw_hdmi_status_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi_qp *hdmi) -+{ -+ u8 buf[11]; -+ -+ snprintf(buf, sizeof(buf), "dw-hdmi%d", hdmi->plat_data->id); -+ hdmi->debugfs_dir = debugfs_create_dir(buf, NULL); -+ if (IS_ERR(hdmi->debugfs_dir)) { -+ dev_err(dev, "failed to create debugfs dir!\n"); -+ return; -+ } -+ -+ debugfs_create_file("status", 0400, hdmi->debugfs_dir, -+ hdmi, &dw_hdmi_status_fops); -+ debugfs_create_file("ctrl", 0600, hdmi->debugfs_dir, -+ hdmi, &dw_hdmi_ctrl_fops); -+} -+ -+static struct dw_hdmi_qp * -+__dw_hdmi_probe(struct platform_device *pdev, -+ const struct dw_hdmi_plat_data *plat_data) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct device_node *ddc_node; -+ struct dw_hdmi_qp *hdmi; -+ struct resource *iores = NULL; -+ int irq; -+ int ret; -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return ERR_PTR(-ENOMEM); -+ -+ hdmi->connector.stereo_allowed = 1; -+ hdmi->plat_data = plat_data; -+ hdmi->dev = dev; -+ hdmi->disabled = true; -+ -+ mutex_init(&hdmi->mutex); -+ -+ ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); -+ if (ddc_node) { -+ hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); -+ of_node_put(ddc_node); -+ if (!hdmi->ddc) { -+ dev_dbg(hdmi->dev, "failed to read ddc node\n"); -+ return ERR_PTR(-EPROBE_DEFER); -+ } -+ -+ } else { -+ dev_dbg(hdmi->dev, "no ddc property found\n"); -+ } -+ -+ if (!plat_data->regm) { -+ const struct regmap_config *reg_config; -+ -+ reg_config = &hdmi_regmap_config; -+ -+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ hdmi->regs = devm_ioremap_resource(dev, iores); -+ if (IS_ERR(hdmi->regs)) { -+ ret = PTR_ERR(hdmi->regs); -+ goto err_res; -+ } -+ -+ hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); -+ if (IS_ERR(hdmi->regm)) { -+ dev_err(dev, "Failed to configure regmap\n"); -+ ret = PTR_ERR(hdmi->regm); -+ goto err_res; -+ } -+ } else { -+ hdmi->regm = plat_data->regm; -+ } -+ -+ ret = dw_hdmi_detect_phy(hdmi); -+ if (ret < 0) -+ goto err_res; -+ -+ hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); -+ hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); -+ hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); -+ if ((hdmi_readl(hdmi, CMU_STATUS) & DISPLAY_CLK_MONITOR) == DISPLAY_CLK_LOCKED) { -+ hdmi->initialized = true; -+ hdmi->disabled = false; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ ret = irq; -+ goto err_res; -+ } -+ -+ hdmi->avp_irq = irq; -+ ret = devm_request_threaded_irq(dev, hdmi->avp_irq, -+ dw_hdmi_qp_avp_hardirq, -+ dw_hdmi_qp_avp_irq, IRQF_SHARED, -+ dev_name(dev), hdmi); -+ if (ret) -+ goto err_res; -+ -+ irq = platform_get_irq(pdev, 1); -+ if (irq < 0) { -+ ret = irq; -+ goto err_res; -+ } -+ -+ irq = platform_get_irq(pdev, 2); -+ if (irq < 0) { -+ ret = irq; -+ goto err_res; -+ } -+ -+ hdmi->earc_irq = irq; -+ ret = devm_request_threaded_irq(dev, hdmi->earc_irq, -+ dw_hdmi_qp_earc_hardirq, -+ dw_hdmi_qp_earc_irq, IRQF_SHARED, -+ dev_name(dev), hdmi); -+ if (ret) -+ goto err_res; -+ -+ irq = platform_get_irq(pdev, 3); -+ if (irq < 0) { -+ ret = irq; -+ goto err_res; -+ } -+ -+ hdmi->main_irq = irq; -+ ret = devm_request_threaded_irq(dev, hdmi->main_irq, -+ dw_hdmi_qp_main_hardirq, NULL, -+ IRQF_SHARED, dev_name(dev), hdmi); -+ if (ret) -+ goto err_res; -+ -+ /* If DDC bus is not specified, try to register HDMI I2C bus */ -+ if (!hdmi->ddc) { -+ hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); -+ if (IS_ERR(hdmi->ddc)) -+ hdmi->ddc = NULL; -+ /* -+ * Read high and low time from device tree. If not available use -+ * the default timing scl clock rate is about 99.6KHz. -+ */ -+ if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns", -+ &hdmi->i2c->scl_high_ns)) -+ hdmi->i2c->scl_high_ns = 4708; -+ if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns", -+ &hdmi->i2c->scl_low_ns)) -+ hdmi->i2c->scl_low_ns = 4916; -+ } -+ -+ hdmi->bridge.driver_private = hdmi; -+ hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; -+#ifdef CONFIG_OF -+ hdmi->bridge.of_node = pdev->dev.of_node; -+#endif -+ -+ if (hdmi->phy.ops->setup_hpd) -+ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); -+ -+ hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed; -+ -+ hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable); -+ if (IS_ERR(hdmi->extcon)) { -+ dev_err(hdmi->dev, "allocate extcon failed\n"); -+ ret = PTR_ERR(hdmi->extcon); -+ goto err_res; -+ } -+ -+ ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon); -+ if (ret) { -+ dev_err(hdmi->dev, "failed to register extcon: %d\n", ret); -+ goto err_res; -+ } -+ -+ ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI, -+ EXTCON_PROP_DISP_HPD); -+ if (ret) { -+ dev_err(hdmi->dev, -+ "failed to set USB property capability: %d\n", ret); -+ goto err_res; -+ } -+ -+ /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ -+ if (hdmi->i2c) -+ dw_hdmi_i2c_init(hdmi); -+ -+ init_completion(&hdmi->flt_cmp); -+ init_completion(&hdmi->earc_cmp); -+ -+ if (of_property_read_bool(np, "scramble-low-rates")) -+ hdmi->scramble_low_rates = true; -+ -+ dw_hdmi_register_debugfs(dev, hdmi); -+ -+ return hdmi; -+ -+err_res: -+ if (hdmi->i2c) -+ i2c_del_adapter(&hdmi->i2c->adap); -+ else -+ i2c_put_adapter(hdmi->ddc); -+ -+ return ERR_PTR(ret); -+} -+ -+static void __dw_hdmi_remove(struct dw_hdmi_qp *hdmi) -+{ -+ if (hdmi->avp_irq) -+ disable_irq(hdmi->avp_irq); -+ -+ if (hdmi->main_irq) -+ disable_irq(hdmi->main_irq); -+ -+ if (hdmi->earc_irq) -+ disable_irq(hdmi->earc_irq); -+ -+ debugfs_remove_recursive(hdmi->debugfs_dir); -+ -+ if (!hdmi->plat_data->first_screen) { -+ dw_hdmi_destroy_properties(hdmi); -+ hdmi->connector.funcs->destroy(&hdmi->connector); -+ } -+ -+ if (hdmi->audio && !IS_ERR(hdmi->audio)) -+ platform_device_unregister(hdmi->audio); -+ -+ // [CC:] dw_hdmi_rockchip_unbind() also calls drm_encoder_cleanup() -+ // and causes a seg fault due to NULL ptr dererence -+ // if (hdmi->bridge.encoder && !hdmi->plat_data->first_screen) -+ // hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder); -+ // -+ if (!IS_ERR(hdmi->cec)) -+ platform_device_unregister(hdmi->cec); -+ if (hdmi->i2c) -+ i2c_del_adapter(&hdmi->i2c->adap); -+ else -+ i2c_put_adapter(hdmi->ddc); -+} -+ -+/* ----------------------------------------------------------------------------- -+ * Bind/unbind API, used from platforms based on the component framework. -+ */ -+struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, -+ struct drm_encoder *encoder, -+ struct dw_hdmi_plat_data *plat_data) -+{ -+ struct dw_hdmi_qp *hdmi; -+ int ret; -+ -+ hdmi = __dw_hdmi_probe(pdev, plat_data); -+ if (IS_ERR(hdmi)) -+ return hdmi; -+ -+ if (!plat_data->first_screen) { -+ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); -+ if (ret) { -+ __dw_hdmi_remove(hdmi); -+ dev_err(hdmi->dev, "Failed to initialize bridge with drm\n"); -+ return ERR_PTR(ret); -+ } -+ -+ plat_data->connector = &hdmi->connector; -+ } -+ -+ if (plat_data->split_mode && !hdmi->plat_data->first_screen) { -+ struct dw_hdmi_qp *secondary = NULL; -+ -+ if (hdmi->plat_data->left) -+ secondary = hdmi->plat_data->left; -+ else if (hdmi->plat_data->right) -+ secondary = hdmi->plat_data->right; -+ -+ if (!secondary) -+ return ERR_PTR(-ENOMEM); -+ ret = drm_bridge_attach(encoder, &secondary->bridge, &hdmi->bridge, -+ DRM_BRIDGE_ATTACH_NO_CONNECTOR); -+ if (ret) -+ return ERR_PTR(ret); -+ } -+ -+ return hdmi; -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); -+ -+void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi) -+{ -+ __dw_hdmi_remove(hdmi); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind); -+ -+void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) -+{ -+ if (!hdmi) { -+ dev_warn(dev, "Hdmi has not been initialized\n"); -+ return; -+ } -+ -+ mutex_lock(&hdmi->mutex); -+ -+ /* -+ * When system shutdown, hdmi should be disabled. -+ * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first. -+ * To prevent duplicate operation, we should determine whether hdmi -+ * has been disabled. -+ */ -+ if (!hdmi->disabled) -+ hdmi->disabled = true; -+ mutex_unlock(&hdmi->mutex); -+ -+ if (hdmi->avp_irq) -+ disable_irq(hdmi->avp_irq); -+ -+ if (hdmi->main_irq) -+ disable_irq(hdmi->main_irq); -+ -+ if (hdmi->earc_irq) -+ disable_irq(hdmi->earc_irq); -+ -+ pinctrl_pm_select_sleep_state(dev); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); -+ -+void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) -+{ -+ if (!hdmi) { -+ dev_warn(dev, "Hdmi has not been initialized\n"); -+ return; -+ } -+ -+ hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); -+ hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); -+ hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); -+ -+ pinctrl_pm_select_default_state(dev); -+ -+ mutex_lock(&hdmi->mutex); -+ if (hdmi->i2c) -+ dw_hdmi_i2c_init(hdmi); -+ if (hdmi->avp_irq) -+ enable_irq(hdmi->avp_irq); -+ -+ if (hdmi->main_irq) -+ enable_irq(hdmi->main_irq); -+ -+ if (hdmi->earc_irq) -+ enable_irq(hdmi->earc_irq); -+ -+ mutex_unlock(&hdmi->mutex); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); -+ -+MODULE_AUTHOR("Algea Cao "); -+MODULE_DESCRIPTION("DW HDMI QP transmitter driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:dw-hdmi-qp"); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h -@@ -0,0 +1,831 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) Rockchip Electronics Co.Ltd -+ * Author: -+ * Algea Cao -+ */ -+#ifndef __DW_HDMI_QP_H__ -+#define __DW_HDMI_QP_H__ -+/* Main Unit Registers */ -+#define CORE_ID 0x0 -+#define VER_NUMBER 0x4 -+#define VER_TYPE 0x8 -+#define CONFIG_REG 0xc -+#define CONFIG_CEC BIT(28) -+#define CONFIG_AUD_UD BIT(23) -+#define CORE_TIMESTAMP_HHMM 0x14 -+#define CORE_TIMESTAMP_MMDD 0x18 -+#define CORE_TIMESTAMP_YYYY 0x1c -+/* Reset Manager Registers */ -+#define GLOBAL_SWRESET_REQUEST 0x40 -+#define EARCRX_CMDC_SWINIT_P BIT(27) -+#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) -+#define GLOBAL_SWDISABLE 0x44 -+#define CEC_SWDISABLE BIT(17) -+#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) -+#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) -+#define RESET_MANAGER_CONFIG0 0x48 -+#define RESET_MANAGER_STATUS0 0x50 -+#define RESET_MANAGER_STATUS1 0x54 -+#define RESET_MANAGER_STATUS2 0x58 -+/* Timer Base Registers */ -+#define TIMER_BASE_CONFIG0 0x80 -+#define TIMER_BASE_STATUS0 0x84 -+/* CMU Registers */ -+#define CMU_CONFIG0 0xa0 -+#define CMU_CONFIG1 0xa4 -+#define CMU_CONFIG2 0xa8 -+#define CMU_CONFIG3 0xac -+#define CMU_STATUS 0xb0 -+#define DISPLAY_CLK_MONITOR 0x3f -+#define DISPLAY_CLK_LOCKED 0X15 -+#define EARC_BPCLK_OFF BIT(9) -+#define AUDCLK_OFF BIT(7) -+#define LINKQPCLK_OFF BIT(5) -+#define VIDQPCLK_OFF BIT(3) -+#define IPI_CLK_OFF BIT(1) -+#define CMU_IPI_CLK_FREQ 0xb4 -+#define CMU_VIDQPCLK_FREQ 0xb8 -+#define CMU_LINKQPCLK_FREQ 0xbc -+#define CMU_AUDQPCLK_FREQ 0xc0 -+#define CMU_EARC_BPCLK_FREQ 0xc4 -+/* I2CM Registers */ -+#define I2CM_SM_SCL_CONFIG0 0xe0 -+#define I2CM_FM_SCL_CONFIG0 0xe4 -+#define I2CM_CONFIG0 0xe8 -+#define I2CM_CONTROL0 0xec -+#define I2CM_STATUS0 0xf0 -+#define I2CM_INTERFACE_CONTROL0 0xf4 -+#define I2CM_ADDR 0xff000 -+#define I2CM_SLVADDR 0xfe0 -+#define I2CM_WR_MASK 0x1e -+#define I2CM_EXT_READ BIT(4) -+#define I2CM_SHORT_READ BIT(3) -+#define I2CM_FM_READ BIT(2) -+#define I2CM_FM_WRITE BIT(1) -+#define I2CM_FM_EN BIT(0) -+#define I2CM_INTERFACE_CONTROL1 0xf8 -+#define I2CM_SEG_PTR 0x7f80 -+#define I2CM_SEG_ADDR 0x7f -+#define I2CM_INTERFACE_WRDATA_0_3 0xfc -+#define I2CM_INTERFACE_WRDATA_4_7 0x100 -+#define I2CM_INTERFACE_WRDATA_8_11 0x104 -+#define I2CM_INTERFACE_WRDATA_12_15 0x108 -+#define I2CM_INTERFACE_RDDATA_0_3 0x10c -+#define I2CM_INTERFACE_RDDATA_4_7 0x110 -+#define I2CM_INTERFACE_RDDATA_8_11 0x114 -+#define I2CM_INTERFACE_RDDATA_12_15 0x118 -+/* SCDC Registers */ -+#define SCDC_CONFIG0 0x140 -+#define SCDC_I2C_FM_EN BIT(12) -+#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) -+#define SCDC_UPD_FLAGS_POLL_EN BIT(4) -+#define SCDC_CONTROL0 0x148 -+#define SCDC_STATUS0 0x150 -+#define STATUS_UPDATE BIT(0) -+#define FRL_START BIT(4) -+#define FLT_UPDATE BIT(5) -+/* FLT Registers */ -+#define FLT_CONFIG0 0x160 -+#define FLT_CONFIG1 0x164 -+#define FLT_CONFIG2 0x168 -+#define FLT_CONTROL0 0x170 -+/* Main Unit 2 Registers */ -+#define MAINUNIT_STATUS0 0x180 -+/* Video Interface Registers */ -+#define VIDEO_INTERFACE_CONFIG0 0x800 -+#define VIDEO_INTERFACE_CONFIG1 0x804 -+#define VIDEO_INTERFACE_CONFIG2 0x808 -+#define VIDEO_INTERFACE_CONTROL0 0x80c -+#define VIDEO_INTERFACE_STATUS0 0x814 -+/* Video Packing Registers */ -+#define VIDEO_PACKING_CONFIG0 0x81c -+/* Audio Interface Registers */ -+#define AUDIO_INTERFACE_CONFIG0 0x820 -+#define AUD_IF_SEL_MSK 0x3 -+#define AUD_IF_SPDIF 0x2 -+#define AUD_IF_I2S 0x1 -+#define AUD_IF_PAI 0x0 -+#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) -+#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) -+#define I2S_LINES_EN_MSK GENMASK(7, 4) -+#define I2S_LINES_EN(x) BIT(x + 4) -+#define I2S_BPCUV_RCV_MSK BIT(12) -+#define I2S_BPCUV_RCV_EN BIT(12) -+#define I2S_BPCUV_RCV_DIS 0 -+#define SPDIF_LINES_EN GENMASK(19, 16) -+#define AUD_FORMAT_MSK GENMASK(26, 24) -+#define AUD_3DOBA (0x7 << 24) -+#define AUD_3DASP (0x6 << 24) -+#define AUD_MSOBA (0x5 << 24) -+#define AUD_MSASP (0x4 << 24) -+#define AUD_HBR (0x3 << 24) -+#define AUD_DST (0x2 << 24) -+#define AUD_OBA (0x1 << 24) -+#define AUD_ASP (0x0 << 24) -+#define AUDIO_INTERFACE_CONFIG1 0x824 -+#define AUDIO_INTERFACE_CONTROL0 0x82c -+#define AUDIO_FIFO_CLR_P BIT(0) -+#define AUDIO_INTERFACE_STATUS0 0x834 -+/* Frame Composer Registers */ -+#define FRAME_COMPOSER_CONFIG0 0x840 -+#define FRAME_COMPOSER_CONFIG1 0x844 -+#define FRAME_COMPOSER_CONFIG2 0x848 -+#define FRAME_COMPOSER_CONFIG3 0x84c -+#define FRAME_COMPOSER_CONFIG4 0x850 -+#define FRAME_COMPOSER_CONFIG5 0x854 -+#define FRAME_COMPOSER_CONFIG6 0x858 -+#define FRAME_COMPOSER_CONFIG7 0x85c -+#define FRAME_COMPOSER_CONFIG8 0x860 -+#define FRAME_COMPOSER_CONFIG9 0x864 -+#define FRAME_COMPOSER_CONTROL0 0x86c -+/* Video Monitor Registers */ -+#define VIDEO_MONITOR_CONFIG0 0x880 -+#define VIDEO_MONITOR_STATUS0 0x884 -+#define VIDEO_MONITOR_STATUS1 0x888 -+#define VIDEO_MONITOR_STATUS2 0x88c -+#define VIDEO_MONITOR_STATUS3 0x890 -+#define VIDEO_MONITOR_STATUS4 0x894 -+#define VIDEO_MONITOR_STATUS5 0x898 -+#define VIDEO_MONITOR_STATUS6 0x89c -+/* HDCP2 Logic Registers */ -+#define HDCP2LOGIC_CONFIG0 0x8e0 -+#define HDCP2_BYPASS BIT(0) -+#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 -+#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 -+/* HDCP14 Registers */ -+#define HDCP14_CONFIG0 0x900 -+#define HDCP14_CONFIG1 0x904 -+#define HDCP14_CONFIG2 0x908 -+#define HDCP14_CONFIG3 0x90c -+#define HDCP14_KEY_SEED 0x914 -+#define HDCP14_KEY_H 0x918 -+#define HDCP14_KEY_L 0x91c -+#define HDCP14_KEY_STATUS 0x920 -+#define HDCP14_AKSV_H 0x924 -+#define HDCP14_AKSV_L 0x928 -+#define HDCP14_AN_H 0x92c -+#define HDCP14_AN_L 0x930 -+#define HDCP14_STATUS0 0x934 -+#define HDCP14_STATUS1 0x938 -+/* Scrambler Registers */ -+#define SCRAMB_CONFIG0 0x960 -+/* Video Configuration Registers */ -+#define LINK_CONFIG0 0x968 -+#define OPMODE_FRL_4LANES BIT(8) -+#define OPMODE_DVI BIT(4) -+#define OPMODE_FRL BIT(0) -+/* TMDS FIFO Registers */ -+#define TMDS_FIFO_CONFIG0 0x970 -+#define TMDS_FIFO_CONTROL0 0x974 -+/* FRL RSFEC Registers */ -+#define FRL_RSFEC_CONFIG0 0xa20 -+#define FRL_RSFEC_STATUS0 0xa30 -+/* FRL Packetizer Registers */ -+#define FRL_PKTZ_CONFIG0 0xa40 -+#define FRL_PKTZ_CONTROL0 0xa44 -+#define FRL_PKTZ_CONTROL1 0xa50 -+#define FRL_PKTZ_STATUS1 0xa54 -+/* Packet Scheduler Registers */ -+#define PKTSCHED_CONFIG0 0xa80 -+#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 -+#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 -+#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c -+#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 -+#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 -+#define PKTSCHED_PKT_CONFIG0 0xa98 -+#define PKTSCHED_PKT_CONFIG1 0xa9c -+#define PKTSCHED_DRMI_FIELDRATE BIT(13) -+#define PKTSCHED_AVI_FIELDRATE BIT(12) -+#define PKTSCHED_PKT_CONFIG2 0xaa0 -+#define PKTSCHED_PKT_CONFIG3 0xaa4 -+#define PKTSCHED_PKT_EN 0xaa8 -+#define PKTSCHED_DRMI_TX_EN BIT(17) -+#define PKTSCHED_AUDI_TX_EN BIT(15) -+#define PKTSCHED_AVI_TX_EN BIT(13) -+#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) -+#define PKTSCHED_AMD_TX_EN BIT(8) -+#define PKTSCHED_GCP_TX_EN BIT(3) -+#define PKTSCHED_AUDS_TX_EN BIT(2) -+#define PKTSCHED_ACR_TX_EN BIT(1) -+#define PKTSCHED_NULL_TX_EN BIT(0) -+#define PKTSCHED_PKT_CONTROL0 0xaac -+#define PKTSCHED_PKT_SEND 0xab0 -+#define PKTSCHED_PKT_STATUS0 0xab4 -+#define PKTSCHED_PKT_STATUS1 0xab8 -+#define PKT_NULL_CONTENTS0 0xb00 -+#define PKT_NULL_CONTENTS1 0xb04 -+#define PKT_NULL_CONTENTS2 0xb08 -+#define PKT_NULL_CONTENTS3 0xb0c -+#define PKT_NULL_CONTENTS4 0xb10 -+#define PKT_NULL_CONTENTS5 0xb14 -+#define PKT_NULL_CONTENTS6 0xb18 -+#define PKT_NULL_CONTENTS7 0xb1c -+#define PKT_ACP_CONTENTS0 0xb20 -+#define PKT_ACP_CONTENTS1 0xb24 -+#define PKT_ACP_CONTENTS2 0xb28 -+#define PKT_ACP_CONTENTS3 0xb2c -+#define PKT_ACP_CONTENTS4 0xb30 -+#define PKT_ACP_CONTENTS5 0xb34 -+#define PKT_ACP_CONTENTS6 0xb38 -+#define PKT_ACP_CONTENTS7 0xb3c -+#define PKT_ISRC1_CONTENTS0 0xb40 -+#define PKT_ISRC1_CONTENTS1 0xb44 -+#define PKT_ISRC1_CONTENTS2 0xb48 -+#define PKT_ISRC1_CONTENTS3 0xb4c -+#define PKT_ISRC1_CONTENTS4 0xb50 -+#define PKT_ISRC1_CONTENTS5 0xb54 -+#define PKT_ISRC1_CONTENTS6 0xb58 -+#define PKT_ISRC1_CONTENTS7 0xb5c -+#define PKT_ISRC2_CONTENTS0 0xb60 -+#define PKT_ISRC2_CONTENTS1 0xb64 -+#define PKT_ISRC2_CONTENTS2 0xb68 -+#define PKT_ISRC2_CONTENTS3 0xb6c -+#define PKT_ISRC2_CONTENTS4 0xb70 -+#define PKT_ISRC2_CONTENTS5 0xb74 -+#define PKT_ISRC2_CONTENTS6 0xb78 -+#define PKT_ISRC2_CONTENTS7 0xb7c -+#define PKT_GMD_CONTENTS0 0xb80 -+#define PKT_GMD_CONTENTS1 0xb84 -+#define PKT_GMD_CONTENTS2 0xb88 -+#define PKT_GMD_CONTENTS3 0xb8c -+#define PKT_GMD_CONTENTS4 0xb90 -+#define PKT_GMD_CONTENTS5 0xb94 -+#define PKT_GMD_CONTENTS6 0xb98 -+#define PKT_GMD_CONTENTS7 0xb9c -+#define PKT_AMD_CONTENTS0 0xba0 -+#define PKT_AMD_CONTENTS1 0xba4 -+#define PKT_AMD_CONTENTS2 0xba8 -+#define PKT_AMD_CONTENTS3 0xbac -+#define PKT_AMD_CONTENTS4 0xbb0 -+#define PKT_AMD_CONTENTS5 0xbb4 -+#define PKT_AMD_CONTENTS6 0xbb8 -+#define PKT_AMD_CONTENTS7 0xbbc -+#define PKT_VSI_CONTENTS0 0xbc0 -+#define PKT_VSI_CONTENTS1 0xbc4 -+#define PKT_VSI_CONTENTS2 0xbc8 -+#define PKT_VSI_CONTENTS3 0xbcc -+#define PKT_VSI_CONTENTS4 0xbd0 -+#define PKT_VSI_CONTENTS5 0xbd4 -+#define PKT_VSI_CONTENTS6 0xbd8 -+#define PKT_VSI_CONTENTS7 0xbdc -+#define PKT_AVI_CONTENTS0 0xbe0 -+#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) -+#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 -+#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 -+#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 -+#define PKT_AVI_CONTENTS1 0xbe4 -+#define PKT_AVI_CONTENTS2 0xbe8 -+#define PKT_AVI_CONTENTS3 0xbec -+#define PKT_AVI_CONTENTS4 0xbf0 -+#define PKT_AVI_CONTENTS5 0xbf4 -+#define PKT_AVI_CONTENTS6 0xbf8 -+#define PKT_AVI_CONTENTS7 0xbfc -+#define PKT_SPDI_CONTENTS0 0xc00 -+#define PKT_SPDI_CONTENTS1 0xc04 -+#define PKT_SPDI_CONTENTS2 0xc08 -+#define PKT_SPDI_CONTENTS3 0xc0c -+#define PKT_SPDI_CONTENTS4 0xc10 -+#define PKT_SPDI_CONTENTS5 0xc14 -+#define PKT_SPDI_CONTENTS6 0xc18 -+#define PKT_SPDI_CONTENTS7 0xc1c -+#define PKT_AUDI_CONTENTS0 0xc20 -+#define PKT_AUDI_CONTENTS1 0xc24 -+#define PKT_AUDI_CONTENTS2 0xc28 -+#define PKT_AUDI_CONTENTS3 0xc2c -+#define PKT_AUDI_CONTENTS4 0xc30 -+#define PKT_AUDI_CONTENTS5 0xc34 -+#define PKT_AUDI_CONTENTS6 0xc38 -+#define PKT_AUDI_CONTENTS7 0xc3c -+#define PKT_NVI_CONTENTS0 0xc40 -+#define PKT_NVI_CONTENTS1 0xc44 -+#define PKT_NVI_CONTENTS2 0xc48 -+#define PKT_NVI_CONTENTS3 0xc4c -+#define PKT_NVI_CONTENTS4 0xc50 -+#define PKT_NVI_CONTENTS5 0xc54 -+#define PKT_NVI_CONTENTS6 0xc58 -+#define PKT_NVI_CONTENTS7 0xc5c -+#define PKT_DRMI_CONTENTS0 0xc60 -+#define PKT_DRMI_CONTENTS1 0xc64 -+#define PKT_DRMI_CONTENTS2 0xc68 -+#define PKT_DRMI_CONTENTS3 0xc6c -+#define PKT_DRMI_CONTENTS4 0xc70 -+#define PKT_DRMI_CONTENTS5 0xc74 -+#define PKT_DRMI_CONTENTS6 0xc78 -+#define PKT_DRMI_CONTENTS7 0xc7c -+#define PKT_GHDMI1_CONTENTS0 0xc80 -+#define PKT_GHDMI1_CONTENTS1 0xc84 -+#define PKT_GHDMI1_CONTENTS2 0xc88 -+#define PKT_GHDMI1_CONTENTS3 0xc8c -+#define PKT_GHDMI1_CONTENTS4 0xc90 -+#define PKT_GHDMI1_CONTENTS5 0xc94 -+#define PKT_GHDMI1_CONTENTS6 0xc98 -+#define PKT_GHDMI1_CONTENTS7 0xc9c -+#define PKT_GHDMI2_CONTENTS0 0xca0 -+#define PKT_GHDMI2_CONTENTS1 0xca4 -+#define PKT_GHDMI2_CONTENTS2 0xca8 -+#define PKT_GHDMI2_CONTENTS3 0xcac -+#define PKT_GHDMI2_CONTENTS4 0xcb0 -+#define PKT_GHDMI2_CONTENTS5 0xcb4 -+#define PKT_GHDMI2_CONTENTS6 0xcb8 -+#define PKT_GHDMI2_CONTENTS7 0xcbc -+/* EMP Packetizer Registers */ -+#define PKT_EMP_CONFIG0 0xce0 -+#define PKT_EMP_CONTROL0 0xcec -+#define PKT_EMP_CONTROL1 0xcf0 -+#define PKT_EMP_CONTROL2 0xcf4 -+#define PKT_EMP_VTEM_CONTENTS0 0xd00 -+#define PKT_EMP_VTEM_CONTENTS1 0xd04 -+#define PKT_EMP_VTEM_CONTENTS2 0xd08 -+#define PKT_EMP_VTEM_CONTENTS3 0xd0c -+#define PKT_EMP_VTEM_CONTENTS4 0xd10 -+#define PKT_EMP_VTEM_CONTENTS5 0xd14 -+#define PKT_EMP_VTEM_CONTENTS6 0xd18 -+#define PKT_EMP_VTEM_CONTENTS7 0xd1c -+#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 -+#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 -+#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 -+#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c -+#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 -+#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 -+#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 -+#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c -+#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 -+#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 -+#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 -+#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c -+#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 -+#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 -+#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 -+#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c -+#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 -+#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 -+#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 -+#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c -+#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 -+#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 -+#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 -+#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c -+#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 -+#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 -+#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 -+#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c -+#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 -+#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 -+#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 -+#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c -+#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 -+#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 -+#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 -+#define PKT4_EMP_CVTEM_CONTENTS3 0xdac -+#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 -+#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 -+#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 -+#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc -+#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 -+#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 -+#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 -+#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc -+#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 -+#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 -+#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 -+#define PKT5_EMP_CVTEM_CONTENTS7 0xddc -+/* Audio Packetizer Registers */ -+#define AUDPKT_CONTROL0 0xe20 -+#define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) -+#define AUDPKT_PBIT_FORCE_EN BIT(12) -+#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) -+#define AUDPKT_CHSTATUS_OVR_EN BIT(0) -+#define AUDPKT_CONTROL1 0xe24 -+#define AUDPKT_ACR_CONTROL0 0xe40 -+#define AUDPKT_ACR_N_VALUE 0xfffff -+#define AUDPKT_ACR_CONTROL1 0xe44 -+#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) -+#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) -+#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) -+#define AUDPKT_ACR_CTS_OVR_EN BIT(1) -+#define AUDPKT_ACR_STATUS0 0xe4c -+#define AUDPKT_CHSTATUS_OVR0 0xe60 -+#define AUDPKT_CHSTATUS_OVR1 0xe64 -+/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ -+#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) -+#define AUDPKT_CHSTATUS_SR_22050 0x4 -+#define AUDPKT_CHSTATUS_SR_24000 0x6 -+#define AUDPKT_CHSTATUS_SR_32000 0x3 -+#define AUDPKT_CHSTATUS_SR_44100 0x0 -+#define AUDPKT_CHSTATUS_SR_48000 0x2 -+#define AUDPKT_CHSTATUS_SR_88200 0x8 -+#define AUDPKT_CHSTATUS_SR_96000 0xa -+#define AUDPKT_CHSTATUS_SR_176400 0xc -+#define AUDPKT_CHSTATUS_SR_192000 0xe -+#define AUDPKT_CHSTATUS_SR_768000 0x9 -+#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 -+/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ -+#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) -+#define AUDPKT_CHSTATUS_OSR_8000 0x6 -+#define AUDPKT_CHSTATUS_OSR_11025 0xa -+#define AUDPKT_CHSTATUS_OSR_12000 0x2 -+#define AUDPKT_CHSTATUS_OSR_16000 0x8 -+#define AUDPKT_CHSTATUS_OSR_22050 0xb -+#define AUDPKT_CHSTATUS_OSR_24000 0x9 -+#define AUDPKT_CHSTATUS_OSR_32000 0xc -+#define AUDPKT_CHSTATUS_OSR_44100 0xf -+#define AUDPKT_CHSTATUS_OSR_48000 0xd -+#define AUDPKT_CHSTATUS_OSR_88200 0x7 -+#define AUDPKT_CHSTATUS_OSR_96000 0x5 -+#define AUDPKT_CHSTATUS_OSR_176400 0x3 -+#define AUDPKT_CHSTATUS_OSR_192000 0x1 -+#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 -+#define AUDPKT_CHSTATUS_OVR2 0xe68 -+#define AUDPKT_CHSTATUS_OVR3 0xe6c -+#define AUDPKT_CHSTATUS_OVR4 0xe70 -+#define AUDPKT_CHSTATUS_OVR5 0xe74 -+#define AUDPKT_CHSTATUS_OVR6 0xe78 -+#define AUDPKT_CHSTATUS_OVR7 0xe7c -+#define AUDPKT_CHSTATUS_OVR8 0xe80 -+#define AUDPKT_CHSTATUS_OVR9 0xe84 -+#define AUDPKT_CHSTATUS_OVR10 0xe88 -+#define AUDPKT_CHSTATUS_OVR11 0xe8c -+#define AUDPKT_CHSTATUS_OVR12 0xe90 -+#define AUDPKT_CHSTATUS_OVR13 0xe94 -+#define AUDPKT_CHSTATUS_OVR14 0xe98 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 -+#define AUDPKT_VBIT_OVR0 0xf24 -+/* CEC Registers */ -+#define CEC_TX_CONTROL 0x1000 -+#define CEC_STATUS 0x1004 -+#define CEC_CONFIG 0x1008 -+#define CEC_ADDR 0x100c -+#define CEC_TX_COUNT 0x1020 -+#define CEC_TX_DATA3_0 0x1024 -+#define CEC_TX_DATA7_4 0x1028 -+#define CEC_TX_DATA11_8 0x102c -+#define CEC_TX_DATA15_12 0x1030 -+#define CEC_RX_COUNT_STATUS 0x1040 -+#define CEC_RX_DATA3_0 0x1044 -+#define CEC_RX_DATA7_4 0x1048 -+#define CEC_RX_DATA11_8 0x104c -+#define CEC_RX_DATA15_12 0x1050 -+#define CEC_LOCK_CONTROL 0x1054 -+#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 -+#define CEC_RX_BITTIME_CONFIG 0x1064 -+#define CEC_TX_BITTIME_CONFIG 0x1068 -+/* eARC RX CMDC Registers */ -+#define EARCRX_CMDC_CONFIG0 0x1800 -+#define EARCRX_XACTREAD_STOP_CFG BIT(26) -+#define EARCRX_XACTREAD_RETRY_CFG BIT(25) -+#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) -+#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) -+#define EARCRX_CMDC_CONFIG1 0x1804 -+#define EARCRX_CMDC_CONTROL 0x1808 -+#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) -+#define EARCRX_CMDC_DISCOVERY_EN BIT(3) -+#define EARCRX_CONNECTOR_HPD BIT(1) -+#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c -+#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 -+#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 -+#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 -+#define EARCRX_CMDC_STATUS 0x181c -+#define EARCRX_CMDC_XACT_INFO 0x1820 -+#define EARCRX_CMDC_XACT_ACTION 0x1824 -+#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 -+#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c -+#define EARCRX_CMDC_XACT_WR0 0x1840 -+#define EARCRX_CMDC_XACT_WR1 0x1844 -+#define EARCRX_CMDC_XACT_WR2 0x1848 -+#define EARCRX_CMDC_XACT_WR3 0x184c -+#define EARCRX_CMDC_XACT_WR4 0x1850 -+#define EARCRX_CMDC_XACT_WR5 0x1854 -+#define EARCRX_CMDC_XACT_WR6 0x1858 -+#define EARCRX_CMDC_XACT_WR7 0x185c -+#define EARCRX_CMDC_XACT_WR8 0x1860 -+#define EARCRX_CMDC_XACT_WR9 0x1864 -+#define EARCRX_CMDC_XACT_WR10 0x1868 -+#define EARCRX_CMDC_XACT_WR11 0x186c -+#define EARCRX_CMDC_XACT_WR12 0x1870 -+#define EARCRX_CMDC_XACT_WR13 0x1874 -+#define EARCRX_CMDC_XACT_WR14 0x1878 -+#define EARCRX_CMDC_XACT_WR15 0x187c -+#define EARCRX_CMDC_XACT_WR16 0x1880 -+#define EARCRX_CMDC_XACT_WR17 0x1884 -+#define EARCRX_CMDC_XACT_WR18 0x1888 -+#define EARCRX_CMDC_XACT_WR19 0x188c -+#define EARCRX_CMDC_XACT_WR20 0x1890 -+#define EARCRX_CMDC_XACT_WR21 0x1894 -+#define EARCRX_CMDC_XACT_WR22 0x1898 -+#define EARCRX_CMDC_XACT_WR23 0x189c -+#define EARCRX_CMDC_XACT_WR24 0x18a0 -+#define EARCRX_CMDC_XACT_WR25 0x18a4 -+#define EARCRX_CMDC_XACT_WR26 0x18a8 -+#define EARCRX_CMDC_XACT_WR27 0x18ac -+#define EARCRX_CMDC_XACT_WR28 0x18b0 -+#define EARCRX_CMDC_XACT_WR29 0x18b4 -+#define EARCRX_CMDC_XACT_WR30 0x18b8 -+#define EARCRX_CMDC_XACT_WR31 0x18bc -+#define EARCRX_CMDC_XACT_WR32 0x18c0 -+#define EARCRX_CMDC_XACT_WR33 0x18c4 -+#define EARCRX_CMDC_XACT_WR34 0x18c8 -+#define EARCRX_CMDC_XACT_WR35 0x18cc -+#define EARCRX_CMDC_XACT_WR36 0x18d0 -+#define EARCRX_CMDC_XACT_WR37 0x18d4 -+#define EARCRX_CMDC_XACT_WR38 0x18d8 -+#define EARCRX_CMDC_XACT_WR39 0x18dc -+#define EARCRX_CMDC_XACT_WR40 0x18e0 -+#define EARCRX_CMDC_XACT_WR41 0x18e4 -+#define EARCRX_CMDC_XACT_WR42 0x18e8 -+#define EARCRX_CMDC_XACT_WR43 0x18ec -+#define EARCRX_CMDC_XACT_WR44 0x18f0 -+#define EARCRX_CMDC_XACT_WR45 0x18f4 -+#define EARCRX_CMDC_XACT_WR46 0x18f8 -+#define EARCRX_CMDC_XACT_WR47 0x18fc -+#define EARCRX_CMDC_XACT_WR48 0x1900 -+#define EARCRX_CMDC_XACT_WR49 0x1904 -+#define EARCRX_CMDC_XACT_WR50 0x1908 -+#define EARCRX_CMDC_XACT_WR51 0x190c -+#define EARCRX_CMDC_XACT_WR52 0x1910 -+#define EARCRX_CMDC_XACT_WR53 0x1914 -+#define EARCRX_CMDC_XACT_WR54 0x1918 -+#define EARCRX_CMDC_XACT_WR55 0x191c -+#define EARCRX_CMDC_XACT_WR56 0x1920 -+#define EARCRX_CMDC_XACT_WR57 0x1924 -+#define EARCRX_CMDC_XACT_WR58 0x1928 -+#define EARCRX_CMDC_XACT_WR59 0x192c -+#define EARCRX_CMDC_XACT_WR60 0x1930 -+#define EARCRX_CMDC_XACT_WR61 0x1934 -+#define EARCRX_CMDC_XACT_WR62 0x1938 -+#define EARCRX_CMDC_XACT_WR63 0x193c -+#define EARCRX_CMDC_XACT_WR64 0x1940 -+#define EARCRX_CMDC_XACT_RD0 0x1960 -+#define EARCRX_CMDC_XACT_RD1 0x1964 -+#define EARCRX_CMDC_XACT_RD2 0x1968 -+#define EARCRX_CMDC_XACT_RD3 0x196c -+#define EARCRX_CMDC_XACT_RD4 0x1970 -+#define EARCRX_CMDC_XACT_RD5 0x1974 -+#define EARCRX_CMDC_XACT_RD6 0x1978 -+#define EARCRX_CMDC_XACT_RD7 0x197c -+#define EARCRX_CMDC_XACT_RD8 0x1980 -+#define EARCRX_CMDC_XACT_RD9 0x1984 -+#define EARCRX_CMDC_XACT_RD10 0x1988 -+#define EARCRX_CMDC_XACT_RD11 0x198c -+#define EARCRX_CMDC_XACT_RD12 0x1990 -+#define EARCRX_CMDC_XACT_RD13 0x1994 -+#define EARCRX_CMDC_XACT_RD14 0x1998 -+#define EARCRX_CMDC_XACT_RD15 0x199c -+#define EARCRX_CMDC_XACT_RD16 0x19a0 -+#define EARCRX_CMDC_XACT_RD17 0x19a4 -+#define EARCRX_CMDC_XACT_RD18 0x19a8 -+#define EARCRX_CMDC_XACT_RD19 0x19ac -+#define EARCRX_CMDC_XACT_RD20 0x19b0 -+#define EARCRX_CMDC_XACT_RD21 0x19b4 -+#define EARCRX_CMDC_XACT_RD22 0x19b8 -+#define EARCRX_CMDC_XACT_RD23 0x19bc -+#define EARCRX_CMDC_XACT_RD24 0x19c0 -+#define EARCRX_CMDC_XACT_RD25 0x19c4 -+#define EARCRX_CMDC_XACT_RD26 0x19c8 -+#define EARCRX_CMDC_XACT_RD27 0x19cc -+#define EARCRX_CMDC_XACT_RD28 0x19d0 -+#define EARCRX_CMDC_XACT_RD29 0x19d4 -+#define EARCRX_CMDC_XACT_RD30 0x19d8 -+#define EARCRX_CMDC_XACT_RD31 0x19dc -+#define EARCRX_CMDC_XACT_RD32 0x19e0 -+#define EARCRX_CMDC_XACT_RD33 0x19e4 -+#define EARCRX_CMDC_XACT_RD34 0x19e8 -+#define EARCRX_CMDC_XACT_RD35 0x19ec -+#define EARCRX_CMDC_XACT_RD36 0x19f0 -+#define EARCRX_CMDC_XACT_RD37 0x19f4 -+#define EARCRX_CMDC_XACT_RD38 0x19f8 -+#define EARCRX_CMDC_XACT_RD39 0x19fc -+#define EARCRX_CMDC_XACT_RD40 0x1a00 -+#define EARCRX_CMDC_XACT_RD41 0x1a04 -+#define EARCRX_CMDC_XACT_RD42 0x1a08 -+#define EARCRX_CMDC_XACT_RD43 0x1a0c -+#define EARCRX_CMDC_XACT_RD44 0x1a10 -+#define EARCRX_CMDC_XACT_RD45 0x1a14 -+#define EARCRX_CMDC_XACT_RD46 0x1a18 -+#define EARCRX_CMDC_XACT_RD47 0x1a1c -+#define EARCRX_CMDC_XACT_RD48 0x1a20 -+#define EARCRX_CMDC_XACT_RD49 0x1a24 -+#define EARCRX_CMDC_XACT_RD50 0x1a28 -+#define EARCRX_CMDC_XACT_RD51 0x1a2c -+#define EARCRX_CMDC_XACT_RD52 0x1a30 -+#define EARCRX_CMDC_XACT_RD53 0x1a34 -+#define EARCRX_CMDC_XACT_RD54 0x1a38 -+#define EARCRX_CMDC_XACT_RD55 0x1a3c -+#define EARCRX_CMDC_XACT_RD56 0x1a40 -+#define EARCRX_CMDC_XACT_RD57 0x1a44 -+#define EARCRX_CMDC_XACT_RD58 0x1a48 -+#define EARCRX_CMDC_XACT_RD59 0x1a4c -+#define EARCRX_CMDC_XACT_RD60 0x1a50 -+#define EARCRX_CMDC_XACT_RD61 0x1a54 -+#define EARCRX_CMDC_XACT_RD62 0x1a58 -+#define EARCRX_CMDC_XACT_RD63 0x1a5c -+#define EARCRX_CMDC_XACT_RD64 0x1a60 -+#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 -+/* eARC RX DMAC Registers */ -+#define EARCRX_DMAC_PHY_CONTROL 0x1c00 -+#define EARCRX_DMAC_CONFIG 0x1c08 -+#define EARCRX_DMAC_CONTROL0 0x1c0c -+#define EARCRX_DMAC_AUDIO_EN BIT(1) -+#define EARCRX_DMAC_EN BIT(0) -+#define EARCRX_DMAC_CONTROL1 0x1c10 -+#define EARCRX_DMAC_STATUS 0x1c14 -+#define EARCRX_DMAC_CHSTATUS0 0x1c18 -+#define EARCRX_DMAC_CHSTATUS1 0x1c1c -+#define EARCRX_DMAC_CHSTATUS2 0x1c20 -+#define EARCRX_DMAC_CHSTATUS3 0x1c24 -+#define EARCRX_DMAC_CHSTATUS4 0x1c28 -+#define EARCRX_DMAC_CHSTATUS5 0x1c2c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 -+#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 -+#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 -+#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c -+#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 -+#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 -+#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 -+#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c -+#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 -+#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 -+#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 -+#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c -+#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 -+#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 -+#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 -+#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c -+#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 -+/* Main Unit Interrupt Registers */ -+#define MAIN_INTVEC_INDEX 0x3000 -+#define MAINUNIT_0_INT_STATUS 0x3010 -+#define MAINUNIT_0_INT_MASK_N 0x3014 -+#define MAINUNIT_0_INT_CLEAR 0x3018 -+#define MAINUNIT_0_INT_FORCE 0x301c -+#define MAINUNIT_1_INT_STATUS 0x3020 -+#define FLT_EXIT_TO_LTSL_IRQ BIT(22) -+#define FLT_EXIT_TO_LTS4_IRQ BIT(21) -+#define FLT_EXIT_TO_LTSP_IRQ BIT(20) -+#define SCDC_NACK_RCVD_IRQ BIT(12) -+#define SCDC_RR_REPLY_STOP_IRQ BIT(11) -+#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) -+#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) -+#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) -+#define I2CM_NACK_RCVD_IRQ BIT(2) -+#define I2CM_READ_REQUEST_IRQ BIT(1) -+#define I2CM_OP_DONE_IRQ BIT(0) -+#define MAINUNIT_1_INT_MASK_N 0x3024 -+#define I2CM_NACK_RCVD_MASK_N BIT(2) -+#define I2CM_READ_REQUEST_MASK_N BIT(1) -+#define I2CM_OP_DONE_MASK_N BIT(0) -+#define MAINUNIT_1_INT_CLEAR 0x3028 -+#define I2CM_NACK_RCVD_CLEAR BIT(2) -+#define I2CM_READ_REQUEST_CLEAR BIT(1) -+#define I2CM_OP_DONE_CLEAR BIT(0) -+#define MAINUNIT_1_INT_FORCE 0x302c -+/* AVPUNIT Interrupt Registers */ -+#define AVP_INTVEC_INDEX 0x3800 -+#define AVP_0_INT_STATUS 0x3810 -+#define AVP_0_INT_MASK_N 0x3814 -+#define AVP_0_INT_CLEAR 0x3818 -+#define AVP_0_INT_FORCE 0x381c -+#define AVP_1_INT_STATUS 0x3820 -+#define AVP_1_INT_MASK_N 0x3824 -+#define HDCP14_AUTH_CHG_MASK_N BIT(6) -+#define AVP_1_INT_CLEAR 0x3828 -+#define AVP_1_INT_FORCE 0x382c -+#define AVP_2_INT_STATUS 0x3830 -+#define AVP_2_INT_MASK_N 0x3834 -+#define AVP_2_INT_CLEAR 0x3838 -+#define AVP_2_INT_FORCE 0x383c -+#define AVP_3_INT_STATUS 0x3840 -+#define AVP_3_INT_MASK_N 0x3844 -+#define AVP_3_INT_CLEAR 0x3848 -+#define AVP_3_INT_FORCE 0x384c -+#define AVP_4_INT_STATUS 0x3850 -+#define AVP_4_INT_MASK_N 0x3854 -+#define AVP_4_INT_CLEAR 0x3858 -+#define AVP_4_INT_FORCE 0x385c -+#define AVP_5_INT_STATUS 0x3860 -+#define AVP_5_INT_MASK_N 0x3864 -+#define AVP_5_INT_CLEAR 0x3868 -+#define AVP_5_INT_FORCE 0x386c -+#define AVP_6_INT_STATUS 0x3870 -+#define AVP_6_INT_MASK_N 0x3874 -+#define AVP_6_INT_CLEAR 0x3878 -+#define AVP_6_INT_FORCE 0x387c -+/* CEC Interrupt Registers */ -+#define CEC_INT_STATUS 0x4000 -+#define CEC_INT_MASK_N 0x4004 -+#define CEC_INT_CLEAR 0x4008 -+#define CEC_INT_FORCE 0x400c -+/* eARC RX Interrupt Registers */ -+#define EARCRX_INTVEC_INDEX 0x4800 -+#define EARCRX_0_INT_STATUS 0x4810 -+#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) -+#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) -+#define EARCRX_0_INT_MASK_N 0x4814 -+#define EARCRX_0_INT_CLEAR 0x4818 -+#define EARCRX_0_INT_FORCE 0x481c -+#define EARCRX_1_INT_STATUS 0x4820 -+#define EARCRX_1_INT_MASK_N 0x4824 -+#define EARCRX_1_INT_CLEAR 0x4828 -+#define EARCRX_1_INT_FORCE 0x482c -+ -+#endif /* __DW_HDMI_QP_H__ */ -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -163,6 +163,8 @@ struct dw_hdmi { - void __iomem *regs; - bool sink_is_hdmi; - bool sink_has_audio; -+ bool support_hdmi; -+ int force_output; - - struct pinctrl *pinctrl; - struct pinctrl_state *default_state; -@@ -255,6 +257,25 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, - hdmi_modb(hdmi, data << shift, mask, reg); - } - -+static bool dw_hdmi_check_output_type_changed(struct dw_hdmi *hdmi) -+{ -+ bool sink_hdmi; -+ -+ sink_hdmi = hdmi->sink_is_hdmi; -+ -+ if (hdmi->force_output == 1) -+ hdmi->sink_is_hdmi = true; -+ else if (hdmi->force_output == 2) -+ hdmi->sink_is_hdmi = false; -+ else -+ hdmi->sink_is_hdmi = hdmi->support_hdmi; -+ -+ if (sink_hdmi != hdmi->sink_is_hdmi) -+ return true; -+ -+ return false; -+} -+ - static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) - { - hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, -@@ -2539,6 +2560,45 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, - return 0; - } - -+void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi) -+{ -+ if (!hdmi->bridge_is_on) -+ return; -+ -+ hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); -+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); -+ hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range); -+ -+void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val) -+{ -+ hdmi->force_output = val; -+ -+ if (!dw_hdmi_check_output_type_changed(hdmi)) -+ return; -+ -+ if (!hdmi->bridge_is_on) -+ return; -+ -+ hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); -+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); -+ hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type); -+ -+bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi) -+{ -+ return hdmi->sink_is_hdmi; -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_get_output_whether_hdmi); -+ -+int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi) -+{ -+ return hdmi->support_hdmi; -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap); -+ - static void dw_hdmi_connector_force(struct drm_connector *connector) - { - struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, -@@ -3668,6 +3728,35 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi) - } - EXPORT_SYMBOL_GPL(dw_hdmi_unbind); - -+void dw_hdmi_suspend(struct dw_hdmi *hdmi) -+{ -+ if (!hdmi) -+ return; -+ -+ mutex_lock(&hdmi->mutex); -+ -+ /* -+ * When system shutdown, hdmi should be disabled. -+ * When system suspend, dw_hdmi_bridge_disable will disable hdmi first. -+ * To prevent duplicate operation, we should determine whether hdmi -+ * has been disabled. -+ */ -+ if (!hdmi->disabled) { -+ hdmi->disabled = true; -+ dw_hdmi_update_power(hdmi); -+ dw_hdmi_update_phy_mask(hdmi); -+ } -+ mutex_unlock(&hdmi->mutex); -+ -+ //[CC: needed?] -+ // if (hdmi->irq) -+ // disable_irq(hdmi->irq); -+ // cancel_delayed_work(&hdmi->work); -+ // flush_workqueue(hdmi->workqueue); -+ pinctrl_pm_select_sleep_state(hdmi->dev); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_suspend); -+ - void dw_hdmi_resume(struct dw_hdmi *hdmi) - { - dw_hdmi_init_hw(hdmi); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -851,6 +851,10 @@ enum { - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, - -+/* HDMI_FC_GCP */ -+ HDMI_FC_GCP_SET_AVMUTE = 0x2, -+ HDMI_FC_GCP_CLEAR_AVMUTE = 0x1, -+ - /* FC_DBGFORCE field values */ - HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, - HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -4,21 +4,32 @@ - */ - - #include -+#include -+#include - #include - #include - #include - #include -+#include - #include - #include - -+#include -+#include -+#include -+#include - #include - #include - #include - #include - #include - -+#include -+ - #include "rockchip_drm_drv.h" - -+#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) -+ - #define RK3228_GRF_SOC_CON2 0x0408 - #define RK3228_HDMI_SDAIN_MSK BIT(14) - #define RK3228_HDMI_SCLIN_MSK BIT(13) -@@ -29,8 +40,11 @@ - - #define RK3288_GRF_SOC_CON6 0x025C - #define RK3288_HDMI_LCDC_SEL BIT(4) --#define RK3328_GRF_SOC_CON2 0x0408 -+#define RK3288_GRF_SOC_CON16 0x03a8 -+#define RK3288_HDMI_LCDC0_YUV420 BIT(2) -+#define RK3288_HDMI_LCDC1_YUV420 BIT(3) - -+#define RK3328_GRF_SOC_CON2 0x0408 - #define RK3328_HDMI_SDAIN_MSK BIT(11) - #define RK3328_HDMI_SCLIN_MSK BIT(10) - #define RK3328_HDMI_HPD_IOE BIT(2) -@@ -54,32 +68,177 @@ - #define RK3568_HDMI_SDAIN_MSK BIT(15) - #define RK3568_HDMI_SCLIN_MSK BIT(14) - --#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) -+#define RK3588_GRF_SOC_CON2 0x0308 -+#define RK3588_HDMI1_HPD_INT_MSK BIT(15) -+#define RK3588_HDMI1_HPD_INT_CLR BIT(14) -+#define RK3588_HDMI0_HPD_INT_MSK BIT(13) -+#define RK3588_HDMI0_HPD_INT_CLR BIT(12) -+#define RK3588_GRF_SOC_CON7 0x031c -+#define RK3588_SET_HPD_PATH_MASK (0x3 << 12) -+#define RK3588_GRF_SOC_STATUS1 0x0384 -+#define RK3588_HDMI0_LOW_MORETHAN100MS BIT(20) -+#define RK3588_HDMI0_HPD_PORT_LEVEL BIT(19) -+#define RK3588_HDMI0_IHPD_PORT BIT(18) -+#define RK3588_HDMI0_OHPD_INT BIT(17) -+#define RK3588_HDMI0_LEVEL_INT BIT(16) -+#define RK3588_HDMI0_INTR_CHANGE_CNT (0x7 << 13) -+#define RK3588_HDMI1_LOW_MORETHAN100MS BIT(28) -+#define RK3588_HDMI1_HPD_PORT_LEVEL BIT(27) -+#define RK3588_HDMI1_IHPD_PORT BIT(26) -+#define RK3588_HDMI1_OHPD_INT BIT(25) -+#define RK3588_HDMI1_LEVEL_INT BIT(24) -+#define RK3588_HDMI1_INTR_CHANGE_CNT (0x7 << 21) -+ -+#define RK3588_GRF_VO1_CON3 0x000c -+#define RK3588_COLOR_FORMAT_MASK 0xf -+#define RK3588_YUV444 0x2 -+#define RK3588_YUV420 0x3 -+#define RK3588_COMPRESSED_DATA 0xb -+#define RK3588_COLOR_DEPTH_MASK (0xf << 4) -+#define RK3588_8BPC (0x5 << 4) -+#define RK3588_10BPC (0x6 << 4) -+#define RK3588_CECIN_MASK BIT(8) -+#define RK3588_SCLIN_MASK BIT(9) -+#define RK3588_SDAIN_MASK BIT(10) -+#define RK3588_MODE_MASK BIT(11) -+#define RK3588_COMPRESS_MODE_MASK BIT(12) -+#define RK3588_I2S_SEL_MASK BIT(13) -+#define RK3588_SPDIF_SEL_MASK BIT(14) -+#define RK3588_GRF_VO1_CON4 0x0010 -+#define RK3588_HDMI21_MASK BIT(0) -+#define RK3588_GRF_VO1_CON9 0x0024 -+#define RK3588_HDMI0_GRANT_SEL BIT(10) -+#define RK3588_HDMI0_GRANT_SW BIT(11) -+#define RK3588_HDMI1_GRANT_SEL BIT(12) -+#define RK3588_HDMI1_GRANT_SW BIT(13) -+#define RK3588_GRF_VO1_CON6 0x0018 -+#define RK3588_GRF_VO1_CON7 0x001c -+ -+#define COLOR_DEPTH_10BIT BIT(31) -+#define HDMI_FRL_MODE BIT(30) -+#define HDMI_EARC_MODE BIT(29) -+ -+#define HDMI20_MAX_RATE 600000 -+#define HDMI_8K60_RATE 2376000 - - /** - * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips - * @lcdsel_grf_reg: grf register offset of lcdc select -+ * @ddc_en_reg: grf register offset of hdmi ddc enable - * @lcdsel_big: reg value of selecting vop big for HDMI - * @lcdsel_lit: reg value of selecting vop little for HDMI -+ * @split_mode: flag indicating split mode capability - */ - struct rockchip_hdmi_chip_data { - int lcdsel_grf_reg; -+ int ddc_en_reg; - u32 lcdsel_big; - u32 lcdsel_lit; -+ bool split_mode; -+}; -+ -+enum hdmi_frl_rate_per_lane { -+ FRL_12G_PER_LANE = 12, -+ FRL_10G_PER_LANE = 10, -+ FRL_8G_PER_LANE = 8, -+ FRL_6G_PER_LANE = 6, -+ FRL_3G_PER_LANE = 3, -+}; -+ -+enum rk_if_color_depth { -+ RK_IF_DEPTH_8, -+ RK_IF_DEPTH_10, -+ RK_IF_DEPTH_12, -+ RK_IF_DEPTH_16, -+ RK_IF_DEPTH_420_10, -+ RK_IF_DEPTH_420_12, -+ RK_IF_DEPTH_420_16, -+ RK_IF_DEPTH_6, -+ RK_IF_DEPTH_MAX, -+}; -+ -+enum rk_if_color_format { -+ RK_IF_FORMAT_RGB, /* default RGB */ -+ RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */ -+ RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */ -+ RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */ -+ RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */ -+ RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */ -+ RK_IF_FORMAT_MAX, - }; - - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -+ struct regmap *vo1_regmap; - struct rockchip_encoder encoder; -+ struct drm_device *drm_dev; - const struct rockchip_hdmi_chip_data *chip_data; -- const struct dw_hdmi_plat_data *plat_data; -+ struct dw_hdmi_plat_data *plat_data; -+ struct clk *aud_clk; - struct clk *ref_clk; - struct clk *grf_clk; -+ struct clk *hclk_vio; -+ struct clk *hclk_vo1; -+ struct clk *hclk_vop; -+ struct clk *hpd_clk; -+ struct clk *pclk; -+ struct clk *earc_clk; -+ struct clk *hdmitx_ref; - struct dw_hdmi *hdmi; -+ struct dw_hdmi_qp *hdmi_qp; -+ - struct regulator *avdd_0v9; - struct regulator *avdd_1v8; - struct phy *phy; -+ -+ u32 max_tmdsclk; -+ bool unsupported_yuv_input; -+ bool unsupported_deep_color; -+ bool skip_check_420_mode; -+ u8 force_output; -+ u8 id; -+ bool hpd_stat; -+ bool is_hdmi_qp; -+ bool user_split_mode; -+ -+ unsigned long bus_format; -+ unsigned long output_bus_format; -+ unsigned long enc_out_encoding; -+ int color_changed; -+ int hpd_irq; -+ int vp_id; -+ -+ struct drm_property *color_depth_property; -+ struct drm_property *hdmi_output_property; -+ struct drm_property *colordepth_capacity; -+ struct drm_property *outputmode_capacity; -+ struct drm_property *quant_range; -+ struct drm_property *hdr_panel_metadata_property; -+ struct drm_property *next_hdr_sink_data_property; -+ struct drm_property *output_hdmi_dvi; -+ struct drm_property *output_type_capacity; -+ struct drm_property *user_split_mode_prop; -+ -+ struct drm_property_blob *hdr_panel_blob_ptr; -+ struct drm_property_blob *next_hdr_data_ptr; -+ -+ unsigned int colordepth; -+ unsigned int colorimetry; -+ unsigned int hdmi_quant_range; -+ unsigned int phy_bus_width; -+ enum rk_if_color_format hdmi_output; -+ // struct rockchip_drm_sub_dev sub_dev; -+ -+ u8 max_frl_rate_per_lane; -+ u8 max_lanes; -+ // struct rockchip_drm_dsc_cap dsc_cap; -+ // struct next_hdr_sink_data next_hdr_data; -+ struct dw_hdmi_link_config link_cfg; -+ struct gpio_desc *enable_gpio; -+ -+ struct delayed_work work; -+ struct workqueue_struct *workqueue; - }; - - static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) -@@ -202,13 +361,830 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - /*pixelclk symbol term vlev*/ - { 74250000, 0x8009, 0x0004, 0x0272}, - { 148500000, 0x802b, 0x0004, 0x028d}, -+ { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, -+ { 594000000, 0x8039, 0x0000, 0x019d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - -+enum ROW_INDEX_BPP { -+ ROW_INDEX_6BPP = 0, -+ ROW_INDEX_8BPP, -+ ROW_INDEX_10BPP, -+ ROW_INDEX_12BPP, -+ ROW_INDEX_23BPP, -+ MAX_ROW_INDEX -+}; -+ -+enum COLUMN_INDEX_BPC { -+ COLUMN_INDEX_8BPC = 0, -+ COLUMN_INDEX_10BPC, -+ COLUMN_INDEX_12BPC, -+ COLUMN_INDEX_14BPC, -+ COLUMN_INDEX_16BPC, -+ MAX_COLUMN_INDEX -+}; -+ -+#define PPS_TABLE_LEN 8 -+#define PPS_BPP_LEN 4 -+#define PPS_BPC_LEN 2 -+ -+struct pps_data { -+ u32 pic_width; -+ u32 pic_height; -+ u32 slice_width; -+ u32 slice_height; -+ bool convert_rgb; -+ u8 bpc; -+ u8 bpp; -+ u8 raw_pps[128]; -+}; -+ -+#if 0 -+/* -+ * Selected Rate Control Related Parameter Recommended Values -+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 -+ */ -+static struct pps_data pps_datas[PPS_TABLE_LEN] = { -+ { -+ /* 7680x4320/960X96 rgb 8bpc 12bpp */ -+ 7680, 4320, 960, 96, 1, 8, 192, -+ { -+ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xc0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, -+ 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, -+ 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, -+ 0x08, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, -+ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x00, 0x82, 0x00, 0xc0, 0x09, 0x00, -+ 0x09, 0x7e, 0x19, 0xbc, 0x19, 0xba, 0x19, 0xf8, -+ 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, -+ 0x2a, 0x76, 0x2a, 0x74, 0x3a, 0xb4, 0x52, 0xf4, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 8bpc 11bpp */ -+ 7680, 4320, 960, 96, 1, 8, 176, -+ { -+ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xb0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, -+ 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, -+ 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, -+ 0x0f, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, -+ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x00, 0x82, 0x01, 0x00, 0x09, 0x40, -+ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, -+ 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, -+ 0x2a, 0x76, 0x2a, 0xb4, 0x3a, 0xb4, 0x52, 0xf4, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 8bpc 10bpp */ -+ 7680, 4320, 960, 96, 1, 8, 160, -+ { -+ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xa0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, -+ 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, -+ 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, -+ 0x16, 0x00, 0x10, 0xec, 0x03, 0x0c, 0x20, 0x00, -+ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, -+ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, -+ 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, -+ 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x5b, 0x34, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 8bpc 9bpp */ -+ 7680, 4320, 960, 96, 1, 8, 144, -+ { -+ 0x12, 0x00, 0x00, 0x8d, 0x30, 0x90, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, -+ 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, -+ 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, -+ 0x17, 0x00, 0x10, 0xf1, 0x03, 0x0c, 0x20, 0x00, -+ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, -+ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, -+ 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, -+ 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x63, 0x74, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 10bpc 12bpp */ -+ 7680, 4320, 960, 96, 1, 10, 192, -+ { -+ 0x12, 0x00, 0x00, 0xad, 0x30, 0xc0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, -+ 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, -+ 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, -+ 0x08, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, -+ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x01, 0x02, 0x11, 0x80, 0x22, 0x00, -+ 0x22, 0x7e, 0x32, 0xbc, 0x32, 0xba, 0x3a, 0xf8, -+ 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, -+ 0x4b, 0x76, 0x4b, 0x74, 0x5b, 0xb4, 0x73, 0xf4, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 10bpc 11bpp */ -+ 7680, 4320, 960, 96, 1, 10, 176, -+ { -+ 0x12, 0x00, 0x00, 0xad, 0x30, 0xb0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, -+ 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, -+ 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, -+ 0x0f, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, -+ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x01, 0x42, 0x19, 0xc0, 0x2a, 0x40, -+ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, -+ 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, -+ 0x4b, 0x76, 0x4b, 0xb4, 0x5b, 0xb4, 0x73, 0xf4, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 10bpc 10bpp */ -+ 7680, 4320, 960, 96, 1, 10, 160, -+ { -+ 0x12, 0x00, 0x00, 0xad, 0x30, 0xa0, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, -+ 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, -+ 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, -+ 0x16, 0x00, 0x10, 0xec, 0x07, 0x10, 0x20, 0x00, -+ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, -+ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, -+ 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, -+ 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x7c, 0x34, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+ { -+ /* 7680x4320/960X96 rgb 10bpc 9bpp */ -+ 7680, 4320, 960, 96, 1, 10, 144, -+ { -+ 0x12, 0x00, 0x00, 0xad, 0x30, 0x90, 0x10, 0xe0, -+ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, -+ 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, -+ 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, -+ 0x17, 0x00, 0x10, 0xf1, 0x07, 0x10, 0x20, 0x00, -+ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, -+ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, -+ 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, -+ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, -+ 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, -+ 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x84, 0x74, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ }, -+ }, -+}; -+ -+static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+#endif -+ -+static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: -+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+static int hdmi_bus_fmt_color_depth(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ return 8; -+ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ return 10; -+ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: -+ return 12; -+ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: -+ return 16; -+ -+ default: -+ return 0; -+ } -+} -+ -+static unsigned int -+hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) -+{ -+ unsigned int tmdsclock = pixelclock; -+ unsigned int depth = -+ hdmi_bus_fmt_color_depth(hdmi->output_bus_format); -+ -+ if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) { -+ switch (depth) { -+ case 16: -+ tmdsclock = pixelclock * 2; -+ break; -+ case 12: -+ tmdsclock = pixelclock * 3 / 2; -+ break; -+ case 10: -+ tmdsclock = pixelclock * 5 / 4; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ return tmdsclock; -+} -+ -+static int rockchip_hdmi_match_by_id(struct device *dev, const void *data) -+{ -+ struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); -+ const unsigned int *id = data; -+ -+ return hdmi->id == *id; -+} -+ -+static struct rockchip_hdmi * -+rockchip_hdmi_find_by_id(struct device_driver *drv, unsigned int id) -+{ -+ struct device *dev; -+ -+ dev = driver_find_device(drv, NULL, &id, rockchip_hdmi_match_by_id); -+ if (!dev) -+ return NULL; -+ -+ return dev_get_drvdata(dev); -+} -+ -+static void hdmi_select_link_config(struct rockchip_hdmi *hdmi, -+ struct drm_crtc_state *crtc_state, -+ unsigned int tmdsclk) -+{ -+ struct drm_display_mode mode; -+ int max_lanes, max_rate_per_lane; -+ // int max_dsc_lanes, max_dsc_rate_per_lane; -+ unsigned long max_frl_rate; -+ -+ drm_mode_copy(&mode, &crtc_state->mode); -+ -+ max_lanes = hdmi->max_lanes; -+ max_rate_per_lane = hdmi->max_frl_rate_per_lane; -+ max_frl_rate = max_lanes * max_rate_per_lane * 1000000; -+ -+ hdmi->link_cfg.dsc_mode = false; -+ hdmi->link_cfg.frl_lanes = max_lanes; -+ hdmi->link_cfg.rate_per_lane = max_rate_per_lane; -+ -+ if (!max_frl_rate || (tmdsclk < HDMI20_MAX_RATE && mode.clock < HDMI20_MAX_RATE)) { -+ hdmi->link_cfg.frl_mode = false; -+ return; -+ } -+ -+ hdmi->link_cfg.frl_mode = true; -+ dev_warn(hdmi->dev, "use unsupported frl hdmi mode\n"); -+ -+ // if (!hdmi->dsc_cap.v_1p2) -+ // return; -+ // -+ // max_dsc_lanes = hdmi->dsc_cap.max_lanes; -+ // max_dsc_rate_per_lane = -+ // hdmi->dsc_cap.max_frl_rate_per_lane; -+ // -+ // if (mode.clock >= HDMI_8K60_RATE && -+ // !hdmi_bus_fmt_is_yuv420(hdmi->bus_format) && -+ // !hdmi_bus_fmt_is_yuv422(hdmi->bus_format)) { -+ // hdmi->link_cfg.dsc_mode = true; -+ // hdmi->link_cfg.frl_lanes = max_dsc_lanes; -+ // hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane; -+ // } else { -+ // hdmi->link_cfg.dsc_mode = false; -+ // hdmi->link_cfg.frl_lanes = max_lanes; -+ // hdmi->link_cfg.rate_per_lane = max_rate_per_lane; -+ // } -+} -+ -+///////////////////////////////////////////////////////////////////////////////////// -+/* CC: disable DSC */ -+#if 0 -+static int hdmi_dsc_get_slice_height(int vactive) -+{ -+ int slice_height; -+ -+ /* -+ * Slice Height determination : HDMI2.1 Section 7.7.5.2 -+ * Select smallest slice height >=96, that results in a valid PPS and -+ * requires minimum padding lines required for final slice. -+ * -+ * Assumption : Vactive is even. -+ */ -+ for (slice_height = 96; slice_height <= vactive; slice_height += 2) -+ if (vactive % slice_height == 0) -+ return slice_height; -+ -+ return 0; -+} -+ -+static int hdmi_dsc_get_num_slices(struct rockchip_hdmi *hdmi, -+ struct drm_crtc_state *crtc_state, -+ int src_max_slices, int src_max_slice_width, -+ int hdmi_max_slices, int hdmi_throughput) -+{ -+/* Pixel rates in KPixels/sec */ -+#define HDMI_DSC_PEAK_PIXEL_RATE 2720000 -+/* -+ * Rates at which the source and sink are required to process pixels in each -+ * slice, can be two levels: either at least 340000KHz or at least 40000KHz. -+ */ -+#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 -+#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 -+ -+/* Spec limits the slice width to 2720 pixels */ -+#define MAX_HDMI_SLICE_WIDTH 2720 -+ int kslice_adjust; -+ int adjusted_clk_khz; -+ int min_slices; -+ int target_slices; -+ int max_throughput; /* max clock freq. in khz per slice */ -+ int max_slice_width; -+ int slice_width; -+ int pixel_clock = crtc_state->mode.clock; -+ -+ if (!hdmi_throughput) -+ return 0; -+ -+ /* -+ * Slice Width determination : HDMI2.1 Section 7.7.5.1 -+ * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as -+ * for 4:4:4 is 1.0. Multiplying these factors by 10 and later -+ * dividing adjusted clock value by 10. -+ */ -+ if (hdmi_bus_fmt_is_yuv444(hdmi->output_bus_format) || -+ hdmi_bus_fmt_is_rgb(hdmi->output_bus_format)) -+ kslice_adjust = 10; -+ else -+ kslice_adjust = 5; -+ -+ /* -+ * As per spec, the rate at which the source and the sink process -+ * the pixels per slice are at two levels: at least 340Mhz or 400Mhz. -+ * This depends upon the pixel clock rate and output formats -+ * (kslice adjust). -+ * If pixel clock * kslice adjust >= 2720MHz slices can be processed -+ * at max 340MHz, otherwise they can be processed at max 400MHz. -+ */ -+ -+ adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); -+ -+ if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) -+ max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; -+ else -+ max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; -+ -+ /* -+ * Taking into account the sink's capability for maximum -+ * clock per slice (in MHz) as read from HF-VSDB. -+ */ -+ max_throughput = min(max_throughput, hdmi_throughput * 1000); -+ -+ min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); -+ max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); -+ -+ /* -+ * Keep on increasing the num of slices/line, starting from min_slices -+ * per line till we get such a number, for which the slice_width is -+ * just less than max_slice_width. The slices/line selected should be -+ * less than or equal to the max horizontal slices that the combination -+ * of PCON encoder and HDMI decoder can support. -+ */ -+ do { -+ if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) -+ target_slices = 1; -+ else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) -+ target_slices = 2; -+ else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) -+ target_slices = 4; -+ else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) -+ target_slices = 8; -+ else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) -+ target_slices = 12; -+ else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) -+ target_slices = 16; -+ else -+ return 0; -+ -+ slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, target_slices); -+ if (slice_width > max_slice_width) -+ min_slices = target_slices + 1; -+ } while (slice_width > max_slice_width); -+ -+ return target_slices; -+} -+ -+static int hdmi_dsc_slices(struct rockchip_hdmi *hdmi, -+ struct drm_crtc_state *crtc_state) -+{ -+ int hdmi_throughput = hdmi->dsc_cap.clk_per_slice; -+ int hdmi_max_slices = hdmi->dsc_cap.max_slices; -+ int rk_max_slices = 8; -+ int rk_max_slice_width = 2048; -+ -+ return hdmi_dsc_get_num_slices(hdmi, crtc_state, rk_max_slices, -+ rk_max_slice_width, -+ hdmi_max_slices, hdmi_throughput); -+} -+ -+static int -+hdmi_dsc_get_bpp(struct rockchip_hdmi *hdmi, int src_fractional_bpp, -+ int slice_width, int num_slices, bool hdmi_all_bpp, -+ int hdmi_max_chunk_bytes) -+{ -+ int max_dsc_bpp, min_dsc_bpp; -+ int target_bytes; -+ bool bpp_found = false; -+ int bpp_decrement_x16; -+ int bpp_target; -+ int bpp_target_x16; -+ -+ /* -+ * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec -+ * Start with the max bpp and keep on decrementing with -+ * fractional bpp, if supported by PCON DSC encoder -+ * -+ * for each bpp we check if no of bytes can be supported by HDMI sink -+ */ -+ -+ /* only 9\10\12 bpp was tested */ -+ min_dsc_bpp = 9; -+ max_dsc_bpp = 12; -+ -+ /* -+ * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink -+ * Section 7.7.34 : Source shall not enable compressed Video -+ * Transport with bpp_target settings above 12 bpp unless -+ * DSC_all_bpp is set to 1. -+ */ -+ if (!hdmi_all_bpp) -+ max_dsc_bpp = min(max_dsc_bpp, 12); -+ -+ /* -+ * The Sink has a limit of compressed data in bytes for a scanline, -+ * as described in max_chunk_bytes field in HFVSDB block of edid. -+ * The no. of bytes depend on the target bits per pixel that the -+ * source configures. So we start with the max_bpp and calculate -+ * the target_chunk_bytes. We keep on decrementing the target_bpp, -+ * till we get the target_chunk_bytes just less than what the sink's -+ * max_chunk_bytes, or else till we reach the min_dsc_bpp. -+ * -+ * The decrement is according to the fractional support from PCON DSC -+ * encoder. For fractional BPP we use bpp_target as a multiple of 16. -+ * -+ * bpp_target_x16 = bpp_target * 16 -+ * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps -+ * {1/16, 1/8, 1/4, 1/2, 1} respectively. -+ */ -+ -+ bpp_target = max_dsc_bpp; -+ -+ /* src does not support fractional bpp implies decrement by 16 for bppx16 */ -+ if (!src_fractional_bpp) -+ src_fractional_bpp = 1; -+ bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); -+ bpp_target_x16 = bpp_target * 16; -+ -+ while (bpp_target_x16 > (min_dsc_bpp * 16)) { -+ int bpp; -+ -+ bpp = DIV_ROUND_UP(bpp_target_x16, 16); -+ target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); -+ if (target_bytes <= hdmi_max_chunk_bytes) { -+ bpp_found = true; -+ break; -+ } -+ bpp_target_x16 -= bpp_decrement_x16; -+ } -+ if (bpp_found) -+ return bpp_target_x16; -+ -+ return 0; -+} -+ -+static int -+dw_hdmi_dsc_bpp(struct rockchip_hdmi *hdmi, -+ int num_slices, int slice_width) -+{ -+ bool hdmi_all_bpp = hdmi->dsc_cap.all_bpp; -+ int fractional_bpp = 0; -+ int hdmi_max_chunk_bytes = hdmi->dsc_cap.total_chunk_kbytes * 1024; -+ -+ return hdmi_dsc_get_bpp(hdmi, fractional_bpp, slice_width, -+ num_slices, hdmi_all_bpp, -+ hdmi_max_chunk_bytes); -+} -+ -+static int dw_hdmi_qp_set_link_cfg(struct rockchip_hdmi *hdmi, -+ u16 pic_width, u16 pic_height, -+ u16 slice_width, u16 slice_height, -+ u16 bits_per_pixel, u8 bits_per_component) -+{ -+ int i; -+ -+ for (i = 0; i < PPS_TABLE_LEN; i++) -+ if (pic_width == pps_datas[i].pic_width && -+ pic_height == pps_datas[i].pic_height && -+ slice_width == pps_datas[i].slice_width && -+ slice_height == pps_datas[i].slice_height && -+ bits_per_component == pps_datas[i].bpc && -+ bits_per_pixel == pps_datas[i].bpp && -+ hdmi_bus_fmt_is_rgb(hdmi->output_bus_format) == pps_datas[i].convert_rgb) -+ break; -+ -+ if (i == PPS_TABLE_LEN) { -+ dev_err(hdmi->dev, "can't find pps cfg!\n"); -+ return -EINVAL; -+ } -+ -+ memcpy(hdmi->link_cfg.pps_payload, pps_datas[i].raw_pps, 128); -+ hdmi->link_cfg.hcactive = DIV_ROUND_UP(slice_width * (bits_per_pixel / 16), 8) * -+ (pic_width / slice_width); -+ -+ return 0; -+} -+ -+static void dw_hdmi_qp_dsc_configure(struct rockchip_hdmi *hdmi, -+ struct rockchip_crtc_state *s, -+ struct drm_crtc_state *crtc_state) -+{ -+ int ret; -+ int slice_height; -+ int slice_width; -+ int bits_per_pixel; -+ int slice_count; -+ bool hdmi_is_dsc_1_2; -+ unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->output_bus_format); -+ -+ if (!crtc_state) -+ return; -+ -+ hdmi_is_dsc_1_2 = hdmi->dsc_cap.v_1p2; -+ -+ if (!hdmi_is_dsc_1_2) -+ return; -+ -+ slice_height = hdmi_dsc_get_slice_height(crtc_state->mode.vdisplay); -+ if (!slice_height) -+ return; -+ -+ slice_count = hdmi_dsc_slices(hdmi, crtc_state); -+ if (!slice_count) -+ return; -+ -+ slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, slice_count); -+ -+ bits_per_pixel = dw_hdmi_dsc_bpp(hdmi, slice_count, slice_width); -+ if (!bits_per_pixel) -+ return; -+ -+ ret = dw_hdmi_qp_set_link_cfg(hdmi, crtc_state->mode.hdisplay, -+ crtc_state->mode.vdisplay, slice_width, -+ slice_height, bits_per_pixel, depth); -+ -+ if (ret) { -+ dev_err(hdmi->dev, "set vdsc cfg failed\n"); -+ return; -+ } -+ dev_info(hdmi->dev, "dsc_enable\n"); -+ s->dsc_enable = 1; -+ s->dsc_sink_cap.version_major = 1; -+ s->dsc_sink_cap.version_minor = 2; -+ s->dsc_sink_cap.slice_width = slice_width; -+ s->dsc_sink_cap.slice_height = slice_height; -+ s->dsc_sink_cap.target_bits_per_pixel_x16 = bits_per_pixel; -+ s->dsc_sink_cap.block_pred = 1; -+ s->dsc_sink_cap.native_420 = 0; -+ -+ memcpy(&s->pps, hdmi->link_cfg.pps_payload, 128); -+} -+#endif -+///////////////////////////////////////////////////////////////////////////////////////// -+ -+// static int rockchip_hdmi_update_phy_table(struct rockchip_hdmi *hdmi, -+// u32 *config, -+// int phy_table_size) -+// { -+// int i; -+// -+// if (phy_table_size > ARRAY_SIZE(rockchip_phy_config)) { -+// dev_err(hdmi->dev, "phy table array number is out of range\n"); -+// return -E2BIG; -+// } -+// -+// for (i = 0; i < phy_table_size; i++) { -+// if (config[i * 4] != 0) -+// rockchip_phy_config[i].mpixelclock = (u64)config[i * 4]; -+// else -+// rockchip_phy_config[i].mpixelclock = ~0UL; -+// rockchip_phy_config[i].sym_ctr = (u16)config[i * 4 + 1]; -+// rockchip_phy_config[i].term = (u16)config[i * 4 + 2]; -+// rockchip_phy_config[i].vlev_ctr = (u16)config[i * 4 + 3]; -+// } -+// -+// return 0; -+// } -+ -+static void repo_hpd_event(struct work_struct *p_work) -+{ -+ struct rockchip_hdmi *hdmi = container_of(p_work, struct rockchip_hdmi, work.work); -+ bool change; -+ -+ change = drm_helper_hpd_irq_event(hdmi->drm_dev); -+ if (change) { -+ dev_dbg(hdmi->dev, "hpd stat changed:%d\n", hdmi->hpd_stat); -+ // dw_hdmi_qp_cec_set_hpd(hdmi->hdmi_qp, hdmi->hpd_stat, change); -+ } -+} -+ -+static irqreturn_t rockchip_hdmi_hardirq(int irq, void *dev_id) -+{ -+ struct rockchip_hdmi *hdmi = dev_id; -+ u32 intr_stat, val; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); -+ -+ if (intr_stat) { -+ dev_dbg(hdmi->dev, "hpd irq %#x\n", intr_stat); -+ -+ if (!hdmi->id) -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, -+ RK3588_HDMI0_HPD_INT_MSK); -+ else -+ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, -+ RK3588_HDMI1_HPD_INT_MSK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ return IRQ_WAKE_THREAD; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static irqreturn_t rockchip_hdmi_irq(int irq, void *dev_id) -+{ -+ struct rockchip_hdmi *hdmi = dev_id; -+ u32 intr_stat, val; -+ int msecs; -+ bool stat; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); -+ -+ if (!intr_stat) -+ return IRQ_NONE; -+ -+ if (!hdmi->id) { -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, -+ RK3588_HDMI0_HPD_INT_CLR); -+ if (intr_stat & RK3588_HDMI0_LEVEL_INT) -+ stat = true; -+ else -+ stat = false; -+ } else { -+ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, -+ RK3588_HDMI1_HPD_INT_CLR); -+ if (intr_stat & RK3588_HDMI1_LEVEL_INT) -+ stat = true; -+ else -+ stat = false; -+ } -+ -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ if (stat) { -+ hdmi->hpd_stat = true; -+ msecs = 150; -+ } else { -+ hdmi->hpd_stat = false; -+ msecs = 20; -+ } -+ mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs)); -+ -+ if (!hdmi->id) { -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, -+ RK3588_HDMI0_HPD_INT_CLR) | -+ HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); -+ } else { -+ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, -+ RK3588_HDMI1_HPD_INT_CLR) | -+ HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); -+ } -+ -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ return IRQ_HANDLED; -+} -+ - static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - { - struct device_node *np = hdmi->dev->of_node; -+ int ret; - - hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(hdmi->regmap)) { -@@ -216,6 +1192,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->regmap); - } - -+ if (hdmi->is_hdmi_qp) { -+ hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,vo1_grf"); -+ if (IS_ERR(hdmi->vo1_regmap)) { -+ DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,vo1_grf\n"); -+ return PTR_ERR(hdmi->vo1_regmap); -+ } -+ } -+ - hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); - if (!hdmi->ref_clk) - hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); -@@ -245,6 +1229,79 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - if (IS_ERR(hdmi->avdd_1v8)) - return PTR_ERR(hdmi->avdd_1v8); - -+ hdmi->hclk_vio = devm_clk_get(hdmi->dev, "hclk_vio"); -+ if (PTR_ERR(hdmi->hclk_vio) == -ENOENT) { -+ hdmi->hclk_vio = NULL; -+ } else if (PTR_ERR(hdmi->hclk_vio) == -EPROBE_DEFER) { -+ return -EPROBE_DEFER; -+ } else if (IS_ERR(hdmi->hclk_vio)) { -+ dev_err(hdmi->dev, "failed to get hclk_vio clock\n"); -+ return PTR_ERR(hdmi->hclk_vio); -+ } -+ -+ hdmi->hclk_vop = devm_clk_get(hdmi->dev, "hclk"); -+ if (PTR_ERR(hdmi->hclk_vop) == -ENOENT) { -+ hdmi->hclk_vop = NULL; -+ } else if (PTR_ERR(hdmi->hclk_vop) == -EPROBE_DEFER) { -+ return -EPROBE_DEFER; -+ } else if (IS_ERR(hdmi->hclk_vop)) { -+ dev_err(hdmi->dev, "failed to get hclk_vop clock\n"); -+ return PTR_ERR(hdmi->hclk_vop); -+ } -+ -+ hdmi->aud_clk = devm_clk_get_optional(hdmi->dev, "aud"); -+ if (IS_ERR(hdmi->aud_clk)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->aud_clk), -+ "failed to get aud_clk clock\n"); -+ return PTR_ERR(hdmi->aud_clk); -+ } -+ -+ hdmi->hpd_clk = devm_clk_get_optional(hdmi->dev, "hpd"); -+ if (IS_ERR(hdmi->hpd_clk)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hpd_clk), -+ "failed to get hpd_clk clock\n"); -+ return PTR_ERR(hdmi->hpd_clk); -+ } -+ -+ hdmi->hclk_vo1 = devm_clk_get_optional(hdmi->dev, "hclk_vo1"); -+ if (IS_ERR(hdmi->hclk_vo1)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hclk_vo1), -+ "failed to get hclk_vo1 clock\n"); -+ return PTR_ERR(hdmi->hclk_vo1); -+ } -+ -+ hdmi->earc_clk = devm_clk_get_optional(hdmi->dev, "earc"); -+ if (IS_ERR(hdmi->earc_clk)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->earc_clk), -+ "failed to get earc_clk clock\n"); -+ return PTR_ERR(hdmi->earc_clk); -+ } -+ -+ hdmi->hdmitx_ref = devm_clk_get_optional(hdmi->dev, "hdmitx_ref"); -+ if (IS_ERR(hdmi->hdmitx_ref)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmitx_ref), -+ "failed to get hdmitx_ref clock\n"); -+ return PTR_ERR(hdmi->hdmitx_ref); -+ } -+ -+ hdmi->pclk = devm_clk_get_optional(hdmi->dev, "pclk"); -+ if (IS_ERR(hdmi->pclk)) { -+ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->pclk), -+ "failed to get pclk clock\n"); -+ return PTR_ERR(hdmi->pclk); -+ } -+ -+ hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", -+ GPIOD_OUT_HIGH); -+ if (IS_ERR(hdmi->enable_gpio)) { -+ ret = PTR_ERR(hdmi->enable_gpio); -+ dev_err(hdmi->dev, "failed to request enable GPIO: %d\n", ret); -+ return ret; -+ } -+ -+ hdmi->skip_check_420_mode = -+ of_property_read_bool(np, "skip-check-420-mode"); -+ - return 0; - } - -@@ -283,9 +1340,114 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, - - return MODE_BAD; - } -+/* [CC:] enable downstream mode_valid() */ -+// static enum drm_mode_status -+// dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, void *data, -+// const struct drm_display_info *info, -+// const struct drm_display_mode *mode) -+// { -+// struct drm_encoder *encoder = connector->encoder; -+// enum drm_mode_status status = MODE_OK; -+// struct drm_device *dev = connector->dev; -+// struct rockchip_drm_private *priv = dev->dev_private; -+// struct drm_crtc *crtc; -+// struct rockchip_hdmi *hdmi; -+// -+// /* -+// * Pixel clocks we support are always < 2GHz and so fit in an -+// * int. We should make sure source rate does too so we don't get -+// * overflow when we multiply by 1000. -+// */ -+// if (mode->clock > INT_MAX / 1000) -+// return MODE_BAD; -+// -+// if (!encoder) { -+// const struct drm_connector_helper_funcs *funcs; -+// -+// funcs = connector->helper_private; -+// if (funcs->atomic_best_encoder) -+// encoder = funcs->atomic_best_encoder(connector, -+// connector->state); -+// else -+// encoder = funcs->best_encoder(connector); -+// } -+// -+// if (!encoder || !encoder->possible_crtcs) -+// return MODE_BAD; -+// -+// hdmi = to_rockchip_hdmi(encoder); -+// -+// /* -+// * If sink max TMDS clock < 340MHz, we should check the mode pixel -+// * clock > 340MHz is YCbCr420 or not and whether the platform supports -+// * YCbCr420. -+// */ -+// if (!hdmi->skip_check_420_mode) { -+// if (mode->clock > 340000 && -+// connector->display_info.max_tmds_clock < 340000 && -+// (!drm_mode_is_420(&connector->display_info, mode) || -+// !connector->ycbcr_420_allowed)) -+// return MODE_BAD; -+// -+// if (hdmi->max_tmdsclk <= 340000 && mode->clock > 340000 && -+// !drm_mode_is_420(&connector->display_info, mode)) -+// return MODE_BAD; -+// }; -+// -+// if (hdmi->phy) { -+// if (hdmi->is_hdmi_qp) -+// phy_set_bus_width(hdmi->phy, mode->clock * 10); -+// else -+// phy_set_bus_width(hdmi->phy, 8); -+// } -+// -+// /* -+// * ensure all drm display mode can work, if someone want support more -+// * resolutions, please limit the possible_crtc, only connect to -+// * needed crtc. -+// */ -+// drm_for_each_crtc(crtc, connector->dev) { -+// int pipe = drm_crtc_index(crtc); -+// const struct rockchip_crtc_funcs *funcs = -+// priv->crtc_funcs[pipe]; -+// -+// if (!(encoder->possible_crtcs & drm_crtc_mask(crtc))) -+// continue; -+// if (!funcs || !funcs->mode_valid) -+// continue; -+// -+// status = funcs->mode_valid(crtc, mode, -+// DRM_MODE_CONNECTOR_HDMIA); -+// if (status != MODE_OK) -+// return status; -+// } -+// -+// return status; -+// } -+// - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) - { -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ // struct drm_crtc *crtc = encoder->crtc; -+ // struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); -+ // -+ // if (crtc->state->active_changed) { -+ // if (hdmi->plat_data->split_mode) { -+ // s->output_if &= ~(VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1); -+ // } else { -+ // if (!hdmi->id) -+ // s->output_if &= ~VOP_OUTPUT_IF_HDMI1; -+ // else -+ // s->output_if &= ~VOP_OUTPUT_IF_HDMI0; -+ // } -+ // } -+ /* -+ * when plug out hdmi it will be switch cvbs and then phy bus width -+ * must be set as 8 -+ */ -+ if (hdmi->phy) -+ phy_set_bus_width(hdmi->phy, 8); - } - - static bool -@@ -301,6 +1463,27 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *adj_mode) - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct drm_crtc *crtc; -+ struct rockchip_crtc_state *s; -+ -+ if (!encoder->crtc) -+ return; -+ crtc = encoder->crtc; -+ -+ if (!crtc->state) -+ return; -+ s = to_rockchip_crtc_state(crtc->state); -+ -+ if (!s) -+ return; -+ -+ if (hdmi->is_hdmi_qp) { -+ // s->dsc_enable = 0; -+ // if (hdmi->link_cfg.dsc_mode) -+ // dw_hdmi_qp_dsc_configure(hdmi, s, crtc->state); -+ -+ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); -+ } - - clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); - } -@@ -308,14 +1491,25 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct drm_crtc *crtc = encoder->crtc; - u32 val; -+ int mux; - int ret; - -+ if (WARN_ON(!crtc || !crtc->state)) -+ return; -+ -+ if (hdmi->phy) -+ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); -+ -+ clk_set_rate(hdmi->ref_clk, -+ crtc->state->adjusted_mode.crtc_clock * 1000); -+ - if (hdmi->chip_data->lcdsel_grf_reg < 0) - return; - -- ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); -- if (ret) -+ mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); -+ if (mux) - val = hdmi->chip_data->lcdsel_lit; - else - val = hdmi->chip_data->lcdsel_big; -@@ -330,24 +1524,992 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) - if (ret != 0) - DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); - -+ if (hdmi->chip_data->lcdsel_grf_reg == RK3288_GRF_SOC_CON6) { -+ struct rockchip_crtc_state *s = -+ to_rockchip_crtc_state(crtc->state); -+ u32 mode_mask = mux ? RK3288_HDMI_LCDC1_YUV420 : -+ RK3288_HDMI_LCDC0_YUV420; -+ -+ if (s->output_mode == ROCKCHIP_OUT_MODE_YUV420) -+ val = HIWORD_UPDATE(mode_mask, mode_mask); -+ else -+ val = HIWORD_UPDATE(0, mode_mask); -+ -+ regmap_write(hdmi->regmap, RK3288_GRF_SOC_CON16, val); -+ } -+ - clk_disable_unprepare(hdmi->grf_clk); - DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", - ret ? "LIT" : "BIG"); - } - --static int --dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, -- struct drm_crtc_state *crtc_state, -- struct drm_connector_state *conn_state) -+static void rk3588_set_link_mode(struct rockchip_hdmi *hdmi) - { -- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ int val; -+ bool is_hdmi0; - -- s->output_mode = ROCKCHIP_OUT_MODE_AAAA; -- s->output_type = DRM_MODE_CONNECTOR_HDMIA; -+ if (!hdmi->id) -+ is_hdmi0 = true; -+ else -+ is_hdmi0 = false; -+ -+ if (!hdmi->link_cfg.frl_mode) { -+ val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); -+ if (is_hdmi0) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); -+ -+ val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); -+ if (is_hdmi0) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+ -+ return; -+ } -+ -+ val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); -+ if (is_hdmi0) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); -+ -+ if (hdmi->link_cfg.dsc_mode) { -+ val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, -+ RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); -+ if (is_hdmi0) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+ } else { -+ val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); -+ if (is_hdmi0) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+ } -+} -+ -+static void rk3588_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format, -+ u32 depth) -+{ -+ u32 val = 0; -+ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK); -+ break; -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ val = HIWORD_UPDATE(RK3588_YUV420, RK3588_COLOR_FORMAT_MASK); -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK); -+ break; -+ default: -+ dev_err(hdmi->dev, "can't set correct color format\n"); -+ return; -+ } -+ -+ if (hdmi->link_cfg.dsc_mode) -+ val = HIWORD_UPDATE(RK3588_COMPRESSED_DATA, RK3588_COLOR_FORMAT_MASK); -+ -+ if (depth == 8) -+ val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK); -+ else -+ val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK); -+ -+ if (!hdmi->id) -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ else -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+} -+ -+static void rk3588_set_grf_cfg(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ int color_depth; -+ -+ rk3588_set_link_mode(hdmi); -+ color_depth = hdmi_bus_fmt_color_depth(hdmi->bus_format); -+ rk3588_set_color_format(hdmi, hdmi->bus_format, color_depth); -+} -+ -+static void -+dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, -+ struct drm_crtc_state *crtc_state, -+ struct rockchip_hdmi *hdmi, -+ unsigned int *color_format, -+ unsigned int *output_mode, -+ unsigned long *bus_format, -+ unsigned int *bus_width, -+ unsigned long *enc_out_encoding, -+ unsigned int *eotf) -+{ -+ struct drm_display_info *info = &conn_state->connector->display_info; -+ struct drm_display_mode mode; -+ struct hdr_output_metadata *hdr_metadata; -+ u32 vic; -+ unsigned long tmdsclock, pixclock; -+ unsigned int color_depth; -+ bool support_dc = false; -+ bool sink_is_hdmi = true; -+ u32 max_tmds_clock = info->max_tmds_clock; -+ int output_eotf; -+ -+ drm_mode_copy(&mode, &crtc_state->mode); -+ pixclock = mode.crtc_clock; -+ // if (hdmi->plat_data->split_mode) { -+ // drm_mode_convert_to_origin_mode(&mode); -+ // pixclock /= 2; -+ // } -+ -+ vic = drm_match_cea_mode(&mode); -+ -+ if (!hdmi->is_hdmi_qp) -+ sink_is_hdmi = dw_hdmi_get_output_whether_hdmi(hdmi->hdmi); -+ -+ *color_format = RK_IF_FORMAT_RGB; -+ -+ switch (hdmi->hdmi_output) { -+ case RK_IF_FORMAT_YCBCR_HQ: -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ *color_format = RK_IF_FORMAT_YCBCR444; -+ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ *color_format = RK_IF_FORMAT_YCBCR422; -+ else if (conn_state->connector->ycbcr_420_allowed && -+ drm_mode_is_420(info, &mode) && -+ (pixclock >= 594000 && !hdmi->is_hdmi_qp)) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ break; -+ case RK_IF_FORMAT_YCBCR_LQ: -+ if (conn_state->connector->ycbcr_420_allowed && -+ drm_mode_is_420(info, &mode) && pixclock >= 594000) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ *color_format = RK_IF_FORMAT_YCBCR422; -+ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ *color_format = RK_IF_FORMAT_YCBCR444; -+ break; -+ case RK_IF_FORMAT_YCBCR420: -+ if (conn_state->connector->ycbcr_420_allowed && -+ drm_mode_is_420(info, &mode) && pixclock >= 594000) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ break; -+ case RK_IF_FORMAT_YCBCR422: -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ *color_format = RK_IF_FORMAT_YCBCR422; -+ break; -+ case RK_IF_FORMAT_YCBCR444: -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ *color_format = RK_IF_FORMAT_YCBCR444; -+ break; -+ case RK_IF_FORMAT_RGB: -+ default: -+ break; -+ } -+ -+ if (*color_format == RK_IF_FORMAT_RGB && -+ info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) -+ support_dc = true; -+ if (*color_format == RK_IF_FORMAT_YCBCR444 && -+ info->edid_hdmi_rgb444_dc_modes & -+ (DRM_EDID_HDMI_DC_Y444 | DRM_EDID_HDMI_DC_30)) -+ support_dc = true; -+ if (*color_format == RK_IF_FORMAT_YCBCR422) -+ support_dc = true; -+ if (*color_format == RK_IF_FORMAT_YCBCR420 && -+ info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) -+ support_dc = true; -+ -+ if (hdmi->colordepth > 8 && support_dc) -+ color_depth = 10; -+ else -+ color_depth = 8; -+ -+ if (!sink_is_hdmi) { -+ *color_format = RK_IF_FORMAT_RGB; -+ color_depth = 8; -+ } -+ -+ *eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR; -+ if (conn_state->hdr_output_metadata) { -+ hdr_metadata = (struct hdr_output_metadata *) -+ conn_state->hdr_output_metadata->data; -+ output_eotf = hdr_metadata->hdmi_metadata_type1.eotf; -+ if (output_eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && -+ output_eotf <= HDMI_EOTF_BT_2100_HLG) -+ *eotf = output_eotf; -+ } -+ -+ hdmi->colorimetry = conn_state->colorspace; -+ -+ if ((*eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && -+ conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & -+ BIT(*eotf)) || ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && -+ (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC))) -+ *enc_out_encoding = V4L2_YCBCR_ENC_BT2020; -+ else if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || -+ (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) -+ *enc_out_encoding = V4L2_YCBCR_ENC_601; -+ else -+ *enc_out_encoding = V4L2_YCBCR_ENC_709; -+ -+ if (*enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { -+ /* BT2020 require color depth at lest 10bit */ -+ color_depth = 10; -+ /* We prefer use YCbCr422 to send 10bit */ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ *color_format = RK_IF_FORMAT_YCBCR422; -+ if (hdmi->is_hdmi_qp) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR420) { -+ if (mode.clock >= 340000) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ else -+ *color_format = RK_IF_FORMAT_RGB; -+ } else { -+ *color_format = RK_IF_FORMAT_RGB; -+ } -+ } -+ } -+ -+ if (mode.flags & DRM_MODE_FLAG_DBLCLK) -+ pixclock *= 2; -+ if ((mode.flags & DRM_MODE_FLAG_3D_MASK) == -+ DRM_MODE_FLAG_3D_FRAME_PACKING) -+ pixclock *= 2; -+ -+ if (*color_format == RK_IF_FORMAT_YCBCR422 || color_depth == 8) -+ tmdsclock = pixclock; -+ else -+ tmdsclock = pixclock * (color_depth) / 8; -+ -+ if (*color_format == RK_IF_FORMAT_YCBCR420) -+ tmdsclock /= 2; -+ -+ /* XXX: max_tmds_clock of some sink is 0, we think it is 340MHz. */ -+ if (!max_tmds_clock) -+ max_tmds_clock = 340000; -+ -+ max_tmds_clock = min(max_tmds_clock, hdmi->max_tmdsclk); -+ -+ if ((tmdsclock > max_tmds_clock) && !hdmi->is_hdmi_qp) { -+ if (max_tmds_clock >= 594000) { -+ color_depth = 8; -+ } else if (max_tmds_clock > 340000) { -+ if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ } else { -+ color_depth = 8; -+ if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ } -+ } -+ -+ if (hdmi->is_hdmi_qp) { -+ if (mode.clock >= 340000) { -+ if (drm_mode_is_420(info, &mode)) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ else -+ *color_format = RK_IF_FORMAT_RGB; -+ } else if (tmdsclock > max_tmds_clock) { -+ color_depth = 8; -+ if (drm_mode_is_420(info, &mode)) -+ *color_format = RK_IF_FORMAT_YCBCR420; -+ } -+ } -+ -+ if (*color_format == RK_IF_FORMAT_YCBCR420) { -+ *output_mode = ROCKCHIP_OUT_MODE_YUV420; -+ if (color_depth > 8) -+ *bus_format = MEDIA_BUS_FMT_UYYVYY10_0_5X30; -+ else -+ *bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24; -+ *bus_width = color_depth / 2; -+ } else { -+ *output_mode = ROCKCHIP_OUT_MODE_AAAA; -+ if (color_depth > 8) { -+ if (*color_format != RK_IF_FORMAT_RGB && -+ !hdmi->unsupported_yuv_input) -+ *bus_format = MEDIA_BUS_FMT_YUV10_1X30; -+ else -+ *bus_format = MEDIA_BUS_FMT_RGB101010_1X30; -+ } else { -+ if (*color_format != RK_IF_FORMAT_RGB && -+ !hdmi->unsupported_yuv_input) -+ *bus_format = MEDIA_BUS_FMT_YUV8_1X24; -+ else -+ *bus_format = MEDIA_BUS_FMT_RGB888_1X24; -+ } -+ if (*color_format == RK_IF_FORMAT_YCBCR422) -+ *bus_width = 8; -+ else -+ *bus_width = color_depth; -+ } -+ -+ hdmi->bus_format = *bus_format; -+ -+ if (*color_format == RK_IF_FORMAT_YCBCR422) { -+ if (color_depth == 12) -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; -+ else if (color_depth == 10) -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; -+ else -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; -+ } else { -+ hdmi->output_bus_format = *bus_format; -+ } -+} -+ -+static bool -+dw_hdmi_rockchip_check_color(struct drm_connector_state *conn_state, -+ struct rockchip_hdmi *hdmi) -+{ -+ struct drm_crtc_state *crtc_state = conn_state->crtc->state; -+ unsigned int colorformat; -+ unsigned long bus_format; -+ unsigned long output_bus_format = hdmi->output_bus_format; -+ unsigned long enc_out_encoding = hdmi->enc_out_encoding; -+ unsigned int eotf, bus_width; -+ unsigned int output_mode; -+ -+ dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, -+ &colorformat, -+ &output_mode, &bus_format, &bus_width, -+ &hdmi->enc_out_encoding, &eotf); -+ -+ if (output_bus_format != hdmi->output_bus_format || -+ enc_out_encoding != hdmi->enc_out_encoding) -+ return true; -+ else -+ return false; -+} -+ -+static int -+dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ unsigned int colorformat, bus_width, tmdsclk; -+ struct drm_display_mode mode; -+ unsigned int output_mode; -+ unsigned long bus_format; -+ int color_depth; -+ bool secondary = false; -+ -+ /* -+ * There are two hdmi but only one encoder in split mode, -+ * so we need to check twice. -+ */ -+secondary: -+ drm_mode_copy(&mode, &crtc_state->mode); -+ -+ hdmi->vp_id = 0; -+ // hdmi->vp_id = s->vp_id; -+ // if (hdmi->plat_data->split_mode) -+ // drm_mode_convert_to_origin_mode(&mode); -+ -+ int eotf; -+ dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, -+ &colorformat, -+ &output_mode, &bus_format, &bus_width, -+ // &hdmi->enc_out_encoding, &s->eotf); -+ &hdmi->enc_out_encoding, &eotf); -+ -+ s->bus_format = bus_format; -+ if (hdmi->is_hdmi_qp) { -+ color_depth = hdmi_bus_fmt_color_depth(bus_format); -+ tmdsclk = hdmi_get_tmdsclock(hdmi, crtc_state->mode.clock); -+ if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) -+ tmdsclk /= 2; -+ hdmi_select_link_config(hdmi, crtc_state, tmdsclk); -+ -+ if (hdmi->link_cfg.frl_mode) { -+ gpiod_set_value(hdmi->enable_gpio, 0); -+ /* in the current version, support max 40G frl */ -+ if (hdmi->link_cfg.rate_per_lane >= 10) { -+ hdmi->link_cfg.frl_lanes = 4; -+ hdmi->link_cfg.rate_per_lane = 10; -+ } -+ bus_width = hdmi->link_cfg.frl_lanes * -+ hdmi->link_cfg.rate_per_lane * 1000000; -+ /* 10 bit color depth and frl mode */ -+ if (color_depth == 10) -+ bus_width |= -+ COLOR_DEPTH_10BIT | HDMI_FRL_MODE; -+ else -+ bus_width |= HDMI_FRL_MODE; -+ } else { -+ gpiod_set_value(hdmi->enable_gpio, 1); -+ bus_width = hdmi_get_tmdsclock(hdmi, mode.clock * 10); -+ if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) -+ bus_width /= 2; -+ -+ if (color_depth == 10) -+ bus_width |= COLOR_DEPTH_10BIT; -+ } -+ } -+ -+ hdmi->phy_bus_width = bus_width; -+ -+ if (hdmi->phy) -+ phy_set_bus_width(hdmi->phy, bus_width); -+ -+ s->output_type = DRM_MODE_CONNECTOR_HDMIA; -+ // s->tv_state = &conn_state->tv; -+ // -+ // if (hdmi->plat_data->split_mode) { -+ // s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; -+ // if (hdmi->plat_data->right && hdmi->id) -+ // s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; -+ // s->output_if |= VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1; -+ // } else { -+ // if (!hdmi->id) -+ // s->output_if |= VOP_OUTPUT_IF_HDMI0; -+ // else -+ // s->output_if |= VOP_OUTPUT_IF_HDMI1; -+ // } -+ -+ s->output_mode = output_mode; -+ hdmi->bus_format = s->bus_format; -+ -+ if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_BT2020) -+ s->color_space = V4L2_COLORSPACE_BT2020; -+ else if (colorformat == RK_IF_FORMAT_RGB) -+ s->color_space = V4L2_COLORSPACE_DEFAULT; -+ else if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_709) -+ s->color_space = V4L2_COLORSPACE_REC709; -+ else -+ s->color_space = V4L2_COLORSPACE_SMPTE170M; -+ -+ if (hdmi->plat_data->split_mode && !secondary) { -+ hdmi = rockchip_hdmi_find_by_id(hdmi->dev->driver, !hdmi->id); -+ secondary = true; -+ goto secondary; -+ } - - return 0; - } - -+static unsigned long -+dw_hdmi_rockchip_get_input_bus_format(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->bus_format; -+} -+ -+static unsigned long -+dw_hdmi_rockchip_get_output_bus_format(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->output_bus_format; -+} -+ -+static unsigned long -+dw_hdmi_rockchip_get_enc_in_encoding(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->enc_out_encoding; -+} -+ -+static unsigned long -+dw_hdmi_rockchip_get_enc_out_encoding(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->enc_out_encoding; -+} -+ -+static unsigned long -+dw_hdmi_rockchip_get_quant_range(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->hdmi_quant_range; -+} -+ -+static struct drm_property * -+dw_hdmi_rockchip_get_hdr_property(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->hdr_panel_metadata_property; -+} -+ -+static struct drm_property_blob * -+dw_hdmi_rockchip_get_hdr_blob(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return hdmi->hdr_panel_blob_ptr; -+} -+ -+static bool -+dw_hdmi_rockchip_get_color_changed(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ bool ret = false; -+ -+ if (hdmi->color_changed) -+ ret = true; -+ hdmi->color_changed = 0; -+ -+ return ret; -+} -+ -+#if 0 -+static int -+dw_hdmi_rockchip_get_edid_dsc_info(void *data, struct edid *edid) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ if (!edid) -+ return -EINVAL; -+ -+ return rockchip_drm_parse_cea_ext(&hdmi->dsc_cap, -+ &hdmi->max_frl_rate_per_lane, -+ &hdmi->max_lanes, edid); -+} -+ -+static int -+dw_hdmi_rockchip_get_next_hdr_data(void *data, struct edid *edid, -+ struct drm_connector *connector) -+{ -+ int ret; -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ struct next_hdr_sink_data *sink_data = &hdmi->next_hdr_data; -+ size_t size = sizeof(*sink_data); -+ struct drm_property *property = hdmi->next_hdr_sink_data_property; -+ struct drm_property_blob *blob = hdmi->hdr_panel_blob_ptr; -+ -+ if (!edid) -+ return -EINVAL; -+ -+ rockchip_drm_parse_next_hdr(sink_data, edid); -+ -+ ret = drm_property_replace_global_blob(connector->dev, &blob, size, sink_data, -+ &connector->base, property); -+ -+ return ret; -+}; -+#endif -+ -+static -+struct dw_hdmi_link_config *dw_hdmi_rockchip_get_link_cfg(void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ return &hdmi->link_cfg; -+} -+ -+#if 0 -+static const struct drm_prop_enum_list color_depth_enum_list[] = { -+ { 0, "Automatic" }, /* Prefer highest color depth */ -+ { 8, "24bit" }, -+ { 10, "30bit" }, -+}; -+ -+static const struct drm_prop_enum_list drm_hdmi_output_enum_list[] = { -+ { RK_IF_FORMAT_RGB, "rgb" }, -+ { RK_IF_FORMAT_YCBCR444, "ycbcr444" }, -+ { RK_IF_FORMAT_YCBCR422, "ycbcr422" }, -+ { RK_IF_FORMAT_YCBCR420, "ycbcr420" }, -+ { RK_IF_FORMAT_YCBCR_HQ, "ycbcr_high_subsampling" }, -+ { RK_IF_FORMAT_YCBCR_LQ, "ycbcr_low_subsampling" }, -+ { RK_IF_FORMAT_MAX, "invalid_output" }, -+}; -+ -+static const struct drm_prop_enum_list quant_range_enum_list[] = { -+ { HDMI_QUANTIZATION_RANGE_DEFAULT, "default" }, -+ { HDMI_QUANTIZATION_RANGE_LIMITED, "limit" }, -+ { HDMI_QUANTIZATION_RANGE_FULL, "full" }, -+}; -+ -+static const struct drm_prop_enum_list output_hdmi_dvi_enum_list[] = { -+ { 0, "auto" }, -+ { 1, "force_hdmi" }, -+ { 2, "force_dvi" }, -+}; -+ -+static const struct drm_prop_enum_list output_type_cap_list[] = { -+ { 0, "DVI" }, -+ { 1, "HDMI" }, -+}; -+#endif -+ -+static void -+dw_hdmi_rockchip_attach_properties(struct drm_connector *connector, -+ unsigned int color, int version, -+ void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ struct drm_property *prop; -+ // struct rockchip_drm_private *private = connector->dev->dev_private; -+ -+ switch (color) { -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ hdmi->hdmi_output = RK_IF_FORMAT_RGB; -+ hdmi->colordepth = 10; -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; -+ hdmi->colordepth = 8; -+ break; -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; -+ hdmi->colordepth = 10; -+ break; -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; -+ hdmi->colordepth = 10; -+ break; -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; -+ hdmi->colordepth = 8; -+ break; -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; -+ hdmi->colordepth = 8; -+ break; -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; -+ hdmi->colordepth = 10; -+ break; -+ default: -+ hdmi->hdmi_output = RK_IF_FORMAT_RGB; -+ hdmi->colordepth = 8; -+ } -+ -+ hdmi->bus_format = color; -+ -+ if (hdmi->hdmi_output == RK_IF_FORMAT_YCBCR422) { -+ if (hdmi->colordepth == 12) -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; -+ else if (hdmi->colordepth == 10) -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; -+ else -+ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; -+ } else { -+ hdmi->output_bus_format = hdmi->bus_format; -+ } -+ -+#if 0 -+ /* RK3368 does not support deep color mode */ -+ if (!hdmi->color_depth_property && !hdmi->unsupported_deep_color) { -+ prop = drm_property_create_enum(connector->dev, 0, -+ RK_IF_PROP_COLOR_DEPTH, -+ color_depth_enum_list, -+ ARRAY_SIZE(color_depth_enum_list)); -+ if (prop) { -+ hdmi->color_depth_property = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ } -+ -+ prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT, -+ drm_hdmi_output_enum_list, -+ ARRAY_SIZE(drm_hdmi_output_enum_list)); -+ if (prop) { -+ hdmi->hdmi_output_property = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create_range(connector->dev, 0, -+ RK_IF_PROP_COLOR_DEPTH_CAPS, -+ 0, 0xff); -+ if (prop) { -+ hdmi->colordepth_capacity = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create_range(connector->dev, 0, -+ RK_IF_PROP_COLOR_FORMAT_CAPS, -+ 0, 0xf); -+ if (prop) { -+ hdmi->outputmode_capacity = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create(connector->dev, -+ DRM_MODE_PROP_BLOB | -+ DRM_MODE_PROP_IMMUTABLE, -+ "HDR_PANEL_METADATA", 0); -+ if (prop) { -+ hdmi->hdr_panel_metadata_property = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create(connector->dev, -+ DRM_MODE_PROP_BLOB | -+ DRM_MODE_PROP_IMMUTABLE, -+ "NEXT_HDR_SINK_DATA", 0); -+ if (prop) { -+ hdmi->next_hdr_sink_data_property = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create_bool(connector->dev, DRM_MODE_PROP_IMMUTABLE, -+ "USER_SPLIT_MODE"); -+ if (prop) { -+ hdmi->user_split_mode_prop = prop; -+ drm_object_attach_property(&connector->base, prop, -+ hdmi->user_split_mode ? 1 : 0); -+ } -+ -+ if (!hdmi->is_hdmi_qp) { -+ prop = drm_property_create_enum(connector->dev, 0, -+ "output_hdmi_dvi", -+ output_hdmi_dvi_enum_list, -+ ARRAY_SIZE(output_hdmi_dvi_enum_list)); -+ if (prop) { -+ hdmi->output_hdmi_dvi = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create_enum(connector->dev, 0, -+ "output_type_capacity", -+ output_type_cap_list, -+ ARRAY_SIZE(output_type_cap_list)); -+ if (prop) { -+ hdmi->output_type_capacity = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ -+ prop = drm_property_create_enum(connector->dev, 0, -+ "hdmi_quant_range", -+ quant_range_enum_list, -+ ARRAY_SIZE(quant_range_enum_list)); -+ if (prop) { -+ hdmi->quant_range = prop; -+ drm_object_attach_property(&connector->base, prop, 0); -+ } -+ } -+#endif -+ -+ prop = connector->dev->mode_config.hdr_output_metadata_property; -+ if (version >= 0x211a || hdmi->is_hdmi_qp) -+ drm_object_attach_property(&connector->base, prop, 0); -+ -+ if (!drm_mode_create_hdmi_colorspace_property(connector, 0)) -+ drm_object_attach_property(&connector->base, -+ connector->colorspace_property, 0); -+ -+#if 0 -+ // [CC:] if this is not needed, also drop connector_id_prop -+ if (!private->connector_id_prop) -+ private->connector_id_prop = drm_property_create_range(connector->dev, -+ DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE, -+ "CONNECTOR_ID", 0, 0xf); -+ if (private->connector_id_prop) -+ drm_object_attach_property(&connector->base, private->connector_id_prop, hdmi->id); -+#endif -+} -+ -+static void -+dw_hdmi_rockchip_destroy_properties(struct drm_connector *connector, -+ void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ if (hdmi->color_depth_property) { -+ drm_property_destroy(connector->dev, -+ hdmi->color_depth_property); -+ hdmi->color_depth_property = NULL; -+ } -+ -+ if (hdmi->hdmi_output_property) { -+ drm_property_destroy(connector->dev, -+ hdmi->hdmi_output_property); -+ hdmi->hdmi_output_property = NULL; -+ } -+ -+ if (hdmi->colordepth_capacity) { -+ drm_property_destroy(connector->dev, -+ hdmi->colordepth_capacity); -+ hdmi->colordepth_capacity = NULL; -+ } -+ -+ if (hdmi->outputmode_capacity) { -+ drm_property_destroy(connector->dev, -+ hdmi->outputmode_capacity); -+ hdmi->outputmode_capacity = NULL; -+ } -+ -+ if (hdmi->quant_range) { -+ drm_property_destroy(connector->dev, -+ hdmi->quant_range); -+ hdmi->quant_range = NULL; -+ } -+ -+ if (hdmi->hdr_panel_metadata_property) { -+ drm_property_destroy(connector->dev, -+ hdmi->hdr_panel_metadata_property); -+ hdmi->hdr_panel_metadata_property = NULL; -+ } -+ -+ if (hdmi->next_hdr_sink_data_property) { -+ drm_property_destroy(connector->dev, -+ hdmi->next_hdr_sink_data_property); -+ hdmi->next_hdr_sink_data_property = NULL; -+ } -+ -+ if (hdmi->output_hdmi_dvi) { -+ drm_property_destroy(connector->dev, -+ hdmi->output_hdmi_dvi); -+ hdmi->output_hdmi_dvi = NULL; -+ } -+ -+ if (hdmi->output_type_capacity) { -+ drm_property_destroy(connector->dev, -+ hdmi->output_type_capacity); -+ hdmi->output_type_capacity = NULL; -+ } -+ -+ if (hdmi->user_split_mode_prop) { -+ drm_property_destroy(connector->dev, -+ hdmi->user_split_mode_prop); -+ hdmi->user_split_mode_prop = NULL; -+ } -+} -+ -+static int -+dw_hdmi_rockchip_set_property(struct drm_connector *connector, -+ struct drm_connector_state *state, -+ struct drm_property *property, -+ u64 val, -+ void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ struct drm_mode_config *config = &connector->dev->mode_config; -+ -+ if (property == hdmi->color_depth_property) { -+ hdmi->colordepth = val; -+ /* If hdmi is disconnected, state->crtc is null */ -+ if (!state->crtc) -+ return 0; -+ if (dw_hdmi_rockchip_check_color(state, hdmi)) -+ hdmi->color_changed++; -+ return 0; -+ } else if (property == hdmi->hdmi_output_property) { -+ hdmi->hdmi_output = val; -+ if (!state->crtc) -+ return 0; -+ if (dw_hdmi_rockchip_check_color(state, hdmi)) -+ hdmi->color_changed++; -+ return 0; -+ } else if (property == hdmi->quant_range) { -+ u64 quant_range = hdmi->hdmi_quant_range; -+ -+ hdmi->hdmi_quant_range = val; -+ if (quant_range != hdmi->hdmi_quant_range) -+ dw_hdmi_set_quant_range(hdmi->hdmi); -+ return 0; -+ } else if (property == config->hdr_output_metadata_property) { -+ return 0; -+ } else if (property == hdmi->output_hdmi_dvi) { -+ if (hdmi->force_output != val) -+ hdmi->color_changed++; -+ hdmi->force_output = val; -+ dw_hdmi_set_output_type(hdmi->hdmi, val); -+ return 0; -+ } else if (property == hdmi->colordepth_capacity) { -+ return 0; -+ } else if (property == hdmi->outputmode_capacity) { -+ return 0; -+ } else if (property == hdmi->output_type_capacity) { -+ return 0; -+ } -+ -+ DRM_ERROR("Unknown property [PROP:%d:%s]\n", -+ property->base.id, property->name); -+ -+ return -EINVAL; -+} -+ -+static int -+dw_hdmi_rockchip_get_property(struct drm_connector *connector, -+ const struct drm_connector_state *state, -+ struct drm_property *property, -+ u64 *val, -+ void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ struct drm_display_info *info = &connector->display_info; -+ struct drm_mode_config *config = &connector->dev->mode_config; -+ -+ if (property == hdmi->color_depth_property) { -+ *val = hdmi->colordepth; -+ return 0; -+ } else if (property == hdmi->hdmi_output_property) { -+ *val = hdmi->hdmi_output; -+ return 0; -+ } else if (property == hdmi->colordepth_capacity) { -+ *val = BIT(RK_IF_DEPTH_8); -+ /* RK3368 only support 8bit */ -+ if (hdmi->unsupported_deep_color) -+ return 0; -+ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) -+ *val |= BIT(RK_IF_DEPTH_10); -+ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) -+ *val |= BIT(RK_IF_DEPTH_12); -+ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_48) -+ *val |= BIT(RK_IF_DEPTH_16); -+ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) -+ *val |= BIT(RK_IF_DEPTH_420_10); -+ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) -+ *val |= BIT(RK_IF_DEPTH_420_12); -+ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) -+ *val |= BIT(RK_IF_DEPTH_420_16); -+ return 0; -+ } else if (property == hdmi->outputmode_capacity) { -+ *val = BIT(RK_IF_FORMAT_RGB); -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ *val |= BIT(RK_IF_FORMAT_YCBCR444); -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ *val |= BIT(RK_IF_FORMAT_YCBCR422); -+ if (connector->ycbcr_420_allowed && -+ info->color_formats & DRM_COLOR_FORMAT_YCBCR420) -+ *val |= BIT(RK_IF_FORMAT_YCBCR420); -+ return 0; -+ } else if (property == hdmi->quant_range) { -+ *val = hdmi->hdmi_quant_range; -+ return 0; -+ } else if (property == config->hdr_output_metadata_property) { -+ *val = state->hdr_output_metadata ? -+ state->hdr_output_metadata->base.id : 0; -+ return 0; -+ } else if (property == hdmi->output_hdmi_dvi) { -+ *val = hdmi->force_output; -+ return 0; -+ } else if (property == hdmi->output_type_capacity) { -+ *val = dw_hdmi_get_output_type_cap(hdmi->hdmi); -+ return 0; -+ } else if (property == hdmi->user_split_mode_prop) { -+ *val = hdmi->user_split_mode; -+ return 0; -+ } -+ -+ DRM_ERROR("Unknown property [PROP:%d:%s]\n", -+ property->base.id, property->name); -+ -+ return -EINVAL; -+} -+ -+static const struct dw_hdmi_property_ops dw_hdmi_rockchip_property_ops = { -+ .attach_properties = dw_hdmi_rockchip_attach_properties, -+ .destroy_properties = dw_hdmi_rockchip_destroy_properties, -+ .set_property = dw_hdmi_rockchip_set_property, -+ .get_property = dw_hdmi_rockchip_get_property, -+}; -+ - static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { - .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, - .mode_set = dw_hdmi_rockchip_encoder_mode_set, -@@ -356,20 +2518,24 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun - .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, - }; - --static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -- const struct drm_display_info *display, -- const struct drm_display_mode *mode) -+static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) - { - struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - -- return phy_power_on(hdmi->phy); -+ while (hdmi->phy->power_count > 0) -+ phy_power_off(hdmi->phy); - } - --static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) -+static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -+ const struct drm_display_info *display, -+ const struct drm_display_mode *mode) - { - struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - -- phy_power_off(hdmi->phy); -+ dw_hdmi_rockchip_genphy_disable(dw_hdmi, data); -+ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); -+ -+ return phy_power_on(hdmi->phy); - } - - static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) -@@ -436,6 +2602,90 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) - RK3328_HDMI_HPD_IOE)); - } - -+static void dw_hdmi_qp_rockchip_phy_disable(struct dw_hdmi_qp *dw_hdmi, -+ void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ while (hdmi->phy->power_count > 0) -+ phy_power_off(hdmi->phy); -+} -+ -+static int dw_hdmi_qp_rockchip_genphy_init(struct dw_hdmi_qp *dw_hdmi, void *data, -+ struct drm_display_mode *mode) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ dw_hdmi_qp_rockchip_phy_disable(dw_hdmi, data); -+ -+ return phy_power_on(hdmi->phy); -+} -+ -+static enum drm_connector_status -+dw_hdmi_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) -+{ -+ u32 val; -+ int ret; -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); -+ -+ if (!hdmi->id) { -+ if (val & RK3588_HDMI0_LEVEL_INT) { -+ hdmi->hpd_stat = true; -+ ret = connector_status_connected; -+ } else { -+ hdmi->hpd_stat = false; -+ ret = connector_status_disconnected; -+ } -+ } else { -+ if (val & RK3588_HDMI1_LEVEL_INT) { -+ hdmi->hpd_stat = true; -+ ret = connector_status_connected; -+ } else { -+ hdmi->hpd_stat = false; -+ ret = connector_status_disconnected; -+ } -+ } -+ -+ return ret; -+} -+ -+static void dw_hdmi_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ u32 val; -+ -+ if (!hdmi->id) { -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, -+ RK3588_HDMI0_HPD_INT_CLR) | -+ HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); -+ } else { -+ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, -+ RK3588_HDMI1_HPD_INT_CLR) | -+ HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); -+ } -+ -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+} -+ -+static void dw_hdmi_rk3588_phy_set_mode(struct dw_hdmi_qp *dw_hdmi, void *data, -+ u32 mode_mask, bool enable) -+{ -+ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; -+ -+ if (!hdmi->phy) -+ return; -+ -+ /* set phy earc/frl mode */ -+ if (enable) -+ hdmi->phy_bus_width |= mode_mask; -+ else -+ hdmi->phy_bus_width &= ~mode_mask; -+ -+ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); -+} -+ - static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { - .init = dw_hdmi_rockchip_genphy_init, - .disable = dw_hdmi_rockchip_genphy_disable, -@@ -525,6 +2775,30 @@ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { - .use_drm_infoframe = true, - }; - -+static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { -+ .init = dw_hdmi_qp_rockchip_genphy_init, -+ .disable = dw_hdmi_qp_rockchip_phy_disable, -+ .read_hpd = dw_hdmi_rk3588_read_hpd, -+ .setup_hpd = dw_hdmi_rk3588_setup_hpd, -+ .set_mode = dw_hdmi_rk3588_phy_set_mode, -+}; -+ -+struct rockchip_hdmi_chip_data rk3588_hdmi_chip_data = { -+ .lcdsel_grf_reg = -1, -+ .ddc_en_reg = RK3588_GRF_VO1_CON3, -+ .split_mode = true, -+}; -+ -+static const struct dw_hdmi_plat_data rk3588_hdmi_drv_data = { -+ .phy_data = &rk3588_hdmi_chip_data, -+ .qp_phy_ops = &rk3588_hdmi_phy_ops, -+ .phy_name = "samsung_hdptx_phy", -+ .phy_force_vendor = true, -+ .ycbcr_420_allowed = true, -+ .is_hdmi_qp = true, -+ .use_drm_infoframe = true, -+}; -+ - static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3228-dw-hdmi", - .data = &rk3228_hdmi_drv_data -@@ -541,6 +2815,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3568-dw-hdmi", - .data = &rk3568_hdmi_drv_data - }, -+ { .compatible = "rockchip,rk3588-dw-hdmi", -+ .data = &rk3588_hdmi_drv_data -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); -@@ -550,44 +2827,103 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - { - struct platform_device *pdev = to_platform_device(dev); - struct dw_hdmi_plat_data *plat_data; -- const struct of_device_id *match; - struct drm_device *drm = data; - struct drm_encoder *encoder; - struct rockchip_hdmi *hdmi; -+ struct rockchip_hdmi *secondary; - int ret; -+ u32 val; - - if (!pdev->dev.of_node) - return -ENODEV; - -- hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); -+ hdmi = platform_get_drvdata(pdev); - if (!hdmi) - return -ENOMEM; - -- match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); -- plat_data = devm_kmemdup(&pdev->dev, match->data, -- sizeof(*plat_data), GFP_KERNEL); -- if (!plat_data) -- return -ENOMEM; -+ plat_data = hdmi->plat_data; -+ hdmi->drm_dev = drm; - -- hdmi->dev = &pdev->dev; -- hdmi->plat_data = plat_data; -- hdmi->chip_data = plat_data->phy_data; - plat_data->phy_data = hdmi; -- plat_data->priv_data = hdmi; -- encoder = &hdmi->encoder.encoder; -+ plat_data->get_input_bus_format = -+ dw_hdmi_rockchip_get_input_bus_format; -+ plat_data->get_output_bus_format = -+ dw_hdmi_rockchip_get_output_bus_format; -+ plat_data->get_enc_in_encoding = -+ dw_hdmi_rockchip_get_enc_in_encoding; -+ plat_data->get_enc_out_encoding = -+ dw_hdmi_rockchip_get_enc_out_encoding; -+ plat_data->get_quant_range = -+ dw_hdmi_rockchip_get_quant_range; -+ plat_data->get_hdr_property = -+ dw_hdmi_rockchip_get_hdr_property; -+ plat_data->get_hdr_blob = -+ dw_hdmi_rockchip_get_hdr_blob; -+ plat_data->get_color_changed = -+ dw_hdmi_rockchip_get_color_changed; -+ // plat_data->get_edid_dsc_info = -+ // dw_hdmi_rockchip_get_edid_dsc_info; -+ // plat_data->get_next_hdr_data = -+ // dw_hdmi_rockchip_get_next_hdr_data; -+ plat_data->get_link_cfg = dw_hdmi_rockchip_get_link_cfg; -+ plat_data->set_grf_cfg = rk3588_set_grf_cfg; -+ // plat_data->convert_to_split_mode = drm_mode_convert_to_split_mode; -+ // plat_data->convert_to_origin_mode = drm_mode_convert_to_origin_mode; -+ -+ plat_data->property_ops = &dw_hdmi_rockchip_property_ops; -+ -+ secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); -+ /* If don't enable hdmi0 and hdmi1, we don't enable split mode */ -+ if (hdmi->chip_data->split_mode && secondary) { - -- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -- rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -- dev->of_node, 0, 0); -+ /* -+ * hdmi can only attach bridge and init encoder/connector in the -+ * last bind hdmi in split mode, or hdmi->hdmi_qp will not be initialized -+ * and plat_data->left/right will be null pointer. we must check if split -+ * mode is on and determine the sequence of hdmi bind. -+ */ -+ if (device_property_read_bool(dev, "split-mode") || -+ device_property_read_bool(secondary->dev, "split-mode")) { -+ plat_data->split_mode = true; -+ secondary->plat_data->split_mode = true; -+ if (!secondary->plat_data->first_screen) -+ plat_data->first_screen = true; -+ } -+ -+ if (device_property_read_bool(dev, "user-split-mode") || -+ device_property_read_bool(secondary->dev, "user-split-mode")) { -+ hdmi->user_split_mode = true; -+ secondary->user_split_mode = true; -+ } -+ } -+ -+ if (!plat_data->first_screen) { -+ encoder = &hdmi->encoder.encoder; -+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -+ dev->of_node, 0, 0); -+ /* -+ * If we failed to find the CRTC(s) which this encoder is -+ * supposed to be connected to, it's because the CRTC has -+ * not been registered yet. Defer probing, and hope that -+ * the required CRTC is added later. -+ */ -+ if (encoder->possible_crtcs == 0) -+ return -EPROBE_DEFER; -+ -+ drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); -+ // [CC:] consider using drmm_simple_encoder_alloc() -+ drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ } -+ -+ if (!plat_data->max_tmdsclk) -+ hdmi->max_tmdsclk = 594000; -+ else -+ hdmi->max_tmdsclk = plat_data->max_tmdsclk; - -- /* -- * If we failed to find the CRTC(s) which this encoder is -- * supposed to be connected to, it's because the CRTC has -- * not been registered yet. Defer probing, and hope that -- * the required CRTC is added later. -- */ -- if (encoder->possible_crtcs == 0) -- return -EPROBE_DEFER; -+ -+ hdmi->unsupported_yuv_input = plat_data->unsupported_yuv_input; -+ hdmi->unsupported_deep_color = plat_data->unsupported_deep_color; - - ret = rockchip_hdmi_parse_dt(hdmi); - if (ret) { -@@ -596,34 +2932,44 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -- hdmi->phy = devm_phy_optional_get(dev, "hdmi"); -- if (IS_ERR(hdmi->phy)) { -- ret = PTR_ERR(hdmi->phy); -- if (ret != -EPROBE_DEFER) -- DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); -+ ret = clk_prepare_enable(hdmi->aud_clk); -+ if (ret) { -+ dev_err(hdmi->dev, "Failed to enable HDMI aud_clk: %d\n", ret); - return ret; - } - -- ret = regulator_enable(hdmi->avdd_0v9); -+ ret = clk_prepare_enable(hdmi->hpd_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -- goto err_avdd_0v9; -+ dev_err(hdmi->dev, "Failed to enable HDMI hpd_clk: %d\n", ret); -+ return ret; - } - -- ret = regulator_enable(hdmi->avdd_1v8); -+ ret = clk_prepare_enable(hdmi->hclk_vo1); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -- goto err_avdd_1v8; -+ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vo1: %d\n", ret); -+ return ret; - } - -- ret = clk_prepare_enable(hdmi->ref_clk); -+ ret = clk_prepare_enable(hdmi->earc_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", -- ret); -- goto err_clk; -+ dev_err(hdmi->dev, "Failed to enable HDMI earc_clk: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(hdmi->hdmitx_ref); -+ if (ret) { -+ dev_err(hdmi->dev, "Failed to enable HDMI hdmitx_ref: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(hdmi->pclk); -+ if (ret) { -+ dev_err(hdmi->dev, "Failed to enable HDMI pclk: %d\n", ret); -+ return ret; - } - -- if (hdmi->chip_data == &rk3568_chip_data) { -+ if (hdmi->chip_data->ddc_en_reg == RK3568_GRF_VO_CON1) { - regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, - HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | - RK3568_HDMI_SCLIN_MSK, -@@ -631,12 +2977,131 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - RK3568_HDMI_SCLIN_MSK)); - } - -- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); -- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ if (hdmi->is_hdmi_qp) { -+ if (!hdmi->id) { -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, -+ RK3588_HDMI0_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ } else { -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, -+ RK3588_HDMI1_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ } -+ } - -- platform_set_drvdata(pdev, hdmi); -+ ret = clk_prepare_enable(hdmi->hclk_vio); -+ if (ret) { -+ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vio: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(hdmi->hclk_vop); -+ if (ret) { -+ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vop: %d\n", -+ ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(hdmi->ref_clk); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", -+ ret); -+ goto err_clk; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_0v9); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -+ goto err_avdd_0v9; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_1v8); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -+ goto err_avdd_1v8; -+ } -+ -+ if (!hdmi->id) -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); -+ else -+ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ if (hdmi->is_hdmi_qp) { -+ hdmi->hpd_irq = platform_get_irq(pdev, 4); -+ if (hdmi->hpd_irq < 0) -+ return hdmi->hpd_irq; -+ -+ ret = devm_request_threaded_irq(hdmi->dev, hdmi->hpd_irq, -+ rockchip_hdmi_hardirq, -+ rockchip_hdmi_irq, -+ IRQF_SHARED, "dw-hdmi-qp-hpd", -+ hdmi); -+ if (ret) -+ return ret; -+ } -+ -+ hdmi->phy = devm_phy_optional_get(dev, "hdmi"); -+ if (IS_ERR(hdmi->phy)) { -+ hdmi->phy = devm_phy_optional_get(dev, "hdmi_phy"); -+ if (IS_ERR(hdmi->phy)) { -+ ret = PTR_ERR(hdmi->phy); -+ if (ret != -EPROBE_DEFER) -+ DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); -+ return ret; -+ } -+ } -+ -+ if (hdmi->is_hdmi_qp) { -+ // [CC:] do proper error handling, e.g. clk_disable_unprepare -+ hdmi->hdmi_qp = dw_hdmi_qp_bind(pdev, &hdmi->encoder.encoder, plat_data); -+ -+ if (IS_ERR(hdmi->hdmi_qp)) { -+ ret = PTR_ERR(hdmi->hdmi_qp); -+ drm_encoder_cleanup(&hdmi->encoder.encoder); -+ } -+ -+ // if (plat_data->connector) { -+ // hdmi->sub_dev.connector = plat_data->connector; -+ // hdmi->sub_dev.of_node = dev->of_node; -+ // rockchip_drm_register_sub_dev(&hdmi->sub_dev); -+ // } -+ -+ if (plat_data->split_mode && secondary) { -+ if (device_property_read_bool(dev, "split-mode")) { -+ plat_data->right = secondary->hdmi_qp; -+ secondary->plat_data->left = hdmi->hdmi_qp; -+ } else { -+ plat_data->left = secondary->hdmi_qp; -+ secondary->plat_data->right = hdmi->hdmi_qp; -+ } -+ } -+ -+ return ret; -+ } - -- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); -+ hdmi->hdmi = dw_hdmi_bind(pdev, &hdmi->encoder.encoder, plat_data); - - /* - * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), -@@ -647,11 +3112,24 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - goto err_bind; - } - -+ // if (plat_data->connector) { -+ // hdmi->sub_dev.connector = plat_data->connector; -+ // hdmi->sub_dev.of_node = dev->of_node; -+ // rockchip_drm_register_sub_dev(&hdmi->sub_dev); -+ // } -+ - return 0; - - err_bind: -- drm_encoder_cleanup(encoder); -+ drm_encoder_cleanup(&hdmi->encoder.encoder); -+ clk_disable_unprepare(hdmi->aud_clk); - clk_disable_unprepare(hdmi->ref_clk); -+ clk_disable_unprepare(hdmi->hclk_vop); -+ clk_disable_unprepare(hdmi->hpd_clk); -+ clk_disable_unprepare(hdmi->hclk_vo1); -+ clk_disable_unprepare(hdmi->earc_clk); -+ clk_disable_unprepare(hdmi->hdmitx_ref); -+ clk_disable_unprepare(hdmi->pclk); - err_clk: - regulator_disable(hdmi->avdd_1v8); - err_avdd_1v8: -@@ -665,9 +3143,29 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - { - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - -- dw_hdmi_unbind(hdmi->hdmi); -+ if (hdmi->is_hdmi_qp) { -+ cancel_delayed_work(&hdmi->work); -+ flush_workqueue(hdmi->workqueue); -+ } -+ -+ // if (hdmi->sub_dev.connector) -+ // rockchip_drm_unregister_sub_dev(&hdmi->sub_dev); -+ // -+ if (hdmi->is_hdmi_qp) -+ dw_hdmi_qp_unbind(hdmi->hdmi_qp); -+ else -+ dw_hdmi_unbind(hdmi->hdmi); -+ - drm_encoder_cleanup(&hdmi->encoder.encoder); -+ -+ clk_disable_unprepare(hdmi->aud_clk); - clk_disable_unprepare(hdmi->ref_clk); -+ clk_disable_unprepare(hdmi->hclk_vop); -+ clk_disable_unprepare(hdmi->hpd_clk); -+ clk_disable_unprepare(hdmi->hclk_vo1); -+ clk_disable_unprepare(hdmi->earc_clk); -+ clk_disable_unprepare(hdmi->hdmitx_ref); -+ clk_disable_unprepare(hdmi->pclk); - - regulator_disable(hdmi->avdd_1v8); - regulator_disable(hdmi->avdd_0v9); -@@ -680,30 +3178,142 @@ static const struct component_ops dw_hdmi_rockchip_ops = { - - static int dw_hdmi_rockchip_probe(struct platform_device *pdev) - { -+ struct rockchip_hdmi *hdmi; -+ const struct of_device_id *match; -+ struct dw_hdmi_plat_data *plat_data; -+ int id; -+ -+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ id = of_alias_get_id(pdev->dev.of_node, "hdmi"); -+ if (id < 0) -+ id = 0; -+ -+ hdmi->id = id; -+ hdmi->dev = &pdev->dev; -+ -+ match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); -+ plat_data = devm_kmemdup(&pdev->dev, match->data, -+ sizeof(*plat_data), GFP_KERNEL); -+ if (!plat_data) -+ return -ENOMEM; -+ -+ plat_data->id = hdmi->id; -+ hdmi->plat_data = plat_data; -+ hdmi->chip_data = plat_data->phy_data; -+ hdmi->is_hdmi_qp = plat_data->is_hdmi_qp; -+ -+ if (hdmi->is_hdmi_qp) { -+ hdmi->workqueue = create_workqueue("hpd_queue"); -+ INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event); -+ } -+ -+ platform_set_drvdata(pdev, hdmi); -+ pm_runtime_enable(&pdev->dev); -+ pm_runtime_get_sync(&pdev->dev); -+ - return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); - } - -+static void dw_hdmi_rockchip_shutdown(struct platform_device *pdev) -+{ -+ struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); -+ -+ if (!hdmi) -+ return; -+ -+ if (hdmi->is_hdmi_qp) { -+ cancel_delayed_work(&hdmi->work); -+ flush_workqueue(hdmi->workqueue); -+ dw_hdmi_qp_suspend(hdmi->dev, hdmi->hdmi_qp); -+ } else { -+ dw_hdmi_suspend(hdmi->hdmi); -+ } -+ pm_runtime_put_sync(&pdev->dev); -+} -+ - static void dw_hdmi_rockchip_remove(struct platform_device *pdev) - { -+ struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); -+ - component_del(&pdev->dev, &dw_hdmi_rockchip_ops); -+ pm_runtime_disable(&pdev->dev); -+ -+ if (hdmi->is_hdmi_qp) -+ destroy_workqueue(hdmi->workqueue); -+} -+ -+static int __maybe_unused dw_hdmi_rockchip_suspend(struct device *dev) -+{ -+ struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); -+ -+ if (hdmi->is_hdmi_qp) -+ dw_hdmi_qp_suspend(dev, hdmi->hdmi_qp); -+ else -+ dw_hdmi_suspend(hdmi->hdmi); -+ -+ pm_runtime_put_sync(dev); -+ -+ return 0; - } - - static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev) - { - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); -+ u32 val; - -- dw_hdmi_resume(hdmi->hdmi); -+ if (hdmi->is_hdmi_qp) { -+ if (!hdmi->id) { -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, -+ RK3588_HDMI0_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ } else { -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, -+ RK3588_HDMI1_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ } -+ -+ dw_hdmi_qp_resume(dev, hdmi->hdmi_qp); -+ drm_helper_hpd_irq_event(hdmi->drm_dev); -+ } else { -+ dw_hdmi_resume(hdmi->hdmi); -+ } -+ pm_runtime_get_sync(dev); - - return 0; - } - - static const struct dev_pm_ops dw_hdmi_rockchip_pm = { -- SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume) -+ SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend, -+ dw_hdmi_rockchip_resume) - }; - - struct platform_driver dw_hdmi_rockchip_pltfm_driver = { - .probe = dw_hdmi_rockchip_probe, - .remove_new = dw_hdmi_rockchip_remove, -+ .shutdown = dw_hdmi_rockchip_shutdown, - .driver = { - .name = "dwhdmi-rockchip", - .pm = &dw_hdmi_rockchip_pm, -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 111111111111..222222222222 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -6,12 +6,14 @@ - #ifndef __DW_HDMI__ - #define __DW_HDMI__ - -+#include - #include - - struct drm_display_info; - struct drm_display_mode; - struct drm_encoder; - struct dw_hdmi; -+struct dw_hdmi_qp; - struct platform_device; - - /** -@@ -92,6 +94,13 @@ enum dw_hdmi_phy_type { - DW_HDMI_PHY_VENDOR_PHY = 0xfe, - }; - -+struct dw_hdmi_audio_tmds_n { -+ unsigned long tmds; -+ unsigned int n_32k; -+ unsigned int n_44k1; -+ unsigned int n_48k; -+}; -+ - struct dw_hdmi_mpll_config { - unsigned long mpixelclock; - struct { -@@ -112,6 +121,15 @@ struct dw_hdmi_phy_config { - u16 vlev_ctr; /* voltage level control */ - }; - -+struct dw_hdmi_link_config { -+ bool dsc_mode; -+ bool frl_mode; -+ int frl_lanes; -+ int rate_per_lane; -+ int hcactive; -+ u8 pps_payload[128]; -+}; -+ - struct dw_hdmi_phy_ops { - int (*init)(struct dw_hdmi *hdmi, void *data, - const struct drm_display_info *display, -@@ -123,14 +141,52 @@ struct dw_hdmi_phy_ops { - void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); - }; - -+struct dw_hdmi_qp_phy_ops { -+ int (*init)(struct dw_hdmi_qp *hdmi, void *data, -+ struct drm_display_mode *mode); -+ void (*disable)(struct dw_hdmi_qp *hdmi, void *data); -+ enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, -+ void *data); -+ void (*update_hpd)(struct dw_hdmi_qp *hdmi, void *data, -+ bool force, bool disabled, bool rxsense); -+ void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); -+ void (*set_mode)(struct dw_hdmi_qp *dw_hdmi, void *data, -+ u32 mode_mask, bool enable); -+}; -+ -+struct dw_hdmi_property_ops { -+ void (*attach_properties)(struct drm_connector *connector, -+ unsigned int color, int version, -+ void *data); -+ void (*destroy_properties)(struct drm_connector *connector, -+ void *data); -+ int (*set_property)(struct drm_connector *connector, -+ struct drm_connector_state *state, -+ struct drm_property *property, -+ u64 val, -+ void *data); -+ int (*get_property)(struct drm_connector *connector, -+ const struct drm_connector_state *state, -+ struct drm_property *property, -+ u64 *val, -+ void *data); -+}; -+ - struct dw_hdmi_plat_data { - struct regmap *regm; - -+ //[CC:] not in dowstream - unsigned int output_port; - -+ unsigned long input_bus_format; - unsigned long input_bus_encoding; -+ unsigned int max_tmdsclk; -+ int id; - bool use_drm_infoframe; - bool ycbcr_420_allowed; -+ bool unsupported_yuv_input; -+ bool unsupported_deep_color; -+ bool is_hdmi_qp; - - /* - * Private data passed to all the .mode_valid() and .configure_phy() -@@ -139,6 +195,7 @@ struct dw_hdmi_plat_data { - void *priv_data; - - /* Platform-specific mode validation (optional). */ -+ //[CC:] downstream changed "struct dw_hdmi *hdmi" to "struct drm_connector *connector" - enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, - const struct drm_display_info *info, - const struct drm_display_mode *mode); -@@ -150,18 +207,50 @@ struct dw_hdmi_plat_data { - - /* Vendor PHY support */ - const struct dw_hdmi_phy_ops *phy_ops; -+ const struct dw_hdmi_qp_phy_ops *qp_phy_ops; - const char *phy_name; - void *phy_data; - unsigned int phy_force_vendor; - -+ /* split mode */ -+ bool split_mode; -+ bool first_screen; -+ struct dw_hdmi_qp *left; -+ struct dw_hdmi_qp *right; -+ - /* Synopsys PHY support */ - const struct dw_hdmi_mpll_config *mpll_cfg; -+ const struct dw_hdmi_mpll_config *mpll_cfg_420; - const struct dw_hdmi_curr_ctrl *cur_ctr; - const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, void *data, - unsigned long mpixelclock); - - unsigned int disable_cec : 1; -+ -+ //[CC:] 7b29b5f29585 ("drm/rockchip: dw_hdmi: Support HDMI 2.0 YCbCr 4:2:0") -+ unsigned long (*get_input_bus_format)(void *data); -+ unsigned long (*get_output_bus_format)(void *data); -+ unsigned long (*get_enc_in_encoding)(void *data); -+ unsigned long (*get_enc_out_encoding)(void *data); -+ -+ unsigned long (*get_quant_range)(void *data); -+ struct drm_property *(*get_hdr_property)(void *data); -+ struct drm_property_blob *(*get_hdr_blob)(void *data); -+ bool (*get_color_changed)(void *data); -+ int (*get_yuv422_format)(struct drm_connector *connector, -+ struct edid *edid); -+ int (*get_edid_dsc_info)(void *data, struct edid *edid); -+ int (*get_next_hdr_data)(void *data, struct edid *edid, -+ struct drm_connector *connector); -+ struct dw_hdmi_link_config *(*get_link_cfg)(void *data); -+ void (*set_grf_cfg)(void *data); -+ void (*convert_to_split_mode)(struct drm_display_mode *mode); -+ void (*convert_to_origin_mode)(struct drm_display_mode *mode); -+ -+ /* Vendor Property support */ -+ const struct dw_hdmi_property_ops *property_ops; -+ struct drm_connector *connector; - }; - - struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, -@@ -172,6 +261,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, - struct drm_encoder *encoder, - const struct dw_hdmi_plat_data *plat_data); - -+void dw_hdmi_suspend(struct dw_hdmi *hdmi); - void dw_hdmi_resume(struct dw_hdmi *hdmi); - - void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); -@@ -205,6 +295,17 @@ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, - void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, - bool force, bool disabled, bool rxsense); - void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); -+void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi); -+void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val); -+bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi); -+int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi); -+ -+void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi); -+struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, -+ struct drm_encoder *encoder, -+ struct dw_hdmi_plat_data *plat_data); -+void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi); -+void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); - - bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); - --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch deleted file mode 100644 index 4c0ad9def237..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: ColorfulRhino -Date: Wed, 12 Jun 2024 12:17:18 +0200 -Subject: Fix HDMI controller patch at - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c - ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -5,6 +5,7 @@ - * Algea Cao - */ - #include -+#include - #include - #include - #include --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0170-drm-rockchip-vop2-add-clocks-reset-support.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0170-drm-rockchip-vop2-add-clocks-reset-support.patch deleted file mode 100644 index 68ee38e939cb..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0170-drm-rockchip-vop2-add-clocks-reset-support.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Fri, 3 May 2024 14:27:39 -0400 -Subject: vop2: Add clock resets support - -At the end of initialization, each VP clock needs to be reset before -they can be used. - -Failing to do so can put the VOP in an undefined state where the -generated HDMI signal is either lost or not matching the selected mode. - -Signed-off-by: Detlev Casanova ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -159,6 +160,7 @@ struct vop2_win { - struct vop2_video_port { - struct drm_crtc crtc; - struct vop2 *vop2; -+ struct reset_control *dclk_rst; - struct clk *dclk; - unsigned int id; - const struct vop2_video_port_data *data; -@@ -2064,6 +2066,26 @@ static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name) - return NULL; - } - -+static int vop2_clk_reset(struct vop2_video_port *vp) -+{ -+ struct reset_control *rstc = vp->dclk_rst; -+ struct vop2 *vop2 = vp->vop2; -+ int ret; -+ -+ if (!rstc) -+ return 0; -+ -+ ret = reset_control_assert(rstc); -+ if (ret < 0) -+ drm_warn(vop2->drm, "failed to assert reset\n"); -+ udelay(10); -+ ret = reset_control_deassert(rstc); -+ if (ret < 0) -+ drm_warn(vop2->drm, "failed to deassert reset\n"); -+ -+ return ret; -+} -+ - static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) - { -@@ -2233,6 +2255,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - - vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); - -+ vop2_clk_reset(vp); -+ - drm_crtc_vblank_on(crtc); - - vop2_unlock(vop2); -@@ -2920,6 +2944,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) - vp->data = vp_data; - - snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); -+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name); -+ if (IS_ERR(vp->dclk_rst)) { -+ drm_err(vop2->drm, "failed to get %s reset\n", dclk_name); -+ return PTR_ERR(vp->dclk_rst); -+ } -+ - vp->dclk = devm_clk_get(vop2->dev, dclk_name); - if (IS_ERR(vp->dclk)) { - drm_err(vop2->drm, "failed to get %s\n", dclk_name); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Fri, 3 May 2024 14:28:12 -0400 -Subject: arm64: dts: rockchip: Add VOP clock resets for rk3588s - -This adds the needed clock resets for all rk3588(s) based SOCs. - -Signed-off-by: Detlev Casanova ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1429,6 +1429,14 @@ vop: vop@fdd90000 { - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; -+ resets = <&cru SRST_D_VOP0>, -+ <&cru SRST_D_VOP1>, -+ <&cru SRST_D_VOP2>, -+ <&cru SRST_D_VOP3>; -+ reset-names = "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2", -+ "dclk_vp3"; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Mon, 6 May 2024 13:54:01 -0400 -Subject: dt-bindings: display: vop2: Add VP clock resets - -Add the documentation for VOP2 video ports reset clocks. -One reset can be set per video port. - -Signed-off-by: Detlev Casanova ---- - Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -@@ -65,6 +65,22 @@ properties: - - const: dclk_vp3 - - const: pclk_vop - -+ resets: -+ minItems: 3 -+ items: -+ - description: Pixel clock reset for video port 0. -+ - description: Pixel clock reset for video port 1. -+ - description: Pixel clock reset for video port 2. -+ - description: Pixel clock reset for video port 3. -+ -+ reset-names: -+ minItems: 3 -+ items: -+ - const: dclk_vp0 -+ - const: dclk_vp1 -+ - const: dclk_vp2 -+ - const: dclk_vp3 -+ - rockchip,grf: - $ref: /schemas/types.yaml#/definitions/phandle - description: -@@ -128,6 +144,11 @@ allOf: - clock-names: - minItems: 7 - -+ resets: -+ minItems: 4 -+ reset-names: -+ minItems: 4 -+ - ports: - required: - - port@0 -@@ -183,6 +204,12 @@ examples: - "dclk_vp0", - "dclk_vp1", - "dclk_vp2"; -+ resets = <&cru SRST_VOP0>, -+ <&cru SRST_VOP1>, -+ <&cru SRST_VOP2>; -+ reset-names = "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2"; - power-domains = <&power RK3568_PD_VO>; - iommus = <&vop_mmu>; - vop_out: ports { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0801-wireless-add-bcm43752.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0801-wireless-add-bcm43752.patch deleted file mode 100644 index 0085fdff2805..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0801-wireless-add-bcm43752.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Wed, 28 Feb 2024 20:59:15 +0100 -Subject: net: wireless: brcmfmac: Add support for AP6275P - -This module features BCM43752A2 chipset. The firmware requires -randomness seeding, so enabled it. - -Signed-off-by: Ondrej Jirman ---- - drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 5 ++++- - drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 2 ++ - 2 files changed, 6 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -index 111111111111..222222222222 100644 ---- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -@@ -70,6 +70,7 @@ BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie"); - BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); - BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie"); - BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie"); -+BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie"); - - /* firmware config files */ - MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); -@@ -104,6 +105,7 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { - BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), - BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), - BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), -+ BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752), - BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */ - BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */ - BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */ -@@ -1720,7 +1722,7 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, - memcpy_toio(devinfo->tcm + address, nvram, nvram_len); - brcmf_fw_nvram_free(nvram); - -- if (devinfo->otp.valid) { -+ if (devinfo->otp.valid || devinfo->ci->chip == BRCM_CC_43752_CHIP_ID) { - size_t rand_len = BRCMF_RANDOM_SEED_LENGTH; - struct brcmf_random_seed_footer footer = { - .length = cpu_to_le32(rand_len), -@@ -2700,6 +2702,7 @@ static const struct pci_device_id brcmf_pcie_devid_table[] = { - BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA), - BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC), - BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW), -+ BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC), - BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC), - BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC), - BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC), -diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h -index 111111111111..222222222222 100644 ---- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h -+++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h -@@ -52,6 +52,7 @@ - #define BRCM_CC_43664_CHIP_ID 43664 - #define BRCM_CC_43666_CHIP_ID 43666 - #define BRCM_CC_4371_CHIP_ID 0x4371 -+#define BRCM_CC_43752_CHIP_ID 43752 - #define BRCM_CC_4377_CHIP_ID 0x4377 - #define BRCM_CC_4378_CHIP_ID 0x4378 - #define BRCM_CC_4387_CHIP_ID 0x4387 -@@ -94,6 +95,7 @@ - #define BRCM_PCIE_4366_5G_DEVICE_ID 0x43c5 - #define BRCM_PCIE_4371_DEVICE_ID 0x440d - #define BRCM_PCIE_43596_DEVICE_ID 0x4415 -+#define BRCM_PCIE_43752_DEVICE_ID 0x449d - #define BRCM_PCIE_4377_DEVICE_ID 0x4488 - #define BRCM_PCIE_4378_DEVICE_ID 0x4425 - #define BRCM_PCIE_4387_DEVICE_ID 0x4433 --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/0802-wireless-add-clk-property.patch b/patch/kernel/archive/rockchip-rk3588-6.10/0802-wireless-add-clk-property.patch deleted file mode 100644 index 193f9892bbe2..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/0802-wireless-add-clk-property.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Wed, 28 Feb 2024 21:09:51 +0100 -Subject: net: wireless: brcmfmac: Add optional 32k clock enable support - -WiFi modules often require 32kHz clock to function. Add support to -enable the clock to pcie driver. - -Signed-off-by: Ondrej Jirman ---- - drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -index 111111111111..222222222222 100644 ---- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c -@@ -3,6 +3,7 @@ - * Copyright (c) 2014 Broadcom Corporation - */ - -+#include - #include - #include - #include -@@ -2413,6 +2414,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) - struct brcmf_pciedev *pcie_bus_dev; - struct brcmf_core *core; - struct brcmf_bus *bus; -+ struct clk *clk; - - if (!id) { - id = pci_match_id(brcmf_pcie_devid_table, pdev); -@@ -2424,6 +2426,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) - - brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); - -+ clk = devm_clk_get_optional_enabled(&pdev->dev, "32k"); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ if (clk) { -+ dev_info(&pdev->dev, "enabling 32kHz clock\n"); -+ clk_set_rate(clk, 32768); -+ } -+ - ret = -ENOMEM; - devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); - if (devinfo == NULL) --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch deleted file mode 100644 index 326476f8c143..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Wed, 27 Dec 2023 15:03:57 +0800 -Subject: arm64: dts: rock-5b: Slow down emmc to hs200 and add tsadc node - ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -371,8 +371,7 @@ &sdhci { - no-sdio; - no-sd; - non-removable; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -+ mmc-hs200-1_8v; - status = "okay"; - }; - -@@ -412,6 +411,10 @@ &sdio { - status = "okay"; - }; - -+&tsadc { -+ status = "okay"; -+}; -+ - &uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch deleted file mode 100644 index bcf1f9460e7c..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: lanefu -Date: Sat, 20 Jan 2024 17:16:20 +0000 -Subject: rock-5b enable SPI flash in device tree - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts - -Signed-off-by: lanefu ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 27 ++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -421,6 +421,33 @@ &uart6 { - status = "okay"; - }; - -+&sfc { -+ status = "okay"; -+ -+ spi_flash: spi-flash@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <50000000>; -+ spi-tx-bus-width = <1>; -+ spi-rx-bus-width = <4>; -+ status = "okay"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ loader@0 { -+ label = "loader"; -+ reg = <0x0 0x1000000>; -+ }; -+ }; -+ }; -+ -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch deleted file mode 100644 index 618d12de804a..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 15 Jan 2024 22:51:17 +0200 -Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b - -Add the necessary DT changes to enable HDMI0 on Rock 5B. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -185,6 +186,20 @@ &gpu { - status = "okay"; - }; - -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -837,3 +852,18 @@ &usb_host1_xhci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch deleted file mode 100644 index 3361d1475e07..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Fri, 3 Nov 2023 20:05:05 +0200 -Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b - -The initial vop2 support for rk3588 in mainline is not able to handle -all display modes supported by connected displays, e.g. -2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. - -Additionally, it doesn't cope with non-integer refresh rates like 59.94, -29.97, 23.98, etc. - -Make use of the HDMI0 PHY PLL to support the additional display modes. - -Note this requires commit "drm/rockchip: vop2: Improve display modes -handling on rk3588", which needs a rework to be upstreamable. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -186,6 +186,11 @@ &gpu { - status = "okay"; - }; - -+&display_subsystem { -+ clocks = <&hdptxphy_hdmi0>; -+ clock-names = "hdmi0_phy_pll"; -+}; -+ - &hdmi0 { - status = "okay"; - }; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1015-board-rock5b-automatic-fan-control.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1015-board-rock5b-automatic-fan-control.patch deleted file mode 100644 index 994755002207..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1015-board-rock5b-automatic-fan-control.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Mon, 6 May 2024 13:36:35 +0400 -Subject: arm64: dts: rockchip: enable automatic fan control on Rock 5B - -This links the PWM fan on Radxa Rock 5B as an active cooling device -managed automatically by the thermal subsystem, with a target SoC -temperature of 65C and a minimum-spin interval from 55C to 65C to -ensure airflow when the system gets warm - -Helped-by: Dragan Simic -Reviewed-by: Dragan Simic -Signed-off-by: Alexey Charkov ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 +++++++++- - 1 file changed, 29 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -53,7 +53,7 @@ led_rgb_b { - - fan: pwm-fan { - compatible = "pwm-fan"; -- cooling-levels = <0 95 145 195 255>; -+ cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; -@@ -299,6 +299,34 @@ i2s0_8ch_p0_0: endpoint { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch deleted file mode 100644 index e26dc7a343a1..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 27 Feb 2024 16:04:42 +0300 -Subject: Add HDMI and VOP2 to Rock 5A - ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -765,3 +766,32 @@ &usb_host1_ohci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch deleted file mode 100644 index da231f67ce8d..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 28 Mar 2024 00:41:34 +0800 -Subject: arch: arm64: dts: enable gpu node for rock-5a - ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -281,6 +281,11 @@ &gmac1_rgmii_clk - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &mdio1 { - rgmii_phy1: ethernet-phy@1 { - /* RTL8211F */ -@@ -434,6 +439,7 @@ rk806_dvs3_null: dvs3-null-pins { - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; -+ regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch deleted file mode 100644 index 7814d306607b..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch +++ /dev/null @@ -1,322 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 16 Nov 2023 18:15:09 +0300 -Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus - ---- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 221 +++++++++- - 1 file changed, 218 insertions(+), 3 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -72,6 +73,17 @@ ir-receiver { - pinctrl-0 = <&ir_receiver_pin>; - }; - -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; -@@ -98,10 +110,10 @@ pwm-leds { - - led { - color = ; -- function = LED_FUNCTION_INDICATOR; -- function-enumerator = <2>; -+ function = LED_FUNCTION_HEARTBEAT; - max-brightness = <255>; - pwms = <&pwm2 0 25000 0>; -+ linux,default-trigger = "heartbeat"; - }; - }; - -@@ -158,6 +170,20 @@ daicodec: simple-audio-card,codec { - }; - }; - -+ wlan-rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-wlan"; -+ radio-type = "wlan"; -+ shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ bluetooth-rfkill { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-bluetooth"; -+ radio-type = "bluetooth"; -+ shutdown-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ }; -+ - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -199,6 +225,18 @@ vcc5v0_sys: vcc5v0-sys-regulator { - regulator-max-microvolt = <5000000>; - }; - -+ vbus5v0_typec: vbus5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc5v0_usb20: vcc5v0-usb20-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -311,6 +349,53 @@ hym8563: rtc@51 { - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -+ -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vbus5v0_typec>; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "dual"; -+ try-power-role = "source"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = ; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; -+ }; -+ }; - }; - - &i2c7 { -@@ -383,9 +468,15 @@ &pcie3x4 { - }; - - &pinctrl { -+ hdmirx { -+ hdmirx_hpd: hdmirx-hpd { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - hym8563 { - hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - -@@ -408,6 +499,14 @@ hp_detect: hp-detect { - }; - - usb { -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usbc0_int: usbc0-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ - vcc5v0_usb20_en: vcc5v0-usb20-en { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -803,6 +902,22 @@ &tsadc { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ - &u2phy2 { - status = "okay"; - }; -@@ -831,6 +946,35 @@ &uart9 { - status = "okay"; - }; - -+&usbdp_phy0 { -+ orientation-switch; -+ mode-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ svid = <0xff01>; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ -+&usbdp_phy1 { -+ rockchip,dp-lane-mux = <2 3>; -+ status = "okay"; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -839,6 +983,20 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "otg"; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; -@@ -846,3 +1004,60 @@ &usb_host1_ehci { - &usb_host1_ohci { - status = "okay"; - }; -+ -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0 { -+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdmi_receiver_cma { -+ status = "disabled"; -+}; -+ -+&hdmi_receiver { -+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch deleted file mode 100644 index bd33b5976c41..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 28 Mar 2024 16:07:18 +0800 -Subject: arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5a - ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -115,6 +115,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - }; - }; - -+&combphy0_ps { -+ status = "okay"; -+}; -+ - &combphy2_psu { - status = "okay"; - }; -@@ -299,6 +303,11 @@ rgmii_phy1: ethernet-phy@1 { - }; - }; - -+&pcie2x1l2 { -+ status = "okay"; -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+}; -+ - &pinctrl { - leds { - io_led: io-led { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch deleted file mode 100644 index 6eae8e695661..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Thu, 6 Jun 2024 23:28:01 +0800 -Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7 - ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -159,11 +160,30 @@ &cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - }; - -+&display_subsystem { -+ clocks = <&hdptxphy_hdmi0>; -+ clock-names = "hdmi0_phy_pll"; -+}; -+ - &gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; - }; - -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -@@ -723,3 +743,18 @@ &usb_host1_xhci { - dr_mode = "host"; - status = "okay"; - }; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch deleted file mode 100644 index a57707485c0e..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Thu, 6 Jun 2024 23:29:39 +0800 -Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7 - ---- - arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts -@@ -283,6 +283,22 @@ &pcie2x1l0 { - &pcie2x1l1 { - reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x300000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ device_type = "pci"; -+ bus-range = <0x30 0x3f>; -+ -+ wifi: wifi@0,0 { -+ compatible = "pci14e4,449d"; -+ reg = <0x310000 0 0 0 0>; -+ clocks = <&hym8563>; -+ clock-names = "32k"; -+ }; -+ }; - }; - - /* phy0 - left ethernet port */ --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1040-board-khadas-edge2-add-nodes.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1040-board-khadas-edge2-add-nodes.patch deleted file mode 100644 index 17e8fbd06bcd..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1040-board-khadas-edge2-add-nodes.patch +++ /dev/null @@ -1,359 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 12 Feb 2024 17:35:13 +0300 -Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2 - -Khadas Edge 2 has 2x Type-C port. One just supports PD and -controlled by MCU. The other one supports PD, DP Alt mode and DRD. This -commit adds support for DRD. - -Signed-off-by: Muhammed Efe Cetin ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 120 ++++++++++ - 1 file changed, 120 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -76,6 +77,18 @@ blue_led: led-2 { - }; - }; - -+ vbus5v0_typec: vbus5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&vcc5v0_sys>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ }; -+ - vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -224,6 +237,56 @@ regulator-state-mem { - &i2c2 { - status = "okay"; - -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vbus5v0_typec>; -+ status = "okay"; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "dual"; -+ try-power-role = "source"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = ; -+ source-pdos = ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_orien_sw: endpoint { -+ remote-endpoint = <&usbdp_phy0_orientation_switch>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_role_sw: endpoint { -+ remote-endpoint = <&dwc3_0_role_switch>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ dp_altmode_mux: endpoint { -+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; -@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en { - }; - }; - -+ usb-typec { -+ usbc0_int: usbc0-int { -+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -681,6 +754,15 @@ &uart9 { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+ - &u2phy2 { - status = "okay"; - }; -@@ -707,6 +789,44 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdp_phy0 { -+ orientation-switch; -+ mode-switch; -+ svid = <0xff01>; -+ sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_orientation_switch: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_orien_sw>; -+ }; -+ -+ usbdp_phy0_dp_altmode_mux: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dp_altmode_mux>; -+ }; -+ }; -+}; -+ -+&usb_host0_xhci { -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dwc3_0_role_switch: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_role_sw>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 12 Feb 2024 17:35:13 +0300 -Subject: arm64: dts: rockchip: Add bluetooth support to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 18 +++++++++- - 1 file changed, 17 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -750,8 +750,24 @@ &uart2 { - - &uart9 { - pinctrl-names = "default"; -- pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; -+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&hym8563>; -+ clock-names = "lpo"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wakeup"; -+ device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>; -+ vbat-supply = <&vcc_3v3_s3>; -+ vddio-supply = <&vcc_1v8_s3>; -+ }; - }; - - &u2phy0 { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 19 Feb 2024 23:32:11 +0300 -Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 53 ++++++++++ - 1 file changed, 53 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -43,6 +44,17 @@ ir-receiver { - pinctrl-0 = <&ir_receiver_pin>; - }; - -+ hdmi0-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi0_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "pwm-leds"; - -@@ -830,6 +842,7 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 { - }; - - &usb_host0_xhci { -+ dr-mode = "otg"; - usb-role-switch; - status = "okay"; - -@@ -854,3 +867,43 @@ &usb_host1_ohci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&hdmi0 { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi0_con_in>; -+ }; -+}; -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&display_subsystem { -+ clocks = <&hdptxphy_hdmi0>; -+ clock-names = "hdmi0_phy_pll"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Sat, 2 Mar 2024 19:13:59 +0300 -Subject: arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 17 ++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -368,6 +368,23 @@ &pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_wl>; - status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x400000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ device_type = "pci"; -+ bus-range = <0x40 0x4f>; -+ -+ wifi: wifi@0,0 { -+ compatible = "pci14e4,449d"; -+ reg = <0x410000 0 0 0 0>; -+ clocks = <&hym8563>; -+ clock-names = "32k"; -+ }; -+ }; -+ - }; - - &pwm11 { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1041-board-khadas-edge2-mcu.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1041-board-khadas-edge2-mcu.patch deleted file mode 100644 index 856b524ef432..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1041-board-khadas-edge2-mcu.patch +++ /dev/null @@ -1,441 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:09:25 +0300 -Subject: mfd: khadas-mcu: add Edge2 registers - ---- - drivers/mfd/khadas-mcu.c | 8 +++- - include/linux/mfd/khadas-mcu.h | 24 ++++++++++ - 2 files changed, 30 insertions(+), 2 deletions(-) - -diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c -index 111111111111..222222222222 100644 ---- a/drivers/mfd/khadas-mcu.c -+++ b/drivers/mfd/khadas-mcu.c -@@ -26,6 +26,10 @@ static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg) - case KHADAS_MCU_CHECK_USER_PASSWD_REG: - case KHADAS_MCU_WOL_INIT_START_REG: - case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG: -+ case KHADAS_MCU_LED_ON_RAM_REG: -+ case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2: -+ case KHADAS_MCU_WDT_EN_REG: -+ case KHADAS_MCU_SYS_RST_REG: - return true; - default: - return false; -@@ -69,14 +73,14 @@ static const struct regmap_config khadas_mcu_regmap_config = { - .reg_bits = 8, - .reg_stride = 1, - .val_bits = 8, -- .max_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, -+ .max_register = KHADAS_MCU_SYS_RST_REG, - .volatile_reg = khadas_mcu_reg_volatile, - .writeable_reg = khadas_mcu_reg_writeable, - .cache_type = REGCACHE_MAPLE, - }; - - static struct mfd_cell khadas_mcu_fan_cells[] = { -- /* VIM1/2 Rev13+ and VIM3 only */ -+ /* VIM1/2 Rev13+, VIM3 and Edge2 only */ - { .name = "khadas-mcu-fan-ctrl", }, - }; - -diff --git a/include/linux/mfd/khadas-mcu.h b/include/linux/mfd/khadas-mcu.h -index 111111111111..222222222222 100644 ---- a/include/linux/mfd/khadas-mcu.h -+++ b/include/linux/mfd/khadas-mcu.h -@@ -35,26 +35,45 @@ - #define KHADAS_MCU_FACTORY_TEST_REG 0x16 /* R */ - #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */ - #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */ -+#define KHADAS_MCU_BOOT_EN_DCIN_REG_V2 0x21 /* RW */ - #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */ - #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */ -+#define KHADAS_MCU_LED_MODE_ON_REG_V2 0x23 /* RW */ -+#define KHADAS_MCU_LED_MODE_OFF_REG_V2 0x24 /* RW */ - #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */ - #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */ -+#define KHADAS_MCU_RGB_ON_R_REG 0x25 /* RW */ -+#define KHADAS_MCU_RGB_ON_G_REG 0x26 /* RW */ - #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */ -+#define KHADAS_MCU_RGB_ON_B_REG 0x27 /* RW */ - #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */ -+#define KHADAS_MCU_RGB_OFF_R_REG 0x28 /* RW */ - #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */ -+#define KHADAS_MCU_RGB_OFF_G_REG 0x29 /* RW */ - #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */ -+#define KHADAS_MCU_RGB_OFF_B_REG 0x2a /* RW */ - #define KHADAS_MCU_SHUTDOWN_NORMAL_REG 0x2c /* RW */ - #define KHADAS_MCU_MAC_SWITCH_REG 0x2d /* RW */ -+#define KHADAS_MCU_REST_CONF_REG 0x2e /* RW */ - #define KHADAS_MCU_MCU_SLEEP_MODE_REG 0x2e /* RW */ -+#define KHADAS_MCU_BOOT_EN_IR_REG_V2 0x2f /* RW */ - #define KHADAS_MCU_IR_CODE1_0_REG 0x2f /* RW */ - #define KHADAS_MCU_IR_CODE1_1_REG 0x30 /* RW */ -+#define KHADAS_MCU_IR1_CUST1_REG 0x30 /* RW */ - #define KHADAS_MCU_IR_CODE1_2_REG 0x31 /* RW */ -+#define KHADAS_MCU_IR1_CUST2_REG 0x31 /* RW */ - #define KHADAS_MCU_IR_CODE1_3_REG 0x32 /* RW */ -+#define KHADAS_MCU_IR1_ORDER1_REG 0x32 /* RW */ - #define KHADAS_MCU_USB_PCIE_SWITCH_REG 0x33 /* RW */ -+#define KHADAS_MCU_IR1_ORDER2_REG 0x33 /* RW */ -+#define KHADAS_MCU_IR2_CUST1_REG 0x34 /* RW */ - #define KHADAS_MCU_IR_CODE2_0_REG 0x34 /* RW */ - #define KHADAS_MCU_IR_CODE2_1_REG 0x35 /* RW */ -+#define KHADAS_MCU_IR2_CUST2_REG 0x35 /* RW */ - #define KHADAS_MCU_IR_CODE2_2_REG 0x36 /* RW */ -+#define KHADAS_MCU_IR2_ORDER1_REG 0x36 /* RW */ - #define KHADAS_MCU_IR_CODE2_3_REG 0x37 /* RW */ -+#define KHADAS_MCU_IR2_ORDER2_REG 0x36 /* RW */ - #define KHADAS_MCU_PASSWD_USER_0_REG 0x40 /* RW */ - #define KHADAS_MCU_PASSWD_USER_1_REG 0x41 /* RW */ - #define KHADAS_MCU_PASSWD_USER_2_REG 0x42 /* RW */ -@@ -69,6 +88,10 @@ - #define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG 0x86 /* RO */ - #define KHADAS_MCU_WOL_INIT_START_REG 0x87 /* WO */ - #define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG 0x88 /* WO */ -+#define KHADAS_MCU_LED_ON_RAM_REG 0x89 /* WO */ -+#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2 0x8A /* WO */ -+#define KHADAS_MCU_WDT_EN_REG 0x8B /* WO */ -+#define KHADAS_MCU_SYS_RST_REG 0x91 /* WO */ - - enum { - KHADAS_BOARD_VIM1 = 0x1, -@@ -76,6 +99,7 @@ enum { - KHADAS_BOARD_VIM3, - KHADAS_BOARD_EDGE = 0x11, - KHADAS_BOARD_EDGE_V, -+ KHADAS_BOARD_EDGE2, - }; - - /** --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:09:58 +0300 -Subject: mfd: khadas-mcu: drop unused code - ---- - drivers/mfd/khadas-mcu.c | 11 ---------- - 1 file changed, 11 deletions(-) - -diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c -index 111111111111..222222222222 100644 ---- a/drivers/mfd/khadas-mcu.c -+++ b/drivers/mfd/khadas-mcu.c -@@ -84,10 +84,6 @@ static struct mfd_cell khadas_mcu_fan_cells[] = { - { .name = "khadas-mcu-fan-ctrl", }, - }; - --static struct mfd_cell khadas_mcu_cells[] = { -- { .name = "khadas-mcu-user-mem", }, --}; -- - static int khadas_mcu_probe(struct i2c_client *client) - { - struct device *dev = &client->dev; -@@ -109,13 +105,6 @@ static int khadas_mcu_probe(struct i2c_client *client) - return ret; - } - -- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, -- khadas_mcu_cells, -- ARRAY_SIZE(khadas_mcu_cells), -- NULL, 0, NULL); -- if (ret) -- return ret; -- - if (of_property_present(dev->of_node, "#cooling-cells")) - return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, - khadas_mcu_fan_cells, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:13:10 +0300 -Subject: thermal: khadas_mcu_fan: add support for Khadas Edge 2 - ---- - drivers/thermal/khadas_mcu_fan.c | 77 +++++++++- - 1 file changed, 73 insertions(+), 4 deletions(-) - -diff --git a/drivers/thermal/khadas_mcu_fan.c b/drivers/thermal/khadas_mcu_fan.c -index 111111111111..222222222222 100644 ---- a/drivers/thermal/khadas_mcu_fan.c -+++ b/drivers/thermal/khadas_mcu_fan.c -@@ -15,10 +15,16 @@ - #include - - #define MAX_LEVEL 3 -+#define MAX_SPEED 0x64 - - struct khadas_mcu_fan_ctx { - struct khadas_mcu *mcu; - unsigned int level; -+ -+ unsigned int fan_max_level; -+ unsigned int fan_register; -+ unsigned int *fan_cooling_levels; -+ - struct thermal_cooling_device *cdev; - }; - -@@ -26,9 +32,21 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, - unsigned int level) - { - int ret; -+ unsigned int write_level = level; -+ -+ if (level > ctx->fan_max_level) -+ return -EINVAL; -+ -+ if (ctx->fan_cooling_levels != NULL) { -+ write_level = ctx->fan_cooling_levels[level]; -+ -+ if (write_level > MAX_SPEED) -+ return -EINVAL; -+ } -+ -+ ret = regmap_write(ctx->mcu->regmap, ctx->fan_register, -+ write_level); - -- ret = regmap_write(ctx->mcu->regmap, KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, -- level); - if (ret) - return ret; - -@@ -40,7 +58,9 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, - static int khadas_mcu_fan_get_max_state(struct thermal_cooling_device *cdev, - unsigned long *state) - { -- *state = MAX_LEVEL; -+ struct khadas_mcu_fan_ctx *ctx = cdev->devdata; -+ -+ *state = ctx->fan_max_level; - - return 0; - } -@@ -61,7 +81,7 @@ khadas_mcu_fan_set_cur_state(struct thermal_cooling_device *cdev, - { - struct khadas_mcu_fan_ctx *ctx = cdev->devdata; - -- if (state > MAX_LEVEL) -+ if (state > ctx->fan_max_level) - return -EINVAL; - - if (state == ctx->level) -@@ -76,6 +96,48 @@ static const struct thermal_cooling_device_ops khadas_mcu_fan_cooling_ops = { - .set_cur_state = khadas_mcu_fan_set_cur_state, - }; - -+// Khadas Edge 2 sets fan level by passing fan speed(0-100). So we need different logic here like pwm-fan cooling-levels. -+// This is optional and just necessary for Edge 2. -+static int khadas_mcu_fan_get_cooling_data_edge2(struct khadas_mcu_fan_ctx *ctx, struct device *dev) { -+ struct device_node *np = ctx->mcu->dev->of_node; -+ int num, i, ret; -+ -+ if (!of_property_present(np, "cooling-levels")) -+ return 0; -+ -+ ret = of_property_count_u32_elems(np, "cooling-levels"); -+ if (ret <= 0) { -+ dev_err(dev, "Wrong data!\n"); -+ return ret ? : -EINVAL; -+ } -+ -+ num = ret; -+ ctx->fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32), -+ GFP_KERNEL); -+ if (!ctx->fan_cooling_levels) -+ return -ENOMEM; -+ -+ ret = of_property_read_u32_array(np, "cooling-levels", -+ ctx->fan_cooling_levels, num); -+ if (ret) { -+ dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); -+ return ret; -+ } -+ -+ for (i = 0; i < num; i++) { -+ if (ctx->fan_cooling_levels[i] > MAX_SPEED) { -+ dev_err(dev, "PWM fan state[%d]:%d > %d\n", i, -+ ctx->fan_cooling_levels[i], MAX_SPEED); -+ return -EINVAL; -+ } -+ } -+ -+ ctx->fan_max_level = num - 1; -+ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2; -+ -+ return 0; -+} -+ - static int khadas_mcu_fan_probe(struct platform_device *pdev) - { - struct khadas_mcu *mcu = dev_get_drvdata(pdev->dev.parent); -@@ -90,6 +152,13 @@ static int khadas_mcu_fan_probe(struct platform_device *pdev) - ctx->mcu = mcu; - platform_set_drvdata(pdev, ctx); - -+ ctx->fan_max_level = MAX_LEVEL; -+ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG; -+ -+ ret = khadas_mcu_fan_get_cooling_data_edge2(ctx, dev); -+ if (ret) -+ return ret; -+ - cdev = devm_thermal_of_cooling_device_register(dev->parent, - dev->parent->of_node, "khadas-mcu-fan", ctx, - &khadas_mcu_fan_cooling_ops); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:14:58 +0300 -Subject: dt-bindings: mfd: khadas-mcu: add cooling-levels property - ---- - Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -+++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml -@@ -11,7 +11,7 @@ maintainers: - - description: | - Khadas embeds a microcontroller on their VIM and Edge boards adding some -- system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory -+ system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory - storage, IR/Key resume control, system power LED control and more. - - properties: -@@ -22,6 +22,11 @@ properties: - "#cooling-cells": # Only needed for boards having FAN control feature - const: 2 - -+ cooling-levels: -+ description: Max speed of PWM fan. This property is necessary for Khadas Edge 2. -+ items: -+ maximum: 100 -+ - reg: - maxItems: 1 - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 6 Mar 2024 00:17:58 +0300 -Subject: arm64: dts: rockchip: Add MCU to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -306,6 +306,13 @@ hym8563: rtc@51 { - clock-output-names = "hym8563"; - wakeup-source; - }; -+ -+ khadas_mcu: system-controller@18 { -+ compatible = "khadas,mcu"; -+ reg = <0x18>; -+ cooling-levels = <0 50 72 100>; -+ #cooling-cells = <2>; -+ }; - }; - - &pinctrl { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 25 Mar 2024 22:41:26 +0300 -Subject: arm64: dts: rockchip: Add automatic fan control to Khadas Edge 2 - ---- - arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 56 ++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts -@@ -315,6 +315,62 @@ khadas_mcu: system-controller@18 { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <45000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <55000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan2: package-fan2 { -+ temperature = <60000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ -+ package_fan3: package-fan3 { -+ temperature = <70000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&package_fan0>; -+ cooling-device = <&khadas_mcu 0 1>; -+ contribution = <1024>; -+ }; -+ -+ map1 { -+ trip = <&package_fan1>; -+ cooling-device = <&khadas_mcu 1 2>; -+ contribution = <1024>; -+ }; -+ -+ map2 { -+ trip = <&package_fan2>; -+ cooling-device = <&khadas_mcu 2 3>; -+ contribution = <1024>; -+ }; -+ -+ map3 { -+ trip = <&package_fan3>; -+ cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>; -+ contribution = <1024>; -+ }; -+ }; -+}; -+ - &pinctrl { - vdd_sd { - vdd_sd_en: vdd-sd-en { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch deleted file mode 100644 index 6b842c006ea3..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ricardo Pardini -Date: Thu, 6 Jun 2024 23:00:05 +0200 -Subject: arm64: dts: rockchip: Add NanoPC T6 SPI Flash - -Signed-off-by: Ricardo Pardini ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -576,6 +576,20 @@ &sdmmc { - status = "okay"; - }; - -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim1_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <50000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch deleted file mode 100644 index 7055c6111ffc..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 31f55e29d6b6a33d800b543c1e92825fe33fb4db Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Wed, 7 Aug 2024 10:19:47 -0400 -Subject: [PATCH] arm64: dts: rockchip: Split pcie30x1m1 pinctrl - -The PCIe 3.0 PHYs need an external clock and will assert CLKREQ# to -get it. Some RK3588 boards such as the Turning RK1, Mixtile 3588E, -and the ArmSoM AIM7 only provide this clock when CLKREQ# is asserted. - -Signed-off-by: Joshua Riek ---- - .../arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -index 30db12c4fc82..e8f5e252a5de 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi -@@ -1785,12 +1785,22 @@ pcie30x4m0_pins: pcie30x4m0-pins { - }; - - /omit-if-no-ref/ -- pcie30x4m1_pins: pcie30x4m1-pins { -+ pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { - rockchip,pins = - /* pcie30x4_clkreqn_m1 */ -- <4 RK_PB4 4 &pcfg_pull_none>, -+ <4 RK_PB4 4 &pcfg_pull_down>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4_perstn_m1: pcie30x4-perstn-m1 { -+ rockchip,pins = - /* pcie30x4_perstn_m1 */ -- <4 RK_PB6 4 &pcfg_pull_none>, -+ <4 RK_PB6 4 &pcfg_pull_none>; -+ }; -+ -+ /omit-if-no-ref/ -+ pcie30x4_waken_m1: pcie30x4-waken-m1 { -+ rockchip,pins = - /* pcie30x4_waken_m1 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; --- -2.25.1 - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch deleted file mode 100644 index d2eab1f53632..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch +++ /dev/null @@ -1,30 +0,0 @@ -From b8322ec8dc89b0020bb4d552e79f99fac04fa3aa Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Wed, 7 Aug 2024 10:30:50 -0400 -Subject: [PATCH 06/15] arm64: dts: rockchip: Add PCIe 3.0 pinctrl to Turing - RK1 - -The Turning RK1 needs to assert CLKREQ# to provide an external -clock to the PCIe 3.0 PHYs. - -Signed-off-by: Joshua Riek ---- - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index dbaa94ca69f4..5d0053ee3d45 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -223,7 +223,7 @@ &pcie30phy { - &pcie3x4 { - linux,pci-domain = <0>; - pinctrl-names = "default"; -- pinctrl-0 = <&pcie3_reset>; -+ pinctrl-0 = <&pcie3_reset>, <&pcie30x4_clkreqn_m1>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; --- -2.25.1 - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch deleted file mode 100644 index 2020f98c10ae..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 82e3d9c7dc918bb4278bdce7e9a0c4579781818d Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Wed, 7 Aug 2024 10:34:35 -0400 -Subject: [PATCH 07/15] arm64: dts: rockchip: Enable GPU node on Turing RK1 - -Enables the Mali G610 GPU. - -Signed-off-by: Joshua Riek ---- - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index 5d0053ee3d45..e157c5acfcb5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -101,6 +101,11 @@ &cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; --- -2.25.1 - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch deleted file mode 100644 index 08b3d5f722fc..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch +++ /dev/null @@ -1,63 +0,0 @@ -From ec302349e26ce4bc00b2d438348d302bd468cb11 Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Thu, 22 Aug 2024 22:32:47 -0400 -Subject: [PATCH 12/15] arm64: dts: rockchip: Enable automatic fan control on - the Turing RK1 - ---- - .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 32 ++++++++++++++++++- - 1 file changed, 31 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index f56a6a10c2ad..18b687a30e94 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -24,7 +24,7 @@ aliases { - - fan: pwm-fan { - compatible = "pwm-fan"; -- cooling-levels = <0 25 95 145 195 255>; -+ cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0m2_pins &fan_int>; -@@ -234,6 +234,36 @@ rgmii_phy: ethernet-phy@1 { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l1 { - linux,pci-domain = <1>; - pinctrl-names = "default"; --- -2.25.1 - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch deleted file mode 100644 index 86636123103b..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 8fa9e89184e736af4b81fdb67d5efa35f5d1996e Mon Sep 17 00:00:00 2001 -From: Joshua Riek -Date: Wed, 7 Aug 2024 14:12:21 -0400 -Subject: [PATCH 08/15] arm64: dts: rockchip: Add missing hym8563 - clock-frequency for Turing RK1 - -Signed-off-by: Joshua Riek ---- - arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -index e157c5acfcb5..dc36a7e048da 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi -@@ -191,6 +191,7 @@ hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; -+ clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; --- -2.25.1 - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-bananapi-m7.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-bananapi-m7.dts deleted file mode 100644 index 8489240ab8bd..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-bananapi-m7.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3588-armsom-sige7.dts" - -/ { - model = "Banana Pi M7"; - compatible = "bananapi,m7", "rockchip,rk3588"; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-hinlink-h88k.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-hinlink-h88k.dts deleted file mode 100644 index ed962d5a9ee1..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-hinlink-h88k.dts +++ /dev/null @@ -1,858 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "HINLINK H88K"; - compatible = "hinlink,h88k", "rockchip,rk3588"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - analog-sound { - compatible = "simple-audio-card"; - label = "rockchip,es8388-codec"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "Analog"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - simple-audio-card,bitclock-master = <&daicpu>; - simple-audio-card,frame-master = <&daicpu>; - - simple-audio-card,widgets = - "Microphone", "Onboard Microphone", - "Microphone", "Microphone Jack", - "Speaker", "Speaker", - "Headphone", "Headphones"; - - simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - - /* single ended signal to LINPUT1 */ - "LINPUT1", "Microphone Jack", - "RINPUT1", "Microphone Jack", - /* differential signal */ - "LINPUT2", "Onboard Microphone", - "RINPUT2", "Onboard Microphone"; - - daicpu: simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - system-clock-frequency = <12288000>; - }; - - daicodec: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_net_en>, <&led_sata_en>, - <&led_user_en>, <&led_work_en>; - - net { - label = "blue:net"; - gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; - }; - - sata { - label = "amber:sata"; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - }; - - user { - label = "green:user"; - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - - work { - label = "red:work"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-name = "vcc12v_dcin"; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb_hub: vcc5v0-usb-hub { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8388: audio-codec@11 { - compatible = "everest,es8388"; - reg = <0x11>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - AVDD-supply = <&vcc_3v3_s3>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - DVDD-supply = <&vcc_1v8_s3>; - HPVDD-supply = <&vcc_3v3_s3>; - PVDD-supply = <&vcc_1v8_s3>; - #sound-dai-cells = <0>; - - port { - es8388_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8388_p0_0>; - }; - }; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_net_en: led_net_en { - rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_sata_en: led_sata_en { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_user_en: led_user_en { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_work_en: led_work_en { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs200-1_8v; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - /* connected to USB hub, which is powered by vcc5v0_sys */ - phy-supply = <&vcc5v0_sys>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-mixtile-blade3.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-mixtile-blade3.dts deleted file mode 100644 index ef0adae48ebf..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-mixtile-blade3.dts +++ /dev/null @@ -1,712 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Mixtile Blade 3"; - compatible = "mixtile,blade3", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - pcie20_avdd0v85: pcie20-avdd0v85-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - enable-active-high; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4m0_xfer>; - status = "okay"; -}; - -/* exposed on the 30-pin connector; shows up as i2c-3 */ -&i2c5 { - pinctrl-0 = <&i2c5m3_xfer>; - status = "okay"; -}; - -&i2s2_2ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_mclk - &i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - status = "okay"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - status = "okay"; -}; - -&pinctrl { - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm8 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm8m2_pins>; - status = "okay"; -}; - -&pwm14 { - pinctrl-0 = <&pwm14m2_pins>; - status = "okay"; -}; - -&pwm15 { - pinctrl-0 = <&pwm15m3_pins>; - status = "disabled"; -}; - -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; - num-cs = <1>; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - // hs400 causes immediate trouble, hs200 works at around 150mb/s - // mmc-hs400-1_8v; - // mmc-hs400-enhanced-strobe; - mmc-hs200-1_8v; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-nanopc-cm3588-nas.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-nanopc-cm3588-nas.dts deleted file mode 100644 index f95c8a708aba..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-nanopc-cm3588-nas.dts +++ /dev/null @@ -1,1436 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd. - * Copyright (c) 2023 Thomas McKahan - * Author: ColorfulRhino - * - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "FriendlyElec CM3588 NAS"; - compatible = "friendlyarm,cm3588", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - // nvme0 = &nvme0; - // nvme1 = &nvme1; - // nvme2 = &nvme2; - // nvme3 = &nvme3; - // ethernet0 = &r8125_u10; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-vol-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - }; - - analog-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&headphone_detect>; - - simple-audio-card,name = "realtek,rt5616-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - - simple-audio-card,routing = - "Headphones", "HPOL", - "Headphones", "HPOR", - "MIC1", "Microphone Jack", - "Microphone Jack", "micbias1"; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Microphone Jack"; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <0 50 100 150 200 255>; - pwms = <&pwm1 0 50000 0>; - status = "disabled"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key1_pin>; - - button-user { - debounce-interval = <50>; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; - label = "User Button"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_sys: led-0 { - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - label = "system-led"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_sys_pin>; - }; - - led_usr: led-1 { - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - label = "user-led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_usr_pin>; - }; - }; - - vcc_12v_dcin: vcc-12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* vcc_5v0_sys powers peripherals */ - vcc_5v0_sys: vcc-5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_12v_dcin>; - }; - - vcc_5v0_host_20: vcc-5v0-host-20 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_5v0_host20_en>; - regulator-name = "vcc_5v0_host_20"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v0_sys>; - }; - - vcc_5v0_host_30: vcc-5v0-host-30 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_5v0_host30_en>; - regulator-name = "vcc_5v0_host_30"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v0_sys>; - }; - - vcc_3v3_host_32: vcc-3v3-host-32-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_3v3_host32_en>; - regulator-name = "vcc_3v3_host_32"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; - - vbus_5v0_typec: vbus-5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec_5v_pwr_en>; - regulator-name = "vbus_5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v0_sys>; - }; - - /* vcc_4v0_sys powers the RK806, RK860's */ - vcc_4v0_sys: vcc-4v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <4000000>; - vin-supply = <&vcc_12v_dcin>; - }; - - vcc_3v3_pcie20: vcc-3v3-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_pcie30: vcc-3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie30"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vcc_3v3_sd_s0"; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-1v1-nldo-s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc_4v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -/* Properties "clock" and "clock-names" introduced by Collabora https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/8fff68cb7cfe1e698445896252e34f79fad41720 */ -&display_subsystem { - clocks = <&hdptxphy_hdmi0>; - clock-names = "hdmi0_phy_pll"; -}; - -/* Signal labels [SIGNAL_LABEL] are from the official CM3588 NAS schematic revision 2309 */ -/* Some GPIOs like USB, sdmmc or SPI-NOR are not listed here */ -&gpio0 { - gpio-line-names = - /* GPIO0 A0-A7 */ - "", "", "", "", - "", "", "", "", - /* GPIO0 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO0 C0-C7 */ - "", "", "", "", - "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "", - /* GPIO0 D0-D7 */ - "", "", "", "", - "IR sensor [PWM3_IR_M0]", "User Button", "", ""; -}; - -&gpio1 { - gpio-line-names = - /* GPIO1 A0-A7 */ - "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "", - "", "", "", "Pin 15", - /* GPIO1 B0-B7 */ - "Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]", - "Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]", - /* GPIO1 C0-C7 */ - "", "", "", "", - "Headphone detect [HP_DET_L]", "", "", "", - /* GPIO1 D0-D7 */ - "", "", "", "Fan [PWM1_M1]", - "", "", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]"; -}; - -&gpio2 { - gpio-line-names = - /* GPIO2 A0-A7 */ - "", "", "", "", - "", "", "", "", - /* GPIO2 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO2 C0-C7 */ - "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "", - "", "", "", "", - /* GPIO2 D0-D7 */ - "", "", "", "", - "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - /* GPIO3 A0-A7 */ - "Pin 35 [SPI4_MISO_M1/PW M10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]", - "Pin 37 [SPI4_CS1_M1]", "", "DSI-Pin 12 [LCD_RST]", "Buzzer [PW M8_M0]", - /* GPIO3 B0-B7 */ - "Pin 33 [PW M9_M0]", "DSI-Pin 10 [PW M2_M1/LCD_BL]", "Pin 07", "Pin 16", - "Pin 18", "Pin 29 [UART3_TX_M1/PW M12_M0]", "Pin 31 [UART3_RX_M1/PW M13_M0]", "Pin 12", - /* GPIO3 C0-C7 */ - "DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]", - "", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]", - /* GPIO3 D0-D7 */ - "DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - /* GPIO4 A0-A7 */ - "", "", "", "", - "", "", "", "", - /* GPIO4 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO4 C0-C7 */ - "", "", "", "", - "", "", "", "", - /* GPIO4 D0-D7 */ - "", "", "", "", - "", "", "", ""; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - sram-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&hdmi0 { - // avdd-0v9-supply = - // avdd-1v8-supply = - /* Dmesg error/warning: - * [ +0.000055] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-0v9-supply from device tree - * [ +0.000011] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-0v9-supply property in node /hdmi@fde80000 failed - * [ +0.000014] dwhdmi-rockchip fde80000.hdmi: supply avdd-0v9 not found, using dummy regulator - * [ +0.000080] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-1v8-supply from device tree - * [ +0.000010] dwhdmi-rockchip fde80000.hdmi: Looking up avdd-1v8-supply property in node /hdmi@fde80000 failed - * [ +0.000010] dwhdmi-rockchip fde80000.hdmi: supply avdd-1v8 not found, using dummy regulator - * [ +0.001009] dwhdmi-rockchip fde80000.hdmi: registered ddc I2C bus driver - */ - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -// /* 4k HDMI capture controller (see rk3588.dtsi) */ -// &hdmirx_cma { -// status = "okay"; -// }; - -// &hdmirx_ctrler { -// status = "okay"; -// hdmirx-5v-detection-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -// pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; -// pinctrl-names = "default"; -// memory-region = <&hdmirx_cma>; -// }; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - status = "disabled"; -}; - -/* Connected to MIPI-DSI0 */ -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m0_xfer>; - status = "disabled"; -}; - -&i2c6 { - clock-frequency = <200000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m0_xfer>; - status = "okay"; - - fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-0 = <&usbc0_int>; - pinctrl-names = "default"; - vbus-supply = <&vbus_5v0_typec>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - source-pdos = ; - sink-pdos = ; - try-power-role = "sink"; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -/* Connected to MIPI-CSI1 */ -&i2c7 { - clock-frequency = <200000>; - status = "okay"; - - rt5616: audio-codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - rt5616_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&i2c8 { - pinctrl-0 = <&i2c8m2_xfer>; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&rt5616_p0_0>; - }; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -/* Temperature sensor near the center of the SoC */ -&package_thermal { - polling-delay = <1000>; - - trips { - package_hot: package_hot { - hysteresis = <2000>; - temperature = <65000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - trip = <&package_hot>; - }; - }; -}; - -&pcie2x1l0 { // @fe170000 - /* 2. M.2 slot, CON14: pcie30phy port0 lane1 */ - max-link-speed = <3>; - num-lanes = <1>; - phys = <&pcie30phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie30>; - status = "okay"; - - // pcie@0,0 { - // reg = <0x00200000 0 0 0 0>; - // #address-cells = <3>; - // #size-cells = <2>; - - // nvme1: pcie@20,0 { - // reg = <0x000000 0 0 0 0>; - // }; - // }; -}; - -&pcie2x1l1 { // @fe180000 - /* 4. M.2 slot, CON16: pcie30phy port1 lane1 */ - max-link-speed = <3>; - num-lanes = <1>; - phys = <&pcie30phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie30>; - status = "okay"; - - // pcie@0,0 { - // reg = <0x00300000 0 0 0 0>; - // #address-cells = <3>; - // #size-cells = <2>; - - // nvme3: pcie@30,0 { - // reg = <0x000000 0 0 0 0>; - // }; - // }; -}; - -&pcie2x1l2 { // @fe190000 - /* r8125 ethernet */ - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; - - // pcie@0,0 { - // reg = <0x00400000 0 0 0 0>; - // #address-cells = <3>; - // #size-cells = <2>; - - // r8125_u10: pcie@40,0 { - // reg = <0x000000 0 0 0 0>; - // local-mac-address = [ 00 00 00 00 00 00 ]; - // }; - // }; -}; - -&pcie30phy { - /* - * Michal Tomek describes: - * The PHY offers the following mapping options: - * - * port 0 lane 0 - always mapped to controller 0 (4L) - * port 0 lane 1 - to controller 0 or 2 (1L0) - * port 1 lane 0 - to controller 0 or 1 (2L) - * port 1 lane 1 - to controller 0, 1 or 3 (1L1) - * - * The data-lanes DT property maps these as follows: - * - * 0 = no controller (unsupported by the HW) - * 1 = 4L - * 2 = 2L - * 3 = 1L0 - * 4 = 1L1 - * - * <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports; - */ - data-lanes = <1 3 2 4>; - status = "okay"; -}; - -&pcie3x4 { // @fe150000 - /* 1. M.2 slot, CON13: pcie30phy port0 lane0 */ - max-link-speed = <3>; - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3x4_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie30>; - status = "okay"; - - // pcie@0,0 { - // reg = <0x00000000 0 0 0 0>; - // #address-cells = <3>; - // #size-cells = <2>; - - // nvme0: pcie@0,0 { - // reg = <0x000000 0 0 0 0>; - // }; - // }; -}; - -&pcie3x2 { // @fe160000 - /* 3. M.2 slot, CON15: pcie30phy port1 lane0 */ - max-link-speed = <3>; - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3x2_rst>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie30>; - status = "okay"; - - // pcie@0,0 { - // reg = <0x00100000 0 0 0 0>; - // #address-cells = <3>; - // #size-cells = <2>; - - // nvme2: pcie@10,0 { - // reg = <0x000000 0 0 0 0>; - // }; - // }; -}; - -&pinctrl { - audio { - headphone_detect: headphone-detect { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gpio-key { - key1_pin: key1-pin { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - led_sys_pin: led-sys-pin { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_usr_pin: led-usr-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3x2_rst: pcie3x2-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3x4_rst: pcie3x4-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc_5v0_host20_en: vcc-5v0-host20-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_5v0_host30_en: vcc-5v0-host30-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_3v3_host32_en: vcc-3v3-host32-en { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec_5v_pwr_en: typec-5v-pwr-en { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -/* Connected to 5V Fan */ -&pwm1 { - pinctrl-0 = <&pwm1m1_pins>; - status = "okay"; -}; - -/* Connected to MIPI-DSI0 */ -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&pwm5 { - pinctrl-0 = <&pwm5m1_pins>; - status = "okay"; -}; - -/* GPIO Connector */ -&pwm8 { - pinctrl-0 = <&pwm8m0_pins>; - status = "okay"; -}; - -/* GPIO Connector */ -&pwm9 { - pinctrl-0 = <&pwm9m0_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -/* eMMC */ -&sdhci { - bus-width = <8>; - full-pwr-cycle-in-suspend; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -/* microSD card */ -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -/* GPIO Connector */ -&spi0 { - num-cs = <1>; - pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; - status = "disabled"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - rk806_single: pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - spi-max-frequency = <1000000>; - - system-power-controller; - - vcc1-supply = <&vcc_4v0_sys>; - vcc2-supply = <&vcc_4v0_sys>; - vcc3-supply = <&vcc_4v0_sys>; - vcc4-supply = <&vcc_4v0_sys>; - vcc5-supply = <&vcc_4v0_sys>; - vcc6-supply = <&vcc_4v0_sys>; - vcc7-supply = <&vcc_4v0_sys>; - vcc8-supply = <&vcc_4v0_sys>; - vcc9-supply = <&vcc_4v0_sys>; - vcc10-supply = <&vcc_4v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc_4v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc_4v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&spi4 { - num-cs = <1>; - pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart0 { - pinctrl-0 = <&uart0m0_xfer>; - status = "disabled"; -}; - -/* Debug UART */ -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart3 { - pinctrl-0 = <&uart3m1_xfer>; - status = "disabled"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart4 { - pinctrl-0 = <&uart4m2_xfer>; - status = "disabled"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart6 { - pinctrl-0 = <&uart6m1_xfer>; - status = "okay"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart7 { - pinctrl-0 = <&uart7m2_xfer>; - status = "disabled"; -}; - -/* GPIO Connector, connected to 40-pin GPIO header */ -&uart8 { - pinctrl-0 = <&uart8m1_xfer>; - status = "disabled"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; /* @TODO Note: This flag is not (yet?) present in Linux 6.9 "Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml" */ - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc_5v0_host_30>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc_5v0_host_20>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc_3v3_host_32>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -/* Upper USB 3.0 port */ -&usb_host1_xhci { - dr_mode = "host"; - snps,xhci-trb-ent-quirk; - status = "okay"; -}; - -/* Lower USB 3.0 port */ -&usb_host2_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; - -&wdt { - status = "okay"; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6c.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6c.dts deleted file mode 100644 index 5c8b850efe75..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6c.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3588s-nanopi-r6s.dts" - -/ { - model = "FriendlyElec NanoPi R6C"; - compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588s"; -}; - -&lan2_led { - /delete-property/ linux,default-trigger; - label = "user_led"; -}; - -&pcie2x1l2 { - /delete-node/ pcie@0,0; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6s.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6s.dts deleted file mode 100644 index b39a3fc976b5..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6s.dts +++ /dev/null @@ -1,865 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "FriendlyElec NanoPi R6S"; - compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588s"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - label = "sys_led"; - gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - wan_led: led-1 { - label = "wan_led"; - gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "r8169-3-3100:00:link"; - pinctrl-names = "default"; - pinctrl-0 = <&wan_led_pin>; - }; - - lan1_led: led-2 { - label = "lan1_led"; - gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "r8169-4-4100:00:link"; - pinctrl-names = "default"; - pinctrl-0 = <&lan1_led_pin>; - }; - - lan2_led: led-3 { - label = "lan2_led"; - gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "stmmac-0:01:link"; - pinctrl-names = "default"; - pinctrl-0 = <&lan2_led_pin>; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-maskrom { - label = "Maskrom"; - linux,code = ; - press-threshold-microvolt = <1800>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key1_pin>; - - button-user { - label = "User"; - linux,code = ; - gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; - debounce-interval = <50>; - wakeup-source; - }; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_otg0"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_host_20: vcc5v0-host-20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host_20"; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host20_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - clock-frequency = <200000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m0_xfer>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - eeprom@53 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x53>; - #address-cells = <2>; - #size-cells = <0>; - pagesize = <16>; - size = <256>; - - eui_48: eui-48@fa { - reg = <0xfa 0x06>; - }; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; - - pcie@0,0 { - reg = <0x00300000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - r8125_u25: pcie@30,0 { - reg = <0x000000 0 0 0 0>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; - - pcie@0,0 { - reg = <0x00400000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - r8125_u40: pcie@40,0 { - reg = <0x000000 0 0 0 0>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; -}; - -&pinctrl { - gpio-key { - key1_pin: key1-pin { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - sys_led_pin: sys-led-pin { - rockchip,pins = - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan1_led_pin: lan1-led-pin { - rockchip,pins = - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan2_led_pin: lan2-led-pin { - rockchip,pins = - <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vcc5v0_host20_en: vcc5v0-host20-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - /* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */ - mmc-hs200-1_8v; - max-frequency = <200000000>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fudr_moden0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_usb_otg0>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5.dts deleted file mode 100644 index ea8c082a58c9..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5.dts +++ /dev/null @@ -1,814 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Xunlong Orange Pi 5"; - compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <1800>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_gpio>; - - led-1 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - }; - }; - - hdmi0-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con_in: endpoint { - remote-endpoint = <&hdmi0_out_con>; - }; - }; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-name = "vbus_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - enable-active-low; - gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie20"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus_typec>; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "source"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_hs: endpoint { - remote-endpoint = <&usb_host0_xhci_drd_sw>; - }; - }; - - port@1 { - reg = <1>; - usbc0_ss: endpoint { - remote-endpoint = <&usbdp_phy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - usbc0_sbu: endpoint { - remote-endpoint = <&usbdp_phy0_typec_sbu>; - }; - }; - }; - }; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pinctrl { - gpio-func { - leds_gpio: leds-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim0_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usbdp_phy0 { - mode-switch; - orientation-switch; - sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usbdp_phy0_typec_ss: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_ss>; - }; - - usbdp_phy0_typec_sbu: endpoint@1 { - reg = <1>; - remote-endpoint = <&usbc0_sbu>; - }; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - usb-role-switch; - status = "okay"; - - port { - usb_host0_xhci_drd_sw: endpoint { - remote-endpoint = <&usbc0_hs>; - }; - }; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdmi0_out { - hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi0_con_in>; - }; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5b.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5b.dts deleted file mode 100644 index 3194df7a5fc8..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5b.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3588s-orangepi-5.dts" - -/ { - model = "Xunlong Orange Pi 5B"; - compatible = "xunlong,orangepi-5b", "rockchip,rk3588s"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - /* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */ - mmc-hs200-1_8v; - max-frequency = <200000000>; - status = "okay"; -}; - -&sfc { - status = "disabled"; -}; - -&pcie2x1l2 { - pcie@0,0 { - reg = <0x400000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - device_type = "pci"; - bus-range = <0x40 0x4f>; - - wifi: wifi@0,0 { - compatible = "pci14e4,449d"; - reg = <0x410000 0 0 0 0>; - clocks = <&hym8563>; - clock-names = "32k"; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-rock-5c.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-rock-5c.dts deleted file mode 100644 index 0666da126cf0..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-rock-5c.dts +++ /dev/null @@ -1,825 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Radxa ROCK 5 Model C"; - compatible = "radxa,rock-5c", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - analog-sound { - compatible = "audio-graph-card"; - label = "rk3588-es8316"; - - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - - user-led { - gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - }; - - io-led { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; - fan-supply = <&vcc_5v0>; - pwms = <&pwm3 0 50000 0>; - #cooling-cells = <2>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_5v0: vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_5v0_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - eeprom: eeprom@50 { - compatible = "belling,bl24c16a", "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m2_xfer>; -}; - -&i2c7 { - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x3a>; - rx_delay = <0x3e>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l2 { - status = "okay"; - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; -}; - -&pinctrl { - power { - vcc_5v0_en: vcc-5v0-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifibt { - wifibt_en: wifibit-en { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - host_wake_wl: host-wake-wl { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_output_high>; - }; - - wl_wake_host: wl-wake-host { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - host_wake_bt: host-wake-bt { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_wake_host: bt-wake-host { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; - vbus-supply = <&vcc5v0_otg>; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; - rockchip,dp-lane-mux = <2 3>; -}; - -&usb_host0_ehci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wifibt_en &host_wake_wl &wl_wake_host &host_wake_bt &bt_wake_host>; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-youyeetoo-r1.dts b/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-youyeetoo-r1.dts deleted file mode 100644 index 1446aa021cb9..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-youyeetoo-r1.dts +++ /dev/null @@ -1,861 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Youyeetoo R1"; - compatible = "youyeetoo,r1", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - label = "sys_led"; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - }; - - /* POWER REGULATOR 12V DC-IN */ - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* POWER REGULATOR 5V SYS */ - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* POWER REGULATOR CPU */ - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* POWER REGULATOR 3V (SD) */ - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - vin-supply = <&vcc_3v3_s3>; - }; - - /* POWER REGULATOR 3.3V (PCIE)*/ - - vcc_3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - /* POWER REGULATOR 5V (USB2 & USB3) */ - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host_20: vcc5v0-host-20 { // U13 (USB 2.0) - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host20_en>; - regulator-name = "vcc5v0_host_20"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_host_30: vcc5v0-host-30 { // U12 (USB 3.0) - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host30_en>; - regulator-name = "vcc5v0_host_30"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - - /* BLUETOOTH */ - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - status = "okay"; - }; - - /* WIFI */ - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "rtl8852be"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - /* FAN */ - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <100 160 190 200 215 235 255>; - pwms = <&pwm6 0 40000 0>; - fan-supply = <&vcc12v_dcin>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - tx_delay = <0x43>; - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - /* RTC */ - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - status = "okay"; - }; -}; - -&package_thermal { - polling-delay = <1000>; - - trips { - package_fan0: package-fan0 { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - package_fan1: package-fan1 { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&package_fan0>; - cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; - }; - map2 { - trip = <&package_fan1>; - cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; - }; - }; -}; - - -&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,init-delay-ms = <100>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - status = "okay"; -}; - - -&pinctrl { - /* TODO: SOUND */ - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - /* GPIO LEDS */ - gpio-leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; - /* RTC */ - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* SD */ - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* USB */ - usb { - vcc5v0_host20_en: vcc5v0-host20-en { // USB 2.0 - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - vcc5v0_host30_en: vcc5v0-host30-en { // USB 3.0 - rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - /* WIRELESS */ - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - /* HS400 doesn't work properly -> https://github.com/torvalds/linux/commit/cee572756aa2cb46e959e9797ad4b730b78a050b */ - mmc-hs200-1_8v; - max-frequency = <200000000>; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fudr_moden0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&pwm6{ - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -/* USB */ - -&u2phy0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_host_30>; - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host_20>; - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; - dr_mode = "host"; - extcon = <&u2phy0>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; - cec-enable = "true"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi0_in_vp0>; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/Makefile b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/Makefile deleted file mode 100644 index 6f79b3b11709..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ - rockchip-rk3588-fanctrl.dtbo \ - rockchip-rk3588-sata1.dtbo \ - rockchip-rk3588-sata2.dtbo \ - rockchip-rk3588-hdmirx.dtbo \ - rockchip-rk3588-i2c8-m2.dtbo \ - rockchip-rk3588-pwm0-m0.dtbo \ - rockchip-rk3588-pwm0-m1.dtbo \ - rockchip-rk3588-pwm0-m2.dtbo \ - rockchip-rk3588-pwm1-m0.dtbo \ - rockchip-rk3588-pwm1-m1.dtbo \ - rockchip-rk3588-pwm1-m2.dtbo \ - rockchip-rk3588-pwm2-m1.dtbo \ - rockchip-rk3588-pwm3-m0.dtbo \ - rockchip-rk3588-pwm3-m1.dtbo \ - rockchip-rk3588-pwm3-m2.dtbo \ - rockchip-rk3588-pwm3-m3.dtbo \ - rockchip-rk3588-pwm5-m2.dtbo \ - rockchip-rk3588-pwm6-m0.dtbo \ - rockchip-rk3588-pwm6-m2.dtbo \ - rockchip-rk3588-pwm7-m0.dtbo \ - rockchip-rk3588-pwm7-m3.dtbo \ - rockchip-rk3588-pwm8-m0.dtbo \ - rockchip-rk3588-pwm10-m0.dtbo \ - rockchip-rk3588-pwm11-m0.dtbo \ - rockchip-rk3588-pwm11-m1.dtbo \ - rockchip-rk3588-pwm12-m0.dtbo \ - rockchip-rk3588-pwm13-m0.dtbo \ - rockchip-rk3588-pwm13-m2.dtbo \ - rockchip-rk3588-pwm14-m0.dtbo \ - rockchip-rk3588-pwm14-m1.dtbo \ - rockchip-rk3588-pwm14-m2.dtbo \ - rockchip-rk3588-pwm15-m0.dtbo \ - rockchip-rk3588-pwm15-m1.dtbo \ - rockchip-rk3588-pwm15-m2.dtbo \ - rockchip-rk3588-pwm15-m3.dtbo \ - rockchip-rk3588-rkvenc-overlay.dtso \ - rockchip-rk3588-uart1-m1.dtbo \ - rockchip-rk3588-uart3-m1.dtbo \ - rockchip-rk3588-uart4-m2.dtbo \ - rockchip-rk3588-uart6-m1.dtbo \ - rockchip-rk3588-uart7-m2.dtbo \ - rockchip-rk3588-uart8-m1.dtbo - -dtb-y += $(dtbo-y) - -clean-files := *.dtbo diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-fanctrl.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-fanctrl.dtso deleted file mode 100644 index 28110b08694f..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-fanctrl.dtso +++ /dev/null @@ -1,11 +0,0 @@ -/dts-v1/; -/plugin/; -/ { - fragment@0 { - target = <&fan>; - __overlay__ { - cooling-levels = <146 146 146 146 146 146 149 149 151>; - }; - }; -}; - diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso deleted file mode 100644 index b61eff3047be..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-hdmirx.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&hdmi_receiver_cma>; - - __overlay__ { - status = "okay"; - }; - }; - - fragment@1 { - target = <&hdmi_receiver>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-i2c8-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-i2c8-m2.dtso deleted file mode 100644 index 24993c880984..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-i2c8-m2.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&i2c8>; - - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m0.dtso deleted file mode 100644 index 211ddc646f45..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m1.dtso deleted file mode 100644 index 353162ec79ee..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm0m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m2.dtso deleted file mode 100644 index f7c03e93e3b8..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm0>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm0m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m0.dtso deleted file mode 100644 index bb19090ad249..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm1m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m1.dtso deleted file mode 100644 index e935135023ee..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm1m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m2.dtso deleted file mode 100644 index 155d0bd4138b..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm1m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm10-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm10-m0.dtso deleted file mode 100644 index 281071bbbc0f..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm10-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm10>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm10m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m0.dtso deleted file mode 100644 index 1bebcd619d95..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm11>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm11m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m1.dtso deleted file mode 100644 index b85076feabad..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM11-M1"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO4_B4"; - description = "Enable PWM11-M1.\nOn Radxa ROCK 5A this is pin 15."; - }; - - fragment@0 { - target = <&pwm11>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm11m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm12-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm12-m0.dtso deleted file mode 100644 index 6dc0c7ed0b58..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm12-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm12>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm12m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m0.dtso deleted file mode 100644 index 38ec499ce586..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm13>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm13m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m2.dtso deleted file mode 100644 index 0d9b225fff0d..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm13>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm13m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m0.dtso deleted file mode 100644 index 330406d939ad..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m0.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m1.dtso deleted file mode 100644 index 82fec22ebbd1..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m1.dtso +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m2.dtso deleted file mode 100644 index 7a26f2dc891a..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm14>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm14m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m0.dtso deleted file mode 100644 index 076bef9f64d9..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM15-M0"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_C3"; - description = "Enable PWM15-M0.\nOn Radxa ROCK 5B this is pin 7."; - }; - - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m1.dtso deleted file mode 100644 index 7d3de70b05cf..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m2.dtso deleted file mode 100644 index c1b2aea10acb..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m3.dtso deleted file mode 100644 index 79e421a4958f..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m3.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM15-M3"; - compatible = "radxa,rock-5a", "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO1_D7"; - description = "Enable PWM15-M3.\nOn Radxa ROCK 5A this is pin 3.\nOn Radxa ROCK 5B this is pin 29."; - }; - - fragment@0 { - target = <&pwm15>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm15m3_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm2-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm2-m1.dtso deleted file mode 100644 index 653583fdb7e4..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm2-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM2-M1"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_B1"; - description = "Enable PWM2-M1.\nOn Radxa ROCK 5B this is pin 36."; - }; - - fragment@0 { - target = <&pwm2>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm2m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m0.dtso deleted file mode 100644 index a6a9181ab596..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m0.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m1.dtso deleted file mode 100644 index 23ff1ad68993..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m1.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM3-M1"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_B2"; - description = "Enable PWM3-M1.\nOn Radxa ROCK 5B this is pin 38."; - }; - - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m1_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m2.dtso deleted file mode 100644 index b70d2097ea32..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m3.dtso deleted file mode 100644 index db544f2502fd..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m3.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pwm3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm3m3_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm5-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm5-m2.dtso deleted file mode 100644 index ce26d29f33cf..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm5-m2.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM5-M2"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C4"; - description = "Enable PWM5-M2.\nOn Radxa ROCK 5B this is pin 18."; - }; - - fragment@0 { - target = <&pwm5>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm5m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m0.dtso deleted file mode 100644 index e4d0ce3f5864..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM6-M0"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO0_C7"; - description = "Enable PWM6-M0.\nOn Radxa ROCK 5A this is pin 27."; - }; - - fragment@0 { - target = <&pwm6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm6m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m2.dtso deleted file mode 100644 index 5e66d1d33ef4..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m2.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM6-M2"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C5"; - description = "Enable PWM6-M2.\nOn Radxa ROCK 5B this is pin 28."; - }; - - fragment@0 { - target = <&pwm6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm6m2_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m0.dtso deleted file mode 100644 index 6516762486dd..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM7-M0"; - compatible = "radxa,rock-5a"; - category = "misc"; - exclusive = "GPIO0_D0"; - description = "Enable PWM7-M0.\nOn Radxa ROCK 5A this is pin 28."; - }; - - fragment@0 { - target = <&pwm7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm7m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m3.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m3.dtso deleted file mode 100644 index 9a7d919f6cd6..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m3.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM7-M3"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO4_C6"; - description = "Enable PWM7-M3.\nOn Radxa ROCK 5B this is pin 27."; - }; - - fragment@0 { - target = <&pwm7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm7m3_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm8-m0.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm8-m0.dtso deleted file mode 100644 index e461cffb597a..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm8-m0.dtso +++ /dev/null @@ -1,21 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - metadata { - title = "Enable PWM8-M0"; - compatible = "radxa,rock-5b"; - category = "misc"; - exclusive = "GPIO3_A7"; - description = "Enable PWM8-M0.\nOn Radxa ROCK 5B this is pin 33."; - }; - - fragment@0 { - target = <&pwm8>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&pwm8m0_pins>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata1.dtso deleted file mode 100644 index 2759ab9cf7af..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata1.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pcie2x1l0>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sata1>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata2.dtso deleted file mode 100644 index c68e11dc1604..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata2.dtso +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&pcie2x1l1>; - - __overlay__ { - status = "disabled"; - }; - }; - - fragment@1 { - target = <&sata2>; - - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart1-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart1-m1.dtso deleted file mode 100644 index 909f6058fd69..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart1-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart1>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart1m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart3-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart3-m1.dtso deleted file mode 100644 index cc5522c9cd3a..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart3-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart3>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart3m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart4-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart4-m2.dtso deleted file mode 100644 index a371018ef585..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart4-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart4>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart4m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart6-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart6-m1.dtso deleted file mode 100644 index 46cea59e9fee..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart6-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart6>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart6m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart7-m2.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart7-m2.dtso deleted file mode 100644 index 6a56f61d13de..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart7-m2.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart7>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart7m2_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart8-m1.dtso b/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart8-m1.dtso deleted file mode 100644 index e1b3b3a38b27..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart8-m1.dtso +++ /dev/null @@ -1,13 +0,0 @@ -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target = <&uart8>; - - __overlay__ { - status = "okay"; - pinctrl-0 = <&uart8m1_xfer>; - }; - }; -}; diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch b/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch deleted file mode 100644 index 3a5c5919abc6..000000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.10/rk3588-rock-5b_dts_add_rfkill-bt.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: John Doe -Date: Tue, 20 Aug 2024 22:47:51 +0000 -Subject: rk3588-rock-5b.dts: add rfkill-bt node to Radxa Rock5B board DT - -Signed-off-by: John Doe ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -66,6 +66,13 @@ rfkill { - shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - -+ rfkill-bt { -+ compatible = "rfkill-gpio"; -+ label = "rfkill-m2-bt"; -+ radio-type = "bluetooth"; -+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch b/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch index 7c37c6b79ceb..facdd2bff61d 100644 --- a/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch +++ b/patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch @@ -3965,3 +3965,153 @@ index 111111111111..222222222222 100644 -- Armbian +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ben Hoff +Date: Sun, 15 Sep 2024 14:52:17 -0400 +Subject: fix spurious triggering of irq 5v while plugout code is running + +--- + drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 12 ++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c ++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +@@ -745,10 +745,17 @@ static void hdmirx_interrupts_setup(struct snps_hdmirx_dev *hdmirx_dev, bool en) + static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) + { + struct arm_smccc_res res; ++ int irq; + + hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0); + hdmirx_interrupts_setup(hdmirx_dev, false); + hdmirx_hpd_ctrl(hdmirx_dev, false); ++ irq = gpiod_to_irq(hdmirx_dev->detect_5v_gpio); ++ ++ if (irq >= 0) { ++ disable_irq(irq); ++ } ++ + hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0); + hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4, + LINE_FLAG_INT_EN | +@@ -766,6 +773,11 @@ static void hdmirx_plugout(struct snps_hdmirx_dev *hdmirx_dev) + cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat); + flush_work(&hdmirx_dev->work_wdt_config); + arm_smccc_smc(SIP_WDT_CFG, WDT_STOP, 0, 0, 0, 0, 0, 0, &res); ++ ++ hdmirx_hpd_ctrl(hdmirx_dev, true); ++ if (irq >= 0) { ++ enable_irq(irq); ++ } + } + + static int hdmirx_set_edid(struct file *file, void *fh, struct v4l2_edid *edid) +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ben Hoff +Date: Sun, 15 Sep 2024 14:53:25 -0400 +Subject: remove timing handling from plug in function + +--- + drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c ++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +@@ -2202,13 +2202,6 @@ static void hdmirx_plugin(struct snps_hdmirx_dev *hdmirx_dev) + hdmirx_hpd_ctrl(hdmirx_dev, true); + hdmirx_phy_config(hdmirx_dev); + ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev); +- if (ret) { +- hdmirx_plugout(hdmirx_dev); +- queue_delayed_work(system_unbound_wq, +- &hdmirx_dev->delayed_work_hotplug, +- msecs_to_jiffies(200)); +- return; +- } + hdmirx_dma_config(hdmirx_dev); + hdmirx_interrupts_setup(hdmirx_dev, true); + } +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ben Hoff +Date: Mon, 23 Sep 2024 09:43:38 -0400 +Subject: expose itc type to v4l2 in synopsys hdmir rx + +--- + drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c | 16 +++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c ++++ b/drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c +@@ -151,6 +151,7 @@ struct snps_hdmirx_dev { + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *detect_tx_5v_ctrl; + struct v4l2_ctrl *rgb_range; ++ struct v4l2_ctrl *content_type; + struct v4l2_dv_timings timings; + struct gpio_desc *detect_5v_gpio; + struct work_struct work_wdt_config; +@@ -512,6 +513,11 @@ static void hdmirx_get_avi_infoframe(struct snps_hdmirx_dev *hdmirx_dev) + } + + v4l2_ctrl_s_ctrl(hdmirx_dev->rgb_range, frame.avi.quantization_range); ++ if (frame.avi.itc) { ++ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, frame.avi.content_type); ++ } else { ++ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); ++ } + } + + /* +@@ -1192,6 +1198,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) + break; + + if (!tx_5v_power_present(hdmirx_dev)) { ++ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); + //v4l2_err(v4l2_dev, "%s: HDMI pull out, return\n", __func__); + return -1; + } +@@ -1204,6 +1211,7 @@ static int hdmirx_wait_lock_and_get_timing(struct snps_hdmirx_dev *hdmirx_dev) + __func__, hdmirx_dev->tmds_clk_ratio); + v4l2_err(v4l2_dev, "%s: mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n", + __func__, mu_status, scdc_status, dma_st10); ++ v4l2_ctrl_s_ctrl(hdmirx_dev->content_type, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); + return -1; + } + +@@ -2668,7 +2676,7 @@ static int hdmirx_probe(struct platform_device *pdev) + strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name)); + + hdl = &hdmirx_dev->hdl; +- v4l2_ctrl_handler_init(hdl, 1); ++ v4l2_ctrl_handler_init(hdl, 3); + + hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, + V4L2_CID_DV_RX_POWER_PRESENT, +@@ -2681,6 +2689,12 @@ static int hdmirx_probe(struct platform_device *pdev) + + hdmirx_dev->rgb_range->flags |= V4L2_CTRL_FLAG_READ_ONLY; + ++ hdmirx_dev->content_type = v4l2_ctrl_new_std_menu(hdl, NULL, ++ V4L2_CID_DV_RX_IT_CONTENT_TYPE, ++ V4L2_DV_IT_CONTENT_TYPE_NO_ITC, ++ 0, ++ V4L2_DV_IT_CONTENT_TYPE_NO_ITC); ++ + if (hdl->error) { + dev_err(dev, "v4l2 ctrl handler init failed\n"); + ret = hdl->error; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch index 8bb768d1994b..a7b27edc61ac 100644 --- a/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch @@ -1,50 +1,7 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 1/9] dt-bindings: arm: rockchip: Add NanoPC-T6 LTS -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:52 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-1-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add devicetree binding for the NanoPC-T6 LTS board. - -Signed-off-by: Marcin Juszkiewicz -Acked-by: Krzysztof Kozlowski ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 1ef09fbfdfaf..f45c7d055a6a 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -243,9 +243,11 @@ properties: - - friendlyarm,nanopi-r6s - - const: rockchip,rk3588s - -- - description: FriendlyElec NanoPC T6 -+ - description: FriendlyElec NanoPC T6 series boards - items: -- - const: friendlyarm,nanopc-t6 -+ - enum: -+ - friendlyarm,nanopc-t6 -+ - friendlyarm,nanopc-t6-lts - - const: rockchip,rk3588 - - - description: FriendlyElec CM3588-based boards --- -2.46.0 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 2/9] arm64: dts: rockchip: prepare NanoPC-T6 for LTS - board +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:53 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-2-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: prepare NanoPC-T6 for LTS board FriendlyELEC introduced a second version of NanoPC-T6 SBC. @@ -53,12 +10,12 @@ patches will add LTS version. Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 932 +-------------------- - ...{rk3588-nanopc-t6.dts => rk3588-nanopc-t6.dtsi} | 0 - 2 files changed, 2 insertions(+), 930 deletions(-) + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 932 +-------- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 945 ++++++++++ + 2 files changed, 947 insertions(+), 930 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -index ad8e36a339dc..3f8fbec65098 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts @@ -2,944 +2,16 @@ @@ -1008,32 +965,975 @@ index ad8e36a339dc..3f8fbec65098 100644 -&usb_host1_ohci { - status = "okay"; }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -similarity index 100% -copy from arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -copy to arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +@@ -0,0 +1,945 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2023 Thomas McKahan ++ * ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPC-T6"; ++ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ sys_led: led-0 { ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "system-led"; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sys_led_pin>; ++ }; ++ ++ usr_led: led-1 { ++ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; ++ label = "user-led"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usr_led_pin>; ++ }; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det>; ++ ++ simple-audio-card,name = "realtek,rt5616-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; ++ simple-audio-card,hp-pin-name = "Headphones"; ++ ++ simple-audio-card,widgets = ++ "Headphone", "Headphones", ++ "Microphone", "Microphone Jack"; ++ simple-audio-card,routing = ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "MIC1", "Microphone Jack", ++ "Microphone Jack", "micbias1"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0_8ch>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rt5616>; ++ }; ++ }; ++ ++ vcc12v_dcin: vcc12v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ /* vcc5v0_sys powers peripherals */ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ /* vcc4v0_sys powers the RK806, RK860's */ ++ vcc4v0_sys: vcc4v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-1v1-nldo-s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc4v0_sys>; ++ }; ++ ++ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pcie20"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vbus5v0_typec: vbus5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_m2_1_pwren>; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_m2_0_pwren>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-low; ++ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; ++ regulator-boot-on; ++ regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-name = "vcc3v3_sd_s0"; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vdd_4g_3v3: vdd-4g-3v3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pin_4g_lte_pwren>; ++ regulator-name = "vdd_4g_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&gpio0 { ++ gpio-line-names = /* GPIO0 A0-A7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO0 B0-B7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO0 C0-C7 */ ++ "", "", "", "", ++ "HEADER_10", "HEADER_08", "HEADER_32", "", ++ /* GPIO0 D0-D7 */ ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = /* GPIO1 A0-A7 */ ++ "HEADER_27", "HEADER_28", "", "", ++ "", "", "", "HEADER_15", ++ /* GPIO1 B0-B7 */ ++ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", ++ "HEADER_24", "HEADER_22", "", "", ++ /* GPIO1 C0-C7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO1 D0-D7 */ ++ "", "", "", "", ++ "", "", "HEADER_05", "HEADER_03"; ++}; ++ ++&gpio2 { ++ gpio-line-names = /* GPIO2 A0-A7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO2 B0-B7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO2 C0-C7 */ ++ "", "CSI1_11", "CSI1_12", "", ++ "", "", "", "", ++ /* GPIO2 D0-D7 */ ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = /* GPIO3 A0-A7 */ ++ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", ++ "HEADER_37", "", "DSI0_12", "", ++ /* GPIO3 B0-B7 */ ++ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", ++ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", ++ /* GPIO3 C0-C7 */ ++ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", ++ "", "", "", "", ++ /* GPIO3 D0-D7 */ ++ "", "", "", "", ++ "", "DSI1_10", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = /* GPIO4 A0-A7 */ ++ "DSI1_08", "DSI1_14", "", "DSI1_12", ++ "", "", "", "", ++ /* GPIO4 B0-B7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO4 C0-C7 */ ++ "", "", "", "", ++ "CSI0_11", "CSI0_12", "", "", ++ /* GPIO4 D0-D7 */ ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ rockchip,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ clock-frequency = <200000>; ++ status = "okay"; ++ ++ fusb302: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-0 = <&usbc0_int>; ++ pinctrl-names = "default"; ++ vbus-supply = <&vbus5v0_typec>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USB-C"; ++ power-role = "dual"; ++ try-power-role = "sink"; ++ source-pdos = ; ++ sink-pdos = ; ++ op-sink-microwatt = <1000000>; ++ }; ++ }; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ clock-frequency = <200000>; ++ status = "okay"; ++ ++ rt5616: codec@1b { ++ compatible = "realtek,rt5616"; ++ reg = <0x1b>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ ++ port { ++ rt5616_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++ ++ /* connected with MIPI-CSI1 */ ++}; ++ ++&i2c8 { ++ pinctrl-0 = <&i2c8m2_xfer>; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&rt5616_p0_0>; ++ }; ++ }; ++}; ++ ++&pcie2x1l0 { ++ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ status = "okay"; ++}; ++ ++&pcie2x1l1 { ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_1_rst>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usr_led_pin: usr-led-pin { ++ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ headphone { ++ hp_det: hp-det { ++ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_1_rst: pcie2-1-rst { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_m2_0_pwren: pcie-m20-pwren { ++ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_m2_1_pwren: pcie-m21-pwren { ++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ pin_4g_lte_pwren: 4g-lte-pwren { ++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usbc0_int: usbc0-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ pinctrl-0 = <&pwm1m1_pins>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <200000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ no-mmc; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sd_s0>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc4v0_sys>; ++ vcc2-supply = <&vcc4v0_sys>; ++ vcc3-supply = <&vcc4v0_sys>; ++ vcc4-supply = <&vcc4v0_sys>; ++ vcc5-supply = <&vcc4v0_sys>; ++ vcc6-supply = <&vcc4v0_sys>; ++ vcc7-supply = <&vcc4v0_sys>; ++ vcc8-supply = <&vcc4v0_sys>; ++ vcc9-supply = <&vcc4v0_sys>; ++ vcc10-supply = <&vcc4v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc4v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc4v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-init-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vdd_4g_3v3>; ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 3/9] arm64: dts: rockchip: move NanoPC-T6 parts to DTS +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:54 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-3-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: move NanoPC-T6 parts to DTS MiniPCIe slot is present only in first version of NanoPC-T6 (2301). Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 24 ++++++++++++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 --------------- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 24 ++++++++++ + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 ------- 2 files changed, 24 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -index 3f8fbec65098..6a16aec7107a 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts @@ -14,4 +14,28 @@ / { @@ -1066,7 +1966,7 @@ index 3f8fbec65098..6a16aec7107a 100644 + status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index ad8e36a339dc..d199f51a220c 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -170,18 +170,6 @@ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { @@ -1108,16 +2008,12 @@ index ad8e36a339dc..d199f51a220c 100644 }; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 4/9] arm64: dts: rockchip: add NanoPC-T6 LTS +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:55 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-4-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: add NanoPC-T6 LTS In the LTS (2310) version the miniPCIe slot got removed and USB 2.0 setup has changed. There are two external accessible ports and two ports @@ -1132,25 +2028,12 @@ The top USB 2.0 connector comes directly from the SoC. Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3588-nanopc-t6-lts.dts | 61 ++++++++++++++++++++++ - 2 files changed, 62 insertions(+) + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts | 61 ++++++++++ + 1 file changed, 61 insertions(+) -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index fda1b980eb4b..0f982c741243 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts new file mode 100644 -index 000000000000..fc465957a00b +index 000000000000..111111111111 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts @@ -0,0 +1,61 @@ @@ -1216,16 +2099,12 @@ index 000000000000..fc465957a00b + status = "okay"; +}; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 5/9] arm64: dts: rockchip: add SPI flash on NanoPC-T6 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:56 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-5-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: add SPI flash on NanoPC-T6 FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board. It is populated with 32MB one on LTS version. @@ -1233,11 +2112,11 @@ It is populated with 32MB one on LTS version. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Jonas Karlman --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index d199f51a220c..77580c671b36 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -560,6 +560,21 @@ &sdmmc { @@ -1263,27 +2142,23 @@ index d199f51a220c..77580c671b36 100644 status = "okay"; assigned-clocks = <&cru CLK_SPI2>; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 6/9] arm64: dts: rockchip: add IR-receiver to NanoPC-T6 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:57 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-6-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: add IR-receiver to NanoPC-T6 FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line which ends as GPIO0_D4. Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++++++- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 77580c671b36..9ad2f1cf8103 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -25,6 +25,13 @@ chosen { @@ -1323,16 +2198,12 @@ index 77580c671b36..9ad2f1cf8103 100644 pcie2_0_rst: pcie2-0-rst { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 7/9] arm64: dts: rockchip: enable GPU on NanoPC-T6 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:58 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-7-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: enable GPU on NanoPC-T6 Enable the Mali GPU on FriendlyELEC NanoPC-T6 @@ -1342,7 +2213,7 @@ Signed-off-by: Marcin Juszkiewicz 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 9ad2f1cf8103..d172a8547a55 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -298,6 +298,11 @@ &gpio4 { @@ -1358,16 +2229,12 @@ index 9ad2f1cf8103..d172a8547a55 100644 pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 8/9] arm64: dts: rockchip: enable USB-C on NanoPC-T6 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:26:59 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-8-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: enable USB-C on NanoPC-T6 Enable the USB-C port on FriendlyELEC NanoPC-T6. @@ -1375,11 +2242,11 @@ Works one way so far but still better than before. Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 76 ++++++++++++++++++++-- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 76 +++++++++- 1 file changed, 72 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index d172a8547a55..1e9a3be23ea9 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -137,6 +137,8 @@ vbus5v0_typec: vbus5v0-typec-regulator { @@ -1495,26 +2362,22 @@ index d172a8547a55..1e9a3be23ea9 100644 status = "okay"; }; -- -2.46.0 +Armbian -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 9/9] arm64: dts: rockchip: add Mask Rom key on NanoPC-T6 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Thu, 29 Aug 2024 14:27:00 +0200 -Message-Id: <20240829-friendlyelec-nanopc-t6-lts-v6-9-edff247e8c02@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit +Subject: arm64: dts: rockchip: add Mask Rom key on NanoPC-T6 Mask Rom key is connected to SARADC and can be read from OS. Signed-off-by: Marcin Juszkiewicz --- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 1e9a3be23ea9..b5f5ce3459a4 100644 +index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -8,6 +8,7 @@ @@ -1547,5 +2410,5 @@ index 1e9a3be23ea9..b5f5ce3459a4 100644 stdout-path = "serial2:1500000n8"; }; -- -2.46.0 +Armbian diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile index 32a3333bdd12..4aebf957207a 100644 --- a/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile +++ b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/Makefile @@ -40,7 +40,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ rockchip-rk3588-uart4-m2.dtbo \ rockchip-rk3588-uart6-m1.dtbo \ rockchip-rk3588-uart7-m2.dtbo \ - rockchip-rk3588-uart8-m1.dtbo + rockchip-rk3588-uart8-m1.dtbo \ + rockchip-rk3588-rkvenc-overlay.dtso dtb-y += $(dtbo-y) diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-rkvenc-overlay.dtso b/patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-rkvenc-overlay.dtso similarity index 100% rename from patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-rkvenc-overlay.dtso rename to patch/kernel/archive/rockchip-rk3588-6.11/overlay/rockchip-rk3588-rkvenc-overlay.dtso