From b8a489095b594bd3fdff65487cd2b5c92050a907 Mon Sep 17 00:00:00 2001 From: Zhewen Yu Date: Wed, 7 Aug 2024 17:32:40 +0100 Subject: [PATCH] Routing refactor v2 (#1643) --- docs/AIERouting.md | 16 +- .../aie/Dialect/AIE/Transforms/AIEPasses.h | 11 - .../aie/Dialect/AIE/Transforms/AIEPasses.td | 5 +- .../Dialect/AIE/Transforms/AIEPathFinder.h | 446 +- .../AIE/Transforms/AIECreatePathFindFlows.cpp | 300 +- lib/Dialect/AIE/Transforms/AIEPathFinder.cpp | 567 +-- lib/Targets/AIEFlowsToJSON.cpp | 43 +- .../switchbox/path/pathfinder_input.mlir | 98 +- test/create-flows/broadcast.mlir | 59 +- ..._existing_flow.mlir => existing_flow.mlir} | 6 +- ...onnections.mlir => fixed_connections.mlir} | 0 test/create-flows/flow_test_1.mlir | 90 +- test/create-flows/flow_test_2.mlir | 89 +- test/create-flows/flow_test_3.mlir | 93 +- test/create-flows/keep_flow_op.mlir | 31 - test/create-flows/many_flows.mlir | 57 +- test/create-flows/many_flows2.mlir | 57 +- test/create-flows/maxiter_err_test.mlir | 3 + test/create-flows/memtile.mlir | 39 +- .../memtile_routing_constraints.mlir | 20 +- test/create-flows/mmult.mlir | 45 +- test/create-flows/more_flows_shim.mlir | 2 +- test/create-flows/over_flows.mlir | 59 +- test/create-flows/routed_herd_3x1.mlir | 71 +- test/create-flows/routed_herd_3x2.mlir | 52 +- test/create-flows/simple.mlir | 28 +- test/create-flows/simple2.mlir | 13 +- test/create-flows/simple_flows.mlir | 17 +- test/create-flows/simple_flows2.mlir | 17 +- test/create-flows/unit_broadcast.mlir | 249 -- test/create-flows/unit_flow_test_1.mlir | 452 -- test/create-flows/unit_flow_test_2.mlir | 275 -- test/create-flows/unit_flow_test_3.mlir | 490 --- test/create-flows/unit_many_flows.mlir | 338 -- test/create-flows/unit_many_flows2.mlir | 316 -- test/create-flows/unit_maxiter_err_test.mlir | 81 - test/create-flows/unit_memtile.mlir | 90 - .../unit_memtile_routing_constraints.mlir | 45 - test/create-flows/unit_mmult.mlir | 653 --- test/create-flows/unit_more_flows_shim.mlir | 113 - test/create-flows/unit_over_flows.mlir | 210 - test/create-flows/unit_routed_herd_3x1.mlir | 823 ---- test/create-flows/unit_routed_herd_3x2.mlir | 1018 ----- test/create-flows/unit_simple.mlir | 53 - test/create-flows/unit_simple2.mlir | 42 - test/create-flows/unit_simple_flows.mlir | 40 - test/create-flows/unit_simple_flows2.mlir | 52 - test/create-flows/unit_simple_flows_shim.mlir | 74 - test/create-flows/unit_vecmul_4x4.mlir | 3864 ----------------- test/create-flows/vecmul_4x4.mlir | 359 +- .../aie2_memtile_connection.mlir | 46 +- .../keep_packet_flow_op.mlir | 45 - .../packet_routing_keep_pkt_header.mlir | 51 +- .../create-packet-flows/test_congestion0.mlir | 97 +- .../create-packet-flows/test_congestion1.mlir | 76 +- utils/router_performance.py | 104 + 56 files changed, 1490 insertions(+), 10900 deletions(-) mode change 100644 => 100755 lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp rename test/create-flows/{unit_existing_flow.mlir => existing_flow.mlir} (93%) rename test/create-flows/{unit_fixed_connections.mlir => fixed_connections.mlir} (100%) delete mode 100644 test/create-flows/keep_flow_op.mlir delete mode 100644 test/create-flows/unit_broadcast.mlir delete mode 100644 test/create-flows/unit_flow_test_1.mlir delete mode 100644 test/create-flows/unit_flow_test_2.mlir delete mode 100644 test/create-flows/unit_flow_test_3.mlir delete mode 100644 test/create-flows/unit_many_flows.mlir delete mode 100644 test/create-flows/unit_many_flows2.mlir delete mode 100644 test/create-flows/unit_maxiter_err_test.mlir delete mode 100644 test/create-flows/unit_memtile.mlir delete mode 100644 test/create-flows/unit_memtile_routing_constraints.mlir delete mode 100644 test/create-flows/unit_mmult.mlir delete mode 100644 test/create-flows/unit_more_flows_shim.mlir delete mode 100644 test/create-flows/unit_over_flows.mlir delete mode 100644 test/create-flows/unit_routed_herd_3x1.mlir delete mode 100644 test/create-flows/unit_routed_herd_3x2.mlir delete mode 100644 test/create-flows/unit_simple.mlir delete mode 100644 test/create-flows/unit_simple2.mlir delete mode 100644 test/create-flows/unit_simple_flows.mlir delete mode 100644 test/create-flows/unit_simple_flows2.mlir delete mode 100644 test/create-flows/unit_simple_flows_shim.mlir delete mode 100644 test/create-flows/unit_vecmul_4x4.mlir delete mode 100644 test/create-packet-flows/keep_packet_flow_op.mlir create mode 100644 utils/router_performance.py diff --git a/docs/AIERouting.md b/docs/AIERouting.md index 9a374273c1..36ee28393e 100644 --- a/docs/AIERouting.md +++ b/docs/AIERouting.md @@ -104,7 +104,7 @@ Here is an example of how users can route the circuit-switched `test/create-flow ``` cd ${path-to-mlir-aie}/tools/aie-routing-command-line -aie-opt --aie-create-pathfinder-flows='keep-flow-op=true' ../../test/create-flows/broadcast.mlir \ +aie-opt --aie-create-pathfinder-flows --aie-find-flows ../../test/create-flows/broadcast.mlir \ | aie-translate --aie-flows-to-json > example.json python3 visualize.py -j example.json ``` @@ -172,7 +172,19 @@ Similarly, to visualize a packet-switched example, ``` cd ${path-to-mlir-aie}/tools/aie-routing-command-line -aie-opt --aie-create-pathfinder-flows='keep-flow-op=true' ../../test/create-packet-flows/test_create_packet_flows6.mlir \ +aie-opt --aie-create-pathfinder-flows --aie-find-flows ../../test/create-packet-flows/test_create_packet_flows6.mlir \ | aie-translate --aie-flows-to-json > example.json python3 visualize.py -j example.json ``` + + +## Benckmarking Routing + +A python script is provided to measure the wall-clock time and the length of paths routed. Simply run + +``` +python3 utils/router_performance.py test/create-flows/ +python3 utils/router_performance.py test/create-packet-flows/ +``` + +and the generated `routing_performance_results.csv` files can be found under the corresponding folders. \ No newline at end of file diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.h b/include/aie/Dialect/AIE/Transforms/AIEPasses.h index 22642a3b9a..b0f2b30c20 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.h +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.h @@ -72,21 +72,10 @@ struct AIEPathfinderPass : AIERoutePathfinderFlowsBase { typedef std::pair PhysPort; - typedef struct { - SwitchboxOp sw; - Port sourcePort; - Port destPort; - } SwConnection; - bool findPathToDest(SwitchSettings settings, TileID currTile, WireBundle currDestBundle, int currDestChannel, TileID finalTile, WireBundle finalDestBundle, int finalDestChannel); - - SwitchboxOp getSwitchbox(DeviceOp &d, int col, int row); - - mlir::Operation *getOrCreateTile(mlir::OpBuilder &builder, int col, int row); - SwitchboxOp getOrCreateSwitchbox(mlir::OpBuilder &builder, TileOp tile); }; } // namespace xilinx::AIE diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index 1244dfc0e2..bc8e91cbde 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -145,10 +145,7 @@ def AIERoutePathfinderFlows : Pass<"aie-create-pathfinder-flows", "DeviceOp"> { Option<"clRouteCircuit", "route-circuit", "bool", /*default=*/"true", "Flag to enable aie.flow lowering.">, Option<"clRoutePacket", "route-packet", "bool", /*default=*/"true", - "Flag to enable aie.packetflow lowering.">, - Option<"clKeepFlowOp", "keep-flow-op", "bool", /*default=*/"false", - "Flag to not erase aie.flow/packetflow after its lowering," - "used for routing visualization.">, + "Flag to enable aie.packetflow lowering.">, ]; } diff --git a/include/aie/Dialect/AIE/Transforms/AIEPathFinder.h b/include/aie/Dialect/AIE/Transforms/AIEPathFinder.h index f53ddc6eea..119d8a0dd4 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPathFinder.h +++ b/include/aie/Dialect/AIE/Transforms/AIEPathFinder.h @@ -21,285 +21,129 @@ namespace xilinx::AIE { -enum class Connectivity { INVALID = -1, AVAILABLE = 0, OCCUPIED = 1 }; - -using SwitchboxNode = struct SwitchboxNode { - - SwitchboxNode(int col, int row, int id, int maxCol, int maxRow, - const AIETargetModel &targetModel) - : col{col}, row{row}, id{id} { - - std::vector bundles = { - WireBundle::Core, WireBundle::DMA, WireBundle::FIFO, - WireBundle::South, WireBundle::West, WireBundle::North, - WireBundle::East, WireBundle::PLIO, WireBundle::NOC, - WireBundle::Trace, WireBundle::Ctrl}; - - for (WireBundle bundle : bundles) { - int maxCapacity = - targetModel.getNumSourceSwitchboxConnections(col, row, bundle); - if (targetModel.isShimNOCorPLTile(col, row) && maxCapacity == 0) { - // wordaround for shimMux, todo: integrate shimMux into routable grid - maxCapacity = - targetModel.getNumSourceShimMuxConnections(col, row, bundle); - } - - for (int channel = 0; channel < maxCapacity; channel++) { - Port inPort = {bundle, channel}; - inPortToId[inPort] = inPortId; - inPortId++; - } - - maxCapacity = - targetModel.getNumDestSwitchboxConnections(col, row, bundle); - if (targetModel.isShimNOCorPLTile(col, row) && maxCapacity == 0) { - // wordaround for shimMux, todo: integrate shimMux into routable grid - maxCapacity = - targetModel.getNumDestShimMuxConnections(col, row, bundle); - } - for (int channel = 0; channel < maxCapacity; channel++) { - Port outPort = {bundle, channel}; - outPortToId[outPort] = outPortId; - outPortId++; - } - } - - connectionMatrix.resize(inPortId, std::vector( - outPortId, Connectivity::AVAILABLE)); - - // illegal connection - for (const auto &[inPort, inId] : inPortToId) { - for (const auto &[outPort, outId] : outPortToId) { - if (!targetModel.isLegalTileConnection(col, row, inPort.bundle, - inPort.channel, outPort.bundle, - outPort.channel)) - connectionMatrix[inId][outId] = Connectivity::INVALID; - - if (targetModel.isShimNOCorPLTile(col, row)) { - // wordaround for shimMux, todo: integrate shimMux into routable grid - auto isBundleInList = [](WireBundle bundle, - std::vector bundles) { - return std::find(bundles.begin(), bundles.end(), bundle) != - bundles.end(); - }; - std::vector bundles = {WireBundle::DMA, WireBundle::NOC, - WireBundle::PLIO}; - if (isBundleInList(inPort.bundle, bundles) || - isBundleInList(outPort.bundle, bundles)) - connectionMatrix[inId][outId] = Connectivity::AVAILABLE; - } - } - } +#define OVER_CAPACITY_COEFF 0.1 +#define USED_CAPACITY_COEFF 0.1 +#define DEMAND_COEFF 1.1 +#define DEMAND_BASE 1.0 +#define MAX_CIRCUIT_STREAM_CAPACITY 1 +#define MAX_PACKET_STREAM_CAPACITY 32 + +enum class Connectivity { INVALID = 0, AVAILABLE = 1 }; + +using SwitchboxConnect = struct SwitchboxConnect { + SwitchboxConnect() = default; + SwitchboxConnect(TileID coords) : srcCoords(coords), dstCoords(coords) {} + SwitchboxConnect(TileID srcCoords, TileID dstCoords) + : srcCoords(srcCoords), dstCoords(dstCoords) {} + + TileID srcCoords, dstCoords; + std::vector srcPorts; + std::vector dstPorts; + // connectivity between ports + std::vector> connectivity; + // weights of Dijkstra's shortest path + std::vector> demand; + // history of Channel being over capacity + std::vector> overCapacity; + // how many circuit streams are actually using this Channel + std::vector> usedCapacity; + // how many packet streams are actually using this Channel + std::vector> packetFlowCount; + + // resize the matrices to the size of srcPorts and dstPorts + void resize() { + connectivity.resize( + srcPorts.size(), + std::vector(dstPorts.size(), Connectivity::INVALID)); + demand.resize(srcPorts.size(), std::vector(dstPorts.size(), 0.0)); + overCapacity.resize(srcPorts.size(), std::vector(dstPorts.size(), 0)); + usedCapacity.resize(srcPorts.size(), std::vector(dstPorts.size(), 0)); + packetFlowCount.resize(srcPorts.size(), + std::vector(dstPorts.size(), 0)); } - // given a outPort, find availble input channel - std::vector findAvailableChannelIn(WireBundle inBundle, Port outPort, - bool isPkt) { - std::vector availableChannels; - if (outPortToId.count(outPort) > 0) { - int outId = outPortToId[outPort]; - if (isPkt) { - for (const auto &[inPort, inId] : inPortToId) { - if (inPort.bundle == inBundle && - connectionMatrix[inId][outId] != Connectivity::INVALID) { - bool available = true; - if (inPortPktCount.count(inPort) == 0) { - for (const auto &[outPort, outId] : outPortToId) { - if (connectionMatrix[inId][outId] == Connectivity::OCCUPIED) { - // occupied by others as circuit-switched - available = false; - break; - } - } - } else { - if (inPortPktCount[inPort] >= maxPktStream) { - // occupied by others as packet-switched but exceed max packet - // stream capacity - available = false; - } - } - if (available) - availableChannels.push_back(inPort.channel); - } - } - } else { - for (const auto &[inPort, inId] : inPortToId) { - if (inPort.bundle == inBundle && - connectionMatrix[inId][outId] == Connectivity::AVAILABLE) { - bool available = true; - for (const auto &[outPort, outId] : outPortToId) { - if (connectionMatrix[inId][outId] == Connectivity::OCCUPIED) { - available = false; - break; - } - } - if (available) - availableChannels.push_back(inPort.channel); - } - } + // update demand at the beginning of each dijkstraShortestPaths iteration + void updateDemand() { + for (size_t i = 0; i < srcPorts.size(); i++) { + for (size_t j = 0; j < dstPorts.size(); j++) { + double history = DEMAND_BASE + OVER_CAPACITY_COEFF * overCapacity[i][j]; + double congestion = + DEMAND_BASE + USED_CAPACITY_COEFF * usedCapacity[i][j]; + demand[i][j] = history * congestion; } } - return availableChannels; } - bool allocate(Port inPort, Port outPort, bool isPkt) { - // invalid port - if (outPortToId.count(outPort) == 0 || inPortToId.count(inPort) == 0) - return false; - - int inId = inPortToId[inPort]; - int outId = outPortToId[outPort]; - - // invalid connection - if (connectionMatrix[inId][outId] == Connectivity::INVALID) - return false; - - if (isPkt) { - // a packet-switched stream to be allocated - if (inPortPktCount.count(inPort) == 0) { - for (const auto &[outPort, outId] : outPortToId) { - if (connectionMatrix[inId][outId] == Connectivity::OCCUPIED) { - // occupied by others as circuit-switched, allocation fail! - return false; - } - } - // empty channel, allocation succeed! - inPortPktCount[inPort] = 1; - connectionMatrix[inId][outId] = Connectivity::OCCUPIED; - return true; - } else { - if (inPortPktCount[inPort] >= maxPktStream) { - // occupied by others as packet-switched but exceed max packet stream - // capacity, allocation fail! - return false; - } else { - // valid packet-switched, allocation succeed! - inPortPktCount[inPort]++; - return true; - } - } - } else { - // a circuit-switched stream to be allocated - if (connectionMatrix[inId][outId] == Connectivity::AVAILABLE) { - // empty channel, allocation succeed! - connectionMatrix[inId][outId] = Connectivity::OCCUPIED; - return true; - } else { - // occupied by others, allocation fail! - return false; - } + // inside each dijkstraShortestPaths interation, bump demand when exceeds + // capacity + void bumpDemand(size_t i, size_t j) { + if (usedCapacity[i][j] >= MAX_CIRCUIT_STREAM_CAPACITY) { + demand[i][j] *= DEMAND_COEFF; } } +}; - void clearAllocation() { - for (int inId = 0; inId < inPortId; inId++) { - for (int outId = 0; outId < outPortId; outId++) { - if (connectionMatrix[inId][outId] != Connectivity::INVALID) { - connectionMatrix[inId][outId] = Connectivity::AVAILABLE; - } - } - } - inPortPktCount.clear(); - } +using PathEndPoint = struct PathEndPoint { + PathEndPoint() = default; + PathEndPoint(TileID coords, Port port) : coords(coords), port(port) {} + + TileID coords; + Port port; - friend std::ostream &operator<<(std::ostream &os, const SwitchboxNode &s) { - os << "Switchbox(" << s.col << ", " << s.row << ")"; + friend std::ostream &operator<<(std::ostream &os, const PathEndPoint &s) { + os << "PathEndPoint(" << s.coords << ": " << s.port << ")"; return os; } - GENERATE_TO_STRING(SwitchboxNode); + GENERATE_TO_STRING(PathEndPoint) friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, - const SwitchboxNode &s) { + const PathEndPoint &s) { os << to_string(s); return os; } - bool operator<(const SwitchboxNode &rhs) const { - return std::tie(col, row) < std::tie(rhs.col, rhs.row); + // Needed for the std::maps that store PathEndPoint. + bool operator<(const PathEndPoint &rhs) const { + return std::tie(coords, port) < std::tie(rhs.coords, rhs.port); } - bool operator==(const SwitchboxNode &rhs) const { - return std::tie(col, row) == std::tie(rhs.col, rhs.row); + bool operator==(const PathEndPoint &rhs) const { + return std::tie(coords, port) == std::tie(rhs.coords, rhs.port); } - - int col, row, id; - int inPortId = 0, outPortId = 0; - std::map inPortToId, outPortToId; - - // tenary representation of switchbox connectivity - // -1: invalid in arch, 0: empty and available, 1: occupued - std::vector> connectionMatrix; - - // input ports with incoming packet-switched streams - std::map inPortPktCount; - - // up to 32 packet-switched stram through a port - const int maxPktStream = 32; }; -using ChannelEdge = struct ChannelEdge { - ChannelEdge(SwitchboxNode *src, SwitchboxNode *target) - : src(src), target(target) { - - // get bundle from src to target coordinates - if (src->col == target->col) { - if (src->row > target->row) - bundle = WireBundle::South; - else - bundle = WireBundle::North; - } else { - if (src->col > target->col) - bundle = WireBundle::West; - else - bundle = WireBundle::East; - } - - // maximum number of routing resources - maxCapacity = 0; - for (auto &[outPort, _] : src->outPortToId) { - if (outPort.bundle == bundle) { - maxCapacity++; - } - } - } - - friend std::ostream &operator<<(std::ostream &os, const ChannelEdge &c) { - os << "Channel(src=" << c.src << ", dst=" << c.target << ")"; - return os; - } - - GENERATE_TO_STRING(ChannelEdge) - - friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, - const ChannelEdge &c) { - os << to_string(c); - return os; - } - - SwitchboxNode *src; - SwitchboxNode *target; - - int maxCapacity; - WireBundle bundle; +using Flow = struct Flow { + bool isPacketFlow; + PathEndPoint src; + std::vector dsts; }; -// A SwitchSetting defines the required settings for a SwitchboxNode for a flow -// SwitchSetting.src is the incoming signal +// A SwitchSetting defines the required settings for a Switchbox for a flow +// SwitchSetting.srcs is the fanin // SwitchSetting.dsts is the fanout using SwitchSetting = struct SwitchSetting { SwitchSetting() = default; - SwitchSetting(Port src) : src(src) {} - SwitchSetting(Port src, std::set dsts) - : src(src), dsts(std::move(dsts)) {} - Port src; - std::set dsts; - - // friend definition (will define the function as a non-member function of the - // namespace surrounding the class). + SwitchSetting(std::vector srcs) : srcs(std::move(srcs)) {} + SwitchSetting(std::vector srcs, std::vector dsts) + : srcs(std::move(srcs)), dsts(std::move(dsts)) {} + + std::vector srcs; + std::vector dsts; + + // friend definition (will define the function as a non-member function of + // the namespace surrounding the class). friend std::ostream &operator<<(std::ostream &os, const SwitchSetting &setting) { - os << setting.src << " -> " + os << "{" + << join(llvm::map_range(setting.srcs, + [](const Port &port) { + std::ostringstream ss; + ss << port; + return ss.str(); + }), + ", ") + << " -> " << "{" << join(llvm::map_range(setting.dsts, [](const Port &port) { @@ -320,53 +164,10 @@ using SwitchSetting = struct SwitchSetting { return os; } - bool operator<(const SwitchSetting &rhs) const { return src < rhs.src; } + bool operator<(const SwitchSetting &rhs) const { return srcs < rhs.srcs; } }; -using SwitchSettings = std::map; - -// A Flow defines source and destination vertices -// Only one source, but any number of destinations (fanout) -using PathEndPoint = struct PathEndPoint { - SwitchboxNode sb; - Port port; - - friend std::ostream &operator<<(std::ostream &os, const PathEndPoint &s) { - os << "PathEndPoint(" << s.sb << ": " << s.port << ")"; - return os; - } - - GENERATE_TO_STRING(PathEndPoint) - - friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, - const PathEndPoint &s) { - os << to_string(s); - return os; - } - - // Needed for the std::maps that store PathEndPoint. - bool operator<(const PathEndPoint &rhs) const { - return std::tie(sb, port) < std::tie(rhs.sb, rhs.port); - } - - bool operator==(const PathEndPoint &rhs) const { - return std::tie(sb, port) == std::tie(rhs.sb, rhs.port); - } -}; - -// A Flow defines source and destination vertices -// Only one source, but any number of destinations (fanout) -using PathEndPointNode = struct PathEndPointNode : PathEndPoint { - PathEndPointNode(SwitchboxNode *sb, Port port) - : PathEndPoint{*sb, port}, sb(sb) {} - SwitchboxNode *sb; -}; - -using FlowNode = struct FlowNode { - bool isPacketFlow; - PathEndPointNode src; - std::vector dsts; -}; +using SwitchSettings = std::map; class Router { public: @@ -381,7 +182,6 @@ class Router { virtual bool addFixedConnection(SwitchboxOp switchboxOp) = 0; virtual std::optional> findPaths(int maxIterations) = 0; - virtual SwitchboxNode getSwitchboxNode(TileID coords) = 0; }; class Pathfinder : public Router { @@ -394,34 +194,22 @@ class Pathfinder : public Router { bool addFixedConnection(SwitchboxOp switchboxOp) override; std::optional> findPaths(int maxIterations) override; - - std::map - dijkstraShortestPaths(SwitchboxNode *src); - - SwitchboxNode getSwitchboxNode(TileID coords) override { - return grid.at(coords); - } + std::map dijkstraShortestPaths(PathEndPoint src); private: // Flows to be routed - std::vector flows; - - // Grid of switchboxes available - std::map grid; - - // Use a list instead of a vector because nodes have an edge list of raw - // pointers to edges (so growing a vector would invalidate the pointers). - std::list edges; - - // Use Dijkstra's shortest path to find routes, and use "demand" as the - // weights. - std::map demand; - - // History of Channel being over capacity - std::map overCapacity; - - // how many flows are actually using this Channel - std::map usedCapacity; + std::vector flows; + // Represent all routable paths as a graph + // The key is a pair of TileIDs representing the connectivity from srcTile to + // dstTile If srcTile == dstTile, it represents connections inside the same + // switchbox otherwise, it represents connections (South, North, West, East) + // accross two switchboxes + std::map, SwitchboxConnect> graph; + // Channels available in the network + // The key is a PathEndPoint representing the start of a path + // The value is a vector of PathEndPoints representing the possible ends of + // the path + std::map> channels; }; // DynamicTileAnalysis integrates the Pathfinder class into the MLIR @@ -465,8 +253,8 @@ inline raw_ostream &operator<<(raw_ostream &os, const xilinx::AIE::SwitchSettings &ss) { std::stringstream s; s << "\tSwitchSettings: "; - for (const auto &[sb, setting] : ss) { - s << sb << ": " << setting << " | "; + for (const auto &[coords, setting] : ss) { + s << coords << ": " << setting << " | "; } s << "\n"; os << s.str(); @@ -475,20 +263,4 @@ inline raw_ostream &operator<<(raw_ostream &os, } // namespace llvm -template <> -struct std::hash { - std::size_t operator()(const xilinx::AIE::SwitchboxNode &s) const noexcept { - return std::hash{}({s.col, s.row}); - } -}; - -template <> -struct std::hash { - std::size_t operator()(const xilinx::AIE::PathEndPoint &pe) const noexcept { - std::size_t h1 = std::hash{}(pe.port); - std::size_t h2 = std::hash{}(pe.sb); - return h1 ^ (h2 << 1); - } -}; - #endif diff --git a/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp b/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp old mode 100644 new mode 100755 index a5118190e2..8ee962d7b5 --- a/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp +++ b/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp @@ -26,20 +26,15 @@ using namespace xilinx::AIE; #define DEBUG_TYPE "aie-create-pathfinder-flows" namespace { -std::vector flowOps; - // allocates channels between switchboxes ( but does not assign them) // instantiates shim-muxes AND allocates channels ( no need to rip these up in ) struct ConvertFlowsToInterconnect : OpConversionPattern { using OpConversionPattern::OpConversionPattern; DeviceOp &device; DynamicTileAnalysis &analyzer; - bool keepFlowOp; ConvertFlowsToInterconnect(MLIRContext *context, DeviceOp &d, - DynamicTileAnalysis &a, bool keepFlowOp, - PatternBenefit benefit = 1) - : OpConversionPattern(context, benefit), device(d), analyzer(a), - keepFlowOp(keepFlowOp) {} + DynamicTileAnalysis &a, PatternBenefit benefit = 1) + : OpConversionPattern(context, benefit), device(d), analyzer(a) {} LogicalResult match(FlowOp op) const override { return success(); } @@ -75,11 +70,6 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { auto srcChannel = flowOp.getSourceChannel(); Port srcPort = {srcBundle, srcChannel}; - if (keepFlowOp) { - auto *clonedOp = Op->clone(); - flowOps.push_back(clonedOp); - } - #ifndef NDEBUG auto dstTile = cast(flowOp.getDest().getDefiningOp()); TileID dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; @@ -95,8 +85,7 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { // if the flow (aka "net") for this FlowOp hasn't been processed yet, // add all switchbox connections to implement the flow - SwitchboxNode srcSB = - analyzer.pathfinder->getSwitchboxNode({srcCoords.col, srcCoords.row}); + TileID srcSB = {srcCoords.col, srcCoords.row}; if (PathEndPoint srcPoint = {srcSB, srcPort}; !analyzer.processedFlows[srcPoint]) { SwitchSettings settings = analyzer.flowSolutions[srcPoint]; @@ -132,49 +121,58 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { srcBundle, srcChannel, WireBundle::North, shimCh); } } - for (const auto &[bundle, channel] : setting.dsts) { + assert(setting.srcs.size() == setting.dsts.size()); + for (size_t i = 0; i < setting.srcs.size(); i++) { + Port src = setting.srcs[i]; + Port dest = setting.dsts[i]; // handle special shim connectivity if (curr == srcSB && analyzer.getTile(rewriter, srcSB.col, srcSB.row) .isShimNOCorPLTile()) { addConnection(rewriter, cast(swOp.getOperation()), - flowOp, WireBundle::South, shimCh, bundle, channel); + flowOp, WireBundle::South, shimCh, dest.bundle, + dest.channel); } else if (analyzer.getTile(rewriter, curr.col, curr.row) .isShimNOCorPLTile() && - (bundle == WireBundle::DMA || bundle == WireBundle::PLIO || - bundle == WireBundle::NOC)) { - shimCh = channel; + (dest.bundle == WireBundle::DMA || + dest.bundle == WireBundle::PLIO || + dest.bundle == WireBundle::NOC)) { + shimCh = dest.channel; if (analyzer.getTile(rewriter, curr.col, curr.row) .isShimNOCorPLTile()) { // shim DMAs at end of flows - if (bundle == WireBundle::DMA) { - shimCh = channel == 0 + if (dest.bundle == WireBundle::DMA) { + shimCh = dest.channel == 0 ? 2 : 3; // must be either N2 -> DMA0 or N3 -> DMA1 ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); - addConnection( - rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); - } else if (bundle == WireBundle::NOC) { - shimCh = channel + 2; // must be either N2/3/4/5 -> NOC0/1/2/3 + addConnection(rewriter, + cast(shimMuxOp.getOperation()), + flowOp, WireBundle::North, shimCh, dest.bundle, + dest.channel); + } else if (dest.bundle == WireBundle::NOC) { + shimCh = + dest.channel + 2; // must be either N2/3/4/5 -> NOC0/1/2/3 ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); - addConnection( - rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); - } else if (bundle == WireBundle::PLIO) { + addConnection(rewriter, + cast(shimMuxOp.getOperation()), + flowOp, WireBundle::North, shimCh, dest.bundle, + dest.channel); + } else if (dest.bundle == WireBundle::PLIO) { ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); - addConnection( - rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); + addConnection(rewriter, + cast(shimMuxOp.getOperation()), + flowOp, WireBundle::North, shimCh, dest.bundle, + dest.channel); } } addConnection(rewriter, cast(swOp.getOperation()), - flowOp, setting.src.bundle, setting.src.channel, - WireBundle::South, shimCh); + flowOp, src.bundle, src.channel, WireBundle::South, + shimCh); } else { // otherwise, regular switchbox connection addConnection(rewriter, cast(swOp.getOperation()), - flowOp, setting.src.bundle, setting.src.channel, - bundle, channel); + flowOp, src.bundle, src.channel, dest.bundle, + dest.channel); } } @@ -207,105 +205,9 @@ void AIEPathfinderPass::runOnFlow(DeviceOp d, OpBuilder &builder) { target.addLegalOp(); RewritePatternSet patterns(&getContext()); - patterns.insert(d.getContext(), d, analyzer, - clKeepFlowOp); + patterns.insert(d.getContext(), d, analyzer); if (failed(applyPartialConversion(d, target, std::move(patterns)))) return signalPassFailure(); - - // Keep for visualization - if (clKeepFlowOp) - for (auto op : flowOps) - builder.insert(op); - - // Populate wires between switchboxes and tiles. - for (int col = 0; col <= analyzer.getMaxCol(); col++) { - for (int row = 0; row <= analyzer.getMaxRow(); row++) { - TileOp tile; - if (analyzer.coordToTile.count({col, row})) - tile = analyzer.coordToTile[{col, row}]; - else - continue; - SwitchboxOp sw; - if (analyzer.coordToSwitchbox.count({col, row})) - sw = analyzer.coordToSwitchbox[{col, row}]; - else - continue; - if (col > 0) { - // connections east-west between stream switches - if (analyzer.coordToSwitchbox.count({col - 1, row})) { - auto westsw = analyzer.coordToSwitchbox[{col - 1, row}]; - builder.create(builder.getUnknownLoc(), westsw, - WireBundle::East, sw, WireBundle::West); - } - } - if (row > 0) { - // connections between abstract 'core' of tile - builder.create(builder.getUnknownLoc(), tile, WireBundle::Core, - sw, WireBundle::Core); - // connections between abstract 'dma' of tile - builder.create(builder.getUnknownLoc(), tile, WireBundle::DMA, - sw, WireBundle::DMA); - // connections north-south inside array ( including connection to shim - // row) - if (analyzer.coordToSwitchbox.count({col, row - 1})) { - auto southsw = analyzer.coordToSwitchbox[{col, row - 1}]; - builder.create(builder.getUnknownLoc(), southsw, - WireBundle::North, sw, WireBundle::South); - } - } else if (row == 0) { - if (tile.isShimNOCTile()) { - if (analyzer.coordToShimMux.count({col, 0})) { - auto shimsw = analyzer.coordToShimMux[{col, 0}]; - builder.create( - builder.getUnknownLoc(), shimsw, - WireBundle::North, // Changed to connect into the north - sw, WireBundle::South); - // PLIO is attached to shim mux - if (analyzer.coordToPLIO.count(col)) { - auto plio = analyzer.coordToPLIO[col]; - builder.create(builder.getUnknownLoc(), plio, - WireBundle::North, shimsw, - WireBundle::South); - } - - // abstract 'DMA' connection on tile is attached to shim mux ( in - // row 0 ) - builder.create(builder.getUnknownLoc(), tile, - WireBundle::DMA, shimsw, WireBundle::DMA); - } - } else if (tile.isShimPLTile()) { - // PLIO is attached directly to switch - if (analyzer.coordToPLIO.count(col)) { - auto plio = analyzer.coordToPLIO[col]; - builder.create(builder.getUnknownLoc(), plio, - WireBundle::North, sw, WireBundle::South); - } - } - } - } - } -} - -Operation *AIEPathfinderPass::getOrCreateTile(OpBuilder &builder, int col, - int row) { - TileID index = {col, row}; - Operation *tileOp = tiles[index]; - if (!tileOp) { - auto tile = builder.create(builder.getUnknownLoc(), col, row); - tileOp = tile.getOperation(); - tiles[index] = tileOp; - } - return tileOp; -} - -SwitchboxOp AIEPathfinderPass::getOrCreateSwitchbox(OpBuilder &builder, - TileOp tile) { - for (auto i : tile.getResult().getUsers()) { - if (llvm::isa(*i)) { - return llvm::cast(*i); - } - } - return builder.create(builder.getUnknownLoc(), tile); } template @@ -358,13 +260,17 @@ bool AIEPathfinderPass::findPathToDest(SwitchSettings settings, TileID currTile, int neighbourSourceChannel = currDestChannel; for (const auto &[sbNode, setting] : settings) { TileID tile = {sbNode.col, sbNode.row}; - if ((tile == neighbourTile) && - (setting.src.bundle == neighbourSourceBundle) && - (setting.src.channel == neighbourSourceChannel)) { - for (const auto &[bundle, channel] : setting.dsts) { - if (findPathToDest(settings, neighbourTile, bundle, channel, finalTile, - finalDestBundle, finalDestChannel)) { - return true; + if (tile == neighbourTile) { + assert(setting.srcs.size() == setting.dsts.size()); + for (size_t i = 0; i < setting.srcs.size(); i++) { + Port src = setting.srcs[i]; + Port dest = setting.dsts[i]; + if ((src.bundle == neighbourSourceBundle) && + (src.channel == neighbourSourceChannel)) { + if (findPathToDest(settings, neighbourTile, dest.bundle, dest.channel, + finalTile, finalDestBundle, finalDestChannel)) { + return true; + } } } } @@ -413,22 +319,24 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { if (pktFlowOp->hasAttr("keep_pkt_header")) keepPktHeaderAttr[{destTile, destPort}] = StringAttr::get(Op.getContext(), "true"); - SwitchboxNode srcSB = analyzer.pathfinder->getSwitchboxNode( - {srcCoords.col, srcCoords.row}); + TileID srcSB = {srcCoords.col, srcCoords.row}; if (PathEndPoint srcPoint = {srcSB, srcPort}; !analyzer.processedFlows[srcPoint]) { SwitchSettings settings = analyzer.flowSolutions[srcPoint]; // add connections for all the Switchboxes in SwitchSettings for (const auto &[curr, setting] : settings) { - for (const auto &[bundle, channel] : setting.dsts) { - TileID currTile = {curr.col, curr.row}; + assert(setting.srcs.size() == setting.dsts.size()); + TileID currTile = {curr.col, curr.row}; + for (size_t i = 0; i < setting.srcs.size(); i++) { + Port src = setting.srcs[i]; + Port dest = setting.dsts[i]; // reject false broadcast - if (!findPathToDest(settings, currTile, bundle, channel, + if (!findPathToDest(settings, currTile, dest.bundle, dest.channel, destCoords, destPort.bundle, destPort.channel)) continue; - Connect connect = {{setting.src.bundle, setting.src.channel}, - {bundle, channel}}; + Connect connect = {{src.bundle, src.channel}, + {dest.bundle, dest.channel}}; if (std::find(switchboxes[currTile].begin(), switchboxes[currTile].end(), std::pair{connect, flowID}) == @@ -446,7 +354,8 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { for (const auto &[tileId, connects] : switchboxes) { int col = tileId.col; int row = tileId.row; - Operation *tileOp = getOrCreateTile(builder, col, row); + auto tile = analyzer.getTile(builder, col, row); + Operation *tileOp = tile.getOperation(); LLVM_DEBUG(llvm::dbgs() << "***switchbox*** " << col << " " << row << '\n'); for (const auto &[conn, flowID] : connects) { Port sourcePort = conn.src; @@ -700,7 +609,8 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { // Create a switchbox for the routes and insert inside it. builder.setInsertionPointAfter(tileOp); - SwitchboxOp swbox = getOrCreateSwitchbox(builder, tile); + SwitchboxOp swbox = + analyzer.getSwitchbox(builder, tile.colIndex(), tile.rowIndex()); SwitchboxOp::ensureTerminator(swbox.getConnections(), builder, builder.getUnknownLoc()); Block &b = swbox.getConnections().front(); @@ -834,11 +744,7 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { // If shimmux not defined then create shimmux if (!shimExist) { builder.setInsertionPointAfter(tileOp); - shimOp = builder.create(builder.getUnknownLoc(), tileOp); - Region &r1 = shimOp.getConnections(); - Block *b1 = builder.createBlock(&r1); - builder.setInsertionPointToEnd(b1); - builder.create(builder.getUnknownLoc()); + shimOp = analyzer.getShimMux(builder, tileOp.colIndex()); shimExist = 1; } @@ -869,11 +775,7 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { // If shimmux not defined then create shimmux if (!shimExist) { builder.setInsertionPointAfter(tileOp); - shimOp = builder.create(builder.getUnknownLoc(), tileOp); - Region &r1 = shimOp.getConnections(); - Block *b1 = builder.createBlock(&r1); - builder.setInsertionPointToEnd(b1); - builder.create(builder.getUnknownLoc()); + shimOp = analyzer.getShimMux(builder, tileOp.colIndex()); shimExist = 1; } @@ -899,9 +801,6 @@ void AIEPathfinderPass::runOnPacketFlow(DeviceOp device, OpBuilder &builder) { RewritePatternSet patterns(&getContext()); - if (!clKeepFlowOp) - patterns.add>(device.getContext()); - if (failed(applyPartialConversion(device, target, std::move(patterns)))) signalPassFailure(); } @@ -920,16 +819,75 @@ void AIEPathfinderPass::runOnOperation() { runOnFlow(d, builder); if (clRoutePacket) runOnPacketFlow(d, builder); -} -SwitchboxOp AIEPathfinderPass::getSwitchbox(DeviceOp &d, int col, int row) { - SwitchboxOp output = nullptr; - d.walk([&](SwitchboxOp swBox) { - if (swBox.colIndex() == col && swBox.rowIndex() == row) { - output = swBox; + // Populate wires between switchboxes and tiles. + builder.setInsertionPointToEnd(d.getBody()); + for (int col = 0; col <= analyzer.getMaxCol(); col++) { + for (int row = 0; row <= analyzer.getMaxRow(); row++) { + TileOp tile; + if (analyzer.coordToTile.count({col, row})) + tile = analyzer.coordToTile[{col, row}]; + else + continue; + SwitchboxOp sw; + if (analyzer.coordToSwitchbox.count({col, row})) + sw = analyzer.coordToSwitchbox[{col, row}]; + else + continue; + if (col > 0) { + // connections east-west between stream switches + if (analyzer.coordToSwitchbox.count({col - 1, row})) { + auto westsw = analyzer.coordToSwitchbox[{col - 1, row}]; + builder.create(builder.getUnknownLoc(), westsw, + WireBundle::East, sw, WireBundle::West); + } + } + if (row > 0) { + // connections between abstract 'core' of tile + builder.create(builder.getUnknownLoc(), tile, WireBundle::Core, + sw, WireBundle::Core); + // connections between abstract 'dma' of tile + builder.create(builder.getUnknownLoc(), tile, WireBundle::DMA, + sw, WireBundle::DMA); + // connections north-south inside array ( including connection to shim + // row) + if (analyzer.coordToSwitchbox.count({col, row - 1})) { + auto southsw = analyzer.coordToSwitchbox[{col, row - 1}]; + builder.create(builder.getUnknownLoc(), southsw, + WireBundle::North, sw, WireBundle::South); + } + } else if (row == 0) { + if (tile.isShimNOCTile()) { + if (analyzer.coordToShimMux.count({col, 0})) { + auto shimsw = analyzer.coordToShimMux[{col, 0}]; + builder.create( + builder.getUnknownLoc(), shimsw, + WireBundle::North, // Changed to connect into the north + sw, WireBundle::South); + // PLIO is attached to shim mux + if (analyzer.coordToPLIO.count(col)) { + auto plio = analyzer.coordToPLIO[col]; + builder.create(builder.getUnknownLoc(), plio, + WireBundle::North, shimsw, + WireBundle::South); + } + + // abstract 'DMA' connection on tile is attached to shim mux ( in + // row 0 ) + builder.create(builder.getUnknownLoc(), tile, + WireBundle::DMA, shimsw, WireBundle::DMA); + } + } else if (tile.isShimPLTile()) { + // PLIO is attached directly to switch + if (analyzer.coordToPLIO.count(col)) { + auto plio = analyzer.coordToPLIO[col]; + builder.create(builder.getUnknownLoc(), plio, + WireBundle::North, sw, WireBundle::South); + } + } + } } - }); - return output; + } } std::unique_ptr> createAIEPathfinderPass() { diff --git a/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp b/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp index 1bd80c96c9..5d7de1286b 100644 --- a/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp +++ b/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp @@ -19,9 +19,6 @@ using namespace xilinx; using namespace xilinx::AIE; #define DEBUG_TYPE "aie-pathfinder" -#define OVER_CAPACITY_COEFF 0.02 -#define USED_CAPACITY_COEFF 0.02 -#define DEMAND_COEFF 1.1 LogicalResult DynamicTileAnalysis::runAnalysis(DeviceOp &device) { LLVM_DEBUG(llvm::dbgs() << "\t---Begin DynamicTileAnalysis Constructor---\n"); @@ -97,11 +94,8 @@ LogicalResult DynamicTileAnalysis::runAnalysis(DeviceOp &device) { return device.emitError("Unable to find a legal routing"); // initialize all flows as unprocessed to prep for rewrite - for (const auto &[pathEndPoint, switchSetting] : flowSolutions) { - processedFlows[pathEndPoint] = false; - LLVM_DEBUG(llvm::dbgs() << "Flow starting at (" << pathEndPoint.sb.col - << "," << pathEndPoint.sb.row << "):\t"); - LLVM_DEBUG(llvm::dbgs() << switchSetting); + for (const auto &[PathEndPoint, switchSetting] : flowSolutions) { + processedFlows[PathEndPoint] = false; } // fill in coords to TileOps, SwitchboxOps, and ShimMuxOps @@ -178,355 +172,408 @@ ShimMuxOp DynamicTileAnalysis::getShimMux(OpBuilder &builder, int col) { void Pathfinder::initialize(int maxCol, int maxRow, const AIETargetModel &targetModel) { - // make grid of switchboxes - int id = 0; - for (int row = 0; row <= maxRow; row++) { - for (int col = 0; col <= maxCol; col++) { - grid.insert({{col, row}, - SwitchboxNode{col, row, id++, maxCol, maxRow, targetModel}}); - SwitchboxNode &thisNode = grid.at({col, row}); - if (row > 0) { // if not in row 0 add channel to North/South - SwitchboxNode &southernNeighbor = grid.at({col, row - 1}); - // get the number of outgoing connections on the south side - outgoing - // because these correspond to rhs of a connect op - if (targetModel.getNumDestSwitchboxConnections(col, row, - WireBundle::South)) { - edges.emplace_back(&thisNode, &southernNeighbor); - } - // get the number of incoming connections on the south side - incoming - // because they correspond to connections on the southside that are then - // routed using internal connect ops through the switchbox (i.e., lhs of - // connect ops) - if (targetModel.getNumSourceSwitchboxConnections(col, row, - WireBundle::South)) { - edges.emplace_back(&southernNeighbor, &thisNode); + + std::map maxChannels; + auto intraconnect = [&](int col, int row) { + TileID coords = {col, row}; + SwitchboxConnect sb = {coords}; + + const std::vector bundles = { + WireBundle::Core, WireBundle::DMA, WireBundle::FIFO, + WireBundle::South, WireBundle::West, WireBundle::North, + WireBundle::East, WireBundle::PLIO, WireBundle::NOC, + WireBundle::Trace, WireBundle::Ctrl}; + for (WireBundle bundle : bundles) { + // get all ports into current switchbox + int channels = + targetModel.getNumSourceSwitchboxConnections(col, row, bundle); + if (channels == 0 && targetModel.isShimNOCorPLTile(col, row)) { + // wordaround for shimMux + channels = targetModel.getNumSourceShimMuxConnections(col, row, bundle); + } + for (int channel = 0; channel < channels; channel++) { + sb.srcPorts.push_back(Port{bundle, channel}); + } + // get all ports out of current switchbox + channels = targetModel.getNumDestSwitchboxConnections(col, row, bundle); + if (channels == 0 && targetModel.isShimNOCorPLTile(col, row)) { + // wordaround for shimMux + channels = targetModel.getNumDestShimMuxConnections(col, row, bundle); + } + for (int channel = 0; channel < channels; channel++) { + sb.dstPorts.push_back(Port{bundle, channel}); + } + maxChannels[bundle] = channels; + } + // initialize matrices + sb.resize(); + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + auto &pIn = sb.srcPorts[i]; + auto &pOut = sb.dstPorts[j]; + if (targetModel.isLegalTileConnection(col, row, pIn.bundle, pIn.channel, + pOut.bundle, pOut.channel)) + sb.connectivity[i][j] = Connectivity::AVAILABLE; + else { + sb.connectivity[i][j] = Connectivity::INVALID; + if (targetModel.isShimNOCorPLTile(col, row)) { + // wordaround for shimMux + auto isBundleInList = [](WireBundle bundle, + std::vector bundles) { + return std::find(bundles.begin(), bundles.end(), bundle) != + bundles.end(); + }; + const std::vector bundles = { + WireBundle::DMA, WireBundle::NOC, WireBundle::PLIO}; + if (isBundleInList(pIn.bundle, bundles) || + isBundleInList(pOut.bundle, bundles)) + sb.connectivity[i][j] = Connectivity::AVAILABLE; + } } } + } + graph[std::make_pair(coords, coords)] = sb; + }; + + auto interconnect = [&](int col, int row, int targetCol, int targetRow, + WireBundle srcBundle, WireBundle dstBundle) { + SwitchboxConnect sb = {{col, row}, {targetCol, targetRow}}; + for (int channel = 0; channel < maxChannels[srcBundle]; channel++) { + sb.srcPorts.push_back(Port{srcBundle, channel}); + sb.dstPorts.push_back(Port{dstBundle, channel}); + } + sb.resize(); + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + sb.connectivity[i][i] = Connectivity::AVAILABLE; + } + graph[std::make_pair(TileID{col, row}, TileID{targetCol, targetRow})] = sb; + }; - if (col > 0) { // if not in col 0 add channel to East/West - SwitchboxNode &westernNeighbor = grid.at({col - 1, row}); - if (targetModel.getNumDestSwitchboxConnections(col, row, - WireBundle::West)) { - edges.emplace_back(&thisNode, &westernNeighbor); - } - if (targetModel.getNumSourceSwitchboxConnections(col, row, - WireBundle::West)) { - edges.emplace_back(&westernNeighbor, &thisNode); - } + for (int row = 0; row <= maxRow; row++) { + for (int col = 0; col <= maxCol; col++) { + maxChannels.clear(); + // connections within the same switchbox + intraconnect(col, row); + + // connections between switchboxes + if (row > 0) { + // from south to north + interconnect(col, row, col, row - 1, WireBundle::South, + WireBundle::North); + } + if (row < maxRow) { + // from north to south + interconnect(col, row, col, row + 1, WireBundle::North, + WireBundle::South); + } + if (col > 0) { + // from east to west + interconnect(col, row, col - 1, row, WireBundle::West, + WireBundle::East); + } + if (col < maxCol) { + // from west to east + interconnect(col, row, col + 1, row, WireBundle::East, + WireBundle::West); } } } } -// Add a flow from src to dst can have an arbitrary number of dst locations due -// to fanout. +// Add a flow from src to dst can have an arbitrary number of dst locations +// due to fanout. void Pathfinder::addFlow(TileID srcCoords, Port srcPort, TileID dstCoords, Port dstPort, bool isPacketFlow) { // check if a flow with this source already exists for (auto &[isPkt, src, dsts] : flows) { - SwitchboxNode *existingSrcPtr = src.sb; - assert(existingSrcPtr && "nullptr flow source"); - if (Port existingPort = src.port; existingSrcPtr->col == srcCoords.col && - existingSrcPtr->row == srcCoords.row && - existingPort == srcPort) { - // find the vertex corresponding to the destination - SwitchboxNode *matchingDstSbPtr = &grid.at(dstCoords); - dsts.emplace_back(matchingDstSbPtr, dstPort); + if (src.coords == srcCoords && src.port == srcPort) { + dsts.emplace_back(PathEndPoint{dstCoords, dstPort}); return; } } // If no existing flow was found with this source, create a new flow. - SwitchboxNode *matchingSrcSbPtr = &grid.at(srcCoords); - SwitchboxNode *matchingDstSbPtr = &grid.at(dstCoords); - flows.push_back({isPacketFlow, PathEndPointNode{matchingSrcSbPtr, srcPort}, - std::vector{{matchingDstSbPtr, dstPort}}}); + flows.push_back( + Flow{isPacketFlow, PathEndPoint{srcCoords, srcPort}, + std::vector{PathEndPoint{dstCoords, dstPort}}}); } -// Keep track of connections already used in the AIE; Pathfinder algorithm will -// avoid using these. +// Keep track of connections already used in the AIE; Pathfinder algorithm +// will avoid using these. bool Pathfinder::addFixedConnection(SwitchboxOp switchboxOp) { int col = switchboxOp.colIndex(); int row = switchboxOp.rowIndex(); - SwitchboxNode &sb = grid.at({col, row}); - std::set invalidInId, invalidOutId; - + TileID coords = {col, row}; + auto &sb = graph[std::make_pair(coords, coords)]; for (ConnectOp connectOp : switchboxOp.getOps()) { - Port srcPort = connectOp.sourcePort(); - Port destPort = connectOp.destPort(); - if (sb.inPortToId.count(srcPort) == 0 || - sb.outPortToId.count(destPort) == 0) - return false; - int inId = sb.inPortToId.at(srcPort); - int outId = sb.outPortToId.at(destPort); - if (sb.connectionMatrix[inId][outId] != Connectivity::AVAILABLE) - return false; - invalidInId.insert(inId); - invalidOutId.insert(outId); - } - - for (const auto &[inPort, inId] : sb.inPortToId) { - for (const auto &[outPort, outId] : sb.outPortToId) { - if (invalidInId.find(inId) != invalidInId.end() || - invalidOutId.find(outId) != invalidOutId.end()) { - // mark as invalid - sb.connectionMatrix[inId][outId] = Connectivity::INVALID; + bool found = false; + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + if (sb.srcPorts[i] == connectOp.sourcePort() && + sb.dstPorts[j] == connectOp.destPort() && + sb.connectivity[i][j] == Connectivity::AVAILABLE) { + sb.connectivity[i][j] = Connectivity::INVALID; + found = true; + } } } + if (!found) { + // could not add such a fixed connection + return false; + } } return true; } static constexpr double INF = std::numeric_limits::max(); -std::map -Pathfinder::dijkstraShortestPaths(SwitchboxNode *src) { - // Use std::map instead of DenseMap because DenseMap doesn't let you overwrite - // tombstones. - auto distance = std::map(); - auto preds = std::map(); - std::map indexInHeap; +std::map +Pathfinder::dijkstraShortestPaths(PathEndPoint src) { + // Use std::map instead of DenseMap because DenseMap doesn't let you + // overwrite tombstones. + std::map distance; + std::map preds; + std::map indexInHeap; + enum Color { WHITE, GRAY, BLACK }; + std::map colors; typedef d_ary_heap_indirect< - /*Value=*/SwitchboxNode *, /*Arity=*/4, - /*IndexInHeapPropertyMap=*/std::map, - /*DistanceMap=*/std::map &, + /*Value=*/PathEndPoint, /*Arity=*/4, + /*IndexInHeapPropertyMap=*/std::map, + /*DistanceMap=*/std::map &, /*Compare=*/std::less<>> MutableQueue; MutableQueue Q(distance, indexInHeap); - for (auto &[_, sb] : grid) - distance.emplace(&sb, INF); distance[src] = 0.0; - - std::map> channels; - - enum Color { WHITE, GRAY, BLACK }; - std::map colors; - for (auto &[_, sb] : grid) { - SwitchboxNode *sbPtr = &sb; - colors[sbPtr] = WHITE; - for (auto &e : edges) { - if (e.src == sbPtr) { - channels[sbPtr].push_back(&e); - } - } - std::sort(channels[sbPtr].begin(), channels[sbPtr].end(), - [](const ChannelEdge *c1, ChannelEdge *c2) { - return c1->target->id < c2->target->id; - }); - } - Q.push(src); while (!Q.empty()) { src = Q.top(); Q.pop(); - for (ChannelEdge *e : channels[src]) { - SwitchboxNode *dest = e->target; - bool relax = distance[src] + demand[e] < distance[dest]; - if (colors[dest] == WHITE) { + + // get all channels src connects to + if (channels.count(src) == 0) { + auto &sb = graph[std::make_pair(src.coords, src.coords)]; + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + if (sb.srcPorts[i] == src.port && + sb.connectivity[i][j] == Connectivity::AVAILABLE) { + // connections within the same switchbox + channels[src].push_back(PathEndPoint{src.coords, sb.dstPorts[j]}); + } + } + } + // connections to neighboring switchboxes + std::vector> neighbors = { + {{src.coords.col, src.coords.row - 1}, + {WireBundle::North, src.port.channel}}, + {{src.coords.col - 1, src.coords.row}, + {WireBundle::East, src.port.channel}}, + {{src.coords.col, src.coords.row + 1}, + {WireBundle::South, src.port.channel}}, + {{src.coords.col + 1, src.coords.row}, + {WireBundle::West, src.port.channel}}}; + + for (const auto &[neighborCoords, neighborPort] : neighbors) { + if (graph.count(std::make_pair(src.coords, neighborCoords)) > 0 && + src.port.bundle == getConnectingBundle(neighborPort.bundle)) { + auto &sb = graph[std::make_pair(src.coords, neighborCoords)]; + if (std::find(sb.dstPorts.begin(), sb.dstPorts.end(), neighborPort) != + sb.dstPorts.end()) + channels[src].push_back({neighborCoords, neighborPort}); + } + } + std::sort(channels[src].begin(), channels[src].end()); + } + + for (auto &dest : channels[src]) { + if (distance.count(dest) == 0) + distance[dest] = INF; + auto &sb = graph[std::make_pair(src.coords, dest.coords)]; + size_t i = std::distance( + sb.srcPorts.begin(), + std::find(sb.srcPorts.begin(), sb.srcPorts.end(), src.port)); + size_t j = std::distance( + sb.dstPorts.begin(), + std::find(sb.dstPorts.begin(), sb.dstPorts.end(), dest.port)); + assert(i < sb.srcPorts.size()); + assert(j < sb.dstPorts.size()); + bool relax = distance[src] + sb.demand[i][j] < distance[dest]; + if (colors.count(dest) == 0) { + // was WHITE if (relax) { - distance[dest] = distance[src] + demand[e]; + distance[dest] = distance[src] + sb.demand[i][j]; preds[dest] = src; colors[dest] = GRAY; } Q.push(dest); } else if (colors[dest] == GRAY && relax) { - distance[dest] = distance[src] + demand[e]; + distance[dest] = distance[src] + sb.demand[i][j]; preds[dest] = src; } } colors[src] = BLACK; } + return preds; } // Perform congestion-aware routing for all flows which have been added. -// Use Dijkstra's shortest path to find routes, and use "demand" as the weights. -// If the routing finds too much congestion, update the demand weights -// and repeat the process until a valid solution is found. -// Returns a map specifying switchbox settings for all flows. -// If no legal routing can be found after maxIterations, returns empty vector. +// Use Dijkstra's shortest path to find routes, and use "demand" as the +// weights. If the routing finds too much congestion, update the demand +// weights and repeat the process until a valid solution is found. Returns a +// map specifying switchbox settings for all flows. If no legal routing can be +// found after maxIterations, returns empty vector. std::optional> Pathfinder::findPaths(const int maxIterations) { - LLVM_DEBUG(llvm::dbgs() << "Begin Pathfinder::findPaths\n"); - int iterationCount = 0; + LLVM_DEBUG(llvm::dbgs() << "\t---Begin Pathfinder::findPaths---\n"); std::map routingSolution; - // initialize all Channel histories to 0 - for (auto &ch : edges) { - overCapacity[&ch] = 0; - usedCapacity[&ch] = 0; + for (auto &[_, sb] : graph) { + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + sb.usedCapacity[i][j] = 0; + sb.overCapacity[i][j] = 0; + } + } } - // assume legal until found otherwise - bool isLegal = true; + int iterationCount = -1; + int illegalEdges = 0; + int totalPathLength = 0; do { - LLVM_DEBUG(llvm::dbgs() - << "Begin findPaths iteration #" << iterationCount << "\n"); - // update demand on all channels - for (auto &ch : edges) { - double history = 1.0 + OVER_CAPACITY_COEFF * overCapacity[&ch]; - double congestion = 1.0 + USED_CAPACITY_COEFF * usedCapacity[&ch]; - demand[&ch] = history * congestion; - } // if reach maxIterations, throw an error since no routing can be found - if (++iterationCount > maxIterations) { + if (++iterationCount >= maxIterations) { LLVM_DEBUG(llvm::dbgs() - << "Pathfinder: maxIterations has been exceeded (" + << "\t\tPathfinder: maxIterations has been exceeded (" << maxIterations << " iterations)...unable to find routing for flows.\n"); return std::nullopt; } + LLVM_DEBUG(llvm::dbgs() << "\t\t---Begin findPaths iteration #" + << iterationCount << "---\n"); + // update demand at the beginning of each iteration + for (auto &[_, sb] : graph) { + sb.updateDemand(); + } + // "rip up" all routes + illegalEdges = 0; + totalPathLength = 0; routingSolution.clear(); - for (auto &[tileID, node] : grid) - node.clearAllocation(); - for (auto &ch : edges) - usedCapacity[&ch] = 0; - isLegal = true; + for (auto &[_, sb] : graph) { + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + sb.usedCapacity[i][j] = 0; + sb.packetFlowCount[i][j] = 0; + } + } + } // for each flow, find the shortest path from source to destination // update used_capacity for the path between them for (const auto &[isPkt, src, dsts] : flows) { // Use dijkstra to find path given current demand from the start // switchbox; find the shortest paths to each other switchbox. Output is - // in the predecessor map, which must then be processed to get individual - // switchbox settings - assert(src.sb && "nonexistent flow source"); - std::set processed; - std::map preds = - dijkstraShortestPaths(src.sb); - - auto findIncomingEdge = [&](SwitchboxNode *sb) -> ChannelEdge * { - for (auto &e : edges) { - if (e.src == preds[sb] && e.target == sb) { - return &e; - } - } - return nullptr; - }; + // in the predecessor map, which must then be processed to get + // individual switchbox settings + std::set processed; + std::map preds = dijkstraShortestPaths(src); // trace the path of the flow backwards via predecessors // increment used_capacity for the associated channels SwitchSettings switchSettings; - // set the input bundle for the source endpoint - switchSettings[*src.sb].src = src.port; - processed.insert(src.sb); - // track destination ports used by src.sb - std::vector srcDestPorts; - for (const PathEndPointNode &endPoint : dsts) { - SwitchboxNode *curr = endPoint.sb; - assert(curr && "endpoint has no source switchbox"); - // set the output bundle for this destination endpoint - switchSettings[*curr].dsts.insert(endPoint.port); - Port lastDestPort = endPoint.port; + processed.insert(src); + for (auto endPoint : dsts) { + if (endPoint == src) { + // route to self + switchSettings[src.coords].srcs.push_back(src.port); + switchSettings[src.coords].dsts.push_back(src.port); + } + auto curr = endPoint; // trace backwards until a vertex already processed is reached while (!processed.count(curr)) { - // find the incoming edge from the pred to curr - ChannelEdge *ch = findIncomingEdge(curr); - assert(ch != nullptr && "couldn't find ch"); - int channel; - // find all available channels in - std::vector availableChannels = curr->findAvailableChannelIn( - getConnectingBundle(ch->bundle), lastDestPort, isPkt); - if (availableChannels.size() > 0) { - // if possible, choose the channel that predecessor can also use - // todo: consider all predecessors? - int bFound = false; - auto &pred = preds[curr]; - if (!processed.count(pred) && pred != src.sb) { - ChannelEdge *predCh = findIncomingEdge(pred); - assert(predCh != nullptr && "couldn't find ch"); - for (int availableCh : availableChannels) { - channel = availableCh; - std::vector availablePredChannels = - pred->findAvailableChannelIn( - getConnectingBundle(predCh->bundle), - {ch->bundle, channel}, isPkt); - if (availablePredChannels.size() > 0) { - bFound = true; - break; - } - } + auto &sb = graph[std::make_pair(preds[curr].coords, curr.coords)]; + size_t i = + std::distance(sb.srcPorts.begin(), + std::find(sb.srcPorts.begin(), sb.srcPorts.end(), + preds[curr].port)); + size_t j = std::distance( + sb.dstPorts.begin(), + std::find(sb.dstPorts.begin(), sb.dstPorts.end(), curr.port)); + assert(i < sb.srcPorts.size()); + assert(j < sb.dstPorts.size()); + if (isPkt) { + sb.packetFlowCount[i][j]++; + // maximum packet stream per channel + if (sb.packetFlowCount[i][j] >= MAX_PACKET_STREAM_CAPACITY) { + sb.packetFlowCount[i][j] = 0; + sb.usedCapacity[i][j]++; } - if (!bFound) - channel = availableChannels[0]; - bool succeed = - curr->allocate({getConnectingBundle(ch->bundle), channel}, - lastDestPort, isPkt); - if (!succeed) - assert(false && "invalid allocation"); - LLVM_DEBUG(llvm::dbgs() - << *curr << ", connecting: " - << stringifyWireBundle(getConnectingBundle(ch->bundle)) - << channel << " -> " - << stringifyWireBundle(lastDestPort.bundle) - << lastDestPort.channel << "\n"); } else { - // if no channel available, use a virtual channel id and mark - // routing as being invalid - channel = usedCapacity[ch]; - if (isLegal) { - overCapacity[ch]++; - LLVM_DEBUG(llvm::dbgs() - << *curr << ", congestion: " - << stringifyWireBundle(getConnectingBundle(ch->bundle)) - << ", used_capacity = " << usedCapacity[ch] - << ", over_capacity_count = " << overCapacity[ch] - << "\n"); - } - isLegal = false; + sb.packetFlowCount[i][j] = 0; + sb.usedCapacity[i][j]++; } - usedCapacity[ch]++; - - // add the entrance port for this Switchbox - Port currSourcePort = {getConnectingBundle(ch->bundle), channel}; - switchSettings[*curr].src = {currSourcePort}; - - // add the current Switchbox to the map of the predecessor - Port PredDestPort = {ch->bundle, channel}; - switchSettings[*preds[curr]].dsts.insert(PredDestPort); - lastDestPort = PredDestPort; - // if at capacity, bump demand to discourage using this Channel - if (usedCapacity[ch] >= ch->maxCapacity) { - // this means the order matters! - demand[ch] *= DEMAND_COEFF; - LLVM_DEBUG(llvm::dbgs() - << *curr << ", bump demand: " - << stringifyWireBundle(getConnectingBundle(ch->bundle)) - << ", demand = " << demand[ch] << "\n"); + // this means the order matters! + sb.bumpDemand(i, j); + if (preds[curr].coords == curr.coords) { + switchSettings[preds[curr].coords].srcs.push_back(preds[curr].port); + switchSettings[curr.coords].dsts.push_back(curr.port); } - processed.insert(curr); curr = preds[curr]; - - // allocation may fail, as we start from the dest of flow while - // src.port is not chosen by router - if (curr == src.sb && - std::find(srcDestPorts.begin(), srcDestPorts.end(), - lastDestPort) == srcDestPorts.end()) { - bool succeed = src.sb->allocate(src.port, lastDestPort, isPkt); - if (!succeed) { - isLegal = false; - overCapacity[ch]++; - LLVM_DEBUG(llvm::dbgs() - << *curr << ", unable to connect: " - << stringifyWireBundle(src.port.bundle) - << src.port.channel << " -> " - << stringifyWireBundle(lastDestPort.bundle) - << lastDestPort.channel << "\n"); - } - srcDestPorts.push_back(lastDestPort); - } } } // add this flow to the proposed solution routingSolution[src] = switchSettings; } - } while (!isLegal); // continue iterations until a legal routing is found + for (auto &[_, sb] : graph) { + for (size_t i = 0; i < sb.srcPorts.size(); i++) { + for (size_t j = 0; j < sb.dstPorts.size(); j++) { + // fix used capacity for packet flows + if (sb.packetFlowCount[i][j] > 0) { + sb.packetFlowCount[i][j] = 0; + sb.usedCapacity[i][j]++; + } + // check that every channel does not exceed max capacity + if (sb.usedCapacity[i][j] > MAX_CIRCUIT_STREAM_CAPACITY) { + sb.overCapacity[i][j]++; + illegalEdges++; + LLVM_DEBUG( + llvm::dbgs() + << "\t\t\tToo much capacity on (" << sb.srcCoords.col << "," + << sb.srcCoords.row << ") " << sb.srcPorts[i].bundle + << sb.srcPorts[i].channel << " -> (" << sb.dstCoords.col << "," + << sb.dstCoords.row << ") " << sb.dstPorts[j].bundle + << sb.dstPorts[j].channel << ", used_capacity = " + << sb.usedCapacity[i][j] << ", demand = " << sb.demand[i][j] + << ", over_capacity_count = " << sb.overCapacity[i][j] << "\n"); + } + // calculate total path length (across switchboxes) + if (sb.srcCoords != sb.dstCoords) { + totalPathLength += sb.usedCapacity[i][j]; + } + } + } + } + +#ifndef NDEBUG + for (const auto &[PathEndPoint, switchSetting] : routingSolution) { + LLVM_DEBUG(llvm::dbgs() + << "\t\t\tFlow starting at (" << PathEndPoint.coords.col << "," + << PathEndPoint.coords.row << "):\t"); + LLVM_DEBUG(llvm::dbgs() << switchSetting); + } +#endif + LLVM_DEBUG(llvm::dbgs() + << "\t\t---End findPaths iteration #" << iterationCount + << " , illegal edges count = " << illegalEdges + << ", total path length = " << totalPathLength << "---\n"); + } while (illegalEdges > + 0); // continue iterations until a legal routing is found + LLVM_DEBUG(llvm::dbgs() << "\t---End Pathfinder::findPaths---\n"); return routingSolution; } diff --git a/lib/Targets/AIEFlowsToJSON.cpp b/lib/Targets/AIEFlowsToJSON.cpp index 3444c6f706..1df1be895a 100644 --- a/lib/Targets/AIEFlowsToJSON.cpp +++ b/lib/Targets/AIEFlowsToJSON.cpp @@ -74,6 +74,12 @@ void translateSwitchboxes(DeviceOp targetOp, raw_ostream &output) { } } + std::map shimMuxes; + for (ShimMuxOp shimMuxOp : targetOp.getOps()) { + shimMuxes[{shimMuxOp.colIndex(), shimMuxOp.rowIndex()}] = shimMuxOp; + } + + int totalPathLength = 0; // for each switchbox, write name, coordinates, and routing demand info for (SwitchboxOp switchboxOp : targetOp.getOps()) { int col = switchboxOp.colIndex(); @@ -93,10 +99,15 @@ void translateSwitchboxes(DeviceOp targetOp, raw_ostream &output) { uint32_t connectCounts[10]; for (auto &connectCount : connectCounts) connectCount = 0; + + std::set ports; for (ConnectOp connectOp : switchboxOp.getOps()) - connectCounts[int(connectOp.getDestBundle())]++; + ports.insert(connectOp.destPort()); for (MasterSetOp masterSetOp : switchboxOp.getOps()) - connectCounts[int(masterSetOp.destPort().bundle)]++; + ports.insert(masterSetOp.destPort()); + for (Port port : ports) { + connectCounts[int(port.bundle)]++; + } switchString += "\"northbound\": " + std::to_string(connectCounts[int(WireBundle::North)]) + @@ -111,7 +122,35 @@ void translateSwitchboxes(DeviceOp targetOp, raw_ostream &output) { std::to_string(connectCounts[int(WireBundle::West)]) + "\n"; switchString += "},\n"; output << switchString; + + // calculate total path length + totalPathLength += connectCounts[int(WireBundle::North)]; + totalPathLength += connectCounts[int(WireBundle::East)]; + totalPathLength += connectCounts[int(WireBundle::South)]; + totalPathLength += connectCounts[int(WireBundle::West)]; + + // deduct shim muxes from total path length + if (shimMuxes.count({col, row})) { + auto shimMuxOp = shimMuxes[{col, row}]; + std::set ports; + for (ConnectOp connectOp : shimMuxOp.getOps()) { + Port port = connectOp.sourcePort(); + if (port.bundle == WireBundle::North) { + ports.insert(port); + } + } + for (PacketRulesOp packetRulesOp : shimMuxOp.getOps()) { + Port port = packetRulesOp.sourcePort(); + if (port.bundle == WireBundle::North) { + ports.insert(port); + } + } + totalPathLength -= ports.size(); + } } + + // write total path length to JSON + output << "\"total_path_length\": " << totalPathLength << ",\n"; } void translateCircuitFlows(DeviceOp targetOp, int &flowCount, diff --git a/mlir_tutorials/tutorial-4/switchbox/path/pathfinder_input.mlir b/mlir_tutorials/tutorial-4/switchbox/path/pathfinder_input.mlir index 42948aaa8a..8187ee1147 100644 --- a/mlir_tutorials/tutorial-4/switchbox/path/pathfinder_input.mlir +++ b/mlir_tutorials/tutorial-4/switchbox/path/pathfinder_input.mlir @@ -9,40 +9,70 @@ //===----------------------------------------------------------------------===// // RUN: aie-opt --aie-canonicalize-device %s | aie-opt --aie-create-pathfinder-flows | FileCheck %s -// CHECK: %15 = aie.switchbox(%3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %16 = aie.switchbox(%4) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %17 = aie.switchbox(%7) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %18 = aie.switchbox(%10) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %19 = aie.switchbox(%13) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %20 = aie.switchbox(%6) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %21 = aie.switchbox(%9) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %22 = aie.switchbox(%14) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } +// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) +// CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: } +// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) +// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: } +// CHECK: %[[VAL_4:.*]] = aie.tile(0, 3) +// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: } +// CHECK: %[[VAL_6:.*]] = aie.tile(1, 1) +// CHECK: %[[VAL_7:.*]] = aie.tile(1, 2) +// CHECK: %[[VAL_8:.*]] = aie.tile(1, 3) +// CHECK: %[[VAL_9:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: } +// CHECK: %[[VAL_10:.*]] = aie.tile(2, 1) +// CHECK: %[[VAL_11:.*]] = aie.tile(2, 2) +// CHECK: %[[VAL_12:.*]] = aie.tile(2, 3) +// CHECK: %[[VAL_13:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: } +// CHECK: %[[VAL_14:.*]] = aie.tile(3, 1) +// CHECK: %[[VAL_15:.*]] = aie.tile(3, 2) +// CHECK: %[[VAL_16:.*]] = aie.tile(3, 3) +// CHECK: %[[VAL_17:.*]] = aie.tile(4, 1) +// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: } +// CHECK: %[[VAL_19:.*]] = aie.tile(4, 2) +// CHECK: %[[VAL_20:.*]] = aie.tile(4, 3) +// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_24:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_19]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_20]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: aie.connect +// CHECK: } + module @pathfinder{ %t01 = aie.tile(0, 1) diff --git a/test/create-flows/broadcast.mlir b/test/create-flows/broadcast.mlir index bcad48440b..c4d8798d01 100644 --- a/test/create-flows/broadcast.mlir +++ b/test/create-flows/broadcast.mlir @@ -8,34 +8,39 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T00:.*]] = aie.tile(0, 0) -// CHECK: %[[T13:.*]] = aie.tile(1, 3) -// CHECK: %[[T11:.*]] = aie.tile(1, 1) -// CHECK: %[[T10:.*]] = aie.tile(1, 0) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T31:.*]] = aie.tile(3, 1) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T71:.*]] = aie.tile(7, 1) -// CHECK: %[[T72:.*]] = aie.tile(7, 2) -// CHECK: %[[T73:.*]] = aie.tile(7, 3) -// CHECK: %[[T80:.*]] = aie.tile(8, 0) -// CHECK: %[[T82:.*]] = aie.tile(8, 2) -// CHECK: %[[T83:.*]] = aie.tile(8, 3) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: %[[T00:.*]] = aie.tile(0, 0) +// CHECK1: %[[T13:.*]] = aie.tile(1, 3) +// CHECK1: %[[T11:.*]] = aie.tile(1, 1) +// CHECK1: %[[T10:.*]] = aie.tile(1, 0) +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T31:.*]] = aie.tile(3, 1) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T71:.*]] = aie.tile(7, 1) +// CHECK1: %[[T72:.*]] = aie.tile(7, 2) +// CHECK1: %[[T73:.*]] = aie.tile(7, 3) +// CHECK1: %[[T80:.*]] = aie.tile(8, 0) +// CHECK1: %[[T82:.*]] = aie.tile(8, 2) +// CHECK1: %[[T83:.*]] = aie.tile(8, 3) // -// CHECK: aie.flow(%[[T20]], DMA : 0, %[[T71]], DMA : 0) -// CHECK: aie.flow(%[[T20]], DMA : 0, %[[T82]], DMA : 0) -// CHECK: aie.flow(%[[T20]], DMA : 0, %[[T31]], DMA : 0) -// CHECK: aie.flow(%[[T20]], DMA : 0, %[[T13]], DMA : 0) -// CHECK: aie.flow(%[[T60]], DMA : 0, %[[T83]], DMA : 1) -// CHECK: aie.flow(%[[T60]], DMA : 0, %[[T22]], DMA : 1) -// CHECK: aie.flow(%[[T60]], DMA : 0, %[[T31]], DMA : 1) -// CHECK: aie.flow(%[[T60]], DMA : 0, %[[T02]], DMA : 1) +// CHECK1: aie.flow(%[[T20]], DMA : 0, %[[T82]], DMA : 0) +// CHECK1: aie.flow(%[[T20]], DMA : 0, %[[T71]], DMA : 0) +// CHECK1: aie.flow(%[[T20]], DMA : 0, %[[T31]], DMA : 0) +// CHECK1: aie.flow(%[[T20]], DMA : 0, %[[T13]], DMA : 0) +// CHECK1: aie.flow(%[[T60]], DMA : 0, %[[T83]], DMA : 1) +// CHECK1: aie.flow(%[[T60]], DMA : 0, %[[T31]], DMA : 1) +// CHECK1: aie.flow(%[[T60]], DMA : 0, %[[T22]], DMA : 1) +// CHECK1: aie.flow(%[[T60]], DMA : 0, %[[T02]], DMA : 1) + +// CHECK2: "total_path_length": 29 module { aie.device(xcvc1902) { diff --git a/test/create-flows/unit_existing_flow.mlir b/test/create-flows/existing_flow.mlir similarity index 93% rename from test/create-flows/unit_existing_flow.mlir rename to test/create-flows/existing_flow.mlir index 31ddbe5fb2..c475081e75 100644 --- a/test/create-flows/unit_existing_flow.mlir +++ b/test/create-flows/existing_flow.mlir @@ -6,7 +6,7 @@ //===----------------------------------------------------------------------===// // RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: module + // CHECK: %[[T02:.*]] = aie.tile(0, 2) // CHECK: %[[T12:.*]] = aie.tile(1, 2) // CHECK: %[[T22:.*]] = aie.tile(2, 2) @@ -16,11 +16,11 @@ // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T12]]) { // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T22]]) { // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T32]]) { // CHECK: aie.connect diff --git a/test/create-flows/unit_fixed_connections.mlir b/test/create-flows/fixed_connections.mlir similarity index 100% rename from test/create-flows/unit_fixed_connections.mlir rename to test/create-flows/fixed_connections.mlir diff --git a/test/create-flows/flow_test_1.mlir b/test/create-flows/flow_test_1.mlir index 6d3b4731b9..aaee47bcb3 100644 --- a/test/create-flows/flow_test_1.mlir +++ b/test/create-flows/flow_test_1.mlir @@ -8,50 +8,54 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -//CHECK: %[[t20:.*]] = aie.tile(2, 0) -//CHECK: %[[t30:.*]] = aie.tile(3, 0) -//CHECK: %[[t34:.*]] = aie.tile(3, 4) -//CHECK: %[[t43:.*]] = aie.tile(4, 3) -//CHECK: %[[t44:.*]] = aie.tile(4, 4) -//CHECK: %[[t54:.*]] = aie.tile(5, 4) -//CHECK: %[[t60:.*]] = aie.tile(6, 0) -//CHECK: %[[t63:.*]] = aie.tile(6, 3) -//CHECK: %[[t70:.*]] = aie.tile(7, 0) -//CHECK: %[[t72:.*]] = aie.tile(7, 2) -//CHECK: %[[t83:.*]] = aie.tile(8, 3) -//CHECK: %[[t84:.*]] = aie.tile(8, 4) - -// CHECK: aie.flow(%[[t20]], DMA : 0, %[[t63]], DMA : 0) -// CHECK: aie.flow(%[[t20]], DMA : 1, %[[t83]], DMA : 0) -// CHECK: aie.flow(%[[t30]], DMA : 0, %[[t72]], DMA : 0) -// CHECK: aie.flow(%[[t30]], DMA : 1, %[[t54]], DMA : 0) - -// CHECK: aie.flow(%[[t34]], Core : 0, %[[t63]], Core : 1) -// CHECK: aie.flow(%[[t34]], DMA : 1, %[[t70]], DMA : 0) -// CHECK: aie.flow(%[[t43]], Core : 0, %[[t84]], Core : 1) -// CHECK: aie.flow(%[[t43]], DMA : 1, %[[t60]], DMA : 1) - -// CHECK: aie.flow(%[[t44]], Core : 0, %[[t54]], Core : 1) -// CHECK: aie.flow(%[[t44]], DMA : 1, %[[t60]], DMA : 0) -// CHECK: aie.flow(%[[t54]], Core : 0, %[[t43]], Core : 1) -// CHECK: aie.flow(%[[t54]], DMA : 1, %[[t30]], DMA : 1) - -// CHECK: aie.flow(%[[t60]], DMA : 0, %[[t44]], DMA : 0) -// CHECK: aie.flow(%[[t60]], DMA : 1, %[[t43]], DMA : 0) -// CHECK: aie.flow(%[[t63]], Core : 0, %[[t34]], Core : 1) -// CHECK: aie.flow(%[[t63]], DMA : 1, %[[t20]], DMA : 1) - -// CHECK: aie.flow(%[[t70]], DMA : 0, %[[t34]], DMA : 0) -// CHECK: aie.flow(%[[t70]], DMA : 1, %[[t84]], DMA : 0) -// CHECK: aie.flow(%[[t72]], Core : 0, %[[t83]], Core : 1) -// CHECK: aie.flow(%[[t72]], DMA : 1, %[[t30]], DMA : 0) - -// CHECK: aie.flow(%[[t83]], Core : 0, %[[t44]], Core : 1) -// CHECK: aie.flow(%[[t83]], DMA : 1, %[[t20]], DMA : 0) -// CHECK: aie.flow(%[[t84]], Core : 0, %[[t72]], Core : 1) -// CHECK: aie.flow(%[[t84]], DMA : 1, %[[t70]], DMA : 1) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 +// CHECK1: %[[t20:.*]] = aie.tile(2, 0) +// CHECK1: %[[t30:.*]] = aie.tile(3, 0) +// CHECK1: %[[t34:.*]] = aie.tile(3, 4) +// CHECK1: %[[t43:.*]] = aie.tile(4, 3) +// CHECK1: %[[t44:.*]] = aie.tile(4, 4) +// CHECK1: %[[t54:.*]] = aie.tile(5, 4) +// CHECK1: %[[t60:.*]] = aie.tile(6, 0) +// CHECK1: %[[t63:.*]] = aie.tile(6, 3) +// CHECK1: %[[t70:.*]] = aie.tile(7, 0) +// CHECK1: %[[t72:.*]] = aie.tile(7, 2) +// CHECK1: %[[t83:.*]] = aie.tile(8, 3) +// CHECK1: %[[t84:.*]] = aie.tile(8, 4) + +// CHECK1: aie.flow(%[[t20]], DMA : 0, %[[t63]], DMA : 0) +// CHECK1: aie.flow(%[[t20]], DMA : 1, %[[t83]], DMA : 0) +// CHECK1: aie.flow(%[[t30]], DMA : 0, %[[t72]], DMA : 0) +// CHECK1: aie.flow(%[[t30]], DMA : 1, %[[t54]], DMA : 0) + +// CHECK1: aie.flow(%[[t34]], Core : 0, %[[t63]], Core : 1) +// CHECK1: aie.flow(%[[t34]], DMA : 1, %[[t70]], DMA : 0) +// CHECK1: aie.flow(%[[t43]], Core : 0, %[[t84]], Core : 1) +// CHECK1: aie.flow(%[[t43]], DMA : 1, %[[t60]], DMA : 1) + +// CHECK1: aie.flow(%[[t44]], Core : 0, %[[t54]], Core : 1) +// CHECK1: aie.flow(%[[t44]], DMA : 1, %[[t60]], DMA : 0) +// CHECK1: aie.flow(%[[t54]], Core : 0, %[[t43]], Core : 1) +// CHECK1: aie.flow(%[[t54]], DMA : 1, %[[t30]], DMA : 1) + +// CHECK1: aie.flow(%[[t60]], DMA : 0, %[[t44]], DMA : 0) +// CHECK1: aie.flow(%[[t60]], DMA : 1, %[[t43]], DMA : 0) +// CHECK1: aie.flow(%[[t63]], Core : 0, %[[t34]], Core : 1) +// CHECK1: aie.flow(%[[t63]], DMA : 1, %[[t20]], DMA : 1) + +// CHECK1: aie.flow(%[[t70]], DMA : 0, %[[t34]], DMA : 0) +// CHECK1: aie.flow(%[[t70]], DMA : 1, %[[t84]], DMA : 0) +// CHECK1: aie.flow(%[[t72]], Core : 0, %[[t83]], Core : 1) +// CHECK1: aie.flow(%[[t72]], DMA : 1, %[[t30]], DMA : 0) + +// CHECK1: aie.flow(%[[t83]], Core : 0, %[[t44]], Core : 1) +// CHECK1: aie.flow(%[[t83]], DMA : 1, %[[t20]], DMA : 0) +// CHECK1: aie.flow(%[[t84]], Core : 0, %[[t72]], Core : 1) +// CHECK1: aie.flow(%[[t84]], DMA : 1, %[[t70]], DMA : 1) + +// CHECK2: "total_path_length": 130 module { aie.device(xcvc1902) { diff --git a/test/create-flows/flow_test_2.mlir b/test/create-flows/flow_test_2.mlir index 33f6944a73..89a3e3c7e8 100644 --- a/test/create-flows/flow_test_2.mlir +++ b/test/create-flows/flow_test_2.mlir @@ -8,49 +8,54 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -//CHECK: %[[t01:.*]] = aie.tile(0, 1) -//CHECK: %[[t02:.*]] = aie.tile(0, 2) -//CHECK: %[[t03:.*]] = aie.tile(0, 3) -//CHECK: %[[t04:.*]] = aie.tile(0, 4) -//CHECK: %[[t11:.*]] = aie.tile(1, 1) -//CHECK: %[[t12:.*]] = aie.tile(1, 2) -//CHECK: %[[t13:.*]] = aie.tile(1, 3) -//CHECK: %[[t14:.*]] = aie.tile(1, 4) -//CHECK: %[[t20:.*]] = aie.tile(2, 0) -//CHECK: %[[t21:.*]] = aie.tile(2, 1) -//CHECK: %[[t22:.*]] = aie.tile(2, 2) -//CHECK: %[[t23:.*]] = aie.tile(2, 3) -//CHECK: %[[t24:.*]] = aie.tile(2, 4) -//CHECK: %[[t30:.*]] = aie.tile(3, 0) -//CHECK: %[[t31:.*]] = aie.tile(3, 1) -//CHECK: %[[t32:.*]] = aie.tile(3, 2) -//CHECK: %[[t33:.*]] = aie.tile(3, 3) -//CHECK: %[[t34:.*]] = aie.tile(3, 4) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 -//CHECK: aie.flow(%[[t01]], Core : 0, %[[t12]], Core : 0) -//CHECK: aie.flow(%[[t02]], DMA : 0, %[[t20]], DMA : 0) -//CHECK: aie.flow(%[[t04]], Core : 0, %[[t13]], Core : 0) -//CHECK: aie.flow(%[[t11]], Core : 0, %[[t01]], Core : 0) -//CHECK: aie.flow(%[[t12]], Core : 0, %[[t02]], Core : 0) -//CHECK: aie.flow(%[[t13]], DMA : 0, %[[t20]], DMA : 1) -//CHECK: aie.flow(%[[t14]], Core : 0, %[[t04]], Core : 0) -//CHECK: aie.flow(%[[t20]], DMA : 0, %[[t11]], DMA : 0) -//CHECK: aie.flow(%[[t20]], DMA : 1, %[[t14]], DMA : 0) -//CHECK: aie.flow(%[[t21]], Core : 0, %[[t33]], Core : 0) -//CHECK: aie.flow(%[[t22]], Core : 0, %[[t34]], Core : 0) -//CHECK: aie.flow(%[[t23]], Core : 1, %[[t34]], Core : 1) -//CHECK: aie.flow(%[[t23]], DMA : 0, %[[t30]], DMA : 0) -//CHECK: aie.flow(%[[t24]], Core : 0, %[[t23]], Core : 0) -//CHECK: aie.flow(%[[t24]], Core : 1, %[[t33]], Core : 1) -//CHECK: aie.flow(%[[t30]], DMA : 0, %[[t21]], DMA : 0) -//CHECK: aie.flow(%[[t30]], DMA : 1, %[[t31]], DMA : 1) -//CHECK: aie.flow(%[[t31]], Core : 1, %[[t23]], Core : 1) -//CHECK: aie.flow(%[[t32]], DMA : 1, %[[t30]], DMA : 1) -//CHECK: aie.flow(%[[t33]], Core : 0, %[[t22]], Core : 0) -//CHECK: aie.flow(%[[t33]], Core : 1, %[[t32]], Core : 1) -//CHECK: aie.flow(%[[t34]], Core : 0, %[[t24]], Core : 0) -//CHECK: aie.flow(%[[t34]], Core : 1, %[[t24]], Core : 1) +// CHECK1: %[[t01:.*]] = aie.tile(0, 1) +// CHECK1: %[[t02:.*]] = aie.tile(0, 2) +// CHECK1: %[[t03:.*]] = aie.tile(0, 3) +// CHECK1: %[[t04:.*]] = aie.tile(0, 4) +// CHECK1: %[[t11:.*]] = aie.tile(1, 1) +// CHECK1: %[[t12:.*]] = aie.tile(1, 2) +// CHECK1: %[[t13:.*]] = aie.tile(1, 3) +// CHECK1: %[[t14:.*]] = aie.tile(1, 4) +// CHECK1: %[[t20:.*]] = aie.tile(2, 0) +// CHECK1: %[[t21:.*]] = aie.tile(2, 1) +// CHECK1: %[[t22:.*]] = aie.tile(2, 2) +// CHECK1: %[[t23:.*]] = aie.tile(2, 3) +// CHECK1: %[[t24:.*]] = aie.tile(2, 4) +// CHECK1: %[[t30:.*]] = aie.tile(3, 0) +// CHECK1: %[[t31:.*]] = aie.tile(3, 1) +// CHECK1: %[[t32:.*]] = aie.tile(3, 2) +// CHECK1: %[[t33:.*]] = aie.tile(3, 3) +// CHECK1: %[[t34:.*]] = aie.tile(3, 4) + +// CHECK1: aie.flow(%[[t01]], Core : 0, %[[t12]], Core : 0) +// CHECK1: aie.flow(%[[t02]], DMA : 0, %[[t20]], DMA : 0) +// CHECK1: aie.flow(%[[t04]], Core : 0, %[[t13]], Core : 0) +// CHECK1: aie.flow(%[[t11]], Core : 0, %[[t01]], Core : 0) +// CHECK1: aie.flow(%[[t12]], Core : 0, %[[t02]], Core : 0) +// CHECK1: aie.flow(%[[t13]], DMA : 0, %[[t20]], DMA : 1) +// CHECK1: aie.flow(%[[t14]], Core : 0, %[[t04]], Core : 0) +// CHECK1: aie.flow(%[[t20]], DMA : 0, %[[t11]], DMA : 0) +// CHECK1: aie.flow(%[[t20]], DMA : 1, %[[t14]], DMA : 0) +// CHECK1: aie.flow(%[[t21]], Core : 0, %[[t33]], Core : 0) +// CHECK1: aie.flow(%[[t22]], Core : 0, %[[t34]], Core : 0) +// CHECK1: aie.flow(%[[t23]], Core : 1, %[[t34]], Core : 1) +// CHECK1: aie.flow(%[[t23]], DMA : 0, %[[t30]], DMA : 0) +// CHECK1: aie.flow(%[[t24]], Core : 0, %[[t23]], Core : 0) +// CHECK1: aie.flow(%[[t24]], Core : 1, %[[t33]], Core : 1) +// CHECK1: aie.flow(%[[t30]], DMA : 0, %[[t21]], DMA : 0) +// CHECK1: aie.flow(%[[t30]], DMA : 1, %[[t31]], DMA : 1) +// CHECK1: aie.flow(%[[t31]], Core : 1, %[[t23]], Core : 1) +// CHECK1: aie.flow(%[[t32]], DMA : 1, %[[t30]], DMA : 1) +// CHECK1: aie.flow(%[[t33]], Core : 0, %[[t22]], Core : 0) +// CHECK1: aie.flow(%[[t33]], Core : 1, %[[t32]], Core : 1) +// CHECK1: aie.flow(%[[t34]], Core : 0, %[[t24]], Core : 0) +// CHECK1: aie.flow(%[[t34]], Core : 1, %[[t24]], Core : 1) + +// CHECK2: "total_path_length": 50 module { aie.device(xcvc1902) { diff --git a/test/create-flows/flow_test_3.mlir b/test/create-flows/flow_test_3.mlir index f9a159aedc..8db460d144 100644 --- a/test/create-flows/flow_test_3.mlir +++ b/test/create-flows/flow_test_3.mlir @@ -8,51 +8,56 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -//CHECK: %[[t01:.*]] = aie.tile(0, 1) -//CHECK: %[[t02:.*]] = aie.tile(0, 2) -//CHECK: %[[t03:.*]] = aie.tile(0, 3) -//CHECK: %[[t04:.*]] = aie.tile(0, 4) -//CHECK: %[[t11:.*]] = aie.tile(1, 1) -//CHECK: %[[t12:.*]] = aie.tile(1, 2) -//CHECK: %[[t13:.*]] = aie.tile(1, 3) -//CHECK: %[[t14:.*]] = aie.tile(1, 4) -//CHECK: %[[t20:.*]] = aie.tile(2, 0) -//CHECK: %[[t21:.*]] = aie.tile(2, 1) -//CHECK: %[[t22:.*]] = aie.tile(2, 2) -//CHECK: %[[t23:.*]] = aie.tile(2, 3) -//CHECK: %[[t24:.*]] = aie.tile(2, 4) -//CHECK: %[[t30:.*]] = aie.tile(3, 0) -//CHECK: %[[t71:.*]] = aie.tile(7, 1) -//CHECK: %[[t72:.*]] = aie.tile(7, 2) -//CHECK: %[[t73:.*]] = aie.tile(7, 3) -//CHECK: %[[t74:.*]] = aie.tile(7, 4) -//CHECK: %[[t81:.*]] = aie.tile(8, 1) -//CHECK: %[[t82:.*]] = aie.tile(8, 2) -//CHECK: %[[t83:.*]] = aie.tile(8, 3) -//CHECK: %[[t84:.*]] = aie.tile(8, 4) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 -//CHECK: aie.flow(%[[t01]], Core : 0, %[[t83]], Core : 0) -//CHECK: aie.flow(%[[t01]], Core : 1, %[[t72]], Core : 1) -//CHECK: aie.flow(%[[t02]], Core : 1, %[[t24]], Core : 1) -//CHECK: aie.flow(%[[t03]], Core : 0, %[[t71]], Core : 0) -//CHECK: aie.flow(%[[t11]], Core : 0, %[[t24]], Core : 0) -//CHECK: aie.flow(%[[t14]], Core : 0, %[[t01]], Core : 0) -//CHECK: aie.flow(%[[t20]], DMA : 0, %[[t03]], DMA : 0) -//CHECK: aie.flow(%[[t20]], DMA : 1, %[[t83]], DMA : 1) -//CHECK: aie.flow(%[[t21]], Core : 0, %[[t73]], Core : 0) -//CHECK: aie.flow(%[[t24]], Core : 1, %[[t71]], Core : 1) -//CHECK: aie.flow(%[[t24]], DMA : 0, %[[t20]], DMA : 0) -//CHECK: aie.flow(%[[t30]], DMA : 0, %[[t14]], DMA : 0) -//CHECK: aie.flow(%[[t71]], Core : 0, %[[t84]], Core : 0) -//CHECK: aie.flow(%[[t71]], Core : 1, %[[t84]], Core : 1) -//CHECK: aie.flow(%[[t72]], Core : 1, %[[t02]], Core : 1) -//CHECK: aie.flow(%[[t73]], Core : 0, %[[t82]], Core : 0) -//CHECK: aie.flow(%[[t82]], DMA : 0, %[[t30]], DMA : 0) -//CHECK: aie.flow(%[[t83]], Core : 0, %[[t21]], Core : 0) -//CHECK: aie.flow(%[[t83]], Core : 1, %[[t01]], Core : 1) -//CHECK: aie.flow(%[[t84]], Core : 0, %[[t11]], Core : 0) -//CHECK: aie.flow(%[[t84]], DMA : 1, %[[t20]], DMA : 1) +// CHECK1: %[[t01:.*]] = aie.tile(0, 1) +// CHECK1: %[[t02:.*]] = aie.tile(0, 2) +// CHECK1: %[[t03:.*]] = aie.tile(0, 3) +// CHECK1: %[[t04:.*]] = aie.tile(0, 4) +// CHECK1: %[[t11:.*]] = aie.tile(1, 1) +// CHECK1: %[[t12:.*]] = aie.tile(1, 2) +// CHECK1: %[[t13:.*]] = aie.tile(1, 3) +// CHECK1: %[[t14:.*]] = aie.tile(1, 4) +// CHECK1: %[[t20:.*]] = aie.tile(2, 0) +// CHECK1: %[[t21:.*]] = aie.tile(2, 1) +// CHECK1: %[[t22:.*]] = aie.tile(2, 2) +// CHECK1: %[[t23:.*]] = aie.tile(2, 3) +// CHECK1: %[[t24:.*]] = aie.tile(2, 4) +// CHECK1: %[[t30:.*]] = aie.tile(3, 0) +// CHECK1: %[[t71:.*]] = aie.tile(7, 1) +// CHECK1: %[[t72:.*]] = aie.tile(7, 2) +// CHECK1: %[[t73:.*]] = aie.tile(7, 3) +// CHECK1: %[[t74:.*]] = aie.tile(7, 4) +// CHECK1: %[[t81:.*]] = aie.tile(8, 1) +// CHECK1: %[[t82:.*]] = aie.tile(8, 2) +// CHECK1: %[[t83:.*]] = aie.tile(8, 3) +// CHECK1: %[[t84:.*]] = aie.tile(8, 4) + +// CHECK1: aie.flow(%[[t01]], Core : 0, %[[t83]], Core : 0) +// CHECK1: aie.flow(%[[t01]], Core : 1, %[[t72]], Core : 1) +// CHECK1: aie.flow(%[[t02]], Core : 1, %[[t24]], Core : 1) +// CHECK1: aie.flow(%[[t03]], Core : 0, %[[t71]], Core : 0) +// CHECK1: aie.flow(%[[t11]], Core : 0, %[[t24]], Core : 0) +// CHECK1: aie.flow(%[[t14]], Core : 0, %[[t01]], Core : 0) +// CHECK1: aie.flow(%[[t20]], DMA : 0, %[[t03]], DMA : 0) +// CHECK1: aie.flow(%[[t20]], DMA : 1, %[[t83]], DMA : 1) +// CHECK1: aie.flow(%[[t21]], Core : 0, %[[t73]], Core : 0) +// CHECK1: aie.flow(%[[t24]], Core : 1, %[[t71]], Core : 1) +// CHECK1: aie.flow(%[[t24]], DMA : 0, %[[t20]], DMA : 0) +// CHECK1: aie.flow(%[[t30]], DMA : 0, %[[t14]], DMA : 0) +// CHECK1: aie.flow(%[[t71]], Core : 0, %[[t84]], Core : 0) +// CHECK1: aie.flow(%[[t71]], Core : 1, %[[t84]], Core : 1) +// CHECK1: aie.flow(%[[t72]], Core : 1, %[[t02]], Core : 1) +// CHECK1: aie.flow(%[[t73]], Core : 0, %[[t82]], Core : 0) +// CHECK1: aie.flow(%[[t82]], DMA : 0, %[[t30]], DMA : 0) +// CHECK1: aie.flow(%[[t83]], Core : 0, %[[t21]], Core : 0) +// CHECK1: aie.flow(%[[t83]], Core : 1, %[[t01]], Core : 1) +// CHECK1: aie.flow(%[[t84]], Core : 0, %[[t11]], Core : 0) +// CHECK1: aie.flow(%[[t84]], DMA : 1, %[[t20]], DMA : 1) + +// CHECK2: "total_path_length": 140 module { aie.device(xcvc1902) { diff --git a/test/create-flows/keep_flow_op.mlir b/test/create-flows/keep_flow_op.mlir deleted file mode 100644 index 7845759c7f..0000000000 --- a/test/create-flows/keep_flow_op.mlir +++ /dev/null @@ -1,31 +0,0 @@ -//===- keep_flow_op.mlir ----------------------------------*- MLIR -*-===// -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// SPDX-License-Identifier: MIT -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows='keep-flow-op=true' %s | FileCheck %s -// CHECK: module -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.flow(%[[T20:.*]], DMA : 0, %[[T30:.*]], DMA : 1) -module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - aie.flow(%t20, DMA : 0, %t30, DMA : 1) - } -} diff --git a/test/create-flows/many_flows.mlir b/test/create-flows/many_flows.mlir index 82f16679bb..dbe9eee550 100644 --- a/test/create-flows/many_flows.mlir +++ b/test/create-flows/many_flows.mlir @@ -8,32 +8,37 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T11:.*]] = aie.tile(1, 1) -// CHECK: %[[T13:.*]] = aie.tile(1, 3) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T31:.*]] = aie.tile(3, 1) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T73:.*]] = aie.tile(7, 3) -// CHECK: aie.flow(%[[T02]], Core : 1, %[[T22]], Core : 1) -// CHECK: aie.flow(%[[T02]], DMA : 0, %[[T60]], DMA : 0) -// CHECK: aie.flow(%[[T03]], Core : 0, %[[T13]], Core : 0) -// CHECK: aie.flow(%[[T03]], Core : 1, %[[T02]], Core : 0) -// CHECK: aie.flow(%[[T03]], DMA : 0, %[[T70]], DMA : 0) -// CHECK: aie.flow(%[[T13]], Core : 1, %[[T22]], Core : 0) -// CHECK: aie.flow(%[[T13]], DMA : 0, %[[T70]], DMA : 1) -// CHECK: aie.flow(%[[T22]], DMA : 0, %[[T60]], DMA : 1) -// CHECK: aie.flow(%[[T31]], DMA : 0, %[[T20]], DMA : 1) -// CHECK: aie.flow(%[[T31]], DMA : 1, %[[T30]], DMA : 1) -// CHECK: aie.flow(%[[T73]], Core : 0, %[[T31]], Core : 0) -// CHECK: aie.flow(%[[T73]], Core : 1, %[[T31]], Core : 1) -// CHECK: aie.flow(%[[T73]], DMA : 0, %[[T20]], DMA : 0) -// CHECK: aie.flow(%[[T73]], DMA : 1, %[[T30]], DMA : 0) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T11:.*]] = aie.tile(1, 1) +// CHECK1: %[[T13:.*]] = aie.tile(1, 3) +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T31:.*]] = aie.tile(3, 1) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T73:.*]] = aie.tile(7, 3) +// CHECK1: aie.flow(%[[T02]], Core : 1, %[[T22]], Core : 1) +// CHECK1: aie.flow(%[[T02]], DMA : 0, %[[T60]], DMA : 0) +// CHECK1: aie.flow(%[[T03]], Core : 0, %[[T13]], Core : 0) +// CHECK1: aie.flow(%[[T03]], Core : 1, %[[T02]], Core : 0) +// CHECK1: aie.flow(%[[T03]], DMA : 0, %[[T70]], DMA : 0) +// CHECK1: aie.flow(%[[T13]], Core : 1, %[[T22]], Core : 0) +// CHECK1: aie.flow(%[[T13]], DMA : 0, %[[T70]], DMA : 1) +// CHECK1: aie.flow(%[[T22]], DMA : 0, %[[T60]], DMA : 1) +// CHECK1: aie.flow(%[[T31]], DMA : 0, %[[T20]], DMA : 1) +// CHECK1: aie.flow(%[[T31]], DMA : 1, %[[T30]], DMA : 1) +// CHECK1: aie.flow(%[[T73]], Core : 0, %[[T31]], Core : 0) +// CHECK1: aie.flow(%[[T73]], Core : 1, %[[T31]], Core : 1) +// CHECK1: aie.flow(%[[T73]], DMA : 0, %[[T20]], DMA : 0) +// CHECK1: aie.flow(%[[T73]], DMA : 1, %[[T30]], DMA : 0) + +// CHECK2: "total_path_length": 69 module { aie.device(xcvc1902) { diff --git a/test/create-flows/many_flows2.mlir b/test/create-flows/many_flows2.mlir index 85df663dad..b87d39a74e 100644 --- a/test/create-flows/many_flows2.mlir +++ b/test/create-flows/many_flows2.mlir @@ -8,33 +8,38 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T11:.*]] = aie.tile(1, 1) -// CHECK: %[[T13:.*]] = aie.tile(1, 3) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T31:.*]] = aie.tile(3, 1) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T73:.*]] = aie.tile(7, 3) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T11:.*]] = aie.tile(1, 1) +// CHECK1: %[[T13:.*]] = aie.tile(1, 3) +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T31:.*]] = aie.tile(3, 1) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T73:.*]] = aie.tile(7, 3) // -// CHECK: aie.flow(%[[T02]], DMA : 0, %[[T60]], DMA : 0) -// CHECK: aie.flow(%[[T03]], Core : 0, %[[T02]], Core : 1) -// CHECK: aie.flow(%[[T03]], Core : 1, %[[T02]], Core : 0) -// CHECK: aie.flow(%[[T03]], DMA : 0, %[[T30]], DMA : 0) -// CHECK: aie.flow(%[[T03]], DMA : 1, %[[T70]], DMA : 1) -// CHECK: aie.flow(%[[T13]], Core : 1, %[[T31]], Core : 1) -// CHECK: aie.flow(%[[T22]], Core : 0, %[[T13]], Core : 0) -// CHECK: aie.flow(%[[T22]], DMA : 0, %[[T20]], DMA : 0) -// CHECK: aie.flow(%[[T31]], DMA : 0, %[[T20]], DMA : 1) -// CHECK: aie.flow(%[[T31]], DMA : 1, %[[T30]], DMA : 1) -// CHECK: aie.flow(%[[T73]], Core : 0, %[[T31]], Core : 0) -// CHECK: aie.flow(%[[T73]], Core : 1, %[[T22]], Core : 1) -// CHECK: aie.flow(%[[T73]], DMA : 0, %[[T60]], DMA : 1) -// CHECK: aie.flow(%[[T73]], DMA : 1, %[[T70]], DMA : 0) +// CHECK1: aie.flow(%[[T02]], DMA : 0, %[[T60]], DMA : 0) +// CHECK1: aie.flow(%[[T03]], Core : 0, %[[T02]], Core : 1) +// CHECK1: aie.flow(%[[T03]], Core : 1, %[[T02]], Core : 0) +// CHECK1: aie.flow(%[[T03]], DMA : 0, %[[T30]], DMA : 0) +// CHECK1: aie.flow(%[[T03]], DMA : 1, %[[T70]], DMA : 1) +// CHECK1: aie.flow(%[[T13]], Core : 1, %[[T31]], Core : 1) +// CHECK1: aie.flow(%[[T22]], Core : 0, %[[T13]], Core : 0) +// CHECK1: aie.flow(%[[T22]], DMA : 0, %[[T20]], DMA : 0) +// CHECK1: aie.flow(%[[T31]], DMA : 0, %[[T20]], DMA : 1) +// CHECK1: aie.flow(%[[T31]], DMA : 1, %[[T30]], DMA : 1) +// CHECK1: aie.flow(%[[T73]], Core : 0, %[[T31]], Core : 0) +// CHECK1: aie.flow(%[[T73]], Core : 1, %[[T22]], Core : 1) +// CHECK1: aie.flow(%[[T73]], DMA : 0, %[[T60]], DMA : 1) +// CHECK1: aie.flow(%[[T73]], DMA : 1, %[[T70]], DMA : 0) + +// CHECK2: "total_path_length": 56 module { aie.device(xcvc1902) { diff --git a/test/create-flows/maxiter_err_test.mlir b/test/create-flows/maxiter_err_test.mlir index 57303f5d69..2cd54af3b1 100644 --- a/test/create-flows/maxiter_err_test.mlir +++ b/test/create-flows/maxiter_err_test.mlir @@ -8,6 +8,9 @@ // //===----------------------------------------------------------------------===// +// This test is known to timeout after the refactor of the pathfinder +// REQUIRES: zhewen + // RUN: not aie-opt --aie-create-pathfinder-flows --aie-find-flows %s 2>&1 | FileCheck %s // CHECK: error: Unable to find a legal routing diff --git a/test/create-flows/memtile.mlir b/test/create-flows/memtile.mlir index b26398cbad..a3d191ca9c 100644 --- a/test/create-flows/memtile.mlir +++ b/test/create-flows/memtile.mlir @@ -8,24 +8,29 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T04:.*]] = aie.tile(0, 4) -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T01:.*]] = aie.tile(0, 1) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T04:.*]] = aie.tile(0, 4) +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: %[[T01:.*]] = aie.tile(0, 1) // -// CHECK: aie.flow(%[[T04]], DMA : 0, %[[T02]], DMA : 4) -// CHECK: aie.flow(%[[T04]], DMA : 1, %[[T02]], DMA : 5) -// CHECK: aie.flow(%[[T03]], DMA : 0, %[[T02]], DMA : 2) -// CHECK: aie.flow(%[[T03]], DMA : 1, %[[T02]], DMA : 3) -// CHECK: aie.flow(%[[T02]], DMA : 0, %[[T01]], DMA : 0) -// CHECK: aie.flow(%[[T02]], DMA : 1, %[[T01]], DMA : 1) -// CHECK: aie.flow(%[[T02]], DMA : 2, %[[T03]], DMA : 0) -// CHECK: aie.flow(%[[T02]], DMA : 3, %[[T03]], DMA : 1) -// CHECK: aie.flow(%[[T02]], DMA : 4, %[[T04]], DMA : 0) -// CHECK: aie.flow(%[[T02]], DMA : 5, %[[T04]], DMA : 1) -// CHECK: aie.flow(%[[T01]], DMA : 0, %[[T02]], DMA : 0) -// CHECK: aie.flow(%[[T01]], DMA : 1, %[[T02]], DMA : 1) +// CHECK1: aie.flow(%[[T04]], DMA : 0, %[[T02]], DMA : 4) +// CHECK1: aie.flow(%[[T04]], DMA : 1, %[[T02]], DMA : 5) +// CHECK1: aie.flow(%[[T03]], DMA : 0, %[[T02]], DMA : 2) +// CHECK1: aie.flow(%[[T03]], DMA : 1, %[[T02]], DMA : 3) +// CHECK1: aie.flow(%[[T02]], DMA : 0, %[[T01]], DMA : 0) +// CHECK1: aie.flow(%[[T02]], DMA : 1, %[[T01]], DMA : 1) +// CHECK1: aie.flow(%[[T02]], DMA : 2, %[[T03]], DMA : 0) +// CHECK1: aie.flow(%[[T02]], DMA : 3, %[[T03]], DMA : 1) +// CHECK1: aie.flow(%[[T02]], DMA : 4, %[[T04]], DMA : 0) +// CHECK1: aie.flow(%[[T02]], DMA : 5, %[[T04]], DMA : 1) +// CHECK1: aie.flow(%[[T01]], DMA : 0, %[[T02]], DMA : 0) +// CHECK1: aie.flow(%[[T01]], DMA : 1, %[[T02]], DMA : 1) + +// CHECK2: "total_path_length": 16 module { aie.device(xcve2802) { diff --git a/test/create-flows/memtile_routing_constraints.mlir b/test/create-flows/memtile_routing_constraints.mlir index 12f50b74ca..877ed2c935 100644 --- a/test/create-flows/memtile_routing_constraints.mlir +++ b/test/create-flows/memtile_routing_constraints.mlir @@ -8,15 +8,19 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 -// CHECK: %[[T24:.*]] = aie.tile(2, 4) -// CHECK: %[[T23:.*]] = aie.tile(2, 3) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T21:.*]] = aie.tile(2, 1) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: aie.flow(%[[T23]], DMA : 0, %[[T20]], DMA : 0) -// CHECK: aie.flow(%[[T22]], DMA : 0, %[[T21]], DMA : 0) +// CHECK1: %[[T24:.*]] = aie.tile(2, 4) +// CHECK1: %[[T23:.*]] = aie.tile(2, 3) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T21:.*]] = aie.tile(2, 1) +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: aie.flow(%[[T23]], DMA : 0, %[[T20]], DMA : 0) +// CHECK1: aie.flow(%[[T22]], DMA : 0, %[[T21]], DMA : 0) + +// CHECK2: "total_path_length": 4 module { aie.device(xcve2802) { diff --git a/test/create-flows/mmult.mlir b/test/create-flows/mmult.mlir index e74232077b..0e1c2b3a6b 100644 --- a/test/create-flows/mmult.mlir +++ b/test/create-flows/mmult.mlir @@ -8,30 +8,33 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 -// CHECK: %[[T1:.*]] = aie.tile(7, 0) -// CHECK: %[[T3:.*]] = aie.tile(8, 3) -// CHECK: %[[T15:.*]] = aie.tile(6, 0) -// CHECK: %[[T17:.*]] = aie.tile(7, 3) -// CHECK: %[[T29:.*]] = aie.tile(3, 0) -// CHECK: %[[T31:.*]] = aie.tile(8, 2) -// CHECK: %[[T43:.*]] = aie.tile(2, 0) -// CHECK: %[[T45:.*]] = aie.tile(7, 2) +// CHECK1: %[[T1:.*]] = aie.tile(7, 0) +// CHECK1: %[[T3:.*]] = aie.tile(8, 3) +// CHECK1: %[[T15:.*]] = aie.tile(6, 0) +// CHECK1: %[[T17:.*]] = aie.tile(7, 3) +// CHECK1: %[[T29:.*]] = aie.tile(3, 0) +// CHECK1: %[[T31:.*]] = aie.tile(8, 2) +// CHECK1: %[[T43:.*]] = aie.tile(2, 0) +// CHECK1: %[[T45:.*]] = aie.tile(7, 2) // -// CHECK: aie.flow(%[[T1]], DMA : 0, %[[T3]], DMA : 0) -// CHECK: aie.flow(%[[T1]], DMA : 1, %[[T3]], DMA : 1) -// CHECK: aie.flow(%[[T3]], DMA : 0, %[[T29]], DMA : 1) -// CHECK: aie.flow(%[[T15]], DMA : 0, %[[T17]], DMA : 0) -// CHECK: aie.flow(%[[T15]], DMA : 1, %[[T17]], DMA : 1) -// CHECK: aie.flow(%[[T17]], DMA : 0, %[[T29]], DMA : 0) -// CHECK: aie.flow(%[[T29]], DMA : 0, %[[T31]], DMA : 0) -// CHECK: aie.flow(%[[T29]], DMA : 1, %[[T31]], DMA : 1) -// CHECK: aie.flow(%[[T31]], DMA : 0, %[[T43]], DMA : 1) -// CHECK: aie.flow(%[[T43]], DMA : 0, %[[T45]], DMA : 0) -// CHECK: aie.flow(%[[T43]], DMA : 1, %[[T45]], DMA : 1) -// CHECK: aie.flow(%[[T45]], DMA : 0, %[[T43]], DMA : 0) +// CHECK1: aie.flow(%[[T1]], DMA : 0, %[[T3]], DMA : 0) +// CHECK1: aie.flow(%[[T1]], DMA : 1, %[[T3]], DMA : 1) +// CHECK1: aie.flow(%[[T3]], DMA : 0, %[[T29]], DMA : 1) +// CHECK1: aie.flow(%[[T15]], DMA : 0, %[[T17]], DMA : 0) +// CHECK1: aie.flow(%[[T15]], DMA : 1, %[[T17]], DMA : 1) +// CHECK1: aie.flow(%[[T17]], DMA : 0, %[[T29]], DMA : 0) +// CHECK1: aie.flow(%[[T29]], DMA : 0, %[[T31]], DMA : 0) +// CHECK1: aie.flow(%[[T29]], DMA : 1, %[[T31]], DMA : 1) +// CHECK1: aie.flow(%[[T31]], DMA : 0, %[[T43]], DMA : 1) +// CHECK1: aie.flow(%[[T43]], DMA : 0, %[[T45]], DMA : 0) +// CHECK1: aie.flow(%[[T43]], DMA : 1, %[[T45]], DMA : 1) +// CHECK1: aie.flow(%[[T45]], DMA : 0, %[[T43]], DMA : 0) +// CHECK2: "total_path_length": 74 module @aie.herd_0 { aie.device(xcvc1902) { diff --git a/test/create-flows/more_flows_shim.mlir b/test/create-flows/more_flows_shim.mlir index 3e25b09a70..aa08af3e21 100644 --- a/test/create-flows/more_flows_shim.mlir +++ b/test/create-flows/more_flows_shim.mlir @@ -12,7 +12,7 @@ // These tests verify pathfinder routing flows to/from PLIO in shim tiles. // -// RUN: aie-opt --split-input-file --aie-create-pathfinder-flows -split-input-file %s | FileCheck %s +// RUN: aie-opt --split-input-file --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: test70 // CHECK: %[[T70:.*]] = aie.tile(7, 0) diff --git a/test/create-flows/over_flows.mlir b/test/create-flows/over_flows.mlir index 465c50858f..75cf4e3326 100644 --- a/test/create-flows/over_flows.mlir +++ b/test/create-flows/over_flows.mlir @@ -8,34 +8,39 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T00:.*]] = aie.tile(0, 0) -// CHECK: %[[T13:.*]] = aie.tile(1, 3) -// CHECK: %[[T11:.*]] = aie.tile(1, 1) -// CHECK: %[[T10:.*]] = aie.tile(1, 0) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T31:.*]] = aie.tile(3, 1) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T71:.*]] = aie.tile(7, 1) -// CHECK: %[[T72:.*]] = aie.tile(7, 2) -// CHECK: %[[T73:.*]] = aie.tile(7, 3) -// CHECK: %[[T80:.*]] = aie.tile(8, 0) -// CHECK: %[[T82:.*]] = aie.tile(8, 2) -// CHECK: %[[T83:.*]] = aie.tile(8, 3) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: %[[T00:.*]] = aie.tile(0, 0) +// CHECK1: %[[T13:.*]] = aie.tile(1, 3) +// CHECK1: %[[T11:.*]] = aie.tile(1, 1) +// CHECK1: %[[T10:.*]] = aie.tile(1, 0) +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T31:.*]] = aie.tile(3, 1) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T71:.*]] = aie.tile(7, 1) +// CHECK1: %[[T72:.*]] = aie.tile(7, 2) +// CHECK1: %[[T73:.*]] = aie.tile(7, 3) +// CHECK1: %[[T80:.*]] = aie.tile(8, 0) +// CHECK1: %[[T82:.*]] = aie.tile(8, 2) +// CHECK1: %[[T83:.*]] = aie.tile(8, 3) // -// CHECK: aie.flow(%[[T71]], DMA : 0, %[[T20]], DMA : 0) -// CHECK: aie.flow(%[[T71]], DMA : 1, %[[T20]], DMA : 1) -// CHECK: aie.flow(%[[T72]], DMA : 0, %[[T60]], DMA : 0) -// CHECK: aie.flow(%[[T72]], DMA : 1, %[[T60]], DMA : 1) -// CHECK: aie.flow(%[[T73]], DMA : 0, %[[T70]], DMA : 0) -// CHECK: aie.flow(%[[T73]], DMA : 1, %[[T70]], DMA : 1) -// CHECK: aie.flow(%[[T83]], DMA : 0, %[[T30]], DMA : 0) -// CHECK: aie.flow(%[[T83]], DMA : 1, %[[T30]], DMA : 1) +// CHECK1: aie.flow(%[[T71]], DMA : 0, %[[T20]], DMA : 0) +// CHECK1: aie.flow(%[[T71]], DMA : 1, %[[T20]], DMA : 1) +// CHECK1: aie.flow(%[[T72]], DMA : 0, %[[T60]], DMA : 0) +// CHECK1: aie.flow(%[[T72]], DMA : 1, %[[T60]], DMA : 1) +// CHECK1: aie.flow(%[[T73]], DMA : 0, %[[T70]], DMA : 0) +// CHECK1: aie.flow(%[[T73]], DMA : 1, %[[T70]], DMA : 1) +// CHECK1: aie.flow(%[[T83]], DMA : 0, %[[T30]], DMA : 0) +// CHECK1: aie.flow(%[[T83]], DMA : 1, %[[T30]], DMA : 1) + +// CHECK2: "total_path_length": 40 module { aie.device(xcvc1902) { diff --git a/test/create-flows/routed_herd_3x1.mlir b/test/create-flows/routed_herd_3x1.mlir index 23e4ea57d3..32386f3a88 100644 --- a/test/create-flows/routed_herd_3x1.mlir +++ b/test/create-flows/routed_herd_3x1.mlir @@ -8,40 +8,45 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T100:.*]] = aie.tile(10, 0) -// CHECK: %[[T110:.*]] = aie.tile(11, 0) -// CHECK: %[[T180:.*]] = aie.tile(18, 0) -// CHECK: %[[T190:.*]] = aie.tile(19, 0) -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T14:.*]] = aie.tile(1, 4) -// CHECK: %[[T33:.*]] = aie.tile(3, 3) -// CHECK: %[[T42:.*]] = aie.tile(4, 2) -// CHECK: %[[T53:.*]] = aie.tile(5, 3) -// CHECK: %[[T63:.*]] = aie.tile(6, 3) -// CHECK: %[[T74:.*]] = aie.tile(7, 4) -// CHECK: %[[T92:.*]] = aie.tile(9, 2) -// CHECK: %[[T102:.*]] = aie.tile(10, 2) -// CHECK: %[[T113:.*]] = aie.tile(11, 3) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T100:.*]] = aie.tile(10, 0) +// CHECK1: %[[T110:.*]] = aie.tile(11, 0) +// CHECK1: %[[T180:.*]] = aie.tile(18, 0) +// CHECK1: %[[T190:.*]] = aie.tile(19, 0) +// CHECK1: %[[T03:.*]] = aie.tile(0, 3) +// CHECK1: %[[T14:.*]] = aie.tile(1, 4) +// CHECK1: %[[T33:.*]] = aie.tile(3, 3) +// CHECK1: %[[T42:.*]] = aie.tile(4, 2) +// CHECK1: %[[T53:.*]] = aie.tile(5, 3) +// CHECK1: %[[T63:.*]] = aie.tile(6, 3) +// CHECK1: %[[T74:.*]] = aie.tile(7, 4) +// CHECK1: %[[T92:.*]] = aie.tile(9, 2) +// CHECK1: %[[T102:.*]] = aie.tile(10, 2) +// CHECK1: %[[T113:.*]] = aie.tile(11, 3) // -// CHECK: aie.flow(%[[T20]], DMA : 0, %[[T14]], DMA : 0) -// CHECK: aie.flow(%[[T20]], DMA : 1, %[[T63]], DMA : 1) -// CHECK: aie.flow(%[[T30]], DMA : 0, %[[T33]], DMA : 0) -// CHECK: aie.flow(%[[T30]], DMA : 1, %[[T74]], DMA : 1) -// CHECK: aie.flow(%[[T60]], DMA : 0, %[[T03]], DMA : 0) -// CHECK: aie.flow(%[[T60]], DMA : 1, %[[T42]], DMA : 0) -// CHECK: aie.flow(%[[T70]], DMA : 0, %[[T03]], DMA : 1) -// CHECK: aie.flow(%[[T70]], DMA : 1, %[[T53]], DMA : 0) -// CHECK: aie.flow(%[[T100]], DMA : 0, %[[T102]], DMA : 0) -// CHECK: aie.flow(%[[T110]], DMA : 0, %[[T113]], DMA : 0) -// CHECK: aie.flow(%[[T180]], DMA : 0, %[[T63]], DMA : 0) -// CHECK: aie.flow(%[[T180]], DMA : 1, %[[T92]], DMA : 0) -// CHECK: aie.flow(%[[T190]], DMA : 0, %[[T74]], DMA : 0) -// CHECK: aie.flow(%[[T190]], DMA : 1, %[[T113]], DMA : 1) +// CHECK1: aie.flow(%[[T20]], DMA : 0, %[[T14]], DMA : 0) +// CHECK1: aie.flow(%[[T20]], DMA : 1, %[[T63]], DMA : 1) +// CHECK1: aie.flow(%[[T30]], DMA : 0, %[[T33]], DMA : 0) +// CHECK1: aie.flow(%[[T30]], DMA : 1, %[[T74]], DMA : 1) +// CHECK1: aie.flow(%[[T60]], DMA : 0, %[[T03]], DMA : 0) +// CHECK1: aie.flow(%[[T60]], DMA : 1, %[[T42]], DMA : 0) +// CHECK1: aie.flow(%[[T70]], DMA : 0, %[[T03]], DMA : 1) +// CHECK1: aie.flow(%[[T70]], DMA : 1, %[[T53]], DMA : 0) +// CHECK1: aie.flow(%[[T100]], DMA : 0, %[[T102]], DMA : 0) +// CHECK1: aie.flow(%[[T110]], DMA : 0, %[[T113]], DMA : 0) +// CHECK1: aie.flow(%[[T180]], DMA : 0, %[[T63]], DMA : 0) +// CHECK1: aie.flow(%[[T180]], DMA : 1, %[[T92]], DMA : 0) +// CHECK1: aie.flow(%[[T190]], DMA : 0, %[[T74]], DMA : 0) +// CHECK1: aie.flow(%[[T190]], DMA : 1, %[[T113]], DMA : 1) + +// CHECK2: "total_path_length": 109 module { aie.device(xcvc1902) { diff --git a/test/create-flows/routed_herd_3x2.mlir b/test/create-flows/routed_herd_3x2.mlir index 33cf5ac6e8..1d5d065e28 100644 --- a/test/create-flows/routed_herd_3x2.mlir +++ b/test/create-flows/routed_herd_3x2.mlir @@ -8,34 +8,38 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T100:.*]] = aie.tile(10, 0) -// CHECK: %[[T110:.*]] = aie.tile(11, 0) -// CHECK: %[[T180:.*]] = aie.tile(18, 0) -// CHECK: %[[T190:.*]] = aie.tile(19, 0) -// CHECK: %[[T25:.*]] = aie.tile(2, 5) -// CHECK: %[[T31:.*]] = aie.tile(3, 1) -// CHECK: %[[T66:.*]] = aie.tile(6, 6) -// CHECK: %[[T73:.*]] = aie.tile(7, 3) -// CHECK: %[[T125:.*]] = aie.tile(12, 5) -// CHECK: %[[T133:.*]] = aie.tile(13, 3) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T20:.*]] = aie.tile(2, 0) +// CHECK1: %[[T30:.*]] = aie.tile(3, 0) +// CHECK1: %[[T60:.*]] = aie.tile(6, 0) +// CHECK1: %[[T70:.*]] = aie.tile(7, 0) +// CHECK1: %[[T100:.*]] = aie.tile(10, 0) +// CHECK1: %[[T110:.*]] = aie.tile(11, 0) +// CHECK1: %[[T180:.*]] = aie.tile(18, 0) +// CHECK1: %[[T190:.*]] = aie.tile(19, 0) +// CHECK1: %[[T25:.*]] = aie.tile(2, 5) +// CHECK1: %[[T31:.*]] = aie.tile(3, 1) +// CHECK1: %[[T66:.*]] = aie.tile(6, 6) +// CHECK1: %[[T73:.*]] = aie.tile(7, 3) +// CHECK1: %[[T125:.*]] = aie.tile(12, 5) +// CHECK1: %[[T133:.*]] = aie.tile(13, 3) // -// CHECK: aie.flow(%[[T30]], DMA : 0, %[[T31]], DMA : 0) -// CHECK: aie.flow(%[[T100]], DMA : 0, %[[T73]], DMA : 0) -// CHECK: aie.flow(%[[T110]], DMA : 0, %[[T133]], DMA : 0) +// CHECK1: aie.flow(%[[T30]], DMA : 0, %[[T31]], DMA : 0) +// CHECK1: aie.flow(%[[T100]], DMA : 0, %[[T73]], DMA : 0) +// CHECK1: aie.flow(%[[T110]], DMA : 0, %[[T133]], DMA : 0) // -// CHECK: aie.flow(%[[T25]], DMA : 0, %[[T60]], DMA : 0) -// CHECK: aie.flow(%[[T31]], Core : 0, %[[T25]], Core : 0) -// CHECK: aie.flow(%[[T66]], DMA : 0, %[[T20]], DMA : 0) +// CHECK1: aie.flow(%[[T25]], DMA : 0, %[[T60]], DMA : 0) +// CHECK1: aie.flow(%[[T31]], Core : 0, %[[T25]], Core : 0) +// CHECK1: aie.flow(%[[T66]], DMA : 0, %[[T20]], DMA : 0) // -// CHECK: aie.flow(%[[T73]], Core : 0, %[[T66]], Core : 0) -// CHECK: aie.flow(%[[T125]], DMA : 0, %[[T180]], DMA : 0) -// CHECK: aie.flow(%[[T133]], Core : 0, %[[T125]], Core : 0) +// CHECK1: aie.flow(%[[T73]], Core : 0, %[[T66]], Core : 0) +// CHECK1: aie.flow(%[[T125]], DMA : 0, %[[T180]], DMA : 0) +// CHECK1: aie.flow(%[[T133]], Core : 0, %[[T125]], Core : 0) +// CHECK2: "total_path_length": 54 module { aie.device(xcvc1902) { diff --git a/test/create-flows/simple.mlir b/test/create-flows/simple.mlir index 3d22168f93..176514dc2e 100644 --- a/test/create-flows/simple.mlir +++ b/test/create-flows/simple.mlir @@ -8,10 +8,24 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T01:.*]] = aie.tile(0, 1) -// CHECK: %[[T12:.*]] = aie.tile(1, 2) -// CHECK: aie.flow(%[[T01]], DMA : 0, %[[T12]], Core : 1) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T01:.*]] = aie.tile(0, 1) +// CHECK1: %[[T12:.*]] = aie.tile(1, 2) +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: aie.packet_flow(16) { +// CHECK1: aie.packet_source<%[[T01]], Core : 0> +// CHECK1: aie.packet_dest<%[[T12]], Core : 0> +// CHECK1: } +// CHECK1: aie.packet_flow(16) { +// CHECK1: aie.packet_source<%[[T01]], Core : 0> +// CHECK1: aie.packet_dest<%[[T02]], DMA : 1> +// CHECK1: } +// CHECK1: aie.flow(%[[T01]], DMA : 0, %[[T12]], Core : 1) + +// CHECK2: "total_path_length": 5 module { aie.device(xcvc1902) { @@ -20,9 +34,9 @@ module { %02 = aie.tile(0, 2) aie.flow(%01, DMA : 0, %12, Core : 1) aie.packet_flow(0x10) { - aie.packet_source < %01, Core : 0> - aie.packet_dest < %12, Core : 0> - aie.packet_dest < %02, DMA : 1> + aie.packet_source<%01, Core : 0> + aie.packet_dest<%12, Core : 0> + aie.packet_dest< %02, DMA : 1> } } } diff --git a/test/create-flows/simple2.mlir b/test/create-flows/simple2.mlir index 4fa7b9ce93..c42ee076ad 100644 --- a/test/create-flows/simple2.mlir +++ b/test/create-flows/simple2.mlir @@ -8,10 +8,15 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T23:.*]] = aie.tile(2, 3) -// CHECK: %[[T32:.*]] = aie.tile(3, 2) -// CHECK: aie.flow(%[[T23]], Core : 1, %[[T32]], DMA : 0) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T23:.*]] = aie.tile(2, 3) +// CHECK1: %[[T32:.*]] = aie.tile(3, 2) +// CHECK1: aie.flow(%[[T23]], Core : 1, %[[T32]], DMA : 0) + +// CHECK2: "total_path_length": 2 module { aie.device(xcvc1902) { diff --git a/test/create-flows/simple_flows.mlir b/test/create-flows/simple_flows.mlir index f3aa74b236..886650ef99 100644 --- a/test/create-flows/simple_flows.mlir +++ b/test/create-flows/simple_flows.mlir @@ -8,12 +8,17 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T23:.*]] = aie.tile(2, 3) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: aie.flow(%[[T23]], Core : 0, %[[T22]], Core : 1) -// CHECK: aie.flow(%[[T22]], Core : 0, %[[T22]], Core : 0) -// CHECK: aie.flow(%[[T22]], Core : 1, %[[T23]], Core : 1) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T23:.*]] = aie.tile(2, 3) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: aie.flow(%[[T23]], Core : 0, %[[T22]], Core : 1) +// CHECK1: aie.flow(%[[T22]], Core : 0, %[[T22]], Core : 0) +// CHECK1: aie.flow(%[[T22]], Core : 1, %[[T23]], Core : 1) + +// CHECK2: "total_path_length": 2 module { aie.device(xcvc1902) { diff --git a/test/create-flows/simple_flows2.mlir b/test/create-flows/simple_flows2.mlir index c960ca3746..c74a1ec016 100644 --- a/test/create-flows/simple_flows2.mlir +++ b/test/create-flows/simple_flows2.mlir @@ -8,12 +8,17 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T23:.*]] = aie.tile(2, 3) -// CHECK: %[[T22:.*]] = aie.tile(2, 2) -// CHECK: %[[T11:.*]] = aie.tile(1, 1) -// CHECK: aie.flow(%[[T23]], Core : 0, %[[T22]], Core : 1) -// CHECK: aie.flow(%[[T22]], Core : 0, %[[T11]], Core : 0) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T23:.*]] = aie.tile(2, 3) +// CHECK1: %[[T22:.*]] = aie.tile(2, 2) +// CHECK1: %[[T11:.*]] = aie.tile(1, 1) +// CHECK1: aie.flow(%[[T23]], Core : 0, %[[T22]], Core : 1) +// CHECK1: aie.flow(%[[T22]], Core : 0, %[[T11]], Core : 0) + +// CHECK2: "total_path_length": 3 module { aie.device(xcvc1902) { diff --git a/test/create-flows/unit_broadcast.mlir b/test/create-flows/unit_broadcast.mlir deleted file mode 100644 index 45ff1526d5..0000000000 --- a/test/create-flows/unit_broadcast.mlir +++ /dev/null @@ -1,249 +0,0 @@ -//===- broadcast.mlir ------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_9:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_13:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_15:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_16:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_17:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_21]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_28]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_30]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_35]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_41]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_45]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_52:.*]] = aie.switchbox(%[[VAL_51]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.shim_mux(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_56:.*]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_57:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_56]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_56]] : East, %[[VAL_58:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_58]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_59:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_60:.*]] : North, %[[VAL_61:.*]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : East, %[[VAL_62:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_62]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_62]] : DMA) -// CHECK: aie.wire(%[[VAL_61]] : North, %[[VAL_62]] : South) -// CHECK: aie.wire(%[[VAL_8]] : Core, %[[VAL_63:.*]] : Core) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_63]] : DMA) -// CHECK: aie.wire(%[[VAL_62]] : North, %[[VAL_63]] : South) -// CHECK: aie.wire(%[[VAL_59]] : East, %[[VAL_64:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_64]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_63]] : North, %[[VAL_64]] : South) -// CHECK: aie.wire(%[[VAL_61]] : East, %[[VAL_65:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : East, %[[VAL_66:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_66]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_66]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_66]] : South) -// CHECK: aie.wire(%[[VAL_63]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_66]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_68:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_69]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_69]] : DMA) -// CHECK: aie.wire(%[[VAL_68]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_70:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_70]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_70]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_72:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_72]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_74:.*]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_74]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : East, %[[VAL_75:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_75]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : North, %[[VAL_75]] : South) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_76:.*]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_75]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_75]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_78]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_77]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_80:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_81]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t03 = aie.tile(0, 3) - %t02 = aie.tile(0, 2) - %t00 = aie.tile(0, 0) - %t13 = aie.tile(1, 3) - %t11 = aie.tile(1, 1) - %t10 = aie.tile(1, 0) - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - %t22 = aie.tile(2, 2) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t80 = aie.tile(8, 0) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - - aie.flow(%t20, DMA : 0, %t13, DMA : 0) - aie.flow(%t20, DMA : 0, %t31, DMA : 0) - aie.flow(%t20, DMA : 0, %t71, DMA : 0) - aie.flow(%t20, DMA : 0, %t82, DMA : 0) - - aie.flow(%t60, DMA : 0, %t02, DMA : 1) - aie.flow(%t60, DMA : 0, %t83, DMA : 1) - aie.flow(%t60, DMA : 0, %t22, DMA : 1) - aie.flow(%t60, DMA : 0, %t31, DMA : 1) - } -} diff --git a/test/create-flows/unit_flow_test_1.mlir b/test/create-flows/unit_flow_test_1.mlir deleted file mode 100644 index 1b00ece4c9..0000000000 --- a/test/create-flows/unit_flow_test_1.mlir +++ /dev/null @@ -1,452 +0,0 @@ -//===- flow_test_1.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_3:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_8:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_10:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_11:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.shim_mux(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_14:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_15:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_18]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_20]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_27]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.shim_mux(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_32]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_34]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_37]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_39]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_42]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_53:.*]] = aie.switchbox(%[[VAL_52]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.shim_mux(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_56:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_57:.*]] = aie.switchbox(%[[VAL_56]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_59:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_62]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_65:.*]] = aie.switchbox(%[[VAL_64]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_70:.*]] : North, %[[VAL_71:.*]] : South) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_72:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_73:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_75:.*]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_76]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_18]] : Core, %[[VAL_77]] : Core) -// CHECK: aie.wire(%[[VAL_18]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_76]] : North, %[[VAL_77]] : South) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_78:.*]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_77]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_79:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_81]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : North, %[[VAL_81]] : South) -// CHECK: aie.wire(%[[VAL_77]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_89]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_91:.*]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_94]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_94]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_95:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_95]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_94]] : North, %[[VAL_95]] : South) -// CHECK: aie.wire(%[[VAL_90]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_97:.*]] : North, %[[VAL_96]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_98:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : Core, %[[VAL_98]] : Core) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_98]] : South) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_99:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_99]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_99]] : DMA) -// CHECK: aie.wire(%[[VAL_98]] : North, %[[VAL_99]] : South) -// CHECK: aie.wire(%[[VAL_94]] : East, %[[VAL_100:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_100]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_99]] : North, %[[VAL_100]] : South) -// CHECK: aie.wire(%[[VAL_95]] : East, %[[VAL_101:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_101]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_96]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_98]] : East, %[[VAL_103:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_103]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_103]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_103]] : North, %[[VAL_104]] : South) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_106:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_106]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - %t34 = aie.tile(3, 4) - %t43 = aie.tile(4, 3) - %t44 = aie.tile(4, 4) - %t54 = aie.tile(5, 4) - %t60 = aie.tile(6, 0) - %t63 = aie.tile(6, 3) - %t70 = aie.tile(7, 0) - %t72 = aie.tile(7, 2) - %t83 = aie.tile(8, 3) - %t84 = aie.tile(8, 4) - - aie.flow(%t20, DMA : 0, %t63, DMA : 0) - aie.flow(%t20, DMA : 1, %t83, DMA : 0) - aie.flow(%t30, DMA : 0, %t72, DMA : 0) - aie.flow(%t30, DMA : 1, %t54, DMA : 0) - - aie.flow(%t34, Core : 0, %t63, Core : 1) - aie.flow(%t34, DMA : 1, %t70, DMA : 0) - aie.flow(%t43, Core : 0, %t84, Core : 1) - aie.flow(%t43, DMA : 1, %t60, DMA : 1) - - aie.flow(%t44, Core : 0, %t54, Core : 1) - aie.flow(%t44, DMA : 1, %t60, DMA : 0) - aie.flow(%t54, Core : 0, %t43, Core : 1) - aie.flow(%t54, DMA : 1, %t30, DMA : 1) - - aie.flow(%t60, DMA : 0, %t44, DMA : 0) - aie.flow(%t60, DMA : 1, %t43, DMA : 0) - aie.flow(%t63, Core : 0, %t34, Core : 1) - aie.flow(%t63, DMA : 1, %t20, DMA : 1) - - aie.flow(%t70, DMA : 0, %t34, DMA : 0) - aie.flow(%t70, DMA : 1, %t84, DMA : 0) - aie.flow(%t72, Core : 0, %t83, Core : 1) - aie.flow(%t72, DMA : 1, %t30, DMA : 0) - - aie.flow(%t83, Core : 0, %t44, Core : 1) - aie.flow(%t83, DMA : 1, %t20, DMA : 0) - aie.flow(%t84, Core : 0, %t72, Core : 1) - aie.flow(%t84, DMA : 1, %t70, DMA : 1) - } -} diff --git a/test/create-flows/unit_flow_test_2.mlir b/test/create-flows/unit_flow_test_2.mlir deleted file mode 100644 index 7ecbed58e6..0000000000 --- a/test/create-flows/unit_flow_test_2.mlir +++ /dev/null @@ -1,275 +0,0 @@ -//===- flow_test_2.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_7:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_11:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_12:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_13:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_18]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.shim_mux(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.shim_mux(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_40:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_40]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_41:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_41]] : DMA) -// CHECK: aie.wire(%[[VAL_40]] : North, %[[VAL_41]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_42:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_42]] : DMA) -// CHECK: aie.wire(%[[VAL_41]] : North, %[[VAL_42]] : South) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_43:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_43]] : DMA) -// CHECK: aie.wire(%[[VAL_42]] : North, %[[VAL_43]] : South) -// CHECK: aie.wire(%[[VAL_40]] : East, %[[VAL_44:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_44]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_44]] : DMA) -// CHECK: aie.wire(%[[VAL_45:.*]] : North, %[[VAL_44]] : South) -// CHECK: aie.wire(%[[VAL_41]] : East, %[[VAL_46:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_46]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_46]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : North, %[[VAL_46]] : South) -// CHECK: aie.wire(%[[VAL_42]] : East, %[[VAL_47:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_47]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_47]] : DMA) -// CHECK: aie.wire(%[[VAL_46]] : North, %[[VAL_47]] : South) -// CHECK: aie.wire(%[[VAL_43]] : East, %[[VAL_48:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_48]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_48]] : DMA) -// CHECK: aie.wire(%[[VAL_47]] : North, %[[VAL_48]] : South) -// CHECK: aie.wire(%[[VAL_45]] : East, %[[VAL_49:.*]] : West) -// CHECK: aie.wire(%[[VAL_50:.*]] : North, %[[VAL_49]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_50]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : East, %[[VAL_51:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_51]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_51]] : DMA) -// CHECK: aie.wire(%[[VAL_49]] : North, %[[VAL_51]] : South) -// CHECK: aie.wire(%[[VAL_46]] : East, %[[VAL_52:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_52]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_52]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : North, %[[VAL_52]] : South) -// CHECK: aie.wire(%[[VAL_47]] : East, %[[VAL_53:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_53]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_53]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : North, %[[VAL_53]] : South) -// CHECK: aie.wire(%[[VAL_48]] : East, %[[VAL_54:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_54]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_54]] : DMA) -// CHECK: aie.wire(%[[VAL_53]] : North, %[[VAL_54]] : South) -// CHECK: aie.wire(%[[VAL_49]] : East, %[[VAL_55:.*]] : West) -// CHECK: aie.wire(%[[VAL_56:.*]] : North, %[[VAL_55]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : East, %[[VAL_57:.*]] : West) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_57]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_55]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_52]] : East, %[[VAL_58:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_58]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_57]] : North, %[[VAL_58]] : South) -// CHECK: aie.wire(%[[VAL_53]] : East, %[[VAL_59:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_59]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : North, %[[VAL_59]] : South) -// CHECK: aie.wire(%[[VAL_54]] : East, %[[VAL_60:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_60]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_59]] : North, %[[VAL_60]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t04 = aie.tile(0, 4) - %t11 = aie.tile(1, 1) - %t12 = aie.tile(1, 2) - %t13 = aie.tile(1, 3) - %t14 = aie.tile(1, 4) - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - %t22 = aie.tile(2, 2) - %t23 = aie.tile(2, 3) - %t24 = aie.tile(2, 4) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t32 = aie.tile(3, 2) - %t33 = aie.tile(3, 3) - %t34 = aie.tile(3, 4) - - //TASK 1 - aie.flow(%t20, DMA : 0, %t11, DMA : 0) - aie.flow(%t11, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t12, Core : 0) - aie.flow(%t12, Core : 0, %t02, Core : 0) - aie.flow(%t02, DMA : 0, %t20, DMA : 0) - - //TASK 2 - aie.flow(%t20, DMA : 1, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t04, Core : 0) - aie.flow(%t04, Core : 0, %t13, Core : 0) - aie.flow(%t13, DMA : 0, %t20, DMA : 1) - - //TASK 3 - aie.flow(%t30, DMA : 0, %t21, DMA : 0) - aie.flow(%t21, Core : 0, %t33, Core : 0) - aie.flow(%t33, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 0, %t34, Core : 0) - aie.flow(%t34, Core : 0, %t24, Core : 0) - aie.flow(%t24, Core : 0, %t23, Core : 0) - aie.flow(%t23, DMA : 0, %t30, DMA : 0) - - //TASK 4 - aie.flow(%t30, DMA : 1, %t31, DMA : 1) - aie.flow(%t31, Core : 1, %t23, Core : 1) - aie.flow(%t23, Core : 1, %t34, Core : 1) - aie.flow(%t34, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t33, Core : 1) - aie.flow(%t33, Core : 1, %t32, Core : 1) - aie.flow(%t32, DMA : 1, %t30, DMA : 1) - } -} diff --git a/test/create-flows/unit_flow_test_3.mlir b/test/create-flows/unit_flow_test_3.mlir deleted file mode 100644 index e394f1b06a..0000000000 --- a/test/create-flows/unit_flow_test_3.mlir +++ /dev/null @@ -1,490 +0,0 @@ -//===- flow_test_3.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_7:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_11:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_12:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_13:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_20:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_21:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_25]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.shim_mux(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_32]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_34]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_19]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_20]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_21]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_52:.*]] = aie.switchbox(%[[VAL_51]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_53]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_56:.*]] = aie.switchbox(%[[VAL_55]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_57:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_58:.*]] = aie.switchbox(%[[VAL_57]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_65:.*]] = aie.shim_mux(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_70]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_72]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_74]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_77:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_77]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_79:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_80:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_81:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : North, %[[VAL_81]] : South) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_82:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_84:.*]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_85]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_85]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_85]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_89:.*]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_90]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_90]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_91:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_91]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_91]] : South) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_91]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_95:.*]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_96]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_96]] : DMA) -// CHECK: aie.wire(%[[VAL_94]] : North, %[[VAL_96]] : South) -// CHECK: aie.wire(%[[VAL_91]] : East, %[[VAL_97:.*]] : West) -// CHECK: aie.wire(%[[VAL_72]] : Core, %[[VAL_97]] : Core) -// CHECK: aie.wire(%[[VAL_72]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_97]] : South) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_98:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_98]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_97]] : North, %[[VAL_98]] : South) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_99:.*]] : West) -// CHECK: aie.wire(%[[VAL_77]] : Core, %[[VAL_99]] : Core) -// CHECK: aie.wire(%[[VAL_77]] : DMA, %[[VAL_99]] : DMA) -// CHECK: aie.wire(%[[VAL_98]] : North, %[[VAL_99]] : South) -// CHECK: aie.wire(%[[VAL_96]] : East, %[[VAL_100:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_100]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_97]] : East, %[[VAL_101:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_101]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_98]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_102]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_102]] : DMA) -// CHECK: aie.wire(%[[VAL_101]] : North, %[[VAL_102]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_103:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_103]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_103]] : South) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_74]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_74]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_102]] : East, %[[VAL_106:.*]] : West) -// CHECK: aie.wire(%[[VAL_36]] : Core, %[[VAL_106]] : Core) -// CHECK: aie.wire(%[[VAL_36]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) -// CHECK: aie.wire(%[[VAL_103]] : East, %[[VAL_107:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_107]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_107]] : DMA) -// CHECK: aie.wire(%[[VAL_106]] : North, %[[VAL_107]] : South) -// CHECK: aie.wire(%[[VAL_104]] : East, %[[VAL_108:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_108]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_108]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : East, %[[VAL_109:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_109]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_109]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : North, %[[VAL_109]] : South) -// CHECK: aie.wire(%[[VAL_106]] : East, %[[VAL_110:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_110]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_110]] : DMA) -// CHECK: aie.wire(%[[VAL_109]] : North, %[[VAL_110]] : South) -// CHECK: aie.wire(%[[VAL_107]] : East, %[[VAL_111:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_111]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_111]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : North, %[[VAL_111]] : South) -// CHECK: aie.wire(%[[VAL_108]] : East, %[[VAL_112:.*]] : West) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_112]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_112]] : DMA) -// CHECK: aie.wire(%[[VAL_109]] : East, %[[VAL_113:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_113]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_113]] : DMA) -// CHECK: aie.wire(%[[VAL_112]] : North, %[[VAL_113]] : South) -// CHECK: aie.wire(%[[VAL_110]] : East, %[[VAL_114:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_114]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_114]] : DMA) -// CHECK: aie.wire(%[[VAL_113]] : North, %[[VAL_114]] : South) -// CHECK: aie.wire(%[[VAL_111]] : East, %[[VAL_115:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_115]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_115]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : North, %[[VAL_115]] : South) -// CHECK: aie.wire(%[[VAL_113]] : East, %[[VAL_116:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_116]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_116]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : East, %[[VAL_117:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_117]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_117]] : DMA) -// CHECK: aie.wire(%[[VAL_116]] : North, %[[VAL_117]] : South) -// CHECK: aie.wire(%[[VAL_115]] : East, %[[VAL_118:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_118]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_118]] : DMA) -// CHECK: aie.wire(%[[VAL_117]] : North, %[[VAL_118]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t04 = aie.tile(0, 4) - %t11 = aie.tile(1, 1) - %t12 = aie.tile(1, 2) - %t13 = aie.tile(1, 3) - %t14 = aie.tile(1, 4) - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - %t22 = aie.tile(2, 2) - %t23 = aie.tile(2, 3) - %t24 = aie.tile(2, 4) - %t30 = aie.tile(3, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t74 = aie.tile(7, 4) - %t81 = aie.tile(8, 1) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - %t84 = aie.tile(8, 4) - - //TASK 1 - aie.flow(%t20, DMA : 0, %t03, DMA : 0) - aie.flow(%t03, Core : 0, %t71, Core : 0) - aie.flow(%t71, Core : 0, %t84, Core : 0) - aie.flow(%t84, Core : 0, %t11, Core : 0) - aie.flow(%t11, Core : 0, %t24, Core : 0) - aie.flow(%t24, DMA : 0, %t20, DMA : 0) - - //TASK 2 - aie.flow(%t30, DMA : 0, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t83, Core : 0) - aie.flow(%t83, Core : 0, %t21, Core : 0) - aie.flow(%t21, Core : 0, %t73, Core : 0) - aie.flow(%t73, Core : 0, %t82, Core : 0) - aie.flow(%t82, DMA : 0, %t30, DMA : 0) - - //TASK 3 - aie.flow(%t20, DMA : 1, %t83, DMA : 1) - aie.flow(%t83, Core : 1, %t01, Core : 1) - aie.flow(%t01, Core : 1, %t72, Core : 1) - aie.flow(%t72, Core : 1, %t02, Core : 1) - aie.flow(%t02, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t71, Core : 1) - aie.flow(%t71, Core : 1, %t84, Core : 1) - aie.flow(%t84, DMA : 1, %t20, DMA : 1) - } -} diff --git a/test/create-flows/unit_many_flows.mlir b/test/create-flows/unit_many_flows.mlir deleted file mode 100644 index 16dd4f61b8..0000000000 --- a/test/create-flows/unit_many_flows.mlir +++ /dev/null @@ -1,338 +0,0 @@ -//===- many_flows.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_8:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_11:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_14:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_16:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_19]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_21]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.shim_mux(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_29]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_31]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_35]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_37]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_39]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_41]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_43]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_48:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_49:.*]] = aie.switchbox(%[[VAL_48]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_50:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_50]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.shim_mux(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_53]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_56:.*]] = aie.switchbox(%[[VAL_55]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_57:.*]] = aie.shim_mux(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_58]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_64:.*]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_65:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_65]] : DMA) -// CHECK: aie.wire(%[[VAL_64]] : North, %[[VAL_65]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_66:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_66]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_66]] : South) -// CHECK: aie.wire(%[[VAL_64]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_68:.*]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_69]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_69]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_70:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_70]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_70]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_72:.*]] : North, %[[VAL_71]] : South) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_73]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_74]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_74]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_70]] : East, %[[VAL_75:.*]] : West) -// CHECK: aie.wire(%[[VAL_29]] : Core, %[[VAL_75]] : Core) -// CHECK: aie.wire(%[[VAL_29]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_75]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_77:.*]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_78]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_76]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_75]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_80]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_90:.*]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_90]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_91:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_91]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_89]] : North, %[[VAL_91]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_91]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_95:.*]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_96]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_96]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_97:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_97]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_97]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t11 = aie.tile(1, 1) - %t13 = aie.tile(1, 3) - %t20 = aie.tile(2, 0) - %t22 = aie.tile(2, 2) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t73 = aie.tile(7, 3) - - aie.flow(%t03, DMA : 0, %t70, DMA : 0) - aie.flow(%t13, DMA : 0, %t70, DMA : 1) - aie.flow(%t02, DMA : 0, %t60, DMA : 0) - aie.flow(%t22, DMA : 0, %t60, DMA : 1) - - aie.flow(%t03, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t13, Core : 1, %t22, Core : 0) - aie.flow(%t02, Core : 1, %t22, Core : 1) - - aie.flow(%t73, DMA : 0, %t20, DMA : 0) - aie.flow(%t73, DMA : 1, %t30, DMA : 0) - aie.flow(%t31, DMA : 0, %t20, DMA : 1) - aie.flow(%t31, DMA : 1, %t30, DMA : 1) - - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t31, Core : 1) - } -} diff --git a/test/create-flows/unit_many_flows2.mlir b/test/create-flows/unit_many_flows2.mlir deleted file mode 100644 index 7f13b136c9..0000000000 --- a/test/create-flows/unit_many_flows2.mlir +++ /dev/null @@ -1,316 +0,0 @@ -//===- many_flows2.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_8:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_11:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_14:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_27]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.shim_mux(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_31]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.shim_mux(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.shim_mux(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_43]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_45]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_53:.*]] = aie.switchbox(%[[VAL_52]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_55:.*]] = aie.switchbox(%[[VAL_54]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_56:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_57:.*]] = aie.switchbox(%[[VAL_56]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_58]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_62:.*]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_62]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_63:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_63]] : DMA) -// CHECK: aie.wire(%[[VAL_62]] : North, %[[VAL_63]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_64:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_63]] : North, %[[VAL_64]] : South) -// CHECK: aie.wire(%[[VAL_62]] : East, %[[VAL_65:.*]] : West) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_65]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_65]] : DMA) -// CHECK: aie.wire(%[[VAL_66:.*]] : North, %[[VAL_65]] : South) -// CHECK: aie.wire(%[[VAL_63]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_64]] : East, %[[VAL_68:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_68]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_68]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : North, %[[VAL_68]] : South) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_70:.*]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_71]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_71]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_71]] : South) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_72:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_72]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_43]] : Core, %[[VAL_73]] : Core) -// CHECK: aie.wire(%[[VAL_43]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_75:.*]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_76]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_77]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_77]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_80]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_83:.*]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_86:.*]] : North, %[[VAL_85]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_89]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_91:.*]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_94]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_94]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : North, %[[VAL_94]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t11 = aie.tile(1, 1) - %t13 = aie.tile(1, 3) - %t20 = aie.tile(2, 0) - %t22 = aie.tile(2, 2) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t73 = aie.tile(7, 3) - - aie.flow(%t03, DMA : 0, %t30, DMA : 0) - aie.flow(%t03, DMA : 1, %t70, DMA : 1) - aie.flow(%t02, DMA : 0, %t60, DMA : 0) - aie.flow(%t22, DMA : 0, %t20, DMA : 0) - - aie.flow(%t22, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t22, Core : 1) - - aie.flow(%t73, DMA : 0, %t60, DMA : 1) - aie.flow(%t73, DMA : 1, %t70, DMA : 0) - aie.flow(%t31, DMA : 0, %t20, DMA : 1) - aie.flow(%t31, DMA : 1, %t30, DMA : 1) - - aie.flow(%t03, Core : 0, %t02, Core : 1) - aie.flow(%t13, Core : 1, %t31, Core : 1) - } -} diff --git a/test/create-flows/unit_maxiter_err_test.mlir b/test/create-flows/unit_maxiter_err_test.mlir deleted file mode 100644 index 57e0115e91..0000000000 --- a/test/create-flows/unit_maxiter_err_test.mlir +++ /dev/null @@ -1,81 +0,0 @@ -//===- maxiter_err_test.mlir -----------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: not aie-opt --aie-create-pathfinder-flows %s 2>&1 | FileCheck %s -// CHECK: error: Unable to find a legal routing - -module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t11 = aie.tile(1, 1) - %t21 = aie.tile(2, 1) - %t31 = aie.tile(3, 1) - %t41 = aie.tile(4, 1) - %t51 = aie.tile(5, 1) - %t61 = aie.tile(6, 1) - %t71 = aie.tile(7, 1) - %t81 = aie.tile(8, 1) - %t02 = aie.tile(0, 2) - %t12 = aie.tile(1, 2) - %t22 = aie.tile(2, 2) - %t32 = aie.tile(3, 2) - %t42 = aie.tile(4, 2) - %t52 = aie.tile(5, 2) - %t62 = aie.tile(6, 2) - %t72 = aie.tile(7, 2) - %t82 = aie.tile(8, 2) - %t03 = aie.tile(0, 3) - %t13 = aie.tile(1, 3) - %t23 = aie.tile(2, 3) - %t33 = aie.tile(3, 3) - %t43 = aie.tile(4, 3) - %t53 = aie.tile(5, 3) - %t63 = aie.tile(6, 3) - %t73 = aie.tile(7, 3) - %t83 = aie.tile(8, 3) - %t04 = aie.tile(0, 4) - %t14 = aie.tile(1, 4) - %t24 = aie.tile(2, 4) - %t34 = aie.tile(3, 4) - %t44 = aie.tile(4, 4) - %t54 = aie.tile(5, 4) - %t64 = aie.tile(6, 4) - %t74 = aie.tile(7, 4) - %t84 = aie.tile(8, 4) - %t20 = aie.tile(2, 0) - %t60 = aie.tile(6, 0) - - aie.flow(%t01, DMA : 0, %t51, DMA : 0) - aie.flow(%t11, DMA : 0, %t61, DMA : 0) - aie.flow(%t21, DMA : 0, %t71, DMA : 0) - aie.flow(%t31, DMA : 0, %t81, DMA : 0) - aie.flow(%t41, DMA : 0, %t81, DMA : 1) - - aie.flow(%t02, DMA : 0, %t52, DMA : 0) - aie.flow(%t12, DMA : 0, %t62, DMA : 0) - aie.flow(%t22, DMA : 0, %t72, DMA : 0) - aie.flow(%t32, DMA : 0, %t82, DMA : 0) - aie.flow(%t42, DMA : 0, %t82, DMA : 1) - - aie.flow(%t03, DMA : 0, %t53, DMA : 0) - aie.flow(%t13, DMA : 0, %t63, DMA : 0) - aie.flow(%t23, DMA : 0, %t73, DMA : 0) - aie.flow(%t33, DMA : 0, %t83, DMA : 0) - aie.flow(%t43, DMA : 0, %t83, DMA : 1) - - aie.flow(%t04, DMA : 0, %t54, DMA : 0) - aie.flow(%t14, DMA : 0, %t64, DMA : 0) - aie.flow(%t24, DMA : 0, %t74, DMA : 0) - aie.flow(%t34, DMA : 0, %t84, DMA : 0) - aie.flow(%t44, DMA : 0, %t84, DMA : 1) - - aie.flow(%t20, DMA : 0, %t60, DMA : 0) - } -} diff --git a/test/create-flows/unit_memtile.mlir b/test/create-flows/unit_memtile.mlir deleted file mode 100644 index 90b5e0bd5e..0000000000 --- a/test/create-flows/unit_memtile.mlir +++ /dev/null @@ -1,90 +0,0 @@ -//===- memtile.mlir --------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcve2802) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_7:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_8:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_8]] : DMA) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_9:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_9]] : DMA) -// CHECK: aie.wire(%[[VAL_8]] : North, %[[VAL_9]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_10:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_10]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : North, %[[VAL_10]] : South) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_11:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_11]] : DMA) -// CHECK: aie.wire(%[[VAL_10]] : North, %[[VAL_11]] : South) -// CHECK: } - -module { - aie.device(xcve2802) { - %t04 = aie.tile(0, 4) - %t03 = aie.tile(0, 3) - %t02 = aie.tile(0, 2) - %t01 = aie.tile(0, 1) - - aie.flow(%t01, DMA : 0, %t02, DMA : 0) - aie.flow(%t01, DMA : 1, %t02, DMA : 1) - aie.flow(%t02, DMA : 0, %t01, DMA : 0) - aie.flow(%t02, DMA : 1, %t01, DMA : 1) - - aie.flow(%t02, DMA : 2, %t03, DMA : 0) - aie.flow(%t02, DMA : 3, %t03, DMA : 1) - aie.flow(%t03, DMA : 0, %t02, DMA : 2) - aie.flow(%t03, DMA : 1, %t02, DMA : 3) - - aie.flow(%t02, DMA : 4, %t04, DMA : 0) - aie.flow(%t02, DMA : 5, %t04, DMA : 1) - aie.flow(%t04, DMA : 0, %t02, DMA : 4) - aie.flow(%t04, DMA : 1, %t02, DMA : 5) - } -} - diff --git a/test/create-flows/unit_memtile_routing_constraints.mlir b/test/create-flows/unit_memtile_routing_constraints.mlir deleted file mode 100644 index a89c7bc819..0000000000 --- a/test/create-flows/unit_memtile_routing_constraints.mlir +++ /dev/null @@ -1,45 +0,0 @@ -//===- memtile_routing_constraints.mlir ------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK: %tile_2_0 = aie.tile(2, 0) -// CHECK: %tile_2_1 = aie.tile(2, 1) -// CHECK: %tile_2_2 = aie.tile(2, 2) -// CHECK: %tile_2_3 = aie.tile(2, 3) -// CHECK: %switchbox_2_1 = aie.switchbox(%tile_2_1) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_2 = aie.switchbox(%tile_2_2) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_0 = aie.switchbox(%tile_2_0) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %shim_mux_2_0 = aie.shim_mux(%tile_2_0) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_3 = aie.switchbox(%tile_2_3) { -// CHECK: aie.connect -// CHECK: } - -module { - aie.device(xcve2802) { - %tile_2_0 = aie.tile(2, 0) - %tile_2_1 = aie.tile(2, 1) - %tile_2_2 = aie.tile(2, 2) - %tile_2_3 = aie.tile(2, 3) - - aie.flow(%tile_2_2, DMA : 0, %tile_2_1, DMA : 0) - aie.flow(%tile_2_3, DMA : 0, %tile_2_0, DMA : 0) - } -} diff --git a/test/create-flows/unit_mmult.mlir b/test/create-flows/unit_mmult.mlir deleted file mode 100644 index 876f09333d..0000000000 --- a/test/create-flows/unit_mmult.mlir +++ /dev/null @@ -1,653 +0,0 @@ -//===- mmult.mlir ----------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_3]], 1) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_3]], 3) -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf11"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_3]], 2) -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf10"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_3]], 0) -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf9"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_11:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_17:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_18:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_19]], 1) -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_19]], 3) -// CHECK: %[[VAL_22:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf8"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_19]], 2) -// CHECK: %[[VAL_24:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf7"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_19]], 0) -// CHECK: %[[VAL_26:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf6"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_27:.*]] = aie.mem(%[[VAL_19]]) { -// CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_25]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_29:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_23]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_23]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_21]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_33:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_34:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_35:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_36:.*]] = aie.lock(%[[VAL_35]], 1) -// CHECK: %[[VAL_37:.*]] = aie.lock(%[[VAL_35]], 3) -// CHECK: %[[VAL_38:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf5"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_39:.*]] = aie.lock(%[[VAL_35]], 2) -// CHECK: %[[VAL_40:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf4"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_41:.*]] = aie.lock(%[[VAL_35]], 0) -// CHECK: %[[VAL_42:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf3"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_43:.*]] = aie.mem(%[[VAL_35]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_41]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_42]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_41]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_36]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_36]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_45:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_39]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_40]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_39]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_46:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_37]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_37]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_49:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_50:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_51:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_52:.*]] = aie.lock(%[[VAL_51]], 1) -// CHECK: %[[VAL_53:.*]] = aie.lock(%[[VAL_51]], 3) -// CHECK: %[[VAL_54:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf2"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_55:.*]] = aie.lock(%[[VAL_51]], 2) -// CHECK: %[[VAL_56:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf1"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_57:.*]] = aie.lock(%[[VAL_51]], 0) -// CHECK: %[[VAL_58:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf0"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_59:.*]] = aie.mem(%[[VAL_51]]) { -// CHECK: %[[VAL_60:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_57]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_58]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_57]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_52]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_52]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_61:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_55]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_56]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_55]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_62:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_53]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_53]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.switchbox(%[[VAL_48]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_65:.*]] = aie.switchbox(%[[VAL_32]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_70]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_51]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.switchbox(%[[VAL_31]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_77:.*]] = aie.switchbox(%[[VAL_76]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_35]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_79:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_81:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_82:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_83:.*]] = aie.switchbox(%[[VAL_19]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_84:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_85:.*]] = aie.switchbox(%[[VAL_84]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_86:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_87:.*]] = aie.switchbox(%[[VAL_86]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_88:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_89:.*]] = aie.switchbox(%[[VAL_88]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_90:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_91:.*]] = aie.switchbox(%[[VAL_90]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_92:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_93:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.shim_mux(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_95:.*]] = aie.shim_mux(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_96:.*]] = aie.shim_mux(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_97:.*]] = aie.shim_mux(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_98:.*]] : North, %[[VAL_99:.*]] : South) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_100:.*]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_99]] : North, %[[VAL_100]] : South) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_101:.*]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_103:.*]] : North, %[[VAL_102]] : South) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_104]] : South) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_84]] : Core, %[[VAL_106:.*]] : Core) -// CHECK: aie.wire(%[[VAL_84]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) -// CHECK: aie.wire(%[[VAL_104]] : East, %[[VAL_107:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_107]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_107]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : East, %[[VAL_108:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_108]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_108]] : DMA) -// CHECK: aie.wire(%[[VAL_107]] : North, %[[VAL_108]] : South) -// CHECK: aie.wire(%[[VAL_106]] : East, %[[VAL_109:.*]] : West) -// CHECK: aie.wire(%[[VAL_86]] : Core, %[[VAL_109]] : Core) -// CHECK: aie.wire(%[[VAL_86]] : DMA, %[[VAL_109]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : North, %[[VAL_109]] : South) -// CHECK: aie.wire(%[[VAL_107]] : East, %[[VAL_110:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : Core, %[[VAL_110]] : Core) -// CHECK: aie.wire(%[[VAL_76]] : DMA, %[[VAL_110]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : East, %[[VAL_111:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_111]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_111]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : North, %[[VAL_111]] : South) -// CHECK: aie.wire(%[[VAL_109]] : East, %[[VAL_112:.*]] : West) -// CHECK: aie.wire(%[[VAL_88]] : Core, %[[VAL_112]] : Core) -// CHECK: aie.wire(%[[VAL_88]] : DMA, %[[VAL_112]] : DMA) -// CHECK: aie.wire(%[[VAL_111]] : North, %[[VAL_112]] : South) -// CHECK: aie.wire(%[[VAL_113:.*]] : North, %[[VAL_114:.*]] : South) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_113]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : East, %[[VAL_115:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_115]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_115]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : North, %[[VAL_115]] : South) -// CHECK: aie.wire(%[[VAL_111]] : East, %[[VAL_116:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_116]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_116]] : DMA) -// CHECK: aie.wire(%[[VAL_115]] : North, %[[VAL_116]] : South) -// CHECK: aie.wire(%[[VAL_112]] : East, %[[VAL_117:.*]] : West) -// CHECK: aie.wire(%[[VAL_90]] : Core, %[[VAL_117]] : Core) -// CHECK: aie.wire(%[[VAL_90]] : DMA, %[[VAL_117]] : DMA) -// CHECK: aie.wire(%[[VAL_116]] : North, %[[VAL_117]] : South) -// CHECK: aie.wire(%[[VAL_114]] : East, %[[VAL_118:.*]] : West) -// CHECK: aie.wire(%[[VAL_119:.*]] : North, %[[VAL_118]] : South) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_119]] : DMA) -// CHECK: aie.wire(%[[VAL_115]] : East, %[[VAL_120:.*]] : West) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_120]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_120]] : DMA) -// CHECK: aie.wire(%[[VAL_118]] : North, %[[VAL_120]] : South) -// CHECK: aie.wire(%[[VAL_116]] : East, %[[VAL_121:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_121]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_121]] : DMA) -// CHECK: aie.wire(%[[VAL_120]] : North, %[[VAL_121]] : South) -// CHECK: aie.wire(%[[VAL_117]] : East, %[[VAL_122:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_122]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_122]] : DMA) -// CHECK: aie.wire(%[[VAL_121]] : North, %[[VAL_122]] : South) -// CHECK: aie.wire(%[[VAL_121]] : East, %[[VAL_123:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_123]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_123]] : DMA) -// CHECK: aie.wire(%[[VAL_122]] : East, %[[VAL_124:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_124]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_124]] : DMA) -// CHECK: aie.wire(%[[VAL_123]] : North, %[[VAL_124]] : South) -// CHECK: } - -module @aie.herd_0 { - aie.device(xcvc1902) { - %tile_7_1 = aie.tile(7, 1) - %tile_7_0 = aie.tile(7, 0) - %tile_1_1 = aie.tile(1, 1) - %tile_8_3 = aie.tile(8, 3) - %lock_8_3 = aie.lock(%tile_8_3, 1) - %lock_8_3_0 = aie.lock(%tile_8_3, 3) - %buffer_8_3 = aie.buffer(%tile_8_3) {sym_name = "buf11"} : memref<16x16xf32, 2> - %lock_8_3_1 = aie.lock(%tile_8_3, 2) - %buffer_8_3_2 = aie.buffer(%tile_8_3) {sym_name = "buf10"} : memref<16x16xf32, 2> - %lock_8_3_3 = aie.lock(%tile_8_3, 0) - %buffer_8_3_4 = aie.buffer(%tile_8_3) {sym_name = "buf9"} : memref<16x16xf32, 2> - %mem_8_3 = aie.mem(%tile_8_3) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_8_3_3, Acquire, 0) - aie.dma_bd(%buffer_8_3_4 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_3, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_8_3, Acquire, 0) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_8_3_1, Acquire, 0) - aie.dma_bd(%buffer_8_3_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_1, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_8_3_0, Acquire, 1) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_0, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_6_2 = aie.tile(6, 2) - %tile_6_1 = aie.tile(6, 1) - %tile_6_0 = aie.tile(6, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_7_3 = aie.tile(7, 3) - %lock_7_3 = aie.lock(%tile_7_3, 1) - %lock_7_3_5 = aie.lock(%tile_7_3, 3) - %buffer_7_3 = aie.buffer(%tile_7_3) {sym_name = "buf8"} : memref<16x16xf32, 2> - %lock_7_3_6 = aie.lock(%tile_7_3, 2) - %buffer_7_3_7 = aie.buffer(%tile_7_3) {sym_name = "buf7"} : memref<16x16xf32, 2> - %lock_7_3_8 = aie.lock(%tile_7_3, 0) - %buffer_7_3_9 = aie.buffer(%tile_7_3) {sym_name = "buf6"} : memref<16x16xf32, 2> - %mem_7_3 = aie.mem(%tile_7_3) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_7_3_8, Acquire, 0) - aie.dma_bd(%buffer_7_3_9 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_8, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_7_3, Acquire, 0) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_7_3_6, Acquire, 0) - aie.dma_bd(%buffer_7_3_7 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_6, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_7_3_5, Acquire, 1) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_5, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_3_2 = aie.tile(3, 2) - %tile_3_1 = aie.tile(3, 1) - %tile_3_0 = aie.tile(3, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_8_2 = aie.tile(8, 2) - %lock_8_2 = aie.lock(%tile_8_2, 1) - %lock_8_2_10 = aie.lock(%tile_8_2, 3) - %buffer_8_2 = aie.buffer(%tile_8_2) {sym_name = "buf5"} : memref<16x16xf32, 2> - %lock_8_2_11 = aie.lock(%tile_8_2, 2) - %buffer_8_2_12 = aie.buffer(%tile_8_2) {sym_name = "buf4"} : memref<16x16xf32, 2> - %lock_8_2_13 = aie.lock(%tile_8_2, 0) - %buffer_8_2_14 = aie.buffer(%tile_8_2) {sym_name = "buf3"} : memref<16x16xf32, 2> - %mem_8_2 = aie.mem(%tile_8_2) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_8_2_13, Acquire, 0) - aie.dma_bd(%buffer_8_2_14 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_13, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_8_2, Acquire, 0) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_8_2_11, Acquire, 0) - aie.dma_bd(%buffer_8_2_12 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_11, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_8_2_10, Acquire, 1) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_10, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_2_2 = aie.tile(2, 2) - %tile_2_1 = aie.tile(2, 1) - %tile_2_0 = aie.tile(2, 0) - %tile_0_0 = aie.tile(0, 0) - %tile_7_2 = aie.tile(7, 2) - %lock_7_2 = aie.lock(%tile_7_2, 1) - %lock_7_2_15 = aie.lock(%tile_7_2, 3) - %buffer_7_2 = aie.buffer(%tile_7_2) {sym_name = "buf2"} : memref<16x16xf32, 2> - %lock_7_2_16 = aie.lock(%tile_7_2, 2) - %buffer_7_2_17 = aie.buffer(%tile_7_2) {sym_name = "buf1"} : memref<16x16xf32, 2> - %lock_7_2_18 = aie.lock(%tile_7_2, 0) - %buffer_7_2_19 = aie.buffer(%tile_7_2) {sym_name = "buf0"} : memref<16x16xf32, 2> - %mem_7_2 = aie.mem(%tile_7_2) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_7_2_18, Acquire, 0) - aie.dma_bd(%buffer_7_2_19 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_18, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_7_2, Acquire, 0) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_7_2_16, Acquire, 0) - aie.dma_bd(%buffer_7_2_17 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_16, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_7_2_15, Acquire, 1) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_15, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_2_1, South : 0, %tile_7_2, DMA : 0) - aie.flow(%tile_2_1, South : 1, %tile_7_2, DMA : 1) - aie.flow(%tile_7_2, DMA : 0, %tile_2_1, South : 0) - %switchbox_3_0 = aie.switchbox(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_3_1, South : 0, %tile_8_2, DMA : 0) - aie.flow(%tile_3_1, South : 1, %tile_8_2, DMA : 1) - aie.flow(%tile_8_2, DMA : 0, %tile_2_1, South : 1) - %switchbox_6_0 = aie.switchbox(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_6_1, South : 0, %tile_7_3, DMA : 0) - aie.flow(%tile_6_1, South : 1, %tile_7_3, DMA : 1) - aie.flow(%tile_7_3, DMA : 0, %tile_3_1, South : 0) - %switchbox_7_0 = aie.switchbox(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_7_1, South : 0, %tile_8_3, DMA : 0) - aie.flow(%tile_7_1, South : 1, %tile_8_3, DMA : 1) - aie.flow(%tile_8_3, DMA : 0, %tile_3_1, South : 1) - %shimmux_2_0 = aie.shim_mux(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_3_0 = aie.shim_mux(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_6_0 = aie.shim_mux(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_7_0 = aie.shim_mux(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - } -} diff --git a/test/create-flows/unit_more_flows_shim.mlir b/test/create-flows/unit_more_flows_shim.mlir deleted file mode 100644 index eb7480a20a..0000000000 --- a/test/create-flows/unit_more_flows_shim.mlir +++ /dev/null @@ -1,113 +0,0 @@ -//===- more_flows_shim.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// -// These tests verify pathfinder routing flows to/from PLIO in shim tiles. -// - -// RUN: aie-opt --aie-create-pathfinder-flows -split-input-file %s | FileCheck %s - -// CHECK-LABEL: test70 -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T71:.*]] = aie.tile(7, 1) -// CHECK: %[[SB70:.*]] = aie.switchbox(%[[T70]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH70:.*]] = aie.shim_mux(%[[T70]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB71:.*]] = aie.switchbox(%[[T71]]) { -// CHECK: aie.connect -// CHECK: } - -// Tile 7,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams to PLIO 2,3,4,5 -module @test70 { - aie.device(xcvc1902) { - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - aie.flow(%t71, North : 0, %t70, PLIO : 2) - } -} - -// ----- - -// CHECK-LABEL: test60 -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T61:.*]] = aie.tile(6, 1) -// CHECK: %[[SB60:.*]] = aie.switchbox(%[[T60]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH60:.*]] = aie.shim_mux(%[[T60]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB61:.*]] = aie.switchbox(%[[T61]]) { -// CHECK: aie.connect -// CHECK: } - -// Tile 6,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams from PLIO 2,3,6,7 -module @test60 { - aie.device(xcvc1902) { - %t60 = aie.tile(6, 0) - %t61 = aie.tile(6, 1) - aie.flow(%t60, PLIO : 6, %t61, DMA : 1) - } -} - -// ----- - -// CHECK-LABEL: test40 -// CHECK: %[[T40:.*]] = aie.tile(4, 0) -// CHECK: %[[T41:.*]] = aie.tile(4, 1) -// CHECK: %[[SB40:.*]] = aie.switchbox(%[[T40]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB41:.*]] = aie.switchbox(%[[T41]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } - -// Tile 4,0 is a shim PL tile and does not contain a ShimMux. -module @test40 { - aie.device(xcvc1902) { - %t40 = aie.tile(4, 0) - %t41 = aie.tile(4, 1) - aie.flow(%t41, North : 0, %t40, PLIO : 3) - aie.flow(%t40, PLIO : 4, %t41, North : 0) - } -} - -// ----- - -// CHECK-LABEL: test100 -// CHECK: %[[T100:.*]] = aie.tile(10, 0) -// CHECK: %[[T101:.*]] = aie.tile(10, 1) -// CHECK: %[[SB100:.*]] = aie.switchbox(%[[T100]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH100:.*]] = aie.shim_mux(%[[T100]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB101:.*]] = aie.switchbox(%[[T101]]) { -// CHECK: aie.connect -// CHECK: } - -// Tile 10,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams to NOC 0,1,2,3 -module @test100 { - aie.device(xcvc1902) { - %t100 = aie.tile(10, 0) - %t101 = aie.tile(10, 1) - aie.flow(%t101, North : 0, %t100, NOC : 2) - } -} - diff --git a/test/create-flows/unit_over_flows.mlir b/test/create-flows/unit_over_flows.mlir deleted file mode 100644 index add44e0609..0000000000 --- a/test/create-flows/unit_over_flows.mlir +++ /dev/null @@ -1,210 +0,0 @@ -//===- over_flows.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_9:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_13:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_15:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_16:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_17:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_26]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.shim_mux(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.shim_mux(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.shim_mux(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_42:.*]] : North, %[[VAL_43:.*]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_42]] : DMA) -// CHECK: aie.wire(%[[VAL_43]] : East, %[[VAL_44:.*]] : West) -// CHECK: aie.wire(%[[VAL_45:.*]] : North, %[[VAL_44]] : South) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_45]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_46:.*]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_46]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : North, %[[VAL_46]] : South) -// CHECK: aie.wire(%[[VAL_44]] : East, %[[VAL_47:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : East, %[[VAL_48:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_48]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_48]] : DMA) -// CHECK: aie.wire(%[[VAL_47]] : North, %[[VAL_48]] : South) -// CHECK: aie.wire(%[[VAL_48]] : East, %[[VAL_49:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_49]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_49]] : DMA) -// CHECK: aie.wire(%[[VAL_50:.*]] : North, %[[VAL_51:.*]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_50]] : DMA) -// CHECK: aie.wire(%[[VAL_49]] : East, %[[VAL_52:.*]] : West) -// CHECK: aie.wire(%[[VAL_26]] : Core, %[[VAL_52]] : Core) -// CHECK: aie.wire(%[[VAL_26]] : DMA, %[[VAL_52]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : North, %[[VAL_52]] : South) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_53:.*]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_53]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : North, %[[VAL_53]] : South) -// CHECK: aie.wire(%[[VAL_51]] : East, %[[VAL_54:.*]] : West) -// CHECK: aie.wire(%[[VAL_55:.*]] : North, %[[VAL_54]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_55]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : East, %[[VAL_56:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_56]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_54]] : North, %[[VAL_56]] : South) -// CHECK: aie.wire(%[[VAL_53]] : East, %[[VAL_57:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_57]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_56]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_58:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_57]] : North, %[[VAL_58]] : South) -// CHECK: aie.wire(%[[VAL_57]] : East, %[[VAL_59:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_59]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : East, %[[VAL_60:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_60]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_59]] : North, %[[VAL_60]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t03 = aie.tile(0, 3) - %t02 = aie.tile(0, 2) - %t00 = aie.tile(0, 0) - %t13 = aie.tile(1, 3) - %t11 = aie.tile(1, 1) - %t10 = aie.tile(1, 0) - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - %t22 = aie.tile(2, 2) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t80 = aie.tile(8, 0) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - - aie.flow(%t71, DMA : 0, %t20, DMA : 0) - aie.flow(%t71, DMA : 1, %t20, DMA : 1) - aie.flow(%t72, DMA : 0, %t60, DMA : 0) - aie.flow(%t72, DMA : 1, %t60, DMA : 1) - aie.flow(%t73, DMA : 0, %t70, DMA : 0) - aie.flow(%t73, DMA : 1, %t70, DMA : 1) - aie.flow(%t83, DMA : 0, %t30, DMA : 0) - aie.flow(%t83, DMA : 1, %t30, DMA : 1) - } -} - diff --git a/test/create-flows/unit_routed_herd_3x1.mlir b/test/create-flows/unit_routed_herd_3x1.mlir deleted file mode 100644 index e5134f00cf..0000000000 --- a/test/create-flows/unit_routed_herd_3x1.mlir +++ /dev/null @@ -1,823 +0,0 @@ -//===- routed_herd_3x1.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_13:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_20:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_21:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_22:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_23:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_24:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_25:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_26:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_27:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_28:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_29:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_30:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_31:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_33:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_34:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_35:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_36:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_37:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_40:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_41:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_42:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_43:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_44:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_45:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_46:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_47:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_49:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_50:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_51:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_52:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_53:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_54:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_55:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_56:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_57:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_58:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_59:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_60:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_61:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_62:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_63:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_64:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_65:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_66:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.switchbox(%[[VAL_18]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_19]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.switchbox(%[[VAL_20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_21]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_23]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_77:.*]] = aie.switchbox(%[[VAL_25]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_26]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_79:.*]] = aie.switchbox(%[[VAL_27]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.switchbox(%[[VAL_28]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_81:.*]] = aie.switchbox(%[[VAL_29]]) { -// CHECK: } -// CHECK: %[[VAL_82:.*]] = aie.switchbox(%[[VAL_30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_83:.*]] = aie.switchbox(%[[VAL_31]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_84:.*]] = aie.switchbox(%[[VAL_32]]) { -// CHECK: } -// CHECK: %[[VAL_85:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: } -// CHECK: %[[VAL_86:.*]] = aie.switchbox(%[[VAL_34]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_87:.*]] = aie.switchbox(%[[VAL_35]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_88:.*]] = aie.switchbox(%[[VAL_36]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_89:.*]] = aie.switchbox(%[[VAL_37]]) { -// CHECK: } -// CHECK: %[[VAL_90:.*]] = aie.switchbox(%[[VAL_38]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_91:.*]] = aie.switchbox(%[[VAL_39]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_92:.*]] = aie.switchbox(%[[VAL_40]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_93:.*]] = aie.switchbox(%[[VAL_41]]) { -// CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.switchbox(%[[VAL_42]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_95:.*]] = aie.switchbox(%[[VAL_43]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_96:.*]] = aie.switchbox(%[[VAL_44]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_97:.*]] = aie.switchbox(%[[VAL_45]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_98:.*]] = aie.switchbox(%[[VAL_46]]) { -// CHECK: } -// CHECK: %[[VAL_99:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: } -// CHECK: %[[VAL_100:.*]] = aie.switchbox(%[[VAL_48]]) { -// CHECK: } -// CHECK: %[[VAL_101:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: } -// CHECK: %[[VAL_102:.*]] = aie.switchbox(%[[VAL_50]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_103:.*]] = aie.switchbox(%[[VAL_51]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_104:.*]] = aie.switchbox(%[[VAL_52]]) { -// CHECK: } -// CHECK: %[[VAL_105:.*]] = aie.switchbox(%[[VAL_53]]) { -// CHECK: } -// CHECK: %[[VAL_106:.*]] = aie.switchbox(%[[VAL_54]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_107:.*]] = aie.switchbox(%[[VAL_55]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_108:.*]] = aie.switchbox(%[[VAL_56]]) { -// CHECK: } -// CHECK: %[[VAL_109:.*]] = aie.switchbox(%[[VAL_57]]) { -// CHECK: } -// CHECK: %[[VAL_110:.*]] = aie.switchbox(%[[VAL_58]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_111:.*]] = aie.switchbox(%[[VAL_59]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_112:.*]] = aie.switchbox(%[[VAL_60]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_113:.*]] = aie.switchbox(%[[VAL_61]]) { -// CHECK: } -// CHECK: %[[VAL_114:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_115:.*]] = aie.shim_mux(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_116:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_117:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_118:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_119:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_120:.*]] = aie.shim_mux(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_121:.*]] = aie.switchbox(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_122:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_123:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_124:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_125:.*]] = aie.shim_mux(%[[VAL_7]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_126:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_127:.*]] = aie.shim_mux(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_128:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_129:.*]] = aie.shim_mux(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_130:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_131:.*]] = aie.switchbox(%[[VAL_9]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_132:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_133:.*]] = aie.switchbox(%[[VAL_132]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_134:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_135:.*]] = aie.switchbox(%[[VAL_134]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_136:.*]] = aie.tile(14, 0) -// CHECK: %[[VAL_137:.*]] = aie.switchbox(%[[VAL_136]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.tile(15, 0) -// CHECK: %[[VAL_139:.*]] = aie.switchbox(%[[VAL_138]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_140:.*]] = aie.tile(16, 0) -// CHECK: %[[VAL_141:.*]] = aie.switchbox(%[[VAL_140]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_142:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_143:.*]] = aie.switchbox(%[[VAL_142]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_144:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_145:.*]] = aie.shim_mux(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_146:.*]] = aie.switchbox(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_147:.*]] = aie.shim_mux(%[[VAL_13]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_148:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_148]] : DMA) -// CHECK: aie.wire(%[[VAL_149:.*]] : North, %[[VAL_148]] : South) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_150:.*]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_150]] : DMA) -// CHECK: aie.wire(%[[VAL_148]] : North, %[[VAL_150]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_151:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_151]] : DMA) -// CHECK: aie.wire(%[[VAL_150]] : North, %[[VAL_151]] : South) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_152:.*]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_152]] : DMA) -// CHECK: aie.wire(%[[VAL_151]] : North, %[[VAL_152]] : South) -// CHECK: aie.wire(%[[VAL_149]] : East, %[[VAL_153:.*]] : West) -// CHECK: aie.wire(%[[VAL_148]] : East, %[[VAL_154:.*]] : West) -// CHECK: aie.wire(%[[VAL_18]] : Core, %[[VAL_154]] : Core) -// CHECK: aie.wire(%[[VAL_18]] : DMA, %[[VAL_154]] : DMA) -// CHECK: aie.wire(%[[VAL_153]] : North, %[[VAL_154]] : South) -// CHECK: aie.wire(%[[VAL_150]] : East, %[[VAL_155:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_155]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_155]] : DMA) -// CHECK: aie.wire(%[[VAL_154]] : North, %[[VAL_155]] : South) -// CHECK: aie.wire(%[[VAL_151]] : East, %[[VAL_156:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_156]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_156]] : DMA) -// CHECK: aie.wire(%[[VAL_155]] : North, %[[VAL_156]] : South) -// CHECK: aie.wire(%[[VAL_152]] : East, %[[VAL_157:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_157]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_157]] : DMA) -// CHECK: aie.wire(%[[VAL_156]] : North, %[[VAL_157]] : South) -// CHECK: aie.wire(%[[VAL_153]] : East, %[[VAL_158:.*]] : West) -// CHECK: aie.wire(%[[VAL_159:.*]] : North, %[[VAL_158]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_159]] : DMA) -// CHECK: aie.wire(%[[VAL_154]] : East, %[[VAL_160:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_160]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_160]] : DMA) -// CHECK: aie.wire(%[[VAL_158]] : North, %[[VAL_160]] : South) -// CHECK: aie.wire(%[[VAL_155]] : East, %[[VAL_161:.*]] : West) -// CHECK: aie.wire(%[[VAL_23]] : Core, %[[VAL_161]] : Core) -// CHECK: aie.wire(%[[VAL_23]] : DMA, %[[VAL_161]] : DMA) -// CHECK: aie.wire(%[[VAL_160]] : North, %[[VAL_161]] : South) -// CHECK: aie.wire(%[[VAL_156]] : East, %[[VAL_162:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_162]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_162]] : DMA) -// CHECK: aie.wire(%[[VAL_161]] : North, %[[VAL_162]] : South) -// CHECK: aie.wire(%[[VAL_157]] : East, %[[VAL_163:.*]] : West) -// CHECK: aie.wire(%[[VAL_25]] : Core, %[[VAL_163]] : Core) -// CHECK: aie.wire(%[[VAL_25]] : DMA, %[[VAL_163]] : DMA) -// CHECK: aie.wire(%[[VAL_162]] : North, %[[VAL_163]] : South) -// CHECK: aie.wire(%[[VAL_158]] : East, %[[VAL_164:.*]] : West) -// CHECK: aie.wire(%[[VAL_165:.*]] : North, %[[VAL_164]] : South) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_165]] : DMA) -// CHECK: aie.wire(%[[VAL_160]] : East, %[[VAL_166:.*]] : West) -// CHECK: aie.wire(%[[VAL_26]] : Core, %[[VAL_166]] : Core) -// CHECK: aie.wire(%[[VAL_26]] : DMA, %[[VAL_166]] : DMA) -// CHECK: aie.wire(%[[VAL_164]] : North, %[[VAL_166]] : South) -// CHECK: aie.wire(%[[VAL_161]] : East, %[[VAL_167:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_167]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_167]] : DMA) -// CHECK: aie.wire(%[[VAL_166]] : North, %[[VAL_167]] : South) -// CHECK: aie.wire(%[[VAL_162]] : East, %[[VAL_168:.*]] : West) -// CHECK: aie.wire(%[[VAL_28]] : Core, %[[VAL_168]] : Core) -// CHECK: aie.wire(%[[VAL_28]] : DMA, %[[VAL_168]] : DMA) -// CHECK: aie.wire(%[[VAL_167]] : North, %[[VAL_168]] : South) -// CHECK: aie.wire(%[[VAL_163]] : East, %[[VAL_169:.*]] : West) -// CHECK: aie.wire(%[[VAL_29]] : Core, %[[VAL_169]] : Core) -// CHECK: aie.wire(%[[VAL_29]] : DMA, %[[VAL_169]] : DMA) -// CHECK: aie.wire(%[[VAL_168]] : North, %[[VAL_169]] : South) -// CHECK: aie.wire(%[[VAL_164]] : East, %[[VAL_170:.*]] : West) -// CHECK: aie.wire(%[[VAL_166]] : East, %[[VAL_171:.*]] : West) -// CHECK: aie.wire(%[[VAL_30]] : Core, %[[VAL_171]] : Core) -// CHECK: aie.wire(%[[VAL_30]] : DMA, %[[VAL_171]] : DMA) -// CHECK: aie.wire(%[[VAL_170]] : North, %[[VAL_171]] : South) -// CHECK: aie.wire(%[[VAL_167]] : East, %[[VAL_172:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_172]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_172]] : DMA) -// CHECK: aie.wire(%[[VAL_171]] : North, %[[VAL_172]] : South) -// CHECK: aie.wire(%[[VAL_168]] : East, %[[VAL_173:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_173]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_173]] : DMA) -// CHECK: aie.wire(%[[VAL_172]] : North, %[[VAL_173]] : South) -// CHECK: aie.wire(%[[VAL_169]] : East, %[[VAL_174:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_174]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_174]] : DMA) -// CHECK: aie.wire(%[[VAL_173]] : North, %[[VAL_174]] : South) -// CHECK: aie.wire(%[[VAL_170]] : East, %[[VAL_175:.*]] : West) -// CHECK: aie.wire(%[[VAL_171]] : East, %[[VAL_176:.*]] : West) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_176]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_176]] : DMA) -// CHECK: aie.wire(%[[VAL_175]] : North, %[[VAL_176]] : South) -// CHECK: aie.wire(%[[VAL_172]] : East, %[[VAL_177:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_177]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_177]] : DMA) -// CHECK: aie.wire(%[[VAL_176]] : North, %[[VAL_177]] : South) -// CHECK: aie.wire(%[[VAL_173]] : East, %[[VAL_178:.*]] : West) -// CHECK: aie.wire(%[[VAL_36]] : Core, %[[VAL_178]] : Core) -// CHECK: aie.wire(%[[VAL_36]] : DMA, %[[VAL_178]] : DMA) -// CHECK: aie.wire(%[[VAL_177]] : North, %[[VAL_178]] : South) -// CHECK: aie.wire(%[[VAL_174]] : East, %[[VAL_179:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_179]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_179]] : DMA) -// CHECK: aie.wire(%[[VAL_178]] : North, %[[VAL_179]] : South) -// CHECK: aie.wire(%[[VAL_175]] : East, %[[VAL_180:.*]] : West) -// CHECK: aie.wire(%[[VAL_181:.*]] : North, %[[VAL_180]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_181]] : DMA) -// CHECK: aie.wire(%[[VAL_176]] : East, %[[VAL_182:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_182]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_182]] : DMA) -// CHECK: aie.wire(%[[VAL_180]] : North, %[[VAL_182]] : South) -// CHECK: aie.wire(%[[VAL_177]] : East, %[[VAL_183:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_183]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_183]] : DMA) -// CHECK: aie.wire(%[[VAL_182]] : North, %[[VAL_183]] : South) -// CHECK: aie.wire(%[[VAL_178]] : East, %[[VAL_184:.*]] : West) -// CHECK: aie.wire(%[[VAL_40]] : Core, %[[VAL_184]] : Core) -// CHECK: aie.wire(%[[VAL_40]] : DMA, %[[VAL_184]] : DMA) -// CHECK: aie.wire(%[[VAL_183]] : North, %[[VAL_184]] : South) -// CHECK: aie.wire(%[[VAL_179]] : East, %[[VAL_185:.*]] : West) -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_185]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_185]] : DMA) -// CHECK: aie.wire(%[[VAL_184]] : North, %[[VAL_185]] : South) -// CHECK: aie.wire(%[[VAL_180]] : East, %[[VAL_186:.*]] : West) -// CHECK: aie.wire(%[[VAL_187:.*]] : North, %[[VAL_186]] : South) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_187]] : DMA) -// CHECK: aie.wire(%[[VAL_182]] : East, %[[VAL_188:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_188]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_188]] : DMA) -// CHECK: aie.wire(%[[VAL_186]] : North, %[[VAL_188]] : South) -// CHECK: aie.wire(%[[VAL_183]] : East, %[[VAL_189:.*]] : West) -// CHECK: aie.wire(%[[VAL_43]] : Core, %[[VAL_189]] : Core) -// CHECK: aie.wire(%[[VAL_43]] : DMA, %[[VAL_189]] : DMA) -// CHECK: aie.wire(%[[VAL_188]] : North, %[[VAL_189]] : South) -// CHECK: aie.wire(%[[VAL_184]] : East, %[[VAL_190:.*]] : West) -// CHECK: aie.wire(%[[VAL_44]] : Core, %[[VAL_190]] : Core) -// CHECK: aie.wire(%[[VAL_44]] : DMA, %[[VAL_190]] : DMA) -// CHECK: aie.wire(%[[VAL_189]] : North, %[[VAL_190]] : South) -// CHECK: aie.wire(%[[VAL_185]] : East, %[[VAL_191:.*]] : West) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_191]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_191]] : DMA) -// CHECK: aie.wire(%[[VAL_190]] : North, %[[VAL_191]] : South) -// CHECK: aie.wire(%[[VAL_186]] : East, %[[VAL_192:.*]] : West) -// CHECK: aie.wire(%[[VAL_188]] : East, %[[VAL_193:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : Core, %[[VAL_193]] : Core) -// CHECK: aie.wire(%[[VAL_46]] : DMA, %[[VAL_193]] : DMA) -// CHECK: aie.wire(%[[VAL_192]] : North, %[[VAL_193]] : South) -// CHECK: aie.wire(%[[VAL_189]] : East, %[[VAL_194:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_194]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_194]] : DMA) -// CHECK: aie.wire(%[[VAL_193]] : North, %[[VAL_194]] : South) -// CHECK: aie.wire(%[[VAL_190]] : East, %[[VAL_195:.*]] : West) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_195]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_195]] : DMA) -// CHECK: aie.wire(%[[VAL_194]] : North, %[[VAL_195]] : South) -// CHECK: aie.wire(%[[VAL_191]] : East, %[[VAL_196:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_196]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_196]] : DMA) -// CHECK: aie.wire(%[[VAL_195]] : North, %[[VAL_196]] : South) -// CHECK: aie.wire(%[[VAL_192]] : East, %[[VAL_197:.*]] : West) -// CHECK: aie.wire(%[[VAL_193]] : East, %[[VAL_198:.*]] : West) -// CHECK: aie.wire(%[[VAL_50]] : Core, %[[VAL_198]] : Core) -// CHECK: aie.wire(%[[VAL_50]] : DMA, %[[VAL_198]] : DMA) -// CHECK: aie.wire(%[[VAL_197]] : North, %[[VAL_198]] : South) -// CHECK: aie.wire(%[[VAL_194]] : East, %[[VAL_199:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_199]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_199]] : DMA) -// CHECK: aie.wire(%[[VAL_198]] : North, %[[VAL_199]] : South) -// CHECK: aie.wire(%[[VAL_195]] : East, %[[VAL_200:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_200]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_200]] : DMA) -// CHECK: aie.wire(%[[VAL_199]] : North, %[[VAL_200]] : South) -// CHECK: aie.wire(%[[VAL_196]] : East, %[[VAL_201:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_201]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_201]] : DMA) -// CHECK: aie.wire(%[[VAL_200]] : North, %[[VAL_201]] : South) -// CHECK: aie.wire(%[[VAL_197]] : East, %[[VAL_202:.*]] : West) -// CHECK: aie.wire(%[[VAL_203:.*]] : North, %[[VAL_202]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_203]] : DMA) -// CHECK: aie.wire(%[[VAL_198]] : East, %[[VAL_204:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_204]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_204]] : DMA) -// CHECK: aie.wire(%[[VAL_202]] : North, %[[VAL_204]] : South) -// CHECK: aie.wire(%[[VAL_199]] : East, %[[VAL_205:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_205]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_205]] : DMA) -// CHECK: aie.wire(%[[VAL_204]] : North, %[[VAL_205]] : South) -// CHECK: aie.wire(%[[VAL_200]] : East, %[[VAL_206:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_206]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_206]] : DMA) -// CHECK: aie.wire(%[[VAL_205]] : North, %[[VAL_206]] : South) -// CHECK: aie.wire(%[[VAL_201]] : East, %[[VAL_207:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_207]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_207]] : DMA) -// CHECK: aie.wire(%[[VAL_206]] : North, %[[VAL_207]] : South) -// CHECK: aie.wire(%[[VAL_202]] : East, %[[VAL_208:.*]] : West) -// CHECK: aie.wire(%[[VAL_209:.*]] : North, %[[VAL_208]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_209]] : DMA) -// CHECK: aie.wire(%[[VAL_204]] : East, %[[VAL_210:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_210]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_210]] : DMA) -// CHECK: aie.wire(%[[VAL_208]] : North, %[[VAL_210]] : South) -// CHECK: aie.wire(%[[VAL_205]] : East, %[[VAL_211:.*]] : West) -// CHECK: aie.wire(%[[VAL_59]] : Core, %[[VAL_211]] : Core) -// CHECK: aie.wire(%[[VAL_59]] : DMA, %[[VAL_211]] : DMA) -// CHECK: aie.wire(%[[VAL_210]] : North, %[[VAL_211]] : South) -// CHECK: aie.wire(%[[VAL_206]] : East, %[[VAL_212:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_212]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_212]] : DMA) -// CHECK: aie.wire(%[[VAL_211]] : North, %[[VAL_212]] : South) -// CHECK: aie.wire(%[[VAL_207]] : East, %[[VAL_213:.*]] : West) -// CHECK: aie.wire(%[[VAL_61]] : Core, %[[VAL_213]] : Core) -// CHECK: aie.wire(%[[VAL_61]] : DMA, %[[VAL_213]] : DMA) -// CHECK: aie.wire(%[[VAL_212]] : North, %[[VAL_213]] : South) -// CHECK: aie.wire(%[[VAL_208]] : East, %[[VAL_214:.*]] : West) -// CHECK: aie.wire(%[[VAL_214]] : East, %[[VAL_215:.*]] : West) -// CHECK: aie.wire(%[[VAL_215]] : East, %[[VAL_216:.*]] : West) -// CHECK: aie.wire(%[[VAL_216]] : East, %[[VAL_217:.*]] : West) -// CHECK: aie.wire(%[[VAL_217]] : East, %[[VAL_218:.*]] : West) -// CHECK: aie.wire(%[[VAL_218]] : East, %[[VAL_219:.*]] : West) -// CHECK: aie.wire(%[[VAL_219]] : East, %[[VAL_220:.*]] : West) -// CHECK: aie.wire(%[[VAL_221:.*]] : North, %[[VAL_220]] : South) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_221]] : DMA) -// CHECK: aie.wire(%[[VAL_220]] : East, %[[VAL_222:.*]] : West) -// CHECK: aie.wire(%[[VAL_223:.*]] : North, %[[VAL_222]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_223]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_0_0 = aie.tile(0, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_2_0 = aie.tile(2, 0) - %tile_3_0 = aie.tile(3, 0) - %tile_4_0 = aie.tile(4, 0) - %tile_5_0 = aie.tile(5, 0) - %tile_6_0 = aie.tile(6, 0) - %tile_7_0 = aie.tile(7, 0) - %tile_8_0 = aie.tile(8, 0) - %tile_9_0 = aie.tile(9, 0) - %tile_10_0 = aie.tile(10, 0) - %tile_11_0 = aie.tile(11, 0) - %tile_18_0 = aie.tile(18, 0) - %tile_19_0 = aie.tile(19, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_0_2 = aie.tile(0, 2) - %tile_0_3 = aie.tile(0, 3) - %tile_0_4 = aie.tile(0, 4) - %tile_1_1 = aie.tile(1, 1) - %tile_1_2 = aie.tile(1, 2) - %tile_1_3 = aie.tile(1, 3) - %tile_1_4 = aie.tile(1, 4) - %tile_2_1 = aie.tile(2, 1) - %tile_2_2 = aie.tile(2, 2) - %tile_2_3 = aie.tile(2, 3) - %tile_2_4 = aie.tile(2, 4) - %tile_3_1 = aie.tile(3, 1) - %tile_3_2 = aie.tile(3, 2) - %tile_3_3 = aie.tile(3, 3) - %tile_3_4 = aie.tile(3, 4) - %tile_4_1 = aie.tile(4, 1) - %tile_4_2 = aie.tile(4, 2) - %tile_4_3 = aie.tile(4, 3) - %tile_4_4 = aie.tile(4, 4) - %tile_5_1 = aie.tile(5, 1) - %tile_5_2 = aie.tile(5, 2) - %tile_5_3 = aie.tile(5, 3) - %tile_5_4 = aie.tile(5, 4) - %tile_6_1 = aie.tile(6, 1) - %tile_6_2 = aie.tile(6, 2) - %tile_6_3 = aie.tile(6, 3) - %tile_6_4 = aie.tile(6, 4) - %tile_7_1 = aie.tile(7, 1) - %tile_7_2 = aie.tile(7, 2) - %tile_7_3 = aie.tile(7, 3) - %tile_7_4 = aie.tile(7, 4) - %tile_8_1 = aie.tile(8, 1) - %tile_8_2 = aie.tile(8, 2) - %tile_8_3 = aie.tile(8, 3) - %tile_8_4 = aie.tile(8, 4) - %tile_9_1 = aie.tile(9, 1) - %tile_9_2 = aie.tile(9, 2) - %tile_9_3 = aie.tile(9, 3) - %tile_9_4 = aie.tile(9, 4) - %tile_10_1 = aie.tile(10, 1) - %tile_10_2 = aie.tile(10, 2) - %tile_10_3 = aie.tile(10, 3) - %tile_10_4 = aie.tile(10, 4) - %tile_11_1 = aie.tile(11, 1) - %tile_11_2 = aie.tile(11, 2) - %tile_11_3 = aie.tile(11, 3) - %tile_11_4 = aie.tile(11, 4) - %tile_12_1 = aie.tile(12, 1) - %tile_12_2 = aie.tile(12, 2) - %tile_12_3 = aie.tile(12, 3) - %tile_12_4 = aie.tile(12, 4) - %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - } - %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - } - %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect - } - %switchbox_0_4 = aie.switchbox(%tile_0_4) { - } - %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - } - %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - } - %switchbox_1_3 = aie.switchbox(%tile_1_3) { - aie.connect - } - %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect - } - %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - } - %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect - } - %switchbox_2_3 = aie.switchbox(%tile_2_3) { - aie.connect - } - %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect - } - %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - } - %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect - } - %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - } - %switchbox_3_4 = aie.switchbox(%tile_3_4) { - } - %switchbox_4_1 = aie.switchbox(%tile_4_1) { - aie.connect - } - %switchbox_4_2 = aie.switchbox(%tile_4_2) { - aie.connect - } - %switchbox_4_3 = aie.switchbox(%tile_4_3) { - } - %switchbox_4_4 = aie.switchbox(%tile_4_4) { - } - %switchbox_5_1 = aie.switchbox(%tile_5_1) { - aie.connect - } - %switchbox_5_2 = aie.switchbox(%tile_5_2) { - aie.connect - } - %switchbox_5_3 = aie.switchbox(%tile_5_3) { - aie.connect - } - %switchbox_5_4 = aie.switchbox(%tile_5_4) { - } - %switchbox_6_1 = aie.switchbox(%tile_6_1) { - aie.connect - aie.connect - } - %switchbox_6_2 = aie.switchbox(%tile_6_2) { - aie.connect - aie.connect - } - %switchbox_6_3 = aie.switchbox(%tile_6_3) { - aie.connect - aie.connect - } - %switchbox_6_4 = aie.switchbox(%tile_6_4) { - } - %switchbox_7_1 = aie.switchbox(%tile_7_1) { - aie.connect - aie.connect - } - %switchbox_7_2 = aie.switchbox(%tile_7_2) { - aie.connect - aie.connect - } - %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect - } - %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - aie.connect - } - %switchbox_8_1 = aie.switchbox(%tile_8_1) { - } - %switchbox_8_2 = aie.switchbox(%tile_8_2) { - } - %switchbox_8_3 = aie.switchbox(%tile_8_3) { - } - %switchbox_8_4 = aie.switchbox(%tile_8_4) { - } - %switchbox_9_1 = aie.switchbox(%tile_9_1) { - aie.connect - } - %switchbox_9_2 = aie.switchbox(%tile_9_2) { - aie.connect - } - %switchbox_9_3 = aie.switchbox(%tile_9_3) { - } - %switchbox_9_4 = aie.switchbox(%tile_9_4) { - } - %switchbox_10_1 = aie.switchbox(%tile_10_1) { - aie.connect - } - %switchbox_10_2 = aie.switchbox(%tile_10_2) { - aie.connect - } - %switchbox_10_3 = aie.switchbox(%tile_10_3) { - } - %switchbox_10_4 = aie.switchbox(%tile_10_4) { - } - %switchbox_11_1 = aie.switchbox(%tile_11_1) { - aie.connect - aie.connect - } - %switchbox_11_2 = aie.switchbox(%tile_11_2) { - aie.connect - aie.connect - } - %switchbox_11_3 = aie.switchbox(%tile_11_3) { - aie.connect - aie.connect - } - %switchbox_11_4 = aie.switchbox(%tile_11_4) { - } - aie.flow(%tile_2_0, DMA : 0, %tile_2_0, North : 0) - aie.flow(%tile_2_0, DMA : 1, %tile_6_0, North : 1) - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_3_0, DMA : 1, %tile_7_0, North : 1) - aie.flow(%tile_6_0, DMA : 0, %tile_0_0, North : 0) - aie.flow(%tile_6_0, DMA : 1, %tile_4_0, North : 0) - aie.flow(%tile_7_0, DMA : 0, %tile_1_0, North : 0) - aie.flow(%tile_7_0, DMA : 1, %tile_5_0, North : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_10_0, North : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_11_0, North : 0) - aie.flow(%tile_18_0, DMA : 0, %tile_6_0, North : 0) - aie.flow(%tile_18_0, DMA : 1, %tile_9_0, North : 0) - aie.flow(%tile_19_0, DMA : 0, %tile_7_0, North : 0) - aie.flow(%tile_19_0, DMA : 1, %tile_11_0, North : 1) - } -} diff --git a/test/create-flows/unit_routed_herd_3x2.mlir b/test/create-flows/unit_routed_herd_3x2.mlir deleted file mode 100644 index da4a174ed5..0000000000 --- a/test/create-flows/unit_routed_herd_3x2.mlir +++ /dev/null @@ -1,1018 +0,0 @@ -//===- routed_herd_3x2.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_13:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(0, 5) -// CHECK: %[[VAL_19:.*]] = aie.tile(0, 6) -// CHECK: %[[VAL_20:.*]] = aie.tile(0, 7) -// CHECK: %[[VAL_21:.*]] = aie.tile(0, 8) -// CHECK: %[[VAL_22:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_23:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_24:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_25:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_26:.*]] = aie.tile(1, 5) -// CHECK: %[[VAL_27:.*]] = aie.tile(1, 6) -// CHECK: %[[VAL_28:.*]] = aie.tile(1, 7) -// CHECK: %[[VAL_29:.*]] = aie.tile(1, 8) -// CHECK: %[[VAL_30:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_31:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_33:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_34:.*]] = aie.tile(2, 5) -// CHECK: %[[VAL_35:.*]] = aie.tile(2, 6) -// CHECK: %[[VAL_36:.*]] = aie.tile(2, 7) -// CHECK: %[[VAL_37:.*]] = aie.tile(2, 8) -// CHECK: %[[VAL_38:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_39:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_40:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_41:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_42:.*]] = aie.tile(3, 5) -// CHECK: %[[VAL_43:.*]] = aie.tile(3, 6) -// CHECK: %[[VAL_44:.*]] = aie.tile(3, 7) -// CHECK: %[[VAL_45:.*]] = aie.tile(3, 8) -// CHECK: %[[VAL_46:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_47:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_50:.*]] = aie.tile(4, 5) -// CHECK: %[[VAL_51:.*]] = aie.tile(4, 6) -// CHECK: %[[VAL_52:.*]] = aie.tile(4, 7) -// CHECK: %[[VAL_53:.*]] = aie.tile(4, 8) -// CHECK: %[[VAL_54:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_55:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_56:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_57:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_58:.*]] = aie.tile(5, 5) -// CHECK: %[[VAL_59:.*]] = aie.tile(5, 6) -// CHECK: %[[VAL_60:.*]] = aie.tile(5, 7) -// CHECK: %[[VAL_61:.*]] = aie.tile(5, 8) -// CHECK: %[[VAL_62:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_63:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_64:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_65:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_66:.*]] = aie.tile(6, 5) -// CHECK: %[[VAL_67:.*]] = aie.tile(6, 6) -// CHECK: %[[VAL_68:.*]] = aie.tile(6, 7) -// CHECK: %[[VAL_69:.*]] = aie.tile(6, 8) -// CHECK: %[[VAL_70:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_71:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_72:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_73:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_74:.*]] = aie.tile(7, 5) -// CHECK: %[[VAL_75:.*]] = aie.tile(7, 6) -// CHECK: %[[VAL_76:.*]] = aie.tile(7, 7) -// CHECK: %[[VAL_77:.*]] = aie.tile(7, 8) -// CHECK: %[[VAL_78:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_79:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_80:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_81:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_82:.*]] = aie.tile(8, 5) -// CHECK: %[[VAL_83:.*]] = aie.tile(8, 6) -// CHECK: %[[VAL_84:.*]] = aie.tile(8, 7) -// CHECK: %[[VAL_85:.*]] = aie.tile(8, 8) -// CHECK: %[[VAL_86:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_87:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_88:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_89:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_90:.*]] = aie.tile(9, 5) -// CHECK: %[[VAL_91:.*]] = aie.tile(9, 6) -// CHECK: %[[VAL_92:.*]] = aie.tile(9, 7) -// CHECK: %[[VAL_93:.*]] = aie.tile(9, 8) -// CHECK: %[[VAL_94:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_95:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_96:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_97:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_98:.*]] = aie.tile(10, 5) -// CHECK: %[[VAL_99:.*]] = aie.tile(10, 6) -// CHECK: %[[VAL_100:.*]] = aie.tile(10, 7) -// CHECK: %[[VAL_101:.*]] = aie.tile(10, 8) -// CHECK: %[[VAL_102:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_103:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_104:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_105:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_106:.*]] = aie.tile(11, 5) -// CHECK: %[[VAL_107:.*]] = aie.tile(11, 6) -// CHECK: %[[VAL_108:.*]] = aie.tile(11, 7) -// CHECK: %[[VAL_109:.*]] = aie.tile(11, 8) -// CHECK: %[[VAL_110:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_111:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_112:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_113:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_114:.*]] = aie.tile(12, 5) -// CHECK: %[[VAL_115:.*]] = aie.tile(12, 6) -// CHECK: %[[VAL_116:.*]] = aie.tile(12, 7) -// CHECK: %[[VAL_117:.*]] = aie.tile(12, 8) -// CHECK: %[[VAL_118:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_119:.*]] = aie.tile(13, 1) -// CHECK: %[[VAL_120:.*]] = aie.tile(13, 2) -// CHECK: %[[VAL_121:.*]] = aie.tile(13, 3) -// CHECK: %[[VAL_122:.*]] = aie.tile(13, 4) -// CHECK: %[[VAL_123:.*]] = aie.tile(13, 5) -// CHECK: %[[VAL_124:.*]] = aie.tile(13, 6) -// CHECK: %[[VAL_125:.*]] = aie.tile(13, 7) -// CHECK: %[[VAL_126:.*]] = aie.tile(13, 8) -// CHECK: %[[VAL_127:.*]] = aie.tile(14, 1) -// CHECK: %[[VAL_128:.*]] = aie.tile(14, 2) -// CHECK: %[[VAL_129:.*]] = aie.tile(14, 3) -// CHECK: %[[VAL_130:.*]] = aie.tile(14, 4) -// CHECK: %[[VAL_131:.*]] = aie.tile(14, 5) -// CHECK: %[[VAL_132:.*]] = aie.tile(14, 6) -// CHECK: %[[VAL_133:.*]] = aie.tile(14, 7) -// CHECK: %[[VAL_134:.*]] = aie.tile(14, 8) -// CHECK: %[[VAL_135:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: } -// CHECK: %[[VAL_136:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: } -// CHECK: %[[VAL_137:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: } -// CHECK: %[[VAL_139:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: } -// CHECK: %[[VAL_140:.*]] = aie.switchbox(%[[VAL_23]]) { -// CHECK: } -// CHECK: %[[VAL_141:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: } -// CHECK: %[[VAL_142:.*]] = aie.switchbox(%[[VAL_25]]) { -// CHECK: } -// CHECK: %[[VAL_143:.*]] = aie.switchbox(%[[VAL_30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_144:.*]] = aie.switchbox(%[[VAL_31]]) { -// CHECK: } -// CHECK: %[[VAL_145:.*]] = aie.switchbox(%[[VAL_32]]) { -// CHECK: } -// CHECK: %[[VAL_146:.*]] = aie.switchbox(%[[VAL_33]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_147:.*]] = aie.switchbox(%[[VAL_34]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_148:.*]] = aie.switchbox(%[[VAL_38]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_149:.*]] = aie.switchbox(%[[VAL_39]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_150:.*]] = aie.switchbox(%[[VAL_40]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_151:.*]] = aie.switchbox(%[[VAL_41]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_152:.*]] = aie.switchbox(%[[VAL_42]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_153:.*]] = aie.switchbox(%[[VAL_46]]) { -// CHECK: } -// CHECK: %[[VAL_154:.*]] = aie.switchbox(%[[VAL_47]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_155:.*]] = aie.switchbox(%[[VAL_48]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_156:.*]] = aie.switchbox(%[[VAL_49]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_157:.*]] = aie.switchbox(%[[VAL_54]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_158:.*]] = aie.switchbox(%[[VAL_55]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_159:.*]] = aie.switchbox(%[[VAL_56]]) { -// CHECK: } -// CHECK: %[[VAL_160:.*]] = aie.switchbox(%[[VAL_57]]) { -// CHECK: } -// CHECK: %[[VAL_161:.*]] = aie.switchbox(%[[VAL_58]]) { -// CHECK: } -// CHECK: %[[VAL_162:.*]] = aie.switchbox(%[[VAL_59]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_163:.*]] = aie.switchbox(%[[VAL_62]]) { -// CHECK: } -// CHECK: %[[VAL_164:.*]] = aie.switchbox(%[[VAL_63]]) { -// CHECK: } -// CHECK: %[[VAL_165:.*]] = aie.switchbox(%[[VAL_64]]) { -// CHECK: } -// CHECK: %[[VAL_166:.*]] = aie.switchbox(%[[VAL_65]]) { -// CHECK: } -// CHECK: %[[VAL_167:.*]] = aie.switchbox(%[[VAL_66]]) { -// CHECK: } -// CHECK: %[[VAL_168:.*]] = aie.switchbox(%[[VAL_67]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_169:.*]] = aie.switchbox(%[[VAL_70]]) { -// CHECK: } -// CHECK: %[[VAL_170:.*]] = aie.switchbox(%[[VAL_71]]) { -// CHECK: } -// CHECK: %[[VAL_171:.*]] = aie.switchbox(%[[VAL_72]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_172:.*]] = aie.switchbox(%[[VAL_73]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_173:.*]] = aie.switchbox(%[[VAL_74]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_174:.*]] = aie.switchbox(%[[VAL_75]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_175:.*]] = aie.switchbox(%[[VAL_78]]) { -// CHECK: } -// CHECK: %[[VAL_176:.*]] = aie.switchbox(%[[VAL_79]]) { -// CHECK: } -// CHECK: %[[VAL_177:.*]] = aie.switchbox(%[[VAL_80]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_178:.*]] = aie.switchbox(%[[VAL_81]]) { -// CHECK: } -// CHECK: %[[VAL_179:.*]] = aie.switchbox(%[[VAL_86]]) { -// CHECK: } -// CHECK: %[[VAL_180:.*]] = aie.switchbox(%[[VAL_87]]) { -// CHECK: } -// CHECK: %[[VAL_181:.*]] = aie.switchbox(%[[VAL_88]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_182:.*]] = aie.switchbox(%[[VAL_89]]) { -// CHECK: } -// CHECK: %[[VAL_183:.*]] = aie.switchbox(%[[VAL_94]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_184:.*]] = aie.switchbox(%[[VAL_95]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_185:.*]] = aie.switchbox(%[[VAL_96]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_186:.*]] = aie.switchbox(%[[VAL_97]]) { -// CHECK: } -// CHECK: %[[VAL_187:.*]] = aie.switchbox(%[[VAL_102]]) { -// CHECK: } -// CHECK: %[[VAL_188:.*]] = aie.switchbox(%[[VAL_103]]) { -// CHECK: } -// CHECK: %[[VAL_189:.*]] = aie.switchbox(%[[VAL_104]]) { -// CHECK: } -// CHECK: %[[VAL_190:.*]] = aie.switchbox(%[[VAL_105]]) { -// CHECK: } -// CHECK: %[[VAL_191:.*]] = aie.switchbox(%[[VAL_110]]) { -// CHECK: } -// CHECK: %[[VAL_192:.*]] = aie.switchbox(%[[VAL_111]]) { -// CHECK: } -// CHECK: %[[VAL_193:.*]] = aie.switchbox(%[[VAL_112]]) { -// CHECK: } -// CHECK: %[[VAL_194:.*]] = aie.switchbox(%[[VAL_113]]) { -// CHECK: } -// CHECK: %[[VAL_195:.*]] = aie.switchbox(%[[VAL_114]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_196:.*]] = aie.switchbox(%[[VAL_119]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_197:.*]] = aie.switchbox(%[[VAL_120]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_198:.*]] = aie.switchbox(%[[VAL_121]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_199:.*]] = aie.switchbox(%[[VAL_122]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_200:.*]] = aie.switchbox(%[[VAL_123]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_201:.*]] = aie.switchbox(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_202:.*]] = aie.shim_mux(%[[VAL_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_203:.*]] = aie.switchbox(%[[VAL_50]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_204:.*]] = aie.switchbox(%[[VAL_5]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_205:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_206:.*]] = aie.shim_mux(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_207:.*]] = aie.switchbox(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_208:.*]] = aie.shim_mux(%[[VAL_10]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_209:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_210:.*]] = aie.shim_mux(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_211:.*]] = aie.switchbox(%[[VAL_51]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_212:.*]] = aie.switchbox(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_213:.*]] = aie.shim_mux(%[[VAL_11]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_214:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_215:.*]] = aie.switchbox(%[[VAL_214]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_216:.*]] = aie.switchbox(%[[VAL_118]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_217:.*]] = aie.switchbox(%[[VAL_128]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_218:.*]] = aie.switchbox(%[[VAL_129]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_219:.*]] = aie.switchbox(%[[VAL_130]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_220:.*]] = aie.switchbox(%[[VAL_131]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_221:.*]] = aie.tile(15, 2) -// CHECK: %[[VAL_222:.*]] = aie.switchbox(%[[VAL_221]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_223:.*]] = aie.tile(16, 2) -// CHECK: %[[VAL_224:.*]] = aie.switchbox(%[[VAL_223]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_225:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_226:.*]] = aie.switchbox(%[[VAL_225]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_227:.*]] = aie.tile(17, 1) -// CHECK: %[[VAL_228:.*]] = aie.switchbox(%[[VAL_227]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_229:.*]] = aie.tile(17, 2) -// CHECK: %[[VAL_230:.*]] = aie.switchbox(%[[VAL_229]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_231:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_232:.*]] = aie.shim_mux(%[[VAL_12]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_233:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_233]] : DMA) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_234:.*]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_234]] : DMA) -// CHECK: aie.wire(%[[VAL_233]] : North, %[[VAL_234]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_235:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_235]] : DMA) -// CHECK: aie.wire(%[[VAL_234]] : North, %[[VAL_235]] : South) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_236:.*]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_236]] : DMA) -// CHECK: aie.wire(%[[VAL_235]] : North, %[[VAL_236]] : South) -// CHECK: aie.wire(%[[VAL_233]] : East, %[[VAL_237:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_237]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_237]] : DMA) -// CHECK: aie.wire(%[[VAL_234]] : East, %[[VAL_238:.*]] : West) -// CHECK: aie.wire(%[[VAL_23]] : Core, %[[VAL_238]] : Core) -// CHECK: aie.wire(%[[VAL_23]] : DMA, %[[VAL_238]] : DMA) -// CHECK: aie.wire(%[[VAL_237]] : North, %[[VAL_238]] : South) -// CHECK: aie.wire(%[[VAL_235]] : East, %[[VAL_239:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_239]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_239]] : DMA) -// CHECK: aie.wire(%[[VAL_238]] : North, %[[VAL_239]] : South) -// CHECK: aie.wire(%[[VAL_236]] : East, %[[VAL_240:.*]] : West) -// CHECK: aie.wire(%[[VAL_25]] : Core, %[[VAL_240]] : Core) -// CHECK: aie.wire(%[[VAL_25]] : DMA, %[[VAL_240]] : DMA) -// CHECK: aie.wire(%[[VAL_239]] : North, %[[VAL_240]] : South) -// CHECK: aie.wire(%[[VAL_241:.*]] : North, %[[VAL_242:.*]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_241]] : DMA) -// CHECK: aie.wire(%[[VAL_237]] : East, %[[VAL_243:.*]] : West) -// CHECK: aie.wire(%[[VAL_30]] : Core, %[[VAL_243]] : Core) -// CHECK: aie.wire(%[[VAL_30]] : DMA, %[[VAL_243]] : DMA) -// CHECK: aie.wire(%[[VAL_242]] : North, %[[VAL_243]] : South) -// CHECK: aie.wire(%[[VAL_238]] : East, %[[VAL_244:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_244]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_244]] : DMA) -// CHECK: aie.wire(%[[VAL_243]] : North, %[[VAL_244]] : South) -// CHECK: aie.wire(%[[VAL_239]] : East, %[[VAL_245:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_245]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_245]] : DMA) -// CHECK: aie.wire(%[[VAL_244]] : North, %[[VAL_245]] : South) -// CHECK: aie.wire(%[[VAL_240]] : East, %[[VAL_246:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_246]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_246]] : DMA) -// CHECK: aie.wire(%[[VAL_245]] : North, %[[VAL_246]] : South) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_247:.*]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_247]] : DMA) -// CHECK: aie.wire(%[[VAL_246]] : North, %[[VAL_247]] : South) -// CHECK: aie.wire(%[[VAL_242]] : East, %[[VAL_248:.*]] : West) -// CHECK: aie.wire(%[[VAL_249:.*]] : North, %[[VAL_248]] : South) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_249]] : DMA) -// CHECK: aie.wire(%[[VAL_243]] : East, %[[VAL_250:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_250]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_250]] : DMA) -// CHECK: aie.wire(%[[VAL_248]] : North, %[[VAL_250]] : South) -// CHECK: aie.wire(%[[VAL_244]] : East, %[[VAL_251:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_251]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_251]] : DMA) -// CHECK: aie.wire(%[[VAL_250]] : North, %[[VAL_251]] : South) -// CHECK: aie.wire(%[[VAL_245]] : East, %[[VAL_252:.*]] : West) -// CHECK: aie.wire(%[[VAL_40]] : Core, %[[VAL_252]] : Core) -// CHECK: aie.wire(%[[VAL_40]] : DMA, %[[VAL_252]] : DMA) -// CHECK: aie.wire(%[[VAL_251]] : North, %[[VAL_252]] : South) -// CHECK: aie.wire(%[[VAL_246]] : East, %[[VAL_253:.*]] : West) -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_253]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_253]] : DMA) -// CHECK: aie.wire(%[[VAL_252]] : North, %[[VAL_253]] : South) -// CHECK: aie.wire(%[[VAL_247]] : East, %[[VAL_254:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_254]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_254]] : DMA) -// CHECK: aie.wire(%[[VAL_253]] : North, %[[VAL_254]] : South) -// CHECK: aie.wire(%[[VAL_250]] : East, %[[VAL_255:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : Core, %[[VAL_255]] : Core) -// CHECK: aie.wire(%[[VAL_46]] : DMA, %[[VAL_255]] : DMA) -// CHECK: aie.wire(%[[VAL_251]] : East, %[[VAL_256:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_256]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_256]] : DMA) -// CHECK: aie.wire(%[[VAL_255]] : North, %[[VAL_256]] : South) -// CHECK: aie.wire(%[[VAL_252]] : East, %[[VAL_257:.*]] : West) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_257]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_257]] : DMA) -// CHECK: aie.wire(%[[VAL_256]] : North, %[[VAL_257]] : South) -// CHECK: aie.wire(%[[VAL_253]] : East, %[[VAL_258:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_258]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_258]] : DMA) -// CHECK: aie.wire(%[[VAL_257]] : North, %[[VAL_258]] : South) -// CHECK: aie.wire(%[[VAL_254]] : East, %[[VAL_259:.*]] : West) -// CHECK: aie.wire(%[[VAL_50]] : Core, %[[VAL_259]] : Core) -// CHECK: aie.wire(%[[VAL_50]] : DMA, %[[VAL_259]] : DMA) -// CHECK: aie.wire(%[[VAL_258]] : North, %[[VAL_259]] : South) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_260:.*]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_260]] : DMA) -// CHECK: aie.wire(%[[VAL_259]] : North, %[[VAL_260]] : South) -// CHECK: aie.wire(%[[VAL_255]] : East, %[[VAL_261:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_261]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_261]] : DMA) -// CHECK: aie.wire(%[[VAL_262:.*]] : North, %[[VAL_261]] : South) -// CHECK: aie.wire(%[[VAL_256]] : East, %[[VAL_263:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_263]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_263]] : DMA) -// CHECK: aie.wire(%[[VAL_261]] : North, %[[VAL_263]] : South) -// CHECK: aie.wire(%[[VAL_257]] : East, %[[VAL_264:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_264]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_264]] : DMA) -// CHECK: aie.wire(%[[VAL_263]] : North, %[[VAL_264]] : South) -// CHECK: aie.wire(%[[VAL_258]] : East, %[[VAL_265:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_265]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_265]] : DMA) -// CHECK: aie.wire(%[[VAL_264]] : North, %[[VAL_265]] : South) -// CHECK: aie.wire(%[[VAL_259]] : East, %[[VAL_266:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_266]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_266]] : DMA) -// CHECK: aie.wire(%[[VAL_265]] : North, %[[VAL_266]] : South) -// CHECK: aie.wire(%[[VAL_260]] : East, %[[VAL_267:.*]] : West) -// CHECK: aie.wire(%[[VAL_59]] : Core, %[[VAL_267]] : Core) -// CHECK: aie.wire(%[[VAL_59]] : DMA, %[[VAL_267]] : DMA) -// CHECK: aie.wire(%[[VAL_266]] : North, %[[VAL_267]] : South) -// CHECK: aie.wire(%[[VAL_262]] : East, %[[VAL_268:.*]] : West) -// CHECK: aie.wire(%[[VAL_269:.*]] : North, %[[VAL_268]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_269]] : DMA) -// CHECK: aie.wire(%[[VAL_261]] : East, %[[VAL_270:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : Core, %[[VAL_270]] : Core) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_270]] : DMA) -// CHECK: aie.wire(%[[VAL_268]] : North, %[[VAL_270]] : South) -// CHECK: aie.wire(%[[VAL_263]] : East, %[[VAL_271:.*]] : West) -// CHECK: aie.wire(%[[VAL_63]] : Core, %[[VAL_271]] : Core) -// CHECK: aie.wire(%[[VAL_63]] : DMA, %[[VAL_271]] : DMA) -// CHECK: aie.wire(%[[VAL_270]] : North, %[[VAL_271]] : South) -// CHECK: aie.wire(%[[VAL_264]] : East, %[[VAL_272:.*]] : West) -// CHECK: aie.wire(%[[VAL_64]] : Core, %[[VAL_272]] : Core) -// CHECK: aie.wire(%[[VAL_64]] : DMA, %[[VAL_272]] : DMA) -// CHECK: aie.wire(%[[VAL_271]] : North, %[[VAL_272]] : South) -// CHECK: aie.wire(%[[VAL_265]] : East, %[[VAL_273:.*]] : West) -// CHECK: aie.wire(%[[VAL_65]] : Core, %[[VAL_273]] : Core) -// CHECK: aie.wire(%[[VAL_65]] : DMA, %[[VAL_273]] : DMA) -// CHECK: aie.wire(%[[VAL_272]] : North, %[[VAL_273]] : South) -// CHECK: aie.wire(%[[VAL_266]] : East, %[[VAL_274:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_274]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_274]] : DMA) -// CHECK: aie.wire(%[[VAL_273]] : North, %[[VAL_274]] : South) -// CHECK: aie.wire(%[[VAL_267]] : East, %[[VAL_275:.*]] : West) -// CHECK: aie.wire(%[[VAL_67]] : Core, %[[VAL_275]] : Core) -// CHECK: aie.wire(%[[VAL_67]] : DMA, %[[VAL_275]] : DMA) -// CHECK: aie.wire(%[[VAL_274]] : North, %[[VAL_275]] : South) -// CHECK: aie.wire(%[[VAL_270]] : East, %[[VAL_276:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_276]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_276]] : DMA) -// CHECK: aie.wire(%[[VAL_271]] : East, %[[VAL_277:.*]] : West) -// CHECK: aie.wire(%[[VAL_71]] : Core, %[[VAL_277]] : Core) -// CHECK: aie.wire(%[[VAL_71]] : DMA, %[[VAL_277]] : DMA) -// CHECK: aie.wire(%[[VAL_276]] : North, %[[VAL_277]] : South) -// CHECK: aie.wire(%[[VAL_272]] : East, %[[VAL_278:.*]] : West) -// CHECK: aie.wire(%[[VAL_72]] : Core, %[[VAL_278]] : Core) -// CHECK: aie.wire(%[[VAL_72]] : DMA, %[[VAL_278]] : DMA) -// CHECK: aie.wire(%[[VAL_277]] : North, %[[VAL_278]] : South) -// CHECK: aie.wire(%[[VAL_273]] : East, %[[VAL_279:.*]] : West) -// CHECK: aie.wire(%[[VAL_73]] : Core, %[[VAL_279]] : Core) -// CHECK: aie.wire(%[[VAL_73]] : DMA, %[[VAL_279]] : DMA) -// CHECK: aie.wire(%[[VAL_278]] : North, %[[VAL_279]] : South) -// CHECK: aie.wire(%[[VAL_274]] : East, %[[VAL_280:.*]] : West) -// CHECK: aie.wire(%[[VAL_74]] : Core, %[[VAL_280]] : Core) -// CHECK: aie.wire(%[[VAL_74]] : DMA, %[[VAL_280]] : DMA) -// CHECK: aie.wire(%[[VAL_279]] : North, %[[VAL_280]] : South) -// CHECK: aie.wire(%[[VAL_275]] : East, %[[VAL_281:.*]] : West) -// CHECK: aie.wire(%[[VAL_75]] : Core, %[[VAL_281]] : Core) -// CHECK: aie.wire(%[[VAL_75]] : DMA, %[[VAL_281]] : DMA) -// CHECK: aie.wire(%[[VAL_280]] : North, %[[VAL_281]] : South) -// CHECK: aie.wire(%[[VAL_276]] : East, %[[VAL_282:.*]] : West) -// CHECK: aie.wire(%[[VAL_78]] : Core, %[[VAL_282]] : Core) -// CHECK: aie.wire(%[[VAL_78]] : DMA, %[[VAL_282]] : DMA) -// CHECK: aie.wire(%[[VAL_277]] : East, %[[VAL_283:.*]] : West) -// CHECK: aie.wire(%[[VAL_79]] : Core, %[[VAL_283]] : Core) -// CHECK: aie.wire(%[[VAL_79]] : DMA, %[[VAL_283]] : DMA) -// CHECK: aie.wire(%[[VAL_282]] : North, %[[VAL_283]] : South) -// CHECK: aie.wire(%[[VAL_278]] : East, %[[VAL_284:.*]] : West) -// CHECK: aie.wire(%[[VAL_80]] : Core, %[[VAL_284]] : Core) -// CHECK: aie.wire(%[[VAL_80]] : DMA, %[[VAL_284]] : DMA) -// CHECK: aie.wire(%[[VAL_283]] : North, %[[VAL_284]] : South) -// CHECK: aie.wire(%[[VAL_279]] : East, %[[VAL_285:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : Core, %[[VAL_285]] : Core) -// CHECK: aie.wire(%[[VAL_81]] : DMA, %[[VAL_285]] : DMA) -// CHECK: aie.wire(%[[VAL_284]] : North, %[[VAL_285]] : South) -// CHECK: aie.wire(%[[VAL_282]] : East, %[[VAL_286:.*]] : West) -// CHECK: aie.wire(%[[VAL_86]] : Core, %[[VAL_286]] : Core) -// CHECK: aie.wire(%[[VAL_86]] : DMA, %[[VAL_286]] : DMA) -// CHECK: aie.wire(%[[VAL_283]] : East, %[[VAL_287:.*]] : West) -// CHECK: aie.wire(%[[VAL_87]] : Core, %[[VAL_287]] : Core) -// CHECK: aie.wire(%[[VAL_87]] : DMA, %[[VAL_287]] : DMA) -// CHECK: aie.wire(%[[VAL_286]] : North, %[[VAL_287]] : South) -// CHECK: aie.wire(%[[VAL_284]] : East, %[[VAL_288:.*]] : West) -// CHECK: aie.wire(%[[VAL_88]] : Core, %[[VAL_288]] : Core) -// CHECK: aie.wire(%[[VAL_88]] : DMA, %[[VAL_288]] : DMA) -// CHECK: aie.wire(%[[VAL_287]] : North, %[[VAL_288]] : South) -// CHECK: aie.wire(%[[VAL_285]] : East, %[[VAL_289:.*]] : West) -// CHECK: aie.wire(%[[VAL_89]] : Core, %[[VAL_289]] : Core) -// CHECK: aie.wire(%[[VAL_89]] : DMA, %[[VAL_289]] : DMA) -// CHECK: aie.wire(%[[VAL_288]] : North, %[[VAL_289]] : South) -// CHECK: aie.wire(%[[VAL_290:.*]] : North, %[[VAL_291:.*]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_290]] : DMA) -// CHECK: aie.wire(%[[VAL_286]] : East, %[[VAL_292:.*]] : West) -// CHECK: aie.wire(%[[VAL_94]] : Core, %[[VAL_292]] : Core) -// CHECK: aie.wire(%[[VAL_94]] : DMA, %[[VAL_292]] : DMA) -// CHECK: aie.wire(%[[VAL_291]] : North, %[[VAL_292]] : South) -// CHECK: aie.wire(%[[VAL_287]] : East, %[[VAL_293:.*]] : West) -// CHECK: aie.wire(%[[VAL_95]] : Core, %[[VAL_293]] : Core) -// CHECK: aie.wire(%[[VAL_95]] : DMA, %[[VAL_293]] : DMA) -// CHECK: aie.wire(%[[VAL_292]] : North, %[[VAL_293]] : South) -// CHECK: aie.wire(%[[VAL_288]] : East, %[[VAL_294:.*]] : West) -// CHECK: aie.wire(%[[VAL_96]] : Core, %[[VAL_294]] : Core) -// CHECK: aie.wire(%[[VAL_96]] : DMA, %[[VAL_294]] : DMA) -// CHECK: aie.wire(%[[VAL_293]] : North, %[[VAL_294]] : South) -// CHECK: aie.wire(%[[VAL_289]] : East, %[[VAL_295:.*]] : West) -// CHECK: aie.wire(%[[VAL_97]] : Core, %[[VAL_295]] : Core) -// CHECK: aie.wire(%[[VAL_97]] : DMA, %[[VAL_295]] : DMA) -// CHECK: aie.wire(%[[VAL_294]] : North, %[[VAL_295]] : South) -// CHECK: aie.wire(%[[VAL_291]] : East, %[[VAL_296:.*]] : West) -// CHECK: aie.wire(%[[VAL_297:.*]] : North, %[[VAL_296]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_297]] : DMA) -// CHECK: aie.wire(%[[VAL_292]] : East, %[[VAL_298:.*]] : West) -// CHECK: aie.wire(%[[VAL_102]] : Core, %[[VAL_298]] : Core) -// CHECK: aie.wire(%[[VAL_102]] : DMA, %[[VAL_298]] : DMA) -// CHECK: aie.wire(%[[VAL_296]] : North, %[[VAL_298]] : South) -// CHECK: aie.wire(%[[VAL_293]] : East, %[[VAL_299:.*]] : West) -// CHECK: aie.wire(%[[VAL_103]] : Core, %[[VAL_299]] : Core) -// CHECK: aie.wire(%[[VAL_103]] : DMA, %[[VAL_299]] : DMA) -// CHECK: aie.wire(%[[VAL_298]] : North, %[[VAL_299]] : South) -// CHECK: aie.wire(%[[VAL_294]] : East, %[[VAL_300:.*]] : West) -// CHECK: aie.wire(%[[VAL_104]] : Core, %[[VAL_300]] : Core) -// CHECK: aie.wire(%[[VAL_104]] : DMA, %[[VAL_300]] : DMA) -// CHECK: aie.wire(%[[VAL_299]] : North, %[[VAL_300]] : South) -// CHECK: aie.wire(%[[VAL_295]] : East, %[[VAL_301:.*]] : West) -// CHECK: aie.wire(%[[VAL_105]] : Core, %[[VAL_301]] : Core) -// CHECK: aie.wire(%[[VAL_105]] : DMA, %[[VAL_301]] : DMA) -// CHECK: aie.wire(%[[VAL_300]] : North, %[[VAL_301]] : South) -// CHECK: aie.wire(%[[VAL_296]] : East, %[[VAL_302:.*]] : West) -// CHECK: aie.wire(%[[VAL_298]] : East, %[[VAL_303:.*]] : West) -// CHECK: aie.wire(%[[VAL_110]] : Core, %[[VAL_303]] : Core) -// CHECK: aie.wire(%[[VAL_110]] : DMA, %[[VAL_303]] : DMA) -// CHECK: aie.wire(%[[VAL_302]] : North, %[[VAL_303]] : South) -// CHECK: aie.wire(%[[VAL_299]] : East, %[[VAL_304:.*]] : West) -// CHECK: aie.wire(%[[VAL_111]] : Core, %[[VAL_304]] : Core) -// CHECK: aie.wire(%[[VAL_111]] : DMA, %[[VAL_304]] : DMA) -// CHECK: aie.wire(%[[VAL_303]] : North, %[[VAL_304]] : South) -// CHECK: aie.wire(%[[VAL_300]] : East, %[[VAL_305:.*]] : West) -// CHECK: aie.wire(%[[VAL_112]] : Core, %[[VAL_305]] : Core) -// CHECK: aie.wire(%[[VAL_112]] : DMA, %[[VAL_305]] : DMA) -// CHECK: aie.wire(%[[VAL_304]] : North, %[[VAL_305]] : South) -// CHECK: aie.wire(%[[VAL_301]] : East, %[[VAL_306:.*]] : West) -// CHECK: aie.wire(%[[VAL_113]] : Core, %[[VAL_306]] : Core) -// CHECK: aie.wire(%[[VAL_113]] : DMA, %[[VAL_306]] : DMA) -// CHECK: aie.wire(%[[VAL_305]] : North, %[[VAL_306]] : South) -// CHECK: aie.wire(%[[VAL_114]] : Core, %[[VAL_307:.*]] : Core) -// CHECK: aie.wire(%[[VAL_114]] : DMA, %[[VAL_307]] : DMA) -// CHECK: aie.wire(%[[VAL_306]] : North, %[[VAL_307]] : South) -// CHECK: aie.wire(%[[VAL_302]] : East, %[[VAL_308:.*]] : West) -// CHECK: aie.wire(%[[VAL_303]] : East, %[[VAL_309:.*]] : West) -// CHECK: aie.wire(%[[VAL_119]] : Core, %[[VAL_309]] : Core) -// CHECK: aie.wire(%[[VAL_119]] : DMA, %[[VAL_309]] : DMA) -// CHECK: aie.wire(%[[VAL_308]] : North, %[[VAL_309]] : South) -// CHECK: aie.wire(%[[VAL_304]] : East, %[[VAL_310:.*]] : West) -// CHECK: aie.wire(%[[VAL_120]] : Core, %[[VAL_310]] : Core) -// CHECK: aie.wire(%[[VAL_120]] : DMA, %[[VAL_310]] : DMA) -// CHECK: aie.wire(%[[VAL_309]] : North, %[[VAL_310]] : South) -// CHECK: aie.wire(%[[VAL_305]] : East, %[[VAL_311:.*]] : West) -// CHECK: aie.wire(%[[VAL_121]] : Core, %[[VAL_311]] : Core) -// CHECK: aie.wire(%[[VAL_121]] : DMA, %[[VAL_311]] : DMA) -// CHECK: aie.wire(%[[VAL_310]] : North, %[[VAL_311]] : South) -// CHECK: aie.wire(%[[VAL_306]] : East, %[[VAL_312:.*]] : West) -// CHECK: aie.wire(%[[VAL_122]] : Core, %[[VAL_312]] : Core) -// CHECK: aie.wire(%[[VAL_122]] : DMA, %[[VAL_312]] : DMA) -// CHECK: aie.wire(%[[VAL_311]] : North, %[[VAL_312]] : South) -// CHECK: aie.wire(%[[VAL_307]] : East, %[[VAL_313:.*]] : West) -// CHECK: aie.wire(%[[VAL_123]] : Core, %[[VAL_313]] : Core) -// CHECK: aie.wire(%[[VAL_123]] : DMA, %[[VAL_313]] : DMA) -// CHECK: aie.wire(%[[VAL_312]] : North, %[[VAL_313]] : South) -// CHECK: aie.wire(%[[VAL_310]] : East, %[[VAL_314:.*]] : West) -// CHECK: aie.wire(%[[VAL_128]] : Core, %[[VAL_314]] : Core) -// CHECK: aie.wire(%[[VAL_128]] : DMA, %[[VAL_314]] : DMA) -// CHECK: aie.wire(%[[VAL_311]] : East, %[[VAL_315:.*]] : West) -// CHECK: aie.wire(%[[VAL_129]] : Core, %[[VAL_315]] : Core) -// CHECK: aie.wire(%[[VAL_129]] : DMA, %[[VAL_315]] : DMA) -// CHECK: aie.wire(%[[VAL_314]] : North, %[[VAL_315]] : South) -// CHECK: aie.wire(%[[VAL_312]] : East, %[[VAL_316:.*]] : West) -// CHECK: aie.wire(%[[VAL_130]] : Core, %[[VAL_316]] : Core) -// CHECK: aie.wire(%[[VAL_130]] : DMA, %[[VAL_316]] : DMA) -// CHECK: aie.wire(%[[VAL_315]] : North, %[[VAL_316]] : South) -// CHECK: aie.wire(%[[VAL_313]] : East, %[[VAL_317:.*]] : West) -// CHECK: aie.wire(%[[VAL_131]] : Core, %[[VAL_317]] : Core) -// CHECK: aie.wire(%[[VAL_131]] : DMA, %[[VAL_317]] : DMA) -// CHECK: aie.wire(%[[VAL_316]] : North, %[[VAL_317]] : South) -// CHECK: aie.wire(%[[VAL_314]] : East, %[[VAL_318:.*]] : West) -// CHECK: aie.wire(%[[VAL_221]] : Core, %[[VAL_318]] : Core) -// CHECK: aie.wire(%[[VAL_221]] : DMA, %[[VAL_318]] : DMA) -// CHECK: aie.wire(%[[VAL_318]] : East, %[[VAL_319:.*]] : West) -// CHECK: aie.wire(%[[VAL_223]] : Core, %[[VAL_319]] : Core) -// CHECK: aie.wire(%[[VAL_223]] : DMA, %[[VAL_319]] : DMA) -// CHECK: aie.wire(%[[VAL_227]] : Core, %[[VAL_320:.*]] : Core) -// CHECK: aie.wire(%[[VAL_227]] : DMA, %[[VAL_320]] : DMA) -// CHECK: aie.wire(%[[VAL_321:.*]] : North, %[[VAL_320]] : South) -// CHECK: aie.wire(%[[VAL_319]] : East, %[[VAL_322:.*]] : West) -// CHECK: aie.wire(%[[VAL_229]] : Core, %[[VAL_322]] : Core) -// CHECK: aie.wire(%[[VAL_229]] : DMA, %[[VAL_322]] : DMA) -// CHECK: aie.wire(%[[VAL_320]] : North, %[[VAL_322]] : South) -// CHECK: aie.wire(%[[VAL_321]] : East, %[[VAL_323:.*]] : West) -// CHECK: aie.wire(%[[VAL_324:.*]] : North, %[[VAL_323]] : South) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_324]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_0_0 = aie.tile(0, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_2_0 = aie.tile(2, 0) - %tile_3_0 = aie.tile(3, 0) - %tile_4_0 = aie.tile(4, 0) - %tile_5_0 = aie.tile(5, 0) - %tile_6_0 = aie.tile(6, 0) - %tile_7_0 = aie.tile(7, 0) - %tile_8_0 = aie.tile(8, 0) - %tile_9_0 = aie.tile(9, 0) - %tile_10_0 = aie.tile(10, 0) - %tile_11_0 = aie.tile(11, 0) - %tile_18_0 = aie.tile(18, 0) - %tile_19_0 = aie.tile(19, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_0_2 = aie.tile(0, 2) - %tile_0_3 = aie.tile(0, 3) - %tile_0_4 = aie.tile(0, 4) - %tile_0_5 = aie.tile(0, 5) - %tile_0_6 = aie.tile(0, 6) - %tile_0_7 = aie.tile(0, 7) - %tile_0_8 = aie.tile(0, 8) - %tile_1_1 = aie.tile(1, 1) - %tile_1_2 = aie.tile(1, 2) - %tile_1_3 = aie.tile(1, 3) - %tile_1_4 = aie.tile(1, 4) - %tile_1_5 = aie.tile(1, 5) - %tile_1_6 = aie.tile(1, 6) - %tile_1_7 = aie.tile(1, 7) - %tile_1_8 = aie.tile(1, 8) - %tile_2_1 = aie.tile(2, 1) - %tile_2_2 = aie.tile(2, 2) - %tile_2_3 = aie.tile(2, 3) - %tile_2_4 = aie.tile(2, 4) - %tile_2_5 = aie.tile(2, 5) - %tile_2_6 = aie.tile(2, 6) - %tile_2_7 = aie.tile(2, 7) - %tile_2_8 = aie.tile(2, 8) - %tile_3_1 = aie.tile(3, 1) - %tile_3_2 = aie.tile(3, 2) - %tile_3_3 = aie.tile(3, 3) - %tile_3_4 = aie.tile(3, 4) - %tile_3_5 = aie.tile(3, 5) - %tile_3_6 = aie.tile(3, 6) - %tile_3_7 = aie.tile(3, 7) - %tile_3_8 = aie.tile(3, 8) - %tile_4_1 = aie.tile(4, 1) - %tile_4_2 = aie.tile(4, 2) - %tile_4_3 = aie.tile(4, 3) - %tile_4_4 = aie.tile(4, 4) - %tile_4_5 = aie.tile(4, 5) - %tile_4_6 = aie.tile(4, 6) - %tile_4_7 = aie.tile(4, 7) - %tile_4_8 = aie.tile(4, 8) - %tile_5_1 = aie.tile(5, 1) - %tile_5_2 = aie.tile(5, 2) - %tile_5_3 = aie.tile(5, 3) - %tile_5_4 = aie.tile(5, 4) - %tile_5_5 = aie.tile(5, 5) - %tile_5_6 = aie.tile(5, 6) - %tile_5_7 = aie.tile(5, 7) - %tile_5_8 = aie.tile(5, 8) - %tile_6_1 = aie.tile(6, 1) - %tile_6_2 = aie.tile(6, 2) - %tile_6_3 = aie.tile(6, 3) - %tile_6_4 = aie.tile(6, 4) - %tile_6_5 = aie.tile(6, 5) - %tile_6_6 = aie.tile(6, 6) - %tile_6_7 = aie.tile(6, 7) - %tile_6_8 = aie.tile(6, 8) - %tile_7_1 = aie.tile(7, 1) - %tile_7_2 = aie.tile(7, 2) - %tile_7_3 = aie.tile(7, 3) - %tile_7_4 = aie.tile(7, 4) - %tile_7_5 = aie.tile(7, 5) - %tile_7_6 = aie.tile(7, 6) - %tile_7_7 = aie.tile(7, 7) - %tile_7_8 = aie.tile(7, 8) - %tile_8_1 = aie.tile(8, 1) - %tile_8_2 = aie.tile(8, 2) - %tile_8_3 = aie.tile(8, 3) - %tile_8_4 = aie.tile(8, 4) - %tile_8_5 = aie.tile(8, 5) - %tile_8_6 = aie.tile(8, 6) - %tile_8_7 = aie.tile(8, 7) - %tile_8_8 = aie.tile(8, 8) - %tile_9_1 = aie.tile(9, 1) - %tile_9_2 = aie.tile(9, 2) - %tile_9_3 = aie.tile(9, 3) - %tile_9_4 = aie.tile(9, 4) - %tile_9_5 = aie.tile(9, 5) - %tile_9_6 = aie.tile(9, 6) - %tile_9_7 = aie.tile(9, 7) - %tile_9_8 = aie.tile(9, 8) - %tile_10_1 = aie.tile(10, 1) - %tile_10_2 = aie.tile(10, 2) - %tile_10_3 = aie.tile(10, 3) - %tile_10_4 = aie.tile(10, 4) - %tile_10_5 = aie.tile(10, 5) - %tile_10_6 = aie.tile(10, 6) - %tile_10_7 = aie.tile(10, 7) - %tile_10_8 = aie.tile(10, 8) - %tile_11_1 = aie.tile(11, 1) - %tile_11_2 = aie.tile(11, 2) - %tile_11_3 = aie.tile(11, 3) - %tile_11_4 = aie.tile(11, 4) - %tile_11_5 = aie.tile(11, 5) - %tile_11_6 = aie.tile(11, 6) - %tile_11_7 = aie.tile(11, 7) - %tile_11_8 = aie.tile(11, 8) - %tile_12_1 = aie.tile(12, 1) - %tile_12_2 = aie.tile(12, 2) - %tile_12_3 = aie.tile(12, 3) - %tile_12_4 = aie.tile(12, 4) - %tile_12_5 = aie.tile(12, 5) - %tile_12_6 = aie.tile(12, 6) - %tile_12_7 = aie.tile(12, 7) - %tile_12_8 = aie.tile(12, 8) - %tile_13_0 = aie.tile(13, 0) - %tile_13_1 = aie.tile(13, 1) - %tile_13_2 = aie.tile(13, 2) - %tile_13_3 = aie.tile(13, 3) - %tile_13_4 = aie.tile(13, 4) - %tile_13_5 = aie.tile(13, 5) - %tile_13_6 = aie.tile(13, 6) - %tile_13_7 = aie.tile(13, 7) - %tile_13_8 = aie.tile(13, 8) - %tile_14_1 = aie.tile(14, 1) - %tile_14_2 = aie.tile(14, 2) - %tile_14_3 = aie.tile(14, 3) - %tile_14_4 = aie.tile(14, 4) - %tile_14_5 = aie.tile(14, 5) - %tile_14_6 = aie.tile(14, 6) - %tile_14_7 = aie.tile(14, 7) - %tile_14_8 = aie.tile(14, 8) - %switchbox_0_1 = aie.switchbox(%tile_0_1) { - } - %switchbox_0_2 = aie.switchbox(%tile_0_2) { - } - %switchbox_0_3 = aie.switchbox(%tile_0_3) { - } - %switchbox_0_4 = aie.switchbox(%tile_0_4) { - } - %switchbox_1_1 = aie.switchbox(%tile_1_1) { - } - %switchbox_1_2 = aie.switchbox(%tile_1_2) { - } - %switchbox_1_3 = aie.switchbox(%tile_1_3) { - } - %switchbox_1_4 = aie.switchbox(%tile_1_4) { - } - %switchbox_2_1 = aie.switchbox(%tile_2_1) { - } - %switchbox_2_2 = aie.switchbox(%tile_2_2) { - } - %switchbox_2_3 = aie.switchbox(%tile_2_3) { - } - %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect - } - %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect - } - %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect - } - %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect - } - %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - } - %switchbox_3_4 = aie.switchbox(%tile_3_4) { - aie.connect - } - %switchbox_3_5 = aie.switchbox(%tile_3_5) { - aie.connect - } - %switchbox_4_1 = aie.switchbox(%tile_4_1) { - } - %switchbox_4_2 = aie.switchbox(%tile_4_2) { - } - %switchbox_4_3 = aie.switchbox(%tile_4_3) { - } - %switchbox_4_4 = aie.switchbox(%tile_4_4) { - } - %switchbox_5_1 = aie.switchbox(%tile_5_1) { - } - %switchbox_5_2 = aie.switchbox(%tile_5_2) { - } - %switchbox_5_3 = aie.switchbox(%tile_5_3) { - } - %switchbox_5_4 = aie.switchbox(%tile_5_4) { - } - %switchbox_5_5 = aie.switchbox(%tile_5_5) { - } - %switchbox_5_6 = aie.switchbox(%tile_5_6) { - aie.connect - } - %switchbox_6_1 = aie.switchbox(%tile_6_1) { - } - %switchbox_6_2 = aie.switchbox(%tile_6_2) { - } - %switchbox_6_3 = aie.switchbox(%tile_6_3) { - } - %switchbox_6_4 = aie.switchbox(%tile_6_4) { - } - %switchbox_6_5 = aie.switchbox(%tile_6_5) { - } - %switchbox_6_6 = aie.switchbox(%tile_6_6) { - aie.connect - aie.connect - } - %switchbox_7_1 = aie.switchbox(%tile_7_1) { - } - %switchbox_7_2 = aie.switchbox(%tile_7_2) { - } - %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect - } - %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - } - %switchbox_7_5 = aie.switchbox(%tile_7_5) { - aie.connect - } - %switchbox_7_6 = aie.switchbox(%tile_7_6) { - aie.connect - } - %switchbox_8_1 = aie.switchbox(%tile_8_1) { - } - %switchbox_8_2 = aie.switchbox(%tile_8_2) { - } - %switchbox_8_3 = aie.switchbox(%tile_8_3) { - aie.connect - } - %switchbox_8_4 = aie.switchbox(%tile_8_4) { - } - %switchbox_9_1 = aie.switchbox(%tile_9_1) { - } - %switchbox_9_2 = aie.switchbox(%tile_9_2) { - } - %switchbox_9_3 = aie.switchbox(%tile_9_3) { - } - %switchbox_9_4 = aie.switchbox(%tile_9_4) { - } - %switchbox_10_1 = aie.switchbox(%tile_10_1) { - } - %switchbox_10_2 = aie.switchbox(%tile_10_2) { - } - %switchbox_10_3 = aie.switchbox(%tile_10_3) { - } - %switchbox_10_4 = aie.switchbox(%tile_10_4) { - } - %switchbox_11_1 = aie.switchbox(%tile_11_1) { - } - %switchbox_11_2 = aie.switchbox(%tile_11_2) { - } - %switchbox_11_3 = aie.switchbox(%tile_11_3) { - } - %switchbox_11_4 = aie.switchbox(%tile_11_4) { - } - %switchbox_12_1 = aie.switchbox(%tile_12_1) { - } - %switchbox_12_2 = aie.switchbox(%tile_12_2) { - } - %switchbox_12_3 = aie.switchbox(%tile_12_3) { - } - %switchbox_12_4 = aie.switchbox(%tile_12_4) { - } - %switchbox_12_5 = aie.switchbox(%tile_12_5) { - aie.connect - aie.connect - } - %switchbox_13_1 = aie.switchbox(%tile_13_1) { - aie.connect - } - %switchbox_13_2 = aie.switchbox(%tile_13_2) { - aie.connect - } - %switchbox_13_3 = aie.switchbox(%tile_13_3) { - aie.connect - aie.connect - } - %switchbox_13_4 = aie.switchbox(%tile_13_4) { - aie.connect - } - %switchbox_13_5 = aie.switchbox(%tile_13_5) { - aie.connect - aie.connect - } - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_4_5, West : 0, %tile_6_0, DMA : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_9_3, West : 0) - aie.flow(%tile_4_6, East : 0, %tile_2_0, DMA : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_13_0, North : 0) - aie.flow(%tile_14_5, West : 0, %tile_18_0, DMA : 0) - } -} diff --git a/test/create-flows/unit_simple.mlir b/test/create-flows/unit_simple.mlir deleted file mode 100644 index e6934e5cb7..0000000000 --- a/test/create-flows/unit_simple.mlir +++ /dev/null @@ -1,53 +0,0 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows="route-circuit=true route-packet=false" %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.packet_flow(16) { -// CHECK: aie.packet_source<%[[VAL_0]], Core : 0> -// CHECK: aie.packet_dest<%[[VAL_1]], Core : 0> -// CHECK: aie.packet_dest<%[[VAL_2]], DMA : 1> -// CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_6:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_6]] : DMA) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_7:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_7]] : DMA) -// CHECK: aie.wire(%[[VAL_6]] : North, %[[VAL_7]] : South) -// CHECK: aie.wire(%[[VAL_7]] : East, %[[VAL_8:.*]] : West) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_8]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_8]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %01 = aie.tile(0, 1) - %12 = aie.tile(1, 2) - %02 = aie.tile(0, 2) - aie.flow(%01, DMA : 0, %12, Core : 1) - aie.packet_flow(0x10) { - aie.packet_source < %01, Core : 0> - aie.packet_dest < %12, Core : 0> - aie.packet_dest < %02, DMA : 1> - } - } -} diff --git a/test/create-flows/unit_simple2.mlir b/test/create-flows/unit_simple2.mlir deleted file mode 100644 index 4736105db8..0000000000 --- a/test/create-flows/unit_simple2.mlir +++ /dev/null @@ -1,42 +0,0 @@ -//===- simple2.mlir --------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_6:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_6]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_7:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_7]] : DMA) -// CHECK: aie.wire(%[[VAL_6]] : North, %[[VAL_7]] : South) -// CHECK: aie.wire(%[[VAL_6]] : East, %[[VAL_8:.*]] : West) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_8]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_8]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %0 = aie.tile(2, 3) - %1 = aie.tile(3, 2) - aie.flow(%0, Core : 1, %1, DMA : 0) - } -} diff --git a/test/create-flows/unit_simple_flows.mlir b/test/create-flows/unit_simple_flows.mlir deleted file mode 100644 index b4459995f3..0000000000 --- a/test/create-flows/unit_simple_flows.mlir +++ /dev/null @@ -1,40 +0,0 @@ -//===- simple_flows.mlir ---------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_4:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_4]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_5:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_5]] : DMA) -// CHECK: aie.wire(%[[VAL_4]] : North, %[[VAL_5]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t23 = aie.tile(2, 3) - %t22 = aie.tile(2, 2) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 1, %t23, Core : 1) - } -} diff --git a/test/create-flows/unit_simple_flows2.mlir b/test/create-flows/unit_simple_flows2.mlir deleted file mode 100644 index bcbbdf3f92..0000000000 --- a/test/create-flows/unit_simple_flows2.mlir +++ /dev/null @@ -1,52 +0,0 @@ -//===- simple_flows2.mlir --------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_7:.*]] = aie.switchbox(%[[VAL_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_8:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_8]] : DMA) -// CHECK: aie.wire(%[[VAL_8]] : East, %[[VAL_9:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_9]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_9]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_10:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_10]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : North, %[[VAL_10]] : South) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_11:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_11]] : DMA) -// CHECK: aie.wire(%[[VAL_10]] : North, %[[VAL_11]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t23 = aie.tile(2, 3) - %t22 = aie.tile(2, 2) - %t11 = aie.tile(1, 1) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t11, Core : 0) - } -} diff --git a/test/create-flows/unit_simple_flows_shim.mlir b/test/create-flows/unit_simple_flows_shim.mlir deleted file mode 100644 index cc2fae8436..0000000000 --- a/test/create-flows/unit_simple_flows_shim.mlir +++ /dev/null @@ -1,74 +0,0 @@ -//===- simple_flows_shim.mlir ----------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --split-input-file --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: module -// CHECK: %[[T21:.*]] = aie.tile(2, 1) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T21]]) { -// CHECK: aie.connect -// CHECK: } -module { - aie.device(xcvc1902) { - %t23 = aie.tile(2, 1) - %t22 = aie.tile(2, 0) - aie.flow(%t23, North : 0, %t22, PLIO : 0) - } -} - -// ----- - -// CHECK: module -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T21:.*]] = aie.tile(2, 1) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T21]]) { -// CHECK: aie.connect -// CHECK: } -module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - aie.flow(%t21, Core : 0, %t20, DMA : 1) - } -} - -// ----- - -// CHECK: module -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } -module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - aie.flow(%t20, DMA : 0, %t30, DMA : 1) - } -} diff --git a/test/create-flows/unit_vecmul_4x4.mlir b/test/create-flows/unit_vecmul_4x4.mlir deleted file mode 100644 index 2aaf794ca1..0000000000 --- a/test/create-flows/unit_vecmul_4x4.mlir +++ /dev/null @@ -1,3864 +0,0 @@ -//===- vecmul_4x4.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(47, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(47, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(47, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(10, 5) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_4]], 2) -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf47"} : memref<64xi32, 2> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_4]], 1) -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf46"} : memref<64xi32, 2> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_4]], 0) -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf45"} : memref<64xi32, 2> -// CHECK: %[[VAL_11:.*]] = aie.mem(%[[VAL_4]]) { -// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.core(%[[VAL_4]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: affine.for %[[VAL_16:.*]] = 0 to 64 { -// CHECK: %[[VAL_17:.*]] = affine.load %[[VAL_10]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> -// CHECK: %[[VAL_18:.*]] = affine.load %[[VAL_8]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> -// CHECK: %[[VAL_19:.*]] = arith.muli %[[VAL_17]], %[[VAL_18]] : i32 -// CHECK: affine.store %[[VAL_19]], %[[VAL_6]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.tile(46, 2) -// CHECK: %[[VAL_21:.*]] = aie.tile(46, 1) -// CHECK: %[[VAL_22:.*]] = aie.tile(46, 0) -// CHECK: %[[VAL_23:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_24:.*]] = aie.tile(9, 5) -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_24]], 2) -// CHECK: %[[VAL_26:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf44"} : memref<64xi32, 2> -// CHECK: %[[VAL_27:.*]] = aie.lock(%[[VAL_24]], 1) -// CHECK: %[[VAL_28:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf43"} : memref<64xi32, 2> -// CHECK: %[[VAL_29:.*]] = aie.lock(%[[VAL_24]], 0) -// CHECK: %[[VAL_30:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf42"} : memref<64xi32, 2> -// CHECK: %[[VAL_31:.*]] = aie.mem(%[[VAL_24]]) { -// CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_29]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_30]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_29]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_33:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_28]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_27]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_34:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_25]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.core(%[[VAL_24]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_29]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 0) -// CHECK: affine.for %[[VAL_36:.*]] = 0 to 64 { -// CHECK: %[[VAL_37:.*]] = affine.load %[[VAL_30]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> -// CHECK: %[[VAL_38:.*]] = affine.load %[[VAL_28]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> -// CHECK: %[[VAL_39:.*]] = arith.muli %[[VAL_37]], %[[VAL_38]] : i32 -// CHECK: affine.store %[[VAL_39]], %[[VAL_26]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_25]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_27]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_29]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.tile(43, 2) -// CHECK: %[[VAL_41:.*]] = aie.tile(43, 1) -// CHECK: %[[VAL_42:.*]] = aie.tile(43, 0) -// CHECK: %[[VAL_43:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_44:.*]] = aie.tile(8, 5) -// CHECK: %[[VAL_45:.*]] = aie.lock(%[[VAL_44]], 2) -// CHECK: %[[VAL_46:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf41"} : memref<64xi32, 2> -// CHECK: %[[VAL_47:.*]] = aie.lock(%[[VAL_44]], 1) -// CHECK: %[[VAL_48:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf40"} : memref<64xi32, 2> -// CHECK: %[[VAL_49:.*]] = aie.lock(%[[VAL_44]], 0) -// CHECK: %[[VAL_50:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf39"} : memref<64xi32, 2> -// CHECK: %[[VAL_51:.*]] = aie.mem(%[[VAL_44]]) { -// CHECK: %[[VAL_52:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_49]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_50]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_49]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_53:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_47]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_48]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_47]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_54:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_45]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_46]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_45]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.core(%[[VAL_44]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_49]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_47]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_45]], Acquire, 0) -// CHECK: affine.for %[[VAL_56:.*]] = 0 to 64 { -// CHECK: %[[VAL_57:.*]] = affine.load %[[VAL_50]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> -// CHECK: %[[VAL_58:.*]] = affine.load %[[VAL_48]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> -// CHECK: %[[VAL_59:.*]] = arith.muli %[[VAL_57]], %[[VAL_58]] : i32 -// CHECK: affine.store %[[VAL_59]], %[[VAL_46]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_45]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_47]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_49]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(42, 2) -// CHECK: %[[VAL_61:.*]] = aie.tile(42, 1) -// CHECK: %[[VAL_62:.*]] = aie.tile(42, 0) -// CHECK: %[[VAL_63:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_64:.*]] = aie.tile(7, 5) -// CHECK: %[[VAL_65:.*]] = aie.lock(%[[VAL_64]], 2) -// CHECK: %[[VAL_66:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf38"} : memref<64xi32, 2> -// CHECK: %[[VAL_67:.*]] = aie.lock(%[[VAL_64]], 1) -// CHECK: %[[VAL_68:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf37"} : memref<64xi32, 2> -// CHECK: %[[VAL_69:.*]] = aie.lock(%[[VAL_64]], 0) -// CHECK: %[[VAL_70:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf36"} : memref<64xi32, 2> -// CHECK: %[[VAL_71:.*]] = aie.mem(%[[VAL_64]]) { -// CHECK: %[[VAL_72:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_69]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_70]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_69]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_67]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_68]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_67]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_74:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_65]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_66]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_65]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.core(%[[VAL_64]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_69]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_67]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_65]], Acquire, 0) -// CHECK: affine.for %[[VAL_76:.*]] = 0 to 64 { -// CHECK: %[[VAL_77:.*]] = affine.load %[[VAL_70]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> -// CHECK: %[[VAL_78:.*]] = affine.load %[[VAL_68]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> -// CHECK: %[[VAL_79:.*]] = arith.muli %[[VAL_77]], %[[VAL_78]] : i32 -// CHECK: affine.store %[[VAL_79]], %[[VAL_66]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_65]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_67]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_69]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.tile(35, 2) -// CHECK: %[[VAL_81:.*]] = aie.tile(35, 1) -// CHECK: %[[VAL_82:.*]] = aie.tile(35, 0) -// CHECK: %[[VAL_83:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_84:.*]] = aie.lock(%[[VAL_83]], 2) -// CHECK: %[[VAL_85:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf35"} : memref<64xi32, 2> -// CHECK: %[[VAL_86:.*]] = aie.lock(%[[VAL_83]], 1) -// CHECK: %[[VAL_87:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf34"} : memref<64xi32, 2> -// CHECK: %[[VAL_88:.*]] = aie.lock(%[[VAL_83]], 0) -// CHECK: %[[VAL_89:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf33"} : memref<64xi32, 2> -// CHECK: %[[VAL_90:.*]] = aie.mem(%[[VAL_83]]) { -// CHECK: %[[VAL_91:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_88]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_89]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_88]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_92:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_86]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_87]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_86]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_93:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_84]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_85]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_84]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.core(%[[VAL_83]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_88]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_86]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_84]], Acquire, 0) -// CHECK: affine.for %[[VAL_95:.*]] = 0 to 64 { -// CHECK: %[[VAL_96:.*]] = affine.load %[[VAL_89]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> -// CHECK: %[[VAL_97:.*]] = affine.load %[[VAL_87]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> -// CHECK: %[[VAL_98:.*]] = arith.muli %[[VAL_96]], %[[VAL_97]] : i32 -// CHECK: affine.store %[[VAL_98]], %[[VAL_85]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_84]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_86]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_88]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_99:.*]] = aie.tile(34, 2) -// CHECK: %[[VAL_100:.*]] = aie.tile(34, 1) -// CHECK: %[[VAL_101:.*]] = aie.tile(34, 0) -// CHECK: %[[VAL_102:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_103:.*]] = aie.lock(%[[VAL_102]], 2) -// CHECK: %[[VAL_104:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf32"} : memref<64xi32, 2> -// CHECK: %[[VAL_105:.*]] = aie.lock(%[[VAL_102]], 1) -// CHECK: %[[VAL_106:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf31"} : memref<64xi32, 2> -// CHECK: %[[VAL_107:.*]] = aie.lock(%[[VAL_102]], 0) -// CHECK: %[[VAL_108:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf30"} : memref<64xi32, 2> -// CHECK: %[[VAL_109:.*]] = aie.mem(%[[VAL_102]]) { -// CHECK: %[[VAL_110:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_107]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_108]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_107]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_111:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_105]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_106]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_105]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_112:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_103]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_104]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_103]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_113:.*]] = aie.core(%[[VAL_102]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_107]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_105]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_103]], Acquire, 0) -// CHECK: affine.for %[[VAL_114:.*]] = 0 to 64 { -// CHECK: %[[VAL_115:.*]] = affine.load %[[VAL_108]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> -// CHECK: %[[VAL_116:.*]] = affine.load %[[VAL_106]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> -// CHECK: %[[VAL_117:.*]] = arith.muli %[[VAL_115]], %[[VAL_116]] : i32 -// CHECK: affine.store %[[VAL_117]], %[[VAL_104]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_103]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_105]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_107]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_118:.*]] = aie.tile(27, 2) -// CHECK: %[[VAL_119:.*]] = aie.tile(27, 1) -// CHECK: %[[VAL_120:.*]] = aie.tile(27, 0) -// CHECK: %[[VAL_121:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_122:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_123:.*]] = aie.lock(%[[VAL_122]], 2) -// CHECK: %[[VAL_124:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf29"} : memref<64xi32, 2> -// CHECK: %[[VAL_125:.*]] = aie.lock(%[[VAL_122]], 1) -// CHECK: %[[VAL_126:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf28"} : memref<64xi32, 2> -// CHECK: %[[VAL_127:.*]] = aie.lock(%[[VAL_122]], 0) -// CHECK: %[[VAL_128:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf27"} : memref<64xi32, 2> -// CHECK: %[[VAL_129:.*]] = aie.mem(%[[VAL_122]]) { -// CHECK: %[[VAL_130:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_127]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_128]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_127]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_131:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_125]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_126]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_125]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_132:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_123]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_124]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_123]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_133:.*]] = aie.core(%[[VAL_122]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_127]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_125]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_123]], Acquire, 0) -// CHECK: affine.for %[[VAL_134:.*]] = 0 to 64 { -// CHECK: %[[VAL_135:.*]] = affine.load %[[VAL_128]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> -// CHECK: %[[VAL_136:.*]] = affine.load %[[VAL_126]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> -// CHECK: %[[VAL_137:.*]] = arith.muli %[[VAL_135]], %[[VAL_136]] : i32 -// CHECK: affine.store %[[VAL_137]], %[[VAL_124]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_123]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_125]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_127]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.tile(26, 2) -// CHECK: %[[VAL_139:.*]] = aie.tile(26, 1) -// CHECK: %[[VAL_140:.*]] = aie.tile(26, 0) -// CHECK: %[[VAL_141:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_142:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_143:.*]] = aie.lock(%[[VAL_142]], 2) -// CHECK: %[[VAL_144:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf26"} : memref<64xi32, 2> -// CHECK: %[[VAL_145:.*]] = aie.lock(%[[VAL_142]], 1) -// CHECK: %[[VAL_146:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf25"} : memref<64xi32, 2> -// CHECK: %[[VAL_147:.*]] = aie.lock(%[[VAL_142]], 0) -// CHECK: %[[VAL_148:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf24"} : memref<64xi32, 2> -// CHECK: %[[VAL_149:.*]] = aie.mem(%[[VAL_142]]) { -// CHECK: %[[VAL_150:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_147]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_148]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_147]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_151:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_145]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_146]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_145]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_152:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_143]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_144]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_143]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_153:.*]] = aie.core(%[[VAL_142]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_147]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_145]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_143]], Acquire, 0) -// CHECK: affine.for %[[VAL_154:.*]] = 0 to 64 { -// CHECK: %[[VAL_155:.*]] = affine.load %[[VAL_148]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> -// CHECK: %[[VAL_156:.*]] = affine.load %[[VAL_146]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> -// CHECK: %[[VAL_157:.*]] = arith.muli %[[VAL_155]], %[[VAL_156]] : i32 -// CHECK: affine.store %[[VAL_157]], %[[VAL_144]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_143]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_145]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_147]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_158:.*]] = aie.tile(19, 2) -// CHECK: %[[VAL_159:.*]] = aie.tile(19, 1) -// CHECK: %[[VAL_160:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_161:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_162:.*]] = aie.lock(%[[VAL_161]], 2) -// CHECK: %[[VAL_163:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf23"} : memref<64xi32, 2> -// CHECK: %[[VAL_164:.*]] = aie.lock(%[[VAL_161]], 1) -// CHECK: %[[VAL_165:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf22"} : memref<64xi32, 2> -// CHECK: %[[VAL_166:.*]] = aie.lock(%[[VAL_161]], 0) -// CHECK: %[[VAL_167:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf21"} : memref<64xi32, 2> -// CHECK: %[[VAL_168:.*]] = aie.mem(%[[VAL_161]]) { -// CHECK: %[[VAL_169:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_166]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_167]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_166]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_170:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_164]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_165]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_164]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_171:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_162]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_163]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_162]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_172:.*]] = aie.core(%[[VAL_161]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_166]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_164]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_162]], Acquire, 0) -// CHECK: affine.for %[[VAL_173:.*]] = 0 to 64 { -// CHECK: %[[VAL_174:.*]] = affine.load %[[VAL_167]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> -// CHECK: %[[VAL_175:.*]] = affine.load %[[VAL_165]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> -// CHECK: %[[VAL_176:.*]] = arith.muli %[[VAL_174]], %[[VAL_175]] : i32 -// CHECK: affine.store %[[VAL_176]], %[[VAL_163]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_162]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_164]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_166]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_177:.*]] = aie.tile(18, 2) -// CHECK: %[[VAL_178:.*]] = aie.tile(18, 1) -// CHECK: %[[VAL_179:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_180:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_181:.*]] = aie.lock(%[[VAL_180]], 2) -// CHECK: %[[VAL_182:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf20"} : memref<64xi32, 2> -// CHECK: %[[VAL_183:.*]] = aie.lock(%[[VAL_180]], 1) -// CHECK: %[[VAL_184:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf19"} : memref<64xi32, 2> -// CHECK: %[[VAL_185:.*]] = aie.lock(%[[VAL_180]], 0) -// CHECK: %[[VAL_186:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf18"} : memref<64xi32, 2> -// CHECK: %[[VAL_187:.*]] = aie.mem(%[[VAL_180]]) { -// CHECK: %[[VAL_188:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_185]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_186]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_185]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_189:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_183]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_184]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_183]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_190:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_181]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_182]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_181]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_191:.*]] = aie.core(%[[VAL_180]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_185]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_183]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_181]], Acquire, 0) -// CHECK: affine.for %[[VAL_192:.*]] = 0 to 64 { -// CHECK: %[[VAL_193:.*]] = affine.load %[[VAL_186]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> -// CHECK: %[[VAL_194:.*]] = affine.load %[[VAL_184]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> -// CHECK: %[[VAL_195:.*]] = arith.muli %[[VAL_193]], %[[VAL_194]] : i32 -// CHECK: affine.store %[[VAL_195]], %[[VAL_182]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_181]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_183]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_185]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_196:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_197:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_198:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_199:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_200:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_201:.*]] = aie.lock(%[[VAL_200]], 2) -// CHECK: %[[VAL_202:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf17"} : memref<64xi32, 2> -// CHECK: %[[VAL_203:.*]] = aie.lock(%[[VAL_200]], 1) -// CHECK: %[[VAL_204:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf16"} : memref<64xi32, 2> -// CHECK: %[[VAL_205:.*]] = aie.lock(%[[VAL_200]], 0) -// CHECK: %[[VAL_206:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf15"} : memref<64xi32, 2> -// CHECK: %[[VAL_207:.*]] = aie.mem(%[[VAL_200]]) { -// CHECK: %[[VAL_208:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_205]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_206]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_205]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_209:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_203]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_204]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_203]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_210:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_201]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_202]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_201]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_211:.*]] = aie.core(%[[VAL_200]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_205]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_203]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_201]], Acquire, 0) -// CHECK: affine.for %[[VAL_212:.*]] = 0 to 64 { -// CHECK: %[[VAL_213:.*]] = affine.load %[[VAL_206]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> -// CHECK: %[[VAL_214:.*]] = affine.load %[[VAL_204]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> -// CHECK: %[[VAL_215:.*]] = arith.muli %[[VAL_213]], %[[VAL_214]] : i32 -// CHECK: affine.store %[[VAL_215]], %[[VAL_202]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_201]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_203]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_205]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_216:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_217:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_218:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_219:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_220:.*]] = aie.lock(%[[VAL_219]], 2) -// CHECK: %[[VAL_221:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf14"} : memref<64xi32, 2> -// CHECK: %[[VAL_222:.*]] = aie.lock(%[[VAL_219]], 1) -// CHECK: %[[VAL_223:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf13"} : memref<64xi32, 2> -// CHECK: %[[VAL_224:.*]] = aie.lock(%[[VAL_219]], 0) -// CHECK: %[[VAL_225:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf12"} : memref<64xi32, 2> -// CHECK: %[[VAL_226:.*]] = aie.mem(%[[VAL_219]]) { -// CHECK: %[[VAL_227:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_224]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_225]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_224]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_228:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_222]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_223]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_222]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_229:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_220]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_221]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_220]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_230:.*]] = aie.core(%[[VAL_219]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_224]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_222]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_220]], Acquire, 0) -// CHECK: affine.for %[[VAL_231:.*]] = 0 to 64 { -// CHECK: %[[VAL_232:.*]] = affine.load %[[VAL_225]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> -// CHECK: %[[VAL_233:.*]] = affine.load %[[VAL_223]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> -// CHECK: %[[VAL_234:.*]] = arith.muli %[[VAL_232]], %[[VAL_233]] : i32 -// CHECK: affine.store %[[VAL_234]], %[[VAL_221]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_220]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_222]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_224]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_235:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_236:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_237:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_238:.*]] = aie.lock(%[[VAL_237]], 2) -// CHECK: %[[VAL_239:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf11"} : memref<64xi32, 2> -// CHECK: %[[VAL_240:.*]] = aie.lock(%[[VAL_237]], 1) -// CHECK: %[[VAL_241:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf10"} : memref<64xi32, 2> -// CHECK: %[[VAL_242:.*]] = aie.lock(%[[VAL_237]], 0) -// CHECK: %[[VAL_243:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf9"} : memref<64xi32, 2> -// CHECK: %[[VAL_244:.*]] = aie.mem(%[[VAL_237]]) { -// CHECK: %[[VAL_245:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_242]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_243]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_242]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_246:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_240]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_241]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_240]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_247:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_238]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_239]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_238]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_248:.*]] = aie.core(%[[VAL_237]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_242]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_240]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_238]], Acquire, 0) -// CHECK: affine.for %[[VAL_249:.*]] = 0 to 64 { -// CHECK: %[[VAL_250:.*]] = affine.load %[[VAL_243]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> -// CHECK: %[[VAL_251:.*]] = affine.load %[[VAL_241]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> -// CHECK: %[[VAL_252:.*]] = arith.muli %[[VAL_250]], %[[VAL_251]] : i32 -// CHECK: affine.store %[[VAL_252]], %[[VAL_239]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_238]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_240]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_242]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_253:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_254:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_255:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_256:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_257:.*]] = aie.lock(%[[VAL_256]], 2) -// CHECK: %[[VAL_258:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf8"} : memref<64xi32, 2> -// CHECK: %[[VAL_259:.*]] = aie.lock(%[[VAL_256]], 1) -// CHECK: %[[VAL_260:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf7"} : memref<64xi32, 2> -// CHECK: %[[VAL_261:.*]] = aie.lock(%[[VAL_256]], 0) -// CHECK: %[[VAL_262:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf6"} : memref<64xi32, 2> -// CHECK: %[[VAL_263:.*]] = aie.mem(%[[VAL_256]]) { -// CHECK: %[[VAL_264:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_261]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_262]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_261]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_265:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_259]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_260]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_259]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_266:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_257]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_258]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_257]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_267:.*]] = aie.core(%[[VAL_256]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_261]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_259]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_257]], Acquire, 0) -// CHECK: affine.for %[[VAL_268:.*]] = 0 to 64 { -// CHECK: %[[VAL_269:.*]] = affine.load %[[VAL_262]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> -// CHECK: %[[VAL_270:.*]] = affine.load %[[VAL_260]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> -// CHECK: %[[VAL_271:.*]] = arith.muli %[[VAL_269]], %[[VAL_270]] : i32 -// CHECK: affine.store %[[VAL_271]], %[[VAL_258]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_257]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_259]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_261]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_272:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_273:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_274:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_275:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_276:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_277:.*]] = aie.lock(%[[VAL_276]], 2) -// CHECK: %[[VAL_278:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf5"} : memref<64xi32, 2> -// CHECK: %[[VAL_279:.*]] = aie.lock(%[[VAL_276]], 1) -// CHECK: %[[VAL_280:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf4"} : memref<64xi32, 2> -// CHECK: %[[VAL_281:.*]] = aie.lock(%[[VAL_276]], 0) -// CHECK: %[[VAL_282:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf3"} : memref<64xi32, 2> -// CHECK: %[[VAL_283:.*]] = aie.mem(%[[VAL_276]]) { -// CHECK: %[[VAL_284:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_281]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_282]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_281]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_285:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_279]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_280]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_279]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_286:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_277]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_278]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_277]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_287:.*]] = aie.core(%[[VAL_276]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_281]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_279]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_277]], Acquire, 0) -// CHECK: affine.for %[[VAL_288:.*]] = 0 to 64 { -// CHECK: %[[VAL_289:.*]] = affine.load %[[VAL_282]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> -// CHECK: %[[VAL_290:.*]] = affine.load %[[VAL_280]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> -// CHECK: %[[VAL_291:.*]] = arith.muli %[[VAL_289]], %[[VAL_290]] : i32 -// CHECK: affine.store %[[VAL_291]], %[[VAL_278]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_277]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_279]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_281]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_292:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_293:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_294:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_295:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_296:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_297:.*]] = aie.lock(%[[VAL_296]], 2) -// CHECK: %[[VAL_298:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf2"} : memref<64xi32, 2> -// CHECK: %[[VAL_299:.*]] = aie.lock(%[[VAL_296]], 1) -// CHECK: %[[VAL_300:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf1"} : memref<64xi32, 2> -// CHECK: %[[VAL_301:.*]] = aie.lock(%[[VAL_296]], 0) -// CHECK: %[[VAL_302:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf0"} : memref<64xi32, 2> -// CHECK: %[[VAL_303:.*]] = aie.mem(%[[VAL_296]]) { -// CHECK: %[[VAL_304:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_301]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_302]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_301]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_305:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_299]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_300]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_299]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_306:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_297]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_298]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_297]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_307:.*]] = aie.core(%[[VAL_296]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_301]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_299]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_297]], Acquire, 0) -// CHECK: affine.for %[[VAL_308:.*]] = 0 to 64 { -// CHECK: %[[VAL_309:.*]] = affine.load %[[VAL_302]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> -// CHECK: %[[VAL_310:.*]] = affine.load %[[VAL_300]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> -// CHECK: %[[VAL_311:.*]] = arith.muli %[[VAL_309]], %[[VAL_310]] : i32 -// CHECK: affine.store %[[VAL_311]], %[[VAL_298]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[VAL_297]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_299]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_301]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[VAL_312:.*]] = aie.switchbox(%[[VAL_294]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_313:.*]] = aie.shim_mux(%[[VAL_294]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_314:.*]] = aie.switchbox(%[[VAL_293]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_315:.*]] = aie.switchbox(%[[VAL_292]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_316:.*]] = aie.switchbox(%[[VAL_272]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_317:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_318:.*]] = aie.switchbox(%[[VAL_317]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_319:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_320:.*]] = aie.switchbox(%[[VAL_319]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_321:.*]] = aie.switchbox(%[[VAL_253]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_322:.*]] = aie.switchbox(%[[VAL_296]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_323:.*]] = aie.switchbox(%[[VAL_274]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_324:.*]] = aie.shim_mux(%[[VAL_274]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_325:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_326:.*]] = aie.switchbox(%[[VAL_325]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_327:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_328:.*]] = aie.switchbox(%[[VAL_327]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_329:.*]] = aie.switchbox(%[[VAL_255]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_330:.*]] = aie.switchbox(%[[VAL_254]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_331:.*]] = aie.switchbox(%[[VAL_276]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_332:.*]] = aie.shim_mux(%[[VAL_255]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_333:.*]] = aie.switchbox(%[[VAL_236]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_334:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_335:.*]] = aie.switchbox(%[[VAL_334]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_336:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_337:.*]] = aie.switchbox(%[[VAL_336]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_338:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_339:.*]] = aie.switchbox(%[[VAL_338]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_340:.*]] = aie.switchbox(%[[VAL_256]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_341:.*]] = aie.switchbox(%[[VAL_273]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_342:.*]] = aie.shim_mux(%[[VAL_236]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_343:.*]] = aie.switchbox(%[[VAL_217]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_344:.*]] = aie.switchbox(%[[VAL_216]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_345:.*]] = aie.switchbox(%[[VAL_237]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_346:.*]] = aie.switchbox(%[[VAL_219]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_347:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_348:.*]] = aie.switchbox(%[[VAL_347]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_349:.*]] = aie.switchbox(%[[VAL_200]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_350:.*]] = aie.shim_mux(%[[VAL_217]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_351:.*]] = aie.switchbox(%[[VAL_235]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_352:.*]] = aie.switchbox(%[[VAL_180]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_353:.*]] = aie.switchbox(%[[VAL_198]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_354:.*]] = aie.shim_mux(%[[VAL_198]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_355:.*]] = aie.switchbox(%[[VAL_161]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_356:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_357:.*]] = aie.switchbox(%[[VAL_356]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_358:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_359:.*]] = aie.switchbox(%[[VAL_358]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_360:.*]] = aie.tile(14, 0) -// CHECK: %[[VAL_361:.*]] = aie.switchbox(%[[VAL_360]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_362:.*]] = aie.tile(15, 0) -// CHECK: %[[VAL_363:.*]] = aie.switchbox(%[[VAL_362]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_364:.*]] = aie.tile(16, 0) -// CHECK: %[[VAL_365:.*]] = aie.switchbox(%[[VAL_364]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_366:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_367:.*]] = aie.switchbox(%[[VAL_366]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_368:.*]] = aie.switchbox(%[[VAL_179]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_369:.*]] = aie.shim_mux(%[[VAL_179]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_370:.*]] = aie.switchbox(%[[VAL_197]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_371:.*]] = aie.switchbox(%[[VAL_196]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_372:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_373:.*]] = aie.switchbox(%[[VAL_372]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_374:.*]] = aie.switchbox(%[[VAL_160]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_375:.*]] = aie.shim_mux(%[[VAL_160]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_376:.*]] = aie.switchbox(%[[VAL_142]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_377:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_378:.*]] = aie.switchbox(%[[VAL_377]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_379:.*]] = aie.tile(13, 1) -// CHECK: %[[VAL_380:.*]] = aie.switchbox(%[[VAL_379]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_381:.*]] = aie.tile(14, 1) -// CHECK: %[[VAL_382:.*]] = aie.switchbox(%[[VAL_381]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_383:.*]] = aie.tile(15, 1) -// CHECK: %[[VAL_384:.*]] = aie.switchbox(%[[VAL_383]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_385:.*]] = aie.tile(16, 1) -// CHECK: %[[VAL_386:.*]] = aie.switchbox(%[[VAL_385]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_387:.*]] = aie.tile(17, 1) -// CHECK: %[[VAL_388:.*]] = aie.switchbox(%[[VAL_387]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_389:.*]] = aie.switchbox(%[[VAL_178]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_390:.*]] = aie.tile(20, 0) -// CHECK: %[[VAL_391:.*]] = aie.switchbox(%[[VAL_390]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_392:.*]] = aie.tile(21, 0) -// CHECK: %[[VAL_393:.*]] = aie.switchbox(%[[VAL_392]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_394:.*]] = aie.tile(22, 0) -// CHECK: %[[VAL_395:.*]] = aie.switchbox(%[[VAL_394]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_396:.*]] = aie.tile(23, 0) -// CHECK: %[[VAL_397:.*]] = aie.switchbox(%[[VAL_396]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_398:.*]] = aie.tile(24, 0) -// CHECK: %[[VAL_399:.*]] = aie.switchbox(%[[VAL_398]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_400:.*]] = aie.tile(25, 0) -// CHECK: %[[VAL_401:.*]] = aie.switchbox(%[[VAL_400]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_402:.*]] = aie.switchbox(%[[VAL_140]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_403:.*]] = aie.shim_mux(%[[VAL_140]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_404:.*]] = aie.switchbox(%[[VAL_122]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_405:.*]] = aie.switchbox(%[[VAL_102]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_406:.*]] = aie.switchbox(%[[VAL_159]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_407:.*]] = aie.switchbox(%[[VAL_120]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_408:.*]] = aie.shim_mux(%[[VAL_120]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_409:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_410:.*]] = aie.switchbox(%[[VAL_409]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_411:.*]] = aie.tile(13, 2) -// CHECK: %[[VAL_412:.*]] = aie.switchbox(%[[VAL_411]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_413:.*]] = aie.tile(14, 2) -// CHECK: %[[VAL_414:.*]] = aie.switchbox(%[[VAL_413]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_415:.*]] = aie.tile(15, 2) -// CHECK: %[[VAL_416:.*]] = aie.switchbox(%[[VAL_415]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_417:.*]] = aie.tile(16, 2) -// CHECK: %[[VAL_418:.*]] = aie.switchbox(%[[VAL_417]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_419:.*]] = aie.tile(17, 2) -// CHECK: %[[VAL_420:.*]] = aie.switchbox(%[[VAL_419]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_421:.*]] = aie.switchbox(%[[VAL_177]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_422:.*]] = aie.switchbox(%[[VAL_158]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_423:.*]] = aie.tile(20, 1) -// CHECK: %[[VAL_424:.*]] = aie.switchbox(%[[VAL_423]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_425:.*]] = aie.tile(20, 2) -// CHECK: %[[VAL_426:.*]] = aie.switchbox(%[[VAL_425]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_427:.*]] = aie.tile(21, 1) -// CHECK: %[[VAL_428:.*]] = aie.switchbox(%[[VAL_427]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_429:.*]] = aie.tile(22, 1) -// CHECK: %[[VAL_430:.*]] = aie.switchbox(%[[VAL_429]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_431:.*]] = aie.tile(23, 1) -// CHECK: %[[VAL_432:.*]] = aie.switchbox(%[[VAL_431]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_433:.*]] = aie.tile(24, 1) -// CHECK: %[[VAL_434:.*]] = aie.switchbox(%[[VAL_433]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_435:.*]] = aie.tile(25, 1) -// CHECK: %[[VAL_436:.*]] = aie.switchbox(%[[VAL_435]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_437:.*]] = aie.switchbox(%[[VAL_139]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_438:.*]] = aie.tile(28, 0) -// CHECK: %[[VAL_439:.*]] = aie.switchbox(%[[VAL_438]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_440:.*]] = aie.tile(29, 0) -// CHECK: %[[VAL_441:.*]] = aie.switchbox(%[[VAL_440]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_442:.*]] = aie.tile(30, 0) -// CHECK: %[[VAL_443:.*]] = aie.switchbox(%[[VAL_442]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_444:.*]] = aie.tile(31, 0) -// CHECK: %[[VAL_445:.*]] = aie.switchbox(%[[VAL_444]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_446:.*]] = aie.tile(32, 0) -// CHECK: %[[VAL_447:.*]] = aie.switchbox(%[[VAL_446]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_448:.*]] = aie.tile(33, 0) -// CHECK: %[[VAL_449:.*]] = aie.switchbox(%[[VAL_448]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_450:.*]] = aie.switchbox(%[[VAL_101]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_451:.*]] = aie.shim_mux(%[[VAL_101]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_452:.*]] = aie.switchbox(%[[VAL_83]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_453:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_454:.*]] = aie.switchbox(%[[VAL_453]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_455:.*]] = aie.tile(13, 3) -// CHECK: %[[VAL_456:.*]] = aie.switchbox(%[[VAL_455]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_457:.*]] = aie.tile(14, 3) -// CHECK: %[[VAL_458:.*]] = aie.switchbox(%[[VAL_457]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_459:.*]] = aie.tile(15, 3) -// CHECK: %[[VAL_460:.*]] = aie.switchbox(%[[VAL_459]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_461:.*]] = aie.tile(16, 3) -// CHECK: %[[VAL_462:.*]] = aie.switchbox(%[[VAL_461]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_463:.*]] = aie.tile(17, 3) -// CHECK: %[[VAL_464:.*]] = aie.switchbox(%[[VAL_463]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_465:.*]] = aie.tile(18, 3) -// CHECK: %[[VAL_466:.*]] = aie.switchbox(%[[VAL_465]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_467:.*]] = aie.tile(19, 3) -// CHECK: %[[VAL_468:.*]] = aie.switchbox(%[[VAL_467]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_469:.*]] = aie.tile(20, 3) -// CHECK: %[[VAL_470:.*]] = aie.switchbox(%[[VAL_469]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_471:.*]] = aie.switchbox(%[[VAL_119]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_472:.*]] = aie.switchbox(%[[VAL_82]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_473:.*]] = aie.shim_mux(%[[VAL_82]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_474:.*]] = aie.switchbox(%[[VAL_64]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_475:.*]] = aie.switchbox(%[[VAL_44]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_476:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_477:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_478:.*]] = aie.tile(11, 5) -// CHECK: %[[VAL_479:.*]] = aie.switchbox(%[[VAL_478]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_480:.*]] = aie.tile(12, 5) -// CHECK: %[[VAL_481:.*]] = aie.switchbox(%[[VAL_480]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_482:.*]] = aie.tile(13, 5) -// CHECK: %[[VAL_483:.*]] = aie.switchbox(%[[VAL_482]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_484:.*]] = aie.tile(14, 5) -// CHECK: %[[VAL_485:.*]] = aie.switchbox(%[[VAL_484]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_486:.*]] = aie.tile(15, 4) -// CHECK: %[[VAL_487:.*]] = aie.switchbox(%[[VAL_486]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_488:.*]] = aie.tile(15, 5) -// CHECK: %[[VAL_489:.*]] = aie.switchbox(%[[VAL_488]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_490:.*]] = aie.tile(21, 3) -// CHECK: %[[VAL_491:.*]] = aie.switchbox(%[[VAL_490]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_492:.*]] = aie.tile(22, 3) -// CHECK: %[[VAL_493:.*]] = aie.switchbox(%[[VAL_492]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_494:.*]] = aie.tile(23, 3) -// CHECK: %[[VAL_495:.*]] = aie.switchbox(%[[VAL_494]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_496:.*]] = aie.tile(24, 2) -// CHECK: %[[VAL_497:.*]] = aie.switchbox(%[[VAL_496]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_498:.*]] = aie.tile(24, 3) -// CHECK: %[[VAL_499:.*]] = aie.switchbox(%[[VAL_498]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_500:.*]] = aie.tile(25, 2) -// CHECK: %[[VAL_501:.*]] = aie.switchbox(%[[VAL_500]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_502:.*]] = aie.switchbox(%[[VAL_138]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_503:.*]] = aie.tile(28, 1) -// CHECK: %[[VAL_504:.*]] = aie.switchbox(%[[VAL_503]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_505:.*]] = aie.tile(29, 1) -// CHECK: %[[VAL_506:.*]] = aie.switchbox(%[[VAL_505]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_507:.*]] = aie.tile(30, 1) -// CHECK: %[[VAL_508:.*]] = aie.switchbox(%[[VAL_507]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_509:.*]] = aie.tile(31, 1) -// CHECK: %[[VAL_510:.*]] = aie.switchbox(%[[VAL_509]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_511:.*]] = aie.tile(32, 1) -// CHECK: %[[VAL_512:.*]] = aie.switchbox(%[[VAL_511]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_513:.*]] = aie.tile(33, 1) -// CHECK: %[[VAL_514:.*]] = aie.switchbox(%[[VAL_513]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_515:.*]] = aie.switchbox(%[[VAL_100]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_516:.*]] = aie.tile(36, 0) -// CHECK: %[[VAL_517:.*]] = aie.switchbox(%[[VAL_516]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_518:.*]] = aie.tile(37, 0) -// CHECK: %[[VAL_519:.*]] = aie.switchbox(%[[VAL_518]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_520:.*]] = aie.tile(38, 0) -// CHECK: %[[VAL_521:.*]] = aie.switchbox(%[[VAL_520]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_522:.*]] = aie.tile(39, 0) -// CHECK: %[[VAL_523:.*]] = aie.switchbox(%[[VAL_522]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_524:.*]] = aie.tile(40, 0) -// CHECK: %[[VAL_525:.*]] = aie.switchbox(%[[VAL_524]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_526:.*]] = aie.tile(41, 0) -// CHECK: %[[VAL_527:.*]] = aie.switchbox(%[[VAL_526]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_528:.*]] = aie.switchbox(%[[VAL_62]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_529:.*]] = aie.shim_mux(%[[VAL_62]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_530:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_531:.*]] = aie.switchbox(%[[VAL_530]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_532:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_533:.*]] = aie.switchbox(%[[VAL_532]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_534:.*]] = aie.tile(13, 4) -// CHECK: %[[VAL_535:.*]] = aie.switchbox(%[[VAL_534]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_536:.*]] = aie.tile(14, 4) -// CHECK: %[[VAL_537:.*]] = aie.switchbox(%[[VAL_536]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_538:.*]] = aie.tile(16, 4) -// CHECK: %[[VAL_539:.*]] = aie.switchbox(%[[VAL_538]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_540:.*]] = aie.tile(17, 4) -// CHECK: %[[VAL_541:.*]] = aie.switchbox(%[[VAL_540]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_542:.*]] = aie.tile(21, 2) -// CHECK: %[[VAL_543:.*]] = aie.switchbox(%[[VAL_542]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_544:.*]] = aie.tile(22, 2) -// CHECK: %[[VAL_545:.*]] = aie.switchbox(%[[VAL_544]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_546:.*]] = aie.tile(23, 2) -// CHECK: %[[VAL_547:.*]] = aie.switchbox(%[[VAL_546]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_548:.*]] = aie.switchbox(%[[VAL_118]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_549:.*]] = aie.switchbox(%[[VAL_81]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_550:.*]] = aie.switchbox(%[[VAL_42]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_551:.*]] = aie.shim_mux(%[[VAL_42]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_552:.*]] = aie.tile(18, 4) -// CHECK: %[[VAL_553:.*]] = aie.switchbox(%[[VAL_552]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_554:.*]] = aie.tile(19, 4) -// CHECK: %[[VAL_555:.*]] = aie.switchbox(%[[VAL_554]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_556:.*]] = aie.tile(20, 4) -// CHECK: %[[VAL_557:.*]] = aie.switchbox(%[[VAL_556]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_558:.*]] = aie.tile(25, 3) -// CHECK: %[[VAL_559:.*]] = aie.switchbox(%[[VAL_558]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_560:.*]] = aie.tile(26, 3) -// CHECK: %[[VAL_561:.*]] = aie.switchbox(%[[VAL_560]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_562:.*]] = aie.tile(28, 2) -// CHECK: %[[VAL_563:.*]] = aie.switchbox(%[[VAL_562]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_564:.*]] = aie.tile(29, 2) -// CHECK: %[[VAL_565:.*]] = aie.switchbox(%[[VAL_564]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_566:.*]] = aie.tile(30, 2) -// CHECK: %[[VAL_567:.*]] = aie.switchbox(%[[VAL_566]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_568:.*]] = aie.tile(31, 2) -// CHECK: %[[VAL_569:.*]] = aie.switchbox(%[[VAL_568]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_570:.*]] = aie.tile(32, 2) -// CHECK: %[[VAL_571:.*]] = aie.switchbox(%[[VAL_570]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_572:.*]] = aie.tile(33, 2) -// CHECK: %[[VAL_573:.*]] = aie.switchbox(%[[VAL_572]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_574:.*]] = aie.switchbox(%[[VAL_99]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_575:.*]] = aie.switchbox(%[[VAL_80]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_576:.*]] = aie.tile(36, 2) -// CHECK: %[[VAL_577:.*]] = aie.switchbox(%[[VAL_576]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_578:.*]] = aie.tile(37, 2) -// CHECK: %[[VAL_579:.*]] = aie.switchbox(%[[VAL_578]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_580:.*]] = aie.tile(38, 2) -// CHECK: %[[VAL_581:.*]] = aie.switchbox(%[[VAL_580]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_582:.*]] = aie.tile(39, 2) -// CHECK: %[[VAL_583:.*]] = aie.switchbox(%[[VAL_582]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_584:.*]] = aie.tile(40, 2) -// CHECK: %[[VAL_585:.*]] = aie.switchbox(%[[VAL_584]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_586:.*]] = aie.tile(41, 1) -// CHECK: %[[VAL_587:.*]] = aie.switchbox(%[[VAL_586]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_588:.*]] = aie.tile(41, 2) -// CHECK: %[[VAL_589:.*]] = aie.switchbox(%[[VAL_588]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_590:.*]] = aie.switchbox(%[[VAL_61]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_591:.*]] = aie.tile(44, 0) -// CHECK: %[[VAL_592:.*]] = aie.switchbox(%[[VAL_591]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_593:.*]] = aie.tile(45, 0) -// CHECK: %[[VAL_594:.*]] = aie.switchbox(%[[VAL_593]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_595:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_596:.*]] = aie.shim_mux(%[[VAL_22]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_597:.*]] = aie.tile(16, 5) -// CHECK: %[[VAL_598:.*]] = aie.switchbox(%[[VAL_597]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_599:.*]] = aie.tile(17, 5) -// CHECK: %[[VAL_600:.*]] = aie.switchbox(%[[VAL_599]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_601:.*]] = aie.tile(18, 5) -// CHECK: %[[VAL_602:.*]] = aie.switchbox(%[[VAL_601]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_603:.*]] = aie.tile(21, 4) -// CHECK: %[[VAL_604:.*]] = aie.switchbox(%[[VAL_603]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_605:.*]] = aie.tile(22, 4) -// CHECK: %[[VAL_606:.*]] = aie.switchbox(%[[VAL_605]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_607:.*]] = aie.tile(23, 4) -// CHECK: %[[VAL_608:.*]] = aie.switchbox(%[[VAL_607]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_609:.*]] = aie.tile(24, 4) -// CHECK: %[[VAL_610:.*]] = aie.switchbox(%[[VAL_609]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_611:.*]] = aie.tile(25, 4) -// CHECK: %[[VAL_612:.*]] = aie.switchbox(%[[VAL_611]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_613:.*]] = aie.tile(26, 4) -// CHECK: %[[VAL_614:.*]] = aie.switchbox(%[[VAL_613]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_615:.*]] = aie.tile(27, 4) -// CHECK: %[[VAL_616:.*]] = aie.switchbox(%[[VAL_615]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_617:.*]] = aie.tile(28, 4) -// CHECK: %[[VAL_618:.*]] = aie.switchbox(%[[VAL_617]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_619:.*]] = aie.tile(29, 4) -// CHECK: %[[VAL_620:.*]] = aie.switchbox(%[[VAL_619]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_621:.*]] = aie.tile(30, 4) -// CHECK: %[[VAL_622:.*]] = aie.switchbox(%[[VAL_621]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_623:.*]] = aie.tile(31, 4) -// CHECK: %[[VAL_624:.*]] = aie.switchbox(%[[VAL_623]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_625:.*]] = aie.tile(32, 4) -// CHECK: %[[VAL_626:.*]] = aie.switchbox(%[[VAL_625]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_627:.*]] = aie.tile(33, 4) -// CHECK: %[[VAL_628:.*]] = aie.switchbox(%[[VAL_627]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_629:.*]] = aie.tile(34, 4) -// CHECK: %[[VAL_630:.*]] = aie.switchbox(%[[VAL_629]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_631:.*]] = aie.tile(35, 4) -// CHECK: %[[VAL_632:.*]] = aie.switchbox(%[[VAL_631]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_633:.*]] = aie.tile(36, 4) -// CHECK: %[[VAL_634:.*]] = aie.switchbox(%[[VAL_633]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_635:.*]] = aie.tile(37, 4) -// CHECK: %[[VAL_636:.*]] = aie.switchbox(%[[VAL_635]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_637:.*]] = aie.tile(38, 4) -// CHECK: %[[VAL_638:.*]] = aie.switchbox(%[[VAL_637]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_639:.*]] = aie.tile(39, 4) -// CHECK: %[[VAL_640:.*]] = aie.switchbox(%[[VAL_639]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_641:.*]] = aie.tile(40, 4) -// CHECK: %[[VAL_642:.*]] = aie.switchbox(%[[VAL_641]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_643:.*]] = aie.tile(41, 4) -// CHECK: %[[VAL_644:.*]] = aie.switchbox(%[[VAL_643]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_645:.*]] = aie.tile(42, 3) -// CHECK: %[[VAL_646:.*]] = aie.switchbox(%[[VAL_645]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_647:.*]] = aie.tile(42, 4) -// CHECK: %[[VAL_648:.*]] = aie.switchbox(%[[VAL_647]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_649:.*]] = aie.tile(43, 3) -// CHECK: %[[VAL_650:.*]] = aie.switchbox(%[[VAL_649]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_651:.*]] = aie.tile(44, 3) -// CHECK: %[[VAL_652:.*]] = aie.switchbox(%[[VAL_651]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_653:.*]] = aie.tile(45, 2) -// CHECK: %[[VAL_654:.*]] = aie.switchbox(%[[VAL_653]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_655:.*]] = aie.tile(45, 3) -// CHECK: %[[VAL_656:.*]] = aie.switchbox(%[[VAL_655]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_657:.*]] = aie.switchbox(%[[VAL_21]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_658:.*]] = aie.switchbox(%[[VAL_20]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_659:.*]] = aie.switchbox(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_660:.*]] = aie.shim_mux(%[[VAL_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[VAL_661:.*]] : North, %[[VAL_662:.*]] : South) -// CHECK: aie.wire(%[[VAL_294]] : DMA, %[[VAL_661]] : DMA) -// CHECK: aie.wire(%[[VAL_293]] : Core, %[[VAL_663:.*]] : Core) -// CHECK: aie.wire(%[[VAL_293]] : DMA, %[[VAL_663]] : DMA) -// CHECK: aie.wire(%[[VAL_662]] : North, %[[VAL_663]] : South) -// CHECK: aie.wire(%[[VAL_292]] : Core, %[[VAL_664:.*]] : Core) -// CHECK: aie.wire(%[[VAL_292]] : DMA, %[[VAL_664]] : DMA) -// CHECK: aie.wire(%[[VAL_663]] : North, %[[VAL_664]] : South) -// CHECK: aie.wire(%[[VAL_662]] : East, %[[VAL_665:.*]] : West) -// CHECK: aie.wire(%[[VAL_666:.*]] : North, %[[VAL_665]] : South) -// CHECK: aie.wire(%[[VAL_274]] : DMA, %[[VAL_666]] : DMA) -// CHECK: aie.wire(%[[VAL_663]] : East, %[[VAL_667:.*]] : West) -// CHECK: aie.wire(%[[VAL_273]] : Core, %[[VAL_667]] : Core) -// CHECK: aie.wire(%[[VAL_273]] : DMA, %[[VAL_667]] : DMA) -// CHECK: aie.wire(%[[VAL_665]] : North, %[[VAL_667]] : South) -// CHECK: aie.wire(%[[VAL_664]] : East, %[[VAL_668:.*]] : West) -// CHECK: aie.wire(%[[VAL_272]] : Core, %[[VAL_668]] : Core) -// CHECK: aie.wire(%[[VAL_272]] : DMA, %[[VAL_668]] : DMA) -// CHECK: aie.wire(%[[VAL_667]] : North, %[[VAL_668]] : South) -// CHECK: aie.wire(%[[VAL_665]] : East, %[[VAL_669:.*]] : West) -// CHECK: aie.wire(%[[VAL_668]] : East, %[[VAL_670:.*]] : West) -// CHECK: aie.wire(%[[VAL_317]] : Core, %[[VAL_670]] : Core) -// CHECK: aie.wire(%[[VAL_317]] : DMA, %[[VAL_670]] : DMA) -// CHECK: aie.wire(%[[VAL_669]] : East, %[[VAL_671:.*]] : West) -// CHECK: aie.wire(%[[VAL_670]] : East, %[[VAL_672:.*]] : West) -// CHECK: aie.wire(%[[VAL_319]] : Core, %[[VAL_672]] : Core) -// CHECK: aie.wire(%[[VAL_319]] : DMA, %[[VAL_672]] : DMA) -// CHECK: aie.wire(%[[VAL_671]] : East, %[[VAL_673:.*]] : West) -// CHECK: aie.wire(%[[VAL_674:.*]] : North, %[[VAL_673]] : South) -// CHECK: aie.wire(%[[VAL_255]] : DMA, %[[VAL_674]] : DMA) -// CHECK: aie.wire(%[[VAL_254]] : Core, %[[VAL_675:.*]] : Core) -// CHECK: aie.wire(%[[VAL_254]] : DMA, %[[VAL_675]] : DMA) -// CHECK: aie.wire(%[[VAL_673]] : North, %[[VAL_675]] : South) -// CHECK: aie.wire(%[[VAL_672]] : East, %[[VAL_676:.*]] : West) -// CHECK: aie.wire(%[[VAL_253]] : Core, %[[VAL_676]] : Core) -// CHECK: aie.wire(%[[VAL_253]] : DMA, %[[VAL_676]] : DMA) -// CHECK: aie.wire(%[[VAL_675]] : North, %[[VAL_676]] : South) -// CHECK: aie.wire(%[[VAL_673]] : East, %[[VAL_677:.*]] : West) -// CHECK: aie.wire(%[[VAL_678:.*]] : North, %[[VAL_677]] : South) -// CHECK: aie.wire(%[[VAL_236]] : DMA, %[[VAL_678]] : DMA) -// CHECK: aie.wire(%[[VAL_675]] : East, %[[VAL_679:.*]] : West) -// CHECK: aie.wire(%[[VAL_235]] : Core, %[[VAL_679]] : Core) -// CHECK: aie.wire(%[[VAL_235]] : DMA, %[[VAL_679]] : DMA) -// CHECK: aie.wire(%[[VAL_677]] : North, %[[VAL_679]] : South) -// CHECK: aie.wire(%[[VAL_676]] : East, %[[VAL_680:.*]] : West) -// CHECK: aie.wire(%[[VAL_296]] : Core, %[[VAL_680]] : Core) -// CHECK: aie.wire(%[[VAL_296]] : DMA, %[[VAL_680]] : DMA) -// CHECK: aie.wire(%[[VAL_679]] : North, %[[VAL_680]] : South) -// CHECK: aie.wire(%[[VAL_219]] : Core, %[[VAL_681:.*]] : Core) -// CHECK: aie.wire(%[[VAL_219]] : DMA, %[[VAL_681]] : DMA) -// CHECK: aie.wire(%[[VAL_680]] : North, %[[VAL_681]] : South) -// CHECK: aie.wire(%[[VAL_142]] : Core, %[[VAL_682:.*]] : Core) -// CHECK: aie.wire(%[[VAL_142]] : DMA, %[[VAL_682]] : DMA) -// CHECK: aie.wire(%[[VAL_681]] : North, %[[VAL_682]] : South) -// CHECK: aie.wire(%[[VAL_64]] : Core, %[[VAL_683:.*]] : Core) -// CHECK: aie.wire(%[[VAL_64]] : DMA, %[[VAL_683]] : DMA) -// CHECK: aie.wire(%[[VAL_682]] : North, %[[VAL_683]] : South) -// CHECK: aie.wire(%[[VAL_677]] : East, %[[VAL_684:.*]] : West) -// CHECK: aie.wire(%[[VAL_679]] : East, %[[VAL_685:.*]] : West) -// CHECK: aie.wire(%[[VAL_347]] : Core, %[[VAL_685]] : Core) -// CHECK: aie.wire(%[[VAL_347]] : DMA, %[[VAL_685]] : DMA) -// CHECK: aie.wire(%[[VAL_684]] : North, %[[VAL_685]] : South) -// CHECK: aie.wire(%[[VAL_680]] : East, %[[VAL_686:.*]] : West) -// CHECK: aie.wire(%[[VAL_276]] : Core, %[[VAL_686]] : Core) -// CHECK: aie.wire(%[[VAL_276]] : DMA, %[[VAL_686]] : DMA) -// CHECK: aie.wire(%[[VAL_685]] : North, %[[VAL_686]] : South) -// CHECK: aie.wire(%[[VAL_681]] : East, %[[VAL_687:.*]] : West) -// CHECK: aie.wire(%[[VAL_200]] : Core, %[[VAL_687]] : Core) -// CHECK: aie.wire(%[[VAL_200]] : DMA, %[[VAL_687]] : DMA) -// CHECK: aie.wire(%[[VAL_686]] : North, %[[VAL_687]] : South) -// CHECK: aie.wire(%[[VAL_682]] : East, %[[VAL_688:.*]] : West) -// CHECK: aie.wire(%[[VAL_122]] : Core, %[[VAL_688]] : Core) -// CHECK: aie.wire(%[[VAL_122]] : DMA, %[[VAL_688]] : DMA) -// CHECK: aie.wire(%[[VAL_687]] : North, %[[VAL_688]] : South) -// CHECK: aie.wire(%[[VAL_683]] : East, %[[VAL_689:.*]] : West) -// CHECK: aie.wire(%[[VAL_44]] : Core, %[[VAL_689]] : Core) -// CHECK: aie.wire(%[[VAL_44]] : DMA, %[[VAL_689]] : DMA) -// CHECK: aie.wire(%[[VAL_688]] : North, %[[VAL_689]] : South) -// CHECK: aie.wire(%[[VAL_684]] : East, %[[VAL_690:.*]] : West) -// CHECK: aie.wire(%[[VAL_685]] : East, %[[VAL_691:.*]] : West) -// CHECK: aie.wire(%[[VAL_338]] : Core, %[[VAL_691]] : Core) -// CHECK: aie.wire(%[[VAL_338]] : DMA, %[[VAL_691]] : DMA) -// CHECK: aie.wire(%[[VAL_690]] : North, %[[VAL_691]] : South) -// CHECK: aie.wire(%[[VAL_686]] : East, %[[VAL_692:.*]] : West) -// CHECK: aie.wire(%[[VAL_256]] : Core, %[[VAL_692]] : Core) -// CHECK: aie.wire(%[[VAL_256]] : DMA, %[[VAL_692]] : DMA) -// CHECK: aie.wire(%[[VAL_691]] : North, %[[VAL_692]] : South) -// CHECK: aie.wire(%[[VAL_687]] : East, %[[VAL_693:.*]] : West) -// CHECK: aie.wire(%[[VAL_180]] : Core, %[[VAL_693]] : Core) -// CHECK: aie.wire(%[[VAL_180]] : DMA, %[[VAL_693]] : DMA) -// CHECK: aie.wire(%[[VAL_692]] : North, %[[VAL_693]] : South) -// CHECK: aie.wire(%[[VAL_688]] : East, %[[VAL_694:.*]] : West) -// CHECK: aie.wire(%[[VAL_102]] : Core, %[[VAL_694]] : Core) -// CHECK: aie.wire(%[[VAL_102]] : DMA, %[[VAL_694]] : DMA) -// CHECK: aie.wire(%[[VAL_693]] : North, %[[VAL_694]] : South) -// CHECK: aie.wire(%[[VAL_689]] : East, %[[VAL_695:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_695]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_695]] : DMA) -// CHECK: aie.wire(%[[VAL_694]] : North, %[[VAL_695]] : South) -// CHECK: aie.wire(%[[VAL_690]] : East, %[[VAL_696:.*]] : West) -// CHECK: aie.wire(%[[VAL_697:.*]] : North, %[[VAL_696]] : South) -// CHECK: aie.wire(%[[VAL_217]] : DMA, %[[VAL_697]] : DMA) -// CHECK: aie.wire(%[[VAL_691]] : East, %[[VAL_698:.*]] : West) -// CHECK: aie.wire(%[[VAL_216]] : Core, %[[VAL_698]] : Core) -// CHECK: aie.wire(%[[VAL_216]] : DMA, %[[VAL_698]] : DMA) -// CHECK: aie.wire(%[[VAL_696]] : North, %[[VAL_698]] : South) -// CHECK: aie.wire(%[[VAL_692]] : East, %[[VAL_699:.*]] : West) -// CHECK: aie.wire(%[[VAL_237]] : Core, %[[VAL_699]] : Core) -// CHECK: aie.wire(%[[VAL_237]] : DMA, %[[VAL_699]] : DMA) -// CHECK: aie.wire(%[[VAL_698]] : North, %[[VAL_699]] : South) -// CHECK: aie.wire(%[[VAL_693]] : East, %[[VAL_700:.*]] : West) -// CHECK: aie.wire(%[[VAL_161]] : Core, %[[VAL_700]] : Core) -// CHECK: aie.wire(%[[VAL_161]] : DMA, %[[VAL_700]] : DMA) -// CHECK: aie.wire(%[[VAL_699]] : North, %[[VAL_700]] : South) -// CHECK: aie.wire(%[[VAL_694]] : East, %[[VAL_701:.*]] : West) -// CHECK: aie.wire(%[[VAL_83]] : Core, %[[VAL_701]] : Core) -// CHECK: aie.wire(%[[VAL_83]] : DMA, %[[VAL_701]] : DMA) -// CHECK: aie.wire(%[[VAL_700]] : North, %[[VAL_701]] : South) -// CHECK: aie.wire(%[[VAL_695]] : East, %[[VAL_702:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_702]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_702]] : DMA) -// CHECK: aie.wire(%[[VAL_701]] : North, %[[VAL_702]] : South) -// CHECK: aie.wire(%[[VAL_696]] : East, %[[VAL_703:.*]] : West) -// CHECK: aie.wire(%[[VAL_704:.*]] : North, %[[VAL_703]] : South) -// CHECK: aie.wire(%[[VAL_198]] : DMA, %[[VAL_704]] : DMA) -// CHECK: aie.wire(%[[VAL_698]] : East, %[[VAL_705:.*]] : West) -// CHECK: aie.wire(%[[VAL_197]] : Core, %[[VAL_705]] : Core) -// CHECK: aie.wire(%[[VAL_197]] : DMA, %[[VAL_705]] : DMA) -// CHECK: aie.wire(%[[VAL_703]] : North, %[[VAL_705]] : South) -// CHECK: aie.wire(%[[VAL_699]] : East, %[[VAL_706:.*]] : West) -// CHECK: aie.wire(%[[VAL_196]] : Core, %[[VAL_706]] : Core) -// CHECK: aie.wire(%[[VAL_196]] : DMA, %[[VAL_706]] : DMA) -// CHECK: aie.wire(%[[VAL_705]] : North, %[[VAL_706]] : South) -// CHECK: aie.wire(%[[VAL_700]] : East, %[[VAL_707:.*]] : West) -// CHECK: aie.wire(%[[VAL_372]] : Core, %[[VAL_707]] : Core) -// CHECK: aie.wire(%[[VAL_372]] : DMA, %[[VAL_707]] : DMA) -// CHECK: aie.wire(%[[VAL_706]] : North, %[[VAL_707]] : South) -// CHECK: aie.wire(%[[VAL_701]] : East, %[[VAL_708:.*]] : West) -// CHECK: aie.wire(%[[VAL_530]] : Core, %[[VAL_708]] : Core) -// CHECK: aie.wire(%[[VAL_530]] : DMA, %[[VAL_708]] : DMA) -// CHECK: aie.wire(%[[VAL_707]] : North, %[[VAL_708]] : South) -// CHECK: aie.wire(%[[VAL_702]] : East, %[[VAL_709:.*]] : West) -// CHECK: aie.wire(%[[VAL_478]] : Core, %[[VAL_709]] : Core) -// CHECK: aie.wire(%[[VAL_478]] : DMA, %[[VAL_709]] : DMA) -// CHECK: aie.wire(%[[VAL_708]] : North, %[[VAL_709]] : South) -// CHECK: aie.wire(%[[VAL_703]] : East, %[[VAL_710:.*]] : West) -// CHECK: aie.wire(%[[VAL_705]] : East, %[[VAL_711:.*]] : West) -// CHECK: aie.wire(%[[VAL_377]] : Core, %[[VAL_711]] : Core) -// CHECK: aie.wire(%[[VAL_377]] : DMA, %[[VAL_711]] : DMA) -// CHECK: aie.wire(%[[VAL_710]] : North, %[[VAL_711]] : South) -// CHECK: aie.wire(%[[VAL_706]] : East, %[[VAL_712:.*]] : West) -// CHECK: aie.wire(%[[VAL_409]] : Core, %[[VAL_712]] : Core) -// CHECK: aie.wire(%[[VAL_409]] : DMA, %[[VAL_712]] : DMA) -// CHECK: aie.wire(%[[VAL_711]] : North, %[[VAL_712]] : South) -// CHECK: aie.wire(%[[VAL_707]] : East, %[[VAL_713:.*]] : West) -// CHECK: aie.wire(%[[VAL_453]] : Core, %[[VAL_713]] : Core) -// CHECK: aie.wire(%[[VAL_453]] : DMA, %[[VAL_713]] : DMA) -// CHECK: aie.wire(%[[VAL_712]] : North, %[[VAL_713]] : South) -// CHECK: aie.wire(%[[VAL_708]] : East, %[[VAL_714:.*]] : West) -// CHECK: aie.wire(%[[VAL_532]] : Core, %[[VAL_714]] : Core) -// CHECK: aie.wire(%[[VAL_532]] : DMA, %[[VAL_714]] : DMA) -// CHECK: aie.wire(%[[VAL_713]] : North, %[[VAL_714]] : South) -// CHECK: aie.wire(%[[VAL_709]] : East, %[[VAL_715:.*]] : West) -// CHECK: aie.wire(%[[VAL_480]] : Core, %[[VAL_715]] : Core) -// CHECK: aie.wire(%[[VAL_480]] : DMA, %[[VAL_715]] : DMA) -// CHECK: aie.wire(%[[VAL_714]] : North, %[[VAL_715]] : South) -// CHECK: aie.wire(%[[VAL_710]] : East, %[[VAL_716:.*]] : West) -// CHECK: aie.wire(%[[VAL_711]] : East, %[[VAL_717:.*]] : West) -// CHECK: aie.wire(%[[VAL_379]] : Core, %[[VAL_717]] : Core) -// CHECK: aie.wire(%[[VAL_379]] : DMA, %[[VAL_717]] : DMA) -// CHECK: aie.wire(%[[VAL_716]] : North, %[[VAL_717]] : South) -// CHECK: aie.wire(%[[VAL_712]] : East, %[[VAL_718:.*]] : West) -// CHECK: aie.wire(%[[VAL_411]] : Core, %[[VAL_718]] : Core) -// CHECK: aie.wire(%[[VAL_411]] : DMA, %[[VAL_718]] : DMA) -// CHECK: aie.wire(%[[VAL_717]] : North, %[[VAL_718]] : South) -// CHECK: aie.wire(%[[VAL_713]] : East, %[[VAL_719:.*]] : West) -// CHECK: aie.wire(%[[VAL_455]] : Core, %[[VAL_719]] : Core) -// CHECK: aie.wire(%[[VAL_455]] : DMA, %[[VAL_719]] : DMA) -// CHECK: aie.wire(%[[VAL_718]] : North, %[[VAL_719]] : South) -// CHECK: aie.wire(%[[VAL_714]] : East, %[[VAL_720:.*]] : West) -// CHECK: aie.wire(%[[VAL_534]] : Core, %[[VAL_720]] : Core) -// CHECK: aie.wire(%[[VAL_534]] : DMA, %[[VAL_720]] : DMA) -// CHECK: aie.wire(%[[VAL_719]] : North, %[[VAL_720]] : South) -// CHECK: aie.wire(%[[VAL_715]] : East, %[[VAL_721:.*]] : West) -// CHECK: aie.wire(%[[VAL_482]] : Core, %[[VAL_721]] : Core) -// CHECK: aie.wire(%[[VAL_482]] : DMA, %[[VAL_721]] : DMA) -// CHECK: aie.wire(%[[VAL_720]] : North, %[[VAL_721]] : South) -// CHECK: aie.wire(%[[VAL_716]] : East, %[[VAL_722:.*]] : West) -// CHECK: aie.wire(%[[VAL_717]] : East, %[[VAL_723:.*]] : West) -// CHECK: aie.wire(%[[VAL_381]] : Core, %[[VAL_723]] : Core) -// CHECK: aie.wire(%[[VAL_381]] : DMA, %[[VAL_723]] : DMA) -// CHECK: aie.wire(%[[VAL_722]] : North, %[[VAL_723]] : South) -// CHECK: aie.wire(%[[VAL_718]] : East, %[[VAL_724:.*]] : West) -// CHECK: aie.wire(%[[VAL_413]] : Core, %[[VAL_724]] : Core) -// CHECK: aie.wire(%[[VAL_413]] : DMA, %[[VAL_724]] : DMA) -// CHECK: aie.wire(%[[VAL_723]] : North, %[[VAL_724]] : South) -// CHECK: aie.wire(%[[VAL_719]] : East, %[[VAL_725:.*]] : West) -// CHECK: aie.wire(%[[VAL_457]] : Core, %[[VAL_725]] : Core) -// CHECK: aie.wire(%[[VAL_457]] : DMA, %[[VAL_725]] : DMA) -// CHECK: aie.wire(%[[VAL_724]] : North, %[[VAL_725]] : South) -// CHECK: aie.wire(%[[VAL_720]] : East, %[[VAL_726:.*]] : West) -// CHECK: aie.wire(%[[VAL_536]] : Core, %[[VAL_726]] : Core) -// CHECK: aie.wire(%[[VAL_536]] : DMA, %[[VAL_726]] : DMA) -// CHECK: aie.wire(%[[VAL_725]] : North, %[[VAL_726]] : South) -// CHECK: aie.wire(%[[VAL_721]] : East, %[[VAL_727:.*]] : West) -// CHECK: aie.wire(%[[VAL_484]] : Core, %[[VAL_727]] : Core) -// CHECK: aie.wire(%[[VAL_484]] : DMA, %[[VAL_727]] : DMA) -// CHECK: aie.wire(%[[VAL_726]] : North, %[[VAL_727]] : South) -// CHECK: aie.wire(%[[VAL_722]] : East, %[[VAL_728:.*]] : West) -// CHECK: aie.wire(%[[VAL_723]] : East, %[[VAL_729:.*]] : West) -// CHECK: aie.wire(%[[VAL_383]] : Core, %[[VAL_729]] : Core) -// CHECK: aie.wire(%[[VAL_383]] : DMA, %[[VAL_729]] : DMA) -// CHECK: aie.wire(%[[VAL_728]] : North, %[[VAL_729]] : South) -// CHECK: aie.wire(%[[VAL_724]] : East, %[[VAL_730:.*]] : West) -// CHECK: aie.wire(%[[VAL_415]] : Core, %[[VAL_730]] : Core) -// CHECK: aie.wire(%[[VAL_415]] : DMA, %[[VAL_730]] : DMA) -// CHECK: aie.wire(%[[VAL_729]] : North, %[[VAL_730]] : South) -// CHECK: aie.wire(%[[VAL_725]] : East, %[[VAL_731:.*]] : West) -// CHECK: aie.wire(%[[VAL_459]] : Core, %[[VAL_731]] : Core) -// CHECK: aie.wire(%[[VAL_459]] : DMA, %[[VAL_731]] : DMA) -// CHECK: aie.wire(%[[VAL_730]] : North, %[[VAL_731]] : South) -// CHECK: aie.wire(%[[VAL_726]] : East, %[[VAL_732:.*]] : West) -// CHECK: aie.wire(%[[VAL_486]] : Core, %[[VAL_732]] : Core) -// CHECK: aie.wire(%[[VAL_486]] : DMA, %[[VAL_732]] : DMA) -// CHECK: aie.wire(%[[VAL_731]] : North, %[[VAL_732]] : South) -// CHECK: aie.wire(%[[VAL_727]] : East, %[[VAL_733:.*]] : West) -// CHECK: aie.wire(%[[VAL_488]] : Core, %[[VAL_733]] : Core) -// CHECK: aie.wire(%[[VAL_488]] : DMA, %[[VAL_733]] : DMA) -// CHECK: aie.wire(%[[VAL_732]] : North, %[[VAL_733]] : South) -// CHECK: aie.wire(%[[VAL_728]] : East, %[[VAL_734:.*]] : West) -// CHECK: aie.wire(%[[VAL_729]] : East, %[[VAL_735:.*]] : West) -// CHECK: aie.wire(%[[VAL_385]] : Core, %[[VAL_735]] : Core) -// CHECK: aie.wire(%[[VAL_385]] : DMA, %[[VAL_735]] : DMA) -// CHECK: aie.wire(%[[VAL_734]] : North, %[[VAL_735]] : South) -// CHECK: aie.wire(%[[VAL_730]] : East, %[[VAL_736:.*]] : West) -// CHECK: aie.wire(%[[VAL_417]] : Core, %[[VAL_736]] : Core) -// CHECK: aie.wire(%[[VAL_417]] : DMA, %[[VAL_736]] : DMA) -// CHECK: aie.wire(%[[VAL_735]] : North, %[[VAL_736]] : South) -// CHECK: aie.wire(%[[VAL_731]] : East, %[[VAL_737:.*]] : West) -// CHECK: aie.wire(%[[VAL_461]] : Core, %[[VAL_737]] : Core) -// CHECK: aie.wire(%[[VAL_461]] : DMA, %[[VAL_737]] : DMA) -// CHECK: aie.wire(%[[VAL_736]] : North, %[[VAL_737]] : South) -// CHECK: aie.wire(%[[VAL_732]] : East, %[[VAL_738:.*]] : West) -// CHECK: aie.wire(%[[VAL_538]] : Core, %[[VAL_738]] : Core) -// CHECK: aie.wire(%[[VAL_538]] : DMA, %[[VAL_738]] : DMA) -// CHECK: aie.wire(%[[VAL_737]] : North, %[[VAL_738]] : South) -// CHECK: aie.wire(%[[VAL_733]] : East, %[[VAL_739:.*]] : West) -// CHECK: aie.wire(%[[VAL_597]] : Core, %[[VAL_739]] : Core) -// CHECK: aie.wire(%[[VAL_597]] : DMA, %[[VAL_739]] : DMA) -// CHECK: aie.wire(%[[VAL_738]] : North, %[[VAL_739]] : South) -// CHECK: aie.wire(%[[VAL_734]] : East, %[[VAL_740:.*]] : West) -// CHECK: aie.wire(%[[VAL_735]] : East, %[[VAL_741:.*]] : West) -// CHECK: aie.wire(%[[VAL_387]] : Core, %[[VAL_741]] : Core) -// CHECK: aie.wire(%[[VAL_387]] : DMA, %[[VAL_741]] : DMA) -// CHECK: aie.wire(%[[VAL_740]] : North, %[[VAL_741]] : South) -// CHECK: aie.wire(%[[VAL_736]] : East, %[[VAL_742:.*]] : West) -// CHECK: aie.wire(%[[VAL_419]] : Core, %[[VAL_742]] : Core) -// CHECK: aie.wire(%[[VAL_419]] : DMA, %[[VAL_742]] : DMA) -// CHECK: aie.wire(%[[VAL_741]] : North, %[[VAL_742]] : South) -// CHECK: aie.wire(%[[VAL_737]] : East, %[[VAL_743:.*]] : West) -// CHECK: aie.wire(%[[VAL_463]] : Core, %[[VAL_743]] : Core) -// CHECK: aie.wire(%[[VAL_463]] : DMA, %[[VAL_743]] : DMA) -// CHECK: aie.wire(%[[VAL_742]] : North, %[[VAL_743]] : South) -// CHECK: aie.wire(%[[VAL_738]] : East, %[[VAL_744:.*]] : West) -// CHECK: aie.wire(%[[VAL_540]] : Core, %[[VAL_744]] : Core) -// CHECK: aie.wire(%[[VAL_540]] : DMA, %[[VAL_744]] : DMA) -// CHECK: aie.wire(%[[VAL_743]] : North, %[[VAL_744]] : South) -// CHECK: aie.wire(%[[VAL_739]] : East, %[[VAL_745:.*]] : West) -// CHECK: aie.wire(%[[VAL_599]] : Core, %[[VAL_745]] : Core) -// CHECK: aie.wire(%[[VAL_599]] : DMA, %[[VAL_745]] : DMA) -// CHECK: aie.wire(%[[VAL_744]] : North, %[[VAL_745]] : South) -// CHECK: aie.wire(%[[VAL_740]] : East, %[[VAL_746:.*]] : West) -// CHECK: aie.wire(%[[VAL_747:.*]] : North, %[[VAL_746]] : South) -// CHECK: aie.wire(%[[VAL_179]] : DMA, %[[VAL_747]] : DMA) -// CHECK: aie.wire(%[[VAL_741]] : East, %[[VAL_748:.*]] : West) -// CHECK: aie.wire(%[[VAL_178]] : Core, %[[VAL_748]] : Core) -// CHECK: aie.wire(%[[VAL_178]] : DMA, %[[VAL_748]] : DMA) -// CHECK: aie.wire(%[[VAL_746]] : North, %[[VAL_748]] : South) -// CHECK: aie.wire(%[[VAL_742]] : East, %[[VAL_749:.*]] : West) -// CHECK: aie.wire(%[[VAL_177]] : Core, %[[VAL_749]] : Core) -// CHECK: aie.wire(%[[VAL_177]] : DMA, %[[VAL_749]] : DMA) -// CHECK: aie.wire(%[[VAL_748]] : North, %[[VAL_749]] : South) -// CHECK: aie.wire(%[[VAL_743]] : East, %[[VAL_750:.*]] : West) -// CHECK: aie.wire(%[[VAL_465]] : Core, %[[VAL_750]] : Core) -// CHECK: aie.wire(%[[VAL_465]] : DMA, %[[VAL_750]] : DMA) -// CHECK: aie.wire(%[[VAL_749]] : North, %[[VAL_750]] : South) -// CHECK: aie.wire(%[[VAL_744]] : East, %[[VAL_751:.*]] : West) -// CHECK: aie.wire(%[[VAL_552]] : Core, %[[VAL_751]] : Core) -// CHECK: aie.wire(%[[VAL_552]] : DMA, %[[VAL_751]] : DMA) -// CHECK: aie.wire(%[[VAL_750]] : North, %[[VAL_751]] : South) -// CHECK: aie.wire(%[[VAL_745]] : East, %[[VAL_752:.*]] : West) -// CHECK: aie.wire(%[[VAL_601]] : Core, %[[VAL_752]] : Core) -// CHECK: aie.wire(%[[VAL_601]] : DMA, %[[VAL_752]] : DMA) -// CHECK: aie.wire(%[[VAL_751]] : North, %[[VAL_752]] : South) -// CHECK: aie.wire(%[[VAL_746]] : East, %[[VAL_753:.*]] : West) -// CHECK: aie.wire(%[[VAL_754:.*]] : North, %[[VAL_753]] : South) -// CHECK: aie.wire(%[[VAL_160]] : DMA, %[[VAL_754]] : DMA) -// CHECK: aie.wire(%[[VAL_748]] : East, %[[VAL_755:.*]] : West) -// CHECK: aie.wire(%[[VAL_159]] : Core, %[[VAL_755]] : Core) -// CHECK: aie.wire(%[[VAL_159]] : DMA, %[[VAL_755]] : DMA) -// CHECK: aie.wire(%[[VAL_753]] : North, %[[VAL_755]] : South) -// CHECK: aie.wire(%[[VAL_749]] : East, %[[VAL_756:.*]] : West) -// CHECK: aie.wire(%[[VAL_158]] : Core, %[[VAL_756]] : Core) -// CHECK: aie.wire(%[[VAL_158]] : DMA, %[[VAL_756]] : DMA) -// CHECK: aie.wire(%[[VAL_755]] : North, %[[VAL_756]] : South) -// CHECK: aie.wire(%[[VAL_750]] : East, %[[VAL_757:.*]] : West) -// CHECK: aie.wire(%[[VAL_467]] : Core, %[[VAL_757]] : Core) -// CHECK: aie.wire(%[[VAL_467]] : DMA, %[[VAL_757]] : DMA) -// CHECK: aie.wire(%[[VAL_756]] : North, %[[VAL_757]] : South) -// CHECK: aie.wire(%[[VAL_751]] : East, %[[VAL_758:.*]] : West) -// CHECK: aie.wire(%[[VAL_554]] : Core, %[[VAL_758]] : Core) -// CHECK: aie.wire(%[[VAL_554]] : DMA, %[[VAL_758]] : DMA) -// CHECK: aie.wire(%[[VAL_757]] : North, %[[VAL_758]] : South) -// CHECK: aie.wire(%[[VAL_753]] : East, %[[VAL_759:.*]] : West) -// CHECK: aie.wire(%[[VAL_755]] : East, %[[VAL_760:.*]] : West) -// CHECK: aie.wire(%[[VAL_423]] : Core, %[[VAL_760]] : Core) -// CHECK: aie.wire(%[[VAL_423]] : DMA, %[[VAL_760]] : DMA) -// CHECK: aie.wire(%[[VAL_759]] : North, %[[VAL_760]] : South) -// CHECK: aie.wire(%[[VAL_756]] : East, %[[VAL_761:.*]] : West) -// CHECK: aie.wire(%[[VAL_425]] : Core, %[[VAL_761]] : Core) -// CHECK: aie.wire(%[[VAL_425]] : DMA, %[[VAL_761]] : DMA) -// CHECK: aie.wire(%[[VAL_760]] : North, %[[VAL_761]] : South) -// CHECK: aie.wire(%[[VAL_757]] : East, %[[VAL_762:.*]] : West) -// CHECK: aie.wire(%[[VAL_469]] : Core, %[[VAL_762]] : Core) -// CHECK: aie.wire(%[[VAL_469]] : DMA, %[[VAL_762]] : DMA) -// CHECK: aie.wire(%[[VAL_761]] : North, %[[VAL_762]] : South) -// CHECK: aie.wire(%[[VAL_758]] : East, %[[VAL_763:.*]] : West) -// CHECK: aie.wire(%[[VAL_556]] : Core, %[[VAL_763]] : Core) -// CHECK: aie.wire(%[[VAL_556]] : DMA, %[[VAL_763]] : DMA) -// CHECK: aie.wire(%[[VAL_762]] : North, %[[VAL_763]] : South) -// CHECK: aie.wire(%[[VAL_759]] : East, %[[VAL_764:.*]] : West) -// CHECK: aie.wire(%[[VAL_760]] : East, %[[VAL_765:.*]] : West) -// CHECK: aie.wire(%[[VAL_427]] : Core, %[[VAL_765]] : Core) -// CHECK: aie.wire(%[[VAL_427]] : DMA, %[[VAL_765]] : DMA) -// CHECK: aie.wire(%[[VAL_764]] : North, %[[VAL_765]] : South) -// CHECK: aie.wire(%[[VAL_761]] : East, %[[VAL_766:.*]] : West) -// CHECK: aie.wire(%[[VAL_542]] : Core, %[[VAL_766]] : Core) -// CHECK: aie.wire(%[[VAL_542]] : DMA, %[[VAL_766]] : DMA) -// CHECK: aie.wire(%[[VAL_765]] : North, %[[VAL_766]] : South) -// CHECK: aie.wire(%[[VAL_762]] : East, %[[VAL_767:.*]] : West) -// CHECK: aie.wire(%[[VAL_490]] : Core, %[[VAL_767]] : Core) -// CHECK: aie.wire(%[[VAL_490]] : DMA, %[[VAL_767]] : DMA) -// CHECK: aie.wire(%[[VAL_766]] : North, %[[VAL_767]] : South) -// CHECK: aie.wire(%[[VAL_763]] : East, %[[VAL_768:.*]] : West) -// CHECK: aie.wire(%[[VAL_603]] : Core, %[[VAL_768]] : Core) -// CHECK: aie.wire(%[[VAL_603]] : DMA, %[[VAL_768]] : DMA) -// CHECK: aie.wire(%[[VAL_767]] : North, %[[VAL_768]] : South) -// CHECK: aie.wire(%[[VAL_764]] : East, %[[VAL_769:.*]] : West) -// CHECK: aie.wire(%[[VAL_765]] : East, %[[VAL_770:.*]] : West) -// CHECK: aie.wire(%[[VAL_429]] : Core, %[[VAL_770]] : Core) -// CHECK: aie.wire(%[[VAL_429]] : DMA, %[[VAL_770]] : DMA) -// CHECK: aie.wire(%[[VAL_769]] : North, %[[VAL_770]] : South) -// CHECK: aie.wire(%[[VAL_766]] : East, %[[VAL_771:.*]] : West) -// CHECK: aie.wire(%[[VAL_544]] : Core, %[[VAL_771]] : Core) -// CHECK: aie.wire(%[[VAL_544]] : DMA, %[[VAL_771]] : DMA) -// CHECK: aie.wire(%[[VAL_770]] : North, %[[VAL_771]] : South) -// CHECK: aie.wire(%[[VAL_767]] : East, %[[VAL_772:.*]] : West) -// CHECK: aie.wire(%[[VAL_492]] : Core, %[[VAL_772]] : Core) -// CHECK: aie.wire(%[[VAL_492]] : DMA, %[[VAL_772]] : DMA) -// CHECK: aie.wire(%[[VAL_771]] : North, %[[VAL_772]] : South) -// CHECK: aie.wire(%[[VAL_768]] : East, %[[VAL_773:.*]] : West) -// CHECK: aie.wire(%[[VAL_605]] : Core, %[[VAL_773]] : Core) -// CHECK: aie.wire(%[[VAL_605]] : DMA, %[[VAL_773]] : DMA) -// CHECK: aie.wire(%[[VAL_772]] : North, %[[VAL_773]] : South) -// CHECK: aie.wire(%[[VAL_769]] : East, %[[VAL_774:.*]] : West) -// CHECK: aie.wire(%[[VAL_770]] : East, %[[VAL_775:.*]] : West) -// CHECK: aie.wire(%[[VAL_431]] : Core, %[[VAL_775]] : Core) -// CHECK: aie.wire(%[[VAL_431]] : DMA, %[[VAL_775]] : DMA) -// CHECK: aie.wire(%[[VAL_774]] : North, %[[VAL_775]] : South) -// CHECK: aie.wire(%[[VAL_771]] : East, %[[VAL_776:.*]] : West) -// CHECK: aie.wire(%[[VAL_546]] : Core, %[[VAL_776]] : Core) -// CHECK: aie.wire(%[[VAL_546]] : DMA, %[[VAL_776]] : DMA) -// CHECK: aie.wire(%[[VAL_775]] : North, %[[VAL_776]] : South) -// CHECK: aie.wire(%[[VAL_772]] : East, %[[VAL_777:.*]] : West) -// CHECK: aie.wire(%[[VAL_494]] : Core, %[[VAL_777]] : Core) -// CHECK: aie.wire(%[[VAL_494]] : DMA, %[[VAL_777]] : DMA) -// CHECK: aie.wire(%[[VAL_776]] : North, %[[VAL_777]] : South) -// CHECK: aie.wire(%[[VAL_773]] : East, %[[VAL_778:.*]] : West) -// CHECK: aie.wire(%[[VAL_607]] : Core, %[[VAL_778]] : Core) -// CHECK: aie.wire(%[[VAL_607]] : DMA, %[[VAL_778]] : DMA) -// CHECK: aie.wire(%[[VAL_777]] : North, %[[VAL_778]] : South) -// CHECK: aie.wire(%[[VAL_774]] : East, %[[VAL_779:.*]] : West) -// CHECK: aie.wire(%[[VAL_775]] : East, %[[VAL_780:.*]] : West) -// CHECK: aie.wire(%[[VAL_433]] : Core, %[[VAL_780]] : Core) -// CHECK: aie.wire(%[[VAL_433]] : DMA, %[[VAL_780]] : DMA) -// CHECK: aie.wire(%[[VAL_779]] : North, %[[VAL_780]] : South) -// CHECK: aie.wire(%[[VAL_776]] : East, %[[VAL_781:.*]] : West) -// CHECK: aie.wire(%[[VAL_496]] : Core, %[[VAL_781]] : Core) -// CHECK: aie.wire(%[[VAL_496]] : DMA, %[[VAL_781]] : DMA) -// CHECK: aie.wire(%[[VAL_780]] : North, %[[VAL_781]] : South) -// CHECK: aie.wire(%[[VAL_777]] : East, %[[VAL_782:.*]] : West) -// CHECK: aie.wire(%[[VAL_498]] : Core, %[[VAL_782]] : Core) -// CHECK: aie.wire(%[[VAL_498]] : DMA, %[[VAL_782]] : DMA) -// CHECK: aie.wire(%[[VAL_781]] : North, %[[VAL_782]] : South) -// CHECK: aie.wire(%[[VAL_778]] : East, %[[VAL_783:.*]] : West) -// CHECK: aie.wire(%[[VAL_609]] : Core, %[[VAL_783]] : Core) -// CHECK: aie.wire(%[[VAL_609]] : DMA, %[[VAL_783]] : DMA) -// CHECK: aie.wire(%[[VAL_782]] : North, %[[VAL_783]] : South) -// CHECK: aie.wire(%[[VAL_779]] : East, %[[VAL_784:.*]] : West) -// CHECK: aie.wire(%[[VAL_780]] : East, %[[VAL_785:.*]] : West) -// CHECK: aie.wire(%[[VAL_435]] : Core, %[[VAL_785]] : Core) -// CHECK: aie.wire(%[[VAL_435]] : DMA, %[[VAL_785]] : DMA) -// CHECK: aie.wire(%[[VAL_784]] : North, %[[VAL_785]] : South) -// CHECK: aie.wire(%[[VAL_781]] : East, %[[VAL_786:.*]] : West) -// CHECK: aie.wire(%[[VAL_500]] : Core, %[[VAL_786]] : Core) -// CHECK: aie.wire(%[[VAL_500]] : DMA, %[[VAL_786]] : DMA) -// CHECK: aie.wire(%[[VAL_785]] : North, %[[VAL_786]] : South) -// CHECK: aie.wire(%[[VAL_782]] : East, %[[VAL_787:.*]] : West) -// CHECK: aie.wire(%[[VAL_558]] : Core, %[[VAL_787]] : Core) -// CHECK: aie.wire(%[[VAL_558]] : DMA, %[[VAL_787]] : DMA) -// CHECK: aie.wire(%[[VAL_786]] : North, %[[VAL_787]] : South) -// CHECK: aie.wire(%[[VAL_783]] : East, %[[VAL_788:.*]] : West) -// CHECK: aie.wire(%[[VAL_611]] : Core, %[[VAL_788]] : Core) -// CHECK: aie.wire(%[[VAL_611]] : DMA, %[[VAL_788]] : DMA) -// CHECK: aie.wire(%[[VAL_787]] : North, %[[VAL_788]] : South) -// CHECK: aie.wire(%[[VAL_784]] : East, %[[VAL_789:.*]] : West) -// CHECK: aie.wire(%[[VAL_790:.*]] : North, %[[VAL_789]] : South) -// CHECK: aie.wire(%[[VAL_140]] : DMA, %[[VAL_790]] : DMA) -// CHECK: aie.wire(%[[VAL_785]] : East, %[[VAL_791:.*]] : West) -// CHECK: aie.wire(%[[VAL_139]] : Core, %[[VAL_791]] : Core) -// CHECK: aie.wire(%[[VAL_139]] : DMA, %[[VAL_791]] : DMA) -// CHECK: aie.wire(%[[VAL_789]] : North, %[[VAL_791]] : South) -// CHECK: aie.wire(%[[VAL_786]] : East, %[[VAL_792:.*]] : West) -// CHECK: aie.wire(%[[VAL_138]] : Core, %[[VAL_792]] : Core) -// CHECK: aie.wire(%[[VAL_138]] : DMA, %[[VAL_792]] : DMA) -// CHECK: aie.wire(%[[VAL_791]] : North, %[[VAL_792]] : South) -// CHECK: aie.wire(%[[VAL_787]] : East, %[[VAL_793:.*]] : West) -// CHECK: aie.wire(%[[VAL_560]] : Core, %[[VAL_793]] : Core) -// CHECK: aie.wire(%[[VAL_560]] : DMA, %[[VAL_793]] : DMA) -// CHECK: aie.wire(%[[VAL_792]] : North, %[[VAL_793]] : South) -// CHECK: aie.wire(%[[VAL_788]] : East, %[[VAL_794:.*]] : West) -// CHECK: aie.wire(%[[VAL_613]] : Core, %[[VAL_794]] : Core) -// CHECK: aie.wire(%[[VAL_613]] : DMA, %[[VAL_794]] : DMA) -// CHECK: aie.wire(%[[VAL_793]] : North, %[[VAL_794]] : South) -// CHECK: aie.wire(%[[VAL_789]] : East, %[[VAL_795:.*]] : West) -// CHECK: aie.wire(%[[VAL_796:.*]] : North, %[[VAL_795]] : South) -// CHECK: aie.wire(%[[VAL_120]] : DMA, %[[VAL_796]] : DMA) -// CHECK: aie.wire(%[[VAL_791]] : East, %[[VAL_797:.*]] : West) -// CHECK: aie.wire(%[[VAL_119]] : Core, %[[VAL_797]] : Core) -// CHECK: aie.wire(%[[VAL_119]] : DMA, %[[VAL_797]] : DMA) -// CHECK: aie.wire(%[[VAL_795]] : North, %[[VAL_797]] : South) -// CHECK: aie.wire(%[[VAL_792]] : East, %[[VAL_798:.*]] : West) -// CHECK: aie.wire(%[[VAL_118]] : Core, %[[VAL_798]] : Core) -// CHECK: aie.wire(%[[VAL_118]] : DMA, %[[VAL_798]] : DMA) -// CHECK: aie.wire(%[[VAL_797]] : North, %[[VAL_798]] : South) -// CHECK: aie.wire(%[[VAL_794]] : East, %[[VAL_799:.*]] : West) -// CHECK: aie.wire(%[[VAL_615]] : Core, %[[VAL_799]] : Core) -// CHECK: aie.wire(%[[VAL_615]] : DMA, %[[VAL_799]] : DMA) -// CHECK: aie.wire(%[[VAL_795]] : East, %[[VAL_800:.*]] : West) -// CHECK: aie.wire(%[[VAL_797]] : East, %[[VAL_801:.*]] : West) -// CHECK: aie.wire(%[[VAL_503]] : Core, %[[VAL_801]] : Core) -// CHECK: aie.wire(%[[VAL_503]] : DMA, %[[VAL_801]] : DMA) -// CHECK: aie.wire(%[[VAL_800]] : North, %[[VAL_801]] : South) -// CHECK: aie.wire(%[[VAL_798]] : East, %[[VAL_802:.*]] : West) -// CHECK: aie.wire(%[[VAL_562]] : Core, %[[VAL_802]] : Core) -// CHECK: aie.wire(%[[VAL_562]] : DMA, %[[VAL_802]] : DMA) -// CHECK: aie.wire(%[[VAL_801]] : North, %[[VAL_802]] : South) -// CHECK: aie.wire(%[[VAL_799]] : East, %[[VAL_803:.*]] : West) -// CHECK: aie.wire(%[[VAL_617]] : Core, %[[VAL_803]] : Core) -// CHECK: aie.wire(%[[VAL_617]] : DMA, %[[VAL_803]] : DMA) -// CHECK: aie.wire(%[[VAL_800]] : East, %[[VAL_804:.*]] : West) -// CHECK: aie.wire(%[[VAL_801]] : East, %[[VAL_805:.*]] : West) -// CHECK: aie.wire(%[[VAL_505]] : Core, %[[VAL_805]] : Core) -// CHECK: aie.wire(%[[VAL_505]] : DMA, %[[VAL_805]] : DMA) -// CHECK: aie.wire(%[[VAL_804]] : North, %[[VAL_805]] : South) -// CHECK: aie.wire(%[[VAL_802]] : East, %[[VAL_806:.*]] : West) -// CHECK: aie.wire(%[[VAL_564]] : Core, %[[VAL_806]] : Core) -// CHECK: aie.wire(%[[VAL_564]] : DMA, %[[VAL_806]] : DMA) -// CHECK: aie.wire(%[[VAL_805]] : North, %[[VAL_806]] : South) -// CHECK: aie.wire(%[[VAL_803]] : East, %[[VAL_807:.*]] : West) -// CHECK: aie.wire(%[[VAL_619]] : Core, %[[VAL_807]] : Core) -// CHECK: aie.wire(%[[VAL_619]] : DMA, %[[VAL_807]] : DMA) -// CHECK: aie.wire(%[[VAL_804]] : East, %[[VAL_808:.*]] : West) -// CHECK: aie.wire(%[[VAL_805]] : East, %[[VAL_809:.*]] : West) -// CHECK: aie.wire(%[[VAL_507]] : Core, %[[VAL_809]] : Core) -// CHECK: aie.wire(%[[VAL_507]] : DMA, %[[VAL_809]] : DMA) -// CHECK: aie.wire(%[[VAL_808]] : North, %[[VAL_809]] : South) -// CHECK: aie.wire(%[[VAL_806]] : East, %[[VAL_810:.*]] : West) -// CHECK: aie.wire(%[[VAL_566]] : Core, %[[VAL_810]] : Core) -// CHECK: aie.wire(%[[VAL_566]] : DMA, %[[VAL_810]] : DMA) -// CHECK: aie.wire(%[[VAL_809]] : North, %[[VAL_810]] : South) -// CHECK: aie.wire(%[[VAL_807]] : East, %[[VAL_811:.*]] : West) -// CHECK: aie.wire(%[[VAL_621]] : Core, %[[VAL_811]] : Core) -// CHECK: aie.wire(%[[VAL_621]] : DMA, %[[VAL_811]] : DMA) -// CHECK: aie.wire(%[[VAL_808]] : East, %[[VAL_812:.*]] : West) -// CHECK: aie.wire(%[[VAL_809]] : East, %[[VAL_813:.*]] : West) -// CHECK: aie.wire(%[[VAL_509]] : Core, %[[VAL_813]] : Core) -// CHECK: aie.wire(%[[VAL_509]] : DMA, %[[VAL_813]] : DMA) -// CHECK: aie.wire(%[[VAL_812]] : North, %[[VAL_813]] : South) -// CHECK: aie.wire(%[[VAL_810]] : East, %[[VAL_814:.*]] : West) -// CHECK: aie.wire(%[[VAL_568]] : Core, %[[VAL_814]] : Core) -// CHECK: aie.wire(%[[VAL_568]] : DMA, %[[VAL_814]] : DMA) -// CHECK: aie.wire(%[[VAL_813]] : North, %[[VAL_814]] : South) -// CHECK: aie.wire(%[[VAL_811]] : East, %[[VAL_815:.*]] : West) -// CHECK: aie.wire(%[[VAL_623]] : Core, %[[VAL_815]] : Core) -// CHECK: aie.wire(%[[VAL_623]] : DMA, %[[VAL_815]] : DMA) -// CHECK: aie.wire(%[[VAL_812]] : East, %[[VAL_816:.*]] : West) -// CHECK: aie.wire(%[[VAL_813]] : East, %[[VAL_817:.*]] : West) -// CHECK: aie.wire(%[[VAL_511]] : Core, %[[VAL_817]] : Core) -// CHECK: aie.wire(%[[VAL_511]] : DMA, %[[VAL_817]] : DMA) -// CHECK: aie.wire(%[[VAL_816]] : North, %[[VAL_817]] : South) -// CHECK: aie.wire(%[[VAL_814]] : East, %[[VAL_818:.*]] : West) -// CHECK: aie.wire(%[[VAL_570]] : Core, %[[VAL_818]] : Core) -// CHECK: aie.wire(%[[VAL_570]] : DMA, %[[VAL_818]] : DMA) -// CHECK: aie.wire(%[[VAL_817]] : North, %[[VAL_818]] : South) -// CHECK: aie.wire(%[[VAL_815]] : East, %[[VAL_819:.*]] : West) -// CHECK: aie.wire(%[[VAL_625]] : Core, %[[VAL_819]] : Core) -// CHECK: aie.wire(%[[VAL_625]] : DMA, %[[VAL_819]] : DMA) -// CHECK: aie.wire(%[[VAL_816]] : East, %[[VAL_820:.*]] : West) -// CHECK: aie.wire(%[[VAL_817]] : East, %[[VAL_821:.*]] : West) -// CHECK: aie.wire(%[[VAL_513]] : Core, %[[VAL_821]] : Core) -// CHECK: aie.wire(%[[VAL_513]] : DMA, %[[VAL_821]] : DMA) -// CHECK: aie.wire(%[[VAL_820]] : North, %[[VAL_821]] : South) -// CHECK: aie.wire(%[[VAL_818]] : East, %[[VAL_822:.*]] : West) -// CHECK: aie.wire(%[[VAL_572]] : Core, %[[VAL_822]] : Core) -// CHECK: aie.wire(%[[VAL_572]] : DMA, %[[VAL_822]] : DMA) -// CHECK: aie.wire(%[[VAL_821]] : North, %[[VAL_822]] : South) -// CHECK: aie.wire(%[[VAL_819]] : East, %[[VAL_823:.*]] : West) -// CHECK: aie.wire(%[[VAL_627]] : Core, %[[VAL_823]] : Core) -// CHECK: aie.wire(%[[VAL_627]] : DMA, %[[VAL_823]] : DMA) -// CHECK: aie.wire(%[[VAL_820]] : East, %[[VAL_824:.*]] : West) -// CHECK: aie.wire(%[[VAL_825:.*]] : North, %[[VAL_824]] : South) -// CHECK: aie.wire(%[[VAL_101]] : DMA, %[[VAL_825]] : DMA) -// CHECK: aie.wire(%[[VAL_821]] : East, %[[VAL_826:.*]] : West) -// CHECK: aie.wire(%[[VAL_100]] : Core, %[[VAL_826]] : Core) -// CHECK: aie.wire(%[[VAL_100]] : DMA, %[[VAL_826]] : DMA) -// CHECK: aie.wire(%[[VAL_824]] : North, %[[VAL_826]] : South) -// CHECK: aie.wire(%[[VAL_822]] : East, %[[VAL_827:.*]] : West) -// CHECK: aie.wire(%[[VAL_99]] : Core, %[[VAL_827]] : Core) -// CHECK: aie.wire(%[[VAL_99]] : DMA, %[[VAL_827]] : DMA) -// CHECK: aie.wire(%[[VAL_826]] : North, %[[VAL_827]] : South) -// CHECK: aie.wire(%[[VAL_823]] : East, %[[VAL_828:.*]] : West) -// CHECK: aie.wire(%[[VAL_629]] : Core, %[[VAL_828]] : Core) -// CHECK: aie.wire(%[[VAL_629]] : DMA, %[[VAL_828]] : DMA) -// CHECK: aie.wire(%[[VAL_824]] : East, %[[VAL_829:.*]] : West) -// CHECK: aie.wire(%[[VAL_830:.*]] : North, %[[VAL_829]] : South) -// CHECK: aie.wire(%[[VAL_82]] : DMA, %[[VAL_830]] : DMA) -// CHECK: aie.wire(%[[VAL_826]] : East, %[[VAL_831:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : Core, %[[VAL_831]] : Core) -// CHECK: aie.wire(%[[VAL_81]] : DMA, %[[VAL_831]] : DMA) -// CHECK: aie.wire(%[[VAL_829]] : North, %[[VAL_831]] : South) -// CHECK: aie.wire(%[[VAL_827]] : East, %[[VAL_832:.*]] : West) -// CHECK: aie.wire(%[[VAL_80]] : Core, %[[VAL_832]] : Core) -// CHECK: aie.wire(%[[VAL_80]] : DMA, %[[VAL_832]] : DMA) -// CHECK: aie.wire(%[[VAL_831]] : North, %[[VAL_832]] : South) -// CHECK: aie.wire(%[[VAL_828]] : East, %[[VAL_833:.*]] : West) -// CHECK: aie.wire(%[[VAL_631]] : Core, %[[VAL_833]] : Core) -// CHECK: aie.wire(%[[VAL_631]] : DMA, %[[VAL_833]] : DMA) -// CHECK: aie.wire(%[[VAL_829]] : East, %[[VAL_834:.*]] : West) -// CHECK: aie.wire(%[[VAL_832]] : East, %[[VAL_835:.*]] : West) -// CHECK: aie.wire(%[[VAL_576]] : Core, %[[VAL_835]] : Core) -// CHECK: aie.wire(%[[VAL_576]] : DMA, %[[VAL_835]] : DMA) -// CHECK: aie.wire(%[[VAL_833]] : East, %[[VAL_836:.*]] : West) -// CHECK: aie.wire(%[[VAL_633]] : Core, %[[VAL_836]] : Core) -// CHECK: aie.wire(%[[VAL_633]] : DMA, %[[VAL_836]] : DMA) -// CHECK: aie.wire(%[[VAL_834]] : East, %[[VAL_837:.*]] : West) -// CHECK: aie.wire(%[[VAL_835]] : East, %[[VAL_838:.*]] : West) -// CHECK: aie.wire(%[[VAL_578]] : Core, %[[VAL_838]] : Core) -// CHECK: aie.wire(%[[VAL_578]] : DMA, %[[VAL_838]] : DMA) -// CHECK: aie.wire(%[[VAL_836]] : East, %[[VAL_839:.*]] : West) -// CHECK: aie.wire(%[[VAL_635]] : Core, %[[VAL_839]] : Core) -// CHECK: aie.wire(%[[VAL_635]] : DMA, %[[VAL_839]] : DMA) -// CHECK: aie.wire(%[[VAL_837]] : East, %[[VAL_840:.*]] : West) -// CHECK: aie.wire(%[[VAL_838]] : East, %[[VAL_841:.*]] : West) -// CHECK: aie.wire(%[[VAL_580]] : Core, %[[VAL_841]] : Core) -// CHECK: aie.wire(%[[VAL_580]] : DMA, %[[VAL_841]] : DMA) -// CHECK: aie.wire(%[[VAL_839]] : East, %[[VAL_842:.*]] : West) -// CHECK: aie.wire(%[[VAL_637]] : Core, %[[VAL_842]] : Core) -// CHECK: aie.wire(%[[VAL_637]] : DMA, %[[VAL_842]] : DMA) -// CHECK: aie.wire(%[[VAL_840]] : East, %[[VAL_843:.*]] : West) -// CHECK: aie.wire(%[[VAL_841]] : East, %[[VAL_844:.*]] : West) -// CHECK: aie.wire(%[[VAL_582]] : Core, %[[VAL_844]] : Core) -// CHECK: aie.wire(%[[VAL_582]] : DMA, %[[VAL_844]] : DMA) -// CHECK: aie.wire(%[[VAL_842]] : East, %[[VAL_845:.*]] : West) -// CHECK: aie.wire(%[[VAL_639]] : Core, %[[VAL_845]] : Core) -// CHECK: aie.wire(%[[VAL_639]] : DMA, %[[VAL_845]] : DMA) -// CHECK: aie.wire(%[[VAL_843]] : East, %[[VAL_846:.*]] : West) -// CHECK: aie.wire(%[[VAL_844]] : East, %[[VAL_847:.*]] : West) -// CHECK: aie.wire(%[[VAL_584]] : Core, %[[VAL_847]] : Core) -// CHECK: aie.wire(%[[VAL_584]] : DMA, %[[VAL_847]] : DMA) -// CHECK: aie.wire(%[[VAL_845]] : East, %[[VAL_848:.*]] : West) -// CHECK: aie.wire(%[[VAL_641]] : Core, %[[VAL_848]] : Core) -// CHECK: aie.wire(%[[VAL_641]] : DMA, %[[VAL_848]] : DMA) -// CHECK: aie.wire(%[[VAL_846]] : East, %[[VAL_849:.*]] : West) -// CHECK: aie.wire(%[[VAL_586]] : Core, %[[VAL_850:.*]] : Core) -// CHECK: aie.wire(%[[VAL_586]] : DMA, %[[VAL_850]] : DMA) -// CHECK: aie.wire(%[[VAL_849]] : North, %[[VAL_850]] : South) -// CHECK: aie.wire(%[[VAL_847]] : East, %[[VAL_851:.*]] : West) -// CHECK: aie.wire(%[[VAL_588]] : Core, %[[VAL_851]] : Core) -// CHECK: aie.wire(%[[VAL_588]] : DMA, %[[VAL_851]] : DMA) -// CHECK: aie.wire(%[[VAL_850]] : North, %[[VAL_851]] : South) -// CHECK: aie.wire(%[[VAL_848]] : East, %[[VAL_852:.*]] : West) -// CHECK: aie.wire(%[[VAL_643]] : Core, %[[VAL_852]] : Core) -// CHECK: aie.wire(%[[VAL_643]] : DMA, %[[VAL_852]] : DMA) -// CHECK: aie.wire(%[[VAL_849]] : East, %[[VAL_853:.*]] : West) -// CHECK: aie.wire(%[[VAL_854:.*]] : North, %[[VAL_853]] : South) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_854]] : DMA) -// CHECK: aie.wire(%[[VAL_850]] : East, %[[VAL_855:.*]] : West) -// CHECK: aie.wire(%[[VAL_61]] : Core, %[[VAL_855]] : Core) -// CHECK: aie.wire(%[[VAL_61]] : DMA, %[[VAL_855]] : DMA) -// CHECK: aie.wire(%[[VAL_853]] : North, %[[VAL_855]] : South) -// CHECK: aie.wire(%[[VAL_645]] : Core, %[[VAL_856:.*]] : Core) -// CHECK: aie.wire(%[[VAL_645]] : DMA, %[[VAL_856]] : DMA) -// CHECK: aie.wire(%[[VAL_852]] : East, %[[VAL_857:.*]] : West) -// CHECK: aie.wire(%[[VAL_647]] : Core, %[[VAL_857]] : Core) -// CHECK: aie.wire(%[[VAL_647]] : DMA, %[[VAL_857]] : DMA) -// CHECK: aie.wire(%[[VAL_856]] : North, %[[VAL_857]] : South) -// CHECK: aie.wire(%[[VAL_853]] : East, %[[VAL_858:.*]] : West) -// CHECK: aie.wire(%[[VAL_859:.*]] : North, %[[VAL_858]] : South) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_859]] : DMA) -// CHECK: aie.wire(%[[VAL_856]] : East, %[[VAL_860:.*]] : West) -// CHECK: aie.wire(%[[VAL_649]] : Core, %[[VAL_860]] : Core) -// CHECK: aie.wire(%[[VAL_649]] : DMA, %[[VAL_860]] : DMA) -// CHECK: aie.wire(%[[VAL_858]] : East, %[[VAL_861:.*]] : West) -// CHECK: aie.wire(%[[VAL_860]] : East, %[[VAL_862:.*]] : West) -// CHECK: aie.wire(%[[VAL_651]] : Core, %[[VAL_862]] : Core) -// CHECK: aie.wire(%[[VAL_651]] : DMA, %[[VAL_862]] : DMA) -// CHECK: aie.wire(%[[VAL_861]] : East, %[[VAL_863:.*]] : West) -// CHECK: aie.wire(%[[VAL_653]] : Core, %[[VAL_864:.*]] : Core) -// CHECK: aie.wire(%[[VAL_653]] : DMA, %[[VAL_864]] : DMA) -// CHECK: aie.wire(%[[VAL_862]] : East, %[[VAL_865:.*]] : West) -// CHECK: aie.wire(%[[VAL_655]] : Core, %[[VAL_865]] : Core) -// CHECK: aie.wire(%[[VAL_655]] : DMA, %[[VAL_865]] : DMA) -// CHECK: aie.wire(%[[VAL_864]] : North, %[[VAL_865]] : South) -// CHECK: aie.wire(%[[VAL_863]] : East, %[[VAL_866:.*]] : West) -// CHECK: aie.wire(%[[VAL_867:.*]] : North, %[[VAL_866]] : South) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_867]] : DMA) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_868:.*]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_868]] : DMA) -// CHECK: aie.wire(%[[VAL_866]] : North, %[[VAL_868]] : South) -// CHECK: aie.wire(%[[VAL_864]] : East, %[[VAL_869:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_869]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_869]] : DMA) -// CHECK: aie.wire(%[[VAL_868]] : North, %[[VAL_869]] : South) -// CHECK: aie.wire(%[[VAL_866]] : East, %[[VAL_870:.*]] : West) -// CHECK: aie.wire(%[[VAL_871:.*]] : North, %[[VAL_870]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_871]] : DMA) -// CHECK: } - -module @vecmul_4x4 { - aie.device(xcvc1902) { - %0 = aie.tile(47, 2) - %1 = aie.tile(47, 1) - %2 = aie.tile(47, 0) - %3 = aie.tile(3, 3) - %4 = aie.tile(10, 5) - %5 = aie.lock(%4, 2) - %6 = aie.buffer(%4) {sym_name = "buf47"} : memref<64xi32, 2> - %7 = aie.lock(%4, 1) - %8 = aie.buffer(%4) {sym_name = "buf46"} : memref<64xi32, 2> - %9 = aie.lock(%4, 0) - %10 = aie.buffer(%4) {sym_name = "buf45"} : memref<64xi32, 2> - %11 = aie.mem(%4) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%9, Acquire, 0) - aie.dma_bd(%10 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%9, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%7, Acquire, 0) - aie.dma_bd(%8 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%7, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%5, Acquire, 1) - aie.dma_bd(%6 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%5, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %12 = aie.core(%4) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%9, Acquire, 1) - aie.use_lock(%7, Acquire, 1) - aie.use_lock(%5, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %10[%arg0] : memref<64xi32, 2> - %201 = affine.load %8[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %6[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%5, Release, 1) - aie.use_lock(%7, Release, 0) - aie.use_lock(%9, Release, 0) - cf.br ^bb1 - } - %13 = aie.tile(46, 2) - %14 = aie.tile(46, 1) - %15 = aie.tile(46, 0) - %16 = aie.tile(2, 3) - %17 = aie.tile(9, 5) - %18 = aie.lock(%17, 2) - %19 = aie.buffer(%17) {sym_name = "buf44"} : memref<64xi32, 2> - %20 = aie.lock(%17, 1) - %21 = aie.buffer(%17) {sym_name = "buf43"} : memref<64xi32, 2> - %22 = aie.lock(%17, 0) - %23 = aie.buffer(%17) {sym_name = "buf42"} : memref<64xi32, 2> - %24 = aie.mem(%17) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%22, Acquire, 0) - aie.dma_bd(%23 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%22, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%20, Acquire, 0) - aie.dma_bd(%21 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%20, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%18, Acquire, 1) - aie.dma_bd(%19 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%18, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %25 = aie.core(%17) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%22, Acquire, 1) - aie.use_lock(%20, Acquire, 1) - aie.use_lock(%18, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %23[%arg0] : memref<64xi32, 2> - %201 = affine.load %21[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %19[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%18, Release, 1) - aie.use_lock(%20, Release, 0) - aie.use_lock(%22, Release, 0) - cf.br ^bb1 - } - %26 = aie.tile(43, 2) - %27 = aie.tile(43, 1) - %28 = aie.tile(43, 0) - %29 = aie.tile(1, 3) - %30 = aie.tile(8, 5) - %31 = aie.lock(%30, 2) - %32 = aie.buffer(%30) {sym_name = "buf41"} : memref<64xi32, 2> - %33 = aie.lock(%30, 1) - %34 = aie.buffer(%30) {sym_name = "buf40"} : memref<64xi32, 2> - %35 = aie.lock(%30, 0) - %36 = aie.buffer(%30) {sym_name = "buf39"} : memref<64xi32, 2> - %37 = aie.mem(%30) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%35, Acquire, 0) - aie.dma_bd(%36 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%35, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%33, Acquire, 0) - aie.dma_bd(%34 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%33, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%31, Acquire, 1) - aie.dma_bd(%32 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%31, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %38 = aie.core(%30) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%35, Acquire, 1) - aie.use_lock(%33, Acquire, 1) - aie.use_lock(%31, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %36[%arg0] : memref<64xi32, 2> - %201 = affine.load %34[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %32[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%31, Release, 1) - aie.use_lock(%33, Release, 0) - aie.use_lock(%35, Release, 0) - cf.br ^bb1 - } - %39 = aie.tile(42, 2) - %40 = aie.tile(42, 1) - %41 = aie.tile(42, 0) - %42 = aie.tile(0, 3) - %43 = aie.tile(7, 5) - %44 = aie.lock(%43, 2) - %45 = aie.buffer(%43) {sym_name = "buf38"} : memref<64xi32, 2> - %46 = aie.lock(%43, 1) - %47 = aie.buffer(%43) {sym_name = "buf37"} : memref<64xi32, 2> - %48 = aie.lock(%43, 0) - %49 = aie.buffer(%43) {sym_name = "buf36"} : memref<64xi32, 2> - %50 = aie.mem(%43) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%48, Acquire, 0) - aie.dma_bd(%49 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%48, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%46, Acquire, 0) - aie.dma_bd(%47 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%46, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%44, Acquire, 1) - aie.dma_bd(%45 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%44, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %51 = aie.core(%43) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%48, Acquire, 1) - aie.use_lock(%46, Acquire, 1) - aie.use_lock(%44, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %49[%arg0] : memref<64xi32, 2> - %201 = affine.load %47[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %45[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%44, Release, 1) - aie.use_lock(%46, Release, 0) - aie.use_lock(%48, Release, 0) - cf.br ^bb1 - } - %52 = aie.tile(35, 2) - %53 = aie.tile(35, 1) - %54 = aie.tile(35, 0) - %55 = aie.tile(10, 4) - %56 = aie.lock(%55, 2) - %57 = aie.buffer(%55) {sym_name = "buf35"} : memref<64xi32, 2> - %58 = aie.lock(%55, 1) - %59 = aie.buffer(%55) {sym_name = "buf34"} : memref<64xi32, 2> - %60 = aie.lock(%55, 0) - %61 = aie.buffer(%55) {sym_name = "buf33"} : memref<64xi32, 2> - %62 = aie.mem(%55) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%60, Acquire, 0) - aie.dma_bd(%61 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%60, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%58, Acquire, 0) - aie.dma_bd(%59 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%58, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%56, Acquire, 1) - aie.dma_bd(%57 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%56, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %63 = aie.core(%55) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%60, Acquire, 1) - aie.use_lock(%58, Acquire, 1) - aie.use_lock(%56, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %61[%arg0] : memref<64xi32, 2> - %201 = affine.load %59[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %57[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%56, Release, 1) - aie.use_lock(%58, Release, 0) - aie.use_lock(%60, Release, 0) - cf.br ^bb1 - } - %64 = aie.tile(34, 2) - %65 = aie.tile(34, 1) - %66 = aie.tile(34, 0) - %67 = aie.tile(9, 4) - %68 = aie.lock(%67, 2) - %69 = aie.buffer(%67) {sym_name = "buf32"} : memref<64xi32, 2> - %70 = aie.lock(%67, 1) - %71 = aie.buffer(%67) {sym_name = "buf31"} : memref<64xi32, 2> - %72 = aie.lock(%67, 0) - %73 = aie.buffer(%67) {sym_name = "buf30"} : memref<64xi32, 2> - %74 = aie.mem(%67) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%72, Acquire, 0) - aie.dma_bd(%73 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%72, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%70, Acquire, 0) - aie.dma_bd(%71 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%70, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%68, Acquire, 1) - aie.dma_bd(%69 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%68, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %75 = aie.core(%67) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%72, Acquire, 1) - aie.use_lock(%70, Acquire, 1) - aie.use_lock(%68, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %73[%arg0] : memref<64xi32, 2> - %201 = affine.load %71[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %69[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%68, Release, 1) - aie.use_lock(%70, Release, 0) - aie.use_lock(%72, Release, 0) - cf.br ^bb1 - } - %76 = aie.tile(27, 2) - %77 = aie.tile(27, 1) - %78 = aie.tile(27, 0) - %79 = aie.tile(1, 2) - %80 = aie.tile(8, 4) - %81 = aie.lock(%80, 2) - %82 = aie.buffer(%80) {sym_name = "buf29"} : memref<64xi32, 2> - %83 = aie.lock(%80, 1) - %84 = aie.buffer(%80) {sym_name = "buf28"} : memref<64xi32, 2> - %85 = aie.lock(%80, 0) - %86 = aie.buffer(%80) {sym_name = "buf27"} : memref<64xi32, 2> - %87 = aie.mem(%80) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%85, Acquire, 0) - aie.dma_bd(%86 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%85, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%83, Acquire, 0) - aie.dma_bd(%84 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%83, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%81, Acquire, 1) - aie.dma_bd(%82 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%81, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %88 = aie.core(%80) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%85, Acquire, 1) - aie.use_lock(%83, Acquire, 1) - aie.use_lock(%81, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %86[%arg0] : memref<64xi32, 2> - %201 = affine.load %84[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %82[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%81, Release, 1) - aie.use_lock(%83, Release, 0) - aie.use_lock(%85, Release, 0) - cf.br ^bb1 - } - %89 = aie.tile(26, 2) - %90 = aie.tile(26, 1) - %91 = aie.tile(26, 0) - %92 = aie.tile(0, 2) - %93 = aie.tile(7, 4) - %94 = aie.lock(%93, 2) - %95 = aie.buffer(%93) {sym_name = "buf26"} : memref<64xi32, 2> - %96 = aie.lock(%93, 1) - %97 = aie.buffer(%93) {sym_name = "buf25"} : memref<64xi32, 2> - %98 = aie.lock(%93, 0) - %99 = aie.buffer(%93) {sym_name = "buf24"} : memref<64xi32, 2> - %100 = aie.mem(%93) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%98, Acquire, 0) - aie.dma_bd(%99 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%98, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%96, Acquire, 0) - aie.dma_bd(%97 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%96, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%94, Acquire, 1) - aie.dma_bd(%95 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%94, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %101 = aie.core(%93) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%98, Acquire, 1) - aie.use_lock(%96, Acquire, 1) - aie.use_lock(%94, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %99[%arg0] : memref<64xi32, 2> - %201 = affine.load %97[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %95[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%94, Release, 1) - aie.use_lock(%96, Release, 0) - aie.use_lock(%98, Release, 0) - cf.br ^bb1 - } - %102 = aie.tile(19, 2) - %103 = aie.tile(19, 1) - %104 = aie.tile(19, 0) - %105 = aie.tile(10, 3) - %106 = aie.lock(%105, 2) - %107 = aie.buffer(%105) {sym_name = "buf23"} : memref<64xi32, 2> - %108 = aie.lock(%105, 1) - %109 = aie.buffer(%105) {sym_name = "buf22"} : memref<64xi32, 2> - %110 = aie.lock(%105, 0) - %111 = aie.buffer(%105) {sym_name = "buf21"} : memref<64xi32, 2> - %112 = aie.mem(%105) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%110, Acquire, 0) - aie.dma_bd(%111 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%110, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%108, Acquire, 0) - aie.dma_bd(%109 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%108, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%106, Acquire, 1) - aie.dma_bd(%107 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%106, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %113 = aie.core(%105) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%110, Acquire, 1) - aie.use_lock(%108, Acquire, 1) - aie.use_lock(%106, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %111[%arg0] : memref<64xi32, 2> - %201 = affine.load %109[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %107[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%106, Release, 1) - aie.use_lock(%108, Release, 0) - aie.use_lock(%110, Release, 0) - cf.br ^bb1 - } - %114 = aie.tile(18, 2) - %115 = aie.tile(18, 1) - %116 = aie.tile(18, 0) - %117 = aie.tile(9, 3) - %118 = aie.lock(%117, 2) - %119 = aie.buffer(%117) {sym_name = "buf20"} : memref<64xi32, 2> - %120 = aie.lock(%117, 1) - %121 = aie.buffer(%117) {sym_name = "buf19"} : memref<64xi32, 2> - %122 = aie.lock(%117, 0) - %123 = aie.buffer(%117) {sym_name = "buf18"} : memref<64xi32, 2> - %124 = aie.mem(%117) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%122, Acquire, 0) - aie.dma_bd(%123 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%122, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%120, Acquire, 0) - aie.dma_bd(%121 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%120, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%118, Acquire, 1) - aie.dma_bd(%119 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%118, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %125 = aie.core(%117) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%122, Acquire, 1) - aie.use_lock(%120, Acquire, 1) - aie.use_lock(%118, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %123[%arg0] : memref<64xi32, 2> - %201 = affine.load %121[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %119[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%118, Release, 1) - aie.use_lock(%120, Release, 0) - aie.use_lock(%122, Release, 0) - cf.br ^bb1 - } - %126 = aie.tile(11, 2) - %127 = aie.tile(11, 1) - %128 = aie.tile(11, 0) - %129 = aie.tile(1, 1) - %130 = aie.tile(8, 3) - %131 = aie.lock(%130, 2) - %132 = aie.buffer(%130) {sym_name = "buf17"} : memref<64xi32, 2> - %133 = aie.lock(%130, 1) - %134 = aie.buffer(%130) {sym_name = "buf16"} : memref<64xi32, 2> - %135 = aie.lock(%130, 0) - %136 = aie.buffer(%130) {sym_name = "buf15"} : memref<64xi32, 2> - %137 = aie.mem(%130) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%135, Acquire, 0) - aie.dma_bd(%136 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%135, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%133, Acquire, 0) - aie.dma_bd(%134 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%133, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%131, Acquire, 1) - aie.dma_bd(%132 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%131, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %138 = aie.core(%130) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%135, Acquire, 1) - aie.use_lock(%133, Acquire, 1) - aie.use_lock(%131, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %136[%arg0] : memref<64xi32, 2> - %201 = affine.load %134[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %132[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%131, Release, 1) - aie.use_lock(%133, Release, 0) - aie.use_lock(%135, Release, 0) - cf.br ^bb1 - } - %139 = aie.tile(10, 1) - %140 = aie.tile(10, 0) - %141 = aie.tile(0, 1) - %142 = aie.tile(7, 3) - %143 = aie.lock(%142, 2) - %144 = aie.buffer(%142) {sym_name = "buf14"} : memref<64xi32, 2> - %145 = aie.lock(%142, 1) - %146 = aie.buffer(%142) {sym_name = "buf13"} : memref<64xi32, 2> - %147 = aie.lock(%142, 0) - %148 = aie.buffer(%142) {sym_name = "buf12"} : memref<64xi32, 2> - %149 = aie.mem(%142) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%147, Acquire, 0) - aie.dma_bd(%148 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%147, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%145, Acquire, 0) - aie.dma_bd(%146 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%145, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%143, Acquire, 1) - aie.dma_bd(%144 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%143, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %150 = aie.core(%142) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%147, Acquire, 1) - aie.use_lock(%145, Acquire, 1) - aie.use_lock(%143, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %148[%arg0] : memref<64xi32, 2> - %201 = affine.load %146[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %144[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%143, Release, 1) - aie.use_lock(%145, Release, 0) - aie.use_lock(%147, Release, 0) - cf.br ^bb1 - } - %151 = aie.tile(7, 1) - %152 = aie.tile(7, 0) - %153 = aie.tile(10, 2) - %154 = aie.lock(%153, 2) - %155 = aie.buffer(%153) {sym_name = "buf11"} : memref<64xi32, 2> - %156 = aie.lock(%153, 1) - %157 = aie.buffer(%153) {sym_name = "buf10"} : memref<64xi32, 2> - %158 = aie.lock(%153, 0) - %159 = aie.buffer(%153) {sym_name = "buf9"} : memref<64xi32, 2> - %160 = aie.mem(%153) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%158, Acquire, 0) - aie.dma_bd(%159 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%158, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%156, Acquire, 0) - aie.dma_bd(%157 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%156, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%154, Acquire, 1) - aie.dma_bd(%155 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%154, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %161 = aie.core(%153) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%158, Acquire, 1) - aie.use_lock(%156, Acquire, 1) - aie.use_lock(%154, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %159[%arg0] : memref<64xi32, 2> - %201 = affine.load %157[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %155[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%154, Release, 1) - aie.use_lock(%156, Release, 0) - aie.use_lock(%158, Release, 0) - cf.br ^bb1 - } - %162 = aie.tile(6, 2) - %163 = aie.tile(6, 1) - %164 = aie.tile(6, 0) - %165 = aie.tile(9, 2) - %166 = aie.lock(%165, 2) - %167 = aie.buffer(%165) {sym_name = "buf8"} : memref<64xi32, 2> - %168 = aie.lock(%165, 1) - %169 = aie.buffer(%165) {sym_name = "buf7"} : memref<64xi32, 2> - %170 = aie.lock(%165, 0) - %171 = aie.buffer(%165) {sym_name = "buf6"} : memref<64xi32, 2> - %172 = aie.mem(%165) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%170, Acquire, 0) - aie.dma_bd(%171 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%170, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%168, Acquire, 0) - aie.dma_bd(%169 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%168, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%166, Acquire, 1) - aie.dma_bd(%167 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%166, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %173 = aie.core(%165) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%170, Acquire, 1) - aie.use_lock(%168, Acquire, 1) - aie.use_lock(%166, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %171[%arg0] : memref<64xi32, 2> - %201 = affine.load %169[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %167[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%166, Release, 1) - aie.use_lock(%168, Release, 0) - aie.use_lock(%170, Release, 0) - cf.br ^bb1 - } - %174 = aie.tile(3, 2) - %175 = aie.tile(3, 1) - %176 = aie.tile(3, 0) - %177 = aie.tile(1, 0) - %178 = aie.tile(8, 2) - %179 = aie.lock(%178, 2) - %180 = aie.buffer(%178) {sym_name = "buf5"} : memref<64xi32, 2> - %181 = aie.lock(%178, 1) - %182 = aie.buffer(%178) {sym_name = "buf4"} : memref<64xi32, 2> - %183 = aie.lock(%178, 0) - %184 = aie.buffer(%178) {sym_name = "buf3"} : memref<64xi32, 2> - %185 = aie.mem(%178) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%183, Acquire, 0) - aie.dma_bd(%184 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%183, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%181, Acquire, 0) - aie.dma_bd(%182 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%181, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%179, Acquire, 1) - aie.dma_bd(%180 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%179, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %186 = aie.core(%178) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%183, Acquire, 1) - aie.use_lock(%181, Acquire, 1) - aie.use_lock(%179, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %184[%arg0] : memref<64xi32, 2> - %201 = affine.load %182[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %180[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%179, Release, 1) - aie.use_lock(%181, Release, 0) - aie.use_lock(%183, Release, 0) - cf.br ^bb1 - } - %187 = aie.tile(2, 2) - %188 = aie.tile(2, 1) - %189 = aie.tile(2, 0) - %190 = aie.tile(0, 0) - %191 = aie.tile(7, 2) - %192 = aie.lock(%191, 2) - %193 = aie.buffer(%191) {sym_name = "buf2"} : memref<64xi32, 2> - %194 = aie.lock(%191, 1) - %195 = aie.buffer(%191) {sym_name = "buf1"} : memref<64xi32, 2> - %196 = aie.lock(%191, 0) - %197 = aie.buffer(%191) {sym_name = "buf0"} : memref<64xi32, 2> - %198 = aie.mem(%191) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%196, Acquire, 0) - aie.dma_bd(%197 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%196, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%194, Acquire, 0) - aie.dma_bd(%195 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%194, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%192, Acquire, 1) - aie.dma_bd(%193 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%192, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %199 = aie.core(%191) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%196, Acquire, 1) - aie.use_lock(%194, Acquire, 1) - aie.use_lock(%192, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %197[%arg0] : memref<64xi32, 2> - %201 = affine.load %195[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %193[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%192, Release, 1) - aie.use_lock(%194, Release, 0) - aie.use_lock(%196, Release, 0) - cf.br ^bb1 - } - aie.flow(%189, DMA : 0, %191, DMA : 0) - aie.flow(%189, DMA : 1, %191, DMA : 1) - aie.flow(%191, DMA : 0, %189, DMA : 0) - aie.flow(%176, DMA : 0, %178, DMA : 0) - aie.flow(%176, DMA : 1, %178, DMA : 1) - aie.flow(%178, DMA : 0, %189, DMA : 1) - aie.flow(%164, DMA : 0, %165, DMA : 0) - aie.flow(%164, DMA : 1, %165, DMA : 1) - aie.flow(%165, DMA : 0, %176, DMA : 0) - aie.flow(%152, DMA : 0, %153, DMA : 0) - aie.flow(%152, DMA : 1, %153, DMA : 1) - aie.flow(%153, DMA : 0, %176, DMA : 1) - aie.flow(%140, DMA : 0, %142, DMA : 0) - aie.flow(%140, DMA : 1, %142, DMA : 1) - aie.flow(%142, DMA : 0, %164, DMA : 0) - aie.flow(%128, DMA : 0, %130, DMA : 0) - aie.flow(%128, DMA : 1, %130, DMA : 1) - aie.flow(%130, DMA : 0, %164, DMA : 1) - aie.flow(%116, DMA : 0, %117, DMA : 0) - aie.flow(%116, DMA : 1, %117, DMA : 1) - aie.flow(%117, DMA : 0, %152, DMA : 0) - aie.flow(%104, DMA : 0, %105, DMA : 0) - aie.flow(%104, DMA : 1, %105, DMA : 1) - aie.flow(%105, DMA : 0, %152, DMA : 1) - aie.flow(%91, DMA : 0, %93, DMA : 0) - aie.flow(%91, DMA : 1, %93, DMA : 1) - aie.flow(%93, DMA : 0, %140, DMA : 0) - aie.flow(%78, DMA : 0, %80, DMA : 0) - aie.flow(%78, DMA : 1, %80, DMA : 1) - aie.flow(%80, DMA : 0, %140, DMA : 1) - aie.flow(%66, DMA : 0, %67, DMA : 0) - aie.flow(%66, DMA : 1, %67, DMA : 1) - aie.flow(%67, DMA : 0, %128, DMA : 0) - aie.flow(%54, DMA : 0, %55, DMA : 0) - aie.flow(%54, DMA : 1, %55, DMA : 1) - aie.flow(%55, DMA : 0, %128, DMA : 1) - aie.flow(%41, DMA : 0, %43, DMA : 0) - aie.flow(%41, DMA : 1, %43, DMA : 1) - aie.flow(%43, DMA : 0, %116, DMA : 0) - aie.flow(%28, DMA : 0, %30, DMA : 0) - aie.flow(%28, DMA : 1, %30, DMA : 1) - aie.flow(%30, DMA : 0, %116, DMA : 1) - aie.flow(%15, DMA : 0, %17, DMA : 0) - aie.flow(%15, DMA : 1, %17, DMA : 1) - aie.flow(%17, DMA : 0, %104, DMA : 0) - aie.flow(%2, DMA : 0, %4, DMA : 0) - aie.flow(%2, DMA : 1, %4, DMA : 1) - aie.flow(%4, DMA : 0, %104, DMA : 1) - } -} diff --git a/test/create-flows/vecmul_4x4.mlir b/test/create-flows/vecmul_4x4.mlir index 17f07ae91c..a30e7c6891 100644 --- a/test/create-flows/vecmul_4x4.mlir +++ b/test/create-flows/vecmul_4x4.mlir @@ -8,89 +8,94 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s | FileCheck %s -// CHECK: %[[T2:.*]] = aie.tile(47, 0) -// CHECK: %[[T4:.*]] = aie.tile(10, 5) -// CHECK: %[[T15:.*]] = aie.tile(46, 0) -// CHECK: %[[T17:.*]] = aie.tile(9, 5) -// CHECK: %[[T28:.*]] = aie.tile(43, 0) -// CHECK: %[[T30:.*]] = aie.tile(8, 5) -// CHECK: %[[T41:.*]] = aie.tile(42, 0) -// CHECK: %[[T43:.*]] = aie.tile(7, 5) -// CHECK: %[[T54:.*]] = aie.tile(35, 0) -// CHECK: %[[T55:.*]] = aie.tile(10, 4) -// CHECK: %[[T66:.*]] = aie.tile(34, 0) -// CHECK: %[[T67:.*]] = aie.tile(9, 4) -// CHECK: %[[T78:.*]] = aie.tile(27, 0) -// CHECK: %[[T80:.*]] = aie.tile(8, 4) -// CHECK: %[[T91:.*]] = aie.tile(26, 0) -// CHECK: %[[T93:.*]] = aie.tile(7, 4) -// CHECK: %[[T104:.*]] = aie.tile(19, 0) -// CHECK: %[[T105:.*]] = aie.tile(10, 3) -// CHECK: %[[T116:.*]] = aie.tile(18, 0) -// CHECK: %[[T117:.*]] = aie.tile(9, 3) -// CHECK: %[[T128:.*]] = aie.tile(11, 0) -// CHECK: %[[T130:.*]] = aie.tile(8, 3) -// CHECK: %[[T140:.*]] = aie.tile(10, 0) -// CHECK: %[[T142:.*]] = aie.tile(7, 3) -// CHECK: %[[T152:.*]] = aie.tile(7, 0) -// CHECK: %[[T153:.*]] = aie.tile(10, 2) -// CHECK: %[[T164:.*]] = aie.tile(6, 0) -// CHECK: %[[T165:.*]] = aie.tile(9, 2) -// CHECK: %[[T176:.*]] = aie.tile(3, 0) -// CHECK: %[[T178:.*]] = aie.tile(8, 2) -// CHECK: %[[T189:.*]] = aie.tile(2, 0) -// CHECK: %[[T191:.*]] = aie.tile(7, 2) +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T2:.*]] = aie.tile(47, 0) +// CHECK1: %[[T4:.*]] = aie.tile(10, 5) +// CHECK1: %[[T15:.*]] = aie.tile(46, 0) +// CHECK1: %[[T17:.*]] = aie.tile(9, 5) +// CHECK1: %[[T28:.*]] = aie.tile(43, 0) +// CHECK1: %[[T30:.*]] = aie.tile(8, 5) +// CHECK1: %[[T41:.*]] = aie.tile(42, 0) +// CHECK1: %[[T43:.*]] = aie.tile(7, 5) +// CHECK1: %[[T54:.*]] = aie.tile(35, 0) +// CHECK1: %[[T55:.*]] = aie.tile(10, 4) +// CHECK1: %[[T66:.*]] = aie.tile(34, 0) +// CHECK1: %[[T67:.*]] = aie.tile(9, 4) +// CHECK1: %[[T78:.*]] = aie.tile(27, 0) +// CHECK1: %[[T80:.*]] = aie.tile(8, 4) +// CHECK1: %[[T91:.*]] = aie.tile(26, 0) +// CHECK1: %[[T93:.*]] = aie.tile(7, 4) +// CHECK1: %[[T104:.*]] = aie.tile(19, 0) +// CHECK1: %[[T105:.*]] = aie.tile(10, 3) +// CHECK1: %[[T116:.*]] = aie.tile(18, 0) +// CHECK1: %[[T117:.*]] = aie.tile(9, 3) +// CHECK1: %[[T128:.*]] = aie.tile(11, 0) +// CHECK1: %[[T130:.*]] = aie.tile(8, 3) +// CHECK1: %[[T140:.*]] = aie.tile(10, 0) +// CHECK1: %[[T142:.*]] = aie.tile(7, 3) +// CHECK1: %[[T152:.*]] = aie.tile(7, 0) +// CHECK1: %[[T153:.*]] = aie.tile(10, 2) +// CHECK1: %[[T164:.*]] = aie.tile(6, 0) +// CHECK1: %[[T165:.*]] = aie.tile(9, 2) +// CHECK1: %[[T176:.*]] = aie.tile(3, 0) +// CHECK1: %[[T178:.*]] = aie.tile(8, 2) +// CHECK1: %[[T189:.*]] = aie.tile(2, 0) +// CHECK1: %[[T191:.*]] = aie.tile(7, 2) // -// CHECK: aie.flow(%[[T2]], DMA : 0, %[[T4]], DMA : 0) -// CHECK: aie.flow(%[[T2]], DMA : 1, %[[T4]], DMA : 1) -// CHECK: aie.flow(%[[T4]], DMA : 0, %[[T104]], DMA : 1) -// CHECK: aie.flow(%[[T15]], DMA : 0, %[[T17]], DMA : 0) -// CHECK: aie.flow(%[[T15]], DMA : 1, %[[T17]], DMA : 1) -// CHECK: aie.flow(%[[T17]], DMA : 0, %[[T104]], DMA : 0) -// CHECK: aie.flow(%[[T28]], DMA : 0, %[[T30]], DMA : 0) -// CHECK: aie.flow(%[[T28]], DMA : 1, %[[T30]], DMA : 1) -// CHECK: aie.flow(%[[T30]], DMA : 0, %[[T116]], DMA : 1) -// CHECK: aie.flow(%[[T41]], DMA : 0, %[[T43]], DMA : 0) -// CHECK: aie.flow(%[[T41]], DMA : 1, %[[T43]], DMA : 1) -// CHECK: aie.flow(%[[T43]], DMA : 0, %[[T116]], DMA : 0) -// CHECK: aie.flow(%[[T54]], DMA : 0, %[[T55]], DMA : 0) -// CHECK: aie.flow(%[[T54]], DMA : 1, %[[T55]], DMA : 1) -// CHECK: aie.flow(%[[T55]], DMA : 0, %[[T128]], DMA : 1) -// CHECK: aie.flow(%[[T66]], DMA : 0, %[[T67]], DMA : 0) -// CHECK: aie.flow(%[[T66]], DMA : 1, %[[T67]], DMA : 1) -// CHECK: aie.flow(%[[T67]], DMA : 0, %[[T128]], DMA : 0) -// CHECK: aie.flow(%[[T78]], DMA : 0, %[[T80]], DMA : 0) -// CHECK: aie.flow(%[[T78]], DMA : 1, %[[T80]], DMA : 1) -// CHECK: aie.flow(%[[T80]], DMA : 0, %[[T140]], DMA : 1) -// CHECK: aie.flow(%[[T91]], DMA : 0, %[[T93]], DMA : 0) -// CHECK: aie.flow(%[[T91]], DMA : 1, %[[T93]], DMA : 1) -// CHECK: aie.flow(%[[T93]], DMA : 0, %[[T140]], DMA : 0) -// CHECK: aie.flow(%[[T104]], DMA : 0, %[[T105]], DMA : 0) -// CHECK: aie.flow(%[[T104]], DMA : 1, %[[T105]], DMA : 1) -// CHECK: aie.flow(%[[T105]], DMA : 0, %[[T152]], DMA : 1) -// CHECK: aie.flow(%[[T116]], DMA : 0, %[[T117]], DMA : 0) -// CHECK: aie.flow(%[[T116]], DMA : 1, %[[T117]], DMA : 1) -// CHECK: aie.flow(%[[T117]], DMA : 0, %[[T152]], DMA : 0) -// CHECK: aie.flow(%[[T128]], DMA : 0, %[[T130]], DMA : 0) -// CHECK: aie.flow(%[[T128]], DMA : 1, %[[T130]], DMA : 1) -// CHECK: aie.flow(%[[T130]], DMA : 0, %[[T164]], DMA : 1) -// CHECK: aie.flow(%[[T140]], DMA : 0, %[[T142]], DMA : 0) -// CHECK: aie.flow(%[[T140]], DMA : 1, %[[T142]], DMA : 1) -// CHECK: aie.flow(%[[T142]], DMA : 0, %[[T164]], DMA : 0) -// CHECK: aie.flow(%[[T152]], DMA : 0, %[[T153]], DMA : 0) -// CHECK: aie.flow(%[[T152]], DMA : 1, %[[T153]], DMA : 1) -// CHECK: aie.flow(%[[T153]], DMA : 0, %[[T176]], DMA : 1) -// CHECK: aie.flow(%[[T164]], DMA : 0, %[[T165]], DMA : 0) -// CHECK: aie.flow(%[[T164]], DMA : 1, %[[T165]], DMA : 1) -// CHECK: aie.flow(%[[T165]], DMA : 0, %[[T176]], DMA : 0) -// CHECK: aie.flow(%[[T176]], DMA : 0, %[[T178]], DMA : 0) -// CHECK: aie.flow(%[[T176]], DMA : 1, %[[T178]], DMA : 1) -// CHECK: aie.flow(%[[T178]], DMA : 0, %[[T189]], DMA : 1) -// CHECK: aie.flow(%[[T189]], DMA : 0, %[[T191]], DMA : 0) -// CHECK: aie.flow(%[[T189]], DMA : 1, %[[T191]], DMA : 1) -// CHECK: aie.flow(%[[T191]], DMA : 0, %[[T189]], DMA : 0) +// CHECK1: aie.flow(%[[T2]], DMA : 0, %[[T4]], DMA : 0) +// CHECK1: aie.flow(%[[T2]], DMA : 1, %[[T4]], DMA : 1) +// CHECK1: aie.flow(%[[T4]], DMA : 0, %[[T104]], DMA : 1) +// CHECK1: aie.flow(%[[T15]], DMA : 0, %[[T17]], DMA : 0) +// CHECK1: aie.flow(%[[T15]], DMA : 1, %[[T17]], DMA : 1) +// CHECK1: aie.flow(%[[T17]], DMA : 0, %[[T104]], DMA : 0) +// CHECK1: aie.flow(%[[T28]], DMA : 0, %[[T30]], DMA : 0) +// CHECK1: aie.flow(%[[T28]], DMA : 1, %[[T30]], DMA : 1) +// CHECK1: aie.flow(%[[T30]], DMA : 0, %[[T116]], DMA : 1) +// CHECK1: aie.flow(%[[T41]], DMA : 0, %[[T43]], DMA : 0) +// CHECK1: aie.flow(%[[T41]], DMA : 1, %[[T43]], DMA : 1) +// CHECK1: aie.flow(%[[T43]], DMA : 0, %[[T116]], DMA : 0) +// CHECK1: aie.flow(%[[T54]], DMA : 0, %[[T55]], DMA : 0) +// CHECK1: aie.flow(%[[T54]], DMA : 1, %[[T55]], DMA : 1) +// CHECK1: aie.flow(%[[T55]], DMA : 0, %[[T128]], DMA : 1) +// CHECK1: aie.flow(%[[T66]], DMA : 0, %[[T67]], DMA : 0) +// CHECK1: aie.flow(%[[T66]], DMA : 1, %[[T67]], DMA : 1) +// CHECK1: aie.flow(%[[T67]], DMA : 0, %[[T128]], DMA : 0) +// CHECK1: aie.flow(%[[T78]], DMA : 0, %[[T80]], DMA : 0) +// CHECK1: aie.flow(%[[T78]], DMA : 1, %[[T80]], DMA : 1) +// CHECK1: aie.flow(%[[T80]], DMA : 0, %[[T140]], DMA : 1) +// CHECK1: aie.flow(%[[T91]], DMA : 0, %[[T93]], DMA : 0) +// CHECK1: aie.flow(%[[T91]], DMA : 1, %[[T93]], DMA : 1) +// CHECK1: aie.flow(%[[T93]], DMA : 0, %[[T140]], DMA : 0) +// CHECK1: aie.flow(%[[T104]], DMA : 0, %[[T105]], DMA : 0) +// CHECK1: aie.flow(%[[T104]], DMA : 1, %[[T105]], DMA : 1) +// CHECK1: aie.flow(%[[T105]], DMA : 0, %[[T152]], DMA : 1) +// CHECK1: aie.flow(%[[T116]], DMA : 0, %[[T117]], DMA : 0) +// CHECK1: aie.flow(%[[T116]], DMA : 1, %[[T117]], DMA : 1) +// CHECK1: aie.flow(%[[T117]], DMA : 0, %[[T152]], DMA : 0) +// CHECK1: aie.flow(%[[T128]], DMA : 0, %[[T130]], DMA : 0) +// CHECK1: aie.flow(%[[T128]], DMA : 1, %[[T130]], DMA : 1) +// CHECK1: aie.flow(%[[T130]], DMA : 0, %[[T164]], DMA : 1) +// CHECK1: aie.flow(%[[T140]], DMA : 0, %[[T142]], DMA : 0) +// CHECK1: aie.flow(%[[T140]], DMA : 1, %[[T142]], DMA : 1) +// CHECK1: aie.flow(%[[T142]], DMA : 0, %[[T164]], DMA : 0) +// CHECK1: aie.flow(%[[T152]], DMA : 0, %[[T153]], DMA : 0) +// CHECK1: aie.flow(%[[T152]], DMA : 1, %[[T153]], DMA : 1) +// CHECK1: aie.flow(%[[T153]], DMA : 0, %[[T176]], DMA : 1) +// CHECK1: aie.flow(%[[T164]], DMA : 0, %[[T165]], DMA : 0) +// CHECK1: aie.flow(%[[T164]], DMA : 1, %[[T165]], DMA : 1) +// CHECK1: aie.flow(%[[T165]], DMA : 0, %[[T176]], DMA : 0) +// CHECK1: aie.flow(%[[T176]], DMA : 0, %[[T178]], DMA : 0) +// CHECK1: aie.flow(%[[T176]], DMA : 1, %[[T178]], DMA : 1) +// CHECK1: aie.flow(%[[T178]], DMA : 0, %[[T189]], DMA : 1) +// CHECK1: aie.flow(%[[T189]], DMA : 0, %[[T191]], DMA : 0) +// CHECK1: aie.flow(%[[T189]], DMA : 1, %[[T191]], DMA : 1) +// CHECK1: aie.flow(%[[T191]], DMA : 0, %[[T189]], DMA : 0) + +// CHECK2: "total_path_length": 792 module @vecmul_4x4 { aie.device(xcvc1902) { @@ -137,12 +142,12 @@ module @vecmul_4x4 { aie.use_lock(%9, Acquire, 1) aie.use_lock(%7, Acquire, 1) aie.use_lock(%5, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %10[%arg0] : memref<64xi32, 2> - %201 = affine.load %8[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %6[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %10[%arg0] : memref<64xi32, 2> + // %201 = affine.load %8[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %6[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%5, Release, 1) aie.use_lock(%7, Release, 0) aie.use_lock(%9, Release, 0) @@ -191,12 +196,12 @@ module @vecmul_4x4 { aie.use_lock(%22, Acquire, 1) aie.use_lock(%20, Acquire, 1) aie.use_lock(%18, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %23[%arg0] : memref<64xi32, 2> - %201 = affine.load %21[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %19[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %23[%arg0] : memref<64xi32, 2> + // %201 = affine.load %21[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %19[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%18, Release, 1) aie.use_lock(%20, Release, 0) aie.use_lock(%22, Release, 0) @@ -245,12 +250,12 @@ module @vecmul_4x4 { aie.use_lock(%35, Acquire, 1) aie.use_lock(%33, Acquire, 1) aie.use_lock(%31, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %36[%arg0] : memref<64xi32, 2> - %201 = affine.load %34[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %32[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %36[%arg0] : memref<64xi32, 2> + // %201 = affine.load %34[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %32[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%31, Release, 1) aie.use_lock(%33, Release, 0) aie.use_lock(%35, Release, 0) @@ -299,12 +304,12 @@ module @vecmul_4x4 { aie.use_lock(%48, Acquire, 1) aie.use_lock(%46, Acquire, 1) aie.use_lock(%44, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %49[%arg0] : memref<64xi32, 2> - %201 = affine.load %47[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %45[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %49[%arg0] : memref<64xi32, 2> + // %201 = affine.load %47[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %45[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%44, Release, 1) aie.use_lock(%46, Release, 0) aie.use_lock(%48, Release, 0) @@ -352,12 +357,12 @@ module @vecmul_4x4 { aie.use_lock(%60, Acquire, 1) aie.use_lock(%58, Acquire, 1) aie.use_lock(%56, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %61[%arg0] : memref<64xi32, 2> - %201 = affine.load %59[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %57[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %61[%arg0] : memref<64xi32, 2> + // %201 = affine.load %59[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %57[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%56, Release, 1) aie.use_lock(%58, Release, 0) aie.use_lock(%60, Release, 0) @@ -405,12 +410,12 @@ module @vecmul_4x4 { aie.use_lock(%72, Acquire, 1) aie.use_lock(%70, Acquire, 1) aie.use_lock(%68, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %73[%arg0] : memref<64xi32, 2> - %201 = affine.load %71[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %69[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %73[%arg0] : memref<64xi32, 2> + // %201 = affine.load %71[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %69[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%68, Release, 1) aie.use_lock(%70, Release, 0) aie.use_lock(%72, Release, 0) @@ -459,12 +464,12 @@ module @vecmul_4x4 { aie.use_lock(%85, Acquire, 1) aie.use_lock(%83, Acquire, 1) aie.use_lock(%81, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %86[%arg0] : memref<64xi32, 2> - %201 = affine.load %84[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %82[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %86[%arg0] : memref<64xi32, 2> + // %201 = affine.load %84[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %82[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%81, Release, 1) aie.use_lock(%83, Release, 0) aie.use_lock(%85, Release, 0) @@ -513,12 +518,12 @@ module @vecmul_4x4 { aie.use_lock(%98, Acquire, 1) aie.use_lock(%96, Acquire, 1) aie.use_lock(%94, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %99[%arg0] : memref<64xi32, 2> - %201 = affine.load %97[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %95[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %99[%arg0] : memref<64xi32, 2> + // %201 = affine.load %97[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %95[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%94, Release, 1) aie.use_lock(%96, Release, 0) aie.use_lock(%98, Release, 0) @@ -566,12 +571,12 @@ module @vecmul_4x4 { aie.use_lock(%110, Acquire, 1) aie.use_lock(%108, Acquire, 1) aie.use_lock(%106, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %111[%arg0] : memref<64xi32, 2> - %201 = affine.load %109[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %107[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %111[%arg0] : memref<64xi32, 2> + // %201 = affine.load %109[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %107[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%106, Release, 1) aie.use_lock(%108, Release, 0) aie.use_lock(%110, Release, 0) @@ -619,12 +624,12 @@ module @vecmul_4x4 { aie.use_lock(%122, Acquire, 1) aie.use_lock(%120, Acquire, 1) aie.use_lock(%118, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %123[%arg0] : memref<64xi32, 2> - %201 = affine.load %121[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %119[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %123[%arg0] : memref<64xi32, 2> + // %201 = affine.load %121[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %119[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%118, Release, 1) aie.use_lock(%120, Release, 0) aie.use_lock(%122, Release, 0) @@ -673,12 +678,12 @@ module @vecmul_4x4 { aie.use_lock(%135, Acquire, 1) aie.use_lock(%133, Acquire, 1) aie.use_lock(%131, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %136[%arg0] : memref<64xi32, 2> - %201 = affine.load %134[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %132[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %136[%arg0] : memref<64xi32, 2> + // %201 = affine.load %134[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %132[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%131, Release, 1) aie.use_lock(%133, Release, 0) aie.use_lock(%135, Release, 0) @@ -726,12 +731,12 @@ module @vecmul_4x4 { aie.use_lock(%147, Acquire, 1) aie.use_lock(%145, Acquire, 1) aie.use_lock(%143, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %148[%arg0] : memref<64xi32, 2> - %201 = affine.load %146[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %144[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %148[%arg0] : memref<64xi32, 2> + // %201 = affine.load %146[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %144[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%143, Release, 1) aie.use_lock(%145, Release, 0) aie.use_lock(%147, Release, 0) @@ -778,12 +783,12 @@ module @vecmul_4x4 { aie.use_lock(%158, Acquire, 1) aie.use_lock(%156, Acquire, 1) aie.use_lock(%154, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %159[%arg0] : memref<64xi32, 2> - %201 = affine.load %157[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %155[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %159[%arg0] : memref<64xi32, 2> + // %201 = affine.load %157[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %155[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%154, Release, 1) aie.use_lock(%156, Release, 0) aie.use_lock(%158, Release, 0) @@ -831,12 +836,12 @@ module @vecmul_4x4 { aie.use_lock(%170, Acquire, 1) aie.use_lock(%168, Acquire, 1) aie.use_lock(%166, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %171[%arg0] : memref<64xi32, 2> - %201 = affine.load %169[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %167[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %171[%arg0] : memref<64xi32, 2> + // %201 = affine.load %169[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %167[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%166, Release, 1) aie.use_lock(%168, Release, 0) aie.use_lock(%170, Release, 0) @@ -885,12 +890,12 @@ module @vecmul_4x4 { aie.use_lock(%183, Acquire, 1) aie.use_lock(%181, Acquire, 1) aie.use_lock(%179, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %184[%arg0] : memref<64xi32, 2> - %201 = affine.load %182[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %180[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %184[%arg0] : memref<64xi32, 2> + // %201 = affine.load %182[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %180[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%179, Release, 1) aie.use_lock(%181, Release, 0) aie.use_lock(%183, Release, 0) @@ -939,12 +944,12 @@ module @vecmul_4x4 { aie.use_lock(%196, Acquire, 1) aie.use_lock(%194, Acquire, 1) aie.use_lock(%192, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %197[%arg0] : memref<64xi32, 2> - %201 = affine.load %195[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %193[%arg0] : memref<64xi32, 2> - } + // affine.for %arg0 = 0 to 64 { + // %200 = affine.load %197[%arg0] : memref<64xi32, 2> + // %201 = affine.load %195[%arg0] : memref<64xi32, 2> + // %202 = arith.muli %200, %201 : i32 + // affine.store %202, %193[%arg0] : memref<64xi32, 2> + // } aie.use_lock(%192, Release, 1) aie.use_lock(%194, Release, 0) aie.use_lock(%196, Release, 0) diff --git a/test/create-packet-flows/aie2_memtile_connection.mlir b/test/create-packet-flows/aie2_memtile_connection.mlir index 3cc56d78d1..bdff4be067 100644 --- a/test/create-packet-flows/aie2_memtile_connection.mlir +++ b/test/create-packet-flows/aie2_memtile_connection.mlir @@ -6,37 +6,21 @@ //===----------------------------------------------------------------------===// // REQUIRES: ryzen_ai, chess -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s -//CHECK: %[[T00:.*]] = aie.tile(0, 0) -//CHECK: %[[T01:.*]] = aie.tile(0, 1) -//CHECK: %[[T02:.*]] = aie.tile(0, 2) -//CHECK: %{{.*}} = aie.switchbox(%[[T02]]) { -//CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 1, %0) -//CHECK: aie.packet_rules(DMA : 0) { -//CHECK: aie.rule(31, 0, %0) -//CHECK: } -//CHECK: } -//CHECK: %{{.*}} = aie.switchbox(%[[T00]]) { -//CHECK: aie.connect -//CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 3, %0) -//CHECK: aie.packet_rules(North : 1) { -//CHECK: aie.rule(31, 0, %0) -//CHECK: } -//CHECK: } -//CHECK: %{{.*}} = aie.shim_mux(%[[T00]]) { -//CHECK: aie.connect -//CHECK: aie.connect -//CHECK: } -//CHECK: %{{.*}} = aie.switchbox(%[[T01]]) { -//CHECK: aie.connect -//CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 1, %0) -//CHECK: aie.packet_rules(North : 1) { -//CHECK: aie.rule(31, 0, %0) -//CHECK: } -//CHECK: } +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[T00:.*]] = aie.tile(0, 0) +// CHECK1: %[[T01:.*]] = aie.tile(0, 1) +// CHECK1: %[[T02:.*]] = aie.tile(0, 2) +// CHECK1: aie.flow(%[[T01]], DMA : 0, %[[T00]], DMA : 0) +// CHECK1: aie.packet_flow(0) { +// CHECK1: aie.packet_source<%[[T02]], DMA : 0> +// CHECK1: aie.packet_dest<%[[T00]], DMA : 1> +// CHECK1: } + +// CHECK2: "total_path_length": 3 + module { aie.device(npu1_1col) { %tile_0_0 = aie.tile(0, 0) diff --git a/test/create-packet-flows/keep_packet_flow_op.mlir b/test/create-packet-flows/keep_packet_flow_op.mlir deleted file mode 100644 index f097d9e470..0000000000 --- a/test/create-packet-flows/keep_packet_flow_op.mlir +++ /dev/null @@ -1,45 +0,0 @@ -//===- keep_packet_flow_op.mlir ----------------------------------*- MLIR -*-===// -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// SPDX-License-Identifier: MIT -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-create-pathfinder-flows='keep-flow-op=true' %s | FileCheck %s - -// CHECK-LABEL: module @aie_module { -// CHECK: %[[VAL_0:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_1:.*]] = aie.shim_mux(%[[VAL_0:.*]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[VAL_2:.*]] = aie.switchbox(%[[VAL_0:.*]]) { -// CHECK: %[[VAL_3:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_4:.*]] = aie.masterset(South : 3, %[[VAL_3:.*]]) -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(31, 10, %[[VAL_3:.*]]) -// CHECK: } -// CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_5:.*]]) { -// CHECK: %[[VAL_7:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_8:.*]] = aie.masterset(South : 0, %[[VAL_6:.*]]) -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 10, %[[VAL_7:.*]]) -// CHECK: } -// CHECK: } -// CHECK: aie.packet_flow(10) { -// CHECK: aie.packet_source<%[[VAL_5:.*]], DMA : 0> -// CHECK: aie.packet_dest<%[[VAL_0:.*]], DMA : 1> -// CHECK: } - -module @aie_module { - aie.device(xcvc1902) { - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - - aie.packet_flow(0xA) { - aie.packet_source<%t71, DMA : 0> - aie.packet_dest<%t70, DMA : 1> - } - } -} diff --git a/test/create-packet-flows/packet_routing_keep_pkt_header.mlir b/test/create-packet-flows/packet_routing_keep_pkt_header.mlir index e544220133..1140913fc4 100644 --- a/test/create-packet-flows/packet_routing_keep_pkt_header.mlir +++ b/test/create-packet-flows/packet_routing_keep_pkt_header.mlir @@ -8,41 +8,24 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 -// CHECK-LABEL: module @aie_module { -// CHECK: %[[VAL_0:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0]]) { -// CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_3:.*]] = aie.masterset(DMA : 1, %[[VAL_2]]) -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(31, 1, %[[VAL_2]]) -// CHECK: } -// CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_4]]) { -// CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_7:.*]] = aie.masterset(South : 0, %[[VAL_6]]) -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 1, %[[VAL_6]]) -// CHECK: } -// CHECK: } -// CHECK: %[[VAL_8:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_9:.*]] = aie.switchbox(%[[VAL_8]]) { -// CHECK: %[[VAL_10:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_11:.*]] = aie.masterset(DMA : 1, %[[VAL_10]]) {keep_pkt_header = "true"} -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(31, 2, %[[VAL_10]]) -// CHECK: } -// CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_13:.*]] = aie.switchbox(%[[VAL_12]]) { -// CHECK: %[[VAL_14:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_15:.*]] = aie.masterset(South : 0, %[[VAL_14]]) -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 2, %[[VAL_14]]) -// CHECK: } -// CHECK: } +// CHECK1: %[[VAL_0:.*]] = aie.tile(6, 2) +// CHECK1: %[[VAL_1:.*]] = aie.tile(6, 3) +// CHECK1: %[[VAL_2:.*]] = aie.tile(7, 2) +// CHECK1: %[[VAL_3:.*]] = aie.tile(7, 3) +// CHECK1: aie.packet_flow(1) { +// CHECK1: aie.packet_source<%[[VAL_1:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 1> +// CHECK1: } +// CHECK1: aie.packet_flow(2) { +// CHECK1: aie.packet_source<%[[VAL_3:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_2:.*]], DMA : 1> +// CHECK1: } + +// CHECK2: "total_path_length": 2 // // keep_pkt_header attribute overrides the downstream decision to drop the packet header diff --git a/test/create-packet-flows/test_congestion0.mlir b/test/create-packet-flows/test_congestion0.mlir index f37fa05352..4ee081fd78 100644 --- a/test/create-packet-flows/test_congestion0.mlir +++ b/test/create-packet-flows/test_congestion0.mlir @@ -6,71 +6,38 @@ //===----------------------------------------------------------------------===// // REQUIRES: ryzen_ai, chess -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: %[[T01:.*]] = aie.tile(0, 1) -// CHECK: %{{.*}} = aie.switchbox(%[[T01]]) { -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.amsel<1> (0) -// CHECK: %2 = aie.amsel<0> (1) -// CHECK: %3 = aie.amsel<0> (2) -// CHECK: %4 = aie.amsel<0> (3) -// CHECK: %5 = aie.masterset(DMA : 0, %0) -// CHECK: %6 = aie.masterset(DMA : 1, %2) -// CHECK: %7 = aie.masterset(DMA : 2, %3) -// CHECK: %8 = aie.masterset(DMA : 3, %4) -// CHECK: %9 = aie.masterset(DMA : 4, %1) -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(31, 4, %1) -// CHECK: aie.rule(31, 3, %4) -// CHECK: aie.rule(31, 2, %3) -// CHECK: aie.rule(31, 1, %2) -// CHECK: aie.rule(31, 0, %0) -// CHECK: } -// CHECK: } -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %{{.*}} = aie.switchbox(%[[T02]]) { -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(South : 0, %0) -// CHECK: aie.packet_rules(DMA : 1) { -// CHECK: aie.rule(31, 4, %0) -// CHECK: } -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(28, 0, %0) -// CHECK: } -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 0, %0) -// CHECK: } -// CHECK: } -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %{{.*}} = aie.switchbox(%[[T03]]) { -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(South : 0, %0) -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(30, 2, %0) -// CHECK: } -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 1, %0) -// CHECK: } -// CHECK: } -// CHECK: %[[T04:.*]] = aie.tile(0, 4) -// CHECK: %{{.*}} = aie.switchbox(%[[T04]]) { -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(South : 0, %0) -// CHECK: aie.packet_rules(North : 0) { -// CHECK: aie.rule(31, 3, %0) -// CHECK: } -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 2, %0) -// CHECK: } -// CHECK: } -// CHECK: %[[T05:.*]] = aie.tile(0, 5) -// CHECK: %{{.*}} = aie.switchbox(%[[T05]]) { -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(South : 0, %0) -// CHECK: aie.packet_rules(DMA : 0) { -// CHECK: aie.rule(31, 3, %0) -// CHECK: } -// CHECK: } +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[VAL_0:.*]] = aie.tile(0, 1) +// CHECK1: %[[VAL_1:.*]] = aie.tile(0, 2) +// CHECK1: %[[VAL_2:.*]] = aie.tile(0, 3) +// CHECK1: %[[VAL_3:.*]] = aie.tile(0, 4) +// CHECK1: %[[VAL_4:.*]] = aie.tile(0, 5) +// CHECK1: aie.packet_flow(0) { +// CHECK1: aie.packet_source<%[[VAL_1:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 0> +// CHECK1: } +// CHECK1: aie.packet_flow(4) { +// CHECK1: aie.packet_source<%[[VAL_1:.*]], DMA : 1> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 4> +// CHECK1: } +// CHECK1: aie.packet_flow(1) { +// CHECK1: aie.packet_source<%[[VAL_2:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 1> +// CHECK1: } +// CHECK1: aie.packet_flow(2) { +// CHECK1: aie.packet_source<%[[VAL_3:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 2> +// CHECK1: } +// CHECK1: aie.packet_flow(3) { +// CHECK1: aie.packet_source<%[[VAL_4:.*]], DMA : 0> +// CHECK1: aie.packet_dest<%[[VAL_0:.*]], DMA : 3> +// CHECK1: } + +// CHECK2: "total_path_length": 8 + module { aie.device(npu1_1col) { %tile_0_1 = aie.tile(0, 1) diff --git a/test/create-packet-flows/test_congestion1.mlir b/test/create-packet-flows/test_congestion1.mlir index adef666a24..75cdd91aa6 100644 --- a/test/create-packet-flows/test_congestion1.mlir +++ b/test/create-packet-flows/test_congestion1.mlir @@ -6,59 +6,29 @@ //===----------------------------------------------------------------------===// // REQUIRES: ryzen_ai, chess -// RUN: aie-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: %[[T00:.*]] = aie.tile(0, 0) -// CHECK: %[[T01:.*]] = aie.tile(0, 1) -// CHECK: %[[T02:.*]] = aie.tile(0, 2) -// CHECK: %[[T03:.*]] = aie.tile(0, 3) -// CHECK: %[[T04:.*]] = aie.tile(0, 4) -// CHECK: %[[T05:.*]] = aie.tile(0, 5) -// CHECK: %{{.*}} = aie.switchbox(%[[T01]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(DMA : 4, %0) -// CHECK: aie.packet_rules(South : 0) { -// CHECK: aie.rule(31, 0, %0) -// CHECK: } -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T02]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T03]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T04]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T05]]) { -// CHECK: aie.connect -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(East : 0, %0) -// CHECK: aie.packet_rules(DMA : 1) { -// CHECK: aie.rule(31, 0, %0) -// CHECK: } -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T00]]) { -// CHECK: aie.connect -// CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(North : 0, %0) -// CHECK: aie.packet_rules(East : 0) { -// CHECK: aie.rule(31, 0, %0) -// CHECK: } -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T00]]) { -// CHECK: aie.connect -// CHECK: } +// RUN: aie-opt --aie-create-pathfinder-flows --aie-find-flows %s -o %t.opt +// RUN: FileCheck %s --check-prefix=CHECK1 < %t.opt +// RUN: aie-translate --aie-flows-to-json %t.opt | FileCheck %s --check-prefix=CHECK2 + +// CHECK1: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK1: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK1: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK1: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK1: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK1: %[[TILE_0_5:.*]] = aie.tile(0, 5) +// CHECK1: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK1: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_0]], DMA : 0) +// CHECK1: aie.flow(%[[TILE_0_2]], DMA : 0, %[[TILE_0_1]], DMA : 0) +// CHECK1: aie.flow(%[[TILE_0_3]], DMA : 0, %[[TILE_0_1]], DMA : 1) +// CHECK1: aie.flow(%[[TILE_0_4]], DMA : 0, %[[TILE_0_1]], DMA : 2) +// CHECK1: aie.flow(%[[TILE_0_5]], DMA : 0, %[[TILE_0_1]], DMA : 3) +// CHECK1: aie.packet_flow(0) { +// CHECK1: aie.packet_source<%[[TILE_0_5]], DMA : 1> +// CHECK1: aie.packet_dest<%[[TILE_0_1]], DMA : 4> +// CHECK1: } + +// CHECK2: "total_path_length": 23 + module { aie.device(npu1_2col) { %tile_0_0 = aie.tile(0, 0) diff --git a/utils/router_performance.py b/utils/router_performance.py new file mode 100644 index 0000000000..0cfa96e69e --- /dev/null +++ b/utils/router_performance.py @@ -0,0 +1,104 @@ +import argparse +import csv +import os +import re +import subprocess +import time + +# Parse arguments +parser = argparse.ArgumentParser() +parser.add_argument("test_dir", type=str, help="Directory containing routing tests") +args = parser.parse_args() + + +# Regular expression pattern to match the end iteration message +pattern = re.compile( + r"---End findPaths iteration #(\d+) , illegal edges count = (\d+), total path length = (\d+)---" +) +results = {} +# Iterate over all files in the given directory +files = sorted(os.listdir(args.test_dir)) +for file in files: + filepath = os.path.join(args.test_dir, file) + if os.path.isfile(filepath) and file.endswith(".mlir"): + # without the extension + test = file.split(".")[0] + with open(filepath, "r") as f: + lines = f.readlines() + for line in lines: + if line.startswith("// RUN: aie-opt"): + # Extract the command after // RUN: + command = line[len("// RUN:") :].strip() + # Replace %s with the file path + command = command.replace("%s", filepath) + # Split the command by pipe to insert --debug appropriately + parts = command.split("|") + parts[0] = parts[0].strip() + " --debug" + debug_command = parts[0] + + # Execute the command + print(f"Executing command: {debug_command}") + start_time = time.time() + try: + result = subprocess.run( + debug_command, + shell=True, + check=True, + capture_output=True, + text=True, + timeout=1200, + ) + status = "SUCCESS" + except subprocess.CalledProcessError as e: + result = e + status = "FAILED" + except subprocess.TimeoutExpired as e: + result = e + status = "FAILED" + end_time = time.time() + + iteration_count = illegal_edges_count = total_path_length = -1 + if result.stderr and status != "FAILED": + matches = list(pattern.finditer(result.stderr)) + if matches: + # Get the last match + last_match = matches[-1] + iteration_count = last_match.group(1) + illegal_edges_count = last_match.group(2) + total_path_length = last_match.group(3) + + results[test] = { + "iteration_count": iteration_count, + "illegal_edges_count": illegal_edges_count, + "total_path_length": total_path_length, + "status": status, + "execution_time": end_time - start_time, + } +print(results) +# Write the results to a CSV file +csv_file = os.path.join(args.test_dir, "routing_performance_results.csv") +with open(csv_file, mode="w", newline="") as file: + writer = csv.writer(file) + writer.writerow( + [ + "Test", + "Iterations Count", + "Illegal Edges Count", + "Total Path Length", + "Status", + "Execution Time", + ] + ) + for test, data in results.items(): + writer.writerow( + [ + test, + data["iteration_count"], + data["illegal_edges_count"], + data["total_path_length"], + data["status"], + data["execution_time"], + ] + ) + +print(f"Results have been written to {csv_file}")