A simple binary operator, which uses a single AIE core to get the modulo of two vectors. The overall vector size in this design is 256 and it processed by the core in smaller sub tiles of size 16. It shows how simple it can be to just feed data into the AIEs using the Object FIFO abstraction, and drain the results back to external memory. This reference design can be run on either a Ryzen™ AI NPU or a VCK5000.
The kernel executes on AIE tile (col, 2). Both input vectors are brought into the tile from Shim tile (col, 0). The value of col is dependent on whether the application is targeting NPU or VCK5000. The AIE tile performs the summation operations and the Shim tile brings the data back out to external memory.
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aie2.py: defines the AIE array structural design using IRON AIE language bindings. This generates mlir-aie that is then compiled usingaiecc.pyto produce design binaries (ie. XCLBIN and inst.txt for the NPU in Ryzen™ AI). -
test.cpp: This C++ code is a testbench for the design example targeting Ryzen™ AI (AIE-ML). The code is responsible for loading the compiled XCLBIN file, configuring the AIE module, providing input data, and executing the AIE design on the NPU. After executing, the program verifies the results. -
test_vck5000.cpp: This C++ code is a testbench for the design example targeting the VCK5000 PCIe card (AIE). The code is responsible for configuring the AIEs, allocating memory, providing input data, and executing the AIE design on the VCK5000. After executing, the program verifies the results.
To compile the design and C++ testbench:
make
make vectorModulo.exe
To run the design:
make run
To compile the design and C++ testbench:
make vck5000
To run the design:
./test.elf