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INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/metrics.csv'.
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/signoff/21-rcx_sta.checks.rpt'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/signoff/21-rcx_sta.checks.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
[INFO]: Note that the following warnings have been generated:
[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta
[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta
[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta
[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta
[WARNING]: VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate.
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/signoff/21-rcx_sta.checks.rpt'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/signoff/21-rcx_sta.checks.rpt'.
make[1]: Leaving directory '/home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane'
The text was updated successfully, but these errors were encountered:
Description
Providing a nonexistent clock (should be wb_clk) in user_project_wrapper:
The flow finishes with no errors and the wb_clk_i pin is unconnected.
Expected Behavior
Flow should fail if a net is nonexistent.
Flow should fail STA if user clock is missing
Environment report
Reproduction material
to rebuild you need this repo cloned in verilog/rtl/ https://github.com/mattvenn/wishbone_buttons_leds
caravel_user_project : https://github.com/mattvenn/caravel_user_project_mpw9e/tree/interview_working
Relevant log output
The text was updated successfully, but these errors were encountered: