Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Using Openlane for symmetric routing #2031

Open
jchin2 opened this issue Oct 30, 2023 · 1 comment
Open

Using Openlane for symmetric routing #2031

jchin2 opened this issue Oct 30, 2023 · 1 comment
Labels
enhancement New feature or request

Comments

@jchin2
Copy link

jchin2 commented Oct 30, 2023

Hi all,
I am laying out a circuit for security based application and they are dependent on balanced parasitic capacitance in its routing. The criteria is all the routing from within the custom standard cells, inter cell connections, to macro-macro routing has to be symmetrical. Motivation is to get balanced parasitic capacitance between them. This circuit uses 4 trapezoidal power clocks at 90 degree phase shift and the sequence follows CLK0 to CLK3. The following images below show the current layout outline, 4-bit width layout, and new layout outline plan for symmetric routing. I recognize I will need to reroute the basic custom cells to realize the new plan, just to make sure they are matched on the lowest hierarchy. The question is does Openlane have some sort of function to facilitate balanced inter-cell or inter-macro routing?
Current 4-bit width layout outline.
image
4-bit width Layout sub-block without considering its parasitic capacitance balance.
image
New logic cell placement plan in vertical pipeline
image

@jchin2
Copy link
Author

jchin2 commented Nov 2, 2023

@kareefardi Please kindly find the design files in the attachment.
Design_files_11012023.zip

@donn donn added the enhancement New feature or request label Sep 12, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request
Projects
None yet
Development

No branches or pull requests

2 participants