Dragonphy ports should all be at top level for proper black boxing.

[steveri]

In general, our CI servers are not powerful enough to do a full chip build with flat hierarchy, so it's useful to be able to black-box the various subcomponents. For successful blackboxing, any port that connects to the outside world should exist at the top level of the design. Unfortunately, dragonphy2 as currently built does not meet that criteria. But it's very easy to fix!

Image 1 below shows metal layer nine of the dragonphy_top cell. Circled in yellow are some of the AVDD/AVSS ports, highlighted in white, and enlarged in image 2 for better detail. Unfortunately, these ports only exist in layer 1 of dragonphy_top, and they do not appear in the top level layer 0.

When we black-box the dragonphy for LVS, only the top level ports are visible, so the wires that connect to these layer 1 ports are seen as floating and that causes errors, i.e. LVS cannot identify the floating net as part of AVSS. To fix this, I hand edited the tape and copied the ports from layer 1 up to the top layer (see image 3---note you have to copy both the text e.g. "AVSS" and the accompanying little M9 square that forms the port itself).

For now, we are using the hand edited version, but it would be nice to have an "official" dragonphy2.gds that has the ports lifted (lowered?) to layer 0.

FYI the hacked dragonphy can be seen here, on host "r7arm-aha":
/sim/steveri/dragonphy/Dec_2020/dragonphy_top.gds
If you look at it you'll see I only lifted a few of the ports to layer 0, out of laziness mostly. One lifted port is sufficient for LVS to establish the named connection for the entire net, but for completeness, it seems like they should all be the same...

[steveri]

Note latest successful run using the blackboxed/hacked/LVS-CORRECT dragonphy2 can be seen here:
https://buildkite.com/tapeout-aha/fullchip/builds/203