diff --git a/LICENSE b/LICENSE index 20ab941..23cb790 100644 --- a/LICENSE +++ b/LICENSE @@ -1,21 +1,339 @@ -MIT License - -Copyright (c) 2021 SiccoDwars - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + {signature of Ty Coon}, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/README.md b/README.md index 6d2f9da..29b32b3 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,96 @@ -# Icestudio-ArithmeticBlocks -.ice blocks for FPGA signed and unsigned integer operations + - * / sqrt min max abs neg. 16, 24 and some 32 bits blocks -A collection of Icestudio blocks for signed integer digital signal processing and control applications. + +# arithmetic Collection + +[![Icestudio][icestudio-image]][icestudio-url] +![Version][version-image] + + +Signed arithmetic collections + + +## License + +Licensed under [LGPL-3.0](https://opensource.org/licenses/LGPL-3.0). + +## Install + +For installing and using this colection in Icestudio follow these steps: + +* Download the collection: [stable](https://github.com/SiccoDwars/Icestudio-ArithmeticBlocks/archive/refs/tags/v0.1.0.zip) or [development](https://github.com/SiccoDwars/Icestudio-ArithmeticBlocks/archive/refs/heads/main.zip) +* Install the collection: *Tools > Collections > Add* +* Select the collection: *Select > Collection* + + +## Blocks +* **int_math_sd** + * **int16** + * abs_int16 + * add_int16_sat + * compare_int16 + * div_int16 + * div_int16_clocked + * max_int16 + * min_int16 + * mul_int16 + * mul_int16_32 + * mul_int16_sat + * muldiv_int16_sat + * muldiv_int16_sat_clocked + * neg_int16 + * nop_int16 + * nop_int16_clocked + * select_int16 + * sub_int16_sat + * **int24** + * abs_int24 + * add_int24_sat + * compare_int24 + * div_int24 + * max_int24 + * min_int24 + * mul_int24_48 + * muldiv_int16_sat + * muldiv_int24 + * neg_int24 + * nop_int24 + * nop_int24_clocked + * select_int24 + * sub_int24_sat + * **int32** + * add_int32_sat + * div_int32 + * div_int32_16 + * sub_int32_sat + * **int48** + * div_int48_24 + * **int8** + * mul_int8_16 + * **uint16** + * div_uint16 + * sqrt_uint16 + * **uint24** + * div_uint24 + * sqrt_uint24 + * **uint32** + * div_uint32 + * sqrt_uint32 +* **utils** + * timer_16bits + +## Examples +* test_serial_muldiv_int16 +* test_serial_sqrt_uint16 + +## Authors +* [SiccoDwars](https://github.com/SiccoDwars) + + + +------- + + + +[icestudio-image]: https://img.shields.io/badge/collection-icestudio-blue.svg +[icestudio-url]: https://github.com/FPGAwars/icestudio +[version-image]: https://img.shields.io/badge/version-v0.1.0-orange.svg diff --git a/abs_int16.ice b/blocks/int_math_sd/int16/abs_int16.ice similarity index 100% rename from abs_int16.ice rename to blocks/int_math_sd/int16/abs_int16.ice diff --git a/add_int16_sat.ice b/blocks/int_math_sd/int16/add_int16_sat.ice similarity index 100% rename from add_int16_sat.ice rename to blocks/int_math_sd/int16/add_int16_sat.ice diff --git a/compare_int16.ice b/blocks/int_math_sd/int16/compare_int16.ice similarity index 100% rename from compare_int16.ice rename to blocks/int_math_sd/int16/compare_int16.ice diff --git a/div_int16.ice b/blocks/int_math_sd/int16/div_int16.ice similarity index 100% rename from div_int16.ice rename to blocks/int_math_sd/int16/div_int16.ice diff --git a/div_int16_clocked.ice b/blocks/int_math_sd/int16/div_int16_clocked.ice similarity index 100% rename from div_int16_clocked.ice rename to blocks/int_math_sd/int16/div_int16_clocked.ice diff --git a/max_int16.ice b/blocks/int_math_sd/int16/max_int16.ice similarity index 100% rename from max_int16.ice rename to blocks/int_math_sd/int16/max_int16.ice diff --git a/min_int16.ice b/blocks/int_math_sd/int16/min_int16.ice similarity index 100% rename from min_int16.ice rename to blocks/int_math_sd/int16/min_int16.ice diff --git a/mul_int16.ice b/blocks/int_math_sd/int16/mul_int16.ice similarity index 100% rename from mul_int16.ice rename to blocks/int_math_sd/int16/mul_int16.ice diff --git a/mul_int16_32.ice b/blocks/int_math_sd/int16/mul_int16_32.ice similarity index 100% rename from mul_int16_32.ice rename to blocks/int_math_sd/int16/mul_int16_32.ice diff --git a/mul_int16_sat.ice b/blocks/int_math_sd/int16/mul_int16_sat.ice similarity index 100% rename from mul_int16_sat.ice rename to blocks/int_math_sd/int16/mul_int16_sat.ice diff --git a/muldiv_int16_sat.ice b/blocks/int_math_sd/int16/muldiv_int16_sat.ice similarity index 100% rename from muldiv_int16_sat.ice rename to blocks/int_math_sd/int16/muldiv_int16_sat.ice diff --git a/muldiv_int16_sat_clocked.ice b/blocks/int_math_sd/int16/muldiv_int16_sat_clocked.ice similarity index 100% rename from muldiv_int16_sat_clocked.ice rename to blocks/int_math_sd/int16/muldiv_int16_sat_clocked.ice diff --git a/neg_int16.ice b/blocks/int_math_sd/int16/neg_int16.ice similarity index 100% rename from neg_int16.ice rename to blocks/int_math_sd/int16/neg_int16.ice diff --git a/nop_int16.ice b/blocks/int_math_sd/int16/nop_int16.ice similarity index 100% rename from nop_int16.ice rename to blocks/int_math_sd/int16/nop_int16.ice diff --git a/nop_int16_clocked.ice b/blocks/int_math_sd/int16/nop_int16_clocked.ice similarity index 100% rename from nop_int16_clocked.ice rename to blocks/int_math_sd/int16/nop_int16_clocked.ice diff --git a/select_int16.ice b/blocks/int_math_sd/int16/select_int16.ice similarity index 100% rename from select_int16.ice rename to blocks/int_math_sd/int16/select_int16.ice diff --git a/sub_int16_sat.ice b/blocks/int_math_sd/int16/sub_int16_sat.ice similarity index 100% rename from sub_int16_sat.ice rename to blocks/int_math_sd/int16/sub_int16_sat.ice diff --git a/abs_int24.ice b/blocks/int_math_sd/int24/abs_int24.ice similarity index 100% rename from abs_int24.ice rename to blocks/int_math_sd/int24/abs_int24.ice diff --git a/add_int24_sat.ice b/blocks/int_math_sd/int24/add_int24_sat.ice similarity index 100% rename from add_int24_sat.ice rename to blocks/int_math_sd/int24/add_int24_sat.ice diff --git a/compare_int24.ice b/blocks/int_math_sd/int24/compare_int24.ice similarity index 100% rename from compare_int24.ice rename to blocks/int_math_sd/int24/compare_int24.ice diff --git a/div_int24.ice b/blocks/int_math_sd/int24/div_int24.ice similarity index 100% rename from div_int24.ice rename to blocks/int_math_sd/int24/div_int24.ice diff --git a/max_int24.ice b/blocks/int_math_sd/int24/max_int24.ice similarity index 100% rename from max_int24.ice rename to blocks/int_math_sd/int24/max_int24.ice diff --git a/min_int24.ice b/blocks/int_math_sd/int24/min_int24.ice similarity index 100% rename from min_int24.ice rename to blocks/int_math_sd/int24/min_int24.ice diff --git a/mul_int24_48.ice b/blocks/int_math_sd/int24/mul_int24_48.ice similarity index 100% rename from mul_int24_48.ice rename to blocks/int_math_sd/int24/mul_int24_48.ice diff --git a/blocks/int_math_sd/int24/muldiv_int16_sat.ice b/blocks/int_math_sd/int24/muldiv_int16_sat.ice new file mode 100644 index 0000000..87aee9c --- /dev/null +++ b/blocks/int_math_sd/int24/muldiv_int16_sat.ice @@ -0,0 +1,553 @@ +{ + "version": "1.2", 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"value": "" + }, + { + "index": "0", + "name": "", + "value": "" + } + ], + "virtual": true + }, + "position": { + "x": 784, + "y": -24 + } + }, + { + "id": "4d45fe21-e51e-4794-8198-1a724fcfcfe4", + "type": "basic.input", + "data": { + "name": "a", + "range": "[15:0]", + "pins": [ + { + "index": "15", + "name": "", + "value": "" + }, + { + "index": "14", + "name": "", + "value": "" + }, + { + "index": "13", + "name": "", + "value": "" + }, + { + "index": "12", + "name": "", + "value": "" + }, + { + "index": "11", + "name": "", + "value": "" + }, + { + "index": "10", + "name": "", + "value": "" + }, + { + "index": "9", + "name": "", + "value": "" + }, + { + "index": "8", + "name": "", + "value": "" + }, + { + "index": "7", + "name": "", + "value": "" + }, + { + "index": "6", + "name": "", + "value": "" + }, + { + "index": "5", + "name": "", + "value": "" + }, + { + "index": "4", + "name": "", + "value": "" + }, + { + "index": "3", + "name": "", + "value": "" + }, + { + "index": "2", + "name": "", + "value": "" + }, + { + "index": "1", + "name": "", + "value": "" + }, + { + "index": "0", + "name": "", + "value": "" + } + ], + "virtual": true, + "clock": false + }, + "position": { + "x": -8, + "y": -24 + } + }, + { + "id": "7376e6a0-ed86-48b1-b06f-59cfe1915a37", + "type": "basic.output", + "data": { + "name": "clipMaxInt", + "pins": [ + { + "index": "0", + "name": "NULL", + "value": "NULL" + } + ], + "virtual": true + }, + "position": { + "x": 792, + "y": 80 + } + }, + { + "id": "62db479e-f47e-4d03-9093-d3610ae08709", + "type": "basic.input", + "data": { + "name": "mul", + "range": "[15:0]", + "pins": [ + { + "index": "15", + "name": "", + "value": "" + }, + { + "index": "14", + "name": "", + "value": "" + }, + { + "index": "13", + "name": "", + "value": "" + }, + { + "index": "12", + "name": "", + "value": "" + }, + { + "index": "11", + "name": "", + "value": "" + }, + { + "index": "10", + "name": "", + "value": "" + }, + { + "index": "9", + "name": "", + "value": "" + }, + { + "index": "8", + "name": "", + "value": "" + }, + { + "index": "7", + "name": "", + "value": "" + }, + { + "index": "6", + "name": "", + "value": "" + }, + { + "index": "5", + "name": "", + "value": "" + }, + { + "index": "4", + "name": "", + "value": "" + }, + { + "index": "3", + "name": "", + "value": "" + }, + { + "index": "2", + "name": "", + "value": "" + }, + { + "index": "1", + "name": "", + "value": "" + }, + { + "index": "0", + "name": "", + "value": "" + } + ], + "virtual": true, + "clock": false + }, + "position": { + "x": 0, + "y": 80 + } + }, + { + "id": "5aad4260-c2e8-44ca-a726-52122bc47a1e", + "type": "basic.output", + "data": { + "name": "clipMinInt", + "pins": [ + { + "index": "0", + "name": "NULL", + "value": "NULL" + } + ], + "virtual": true + }, + "position": { + "x": 792, + "y": 176 + } + }, + { + "id": "261ad5a4-3233-4df3-a493-9fa7894c09c4", + "type": "basic.input", + "data": { + "name": "div", + "range": "[15:0]", + "pins": [ + { + "index": "15", + "name": "", + "value": "" + }, + { + "index": "14", + "name": "", + "value": "" + }, + { + "index": "13", + "name": "", + "value": "" + }, + { + "index": "12", + "name": "", + "value": "" + }, + { + "index": "11", + "name": "", + "value": "" + }, + { + "index": "10", + "name": "", + "value": "" + }, + { + "index": "9", + "name": "", + "value": "" + }, + { + "index": "8", + "name": "", + "value": "" + }, + { + "index": "7", + "name": "", + "value": "" + }, + { + "index": "6", + "name": "", + "value": "" + }, + { + "index": "5", + "name": "", + "value": "" + }, + { + "index": "4", + "name": "", + "value": "" + }, + { + "index": "3", + "name": "", + "value": "" + }, + { + "index": "2", + "name": "", + "value": "" + }, + { + "index": "1", + "name": "", + "value": "" + }, + { + "index": "0", + "name": "", + "value": "" + } + ], + "virtual": true, + "clock": false + }, + "position": { + "x": 0, + "y": 176 + } + }, + { + "id": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "type": "basic.code", + "data": { + "code": "// y = (a * mul) / div; signed 16 bits integers, coerce product y in [-32768..32767 range]\n\nwire signed [31:0] product32bits;\nwire signed [31:0] div32bits;\n\nassign product32bits = $signed(a) * $signed(mul);\nassign div32bits = product32bits / $signed(div);\nassign clipMinInt = (div32bits < -32768);\nassign clipMaxInt = (div32bits > 32767);\n\nassign y = (a==0) ? 0 : clipMinInt ? -32768 : clipMaxInt ? 32767 : div32bits[15:0];\n", + "params": [], + "ports": { + "in": [ + { + "name": "a", + "range": "[15:0]", + "size": 16 + }, + { + "name": "mul", + "range": "[15:0]", + "size": 16 + }, + { + "name": "div", + "range": "[15:0]", + "size": 16 + } + ], + "out": [ + { + "name": "y", + "range": "[15:0]", + "size": 16 + }, + { + "name": "clipMaxInt" + }, + { + "name": "clipMinInt" + } + ] + } + }, + "position": { + "x": 224, + "y": -40 + }, + "size": { + "width": 472, + "height": 296 + } + } + ], + "wires": [ + { + "source": { + "block": "4d45fe21-e51e-4794-8198-1a724fcfcfe4", + "port": "out" + }, + "target": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "a" + }, + "size": 16 + }, + { + "source": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "clipMaxInt" + }, + "target": { + "block": "7376e6a0-ed86-48b1-b06f-59cfe1915a37", + "port": "in" + } + }, + { + "source": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "clipMinInt" + }, + "target": { + "block": "5aad4260-c2e8-44ca-a726-52122bc47a1e", + "port": "in" + } + }, + { + "source": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "y" + }, + "target": { + "block": "a947797a-75f6-419b-8ebc-98ee46ff3307", + "port": "in" + }, + "size": 16 + }, + { + "source": { + "block": "62db479e-f47e-4d03-9093-d3610ae08709", + "port": "out" + }, + "target": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "mul" + }, + "size": 16 + }, + { + "source": { + "block": "261ad5a4-3233-4df3-a493-9fa7894c09c4", + "port": "out" + }, + "target": { + "block": "1305a83f-5378-4d61-a0ab-8ad1e8b196d4", + "port": "div" + }, + "size": 16 + } + ] + } + }, + "dependencies": {} +} \ No newline at end of file diff --git a/muldiv_int24.ice b/blocks/int_math_sd/int24/muldiv_int24.ice similarity index 100% rename from muldiv_int24.ice rename to blocks/int_math_sd/int24/muldiv_int24.ice diff --git a/neg_int24.ice b/blocks/int_math_sd/int24/neg_int24.ice similarity index 100% rename from neg_int24.ice rename to blocks/int_math_sd/int24/neg_int24.ice diff --git a/nop_int24.ice b/blocks/int_math_sd/int24/nop_int24.ice similarity index 100% rename from nop_int24.ice rename to blocks/int_math_sd/int24/nop_int24.ice diff --git a/nop_int24_clocked.ice b/blocks/int_math_sd/int24/nop_int24_clocked.ice similarity index 100% rename from nop_int24_clocked.ice rename to blocks/int_math_sd/int24/nop_int24_clocked.ice diff --git a/select_int24.ice b/blocks/int_math_sd/int24/select_int24.ice similarity index 100% rename from select_int24.ice rename to blocks/int_math_sd/int24/select_int24.ice diff --git a/sub_int24_sat.ice b/blocks/int_math_sd/int24/sub_int24_sat.ice similarity index 100% rename from sub_int24_sat.ice rename to blocks/int_math_sd/int24/sub_int24_sat.ice diff --git a/add_int32_sat.ice b/blocks/int_math_sd/int32/add_int32_sat.ice similarity index 100% rename from add_int32_sat.ice rename to blocks/int_math_sd/int32/add_int32_sat.ice diff --git a/div_int32.ice b/blocks/int_math_sd/int32/div_int32.ice similarity index 100% rename from div_int32.ice rename to blocks/int_math_sd/int32/div_int32.ice diff --git a/div_int32_16.ice b/blocks/int_math_sd/int32/div_int32_16.ice similarity index 100% rename from div_int32_16.ice rename to blocks/int_math_sd/int32/div_int32_16.ice diff --git a/sub_int32_sat.ice b/blocks/int_math_sd/int32/sub_int32_sat.ice similarity index 100% rename from sub_int32_sat.ice rename to blocks/int_math_sd/int32/sub_int32_sat.ice diff --git a/div_int48_24.ice b/blocks/int_math_sd/int48/div_int48_24.ice similarity index 100% rename from div_int48_24.ice rename to blocks/int_math_sd/int48/div_int48_24.ice diff --git a/mul_int8_16.ice b/blocks/int_math_sd/int8/mul_int8_16.ice similarity index 100% rename from mul_int8_16.ice rename to blocks/int_math_sd/int8/mul_int8_16.ice diff --git a/div_uint16.ice b/blocks/int_math_sd/uint16/div_uint16.ice similarity index 100% rename from div_uint16.ice rename to blocks/int_math_sd/uint16/div_uint16.ice diff --git a/sqrt_uint16.ice b/blocks/int_math_sd/uint16/sqrt_uint16.ice similarity index 100% rename from sqrt_uint16.ice rename to blocks/int_math_sd/uint16/sqrt_uint16.ice diff --git a/div_uint24.ice b/blocks/int_math_sd/uint24/div_uint24.ice similarity index 100% rename from div_uint24.ice rename to blocks/int_math_sd/uint24/div_uint24.ice diff --git a/sqrt_uint24.ice b/blocks/int_math_sd/uint24/sqrt_uint24.ice similarity index 100% rename from sqrt_uint24.ice rename to blocks/int_math_sd/uint24/sqrt_uint24.ice diff --git a/div_uint32.ice b/blocks/int_math_sd/uint32/div_uint32.ice similarity index 100% rename from div_uint32.ice rename to blocks/int_math_sd/uint32/div_uint32.ice diff --git a/sqrt_uint32.ice b/blocks/int_math_sd/uint32/sqrt_uint32.ice similarity index 100% rename from sqrt_uint32.ice rename to blocks/int_math_sd/uint32/sqrt_uint32.ice diff --git a/timer_16bits.ice b/blocks/utils/timer_16bits.ice similarity index 100% rename from timer_16bits.ice rename to blocks/utils/timer_16bits.ice diff --git a/test_serial_muldiv_int16.ice b/examples/test_serial_muldiv_int16.ice similarity index 100% rename from test_serial_muldiv_int16.ice rename to examples/test_serial_muldiv_int16.ice diff --git a/test_serial_sqrt_uint16.ice b/examples/test_serial_sqrt_uint16.ice similarity index 100% rename from test_serial_sqrt_uint16.ice rename to examples/test_serial_sqrt_uint16.ice diff --git a/int_math_Collection_sd.zip b/int_math_Collection_sd.zip deleted file mode 100644 index 16d257f..0000000 Binary files a/int_math_Collection_sd.zip and /dev/null differ diff --git a/locale/en/en.po b/locale/en/en.po new file mode 100644 index 0000000..d35b87d --- /dev/null +++ b/locale/en/en.po @@ -0,0 +1,9 @@ +msgid "" +msgstr "" +"Language: en\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Poedit-Basepath: ..\n" +"Plural-Forms: nplurals=2; plural=(n != 1);\n" +"X-Poedit-SearchPath-0: translation.js\n" diff --git a/locale/translation.js b/locale/translation.js new file mode 100644 index 0000000..ce7e23a --- /dev/null +++ b/locale/translation.js @@ -0,0 +1,162 @@ +// Translation document for the collection +// ======================================= +// This file contains the texts +// annotated for translation +// +// Instructions: +// 1. Open the PO file with Poedit +// 2. Press "Update" to update from sources + +gettext('int_math_sd'); +gettext('utils'); +gettext('int16'); +gettext('int24'); +gettext('int32'); +gettext('int48'); +gettext('int8'); +gettext('uint16'); +gettext('uint24'); +gettext('uint32'); +gettext('abs_int16'); +gettext('16 bits signed integer absolute value ( y = abs (a) ) '); +gettext('add_int16_sat'); +gettext('16 bits signed integer add with minint,maxint saturation'); +gettext('compare_int16'); +gettext('16 bits signed integer value comparator'); +gettext('div_int16'); +gettext('16 bits signed integer divider'); +gettext('div_int16_clocked'); +gettext('16 bits signed integer division, y = a * 16384 / b'); +gettext('max_int16'); +gettext('16 bits signed integer maximum value selector'); +gettext('min_int16'); +gettext('16 bits signed integer minimum value selector'); +gettext('mul_int16'); +gettext('mul_int16_32'); +gettext('16 bit inputs signed integer multiplier, 32 bits output'); +gettext('mul_int16_sat'); +gettext('16 bits signed integer multiplication with minint,maxint saturation, 100%=16384'); +gettext('muldiv_int16_sat'); +gettext('16 bits signed integer multiplication and division with minint,maxint saturation, 100%=16384'); +gettext('muldiv_int16_sat_clocked'); +gettext('clocked 16 bits signed integer multiplication and division with minint,maxint saturation'); +gettext('neg_int16'); +gettext('16 bits signed integer negation ( y = -a ) '); +gettext('nop_int16'); +gettext('16 bits signed integer no operation (y=a)'); +gettext('nop_int16_clocked'); +gettext('pos and neg edge d-flipflip, 16 bits'); +gettext('select_int16'); +gettext('16 bits signed integer value selector (switch, mux)'); +gettext('sub_int16_sat'); +gettext('16 bits signed integer subtract with minint,maxint saturation'); +gettext('abs_int24'); +gettext('24 bits signed integer absolute value ( y = abs (a) ) '); +gettext('add_int24_sat'); +gettext('24 bits signed integer add with minint,maxint saturation'); +gettext('compare_int24'); +gettext('24 bits signed integer value comparator'); +gettext('div_int24'); +gettext('24 bits signed integer divider'); +gettext('max_int24'); +gettext('24 bits signed integer maximum value selector'); +gettext('min_int24'); +gettext('24 bits signed integer minimum value selector'); +gettext('mul_int24_48'); +gettext('24 bit inputs signed integer multiplier, 48 bits output'); +gettext('muldiv_int16_sat'); +gettext('muldiv_int24'); +gettext('24 bits signed integer multiply divide with output saturation, 48 bits internal'); +gettext('Puerta OR'); +gettext('48 bits signed integer division, divide 48 bits numerator by a 24 bits int denominator, result in 24 bits int'); +gettext('neg_int24'); +gettext('24 bits signed integer negation ( y = -a ) '); +gettext('nop_int24'); +gettext('24 bits signed integer no operation (y=a)'); +gettext('nop_int24_clocked'); +gettext('pos and neg edge d-flipflip, 24 bits'); +gettext('select_int24'); +gettext('24 bits signed integer value selector (switch, mux)'); +gettext('sub_int24_sat'); +gettext('24 bits signed integer subtract with minint,maxint saturation'); +gettext('add_int32_sat'); +gettext('32 bits signed integer add with minint,maxint saturation'); +gettext('div_int32'); +gettext('32 bits signed integer divider'); +gettext('div_int32_16'); +gettext('32 bits signed integer division, divide 32 bits numerator by a 16 bits int denominator, result in 16 bits int'); +gettext('sub_int32_sat'); +gettext('32 bits signed integer subtract with minint,maxint saturation'); +gettext('div_int48_24'); +gettext('mul_int8_16'); +gettext('8 bit inputs signed integer multiplier, 16 bits output'); +gettext('div_uint16'); +gettext('16 bits unsigned divider'); +gettext('sqrt_uint16'); +gettext('16 bits unsigned integer square root'); +gettext('div_uint24'); +gettext('24 bits unsigned divider'); +gettext('sqrt_uint24'); +gettext('24 bits unsigned integer square root'); +gettext('div_uint32'); +gettext('32 bits unsigned divider'); +gettext('sqrt_uint32'); +gettext('32 bits unsigned integer square root'); +gettext('timer_16bits'); +gettext('measure time by counting clk periods between start and stop pulse'); +gettext('test_serial_muldiv_int16'); +gettext('Registro de 16 bits'); +gettext('Puerta NOT'); +gettext('Transmisor serie (hecho a partir de bloques)'); +gettext('Biestable de datos (Tipo D). Cuando se recibe un tic por load se captura el dato'); +gettext('Un bit constante a 1'); +gettext('Biestable con entradas de Set y Reset síncronas, para poner y quitar notaficaciones de eventos'); +gettext('Contador módulo M, ascendente, de 4 bits, con reset '); +gettext('Un simple cable pasivo, para organizar las conexiones complicadas'); +gettext('Corazón de tics para generar las velocidades de transmisión serie en baudios (Por defecto emite tics a 11500 baudios)'); +gettext('Registro de desplazamiento (derecha) de 9 bits'); +gettext('Agregador de buses de 8 y 2 bits a uno de 9bits'); +gettext('Un bit constante a 0'); +gettext('Detector de flanco de subida. Emite un tic cuando detecta un flanco ascendente'); +gettext('Convierte números (0..65535) introducidos desde el serial a binario de 16 bits.'); +gettext('Receptor serie asíncrono. Velocidad por defecto: 115200 baudios'); +gettext('Char detect & LF, CR, space & comma.'); +gettext('Comparador de un operando de 8 bits. Se compara si el operando es igual al parámetro'); +gettext('Puerta AND'); +gettext('Puerta OR de 4 entradas'); +gettext('Convierte un número ASCII a binario de 16 bits.'); +gettext('Registro doble de 16 bits, con entrada normal y el reset vale el ASCII 48 ----->'0'.'); +gettext('Registro de 8 bits ASCII'); +gettext('16 bits signed integer multiply divide with output saturation, 32 bits internal'); +gettext('Biestable De del sistema que hay que \nañadir para cumplir las reglas de diseño \nsíncrono: toda señal sacada al exterior, \nespecialmente si es un cable de comunicaciones \nasíncronas, debe pasar por un biestable'); +gettext('Este Biestable desde \nestar inicialmente \na 1, ya que es el \nvalor de reposo de la \nlínea serie'); +gettext('**Registro de**\n**Desplazamiento**'); +gettext('Conversión de los datos serie a \nparalelo, mediante un registro \nde 9 bits. Inicialmente tiene todos \nsus bits a 1, porque la línea está \nen reposo'); +gettext('**Biestable D**'); +gettext('Evento: Comienzo de \ntransmisión'); +gettext('Cargar el registro con \nel dato a enviar en el \narranque (0 -> 1)'); +gettext('**Biestable RS** \nEstado del transmisor'); +gettext('0: Parado. Sin transmitir \n1: Ocupado. Transmitiendo dato'); +gettext('**Generador de**\n**Baudios**'); +gettext('Contador de bits \ntransmitidos'); +gettext('El registro de desplazamiento \nes de 9 bits, para almacenar \nlos 8 bits de datos y \nel bit de comienzo (start)'); +gettext('Evento: Ultimo \nbit enviado'); +gettext('Al enviarse el último \nbit, se cambia el estado \na parado (reset)'); +gettext('**Cable pasivo** \nPara organizar el \ncableado del reloj'); +gettext('**Dato a transmitir**'); +gettext('**Bit de Stop**'); +gettext('**Bit de start**'); +gettext('**Tic de transmisión** \n¡Que comience la \ntransmisión!'); +gettext('**Línea serie**'); +gettext('**Tic de terminación (done)**'); +gettext('**Reloj del sistema**'); +gettext('**BAUDIOS**\n'); +gettext('El tic de terminación está un \nperiodo de reloj retrasado para \nque el transmisor pase al estado \nParado, y que todo se reinicie \nantes de que se pueda volve a \nenviar el siguiente caracter'); +gettext('El estado del transmisor \nse saca por la señal \nbusy'); +gettext('Arrancar el generar de baudios \nal activarse el transmisor'); +gettext('**Parámetro**: Módulo del contador'); +gettext('Estos registros de 8 bits con reset son especiales. Cuando recibe un reset no se pone a 0, sino a 48, que es el '0' ASCII.'); +gettext('Estos registros se inician con el valor 48 ('0' en ASCII).'); +gettext('Convierte el valor ASCII a binario.'); +gettext('Cuando recibe LF o CR produce un pulso en \"rst\" para el resto de caracteres da un pulso por \"tic\".'); +gettext('test_serial_sqrt_uint16'); diff --git a/muldiv_int16.ice b/muldiv_int16.ice deleted file mode 100644 index 7d7c70f..0000000 --- a/muldiv_int16.ice +++ /dev/null @@ -1,1007 +0,0 @@ -{ - "version": "1.2", - "package": { - "name": "muldiv_int16", - "version": "1.0", - "description": "16 bits signed integer multiply divide with output saturation, 32 bits internal", - "author": "Sicco Dwars", - "image": "%3Csvg%20width=%22800%22%20height=%22600%22%20xmlns=%22http://www.w3.org/2000/svg%22%3E%3Ctitle%3ELayer%201%3C/title%3E%3Ctext%20transform=%22matrix(6.12846%200%200%2014.5988%20-734.172%20-2177.67)%22%20stroke=%22#000%22%20font-family=%22sans-serif%22%20font-size=%2224%22%20y=%22173.671%22%20x=%22138.638%22%20stroke-width=%220%22%20fill=%22#46673D%22%3EMULDIV%3C/text%3E%3Ctext%20transform=%22matrix(6.02479%200%200%203.13937%20-2371.17%20-955.151)%22%20stroke=%22#000%22%20font-family=%22sans-serif%22%20font-size=%2224%22%20y=%22473.289%22%20x=%22407.223%22%20stroke-width=%220%22%3Eint_16_sat%3C/text%3E%3C/svg%3E" - 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"data": { - "name": "y", - "range": "[31:0]", - "size": 32 - }, - "position": { - "x": 1632, - "y": 680 - } - }, - { - "id": "8d4a8181-ec5c-4309-948f-ae351261da55", - "type": "basic.input", - "data": { - "name": "b", - "range": "[15:0]", - "clock": false, - "size": 16 - }, - "position": { - "x": 296, - "y": 712 - } - }, - { - "id": "396814a2-9764-4311-96f8-10d766e29af3", - "type": "basic.code", - "data": { - "code": "// y = a * b, signed integers\r\n\r\nlocalparam N = 16;\r\n\r\nreg [(N+N-1):0] y = 0;\r\nreg out_valid;\r\nreg ready = 1;\r\nreg pulse_done = 0;\r\nreg busy = 0;\r\n\r\nreg [N-1:0] A;\r\nreg [N-1:0] B;\r\nreg [$clog2(N+1)-1:0] state = 0;\r\nreg [N-1:0] work; \r\nreg [N-2:0] resultLsb;\r\n\r\nwire [N-1:0] pp = {N{A[0]}} & B;\r\nwire [N-1:0] pMod1 = {~pp[N-1], pp[N-2:0]};\r\nwire [N-1:0] pMod2 = ~pMod1;\r\nwire [N:0] sum12 = work + ((state == N) ? pMod2 : pMod1);\r\nwire [N:0] sum1 = sum12;\r\nwire [N:0] sum2 = sum12;\r\n \r\nreg prev_start = 0; \r\n \r\nalways @(posedge clk) \r\nbegin\r\n out_valid <= 0;\r\n A <= {1'bx, A[N-1:1]}; \r\n case (state)\r\n\t 0:\r\n\t begin \r\n\t pulse_done <= 0;\r\n\t busy <= 0;\r\n\t end\r\n\t 1: begin\r\n\t work <= {1'b1, pMod1[N-1:1]};\r\n\t resultLsb <= {pMod1[0], {N-2{1'bx}}};\r\n\t state <= state + 1;\r\n\t end\r\n\t default: \r\n\t begin\r\n\t work <= sum1[N:1];\r\n\t resultLsb <= {sum1[0], resultLsb[N-2:1]};\t \r\n\t state <= state + 1;\r\n\t end\r\n\t N: \r\n\t begin\r\n\t y <= {~sum2[N], sum2[N-1:0], resultLsb};\r\n\t out_valid <= 1;\r\n\t pulse_done <= 1;\r\n\t work <= 'bx;\r\n\t state <= 0;\r\n\t resultLsb <= 'bx;\r\n\t B <= 'bx;\r\n\t ready <= 1;\t \r\n\t end\r\n endcase\r\n \r\n if (start && !prev_start) \r\n begin\r\n\t A <= a;\r\n\t B <= b;\r\n\t state <= 1;\r\n\t ready <= 0;\r\n\t busy <= 1;\r\n end\r\n \r\n prev_start <= start;\r\nend", - "params": [], - "ports": { - "in": [ - { - "name": "clk" - }, - { - "name": "start" - }, - { - "name": "a", - "range": "[15:0]", - "size": 16 - }, - { - "name": "b", - "range": "[15:0]", - "size": 16 - } - ], - "out": [ - { - "name": "pulse_done" - }, - { - "name": "busy" - }, - { - "name": "y", - "range": "[31:0]", - "size": 32 - } - ] - } - }, - "position": { - "x": 488, - "y": 104 - }, - "size": { - "width": 1032, - "height": 728 - } - } - ], - "wires": [ - { - "source": { - "block": "008bc8ae-2c14-480d-ad2a-b595e21d6980", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "start" - } - }, - { - "source": { - "block": "c52eb53f-45ba-4dc2-a1ed-3471922053c3", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "clk" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "busy" - }, - "target": { - "block": "77545349-454a-4d5f-82e6-a8b1f6261f26", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "pulse_done" - }, - "target": { - "block": "b594bd8c-4263-4b91-9aa3-591541041457", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "y" - }, - "target": { - "block": "5b4ccfd9-6cb9-4e4a-92b9-540ff20533ff", - "port": "in" - }, - "size": 32 - }, - { - "source": { - "block": "9ec9e347-b88c-48f5-86e0-606495e1ce43", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "a" - }, - "size": 16 - }, - { - "source": { - "block": "8d4a8181-ec5c-4309-948f-ae351261da55", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "b" - }, - "size": 16 - } - ] - } - } - }, - "53e376e76eb0fbf461402cb00907f2bec8d9ff24": { - "package": { - "name": "div_int32_16", - "version": "1.0", - "description": "32 bits signed integer division, divide 32 bits numerator by a 16 bits int denominator, result in 16 bits int", - "author": "", - "image": "%3Csvg%20width=%22800%22%20height=%22600%22%20xmlns=%22http://www.w3.org/2000/svg%22%3E%3Ctitle%3ELayer%201%3C/title%3E%3Ctext%20transform=%22matrix(11.6228%200%200%2013.7183%20-1447.34%20-2037.34)%22%20stroke=%22#000%22%20font-family=%22sans-serif%22%20font-size=%2224%22%20y=%22173.397%22%20x=%22135.701%22%20stroke-width=%220%22%20fill=%22#46673D%22%20cursor=%22move%22%3EDIV%3C/text%3E%3Ctext%20transform=%22matrix(6.40974%200%200%205.3641%20-2559.75%20-1996.65)%22%20stroke=%22#000%22%20font-family=%22sans-serif%22%20font-size=%2224%22%20y=%22472.357%22%20x=%22410.655%22%20stroke-width=%220%22%20cursor=%22move%22%3Eint_32_16%3C/text%3E%3C/svg%3E" - }, - "design": { - "graph": { - "blocks": [ - { - "id": "b594bd8c-4263-4b91-9aa3-591541041457", - "type": "basic.output", - "data": { - "name": "done", - "virtual": true - }, - "position": { - "x": 1608, - "y": 136 - } - }, - { - "id": "c52eb53f-45ba-4dc2-a1ed-3471922053c3", - "type": "basic.input", - "data": { - "name": "clk", - "clock": false, - "virtual": true - }, - "position": { - "x": 304, - "y": 160 - } - }, - { - "id": "77545349-454a-4d5f-82e6-a8b1f6261f26", - "type": "basic.output", - "data": { - "name": "busy", - "virtual": true - }, - "position": { - "x": 1592, - "y": 256 - } - }, - { - "id": "008bc8ae-2c14-480d-ad2a-b595e21d6980", - "type": "basic.input", - "data": { - "name": "start", - "clock": false, - "virtual": true - }, - "position": { - "x": 296, - "y": 344 - } - }, - { - "id": "fb0d9a68-cf3f-4768-b540-483468429470", - "type": "basic.output", - "data": { - "name": "valid", - "virtual": true - }, - "position": { - "x": 1592, - "y": 376 - } - }, - { - "id": "2cf01ed6-9923-4eee-9fd0-1c9c9ca24346", - "type": "basic.output", - "data": { - "name": "dbz", - "virtual": true - }, - "position": { - "x": 1592, - "y": 496 - } - }, - { - "id": "de4d0ace-40c4-481b-b5f6-7a5fa629ee32", - "type": "basic.input", - "data": { - "name": "x", - "range": "[31:0]", - "clock": false, - "size": 32, - "virtual": true - }, - "position": { - "x": 296, - "y": 528 - } - }, - { - "id": "f82803bd-2218-4b79-bc5d-0b5fa6f00b59", - "type": "basic.output", - "data": { - "name": "q", - "range": "[15:0]", - "size": 16, - "virtual": true - }, - "position": { - "x": 1608, - "y": 616 - } - }, - { - "id": "4ed0fc5b-2081-4c05-98e5-5262bcb776e5", - "type": "basic.input", - "data": { - "name": "y", - "range": "[15:0]", - "clock": false, - "size": 16, - "virtual": true - }, - "position": { - "x": 296, - "y": 712 - } - }, - { - "id": "7d453a81-da0e-43df-be6e-ea315ff5a89b", - "type": "basic.output", - "data": { - "name": "r", - "range": "[31:0]", - "size": 32, - "virtual": true - }, - "position": { - "x": 1608, - "y": 736 - } - }, - { - "id": "396814a2-9764-4311-96f8-10d766e29af3", - "type": "basic.code", - "data": { - "code": "// q = a / b signed ints, a is 32 bits, b is 16 bits, q is 16 bits and coerced to [MININT..MAXINT]\r\n\r\nlocalparam N = 32;\r\nlocalparam NH = N >> 1;\r\nlocalparam NH_M1 = NH - 1;\r\n\r\nwire [N-1:0] xw;\r\nwire [N-1:0] yN;\r\n\r\nwire [N-1:0] yw;\r\n\r\nreg [N-1:0] y1;\r\nreg [N-1:0] q1;\r\nreg [N-1:0] q1_next;\r\nreg [N:0] ac;\r\nreg [N:0] ac_next;\r\nreg [$clog2(N)-1:0] i;\r\n\r\nreg pulse_done = 0;\r\nreg busy = 0;\r\nreg valid = 0;\r\nreg dbz = 0;\r\nreg signed [NH-1:0] q = 0;\r\nreg signed [N-1:0] r = 0;\r\nreg qs;\r\nreg xs;\r\n\r\nreg prev_start = 0;\r\n\r\nwire [N:0] ac_nextw;\r\n\r\nassign ac_nextw = ac - y1;\r\n\r\nassign xw = (a[N-1]) ? (~a + 1) : a;\r\nassign yN = b[NH_M1] ? {{NH{1'b1}}, b} : {{NH{1'b0}}, b};\r\nassign yw = yN[N-1] ? (~yN + 1) : yN;\r\n\r\nwire y_less_than_MININT;\r\nwire y_more_than_MAXINT;\r\n\r\nwire signed [NH_M1:0] MININT = {1'b1,{NH_M1{1'b0}}};\r\nwire signed [NH_M1:0] MAXINT = {1'b0,{NH_M1{1'b1}}};\r\n\r\nassign y_less_than_MININT = y[N-1] && (y[N-2:NH-1] != {NH{1'b1}});\r\nassign y_more_than_MAXINT = !y[N-1] && (y[N-2:NH-1] != {NH{1'b0}});\r\n\r\nwire signed [N-1:0] y = qs ? (~q1_next + 1) : q1_next;\r\nwire [NH-1:0] y_coerced = y_less_than_MININT ? MININT : y_more_than_MAXINT ? MAXINT : y[N-1:0];\r\n\r\nalways @(negedge clk) \r\nbegin\r\n if (ac >= {1'b0,y1}) \r\n {ac_next, q1_next} <= {ac_nextw[N-1:0], q1, 1'b1};\r\n else \r\n {ac_next, q1_next} <= {ac, q1} << 1;\r\nend\r\n\r\nalways @(posedge clk) \r\nbegin\r\n prev_start <= start;\r\n if (start && !prev_start) \r\n begin\r\n valid <= 0;\r\n i <= 0;\r\n if (b == 0) // divide by 0? \r\n begin\r\n if (a == 0)\r\n q <= 0;\r\n else\r\n q <= {NH{1'b1}};\r\n r <= 0;\r\n pulse_done <= 1;\r\n busy <= 0;\r\n dbz <= 1;\r\n end \r\n else \r\n begin\r\n busy <= 1;\r\n dbz <= 0;\r\n y1 <= yw;\r\n {ac, q1} <= {{N{1'b0}}, xw, 1'b0};\r\n qs <= a[N-1] ^ b[NH_M1];\r\n xs <= a[N-1];\r\n end\r\n end \r\n else \r\n if (busy) \r\n begin\r\n if (i == N-1) \r\n begin\r\n busy <= 0;\r\n valid <= 1;\r\n \r\n q <= y_coerced;\r\n\r\n if (xs)\r\n r <= ~ac_next[N:1] + 1;\r\n else\r\n r <= ac_next[N:1];\r\n pulse_done <= 1;\r\n end \r\n else \r\n begin\r\n i <= i + 1;\r\n ac <= ac_next;\r\n q1 <= q1_next;\r\n end\r\n end\r\n else\r\n begin\r\n pulse_done <= 0;\r\n end\r\nend\r\n", - "params": [], - "ports": { - "in": [ - { - "name": "clk" - }, - { - "name": "start" - }, - { - "name": "a", - "range": "[31:0]", - "size": 32 - }, - { - "name": "b", - "range": "[15:0]", - "size": 16 - } - ], - "out": [ - { - "name": "pulse_done" - }, - { - "name": "busy" - }, - { - "name": "valid" - }, - { - "name": "dbz" - }, - { - "name": "q", - "range": "[15:0]", - "size": 16 - }, - { - "name": "r", - "range": "[31:0]", - "size": 32 - } - ] - } - }, - "position": { - "x": 488, - "y": 104 - }, - "size": { - "width": 1032, - "height": 728 - } - } - ], - "wires": [ - { - "source": { - "block": "008bc8ae-2c14-480d-ad2a-b595e21d6980", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "start" - } - }, - { - "source": { - "block": "c52eb53f-45ba-4dc2-a1ed-3471922053c3", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "clk" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "busy" - }, - "target": { - "block": "77545349-454a-4d5f-82e6-a8b1f6261f26", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "valid" - }, - "target": { - "block": "fb0d9a68-cf3f-4768-b540-483468429470", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "dbz" - }, - "target": { - "block": "2cf01ed6-9923-4eee-9fd0-1c9c9ca24346", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "pulse_done" - }, - "target": { - "block": "b594bd8c-4263-4b91-9aa3-591541041457", - "port": "in" - } - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "r" - }, - "target": { - "block": "7d453a81-da0e-43df-be6e-ea315ff5a89b", - "port": "in" - }, - "size": 32 - }, - { - "source": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "q" - }, - "target": { - "block": "f82803bd-2218-4b79-bc5d-0b5fa6f00b59", - "port": "in" - }, - "size": 16 - }, - { - "source": { - "block": "de4d0ace-40c4-481b-b5f6-7a5fa629ee32", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "a" - }, - "size": 32 - }, - { - "source": { - "block": "4ed0fc5b-2081-4c05-98e5-5262bcb776e5", - "port": "out" - }, - "target": { - "block": "396814a2-9764-4311-96f8-10d766e29af3", - "port": "b" - }, - "size": 16 - } - ] - } - } - } - } -} \ No newline at end of file diff --git a/package.json b/package.json new file mode 100644 index 0000000..95ec9a6 --- /dev/null +++ b/package.json @@ -0,0 +1,17 @@ +{ + "name": "arithmetic", + "version": "0.1.0", + "description": "Signed arithmetic collections", + "keywords": ["integer", "signed", "arithmetic"], + "license": "LGPL-3.0", + "authors": [{ + "name": "SiccoDwars", + "email": "", + "url": "https://github.com/SiccoDwars" + }], + "repository": { + "type": "git", + "branch": "main", + "url": "https://github.com/SiccoDwars/Icestudio-ArithmeticBlocks" + } +}